From 380559c1c3ac80c0d2581a931c80323d1fefbfd6 Mon Sep 17 00:00:00 2001
From: Dimitris Papastamos <dimitris.papastamos@arm.com>
Date: Thu, 12 Oct 2017 13:02:29 +0100
Subject: AMU: Implement support for aarch64

The `ENABLE_AMU` build option can be used to enable the
architecturally defined AMU counters.  At present, there is no support
for the auxiliary counter group.

Change-Id: I7ea0c0a00327f463199d1b0a481f01dadb09d312
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
---
 lib/el3_runtime/aarch64/context_mgmt.c |  5 +++++
 lib/extensions/amu/aarch64/amu.c       | 40 ++++++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)
 create mode 100644 lib/extensions/amu/aarch64/amu.c

(limited to 'lib')

diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 8f1523f0d..b892729ef 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <amu.h>
 #include <arch.h>
 #include <arch_helpers.h>
 #include <assert.h>
@@ -220,6 +221,10 @@ static void enable_extensions_nonsecure(int el2_unused)
 #if ENABLE_SPE_FOR_LOWER_ELS
 	spe_enable(el2_unused);
 #endif
+
+#if ENABLE_AMU
+	amu_enable(el2_unused);
+#endif
 #endif
 }
 
diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c
new file mode 100644
index 000000000..007b3494f
--- /dev/null
+++ b/lib/extensions/amu/aarch64/amu.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <amu.h>
+#include <arch.h>
+#include <arch_helpers.h>
+
+void amu_enable(int el2_unused)
+{
+	uint64_t features;
+
+	features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT;
+	if ((features & ID_AA64PFR0_AMU_MASK) == 1) {
+		uint64_t v;
+
+		if (el2_unused) {
+			/*
+			 * CPTR_EL2.TAM: Set to zero so any accesses to
+			 * the Activity Monitor registers do not trap to EL2.
+			 */
+			v = read_cptr_el2();
+			v &= ~CPTR_EL2_TAM_BIT;
+			write_cptr_el2(v);
+		}
+
+		/*
+		 * CPTR_EL3.TAM: Set to zero so that any accesses to
+		 * the Activity Monitor registers do not trap to EL3.
+		 */
+		v = read_cptr_el3();
+		v &= ~TAM_BIT;
+		write_cptr_el3(v);
+
+		/* Enable group 0 counters */
+		write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);
+	}
+}
-- 
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