From a10d3632acbd1135648f07c2a998cba8c5c77cfd Mon Sep 17 00:00:00 2001 From: Jeenu Viswambharan Date: Fri, 6 Jan 2017 14:58:11 +0000 Subject: PSCI: Introduce cache and barrier wrappers The PSCI implementation performs cache maintenance operations on its data structures to ensure their visibility to both cache-coherent and non-cache-coherent participants. These cache maintenance operations can be skipped if all PSCI participants are cache-coherent. When HW_ASSISTED_COHERENCY build option is enabled, we assume PSCI participants are cache-coherent. For usage abstraction, this patch introduces wrappers for PSCI cache maintenance and barrier operations used for state coordination: they are effectively NOPs when HW_ASSISTED_COHERENCY is enabled, but are applied otherwise. Also refactor local state usage and associated cache operations to make it clearer. Change-Id: I77f17a90cba41085b7188c1345fe5731c99fad87 Signed-off-by: Jeenu Viswambharan --- lib/psci/psci_suspend.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'lib/psci/psci_suspend.c') diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c index 302116bd4..23e5adab3 100644 --- a/lib/psci/psci_suspend.c +++ b/lib/psci/psci_suspend.c @@ -91,10 +91,10 @@ static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl, psci_set_suspend_pwrlvl(end_pwrlvl); /* - * Flush the target power level as it will be accessed on power up with + * Flush the target power level as it might be accessed on power up with * Data cache disabled. */ - flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); + psci_flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); /* * Call the cpu suspend handler registered by the Secure Payload -- cgit v1.2.3