From fd4bb0ad4b2403156c62dea2ae7c1e02c19e79bf Mon Sep 17 00:00:00 2001 From: John Tsichritzis Date: Tue, 19 Feb 2019 13:54:21 +0000 Subject: Rename Cortex-Helios filenames to Neoverse E1 Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3 Signed-off-by: John Tsichritzis --- include/lib/cpus/aarch64/cortex_helios.h | 31 ------------------------------- include/lib/cpus/aarch64/neoverse_e1.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 31 deletions(-) delete mode 100644 include/lib/cpus/aarch64/cortex_helios.h create mode 100644 include/lib/cpus/aarch64/neoverse_e1.h (limited to 'include') diff --git a/include/lib/cpus/aarch64/cortex_helios.h b/include/lib/cpus/aarch64/cortex_helios.h deleted file mode 100644 index 0c11a9a4c..000000000 --- a/include/lib/cpus/aarch64/cortex_helios.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_HELIOS_H -#define CORTEX_HELIOS_H - -#include - -#define CORTEX_HELIOS_MIDR U(0x410FD060) - -/******************************************************************************* - * CPU Extended Control register specific definitions. - ******************************************************************************/ -#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 - -/******************************************************************************* - * CPU Auxiliary Control register specific definitions. - ******************************************************************************/ -#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 - -/******************************************************************************* - * CPU Power Control register specific definitions. - ******************************************************************************/ - -#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) - -#endif /* CORTEX_HELIOS_H */ diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h new file mode 100644 index 000000000..0c11a9a4c --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_e1.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_HELIOS_H +#define CORTEX_HELIOS_H + +#include + +#define CORTEX_HELIOS_MIDR U(0x410FD060) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ + +#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_HELIOS_H */ -- cgit v1.2.3