From b04ea14b790b7899e73c34f6c678d90efdb9f9fc Mon Sep 17 00:00:00 2001 From: John Tsichritzis Date: Tue, 19 Feb 2019 13:48:44 +0000 Subject: Rename Cortex-Ares filenames to Neoverse N1 Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896 Signed-off-by: John Tsichritzis --- include/lib/cpus/aarch64/cortex_ares.h | 35 ---------------------------------- include/lib/cpus/aarch64/neoverse_n1.h | 35 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 35 deletions(-) delete mode 100644 include/lib/cpus/aarch64/cortex_ares.h create mode 100644 include/lib/cpus/aarch64/neoverse_n1.h (limited to 'include') diff --git a/include/lib/cpus/aarch64/cortex_ares.h b/include/lib/cpus/aarch64/cortex_ares.h deleted file mode 100644 index cfc36e473..000000000 --- a/include/lib/cpus/aarch64/cortex_ares.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_ARES_H -#define CORTEX_ARES_H - -#include - -/* Cortex-ARES MIDR for revision 0 */ -#define CORTEX_ARES_MIDR U(0x410fd0c0) - -/******************************************************************************* - * CPU Extended Control register specific definitions. - ******************************************************************************/ -#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 - -/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ -#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1) - -#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) - -#define CORTEX_ARES_AMU_NR_COUNTERS U(5) -#define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f) - -/* Instruction patching registers */ -#define CPUPSELR_EL3 S3_6_C15_C8_0 -#define CPUPCR_EL3 S3_6_C15_C8_1 -#define CPUPOR_EL3 S3_6_C15_C8_2 -#define CPUPMR_EL3 S3_6_C15_C8_3 - -#endif /* CORTEX_ARES_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h new file mode 100644 index 000000000..cfc36e473 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_ARES_H +#define CORTEX_ARES_H + +#include + +/* Cortex-ARES MIDR for revision 0 */ +#define CORTEX_ARES_MIDR U(0x410fd0c0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ +#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1) + +#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) + +#define CORTEX_ARES_AMU_NR_COUNTERS U(5) +#define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f) + +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* CORTEX_ARES_H */ -- cgit v1.2.3