From 5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8 Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Wed, 20 Feb 2019 12:11:41 +0000 Subject: Add workaround for errata 764081 of Cortex-A75 Implicit Error Synchronization Barrier (IESB) might not be correctly generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all expection levels. Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad Signed-off-by: Louis Mayencourt --- include/arch/aarch64/arch.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 76c3e277b..45aa0778d 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -255,6 +255,7 @@ #define SCTLR_NTWE_BIT (ULL(1) << 18) #define SCTLR_WXN_BIT (ULL(1) << 19) #define SCTLR_UWXN_BIT (ULL(1) << 20) +#define SCTLR_IESB_BIT (ULL(1) << 21) #define SCTLR_E0E_BIT (ULL(1) << 24) #define SCTLR_EE_BIT (ULL(1) << 25) #define SCTLR_UCI_BIT (ULL(1) << 26) -- cgit v1.2.3