From 5c6aa01affe14c40efdebdc9450cdbc4ae0bc494 Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Mon, 25 Feb 2019 15:17:44 +0000 Subject: Add workaround for errata 1073348 for Cortex-A76 Concurrent instruction TLB miss and mispredicted return instruction might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to prevent this. Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58 Signed-off-by: Louis Mayencourt --- include/lib/cpus/aarch64/cortex_a76.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index 52ab92ef6..c2af8cad9 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -23,6 +23,10 @@ /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ +#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) + #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) -- cgit v1.2.3