From cba71b70ef7070bcd38a8d202f30e58f79e36c6b Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Fri, 5 Apr 2019 16:25:25 +0100 Subject: Cortex-A35: Implement workaround for errata 855472 Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt --- include/lib/cpus/aarch64/cortex_a35.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/lib') diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h index 067880491..5421478d2 100644 --- a/include/lib/cpus/aarch64/cortex_a35.h +++ b/include/lib/cpus/aarch64/cortex_a35.h @@ -19,4 +19,11 @@ #define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1 #define CORTEX_A35_CPUECTLR_SMPEN_BIT (ULL(1) << 6) +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A35_CPUACTLR_EL1 S3_1_C15_C2_0 + +#define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI (ULL(1) << 44) + #endif /* CORTEX_A35_H */ -- cgit v1.2.3