From 08826b6cf8a052fc68685a47f352dc95e95c6304 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Sun, 8 Dec 2019 08:12:52 +0100 Subject: dts: bindings: stm32mp1: define SCMI clock and reset domain IDs Define the platform SCMI clocks and reset domains for stm32mp1 family. SCMI agent 0 accesses clock/reset controllers under RCC TZEN hardening. SCMI agent 1 accesses clock controllers under RCC MCKPROT hardening. Change-Id: I52e906f846d445a3e6850e5f2e1584da14692553 Signed-off-by: Etienne Carriere --- include/dt-bindings/clock/stm32mp1-clks.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'include/dt-bindings/clock/stm32mp1-clks.h') diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 18bdb57f3..67e66b23f 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,4 +248,31 @@ #define STM32MP1_LAST_CLK 232 +/* SCMI clock identifiers */ +#define CK_SCMI0_HSE 0 +#define CK_SCMI0_HSI 1 +#define CK_SCMI0_CSI 2 +#define CK_SCMI0_LSE 3 +#define CK_SCMI0_LSI 4 +#define CK_SCMI0_PLL2_Q 5 +#define CK_SCMI0_PLL2_R 6 +#define CK_SCMI0_MPU 7 +#define CK_SCMI0_AXI 8 +#define CK_SCMI0_BSEC 9 +#define CK_SCMI0_CRYP1 10 +#define CK_SCMI0_GPIOZ 11 +#define CK_SCMI0_HASH1 12 +#define CK_SCMI0_I2C4 13 +#define CK_SCMI0_I2C6 14 +#define CK_SCMI0_IWDG1 15 +#define CK_SCMI0_RNG1 16 +#define CK_SCMI0_RTC 17 +#define CK_SCMI0_RTCAPB 18 +#define CK_SCMI0_SPI6 19 +#define CK_SCMI0_USART1 20 + +#define CK_SCMI1_PLL3_Q 0 +#define CK_SCMI1_PLL3_R 1 +#define CK_SCMI1_MCU 2 + #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ -- cgit v1.2.3