From 5c6aa01affe14c40efdebdc9450cdbc4ae0bc494 Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Mon, 25 Feb 2019 15:17:44 +0000 Subject: Add workaround for errata 1073348 for Cortex-A76 Concurrent instruction TLB miss and mispredicted return instruction might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to prevent this. Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58 Signed-off-by: Louis Mayencourt --- docs/cpu-specific-build-macros.rst | 3 +++ 1 file changed, 3 insertions(+) (limited to 'docs') diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index bbfc86339..1f23b5bf6 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -147,6 +147,9 @@ For Cortex-A75, the following errata build flags are defined : For Cortex-A76, the following errata build flags are defined : +- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r1p0 of the CPU. + - ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. -- cgit v1.2.3