From 076b5f02e2747ef1b5a55f1c5d368df16f046b1c Mon Sep 17 00:00:00 2001 From: John Tsichritzis Date: Tue, 19 Mar 2019 17:20:52 +0000 Subject: Add compile-time errors for HW_ASSISTED_COHERENCY flag This patch fixes this issue: https://github.com/ARM-software/tf-issues/issues/660 The introduced changes are the following: 1) Some cores implement cache coherency maintenance operation on the hardware level. For those cores, such as - but not only - the DynamIQ cores, it is mandatory that TF-A is compiled with the HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is unpredictable. To prevent this, compile time checks have been added and compilation errors are generated, if needed. 2) To enable this change for FVP, a logical separation has been done for the core libraries. A system cannot contain cores of both groups, i.e. cores that manage coherency on hardware and cores that don't do it. As such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the libraries only of the relevant cores. 3) The neoverse_e1.S file has been added to the FVP sources. Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3 Signed-off-by: John Tsichritzis --- docs/user-guide.rst | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) (limited to 'docs') diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 01cf17a23..ce12f0835 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -530,13 +530,21 @@ Common build options - ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific software operations are required for CPUs to enter and exit coherency. - However, there exists newer systems where CPUs' entry to and exit from - coherency is managed in hardware. Such systems require software to only - initiate the operations, and the rest is managed in hardware, minimizing - active software management. In such systems, this boolean option enables - TF-A to carry out build and run-time optimizations during boot and power - management operations. This option defaults to 0 and if it is enabled, - then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. + However, newer systems exist where CPUs' entry to and exit from coherency + is managed in hardware. Such systems require software to only initiate these + operations, and the rest is managed in hardware, minimizing active software + management. In such systems, this boolean option enables TF-A to carry out + build and run-time optimizations during boot and power management operations. + This option defaults to 0 and if it is enabled, then it implies + ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. + + If this flag is disabled while the platform which TF-A is compiled for + includes cores that manage coherency in hardware, then a compilation error is + generated. This is based on the fact that a system cannot have, at the same + time, cores that manage coherency in hardware and cores that don't. In other + words, a platform cannot have, at the same time, cores that require + ``HW_ASSISTED_COHERENCY=1`` and cores that require + ``HW_ASSISTED_COHERENCY=0``. Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of translation library (xlat tables v2) must be used; version 1 of translation -- cgit v1.2.3