From afd241e71d76470478039388a358d0176491734f Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Fri, 24 Jan 2020 16:20:15 +0100 Subject: amlogic: axg: Add support for the A113D (AXG) platform Introduce the preliminary support for the Amlogic A113D (AXG) SoC. This port is a minimal implementation of BL31 capable of booting mainline U-Boot, Linux and chainloading BL32 (ATOS). Tested on a A113D board. Signed-off-by: Carlo Caione Change-Id: Ic4548fa2f7c48d61b485b2a6517ec36c53c20809 --- docs/plat/meson-axg.rst | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 docs/plat/meson-axg.rst (limited to 'docs/plat') diff --git a/docs/plat/meson-axg.rst b/docs/plat/meson-axg.rst new file mode 100644 index 000000000..8a623bd37 --- /dev/null +++ b/docs/plat/meson-axg.rst @@ -0,0 +1,26 @@ +Amlogic Meson A113D (AXG) +=========================== + +The Amlogic Meson A113D is a SoC with a quad core Arm Cortex-A53 running at +~1.2GHz. It also contains a Cortex-M3 used as SCP. + +This port is a minimal implementation of BL31 capable of booting mainline U-Boot +and Linux: + +- SCPI support. +- Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0 + can't be turned off, so there is a workaround to hide this from the caller. +- GICv2 driver set up. +- Basic SIP services (read efuse data, enable/disable JTAG). + +In order to build it: + +.. code:: shell + + CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=axg [SPD=opteed] + +This port has been tested on a A113D board. After building it, follow the +instructions in the `U-Boot repository`_, replacing the mentioned **bl31.img** +by the one built from this port. + +.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/board/amlogic/s400/README -- cgit v1.2.3 From 72d2535afde2df0d9edd851dad425d8fabf6d449 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 27 Jan 2020 16:03:28 +0100 Subject: amlogic: axg: Add a build flag when using ATOS as BL32 BL2 is unconditionally setting 0 (OPTEE_AARCH64) in arg0 even when the BL32 image is 32bit (OPTEE_AARCH32). This is causing the boot to hang when ATOS (32bit Amlogic BL32 binary-only TEE OS) is used. Since we are not aware of any Amlogic platform shipping a 64bit version of ATOS we can hardcode OPTEE_AARCH32 / MODE_RW_32 when using ATOS. Signed-off-by: Carlo Caione Change-Id: Iaea47cf6dc48bf8a646056761f02fb81b41c78a3 --- docs/plat/meson-axg.rst | 1 + 1 file changed, 1 insertion(+) (limited to 'docs/plat') diff --git a/docs/plat/meson-axg.rst b/docs/plat/meson-axg.rst index 8a623bd37..1e4b2c207 100644 --- a/docs/plat/meson-axg.rst +++ b/docs/plat/meson-axg.rst @@ -18,6 +18,7 @@ In order to build it: .. code:: shell CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=axg [SPD=opteed] + [AML_USE_ATOS=1 when using ATOS as BL32] This port has been tested on a A113D board. After building it, follow the instructions in the `U-Boot repository`_, replacing the mentioned **bl31.img** -- cgit v1.2.3 From a6ffddec33be0f10382f0f66eacafb03492c8141 Mon Sep 17 00:00:00 2001 From: Max Shvetsov Date: Fri, 6 Dec 2019 11:50:12 +0000 Subject: Adds option to read ROTPK from registers for FVP Enables usage of ARM_ROTPK_LOCATION=regs for FVP board. Removes hard-coded developer keys. Instead, setting ARM_ROTPK_LOCATION=devel_* takes keys from default directory. In case of ROT_KEY specified - generates a new hash and replaces the original. Note: Juno board was tested by original feature author and was not tested for this patch since we don't have access to the private key. Juno implementation was moved to board-specific file without changing functionality. It is not known whether byte-swapping is still needed for this platform. Change-Id: I0fdbaca0415cdcd78f3a388551c2e478c01ed986 Signed-off-by: Max Shvetsov --- docs/plat/arm/arm-build-options.rst | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst index d24ad231d..a6f3796b9 100644 --- a/docs/plat/arm/arm-build-options.rst +++ b/docs/plat/arm/arm-build-options.rst @@ -57,8 +57,7 @@ Arm Platform Build Options ``ARM_ROTPK_LOCATION`` are: - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage - registers. The private key corresponding to this ROTPK hash is not - currently available. + registers. - ``devel_rsa`` : return a development public key hash embedded in the BL1 and BL2 binaries. This hash has been obtained from the RSA public key ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use @@ -70,6 +69,12 @@ Arm Platform Build Options use this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY`` when creating the certificates. +- ``ARM_ROTPK_HASH``: used when ``ARM_ROTPK_LOCATION=devel_*``. Specifies the + location of the ROTPK hash. Not expected to be a build option. This defaults to + ``plat/arm/board/common/rotpk/*_sha256.bin`` depending on the specified algorithm. + Providing ``ROT_KEY`` enforces generation of the hash from the ``ROT_KEY`` and + overwrites the default hash file. + - ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options: - ``tsram`` : Trusted SRAM (default option when TBB is not enabled) @@ -111,4 +116,4 @@ Arm CSS Platform-Specific Build Options -------------- -*Copyright (c) 2019, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* -- cgit v1.2.3 From 4d37aa76fdc53095f27b455f486013bdde10e0af Mon Sep 17 00:00:00 2001 From: Vijayenthiran Subramaniam Date: Thu, 26 Dec 2019 17:45:58 +0530 Subject: plat/arm/sgi: introduce number of chips macro Introduce macro 'CSS_SGI_CHIP_COUNT' to allow Arm CSS platforms with multi-chip support to define number of chiplets on the platform. By default, this flag is set to 1 and does not affect the existing single chip platforms. For multi-chip platforms, override the default value of CSS_SGI_CHIP_COUNT with the number of chiplets supported on the platform. As an example, the command below sets the number of chiplets to two on the RD-N1-Edge multi-chip platform: export CROSS_COMPILE= make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all Change-Id: If364dc36bd34b30cc356f74b3e97633933e6c8ee Signed-off-by: Vijayenthiran Subramaniam --- docs/plat/arm/arm-build-options.rst | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst index a6f3796b9..9622de65d 100644 --- a/docs/plat/arm/arm-build-options.rst +++ b/docs/plat/arm/arm-build-options.rst @@ -114,6 +114,11 @@ Arm CSS Platform-Specific Build Options management operations and for SCP RAM Firmware transfer. If this option is set to 1, then SCMI/SDS drivers will be used. Default is 0. + - ``CSS_SGI_CHIP_COUNT``: Configures the number of chips on a SGI/RD platform + which supports multi-chip operation. If ``CSS_SGI_CHIP_COUNT`` is set to any + valid value greater than 1, the platform code performs required configuration + to support multi-chip operation. + -------------- *Copyright (c) 2019-2020, Arm Limited. All rights reserved.* -- cgit v1.2.3 From 6227cca9e8bbcb322dc0caa0da94b9a3628385ed Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Mon, 17 Feb 2020 13:38:35 +0000 Subject: FVP: Fix BL31 load address and image size for RESET_TO_BL31=1 When TF-A is built with RESET_TO_BL31=1 option, BL31 is the first image to be run and should have all the memory allocated to it except for the memory reserved for Shared RAM at the start of Trusted SRAM. This patch fixes FVP BL31 load address and its image size for RESET_TO_BL31=1 option. BL31 startup address should be set to 0x400_1000 and its maximum image size to the size of Trusted SRAM minus the first 4KB of shared memory. Loading BL31 at 0x0402_0000 as it is currently stated in '\docs\plat\arm\fvp\index.rst' causes EL3 exception when the image size gets increased (i.e. building with LOG_LEVEL=50) but doesn't exceed 0x3B000 not causing build error. Change-Id: Ie450baaf247f1577112f8d143b24e76c39d33e91 Signed-off-by: Alexei Fedorov --- docs/plat/arm/fvp/index.rst | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index 37010e1a5..40e966117 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -277,15 +277,15 @@ And the FVP binary can be run with the following command: -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ - -C cluster0.cpu0.RVBAR=0x04020000 \ - -C cluster0.cpu1.RVBAR=0x04020000 \ - -C cluster0.cpu2.RVBAR=0x04020000 \ - -C cluster0.cpu3.RVBAR=0x04020000 \ - -C cluster1.cpu0.RVBAR=0x04020000 \ - -C cluster1.cpu1.RVBAR=0x04020000 \ - -C cluster1.cpu2.RVBAR=0x04020000 \ - -C cluster1.cpu3.RVBAR=0x04020000 \ - --data cluster0.cpu0="/bl31.bin"@0x04020000 \ + -C cluster0.cpu0.RVBAR=0x04001000 \ + -C cluster0.cpu1.RVBAR=0x04001000 \ + -C cluster0.cpu2.RVBAR=0x04001000 \ + -C cluster0.cpu3.RVBAR=0x04001000 \ + -C cluster1.cpu0.RVBAR=0x04001000 \ + -C cluster1.cpu1.RVBAR=0x04001000 \ + -C cluster1.cpu2.RVBAR=0x04001000 \ + -C cluster1.cpu3.RVBAR=0x04001000 \ + --data cluster0.cpu0="/bl31.bin"@0x04001000 \ --data cluster0.cpu0="/"@0x82000000 \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000 -- cgit v1.2.3 From e58901d4bc9507f0d7060a71509cb6bb78b3a947 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Wed, 26 Feb 2020 15:52:23 +0100 Subject: amlogic/axg: Add documentation page to the index It is needed to make it appear in the table of contents. Right now, all Amlogic documentation pages appear under the "Platform ports" section, except the AXG one. Change-Id: Ibcfc3b156888d2a9574953578978b629e185c708 Signed-off-by: Sandrine Bailleux --- docs/plat/index.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'docs/plat') diff --git a/docs/plat/index.rst b/docs/plat/index.rst index 63d29a9be..a6ef1884b 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -9,6 +9,7 @@ Platform Ports allwinner arm/index + meson-axg meson-gxbb meson-gxl meson-g12a @@ -53,4 +54,4 @@ documentation associated with them. -------------- -*Copyright (c) 2019, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* -- cgit v1.2.3 From 4ebdbc70836313087667d4c27cfc4bc13e95c48b Mon Sep 17 00:00:00 2001 From: Imre Kis Date: Thu, 27 Feb 2020 15:05:03 +0100 Subject: Add Cortex-A65/AE to the supported FVP list Cortex-A65x4 and Cortex-A65AEx8 is now included in the list of the supported Arm Fixed Virtual Platforms. Signed-off-by: Imre Kis Change-Id: Ibfcaec11bc75549d60455e96858d79b679e71e5e --- docs/plat/arm/fvp/index.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index 40e966117..169b6f366 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -26,6 +26,8 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores - ``FVP_Base_Cortex-A57x2-A53x4`` - ``FVP_Base_Cortex-A57x4-A53x4`` - ``FVP_Base_Cortex-A57x4`` +- ``FVP_Base_Cortex-A65x4`` (Version 11.9 build 41) +- ``FVP_Base_Cortex-A65AEx8`` (Version 11.9 build 41) - ``FVP_Base_Cortex-A72x4-A53x4`` - ``FVP_Base_Cortex-A72x4`` - ``FVP_Base_Cortex-A73x4-A53x4`` @@ -628,7 +630,7 @@ boot Linux with 4 CPUs using the AArch32 build of TF-A. -------------- -*Copyright (c) 2019, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* .. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts .. _Arm's website: `FVP models`_ -- cgit v1.2.3 From 4ebbea9592ab37fc62217d0ac62fa13a3e063527 Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Fri, 15 Nov 2019 20:16:58 +0530 Subject: docs: qemu: Add instructions to boot using FIP image Update qemu documentation with instructions to boot using FIP image. Also, add option to build TF-A with TBBR and firmware encryption enabled. Signed-off-by: Sumit Garg Change-Id: Ib3af485d413cd595352034c82c2268d7f4cb120a --- docs/plat/qemu.rst | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) (limited to 'docs/plat') diff --git a/docs/plat/qemu.rst b/docs/plat/qemu.rst index 88196bc93..afa32c11b 100644 --- a/docs/plat/qemu.rst +++ b/docs/plat/qemu.rst @@ -21,11 +21,13 @@ Current limitations: - Only cold boot is supported - No build instructions for QEMU\_EFI.fd and rootfs-arm64.cpio.gz -- No instructions for how to load a BL32 (Secure Payload) ``QEMU_EFI.fd`` can be dowloaded from http://snapshots.linaro.org/components/kernel/leg-virt-tianocore-edk2-upstream/latest/QEMU-KERNEL-AARCH64/RELEASE_GCC5/QEMU_EFI.fd +Booting via semi-hosting option +------------------------------- + Boot binaries, except BL1, are primarily loaded via semi-hosting so all binaries has to reside in the same directory as QEMU is started from. This is conveniently achieved with symlinks the local names as: @@ -50,3 +52,52 @@ To start (QEMU v4.1.0): -append "console=ttyAMA0,38400 keep_bootcon root=/dev/vda2" \ -initrd rootfs-arm64.cpio.gz -smp 2 -m 1024 -bios bl1.bin \ -d unimp -semihosting-config enable,target=native + +Booting via flash based firmwares +--------------------------------- + +Boot firmwares are loaded via secure FLASH0 device so ``bl1.bin`` and +``fip.bin`` should be concatenated to create a ``flash.bin`` that is flashed +onto secure FLASH0. + +- ``bl32.bin`` -> BL32 (``tee-header_v2.bin``) +- ``bl32_extra1.bin`` -> BL32 Extra1 (``tee-pager_v2.bin``) +- ``bl32_extra2.bin`` -> BL32 Extra2 (``tee-pageable_v2.bin``) +- ``bl33.bin`` -> BL33 (``QEMU_EFI.fd``) +- ``Image`` -> linux/arch/arm64/boot/Image + +To build: + +.. code:: shell + + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=qemu BL32=bl32.bin \ + BL32_EXTRA1=bl32_extra1.bin BL32_EXTRA2=bl32_extra2.bin \ + BL33=bl33.bin BL32_RAM_LOCATION=tdram SPD=opteed all fip + +To build with TBBR enabled, BL31 and BL32 encrypted with test key: + +.. code:: shell + + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=qemu BL32=bl32.bin \ + BL32_EXTRA1=bl32_extra1.bin BL32_EXTRA2=bl32_extra2.bin \ + BL33=bl33.bin BL32_RAM_LOCATION=tdram SPD=opteed all fip \ + MBEDTLS_DIR= TRUSTED_BOARD_BOOT=1 \ + GENERATE_COT=1 DECRYPTION_SUPPORT=aes_gcm FW_ENC_STATUS=0 \ + ENCRYPT_BL31=1 ENCRYPT_BL32=1 + +To build flash.bin: + +.. code:: shell + + dd if=build/qemu/release/bl1.bin of=flash.bin bs=4096 conv=notrunc + dd if=build/qemu/release/fip.bin of=flash.bin seek=64 bs=4096 conv=notrunc + +To start (QEMU v2.6.0): + +.. code:: shell + + qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57 \ + -kernel Image -no-acpi \ + -append 'console=ttyAMA0,38400 keep_bootcon root=/dev/vda2' \ + -initrd rootfs-arm64.cpio.gz -smp 2 -m 1024 -bios flash.bin \ + -d unimp -- cgit v1.2.3 From 3888c2d4daf192fd41c74112deac00e939dc106f Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 14 Mar 2020 10:24:41 +0800 Subject: docs: remove uefi-tools in hikey and hikey960 Since uefi-tools isn't used any more in hikey and hikey960, update the documents. Signed-off-by: Haojian Zhuang Change-Id: I0843d27610e241d442e58b6cd71967998730a35d --- docs/plat/hikey.rst | 24 ++++-------------------- docs/plat/hikey960.rst | 20 ++++---------------- 2 files changed, 8 insertions(+), 36 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst index 372d38867..6c488b827 100644 --- a/docs/plat/hikey.rst +++ b/docs/plat/hikey.rst @@ -26,9 +26,6 @@ Code Locations - l-loader: `link `__ -- uefi-tools: - `link `__ - - atf-fastboot: `link `__ @@ -45,7 +42,6 @@ Build Procedure git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5 git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4 git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2 - git clone https://git.linaro.org/uefi/uefi-tools git clone https://github.com/96boards-hikey/atf-fastboot - Create the symbol link to OpenPlatformPkg in edk2. @@ -57,13 +53,12 @@ Build Procedure - Prepare AARCH64 && AARCH32 toolchain. Prepare python. -- If your hikey hardware is built by CircuitCo, update *uefi-tools/platform.config* first. *(optional)* - **Uncomment the below sentence. Otherwise, UEFI can't output messages on serial +- If your hikey hardware is built by CircuitCo, update *OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dsc* first. *(optional)* console on hikey.** .. code:: shell - BUILDFLAGS=-DSERIAL_BASE=0xF8015000 + DEFINE SERIAL_BASE=0xF8015000 If your hikey hardware is built by LeMaker, nothing to do. @@ -71,19 +66,8 @@ Build Procedure .. code:: shell - BUILD_OPTION=DEBUG - export AARCH64_TOOLCHAIN=GCC5 - export UEFI_TOOLS_DIR=${BUILD_PATH}/uefi-tools - export EDK2_DIR=${BUILD_PATH}/edk2 - EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey/${BUILD_OPTION}_${AARCH64_TOOLCHAIN} - # Build fastboot for Trusted Firmware-A. It's used for recovery mode. - cd ${BUILD_PATH}/atf-fastboot - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=hikey DEBUG=1 - # Convert DEBUG/RELEASE to debug/release - FASTBOOT_BUILD_OPTION=$(echo ${BUILD_OPTION} | tr '[A-Z]' '[a-z]') - cd ${EDK2_DIR} - # Build UEFI & Trusted Firmware-A - ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey + cd {BUILD_PATH}/arm-trusted-firmware + sh ../l-loader/build_uefi.sh hikey - Generate l-loader.bin and partition table for aosp. The eMMC capacity is either 8GB or 4GB. Just change "aosp-8g" to "linux-8g" for debian. diff --git a/docs/plat/hikey960.rst b/docs/plat/hikey960.rst index 3d42a77c5..982c2c854 100644 --- a/docs/plat/hikey960.rst +++ b/docs/plat/hikey960.rst @@ -26,9 +26,6 @@ Code Locations - l-loader: `link `__ -- uefi-tools: - `link `__ - Build Procedure ~~~~~~~~~~~~~~~ @@ -42,7 +39,6 @@ Build Procedure git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5 git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4 git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2 - git clone https://git.linaro.org/uefi/uefi-tools - Create the symbol link to OpenPlatformPkg in edk2. @@ -53,13 +49,11 @@ Build Procedure - Prepare AARCH64 toolchain. -- If your hikey960 hardware is v1, update *uefi-tools/platform.config* first. *(optional)* - **Uncomment the below sentence. Otherwise, UEFI can't output messages on serial - console on hikey960 v1.** +- If your hikey960 hardware is v1, update *OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960.dsc* first. *(optional)* .. code:: shell - BUILDFLAGS=-DSERIAL_BASE=0xFDF05000 + DEFINE SERIAL_BASE=0xFDF05000 If your hikey960 hardware is v2 or newer, nothing to do. @@ -67,14 +61,8 @@ Build Procedure .. code:: shell - BUILD_OPTION=DEBUG - export AARCH64_TOOLCHAIN=GCC5 - export UEFI_TOOLS_DIR=${BUILD_PATH}/uefi-tools - export EDK2_DIR=${BUILD_PATH}/edk2 - EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey960/${BUILD_OPTION}_${AARCH64_TOOLCHAIN} - cd ${EDK2_DIR} - # Build UEFI & Trusted Firmware-A - ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey960 + cd {BUILD_PATH}/arm-trusted-firmware + sh ../l-loader/build_uefi.sh hikey960 - Generate l-loader.bin and partition table. *Make sure that you're using the sgdisk in the l-loader directory.* -- cgit v1.2.3 From db059ea4d9741b54ad4a8305e3edc24d21c1d5ac Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 31 Mar 2020 20:38:01 +0200 Subject: doc: Fix broken external link for Odroid C2 The file README.odroid-c2 has been moved in the U-Boot repository. Reference the official uplink repository. Signed-off-by: Heinrich Schuchardt Change-Id: Ie72c7aefd6363a406f88ad2c87faee1c7a2125a3 --- docs/plat/meson-gxbb.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'docs/plat') diff --git a/docs/plat/meson-gxbb.rst b/docs/plat/meson-gxbb.rst index 2cd8342cb..dbd83e0bc 100644 --- a/docs/plat/meson-gxbb.rst +++ b/docs/plat/meson-gxbb.rst @@ -23,4 +23,4 @@ This port has been tested in a ODROID-C2. After building it, follow the instructions in the `U-Boot repository`_, replacing the mentioned **bl31.bin** by the one built from this port. -.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/board/amlogic/odroid-c2/README.odroid-c2 +.. _U-Boot repository: https://gitlab.denx.de/u-boot/u-boot/-/blob/master/board/amlogic/p200/README.odroid-c2 -- cgit v1.2.3 From fd1017b121f7be9434bbdcb33177bf9311bf5d82 Mon Sep 17 00:00:00 2001 From: Sheetal Tigadoli Date: Sat, 21 Mar 2020 00:12:50 +0530 Subject: doc: brcm: Add documentation file for brcm stingray platform Signed-off-by: Sheetal Tigadoli Change-Id: I5e2c1220e9694d6ba771cc90daa0e70e967eebe6 --- docs/plat/brcm-stingray.rst | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 docs/plat/brcm-stingray.rst (limited to 'docs/plat') diff --git a/docs/plat/brcm-stingray.rst b/docs/plat/brcm-stingray.rst new file mode 100644 index 000000000..c43c8504c --- /dev/null +++ b/docs/plat/brcm-stingray.rst @@ -0,0 +1,40 @@ +Description +=========== +Broadcom's Stingray(BCM958742t) is a multi-core processor with 8 Cortex-A72 cores. +Trusted Firmware-A (TF-A) is used to implement secure world firmware, supporting +BL2 and BL31 for Broadcom Stingray SoCs + +On Poweron, Boot ROM will load bl2 image and Bl2 will initialize the hardware, +then loads bl31 and bl33 into DDR and boots to bl33. + +Boot Sequence +============= + +Bootrom --> TF-A BL2 --> TF-A BL31 --> BL33(u-boot) + +Code Locations +-------------- +- Trusted Firmware-A: + `link `__ + +How to build +============ + +Build Procedure +--------------- + +- Prepare AARCH64 toolchain. + +- Build u-boot first, and get the binary image: u-boot.bin, + +- Build TF-A + + Build fip: + + .. code::shell + + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=stingray BOARD_CFG=bcm958742t all fip BL33=u-boot.bin + +Deploy TF-A Images +----------------- +The u-boot will be upstreamed soon, this doc will be updated once they are ready, and the link will be posted. -- cgit v1.2.3 From 77516a733100bd1e138a4af319688eeb7d1d08a6 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Wed, 15 Apr 2020 11:13:38 +0200 Subject: Fix Broadcom Stingray platform documentation - Include the platform documentation in the table of contents. - Add a title for the document. Without this, the platform documentation was listed under a 'Description' title on page https://trustedfirmware-a.readthedocs.io/en/latest/plat/index.html - Change TF-A git repository URL to point to tf.org (rather than the deprecated read-only mirror on Github). - Fix the restructuredText syntax for the FIP command line. It was not displayed at all on the rendered version. Change-Id: I7a0f062bcf8e0dfc65e8f8bdd6775c497a47e619 Signed-off-by: Sandrine Bailleux --- docs/plat/brcm-stingray.rst | 21 ++++++++++++--------- docs/plat/index.rst | 1 + 2 files changed, 13 insertions(+), 9 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/brcm-stingray.rst b/docs/plat/brcm-stingray.rst index c43c8504c..95029cc3d 100644 --- a/docs/plat/brcm-stingray.rst +++ b/docs/plat/brcm-stingray.rst @@ -1,27 +1,30 @@ +Broadcom Stingray +================= + Description -=========== +----------- Broadcom's Stingray(BCM958742t) is a multi-core processor with 8 Cortex-A72 cores. Trusted Firmware-A (TF-A) is used to implement secure world firmware, supporting -BL2 and BL31 for Broadcom Stingray SoCs +BL2 and BL31 for Broadcom Stingray SoCs. On Poweron, Boot ROM will load bl2 image and Bl2 will initialize the hardware, then loads bl31 and bl33 into DDR and boots to bl33. Boot Sequence -============= +------------- Bootrom --> TF-A BL2 --> TF-A BL31 --> BL33(u-boot) Code Locations --------------- +~~~~~~~~~~~~~~ - Trusted Firmware-A: - `link `__ + `link `__ How to build -============ +------------ Build Procedure ---------------- +~~~~~~~~~~~~~~~ - Prepare AARCH64 toolchain. @@ -31,10 +34,10 @@ Build Procedure Build fip: - .. code::shell + .. code:: shell make CROSS_COMPILE=aarch64-linux-gnu- PLAT=stingray BOARD_CFG=bcm958742t all fip BL33=u-boot.bin Deploy TF-A Images ------------------ +~~~~~~~~~~~~~~~~~~ The u-boot will be upstreamed soon, this doc will be updated once they are ready, and the link will be posted. diff --git a/docs/plat/index.rst b/docs/plat/index.rst index a6ef1884b..7969003c9 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -37,6 +37,7 @@ Platform Ports ti-k3 xilinx-versal xilinx-zynqmp + brcm-stingray This section provides a list of supported upstream *platform ports* and the documentation associated with them. -- cgit v1.2.3 From 495553d5725a9ea7f9b1c651144e2278e1518c44 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Wed, 15 Apr 2020 17:48:36 -0500 Subject: docs: Fixes and updates for the v2.3 release A small set of misc changes to ensure correctness before the v2.3 release. Signed-off-by: Lauren Wehrmeister Change-Id: I5b4e35b3b46616df0453cecff61f5a414951cd62 --- docs/plat/arm/fvp/index.rst | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index 169b6f366..eb7eb0054 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -12,7 +12,7 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only). .. note:: - The FVP models used are Version 11.6 Build 45, unless otherwise stated. + The FVP models used are Version 11.9 Build 41, unless otherwise stated. - ``FVP_Base_AEMv8A-AEMv8A`` - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` @@ -26,8 +26,8 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores - ``FVP_Base_Cortex-A57x2-A53x4`` - ``FVP_Base_Cortex-A57x4-A53x4`` - ``FVP_Base_Cortex-A57x4`` -- ``FVP_Base_Cortex-A65x4`` (Version 11.9 build 41) -- ``FVP_Base_Cortex-A65AEx8`` (Version 11.9 build 41) +- ``FVP_Base_Cortex-A65x4`` +- ``FVP_Base_Cortex-A65AEx8`` - ``FVP_Base_Cortex-A72x4-A53x4`` - ``FVP_Base_Cortex-A72x4`` - ``FVP_Base_Cortex-A73x4-A53x4`` @@ -36,13 +36,13 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores - ``FVP_Base_Cortex-A76x4`` - ``FVP_Base_Cortex-A76AEx4`` - ``FVP_Base_Cortex-A76AEx8`` -- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) +- ``FVP_Base_Cortex-A77x4`` - ``FVP_Base_Neoverse-N1x4`` - ``FVP_Base_Zeusx4`` -- ``FVP_CSS_SGI-575`` (Version 11.3 build 42) -- ``FVP_CSS_SGM-775`` (Version 11.3 build 42) -- ``FVP_RD_E1Edge`` (Version 11.3 build 42) -- ``FVP_RD_N1Edge`` +- ``FVP_CSS_SGI-575`` (Version 11.10 build 25) +- ``FVP_CSS_SGM-775`` +- ``FVP_RD_E1Edge`` +- ``FVP_RD_N1Edge`` (Version 11.10 build 25) - ``Foundation_Platform`` The latest version of the AArch32 build of TF-A has been tested on the -- cgit v1.2.3 From 58fdd608a495ebc969c8f1cb39ba1705df3b277c Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Thu, 28 Nov 2019 13:16:33 +0800 Subject: plat: imx8mn: Add imx8mn basic support Add imx8mn basic support Signed-off-by: Jacky Bai Change-Id: Ibdfcc87700bfaf980e429f3a5fa08515218ae78d --- docs/plat/imx8m.rst | 1 + 1 file changed, 1 insertion(+) (limited to 'docs/plat') diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst index 8acd13cf7..ba087a2a3 100644 --- a/docs/plat/imx8m.rst +++ b/docs/plat/imx8m.rst @@ -32,6 +32,7 @@ Build Procedure Target_SoC should be "imx8mq" for i.MX8MQ SoC. Target_SoC should be "imx8mm" for i.MX8MM SoC. + Target_SoC should be "imx8mn" for i.MX8MN SoC. Deploy TF-A Images ~~~~~~~~~~~~~~~~~~ -- cgit v1.2.3 From f5c58af653b69687b17aac10da1d62179abe48ec Mon Sep 17 00:00:00 2001 From: Usama Arif Date: Fri, 17 Apr 2020 16:13:39 +0100 Subject: plat/arm: Introduce TC0 platform This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later. TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy. Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS. Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif --- docs/plat/arm/index.rst | 1 + docs/plat/arm/tc0/index.rst | 50 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 docs/plat/arm/tc0/index.rst (limited to 'docs/plat') diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst index e26f75e56..1afe475c6 100644 --- a/docs/plat/arm/index.rst +++ b/docs/plat/arm/index.rst @@ -8,6 +8,7 @@ Arm Development Platforms juno/index fvp/index fvp-ve/index + tc0/index arm-build-options This chapter holds documentation related to Arm's development platforms, diff --git a/docs/plat/arm/tc0/index.rst b/docs/plat/arm/tc0/index.rst new file mode 100644 index 000000000..34d1f1342 --- /dev/null +++ b/docs/plat/arm/tc0/index.rst @@ -0,0 +1,50 @@ +TC0 Total Compute Platform +========================== + +Some of the features of TC0 platform referenced in TF-A include: + +- A `System Control Processor `_ + to abstract power and system management tasks away from application + processors. The RAM firmware for SCP is included in the TF-A FIP and is + loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access + to AP SRAM). +- GICv4 +- Trusted Board Boot +- SCMI +- MHUv2 + +Boot Sequence +------------- + +The execution begins from SCP_BL1. SCP_BL1 powers up the AP which starts +executing AP_BL1 and then executes AP_BL2 which loads the SCP_BL2 from +FIP to SRAM. The SCP has access to AP SRAM. The address and size of SCP_BL2 +is communicated to SCP using SDS. SCP copies SCP_BL2 from SRAM to its own +RAM and starts executing it. The AP then continues executing the rest of TF-A +stages including BL31 runtime stage and hands off executing to +Non-secure world (u-boot). + +Build Procedure (TF-A only) +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Obtain arm `toolchain `_. + Set the CROSS_COMPILE environment variable to point to the toolchain folder. + +- Build TF-A: + + .. code:: shell + + make PLAT=tc0 BL33= \ + SCP_BL2= all fip + + Enable TBBR by adding the following options to the make command: + + .. code:: shell + + MBEDTLS_DIR= \ + TRUSTED_BOARD_BOOT=1 \ + GENERATE_COT=1 \ + ARM_ROTPK_LOCATION=devel_rsa \ + ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem + +*Copyright (c) 2020, Arm Limited. All rights reserved.* -- cgit v1.2.3 From a28471722afb3ae784d7bce2118c2ea703f8444c Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Tue, 5 Nov 2019 13:14:59 +0100 Subject: marvell: armada: add extra level in marvell platform hierarchy This commit is a preparation for upcoming support for OcteonTX and OcteonTX2 product families. Armada platform related files (docs, plat, include/plat) are moved to the new "armada" sub-folder. Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655 Signed-off-by: Grzegorz Jaszczyk Signed-off-by: Marcin Wojtas --- docs/plat/marvell/armada/build.rst | 253 +++++++++++++++++++++ .../marvell/armada/misc/mvebu-a8k-addr-map.rst | 49 ++++ docs/plat/marvell/armada/misc/mvebu-amb.rst | 58 +++++ docs/plat/marvell/armada/misc/mvebu-ccu.rst | 33 +++ docs/plat/marvell/armada/misc/mvebu-io-win.rst | 46 ++++ docs/plat/marvell/armada/misc/mvebu-iob.rst | 52 +++++ docs/plat/marvell/armada/porting.rst | 163 +++++++++++++ docs/plat/marvell/build.rst | 253 --------------------- docs/plat/marvell/index.rst | 14 +- docs/plat/marvell/misc/mvebu-a8k-addr-map.rst | 49 ---- docs/plat/marvell/misc/mvebu-amb.rst | 58 ----- docs/plat/marvell/misc/mvebu-ccu.rst | 33 --- docs/plat/marvell/misc/mvebu-io-win.rst | 46 ---- docs/plat/marvell/misc/mvebu-iob.rst | 52 ----- docs/plat/marvell/porting.rst | 163 ------------- 15 files changed, 661 insertions(+), 661 deletions(-) create mode 100644 docs/plat/marvell/armada/build.rst create mode 100644 docs/plat/marvell/armada/misc/mvebu-a8k-addr-map.rst create mode 100644 docs/plat/marvell/armada/misc/mvebu-amb.rst create mode 100644 docs/plat/marvell/armada/misc/mvebu-ccu.rst create mode 100644 docs/plat/marvell/armada/misc/mvebu-io-win.rst create mode 100644 docs/plat/marvell/armada/misc/mvebu-iob.rst create mode 100644 docs/plat/marvell/armada/porting.rst delete mode 100644 docs/plat/marvell/build.rst delete mode 100644 docs/plat/marvell/misc/mvebu-a8k-addr-map.rst delete mode 100644 docs/plat/marvell/misc/mvebu-amb.rst delete mode 100644 docs/plat/marvell/misc/mvebu-ccu.rst delete mode 100644 docs/plat/marvell/misc/mvebu-io-win.rst delete mode 100644 docs/plat/marvell/misc/mvebu-iob.rst delete mode 100644 docs/plat/marvell/porting.rst (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst new file mode 100644 index 000000000..1b60fc554 --- /dev/null +++ b/docs/plat/marvell/armada/build.rst @@ -0,0 +1,253 @@ +TF-A Build Instructions for Marvell Platforms +============================================= + +This section describes how to compile the Trusted Firmware-A (TF-A) project for Marvell's platforms. + +Build Instructions +------------------ +(1) Set the cross compiler + + .. code:: shell + + > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu- + +(2) Set path for FIP images: + +Set U-Boot image path (relatively to TF-A root or absolute path) + + .. code:: shell + + > export BL33=path/to/u-boot.bin + +For example: if U-Boot project (and its images) is located at ``~/project/u-boot``, +BL33 should be ``~/project/u-boot/u-boot.bin`` + + .. note:: + + *u-boot.bin* should be used and not *u-boot-spl.bin* + +Set MSS/SCP image path (mandatory only for Armada80x0) + + .. code:: shell + + > export SCP_BL2=path/to/mrvl_scp_bl2*.img + +(3) Armada-37x0 build requires WTP tools installation. + +See below in the section "Tools and external components installation". +Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3 + + .. code:: shell + + > sudo apt-get install gcc-arm-linux-gnueabi + +(4) Clean previous build residuals (if any) + + .. code:: shell + + > make distclean + +(5) Build TF-A + +There are several build options: + +- DEBUG + + Default is without debug information (=0). in order to enable it use ``DEBUG=1``. + Must be disabled when building UART recovery images due to current console driver + implementation that is not compatible with Xmodem protocol used for boot image download. + +- LOG_LEVEL + + Defines the level of logging which will be purged to the default output port. + + LOG_LEVEL_NONE 0 + LOG_LEVEL_ERROR 10 + LOG_LEVEL_NOTICE 20 + LOG_LEVEL_WARNING 30 + LOG_LEVEL_INFO 40 + LOG_LEVEL_VERBOSE 50 + +- USE_COHERENT_MEM + + This flag determines whether to include the coherent memory region in the + BL memory map or not. + +- LLC_ENABLE + + Flag defining the LLC (L3) cache state. The cache is enabled by default (``LLC_ENABLE=1``). + +- MARVELL_SECURE_BOOT + + Build trusted(=1)/non trusted(=0) image, default is non trusted. + +- BLE_PATH + + Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds. + The parameter is optional, its default value is ``plat/marvell/armada/a8k/common/ble``. + +- MV_DDR_PATH + + For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0, + it is used for ddr_tool build. + + Usage example: MV_DDR_PATH=path/to/mv_ddr + + The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr + sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter + is necessary for A37x0. + + For the mv_ddr source location, check the section "Tools and external components installation" + +- DDR_TOPOLOGY + + For Armada37x0 only, the DDR topology map index/name, default is 0. + + Supported Options: + - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) + - DDR4 1CS (1): DB-88F3720-DDR4-Modular (512MB) + - DDR3 2CS (2): EspressoBIN V3-V5 (1GB) + - DDR4 2CS (3): DB-88F3720-DDR4-Modular (4GB) + - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB) + - DDR4 1CS (5): EspressoBin V7 (1GB) + - DDR4 2CS (6): EspressoBin V7 (2GB) + - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB + +- CLOCKSPRESET + + For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency, + default is CPU_800_DDR_800. + + - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz + - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz + - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz + - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz + +- BOOTDEV + + For Armada37x0 only, the flash boot device, default is ``SPINOR``. + + Currently, Armada37x0 only supports ``SPINOR``, ``SPINAND``, ``EMMCNORM`` and ``SATA``: + + - SPINOR - SPI NOR flash boot + - SPINAND - SPI NAND flash boot + - EMMCNORM - eMMC Download Mode + + Download boot loader or program code from eMMC flash into CM3 or CA53 + Requires full initialization and command sequence + + - SATA - SATA device boot + +- PARTNUM + + For Armada37x0 only, the boot partition number, default is 0. + + To boot from eMMC, the value should be aligned with the parameter in + U-Boot with name of ``CONFIG_SYS_MMC_ENV_PART``, whose value by default is + 1. For details about CONFIG_SYS_MMC_ENV_PART, please refer to the U-Boot + build instructions. + +- WTMI_IMG + + For Armada37x0 only, the path of the WTMI image can point to an image which + does nothing, an image which supports EFUSE or a customized CM3 firmware + binary. The default image is wtmi.bin that built from sources in WTP + folder, which is the next option. If the default image is OK, then this + option should be skipped. + +- WTP + + For Armada37x0 only, use this parameter to point to wtptools source code + directory, which can be found as a3700_utils.zip in the release. Usage + example: ``WTP=/path/to/a3700_utils`` + + For example, in order to build the image in debug mode with log level up to 'notice' level run + + .. code:: shell + + > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT= all fip + + And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level, + the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS, + the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command + line is as following + + .. code:: shell + + > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \ + MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip + + Supported MARVELL_PLATFORM are: + - a3700 (for both A3720 DB and EspressoBin) + - a70x0 + - a70x0_amc (for AMC board) + - a80x0 + - a80x0_mcbin (for MacciatoBin) + +Special Build Flags +-------------------- + +- PLAT_RECOVERY_IMAGE_ENABLE + When set this option to enable secondary recovery function when build atf. + In order to build UART recovery image this operation should be disabled for + a70x0 and a80x0 because of hardware limitation (boot from secondary image + can interrupt UART recovery process). This MACRO definition is set in + ``plat/marvell/armada/a8k/common/include/platform_def.h`` file. + +For more information about build options, please refer to the +:ref:`Build Options` document. + + +Build output +------------ +Marvell's TF-A compilation generates 7 files: + + - ble.bin - BLe image + - bl1.bin - BL1 image + - bl2.bin - BL2 image + - bl31.bin - BL31 image + - fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images) + - boot-image.bin - TF-A image (contains BL1 and FIP images) + - flash-image.bin - Image which contains boot-image.bin and SPL image. + Should be placed on the boot flash/device. + + +Tools and external components installation +------------------------------------------ + +Armada37x0 Builds require installation of 3 components +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +(1) ARM cross compiler capable of building images for the service CPU (CM3). + This component is usually included in the Linux host packages. + On Debian/Ubuntu hosts the default GNU ARM tool chain can be installed + using the following command + + .. code:: shell + + > sudo apt-get install gcc-arm-linux-gnueabi + + Only if required, the default tool chain prefix ``arm-linux-gnueabi-`` can be + overwritten using the environment variable ``CROSS_CM3``. + Example for BASH shell + + .. code:: shell + + > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi + +(2) DDR initialization library sources (mv_ddr) available at the following repository + (use the "mv_ddr-armada-atf-mainline" branch): + + https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git + +(3) Armada3700 tools available at the following repository (use the latest release branch): + + https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git + +Armada70x0 and Armada80x0 Builds require installation of an additional component +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +(1) DDR initialization library sources (mv_ddr) available at the following repository + (use the "mv_ddr-armada-atf-mainline" branch): + + https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git diff --git a/docs/plat/marvell/armada/misc/mvebu-a8k-addr-map.rst b/docs/plat/marvell/armada/misc/mvebu-a8k-addr-map.rst new file mode 100644 index 000000000..e88a4582b --- /dev/null +++ b/docs/plat/marvell/armada/misc/mvebu-a8k-addr-map.rst @@ -0,0 +1,49 @@ +Address decoding flow and address translation units of Marvell Armada 8K SoC family +=================================================================================== + +:: + + +--------------------------------------------------------------------------------------------------+ + | +-------------+ +--------------+ | + | | Memory +----- DRAM CS | | + |+------------+ +-----------+ +-----------+ | Controller | +--------------+ | + || AP DMA | | | | | +-------------+ | + || SD/eMMC | | CA72 CPUs | | AP MSS | +-------------+ | + || MCI-0/1 | | | | | | Memory | | + |+------+-----+ +--+--------+ +--------+--+ +------------+ | Controller | +-------------+ | + | | | | | +----- Translaton | |AP | | + | | | | | | +-------------+ |Configuration| | + | | | +-----+ +-------------------------Space | | + | | | +-------------+ | CCU | +-------------+ | + | | | | MMU +---------+ Windows | +-----------+ +-------------+ | + | | +-| translation | | Lookup +---- +--------- AP SPI | | + | | +-------------+ | | | | +-------------+ | + | | +-------------+ | | | IO | +-------------+ | + | +------------| SMMU +---------+ | | Windows +--------- AP MCI0/1 | | + | | translation | +------------+ | Lookup | +-------------+ | + | +---------+---+ | | +-------------+ | + | - | | +--------- AP STM | | + | +----------------- | | +-------------+ | + | AP | | +-+---------+ | + +---------------------------------------------------------------|----------------------------------+ + +-------------|-------------------------------------------------|----------------------------------+ + | CP | +-------------+ +------+-----+ +-------------------+ | + | | | | | +------- SB CFG Space | | + | | | DIOB | | | +-------------------+ | + | | | Windows ----------------- IOB | +-------------------+ | + | | | Control | | Windows +------| SB PCIe-0 - PCIe2 | | + | | | | | Lookup | +-------------------+ | + | | +------+------+ | | +-------------------+ | + | | | | +------+ SB NAND | | + | | | +------+-----+ +-------------------+ | + | | | | | + | | | | | + | +------------------+ +------------+ +------+-----+ +-------------------+ | + | | Network Engine | | | | +------- SB SPI-0/SPI-1 | | + | | Security Engine | | PCIe, MSS | | RUNIT | +-------------------+ | + | | SATA, USB | | DMA | | Windows | +-------------------+ | + | | SD/eMMC | | | | Lookup +------- SB Device Bus | | + | | TDM, I2C | | | | | +-------------------+ | + | +------------------+ +------------+ +------------+ | + | | + +--------------------------------------------------------------------------------------------------+ diff --git a/docs/plat/marvell/armada/misc/mvebu-amb.rst b/docs/plat/marvell/armada/misc/mvebu-amb.rst new file mode 100644 index 000000000..d734003d6 --- /dev/null +++ b/docs/plat/marvell/armada/misc/mvebu-amb.rst @@ -0,0 +1,58 @@ +AMB - AXI MBUS address decoding +=============================== + +AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs. + +The Runit offers a second level of address windows lookup. It is used to map +transaction towards the CD BootROM, SPI0, SPI1 and Device bus (NOR). + +The Runit contains eight configurable windows. Each window defines a contiguous, +address space and the properties associated with that address space. + +:: + + Unit Bank ATTR + Device-Bus DEV_BOOT_CS 0x2F + DEV_CS0 0x3E + DEV_CS1 0x3D + DEV_CS2 0x3B + DEV_CS3 0x37 + SPI-0 SPI_A_CS0 0x1E + SPI_A_CS1 0x5E + SPI_A_CS2 0x9E + SPI_A_CS3 0xDE + SPI_A_CS4 0x1F + SPI_A_CS5 0x5F + SPI_A_CS6 0x9F + SPI_A_CS7 0xDF + SPI SPI_B_CS0 0x1A + SPI_B_CS1 0x5A + SPI_B_CS2 0x9A + SPI_B_CS3 0xDA + BOOT_ROM BOOT_ROM 0x1D + UART UART 0x01 + +Mandatory functions +------------------- + +- marvell_get_amb_memory_map + Returns the AMB windows configuration and the number of windows + +Mandatory structures +-------------------- + +- amb_memory_map + Array that include the configuration of the windows. Every window/entry is a + struct which has 2 parameters: + + - Base address of the window + - Attribute of the window + +Examples +-------- + +.. code:: c + + struct addr_map_win amb_memory_map[] = { + {0xf900, AMB_DEV_CS0_ID}, + }; diff --git a/docs/plat/marvell/armada/misc/mvebu-ccu.rst b/docs/plat/marvell/armada/misc/mvebu-ccu.rst new file mode 100644 index 000000000..5bac11faf --- /dev/null +++ b/docs/plat/marvell/armada/misc/mvebu-ccu.rst @@ -0,0 +1,33 @@ +Marvell CCU address decoding bindings +===================================== + +CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs. + +The CCU node includes a description of the address decoding configuration. + +Mandatory functions +------------------- + +- marvell_get_ccu_memory_map + Return the CCU windows configuration and the number of windows of the + specific AP. + +Mandatory structures +-------------------- + +- ccu_memory_map + Array that includes the configuration of the windows. Every window/entry is + a struct which has 3 parameters: + + - Base address of the window + - Size of the window + - Target-ID of the window + +Example +------- + +.. code:: c + + struct addr_map_win ccu_memory_map[] = { + {0x00000000f2000000, 0x00000000e000000, IO_0_TID}, /* IO window */ + }; diff --git a/docs/plat/marvell/armada/misc/mvebu-io-win.rst b/docs/plat/marvell/armada/misc/mvebu-io-win.rst new file mode 100644 index 000000000..52845ca02 --- /dev/null +++ b/docs/plat/marvell/armada/misc/mvebu-io-win.rst @@ -0,0 +1,46 @@ +Marvell IO WIN address decoding bindings +======================================== + +IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. + +The IO WIN includes a description of the address decoding configuration. + +Transactions that are decoded by CCU windows as IO peripheral, have an additional +layer of decoding. This additional address decoding layer defines one of the +following targets: + +- **0x0** = BootRom +- **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream) +- **0x2** = SPI direct access +- **0x3** = PCIe registers +- **0x4** = MCI Port +- **0x5** = PCIe port + +Mandatory functions +------------------- + +- marvell_get_io_win_memory_map + Returns the IO windows configuration and the number of windows of the + specific AP. + +Mandatory structures +-------------------- + +- io_win_memory_map + Array that include the configuration of the windows. Every window/entry is + a struct which has 3 parameters: + + - Base address of the window + - Size of the window + - Target-ID of the window + +Example +------- + +.. code:: c + + struct addr_map_win io_win_memory_map[] = { + {0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/ + {0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/ + {0x00000000f6000000, 0x000000000100000, MCIPHY_TID}, /* MCI window 1Mb for PHY-reg*/ + }; diff --git a/docs/plat/marvell/armada/misc/mvebu-iob.rst b/docs/plat/marvell/armada/misc/mvebu-iob.rst new file mode 100644 index 000000000..d02a7e84c --- /dev/null +++ b/docs/plat/marvell/armada/misc/mvebu-iob.rst @@ -0,0 +1,52 @@ +Marvell IOB address decoding bindings +===================================== + +IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs. + +The IOB includes a description of the address decoding configuration. + +IOB supports up to n (in CP110 n=24) windows for external memory transaction. +When a transaction passes through the IOB, its address is compared to each of +the enabled windows. If there is a hit and it passes the security checks, it is +advanced to the target port. + +Mandatory functions +------------------- + +- marvell_get_iob_memory_map + Returns the IOB windows configuration and the number of windows + +Mandatory structures +-------------------- + +- iob_memory_map + Array that includes the configuration of the windows. Every window/entry is + a struct which has 3 parameters: + + - Base address of the window + - Size of the window + - Target-ID of the window + +Target ID options +----------------- + +- **0x0** = Internal configuration space +- **0x1** = MCI0 +- **0x2** = PEX1_X1 +- **0x3** = PEX2_X1 +- **0x4** = PEX0_X4 +- **0x5** = NAND flash +- **0x6** = RUNIT (NOR/SPI/BootRoom) +- **0x7** = MCI1 + +Example +------- + +.. code:: c + + struct addr_map_win iob_memory_map[] = { + {0x00000000f7000000, 0x0000000001000000, PEX1_TID}, /* PEX1_X1 window */ + {0x00000000f8000000, 0x0000000001000000, PEX2_TID}, /* PEX2_X1 window */ + {0x00000000f6000000, 0x0000000001000000, PEX0_TID}, /* PEX0_X4 window */ + {0x00000000f9000000, 0x0000000001000000, NAND_TID} /* NAND window */ + }; diff --git a/docs/plat/marvell/armada/porting.rst b/docs/plat/marvell/armada/porting.rst new file mode 100644 index 000000000..1723ebb57 --- /dev/null +++ b/docs/plat/marvell/armada/porting.rst @@ -0,0 +1,163 @@ +TF-A Porting Guide for Marvell Platforms +======================================== + +This section describes how to port TF-A to a customer board, assuming that the +SoC being used is already supported in TF-A. + + +Source Code Structure +--------------------- + +- The customer platform specific code shall reside under ``plat/marvell/armada//_cust`` + (e.g. 'plat/marvell/armada/a8k/a7040_cust'). +- The platform name for build purposes is called ``_cust`` (e.g. ``a7040_cust``). +- The build system will reuse all files from within the soc directory, and take only the porting + files from the customer platform directory. + +Files that require porting are located at ``plat/marvell/armada//_cust`` directory. + + +Armada-70x0/Armada-80x0 Porting +------------------------------- + +SoC Physical Address Map (marvell_plat_config.c) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This file describes the SoC physical memory mapping to be used for the CCU, +IOWIN, AXI-MBUS and IOB address decode units (Refer to the functional spec for +more details). + +In most cases, using the default address decode windows should work OK. + +In cases where a special physical address map is needed (e.g. Special size for +PCIe MEM windows, large memory mapped SPI flash...), then porting of the SoC +memory map is required. + +.. note:: + For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please + refer to the SoC functional spec, and under + ``docs/marvell/misc/mvebu-[ccu/iob/amb/io-win].txt`` files. + +boot loader recovery (marvell_plat_config.c) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Background: + + Boot rom can skip the current image and choose to boot from next position if a + specific value (``0xDEADB002``) is returned by the ble main function. This + feature is used for boot loader recovery by booting from a valid flash-image + saved in next position on flash (e.g. address 2M in SPI flash). + + Supported options to implement the skip request are: + - GPIO + - I2C + - User defined + +- Porting: + + Under marvell_plat_config.c, implement struct skip_image that includes + specific board parameters. + + .. warning:: + To disable this feature make sure the struct skip_image is not implemented. + +- Example: + +In A7040-DB specific implementation +(``plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c``), the image skip is +implemented using GPIO: mpp 33 (SW5). + +Before resetting the board make sure there is a valid image on the next flash +address: + + -tftp [valid address] flash-image.bin + -sf update [valid address] 0x2000000 [size] + +Press reset and keep pressing the button connected to the chosen GPIO pin. A +skip image request message is printed on the screen and boot rom boots from the +saved image at the next position. + +DDR Porting (dram_port.c) +~~~~~~~~~~~~~~~~~~~~~~~~~ + +This file defines the dram topology and parameters of the target board. + +The DDR code is part of the BLE component, which is an extension of ARM Trusted +Firmware (TF-A). + +The DDR driver called mv_ddr is released separately apart from TF-A sources. + +The BLE and consequently, the DDR init code is executed at the early stage of +the boot process. + +Each supported platform of the TF-A has its own DDR porting file called +dram_port.c located at ``atf/plat/marvell/armada/a8k//board`` directory. + +Please refer to '/doc/porting_guide.txt' for detailed +porting description. + +The build target directory is "build//release/ble". + +Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Background: + Some of the comphy's parameters value depend on the HW connection between + the SoC and the PHY. Every board type has specific HW characteristics like + wire length. Due to those differences some comphy parameters vary between + board types. Therefore each board type can have its own list of values for + all relevant comphy parameters. The PHY porting layer specifies which + parameters need to be suited and the board designer should provide relevant + values. + + .. seealso:: + For XFI/SFI comphy type there is procedure "rx_training" which eases + process of suiting some of the parameters. Please see *uboot_cmd* + section: rx_training. + + The PHY porting layer simplifies updating static values per board type, + which are now grouped in one place. + + .. note:: + The parameters for the same type of comphy may vary even for the same + board type, it is because the lanes from comphy-x to some PHY may have + different HW characteristic than lanes from comphy-y to the same + (multiplexed) or other PHY. + +- Porting: + The porting layer for PHY was introduced in TF-A. There is one file + ``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the + defaults. Those default parameters are used only if there is no appropriate + phy-porting-layer.h file under: ``plat/marvell/armada///board/phy-porting-layer.h``. If the phy-porting-layer.h + exists, the phy-default-porting-layer.h is not going to be included. + + .. warning:: + Not all comphy types are already reworked to support the PHY porting + layer, currently the porting layer is supported for XFI/SFI and SATA + comphy types. + + The easiest way to prepare the PHY porting layer for custom board is to copy + existing example to a new platform: + + - cp ``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/armada///board/phy-porting-layer.h" + - adjust relevant parameters or + - if different comphy index is used for specific feature, move it to proper table entry and then adjust. + + .. note:: + The final table size with comphy parameters can be different, depending + on the CP module count for given SoC type. + +- Example: + Example porting layer for armada-8040-db is under: + ``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h`` + + .. note:: + If there is no PHY porting layer for new platform (missing + phy-porting-layer.h), the default values are used + (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is + warned: + + .. warning:: + "Using default comphy parameters - it may be required to suit them for + your board". diff --git a/docs/plat/marvell/build.rst b/docs/plat/marvell/build.rst deleted file mode 100644 index c10bcff79..000000000 --- a/docs/plat/marvell/build.rst +++ /dev/null @@ -1,253 +0,0 @@ -TF-A Build Instructions for Marvell Platforms -============================================= - -This section describes how to compile the Trusted Firmware-A (TF-A) project for Marvell's platforms. - -Build Instructions ------------------- -(1) Set the cross compiler - - .. code:: shell - - > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu- - -(2) Set path for FIP images: - -Set U-Boot image path (relatively to TF-A root or absolute path) - - .. code:: shell - - > export BL33=path/to/u-boot.bin - -For example: if U-Boot project (and its images) is located at ``~/project/u-boot``, -BL33 should be ``~/project/u-boot/u-boot.bin`` - - .. note:: - - *u-boot.bin* should be used and not *u-boot-spl.bin* - -Set MSS/SCP image path (mandatory only for Armada80x0) - - .. code:: shell - - > export SCP_BL2=path/to/mrvl_scp_bl2*.img - -(3) Armada-37x0 build requires WTP tools installation. - -See below in the section "Tools and external components installation". -Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3 - - .. code:: shell - - > sudo apt-get install gcc-arm-linux-gnueabi - -(4) Clean previous build residuals (if any) - - .. code:: shell - - > make distclean - -(5) Build TF-A - -There are several build options: - -- DEBUG - - Default is without debug information (=0). in order to enable it use ``DEBUG=1``. - Must be disabled when building UART recovery images due to current console driver - implementation that is not compatible with Xmodem protocol used for boot image download. - -- LOG_LEVEL - - Defines the level of logging which will be purged to the default output port. - - LOG_LEVEL_NONE 0 - LOG_LEVEL_ERROR 10 - LOG_LEVEL_NOTICE 20 - LOG_LEVEL_WARNING 30 - LOG_LEVEL_INFO 40 - LOG_LEVEL_VERBOSE 50 - -- USE_COHERENT_MEM - - This flag determines whether to include the coherent memory region in the - BL memory map or not. - -- LLC_ENABLE - - Flag defining the LLC (L3) cache state. The cache is enabled by default (``LLC_ENABLE=1``). - -- MARVELL_SECURE_BOOT - - Build trusted(=1)/non trusted(=0) image, default is non trusted. - -- BLE_PATH - - Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds. - The parameter is optional, its default value is ``plat/marvell/a8k/common/ble``. - -- MV_DDR_PATH - - For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0, - it is used for ddr_tool build. - - Usage example: MV_DDR_PATH=path/to/mv_ddr - - The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr - sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter - is necessary for A37x0. - - For the mv_ddr source location, check the section "Tools and external components installation" - -- DDR_TOPOLOGY - - For Armada37x0 only, the DDR topology map index/name, default is 0. - - Supported Options: - - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) - - DDR4 1CS (1): DB-88F3720-DDR4-Modular (512MB) - - DDR3 2CS (2): EspressoBIN V3-V5 (1GB) - - DDR4 2CS (3): DB-88F3720-DDR4-Modular (4GB) - - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB) - - DDR4 1CS (5): EspressoBin V7 (1GB) - - DDR4 2CS (6): EspressoBin V7 (2GB) - - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB - -- CLOCKSPRESET - - For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency, - default is CPU_800_DDR_800. - - - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz - - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz - - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz - - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz - -- BOOTDEV - - For Armada37x0 only, the flash boot device, default is ``SPINOR``. - - Currently, Armada37x0 only supports ``SPINOR``, ``SPINAND``, ``EMMCNORM`` and ``SATA``: - - - SPINOR - SPI NOR flash boot - - SPINAND - SPI NAND flash boot - - EMMCNORM - eMMC Download Mode - - Download boot loader or program code from eMMC flash into CM3 or CA53 - Requires full initialization and command sequence - - - SATA - SATA device boot - -- PARTNUM - - For Armada37x0 only, the boot partition number, default is 0. - - To boot from eMMC, the value should be aligned with the parameter in - U-Boot with name of ``CONFIG_SYS_MMC_ENV_PART``, whose value by default is - 1. For details about CONFIG_SYS_MMC_ENV_PART, please refer to the U-Boot - build instructions. - -- WTMI_IMG - - For Armada37x0 only, the path of the WTMI image can point to an image which - does nothing, an image which supports EFUSE or a customized CM3 firmware - binary. The default image is wtmi.bin that built from sources in WTP - folder, which is the next option. If the default image is OK, then this - option should be skipped. - -- WTP - - For Armada37x0 only, use this parameter to point to wtptools source code - directory, which can be found as a3700_utils.zip in the release. Usage - example: ``WTP=/path/to/a3700_utils`` - - For example, in order to build the image in debug mode with log level up to 'notice' level run - - .. code:: shell - - > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT= all fip - - And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level, - the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS, - the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command - line is as following - - .. code:: shell - - > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \ - MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip - - Supported MARVELL_PLATFORM are: - - a3700 (for both A3720 DB and EspressoBin) - - a70x0 - - a70x0_amc (for AMC board) - - a80x0 - - a80x0_mcbin (for MacciatoBin) - -Special Build Flags --------------------- - -- PLAT_RECOVERY_IMAGE_ENABLE - When set this option to enable secondary recovery function when build atf. - In order to build UART recovery image this operation should be disabled for - a70x0 and a80x0 because of hardware limitation (boot from secondary image - can interrupt UART recovery process). This MACRO definition is set in - ``plat/marvell/a8k/common/include/platform_def.h`` file. - -For more information about build options, please refer to the -:ref:`Build Options` document. - - -Build output ------------- -Marvell's TF-A compilation generates 7 files: - - - ble.bin - BLe image - - bl1.bin - BL1 image - - bl2.bin - BL2 image - - bl31.bin - BL31 image - - fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images) - - boot-image.bin - TF-A image (contains BL1 and FIP images) - - flash-image.bin - Image which contains boot-image.bin and SPL image. - Should be placed on the boot flash/device. - - -Tools and external components installation ------------------------------------------- - -Armada37x0 Builds require installation of 3 components -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -(1) ARM cross compiler capable of building images for the service CPU (CM3). - This component is usually included in the Linux host packages. - On Debian/Ubuntu hosts the default GNU ARM tool chain can be installed - using the following command - - .. code:: shell - - > sudo apt-get install gcc-arm-linux-gnueabi - - Only if required, the default tool chain prefix ``arm-linux-gnueabi-`` can be - overwritten using the environment variable ``CROSS_CM3``. - Example for BASH shell - - .. code:: shell - - > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi - -(2) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv_ddr-armada-atf-mainline" branch): - - https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git - -(3) Armada3700 tools available at the following repository (use the latest release branch): - - https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git - -Armada70x0 and Armada80x0 Builds require installation of an additional component -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -(1) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv_ddr-armada-atf-mainline" branch): - - https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git diff --git a/docs/plat/marvell/index.rst b/docs/plat/marvell/index.rst index 89ebdc0a4..0d33432ba 100644 --- a/docs/plat/marvell/index.rst +++ b/docs/plat/marvell/index.rst @@ -5,10 +5,10 @@ Marvell :maxdepth: 1 :caption: Contents - build - porting - misc/mvebu-a8k-addr-map - misc/mvebu-amb - misc/mvebu-ccu - misc/mvebu-io-win - misc/mvebu-iob + armada/build + armada/porting + armada/misc/mvebu-a8k-addr-map + armada/misc/mvebu-amb + armada/misc/mvebu-ccu + armada/misc/mvebu-io-win + armada/misc/mvebu-iob diff --git a/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst b/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst deleted file mode 100644 index e88a4582b..000000000 --- a/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst +++ /dev/null @@ -1,49 +0,0 @@ -Address decoding flow and address translation units of Marvell Armada 8K SoC family -=================================================================================== - -:: - - +--------------------------------------------------------------------------------------------------+ - | +-------------+ +--------------+ | - | | Memory +----- DRAM CS | | - |+------------+ +-----------+ +-----------+ | Controller | +--------------+ | - || AP DMA | | | | | +-------------+ | - || SD/eMMC | | CA72 CPUs | | AP MSS | +-------------+ | - || MCI-0/1 | | | | | | Memory | | - |+------+-----+ +--+--------+ +--------+--+ +------------+ | Controller | +-------------+ | - | | | | | +----- Translaton | |AP | | - | | | | | | +-------------+ |Configuration| | - | | | +-----+ +-------------------------Space | | - | | | +-------------+ | CCU | +-------------+ | - | | | | MMU +---------+ Windows | +-----------+ +-------------+ | - | | +-| translation | | Lookup +---- +--------- AP SPI | | - | | +-------------+ | | | | +-------------+ | - | | +-------------+ | | | IO | +-------------+ | - | +------------| SMMU +---------+ | | Windows +--------- AP MCI0/1 | | - | | translation | +------------+ | Lookup | +-------------+ | - | +---------+---+ | | +-------------+ | - | - | | +--------- AP STM | | - | +----------------- | | +-------------+ | - | AP | | +-+---------+ | - +---------------------------------------------------------------|----------------------------------+ - +-------------|-------------------------------------------------|----------------------------------+ - | CP | +-------------+ +------+-----+ +-------------------+ | - | | | | | +------- SB CFG Space | | - | | | DIOB | | | +-------------------+ | - | | | Windows ----------------- IOB | +-------------------+ | - | | | Control | | Windows +------| SB PCIe-0 - PCIe2 | | - | | | | | Lookup | +-------------------+ | - | | +------+------+ | | +-------------------+ | - | | | | +------+ SB NAND | | - | | | +------+-----+ +-------------------+ | - | | | | | - | | | | | - | +------------------+ +------------+ +------+-----+ +-------------------+ | - | | Network Engine | | | | +------- SB SPI-0/SPI-1 | | - | | Security Engine | | PCIe, MSS | | RUNIT | +-------------------+ | - | | SATA, USB | | DMA | | Windows | +-------------------+ | - | | SD/eMMC | | | | Lookup +------- SB Device Bus | | - | | TDM, I2C | | | | | +-------------------+ | - | +------------------+ +------------+ +------------+ | - | | - +--------------------------------------------------------------------------------------------------+ diff --git a/docs/plat/marvell/misc/mvebu-amb.rst b/docs/plat/marvell/misc/mvebu-amb.rst deleted file mode 100644 index d734003d6..000000000 --- a/docs/plat/marvell/misc/mvebu-amb.rst +++ /dev/null @@ -1,58 +0,0 @@ -AMB - AXI MBUS address decoding -=============================== - -AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs. - -The Runit offers a second level of address windows lookup. It is used to map -transaction towards the CD BootROM, SPI0, SPI1 and Device bus (NOR). - -The Runit contains eight configurable windows. Each window defines a contiguous, -address space and the properties associated with that address space. - -:: - - Unit Bank ATTR - Device-Bus DEV_BOOT_CS 0x2F - DEV_CS0 0x3E - DEV_CS1 0x3D - DEV_CS2 0x3B - DEV_CS3 0x37 - SPI-0 SPI_A_CS0 0x1E - SPI_A_CS1 0x5E - SPI_A_CS2 0x9E - SPI_A_CS3 0xDE - SPI_A_CS4 0x1F - SPI_A_CS5 0x5F - SPI_A_CS6 0x9F - SPI_A_CS7 0xDF - SPI SPI_B_CS0 0x1A - SPI_B_CS1 0x5A - SPI_B_CS2 0x9A - SPI_B_CS3 0xDA - BOOT_ROM BOOT_ROM 0x1D - UART UART 0x01 - -Mandatory functions -------------------- - -- marvell_get_amb_memory_map - Returns the AMB windows configuration and the number of windows - -Mandatory structures --------------------- - -- amb_memory_map - Array that include the configuration of the windows. Every window/entry is a - struct which has 2 parameters: - - - Base address of the window - - Attribute of the window - -Examples --------- - -.. code:: c - - struct addr_map_win amb_memory_map[] = { - {0xf900, AMB_DEV_CS0_ID}, - }; diff --git a/docs/plat/marvell/misc/mvebu-ccu.rst b/docs/plat/marvell/misc/mvebu-ccu.rst deleted file mode 100644 index 5bac11faf..000000000 --- a/docs/plat/marvell/misc/mvebu-ccu.rst +++ /dev/null @@ -1,33 +0,0 @@ -Marvell CCU address decoding bindings -===================================== - -CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs. - -The CCU node includes a description of the address decoding configuration. - -Mandatory functions -------------------- - -- marvell_get_ccu_memory_map - Return the CCU windows configuration and the number of windows of the - specific AP. - -Mandatory structures --------------------- - -- ccu_memory_map - Array that includes the configuration of the windows. Every window/entry is - a struct which has 3 parameters: - - - Base address of the window - - Size of the window - - Target-ID of the window - -Example -------- - -.. code:: c - - struct addr_map_win ccu_memory_map[] = { - {0x00000000f2000000, 0x00000000e000000, IO_0_TID}, /* IO window */ - }; diff --git a/docs/plat/marvell/misc/mvebu-io-win.rst b/docs/plat/marvell/misc/mvebu-io-win.rst deleted file mode 100644 index 52845ca02..000000000 --- a/docs/plat/marvell/misc/mvebu-io-win.rst +++ /dev/null @@ -1,46 +0,0 @@ -Marvell IO WIN address decoding bindings -======================================== - -IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. - -The IO WIN includes a description of the address decoding configuration. - -Transactions that are decoded by CCU windows as IO peripheral, have an additional -layer of decoding. This additional address decoding layer defines one of the -following targets: - -- **0x0** = BootRom -- **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream) -- **0x2** = SPI direct access -- **0x3** = PCIe registers -- **0x4** = MCI Port -- **0x5** = PCIe port - -Mandatory functions -------------------- - -- marvell_get_io_win_memory_map - Returns the IO windows configuration and the number of windows of the - specific AP. - -Mandatory structures --------------------- - -- io_win_memory_map - Array that include the configuration of the windows. Every window/entry is - a struct which has 3 parameters: - - - Base address of the window - - Size of the window - - Target-ID of the window - -Example -------- - -.. code:: c - - struct addr_map_win io_win_memory_map[] = { - {0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/ - {0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/ - {0x00000000f6000000, 0x000000000100000, MCIPHY_TID}, /* MCI window 1Mb for PHY-reg*/ - }; diff --git a/docs/plat/marvell/misc/mvebu-iob.rst b/docs/plat/marvell/misc/mvebu-iob.rst deleted file mode 100644 index d02a7e84c..000000000 --- a/docs/plat/marvell/misc/mvebu-iob.rst +++ /dev/null @@ -1,52 +0,0 @@ -Marvell IOB address decoding bindings -===================================== - -IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs. - -The IOB includes a description of the address decoding configuration. - -IOB supports up to n (in CP110 n=24) windows for external memory transaction. -When a transaction passes through the IOB, its address is compared to each of -the enabled windows. If there is a hit and it passes the security checks, it is -advanced to the target port. - -Mandatory functions -------------------- - -- marvell_get_iob_memory_map - Returns the IOB windows configuration and the number of windows - -Mandatory structures --------------------- - -- iob_memory_map - Array that includes the configuration of the windows. Every window/entry is - a struct which has 3 parameters: - - - Base address of the window - - Size of the window - - Target-ID of the window - -Target ID options ------------------ - -- **0x0** = Internal configuration space -- **0x1** = MCI0 -- **0x2** = PEX1_X1 -- **0x3** = PEX2_X1 -- **0x4** = PEX0_X4 -- **0x5** = NAND flash -- **0x6** = RUNIT (NOR/SPI/BootRoom) -- **0x7** = MCI1 - -Example -------- - -.. code:: c - - struct addr_map_win iob_memory_map[] = { - {0x00000000f7000000, 0x0000000001000000, PEX1_TID}, /* PEX1_X1 window */ - {0x00000000f8000000, 0x0000000001000000, PEX2_TID}, /* PEX2_X1 window */ - {0x00000000f6000000, 0x0000000001000000, PEX0_TID}, /* PEX0_X4 window */ - {0x00000000f9000000, 0x0000000001000000, NAND_TID} /* NAND window */ - }; diff --git a/docs/plat/marvell/porting.rst b/docs/plat/marvell/porting.rst deleted file mode 100644 index 0a71dbd54..000000000 --- a/docs/plat/marvell/porting.rst +++ /dev/null @@ -1,163 +0,0 @@ -TF-A Porting Guide for Marvell Platforms -======================================== - -This section describes how to port TF-A to a customer board, assuming that the -SoC being used is already supported in TF-A. - - -Source Code Structure ---------------------- - -- The customer platform specific code shall reside under ``plat/marvell//_cust`` - (e.g. 'plat/marvell/a8k/a7040_cust'). -- The platform name for build purposes is called ``_cust`` (e.g. ``a7040_cust``). -- The build system will reuse all files from within the soc directory, and take only the porting - files from the customer platform directory. - -Files that require porting are located at ``plat/marvell//_cust`` directory. - - -Armada-70x0/Armada-80x0 Porting -------------------------------- - -SoC Physical Address Map (marvell_plat_config.c) -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -This file describes the SoC physical memory mapping to be used for the CCU, -IOWIN, AXI-MBUS and IOB address decode units (Refer to the functional spec for -more details). - -In most cases, using the default address decode windows should work OK. - -In cases where a special physical address map is needed (e.g. Special size for -PCIe MEM windows, large memory mapped SPI flash...), then porting of the SoC -memory map is required. - -.. note:: - For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please - refer to the SoC functional spec, and under - ``docs/marvell/misc/mvebu-[ccu/iob/amb/io-win].txt`` files. - -boot loader recovery (marvell_plat_config.c) -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -- Background: - - Boot rom can skip the current image and choose to boot from next position if a - specific value (``0xDEADB002``) is returned by the ble main function. This - feature is used for boot loader recovery by booting from a valid flash-image - saved in next position on flash (e.g. address 2M in SPI flash). - - Supported options to implement the skip request are: - - GPIO - - I2C - - User defined - -- Porting: - - Under marvell_plat_config.c, implement struct skip_image that includes - specific board parameters. - - .. warning:: - To disable this feature make sure the struct skip_image is not implemented. - -- Example: - -In A7040-DB specific implementation -(``plat/marvell/a8k/a70x0/board/marvell_plat_config.c``), the image skip is -implemented using GPIO: mpp 33 (SW5). - -Before resetting the board make sure there is a valid image on the next flash -address: - - -tftp [valid address] flash-image.bin - -sf update [valid address] 0x2000000 [size] - -Press reset and keep pressing the button connected to the chosen GPIO pin. A -skip image request message is printed on the screen and boot rom boots from the -saved image at the next position. - -DDR Porting (dram_port.c) -~~~~~~~~~~~~~~~~~~~~~~~~~ - -This file defines the dram topology and parameters of the target board. - -The DDR code is part of the BLE component, which is an extension of ARM Trusted -Firmware (TF-A). - -The DDR driver called mv_ddr is released separately apart from TF-A sources. - -The BLE and consequently, the DDR init code is executed at the early stage of -the boot process. - -Each supported platform of the TF-A has its own DDR porting file called -dram_port.c located at ``atf/plat/marvell/a8k//board`` directory. - -Please refer to '/doc/porting_guide.txt' for detailed -porting description. - -The build target directory is "build//release/ble". - -Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h) -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -- Background: - Some of the comphy's parameters value depend on the HW connection between - the SoC and the PHY. Every board type has specific HW characteristics like - wire length. Due to those differences some comphy parameters vary between - board types. Therefore each board type can have its own list of values for - all relevant comphy parameters. The PHY porting layer specifies which - parameters need to be suited and the board designer should provide relevant - values. - - .. seealso:: - For XFI/SFI comphy type there is procedure "rx_training" which eases - process of suiting some of the parameters. Please see *uboot_cmd* - section: rx_training. - - The PHY porting layer simplifies updating static values per board type, - which are now grouped in one place. - - .. note:: - The parameters for the same type of comphy may vary even for the same - board type, it is because the lanes from comphy-x to some PHY may have - different HW characteristic than lanes from comphy-y to the same - (multiplexed) or other PHY. - -- Porting: - The porting layer for PHY was introduced in TF-A. There is one file - ``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the - defaults. Those default parameters are used only if there is no appropriate - phy-porting-layer.h file under: ``plat/marvell///board/phy-porting-layer.h``. If the phy-porting-layer.h - exists, the phy-default-porting-layer.h is not going to be included. - - .. warning:: - Not all comphy types are already reworked to support the PHY porting - layer, currently the porting layer is supported for XFI/SFI and SATA - comphy types. - - The easiest way to prepare the PHY porting layer for custom board is to copy - existing example to a new platform: - - - cp ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell///board/phy-porting-layer.h" - - adjust relevant parameters or - - if different comphy index is used for specific feature, move it to proper table entry and then adjust. - - .. note:: - The final table size with comphy parameters can be different, depending - on the CP module count for given SoC type. - -- Example: - Example porting layer for armada-8040-db is under: - ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` - - .. note:: - If there is no PHY porting layer for new platform (missing - phy-porting-layer.h), the default values are used - (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is - warned: - - .. warning:: - "Using default comphy parameters - it may be required to suit them for - your board". -- cgit v1.2.3 From 57adbf37e6177eab79277ce5406a9bbde930ee3c Mon Sep 17 00:00:00 2001 From: Alex Leibovich Date: Mon, 25 Feb 2019 12:24:29 +0200 Subject: ddr: a80x0: add DDR 32-bit mode support This commit introduces 32-bit DDR topology map initialization. For that purpose a new DDR32 build flag is added, with according documentation update. Change-Id: I169ff358c2923afd984e27bc126dc551dcaefc01 Signed-off-by: Alex Leibovich --- docs/plat/marvell/armada/build.rst | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 1b60fc554..6f28721d5 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -194,6 +194,10 @@ Special Build Flags can interrupt UART recovery process). This MACRO definition is set in ``plat/marvell/armada/a8k/common/include/platform_def.h`` file. +- DDR32 + In order to work in 32bit DDR, instead of the default 64bit ECC DDR, + this flag should be set to 1. + For more information about build options, please refer to the :ref:`Build Options` document. -- cgit v1.2.3 From b4ad365a4642fb8b2ecb1df73dd69ee4caf58bd2 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 25 Mar 2020 15:50:38 +0000 Subject: GICv3: GIC-600: Detect GIC-600 at runtime The only difference between GIC-500 and GIC-600 relevant to TF-A is the differing power management sequence. A certain GIC implementation is detectable at runtime, for instance by checking the IIDR register. Let's add that test before initiating the GIC-600 specific sequence, so the code can be used on both GIC-600 and GIC-500 chips alike, without deciding on a GIC chip at compile time. This means that the GIC-500 "driver" is now redundant. To allow minimal platform support, add a switch to disable GIC-600 support. Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557 Signed-off-by: Andre Przywara --- docs/plat/arm/fvp/index.rst | 1 - 1 file changed, 1 deletion(-) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index eb7eb0054..f23ec2804 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -116,7 +116,6 @@ Arm FVP Platform Specific Build Options - ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: - - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected - ``FVP_GICV2`` : The GICv2 only driver is selected - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) -- cgit v1.2.3 From 5a40d70f067b6238159142755e4e5cb27e292045 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Sun, 31 Mar 2019 16:58:11 +0300 Subject: drivers: marvell: add support for mapping the entire LLC to SRAM Add llc_sram_enable() and llc_sram_disable() APIs to Marvell cache_lls driver. Add LLC_SRAM definition to Marvell common makefile - disabled by the default. Add description of LLC_SRAM flag to the build documentation. Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182 Signed-off-by: Konstantin Porotchkin --- docs/plat/marvell/armada/build.rst | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 6f28721d5..bec0bcbd4 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -77,6 +77,13 @@ There are several build options: Flag defining the LLC (L3) cache state. The cache is enabled by default (``LLC_ENABLE=1``). +- LLC_SRAM + + Flag defining the LLC (L3) cache SRAM support. The feature is + disabled by default (``LLC_ENABLE=0``). + When LLC SRAM is enabled, the secure payload (BL32) is loaded into this + SRAM area instead of the DRAM. + - MARVELL_SECURE_BOOT Build trusted(=1)/non trusted(=0) image, default is non trusted. -- cgit v1.2.3 From 0396bcbc6ae75a71489c078ae43f6f549abd5be4 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Wed, 1 Jul 2020 13:53:07 +0200 Subject: doc: Fix some broken links Fix all external broken links reported by Sphinx linkcheck tool. This does not take care of broken cross-references between internal TF-A documentation files. These will be fixed in a future patch. Change-Id: I2a740a3ec0b688c14aad575a6c2ac71e72ce051e Signed-off-by: Sandrine Bailleux --- docs/plat/allwinner.rst | 2 +- docs/plat/meson-axg.rst | 2 +- docs/plat/meson-g12a.rst | 4 ++-- docs/plat/meson-gxl.rst | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/allwinner.rst b/docs/plat/allwinner.rst index a1e06590a..d82380ddf 100644 --- a/docs/plat/allwinner.rst +++ b/docs/plat/allwinner.rst @@ -34,7 +34,7 @@ To build for machines with an H6 SoC: make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31 -.. _U-Boot documentation: http://git.denx.de/?p=u-boot.git;f=board/sunxi/README.sunxi64;hb=HEAD +.. _U-Boot documentation: https://gitlab.denx.de/u-boot/u-boot/-/blob/master/board/sunxi/README.sunxi64 Trusted OS dispatcher --------------------- diff --git a/docs/plat/meson-axg.rst b/docs/plat/meson-axg.rst index 1e4b2c207..6f6732e95 100644 --- a/docs/plat/meson-axg.rst +++ b/docs/plat/meson-axg.rst @@ -24,4 +24,4 @@ This port has been tested on a A113D board. After building it, follow the instructions in the `U-Boot repository`_, replacing the mentioned **bl31.img** by the one built from this port. -.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/board/amlogic/s400/README +.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/doc/board/amlogic/s400.rst diff --git a/docs/plat/meson-g12a.rst b/docs/plat/meson-g12a.rst index 7cd1bf746..9588ec498 100644 --- a/docs/plat/meson-g12a.rst +++ b/docs/plat/meson-g12a.rst @@ -20,8 +20,8 @@ In order to build it: CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=g12a This port has been tested on a SEI510 board. After building it, follow the -instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the +instructions in the `gxlimg repository`_ or `U-Boot repository`_, replacing the mentioned **bl31.img** by the one built from this port. .. _gxlimg repository: https://github.com/repk/gxlimg/blob/master/README.g12a -.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/board/amlogic/sei510/README +.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/doc/board/amlogic/sei510.rst diff --git a/docs/plat/meson-gxl.rst b/docs/plat/meson-gxl.rst index c6d850446..0751f1d00 100644 --- a/docs/plat/meson-gxl.rst +++ b/docs/plat/meson-gxl.rst @@ -20,8 +20,8 @@ In order to build it: CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxl This port has been tested on a Lepotato. After building it, follow the -instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the +instructions in the `gxlimg repository`_ or `U-Boot repository`_, replacing the mentioned **bl31.img** by the one built from this port. .. _gxlimg repository: https://github.com/repk/gxlimg/blob/master/README -.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/board/amlogic/p212/README.libretech-cc +.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/doc/board/amlogic/p212.rst -- cgit v1.2.3 From a66f0309e5ac56c8223414542874a657768eec03 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 4 Jul 2020 16:12:55 +0900 Subject: docs: qemu: add build instructions for QEMU_EFI.fd and rootfs.cpio.gz This commit solves the limitation, "No build instructions for QEMU_EFI.fd and rootfs-arm64.cpio.gz" Document the steps to build them. Change-Id: Ic6d895617cf71fe969f4aa9820dad25cc6182023 Signed-off-by: Masahiro Yamada --- docs/plat/qemu.rst | 43 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 4 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/qemu.rst b/docs/plat/qemu.rst index afa32c11b..368300d86 100644 --- a/docs/plat/qemu.rst +++ b/docs/plat/qemu.rst @@ -20,11 +20,46 @@ provided as it's generated by QEMU. Current limitations: - Only cold boot is supported -- No build instructions for QEMU\_EFI.fd and rootfs-arm64.cpio.gz -``QEMU_EFI.fd`` can be dowloaded from +Getting non-TF images +--------------------- + +``QEMU_EFI.fd`` can be downloaded from http://snapshots.linaro.org/components/kernel/leg-virt-tianocore-edk2-upstream/latest/QEMU-KERNEL-AARCH64/RELEASE_GCC5/QEMU_EFI.fd +or, can be built as follows: + +.. code:: shell + + git clone https://github.com/tianocore/edk2.git + cd edk2 + git submodule update --init + make -C BaseTools + source edksetup.sh + export GCC5_AARCH64_PREFIX=aarch64-linux-gnu- + build -a AARCH64 -t GCC5 -p ArmVirtPkg/ArmVirtQemuKernel.dsc + +```` + +Then, you will get ``Build/ArmVirtQemuKernel-AARCH64/DEBUG_GCC5/FV/QEMU_EFI.fd`` + +Please note you do not need to use GCC 5 in spite of the environment variable +``GCC5_AARCH64_PREFIX`` + +The rootfs can be built by using Buildroot as follows: + +.. code:: shell + + git clone git://git.buildroot.net/buildroot.git + cd buildroot + make qemu_aarch64_virt_defconfig + utils/config -e BR2_TARGET_ROOTFS_CPIO + utils/config -e BR2_TARGET_ROOTFS_CPIO_GZIP + make olddefconfig + make + +Then, you will get ``output/images/rootfs.cpio.gz``. + Booting via semi-hosting option ------------------------------- @@ -50,7 +85,7 @@ To start (QEMU v4.1.0): qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57 \ -kernel Image \ -append "console=ttyAMA0,38400 keep_bootcon root=/dev/vda2" \ - -initrd rootfs-arm64.cpio.gz -smp 2 -m 1024 -bios bl1.bin \ + -initrd rootfs.cpio.gz -smp 2 -m 1024 -bios bl1.bin \ -d unimp -semihosting-config enable,target=native Booting via flash based firmwares @@ -99,5 +134,5 @@ To start (QEMU v2.6.0): qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57 \ -kernel Image -no-acpi \ -append 'console=ttyAMA0,38400 keep_bootcon root=/dev/vda2' \ - -initrd rootfs-arm64.cpio.gz -smp 2 -m 1024 -bios flash.bin \ + -initrd rootfs.cpio.gz -smp 2 -m 1024 -bios flash.bin \ -d unimp -- cgit v1.2.3 From 624120e05c7a864b90848c7a31c881f2b98c5b74 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 4 Jul 2020 17:10:25 +0900 Subject: docs: qemu: remove unneeded root=/dev/vda2 kernel parameter In my understanding, /dev/vda2 does not exist unless you add virtio drive to the qemu command line. The rootfs is already specified by '-initrd rootfs.cpio.gz'. Change-Id: Ifdca5d4f3819d87ef7e8a08ed870872d24b86370 Signed-off-by: Masahiro Yamada --- docs/plat/qemu.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/qemu.rst b/docs/plat/qemu.rst index 368300d86..3f79d76eb 100644 --- a/docs/plat/qemu.rst +++ b/docs/plat/qemu.rst @@ -84,7 +84,7 @@ To start (QEMU v4.1.0): qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57 \ -kernel Image \ - -append "console=ttyAMA0,38400 keep_bootcon root=/dev/vda2" \ + -append "console=ttyAMA0,38400 keep_bootcon" \ -initrd rootfs.cpio.gz -smp 2 -m 1024 -bios bl1.bin \ -d unimp -semihosting-config enable,target=native @@ -133,6 +133,6 @@ To start (QEMU v2.6.0): qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57 \ -kernel Image -no-acpi \ - -append 'console=ttyAMA0,38400 keep_bootcon root=/dev/vda2' \ + -append 'console=ttyAMA0,38400 keep_bootcon' \ -initrd rootfs.cpio.gz -smp 2 -m 1024 -bios flash.bin \ -d unimp -- cgit v1.2.3 From 231d0b351d42266da9814d025f1a0b7c6a856bb3 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 4 Jul 2020 17:15:44 +0900 Subject: docs: qemu: bump to QEMU 5.0.0 Fix the version inconsistency in the same file. I tested QEMU 5.0.0, and it worked for me. Change-Id: I9d8ca9aae1e413410eb5676927e13ae4aee9fad8 Signed-off-by: Masahiro Yamada --- docs/plat/qemu.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/qemu.rst b/docs/plat/qemu.rst index 3f79d76eb..66b82473c 100644 --- a/docs/plat/qemu.rst +++ b/docs/plat/qemu.rst @@ -78,7 +78,7 @@ To build: make CROSS_COMPILE=aarch64-none-elf- PLAT=qemu -To start (QEMU v4.1.0): +To start (QEMU v5.0.0): .. code:: shell @@ -127,7 +127,7 @@ To build flash.bin: dd if=build/qemu/release/bl1.bin of=flash.bin bs=4096 conv=notrunc dd if=build/qemu/release/fip.bin of=flash.bin seek=64 bs=4096 conv=notrunc -To start (QEMU v2.6.0): +To start (QEMU v5.0.0): .. code:: shell -- cgit v1.2.3 From a775ef25c3127ae9175f48aa0092432c08e6fab6 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Wed, 3 Jun 2020 14:28:45 +0800 Subject: plat: imx8mp: Add the basic support for i.MX8MP The i.MX 8MP Media Applications Processor is part of the growing i.MX8M family targeting the consumer and industrial market. It brings an effective Machine Learning and AI accelerator that enables a new class of applications. It is built in 14LPP to achieve both high performance and low power consumption and relies on a powerful fully coherent core complex based on a quad core Arm Cortex-A53 cluster and Cortex-M7 low-power coprocessor, audio digital signal processor, machine learning and graphics accelerators. Signed-off-by: Jacky Bai Change-Id: I98311ebc32bee20af05031492e9fc24d06e55f4a --- docs/plat/imx8m.rst | 1 + 1 file changed, 1 insertion(+) (limited to 'docs/plat') diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst index ba087a2a3..f184b6990 100644 --- a/docs/plat/imx8m.rst +++ b/docs/plat/imx8m.rst @@ -33,6 +33,7 @@ Build Procedure Target_SoC should be "imx8mq" for i.MX8MQ SoC. Target_SoC should be "imx8mm" for i.MX8MM SoC. Target_SoC should be "imx8mn" for i.MX8MN SoC. + Target_SoC should be "imx8mp" for i.MX8MP SoC. Deploy TF-A Images ~~~~~~~~~~~~~~~~~~ -- cgit v1.2.3 From 0a977b9b8bfc0356830d88e3602e2e5ef4a1ac06 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Mon, 15 Apr 2019 16:32:59 +0300 Subject: plat: marvell: armada: a8k: change CCU LLC SRAM mapping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage. The CCU have to prepare SRAM window, but point to the DRAM-0 target until the SRAM is actually enabled. This patch changes CCU SRAM window target to DRAM-0 Remove dependence between LLC_SRAM and LLC_ENABLE and update the build documentation. The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000) Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456 Signed-off-by: Konstantin Porotchkin --- docs/plat/marvell/armada/build.rst | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index bec0bcbd4..da4ba565a 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -79,10 +79,12 @@ There are several build options: - LLC_SRAM - Flag defining the LLC (L3) cache SRAM support. The feature is - disabled by default (``LLC_ENABLE=0``). - When LLC SRAM is enabled, the secure payload (BL32) is loaded into this - SRAM area instead of the DRAM. + Flag enabling the LLC (L3) cache SRAM support. The LLC SRAM is activated and used + by Trusted OS (OP-TEE OS, BL32). The TF-A only prepares CCU address translation windows + for SRAM address range at BL31 execution stage with window target set to DRAM-0. + When Trusted OS activates LLC SRAM, the CCU window target is changed to SRAM. + There is no reason to enable this feature if OP-TEE OS built with CFG_WITH_PAGER=n. + Only set LLC_SRAM=1 if OP-TEE OS is built with CFG_WITH_PAGER=y. - MARVELL_SECURE_BOOT -- cgit v1.2.3 From 91879af72e9c9dc17bd6b1db630d31d80f89109b Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Mon, 20 Jul 2020 13:26:49 +0100 Subject: FVP Doc: Update list of supported FVP platforms This patch adds the following models FVP_Base_Neoverse-E1x1 FVP_Base_Neoverse-E1x2 FVP_Base_Neoverse-E1x4 to the list of supported FVP platforms. Change-Id: Ib526a2a735f17724af3a874b06bf69b4ca85d0dd Signed-off-by: Alexei Fedorov --- docs/plat/arm/fvp/index.rst | 3 +++ 1 file changed, 3 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index f23ec2804..a6ff19a25 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -37,6 +37,9 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores - ``FVP_Base_Cortex-A76AEx4`` - ``FVP_Base_Cortex-A76AEx8`` - ``FVP_Base_Cortex-A77x4`` +- ``FVP_Base_Neoverse-E1x1`` +- ``FVP_Base_Neoverse-E1x2`` +- ``FVP_Base_Neoverse-E1x4`` - ``FVP_Base_Neoverse-N1x4`` - ``FVP_Base_Zeusx4`` - ``FVP_CSS_SGI-575`` (Version 11.10 build 25) -- cgit v1.2.3 From e09559fd7d1eabe78863849e113b389f79728858 Mon Sep 17 00:00:00 2001 From: Vijayenthiran Subramaniam Date: Wed, 22 Jul 2020 22:08:28 +0530 Subject: docs/fvp: update SGI and RD FVP list Update SGI-575, RD-E1-Edge and RD-N1-Edge FVP versions to 11.10/36 and add RD-N1-Edge-Dual to the list of supported Arm Fixed Virtual Platforms. Change-Id: I9e7e5662324eeefc80d799ca5341b5bc4dc39cbb Signed-off-by: Vijayenthiran Subramaniam --- docs/plat/arm/fvp/index.rst | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index a6ff19a25..fd658bbff 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -42,10 +42,11 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores - ``FVP_Base_Neoverse-E1x4`` - ``FVP_Base_Neoverse-N1x4`` - ``FVP_Base_Zeusx4`` -- ``FVP_CSS_SGI-575`` (Version 11.10 build 25) +- ``FVP_CSS_SGI-575`` (Version 11.10 build 36) - ``FVP_CSS_SGM-775`` -- ``FVP_RD_E1Edge`` -- ``FVP_RD_N1Edge`` (Version 11.10 build 25) +- ``FVP_RD_E1_edge`` (Version 11.10 build 36) +- ``FVP_RD_N1_edge`` (Version 11.10 build 36) +- ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36) - ``Foundation_Platform`` The latest version of the AArch32 build of TF-A has been tested on the -- cgit v1.2.3 From eed02440afd123689b44fb2da657a2b7e1f4a33d Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Tue, 19 Feb 2019 10:40:33 +0200 Subject: docs: marvell: update build instructions with CN913x Add references to the OcteonTX2 CN913x family. Change-Id: I172a8e3d061086bf4843acad014c113c80359e01 Signed-off-by: Konstantin Porotchkin --- docs/plat/marvell/armada/build.rst | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index da4ba565a..6b9054c7c 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -26,7 +26,7 @@ BL33 should be ``~/project/u-boot/u-boot.bin`` *u-boot.bin* should be used and not *u-boot-spl.bin* -Set MSS/SCP image path (mandatory only for Armada80x0) +Set MSS/SCP image path (mandatory only for A7K/8K/CN913x) .. code:: shell @@ -92,22 +92,31 @@ There are several build options: - BLE_PATH - Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds. + Points to BLE (Binary ROM extension) sources folder. + Only required for A7K/8K/CN913x builds. The parameter is optional, its default value is ``plat/marvell/armada/a8k/common/ble``. - MV_DDR_PATH - For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0, + For A7K/8K/CN913x, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0, it is used for ddr_tool build. Usage example: MV_DDR_PATH=path/to/mv_ddr - The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr + The parameter is optional for A7K/8K/CN913x, when this parameter is not set, the mv_ddr sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter is necessary for A37x0. For the mv_ddr source location, check the section "Tools and external components installation" +- CP_NUM + + Total amount of CPs (South Bridge) connected to AP. When the parameter is omitted, + the build uses the default number of CPs, which is a number of embedded CPs inside the + package: 1 or 2 depending on the SoC used. The parameter is valid for OcteonTX2 CN913x SoC + family (PLAT=t9130), which can have external CPs connected to the MCI ports. Valid + values with CP_NUM are in a range of 1 to 3. + - DDR_TOPOLOGY For Armada37x0 only, the DDR topology map index/name, default is 0. @@ -191,7 +200,8 @@ There are several build options: - a70x0 - a70x0_amc (for AMC board) - a80x0 - - a80x0_mcbin (for MacciatoBin) + - a80x0_mcbin (for MacchiatoBin) + - t9130 (OcteonTX2 CN913x) Special Build Flags -------------------- @@ -199,7 +209,7 @@ Special Build Flags - PLAT_RECOVERY_IMAGE_ENABLE When set this option to enable secondary recovery function when build atf. In order to build UART recovery image this operation should be disabled for - a70x0 and a80x0 because of hardware limitation (boot from secondary image + A7K/8K/CN913x because of hardware limitation (boot from secondary image can interrupt UART recovery process). This MACRO definition is set in ``plat/marvell/armada/a8k/common/include/platform_def.h`` file. -- cgit v1.2.3 From 663f6bcfe8ebb041f57674655deaeba6368bb025 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Mon, 10 Dec 2018 12:01:29 +0100 Subject: docs: marvell: update path in marvell documentation Change-Id: I0cebbaa900aa518700f13cbf02f8a97e0c76b21c Signed-off-by: Grzegorz Jaszczyk --- docs/plat/marvell/armada/porting.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/porting.rst b/docs/plat/marvell/armada/porting.rst index 1723ebb57..e3fc9ba73 100644 --- a/docs/plat/marvell/armada/porting.rst +++ b/docs/plat/marvell/armada/porting.rst @@ -36,7 +36,7 @@ memory map is required. .. note:: For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please refer to the SoC functional spec, and under - ``docs/marvell/misc/mvebu-[ccu/iob/amb/io-win].txt`` files. + ``docs/plat/marvell/armada/misc/mvebu-[ccu/iob/amb/io-win].rst`` files. boot loader recovery (marvell_plat_config.c) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- cgit v1.2.3 From 3045dfe10c3daaf3eb93f22090e62e062b19b981 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Fri, 22 Mar 2019 11:38:56 +0100 Subject: docs: marvell: update PHY porting layer description The purpose of rx_training had changed after last update. Currently it is not supposed to help with providing static parameters for porting layer. Instead, it aims to suit the parameters per connection. Change-Id: I2a146b71e2e20bd264c090a9a627d0b6bc56e052 Signed-off-by: Grzegorz Jaszczyk --- docs/plat/marvell/armada/porting.rst | 5 ----- 1 file changed, 5 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/porting.rst b/docs/plat/marvell/armada/porting.rst index e3fc9ba73..ba8736dc6 100644 --- a/docs/plat/marvell/armada/porting.rst +++ b/docs/plat/marvell/armada/porting.rst @@ -110,11 +110,6 @@ Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h) parameters need to be suited and the board designer should provide relevant values. - .. seealso:: - For XFI/SFI comphy type there is procedure "rx_training" which eases - process of suiting some of the parameters. Please see *uboot_cmd* - section: rx_training. - The PHY porting layer simplifies updating static values per board type, which are now grouped in one place. -- cgit v1.2.3 From db1ef41a78235fe228bbe28fb298ad4e3f9d644d Mon Sep 17 00:00:00 2001 From: Olivier Deprez Date: Wed, 1 Apr 2020 21:28:26 +0200 Subject: SPM: build OP-TEE as an S-EL1 Secure Partition Provide manifest and build options to boot OP-TEE as a guest S-EL1 Secure Partition on top of Hafnium in S-EL2. Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image. Signed-off-by: Olivier Deprez Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb --- docs/plat/arm/arm-build-options.rst | 3 +++ 1 file changed, 3 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst index 9622de65d..2e50068f6 100644 --- a/docs/plat/arm/arm-build-options.rst +++ b/docs/plat/arm/arm-build-options.rst @@ -91,6 +91,9 @@ Arm Platform Build Options platforms. If this option is specified, then the path to the CryptoCell SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag. +- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the + SPMC Core manifest. Valid when ``SPD=spmd`` is selected. + For a better understanding of these options, the Arm development platform memory map is explained in the :ref:`Firmware Design`. -- cgit v1.2.3 From f85f37d4f78c8c81fb0d6402b5f98b2428a9ab54 Mon Sep 17 00:00:00 2001 From: Nina Wu Date: Fri, 17 Apr 2020 17:14:23 +0800 Subject: Initialize platform for MediaTek mt8192 - Add basic platform setup - Add mt8192 documentation at docs/plat/ - Add generic CPU helper functions - Add basic register address Change-Id: Ife34622105404a8227441aab939e3c55c96374e9 Signed-off-by: Nina Wu --- docs/plat/index.rst | 1 + docs/plat/mt8192.rst | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 docs/plat/mt8192.rst (limited to 'docs/plat') diff --git a/docs/plat/index.rst b/docs/plat/index.rst index 7969003c9..6a38113fc 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -19,6 +19,7 @@ Platform Ports intel-stratix10 marvell/index mt8183 + mt8192 nvidia-tegra warp7 imx8 diff --git a/docs/plat/mt8192.rst b/docs/plat/mt8192.rst new file mode 100644 index 000000000..369afcfb7 --- /dev/null +++ b/docs/plat/mt8192.rst @@ -0,0 +1,21 @@ +MediaTek 8192 +============= + +MediaTek 8192 (MT8192) is a 64-bit ARM SoC introduced by MediaTek in 2020. +The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76. +Cortex-A76 can operate at up to 2.2 GHz. +Cortex-A55 can operate at up to 2 GHz. + +Boot Sequence +------------- + +:: + + Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel + +How to Build +------------ + +.. code:: shell + + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8192 DEBUG=1 COREBOOT=1 -- cgit v1.2.3 From 6844c3477b862195c12660f136e22313e84d4306 Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Wed, 29 Jul 2020 09:37:25 -0500 Subject: Fix broken links to various sections across docs These broken links were found with the help of this command: $> sphinx-build -M linkcheck . build A sample broken link is reported as follows: (line 80) -local- firmware-design.rst#secure-el1-payloads-and-dispatchers Change-Id: I5dcefdd4b8040908658115647e957f6c2c5da7c2 Signed-off-by: Madhukar Pappireddy --- docs/plat/arm/fvp/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index fd658bbff..745e31f9e 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -635,7 +635,7 @@ boot Linux with 4 CPUs using the AArch32 build of TF-A. *Copyright (c) 2019-2020, Arm Limited. All rights reserved.* -.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts +.. _TB_FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts .. _Arm's website: `FVP models`_ .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms .. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 -- cgit v1.2.3 From 5bd9c17d023288e6b819fa3eecc01b7981399cfa Mon Sep 17 00:00:00 2001 From: Saurabh Gorecha Date: Wed, 22 Apr 2020 21:31:24 +0530 Subject: sc7180 platform support Adding support for QTI CHIP SC7180 on ATF Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82 Signed-off-by: Saurabh Gorecha Co-authored-by: Maulik Shah --- docs/plat/index.rst | 1 + docs/plat/qti.rst | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 docs/plat/qti.rst (limited to 'docs/plat') diff --git a/docs/plat/index.rst b/docs/plat/index.rst index 7969003c9..553d8b53e 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -27,6 +27,7 @@ Platform Ports poplar qemu qemu-sbsa + qti rpi3 rpi4 rcar-gen3 diff --git a/docs/plat/qti.rst b/docs/plat/qti.rst new file mode 100644 index 000000000..814e6726a --- /dev/null +++ b/docs/plat/qti.rst @@ -0,0 +1,41 @@ +Qualcomm Technologies, Inc. +=========================== + +Trusted Firmware-A (TF-A) implements the EL3 firmware layer for QTI SC7180. + + +Boot Trace +------------- + +Bootrom --> BL1/BL2 --> BL31 --> BL33 --> Linux kernel + +BL1/2 and BL33 can currently be supplied from Coreboot + Depthcharge + +How to build +------------ + +Code Locations +~~~~~~~~~~~~~~ + +- Trusted Firmware-A: + `link `__ + +Build Procedure +~~~~~~~~~~~~~~~ + +QTI SoC expects TF-A's BL31 to get integrated with other boot software +Coreboot, so only bl31.elf need to get build from the TF-A repository. + +The build command looks like + + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sc7180 COREBOOT=1 + +update value of CROSS_COMPILE argument with your cross-compilation toolchain. + +Additional QTISECLIB_PATH= can be added in build command. +if QTISECLIB_PATH is not added in build command stub implementation of qtiseclib +is picked. qtiseclib with stub implementation doesn't boot device. This was +added to satisfy compilation. + +QTISELIB for SC7180 is available at +`link `__ -- cgit v1.2.3 From fddfb3baf7c9e6e5e6d3462e71df6ba9d292f142 Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Wed, 12 Aug 2020 13:18:19 -0500 Subject: plat/arm: Use common build flag for using generic sp804 driver SP804 TIMER is not platform specific, and current code base adds multiple defines to use this driver. Like FVP_USE_SP804_TIMER and FVP_VE_USE_SP804_TIMER. This patch removes platform specific build flag and adds generic flag `USE_SP804_TIMER` to be set to 1 by platform if needed. Change-Id: I5ab792c189885fd1b98ddd187f3a38ebdd0baba2 Signed-off-by: Madhukar Pappireddy --- docs/plat/arm/fvp/index.rst | 4 ---- 1 file changed, 4 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index 745e31f9e..e3bf42ad9 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -123,10 +123,6 @@ Arm FVP Platform Specific Build Options - ``FVP_GICV2`` : The GICv2 only driver is selected - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) -- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer - for functions that wait for an arbitrary time length (udelay and mdelay). - The default value is 0. - - ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for details on HW_CONFIG. By default, this is initialized to a sensible DTS -- cgit v1.2.3 From 6a2426a94f78815e9390835db4b6c9b4a29facf7 Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Thu, 11 Jun 2020 21:46:44 +0900 Subject: qemu/qemu_sbsa: enable SPM support Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM. Co-developed-by: Fu Wei Signed-off-by: Fu Wei Signed-off-by: Masahisa Kojima Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a --- docs/plat/qemu-sbsa.rst | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/qemu-sbsa.rst b/docs/plat/qemu-sbsa.rst index 51fe41404..bc82ae526 100644 --- a/docs/plat/qemu-sbsa.rst +++ b/docs/plat/qemu-sbsa.rst @@ -19,7 +19,6 @@ and also enable methods for the CPUs. Current limitations: - Only cold boot is supported -- No instructions for how to load a BL32 (Secure Payload) To build TF-A: @@ -27,9 +26,18 @@ To build TF-A: git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa cd tfa - export CROSS_COMPILE=aarch64-linux-gnu- + export CROSS_COMPILE=aarch64-none-elf- make PLAT=qemu_sbsa all fip +To build TF-A with BL32 and SPM enabled(StandaloneMM as a Secure Payload): + +:: + + git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa + cd tfa + export CROSS_COMPILE=aarch64-none-elf- + make PLAT=qemu_sbsa BL32=../STANDALONE_MM.fd SPM_MM=1 EL3_EXCEPTION_HANDLING=1 all fip + Images will be placed at build/qemu_sbsa/release (bl1.bin and fip.bin). Need to copy them into top directory for EDK2 compilation. -- cgit v1.2.3 From dfd5bfb097a694a136d067bb1b80133500adcfce Mon Sep 17 00:00:00 2001 From: Chandni Cherukuri Date: Tue, 22 Sep 2020 18:56:25 +0530 Subject: plat/arm: Add platform support for Morello This patch adds support for Morello platform. It is an initial port which includes only BL31 support as the System Control Processor (SCP) is expected to take the role of primary bootloader. Change-Id: I1ecbe5a14a2d487b2ecea3c1ca227f08473ed2dd Co-authored-by: Chandni Cherukuri Signed-off-by: Chandni Cherukuri Signed-off-by: Anurag Koul --- docs/plat/index.rst | 1 + 1 file changed, 1 insertion(+) (limited to 'docs/plat') diff --git a/docs/plat/index.rst b/docs/plat/index.rst index bd2341010..fb60e5639 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -54,6 +54,7 @@ documentation associated with them. - Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP - Arm SGI-575 and SGM-775 - MediaTek MT6795 and MT8173 SoCs + - Arm Morello Platform -------------- -- cgit v1.2.3 From a6c07e0ddfa3658d7bc0ad1693b6e908293c1c96 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 27 Aug 2020 12:13:30 +0100 Subject: arm_fpga: Add platform documentation As the Arm Ltd. FPGA port is now working for all existing images, add some documentation file. Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6 Signed-off-by: Andre Przywara --- docs/plat/arm/arm_fpga/index.rst | 97 ++++++++++++++++++++++++++++++++++++++++ docs/plat/arm/index.rst | 1 + 2 files changed, 98 insertions(+) create mode 100644 docs/plat/arm/arm_fpga/index.rst (limited to 'docs/plat') diff --git a/docs/plat/arm/arm_fpga/index.rst b/docs/plat/arm/arm_fpga/index.rst new file mode 100644 index 000000000..5427c1dde --- /dev/null +++ b/docs/plat/arm/arm_fpga/index.rst @@ -0,0 +1,97 @@ +Arm FPGA Platform +================= + +This platform supports FPGA images used internally in Arm Ltd., for +testing and bringup of new cores. With that focus, peripheral support is +minimal: there is no mass storage or display output, for instance. Also +this port ignores any power management features of the platform. +Some interconnect setup is done internally by the platform, so the TF-A code +just needs to setup UART and GIC. + +The FPGA platform requires to pass on a DTB for the non-secure payload +(mostly Linux), so we let TF-A use information from the DTB for dynamic +configuration: the UART and GIC base addresses are read from there. + +As a result this port is a fairly generic BL31-only port, which can serve +as a template for a minimal new (and possibly DT-based) platform port. + +The aim of this port is to support as many FPGA images as possible with +a single build. Image specific data must be described in the DTB or should +be auto-detected at runtime. + +As the number and topology layout of the CPU cores differs significantly +across the various images, this is detected at runtime by BL31. +The /cpus node in the DT will be added and filled accordingly, as long as +it does not exist already. + +Platform-specific build options +------------------------------- + +- ``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers. + Normally TF-A panics if it encounters a MPID value not matched to its + internal list, but for new or experimental cores this creates a lot of + churn. With this option, the code will fall back to some basic CPU support + code (only architectural system registers, and no errata). + Default value of this flag is 1. + +- ``PRELOADED_BL33_BASE`` : Physical address of the BL33 non-secure payload. + It must have been loaded into DRAM already, typically this is done by + the script that also loads BL31 and the DTB. + It defaults to 0x80080000, which is the traditional load address for an + arm64 Linux kernel. + +- ``FPGA_PRELOADED_DTB_BASE`` : Physical address of the flattened device + tree blob (DTB). This DT will be used by TF-A for dynamic configuration, + so it must describe at least the UART and a GICv3 interrupt controller. + The DT gets amended by the code, to potentially add a command line and + fill the CPU topology nodes. It will also be passed on to BL33, by + putting its address into the x0 register before jumping to the entry + point (following the Linux kernel boot protocol). + It defaults to 0x80070000, which is 64KB before the BL33 load address. + +- ``FPGA_PRELOADED_CMD_LINE`` : Physical address of the command line to + put into the devicetree blob. Due to the lack of a proper bootloader, + a command line can be put somewhere into memory, so that BL31 will + detect it and copy it into the DTB passed on to BL33. + To avoid random garbage, there needs to be a "CMD:" signature before the + actual command line. + Defaults to 0x1000, which is normally in the "ROM" space of the typical + FPGA image (which can be written by the FPGA payload uploader, but is + read-only to the CPU). The FPGA payload tool should be given a text file + containing the desired command line, prefixed by the "CMD:" signature. + +Building the TF-A image +----------------------- + + .. code:: shell + + make PLAT=arm_fgpa DEBUG=1 + + This will use the default load addresses as described above. When those + addresses need to differ for a certain setup, they can be passed on the + make command line: + + .. code:: shell + + make PLAT=arm_fgpa DEBUG=1 PRELOADED_BL33_BASE=0x80200000 FPGA_PRELOADED_DTB_BASE=0x80180000 bl31 + +Running the TF-A image +---------------------- + +After building TF-A, the actual TF-A code will be located in ``bl31.bin`` in +the build directory. +Additionally there is a ``bl31.axf`` ELF file, which contains BL31, as well +as some simple ROM trampoline code (required by the Arm FPGA boot flow) and +a generic DTB to support most of the FPGA images. This can be simply handed +over to the FPGA payload uploader, which will take care of loading the +components at their respective load addresses. In addition to this file +you need at least a BL33 payload (typically a Linux kernel image), optionally +a Linux initrd image file and possibly a command line: + + .. code:: shell + + fpga-run ... -m bl31.axf -l auto -m Image -l 0x80080000 -m initrd.gz -l 0x84000000 -m cmdline.txt -l 0x1000 + +-------------- + +*Copyright (c) 2020, Arm Limited. All rights reserved.* diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst index 1afe475c6..9c2fcb102 100644 --- a/docs/plat/arm/index.rst +++ b/docs/plat/arm/index.rst @@ -9,6 +9,7 @@ Arm Development Platforms fvp/index fvp-ve/index tc0/index + arm_fpga/index arm-build-options This chapter holds documentation related to Arm's development platforms, -- cgit v1.2.3 From 219e45cdd2404c6553b475b315167dda51f74227 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Fri, 2 Oct 2020 10:07:00 +0200 Subject: doc: stm32mp1: Improve OP-TEE related documentation stm32mp15_optee_defconfig has been dropped from U-Boot as it became identical to stm32mp15_trusted_defconfig. Furthermore give a hint how OP-TEE is supposed to be installed. Signed-off-by: Jan Kiszka Change-Id: Id8f0bd84a87e3a62072dd4405aadddcdd3511213 --- docs/plat/stm32mp1.rst | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'docs/plat') diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst index 2c372a6a3..263867c25 100644 --- a/docs/plat/stm32mp1.rst +++ b/docs/plat/stm32mp1.rst @@ -101,7 +101,7 @@ To build TF-A with OP-TEE support for all bootable devices: cd make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts cd - make stm32mp15_optee_defconfig + make stm32mp15_trusted_defconfig make DEVICE_TREE=stm32mp157c-ev1 all @@ -121,5 +121,11 @@ It should contain at least those partitions: Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl. +OP-TEE artifacts go into separate partitions as follows: + +- teeh: tee-header_v2.stm32 +- teed: tee-pageable_v2.stm32 +- teex: tee-pager_v2.stm32 + .. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html -- cgit v1.2.3 From ccf220adcbe393de148efc50462b157685478f13 Mon Sep 17 00:00:00 2001 From: Manish V Badarkhe Date: Fri, 2 Oct 2020 07:27:27 +0100 Subject: doc: Update list of supported FVP platforms Updated the list of supported FVP platform as per latest FVP platform release. Signed-off-by: Manish V Badarkhe Change-Id: I45ef79aff147ed598a3a92ab6f6b277f7f70604a --- docs/plat/arm/fvp/index.rst | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index e3bf42ad9..3a13268fa 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -12,8 +12,9 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only). .. note:: - The FVP models used are Version 11.9 Build 41, unless otherwise stated. + The FVP models used are Version 11.12 Build 38, unless otherwise stated. +- ``FVP_Base_AEMvA`` - ``FVP_Base_AEMv8A-AEMv8A`` - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` - ``FVP_Base_RevC-2xAEMv8A`` @@ -37,22 +38,26 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores - ``FVP_Base_Cortex-A76AEx4`` - ``FVP_Base_Cortex-A76AEx8`` - ``FVP_Base_Cortex-A77x4`` +- ``FVP_Base_Cortex-A78x4`` - ``FVP_Base_Neoverse-E1x1`` - ``FVP_Base_Neoverse-E1x2`` - ``FVP_Base_Neoverse-E1x4`` - ``FVP_Base_Neoverse-N1x4`` -- ``FVP_Base_Zeusx4`` +- ``FVP_Base_Neoverse-V1x4`` - ``FVP_CSS_SGI-575`` (Version 11.10 build 36) - ``FVP_CSS_SGM-775`` -- ``FVP_RD_E1_edge`` (Version 11.10 build 36) +- ``FVP_RD_E1_edge`` (Version 11.9 build 41) - ``FVP_RD_N1_edge`` (Version 11.10 build 36) - ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36) +- ``FVP_RD_Daniel`` (Version 11.10 build 36) +- ``FVP_TC0`` (Version 0.0 build 6114) - ``Foundation_Platform`` The latest version of the AArch32 build of TF-A has been tested on the following Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only). +- ``FVP_Base_AEMvA`` - ``FVP_Base_AEMv8A-AEMv8A`` - ``FVP_Base_Cortex-A32x4`` -- cgit v1.2.3 From 8445253e3ff0f17e04bb0dd8d0744548481cb795 Mon Sep 17 00:00:00 2001 From: Chandni Cherukuri Date: Thu, 1 Oct 2020 13:10:45 +0530 Subject: morello: Add Morello platform documentation Morello platform has a SCP which brings the primary Rainier CPU out of reset which starts executing at BL31. This patch provides documentation support for Morello platform. Signed-off-by: Chandni Cherukuri Change-Id: I38f596668e2b14862d543fabc04549ff34bfb8a2 --- docs/plat/arm/index.rst | 1 + docs/plat/arm/morello/index.rst | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 docs/plat/arm/morello/index.rst (limited to 'docs/plat') diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst index 9c2fcb102..f72992b80 100644 --- a/docs/plat/arm/index.rst +++ b/docs/plat/arm/index.rst @@ -11,6 +11,7 @@ Arm Development Platforms tc0/index arm_fpga/index arm-build-options + morello/index This chapter holds documentation related to Arm's development platforms, including both software models (FVPs) and hardware development boards diff --git a/docs/plat/arm/morello/index.rst b/docs/plat/arm/morello/index.rst new file mode 100644 index 000000000..b18001cae --- /dev/null +++ b/docs/plat/arm/morello/index.rst @@ -0,0 +1,33 @@ +Morello Platform +================ + +Morello is an ARMv8-A platform that implements the capability architecture extension. +The platform port present at `site `_ +provides ARMv8-A architecture enablement. + +Capability architecture specific changes will be added `here `_ + +Further information on Morello Platform is available at `info `_ + +Boot Sequence +------------- + +The execution begins from SCP_BL1 which loads the SCP_BL2 and starts its +execution. SCP_BL2 powers up the AP which starts execution at AP_BL31. The AP +then continues executing and hands off execution to Non-secure world (UEFI). + +Build Procedure (TF-A only) +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Obtain arm `toolchain `_. + Set the CROSS_COMPILE environment variable to point to the toolchain folder. + +- Build TF-A: + + .. code:: shell + + export CROSS_COMPILE=/bin/aarch64-none-elf- + + make PLAT=morello all + +*Copyright (c) 2020, Arm Limited. All rights reserved.* -- cgit v1.2.3 From 1d935a1b557b6f85d0d42b1fb90cd261d2e57717 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Sun, 4 Oct 2020 16:00:07 +0200 Subject: docs: marvell: update mv_ddr branch Now that the BLE image sources (mv_ddr) are updated, reflect the proper branch in the Armada build howto. Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1 Signed-off-by: Marcin Wojtas --- docs/plat/marvell/armada/build.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 6b9054c7c..56b627b48 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -259,7 +259,7 @@ Armada37x0 Builds require installation of 3 components > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi (2) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv_ddr-armada-atf-mainline" branch): + (use the "mv_ddr-armada-18.12" branch): https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git @@ -271,6 +271,6 @@ Armada70x0 and Armada80x0 Builds require installation of an additional component ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ (1) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv_ddr-armada-atf-mainline" branch): + (use the "mv_ddr-armada-18.12" branch): https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git -- cgit v1.2.3 From 583079ae0680bb7c69e3d81a3b6742947efd699b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 7 Oct 2020 11:01:00 +0200 Subject: docs: marvell: update ddr3 build instructions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add information about 2GB variant of EspressoBin V5 and use Marvell git branches which contain required fixes for EspressoBin. Signed-off-by: Pali Rohár Change-Id: I1db510f1576f4762259ad7b0c10024b8ab434a59 --- docs/plat/marvell/armada/build.rst | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 56b627b48..e21fb3cfb 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -124,11 +124,12 @@ There are several build options: Supported Options: - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) - DDR4 1CS (1): DB-88F3720-DDR4-Modular (512MB) - - DDR3 2CS (2): EspressoBIN V3-V5 (1GB) + - DDR3 2CS (2): EspressoBIN V3-V5 (1GB 2CS) - DDR4 2CS (3): DB-88F3720-DDR4-Modular (4GB) - - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB) + - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB); EspressoBIN V3-V5 (1GB 1CS) - DDR4 1CS (5): EspressoBin V7 (1GB) - DDR4 2CS (6): EspressoBin V7 (2GB) + - DDR3 2CS (7): EspressoBin V3-V5 (2GB) - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB - CLOCKSPRESET @@ -259,11 +260,12 @@ Armada37x0 Builds require installation of 3 components > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi (2) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv_ddr-armada-18.12" branch): + (use the "mv-ddr-devel" branch): https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git -(3) Armada3700 tools available at the following repository (use the latest release branch): +(3) Armada3700 tools available at the following repository + (use the "A3700_utils-armada-18.12-fixed" branch): https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git @@ -271,6 +273,6 @@ Armada70x0 and Armada80x0 Builds require installation of an additional component ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ (1) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv_ddr-armada-18.12" branch): + (use the "mv-ddr-devel" branch): https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git -- cgit v1.2.3 From 6354401276aaf02a671398c8c69a11b9c7ebd80c Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 13 Oct 2020 11:27:05 +0200 Subject: docs: update STM32MP1 with versions details After introducing the new STM32MP1 SoC versions in patch [1], the document describing STM32MP1 platform is updated with the information given in the patch commit message. [1]: stm32mp1: add support for new SoC profiles Change-Id: I6d7ce1a3c29678ddac78a6685f5d5daf28c3c3a1 Signed-off-by: Yann Gautier --- docs/plat/stm32mp1.rst | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst index 263867c25..f597460db 100644 --- a/docs/plat/stm32mp1.rst +++ b/docs/plat/stm32mp1.rst @@ -8,6 +8,23 @@ The STM32MP1 chip also embeds a Cortex-M4. More information can be found on `STM32MP1 Series`_ page. +STM32MP1 Versions +----------------- +The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: + +- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD +- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD +- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz + +Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option: + +- A Basic + Cortex-A7 @ 650 MHz +- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz +- D Basic + Cortex-A7 @ 800 MHz +- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz + +The `STM32MP1 part number codification`_ page gives more information about part numbers. + Design ------ The STM32MP1 resets in the ROM code of the Cortex-A7. @@ -129,3 +146,4 @@ OP-TEE artifacts go into separate partitions as follows: .. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html +.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification -- cgit v1.2.3 From f20cb7e54e152863a8cba9cc4802fb9381a317ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 29 Oct 2020 17:44:27 +0100 Subject: docs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash changes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also add example how to build TF-A for A3720 Turris MOX board and also fix style/indentation issues and information about default values. Signed-off-by: Pali Rohár Change-Id: I2dc957307b1b627b403a8d960e85f5ac9e15aee5 --- docs/plat/marvell/armada/build.rst | 107 +++++++++++++++++++++++-------------- 1 file changed, 66 insertions(+), 41 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index e21fb3cfb..54182cb08 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -61,17 +61,17 @@ There are several build options: Defines the level of logging which will be purged to the default output port. - LOG_LEVEL_NONE 0 - LOG_LEVEL_ERROR 10 - LOG_LEVEL_NOTICE 20 - LOG_LEVEL_WARNING 30 - LOG_LEVEL_INFO 40 - LOG_LEVEL_VERBOSE 50 + - 0 - LOG_LEVEL_NONE + - 10 - LOG_LEVEL_ERROR + - 20 - LOG_LEVEL_NOTICE (default for DEBUG=0) + - 30 - LOG_LEVEL_WARNING + - 40 - LOG_LEVEL_INFO (default for DEBUG=1) + - 50 - LOG_LEVEL_VERBOSE - USE_COHERENT_MEM This flag determines whether to include the coherent memory region in the - BL memory map or not. + BL memory map or not. Enabled by default. - LLC_ENABLE @@ -122,25 +122,25 @@ There are several build options: For Armada37x0 only, the DDR topology map index/name, default is 0. Supported Options: - - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) - - DDR4 1CS (1): DB-88F3720-DDR4-Modular (512MB) - - DDR3 2CS (2): EspressoBIN V3-V5 (1GB 2CS) - - DDR4 2CS (3): DB-88F3720-DDR4-Modular (4GB) - - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB); EspressoBIN V3-V5 (1GB 1CS) - - DDR4 1CS (5): EspressoBin V7 (1GB) - - DDR4 2CS (6): EspressoBin V7 (2GB) - - DDR3 2CS (7): EspressoBin V3-V5 (2GB) - - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB + - 0 - DDR3 1CS: DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) + - 1 - DDR4 1CS: DB-88F3720-DDR4-Modular (512MB) + - 2 - DDR3 2CS: EspressoBIN V3-V5 (1GB 2CS) + - 3 - DDR4 2CS: DB-88F3720-DDR4-Modular (4GB) + - 4 - DDR3 1CS: DB-88F3720-DDR3-Modular (1GB); EspressoBIN V3-V5 (1GB 1CS) + - 5 - DDR4 1CS: EspressoBin V7 (1GB) + - 6 - DDR4 2CS: EspressoBin V7 (2GB) + - 7 - DDR3 2CS: EspressoBin V3-V5 (2GB) + - CUST - CUSTOMER: Customer board, DDR3 1CS 512MB - CLOCKSPRESET For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency, default is CPU_800_DDR_800. - - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz - - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz - - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz - - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz + - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz + - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz + - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz + - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz - BOOTDEV @@ -176,33 +176,48 @@ There are several build options: - WTP - For Armada37x0 only, use this parameter to point to wtptools source code - directory, which can be found as a3700_utils.zip in the release. Usage - example: ``WTP=/path/to/a3700_utils`` + For Armada37x0 only, use this parameter to point to wtptools source code + directory, which can be found as a3700_utils.zip in the release. Usage + example: ``WTP=/path/to/a3700_utils`` - For example, in order to build the image in debug mode with log level up to 'notice' level run +- CRYPTOPP_PATH - .. code:: shell + For Armada37x0 only, use this parameter tp point to Crypto++ source code + directory, which is required for building WTP image tool. - > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT= all fip - And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level, - the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS, - the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command - line is as following +For example, in order to build the image in debug mode with log level up to 'notice' level run - .. code:: shell +.. code:: shell + + > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT= mrvl_flash + +And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level, +the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS, +the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command +line is as following + +.. code:: shell + + > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \ + MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 \ + MV_DDR_PATH=/path/to/mv-ddr-marvell/ WTP=/path/to/A3700-utils-marvell/ \ + CRYPTOPP_PATH=/path/to/cryptopp/ BL33=/path/to/u-boot.bin \ + all fip mrvl_bootimage mrvl_flash - > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \ - MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip +To build just TF-A without WTMI image (useful for A3720 Turris MOX board), run following command: - Supported MARVELL_PLATFORM are: - - a3700 (for both A3720 DB and EspressoBin) - - a70x0 - - a70x0_amc (for AMC board) - - a80x0 - - a80x0_mcbin (for MacchiatoBin) - - t9130 (OcteonTX2 CN913x) +.. code:: shell + + > make USE_COHERENT_MEM=0 PLAT=a3700 BL33=/path/to/u-boot.bin CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage + +Supported MARVELL_PLATFORM are: + - a3700 (for both A3720 DB and EspressoBin) + - a70x0 + - a70x0_amc (for AMC board) + - a80x0 + - a80x0_mcbin (for MacchiatoBin) + - t9130 (OcteonTX2 CN913x) Special Build Flags -------------------- @@ -224,7 +239,7 @@ For more information about build options, please refer to the Build output ------------ -Marvell's TF-A compilation generates 7 files: +Marvell's TF-A compilation generates 8 files: - ble.bin - BLe image - bl1.bin - BL1 image @@ -234,6 +249,12 @@ Marvell's TF-A compilation generates 7 files: - boot-image.bin - TF-A image (contains BL1 and FIP images) - flash-image.bin - Image which contains boot-image.bin and SPL image. Should be placed on the boot flash/device. + - uart-images.tgz.bin - GZIPed TAR archive which contains Armada37x0 images + for booting via UART. Could be loaded via Marvell's WtpDownload tool from + A3700-utils-marvell repository. + +Additional make target ``mrvl_bootimage`` produce ``boot-image.bin`` file and target +``mrvl_flash`` produce final ``flash-image.bin`` and ``uart-images.tgz.bin`` files. Tools and external components installation @@ -269,6 +290,10 @@ Armada37x0 Builds require installation of 3 components https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git +(4) Crypto++ library available at the following repository: + + https://github.com/weidai11/cryptopp.git + Armada70x0 and Armada80x0 Builds require installation of an additional component ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- cgit v1.2.3 From 7b24e48a46b47b2b37c0b0c4458d4ce515487e36 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Tue, 8 Dec 2020 13:35:27 +0530 Subject: doc: Update list of supported FVP platforms Updated the list of supported FVP platforms with support for RD-N2 FVP. Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386 Signed-off-by: Aditya Angadi --- docs/plat/arm/fvp/index.rst | 1 + 1 file changed, 1 insertion(+) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index 3a13268fa..f643f6b00 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -50,6 +50,7 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores - ``FVP_RD_N1_edge`` (Version 11.10 build 36) - ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36) - ``FVP_RD_Daniel`` (Version 11.10 build 36) +- ``FVP_RD_N2`` (Version 11.13 build 10) - ``FVP_TC0`` (Version 0.0 build 6114) - ``Foundation_Platform`` -- cgit v1.2.3 From be3a3bc715619b5ea15b3f338cd80d00d92cb836 Mon Sep 17 00:00:00 2001 From: Arunachalam Ganapathy Date: Tue, 8 Dec 2020 16:35:18 +0000 Subject: docs: arm: Add OPTEE_SP_FW_CONFIG This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG. Signed-off-by: Arunachalam Ganapathy Change-Id: Ie45f075cf04182701007f87aa0c8912cd567157a --- docs/plat/arm/arm-build-options.rst | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst index 2e50068f6..a1d231357 100644 --- a/docs/plat/arm/arm-build-options.rst +++ b/docs/plat/arm/arm-build-options.rst @@ -94,6 +94,10 @@ Arm Platform Build Options - ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the SPMC Core manifest. Valid when ``SPD=spmd`` is selected. +- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in tb_fw_config + device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest + file name contains pattern optee_sp. + For a better understanding of these options, the Arm development platform memory map is explained in the :ref:`Firmware Design`. -- cgit v1.2.3 From d9243f264b91b45d82376081afc3c2b45c0e540f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 5 Jan 2021 14:01:05 +0100 Subject: plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which, when enabled, adds code to the PSCI reset handler to try to do system reset by the WTMI firmware running on the Cortex-M3 secure coprocessor. (This function is exposed via the mailbox interface.) The reason is that the Turris MOX board has a HW bug which causes reset to hang unpredictably. This issue can be solved by putting the board in a specific state before reset. Signed-off-by: Marek Behún Change-Id: I3f60b9f244f334adcd33d6db6a361fbc8b8d209f --- docs/plat/marvell/armada/build.rst | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 54182cb08..2c2bd680c 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -86,6 +86,20 @@ There are several build options: There is no reason to enable this feature if OP-TEE OS built with CFG_WITH_PAGER=n. Only set LLC_SRAM=1 if OP-TEE OS is built with CFG_WITH_PAGER=y. +- CM3_SYSTEM_RESET + + For Armada37x0 only, when ``CM3_SYSTEM_RESET=1``, the Cortex-M3 secure coprocessor will + be used for system reset. + TF-A will send command 0x0009 with a magic value via the rWTM mailbox interface to the + Cortex-M3 secure coprocessor. + The firmware running in the coprocessor must either implement this functionality or + ignore the 0x0009 command (which is true for the firmware from A3700-utils-marvell + repository). If this option is enabled but the firmware does not support this command, + an error message will be printed prior trying to reboot via the usual way. + + This option is needed on Turris MOX as a workaround to a HW bug which causes reset to + sometime hang the board. + - MARVELL_SECURE_BOOT Build trusted(=1)/non trusted(=0) image, default is non trusted. @@ -209,7 +223,8 @@ To build just TF-A without WTMI image (useful for A3720 Turris MOX board), run f .. code:: shell - > make USE_COHERENT_MEM=0 PLAT=a3700 BL33=/path/to/u-boot.bin CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage + > make USE_COHERENT_MEM=0 PLAT=a3700 CM3_SYSTEM_RESET=1 BL33=/path/to/u-boot.bin \ + CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage Supported MARVELL_PLATFORM are: - a3700 (for both A3720 DB and EspressoBin) -- cgit v1.2.3 From 06ea86fee8bfd1de1a0620e1c627a22af020f40f Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 13 Jan 2021 21:54:01 +0530 Subject: docs: update fvp version to be used for rdv1 platform Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36 to 11.13 build 10 Signed-off-by: Aditya Angadi Change-Id: I9622c03d342bb780234dec8ffe4ab11d8069acab --- docs/plat/arm/fvp/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index f643f6b00..ea72962e8 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -49,7 +49,7 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores - ``FVP_RD_E1_edge`` (Version 11.9 build 41) - ``FVP_RD_N1_edge`` (Version 11.10 build 36) - ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36) -- ``FVP_RD_Daniel`` (Version 11.10 build 36) +- ``FVP_RD_Daniel`` (Version 11.13 build 10) - ``FVP_RD_N2`` (Version 11.13 build 10) - ``FVP_TC0`` (Version 0.0 build 6114) - ``Foundation_Platform`` -- cgit v1.2.3 From 2bc485858b9cb3d2f47470e2798fcab7f920a10f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 7 Dec 2020 13:14:38 +0000 Subject: doc: renesas: Document platforms based on RZ/G2 SoC's Document the platforms based on RZ/G2 SoC's. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Change-Id: I9ce5b9df3573b1198c5c7be79b5471d54573609a --- docs/plat/index.rst | 1 + docs/plat/rz-g2.rst | 228 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 229 insertions(+) create mode 100644 docs/plat/rz-g2.rst (limited to 'docs/plat') diff --git a/docs/plat/index.rst b/docs/plat/index.rst index fb60e5639..3cbb55246 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -32,6 +32,7 @@ Platform Ports rpi3 rpi4 rcar-gen3 + rz-g2 rockchip socionext-uniphier synquacer diff --git a/docs/plat/rz-g2.rst b/docs/plat/rz-g2.rst new file mode 100644 index 000000000..e7ae62040 --- /dev/null +++ b/docs/plat/rz-g2.rst @@ -0,0 +1,228 @@ +Renesas RZ/G +============ + +The "RZ/G" Family of high-end 64-bit Arm®-based microprocessors (MPUs) +enables the solutions required for the smart society of the future. +Through a variety of Arm Cortex®-A53 and A57-based devices, engineers can +easily implement high-resolution human machine interfaces (HMI), embedded +vision, embedded artificial intelligence (e-AI) and real-time control and +industrial ethernet connectivity. + +The scalable RZ/G hardware platform and flexible software platform +cover the full product range, from the premium class to the entry +level. Plug-ins are available for multiple open-source software tools. + + +Renesas RZ/G2 reference platforms: +---------------------------------- + ++--------------+----------------------------------------------------------------------------------+ +| Board | Details | ++==============+===============+==================================================================+ +| hihope-rzg2h | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2H SoC | +| +----------------------------------------------------------------------------------+ +| | http://hihope.org/product/musashi | ++--------------+----------------------------------------------------------------------------------+ +| hihope-rzg2m | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2M SoC | +| +----------------------------------------------------------------------------------+ +| | http://hihope.org/product/musashi | ++--------------+----------------------------------------------------------------------------------+ +| hihope-rzg2n | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2N SoC | +| +----------------------------------------------------------------------------------+ +| | http://hihope.org/product/musashi | ++--------------+----------------------------------------------------------------------------------+ +| ek874 | "96 boards" compatible board from Silicon Linux equipped with Renesas RZ/G2E SoC | +| +----------------------------------------------------------------------------------+ +| | https://www.si-linux.co.jp/index.php?CAT%2FCAT874 | ++--------------+----------------------------------------------------------------------------------+ + +`boards info `__ + +The current TF-A port has been tested on the HiHope RZ/G2M +SoC_id r8a774a1 revision ES1.3. + + +:: + + ARM CA57 (ARMv8) 1.5 GHz dual core, with NEON/VFPv4, L1$ I/D 48K/32K, L2$ 1MB + ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K, L2$ 512K + Memory controller for LPDDR4-3200 4GB in 2 channels(32-bit bus mode) + Two- and three-dimensional graphics engines, + Video processing units, + Display Output, + Video Input, + SD card host interface, + USB3.0 and USB2.0 interfaces, + CAN interfaces, + Ethernet AVB, + Wi-Fi + BT, + PCI Express Interfaces, + Memories + INTERNAL 384KB SYSTEM RAM + DDR 4 GB LPDDR4 + QSPI FLASH 64MB + EMMC 32 GB EMMC (HS400 240 MBYTES/S) + MICROSD-CARD SLOT (SDR104 100 MBYTES/S) + +Overview +-------- +On RZ/G2 SoCs the BOOTROM starts the cpu at EL3; for this port BL2 +will therefore be entered at this exception level (the Renesas' ATF +reference tree [1] resets into EL1 before entering BL2 - see its +bl2.ld.S) + +BL2 initializes DDR before determining the boot reason (cold or warm). + +Once BL2 boots, it determines the boot reason, writes it to shared +memory (BOOT_KIND_BASE) together with the BL31 parameters +(PARAMS_BASE) and jumps to BL31. + +To all effects, BL31 is as if it is being entered in reset mode since +it still needs to initialize the rest of the cores; this is the reason +behind using direct shared memory access to BOOT_KIND_BASE _and_ +PARAMS_BASE instead of using registers to get to those locations (see +el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use +case). + +[1] https://github.com/renesas-rz/meta-rzg2/tree/BSP-1.0.5/recipes-bsp/arm-trusted-firmware/files + + +How to build +------------ + +The TF-A build options depend on the target board so you will have to +refer to those specific instructions. What follows is customized to +the HiHope RZ/G2M development kit used in this port. + +Build Tested: +~~~~~~~~~~~~~ + +.. code:: bash + + make bl2 bl31 rzg LOG_LEVEL=40 PLAT=rzg LSI=G2M RCAR_DRAM_SPLIT=2\ + RCAR_LOSSY_ENABLE=1 SPD="none" MBEDTLS_DIR=$mbedtls + +System Tested: +~~~~~~~~~~~~~~ +* mbed_tls: + git@github.com:ARMmbed/mbedtls.git [devel] + +| commit 72ca39737f974db44723760623d1b29980c00a88 +| Merge: ef94c4fcf dd9ec1c57 +| Author: Janos Follath +| Date: Wed Oct 7 09:21:01 2020 +0100 + +* u-boot: + The port has beent tested using mainline uboot with HiHope RZ/G2M board + specific patches. + +| commit 46ce9e777c1314ccb78906992b94001194eaa87b +| Author: Heiko Schocher +| Date: Tue Nov 3 15:22:36 2020 +0100 + +* linux: + The port has beent tested using mainline kernel. + +| commit f8394f232b1eab649ce2df5c5f15b0e528c92091 +| Author: Linus Torvalds +| Date: Sun Nov 8 16:10:16 2020 -0800 +| Linux 5.10-rc3 + +TF-A Build Procedure +~~~~~~~~~~~~~~~~~~~~ + +- Fetch all the above 3 repositories. + +- Prepare the AARCH64 toolchain. + +- Build u-boot using hihope_rzg2_defconfig. + + Result: u-boot-elf.srec + +.. code:: bash + + make CROSS_COMPILE=aarch64-linux-gnu- + hihope_rzg2_defconfig + + make CROSS_COMPILE=aarch64-linux-gnu- + +- Build TF-A + + Result: bootparam_sa0.srec, cert_header_sa6.srec, bl2.srec, bl31.srec + +.. code:: bash + + make bl2 bl31 rzg LOG_LEVEL=40 PLAT=rzg LSI=G2M RCAR_DRAM_SPLIT=2\ + RCAR_LOSSY_ENABLE=1 SPD="none" MBEDTLS_DIR=$mbedtls + + +Install Procedure +~~~~~~~~~~~~~~~~~ + +- Boot the board in Mini-monitor mode and enable access to the + QSPI flash. + + +- Use the flash_writer utility[2] to flash all the SREC files. + +[2] https://github.com/renesas-rz/rzg2_flash_writer + + +Boot trace +---------- +:: + + INFO: ARM GICv2 driver initialized + NOTICE: BL2: RZ/G2 Initial Program Loader(CA57) Rev.2.0.6 + NOTICE: BL2: PRR is RZ/G2M Ver.1.3 + NOTICE: BL2: Board is HiHope RZ/G2M Rev.4.0 + NOTICE: BL2: Boot device is QSPI Flash(40MHz) + NOTICE: BL2: LCM state is unknown + NOTICE: BL2: DDR3200(rev.0.40) + NOTICE: BL2: [COLD_BOOT] + NOTICE: BL2: DRAM Split is 2ch + NOTICE: BL2: QoS is default setting(rev.0.19) + NOTICE: BL2: DRAM refresh interval 1.95 usec + NOTICE: BL2: Periodic Write DQ Training + NOTICE: BL2: CH0: 400000000 - 47fffffff, 2 GiB + NOTICE: BL2: CH2: 600000000 - 67fffffff, 2 GiB + NOTICE: BL2: Lossy Decomp areas + NOTICE: Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570 + NOTICE: Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0 + NOTICE: Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0 + NOTICE: BL2: FDT at 0xe631db30 + NOTICE: BL2: v2.3(release):v2.4-rc0-2-g1433701e5 + NOTICE: BL2: Built : 13:45:26, Nov 7 2020 + NOTICE: BL2: Normal boot + INFO: BL2: Doing platform setup + INFO: BL2: Loading image id 3 + NOTICE: BL2: dst=0xe631d200 src=0x8180000 len=512(0x200) + NOTICE: BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800) + WARNING: r-car ignoring the BL31 size from certificate,using RCAR_TRUSTED_SRAM_SIZE instead + INFO: Loading image id=3 at address 0x44000000 + NOTICE: rcar_file_len: len: 0x0003e000 + NOTICE: BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000) + INFO: Image id=3 loaded: 0x44000000 - 0x4403e000 + INFO: BL2: Loading image id 5 + INFO: Loading image id=5 at address 0x50000000 + NOTICE: rcar_file_len: len: 0x00100000 + NOTICE: BL2: dst=0x50000000 src=0x8300000 len=1048576(0x100000) + INFO: Image id=5 loaded: 0x50000000 - 0x50100000 + NOTICE: BL2: Booting BL31 + INFO: Entry point address = 0x44000000 + INFO: SPSR = 0x3cd + + + U-Boot 2021.01-rc1-00244-gac37e14fbd (Nov 04 2020 - 20:03:34 +0000) + + CPU: Renesas Electronics R8A774A1 rev 1.3 + Model: HopeRun HiHope RZ/G2M with sub board + DRAM: 3.9 GiB + MMC: mmc@ee100000: 0, mmc@ee160000: 1 + Loading Environment from MMC... OK + In: serial@e6e88000 + Out: serial@e6e88000 + Err: serial@e6e88000 + Net: eth0: ethernet@e6800000 + Hit any key to stop autoboot: 0 + => -- cgit v1.2.3 From d0b367b77a67b14922a0139ea1b6ecd620995cb4 Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Thu, 14 Jan 2021 14:25:15 +0100 Subject: docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions The supported MARVELL_PLATFORM list is updated to include the recently added a80x0_puzzle platform (IEI Puzzle-M801). Additionally building instructions are added for the GST ESPRESSObin-Ultra board (1 GB, DDR4 RAM variant), which has been tested successfully and booted TF-A on the board. Signed-off-by: Luka Kovacic Change-Id: Ie5724df27c1ee2e8f6a52664520579e872471e93 --- docs/plat/marvell/armada/build.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 2c2bd680c..29fe4d452 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -226,12 +226,23 @@ To build just TF-A without WTMI image (useful for A3720 Turris MOX board), run f > make USE_COHERENT_MEM=0 PLAT=a3700 CM3_SYSTEM_RESET=1 BL33=/path/to/u-boot.bin \ CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage +You can build TF-A for the Globalscale ESPRESSObin-Ultra board (DDR4, 1 GB) by running the following command: + +.. code:: shell + + > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1200_DDR_750 \ + MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=5 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 \ + MV_DDR_PATH=/path/to/mv-ddr-marvell/ WTP=/path/to/A3700-utils-marvell/ \ + CRYPTOPP_PATH=/path/to/cryptopp/ BL33=/path/to/u-boot.bin \ + all fip mrvl_bootimage mrvl_flash + Supported MARVELL_PLATFORM are: - a3700 (for both A3720 DB and EspressoBin) - a70x0 - a70x0_amc (for AMC board) - a80x0 - a80x0_mcbin (for MacchiatoBin) + - a80x0_puzzle (for IEI Puzzle-M801) - t9130 (OcteonTX2 CN913x) Special Build Flags -- cgit v1.2.3 From 47147013b437b1217eba92546b12862e6297bfed Mon Sep 17 00:00:00 2001 From: David Horstmann Date: Thu, 21 Jan 2021 12:29:59 +0000 Subject: Fix documentation typos and misspellings Fix some typos and misspellings in TF-A documentation. Signed-off-by: David Horstmann Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4949909fa --- docs/plat/marvell/armada/misc/mvebu-ccu.rst | 2 +- docs/plat/marvell/armada/misc/mvebu-io-win.rst | 2 +- docs/plat/marvell/armada/misc/mvebu-iob.rst | 2 +- docs/plat/rpi4.rst | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/misc/mvebu-ccu.rst b/docs/plat/marvell/armada/misc/mvebu-ccu.rst index 5bac11faf..12118e9d9 100644 --- a/docs/plat/marvell/armada/misc/mvebu-ccu.rst +++ b/docs/plat/marvell/armada/misc/mvebu-ccu.rst @@ -1,7 +1,7 @@ Marvell CCU address decoding bindings ===================================== -CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs. +CCU configuration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs. The CCU node includes a description of the address decoding configuration. diff --git a/docs/plat/marvell/armada/misc/mvebu-io-win.rst b/docs/plat/marvell/armada/misc/mvebu-io-win.rst index 52845ca02..749829199 100644 --- a/docs/plat/marvell/armada/misc/mvebu-io-win.rst +++ b/docs/plat/marvell/armada/misc/mvebu-io-win.rst @@ -1,7 +1,7 @@ Marvell IO WIN address decoding bindings ======================================== -IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. +IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. The IO WIN includes a description of the address decoding configuration. diff --git a/docs/plat/marvell/armada/misc/mvebu-iob.rst b/docs/plat/marvell/armada/misc/mvebu-iob.rst index d02a7e84c..aa41822f4 100644 --- a/docs/plat/marvell/armada/misc/mvebu-iob.rst +++ b/docs/plat/marvell/armada/misc/mvebu-iob.rst @@ -1,7 +1,7 @@ Marvell IOB address decoding bindings ===================================== -IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs. +IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs. The IOB includes a description of the address decoding configuration. diff --git a/docs/plat/rpi4.rst b/docs/plat/rpi4.rst index beb0227c2..6e83fd730 100644 --- a/docs/plat/rpi4.rst +++ b/docs/plat/rpi4.rst @@ -60,7 +60,7 @@ As with the previous models, the GPU and its firmware are the first entity to run after the SoC gets its power. The on-chip Boot ROM loads the next stage (bootcode.bin) from flash (EEPROM), which is again GPU code. This part knows how to access the MMC controller and how to parse a FAT -filesystem, so it will load further compononents and configuration files +filesystem, so it will load further components and configuration files from the first FAT partition on the SD card. To accommodate this existing way of configuring and setting up the board, -- cgit v1.2.3 From 1cea02133f84148575687b0f2d0b953a01b9015d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 26 Jan 2021 10:44:07 +0100 Subject: docs: marvell: Update mv-ddr-marvell and A3700-utils-marvell branches MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Marvell finally started providing the latest version of mv-ddr-marvell and A3700-utils-marvell code in master branch of their git repositories. Reflect this in build instructions. Signed-off-by: Pali Rohár Change-Id: I08d1189dac60eb2a28335c68f611c1da634106f6 --- docs/plat/marvell/armada/build.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 29fe4d452..5135831f3 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -307,12 +307,12 @@ Armada37x0 Builds require installation of 3 components > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi (2) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv-ddr-devel" branch): + (use the "master" branch): https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git (3) Armada3700 tools available at the following repository - (use the "A3700_utils-armada-18.12-fixed" branch): + (use the "master" branch): https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git @@ -324,6 +324,6 @@ Armada70x0 and Armada80x0 Builds require installation of an additional component ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ (1) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv-ddr-devel" branch): + (use the "master" branch): https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git -- cgit v1.2.3 From 494be3ee0efbca70f4218d7eeb9af7225c9c1d58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 26 Jan 2021 10:44:07 +0100 Subject: docs: marvell: Update info about WTP and MV_DDR_PATH parameters MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Pali Rohár Change-Id: Id5e36b7ba3a840cb3598c580e806b52d8e8dd70f --- docs/plat/marvell/armada/build.rst | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 5135831f3..4995bb57e 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -123,6 +123,9 @@ There are several build options: For the mv_ddr source location, check the section "Tools and external components installation" + If MV_DDR_PATH source code is a git snapshot then provide path to the full git + repository (including .git subdir) because mv_ddr build process calls git commands. + - CP_NUM Total amount of CPs (South Bridge) connected to AP. When the parameter is omitted, @@ -194,6 +197,9 @@ There are several build options: directory, which can be found as a3700_utils.zip in the release. Usage example: ``WTP=/path/to/a3700_utils`` + If WTP source code is a git snapshot then provide path to the full git + repository (including .git subdir) because WTP build process calls git commands. + - CRYPTOPP_PATH For Armada37x0 only, use this parameter tp point to Crypto++ source code -- cgit v1.2.3 From 8708a884ae227f0d37618db7f50f6dd66cfaeaef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 26 Jan 2021 10:44:07 +0100 Subject: plat: marvell: armada: a3k: Allow use of the system Crypto++ library MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change introduces two new A3720 parameters, CRYPTOPP_LIBDIR and CRYPTOPP_INCDIR, which can be used to specify directory paths to pre-compiled Crypto++ library and header files. When both new parameters are specified then the source code of Crypto++ via CRYPTOPP_PATH parameter is not needed. And therefore it allows TF-A build process to use system Crypto++ library. Signed-off-by: Pali Rohár Change-Id: I6d440f86153373b11b8d098bb68eb7325e86b20b --- docs/plat/marvell/armada/build.rst | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 4995bb57e..d22477941 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -202,8 +202,21 @@ There are several build options: - CRYPTOPP_PATH - For Armada37x0 only, use this parameter tp point to Crypto++ source code - directory, which is required for building WTP image tool. + For Armada37x0 only, use this parameter to point to Crypto++ source code + directory. If this option is specified then Crypto++ source code in + CRYPTOPP_PATH directory will be automatically compiled. Crypto++ library + is required for building WTP image tool. Either CRYPTOPP_PATH or + CRYPTOPP_LIBDIR with CRYPTOPP_INCDIR needs to be specified for Armada37x0. + +- CRYPTOPP_LIBDIR + + For Armada37x0 only, use this parameter to point to the directory with + compiled Crypto++ library. By default it points to the CRYPTOPP_PATH. + +- CRYPTOPP_INCDIR + + For Armada37x0 only, use this parameter to point to the directory with + header files of Crypto++ library. By default it points to the CRYPTOPP_PATH. For example, in order to build the image in debug mode with log level up to 'notice' level run -- cgit v1.2.3 From 8b920973664fe73a84b608ba8922dc9da556a526 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 26 Jan 2021 10:44:07 +0100 Subject: plat: marvell: armada: a3k: Add a new target mrvl_uart which builds UART image MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change separates building of flash and UART images, so it is possible to build only one of these images. Also this change allows make to build them in parallel. Target mrvl_flash now builds only flash image and mrvl_uart only UART image. This change reflects it also in the documentation. Signed-off-by: Pali Rohár Change-Id: Ie9ce4538d52188dd26d99dfeeb5ad171a5b818f3 --- docs/plat/marvell/armada/build.rst | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index d22477941..750bf6682 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -236,7 +236,7 @@ line is as following MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 \ MV_DDR_PATH=/path/to/mv-ddr-marvell/ WTP=/path/to/A3700-utils-marvell/ \ CRYPTOPP_PATH=/path/to/cryptopp/ BL33=/path/to/u-boot.bin \ - all fip mrvl_bootimage mrvl_flash + all fip mrvl_bootimage mrvl_flash mrvl_uart To build just TF-A without WTMI image (useful for A3720 Turris MOX board), run following command: @@ -298,8 +298,9 @@ Marvell's TF-A compilation generates 8 files: for booting via UART. Could be loaded via Marvell's WtpDownload tool from A3700-utils-marvell repository. -Additional make target ``mrvl_bootimage`` produce ``boot-image.bin`` file and target -``mrvl_flash`` produce final ``flash-image.bin`` and ``uart-images.tgz.bin`` files. +Additional make target ``mrvl_bootimage`` produce ``boot-image.bin`` file. Target +``mrvl_flash`` produce final ``flash-image.bin`` file and target ``mrvl_uart`` +produce ``uart-images.tgz.bin`` file. Tools and external components installation -- cgit v1.2.3 From 33af2937cdaecbb65c74677aa68a9a0b39f59764 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 28 Jan 2021 13:09:36 +0100 Subject: docs: marvell: Update info about BOOTDEV=SATA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Information is taken from the post https://lists.denx.de/pipermail/u-boot/2017-July/299351.html Signed-off-by: Pali Rohár Change-Id: I5f608e135ec56685a3e2b986a52670540d48a4bf --- docs/plat/marvell/armada/build.rst | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 10d30aec9..ae67ab0b0 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -174,6 +174,10 @@ There are several build options: - SATA - SATA device boot + Image needs to be stored at disk LBA 0 or at disk partition with + MBR type 0x4d (ASCII 'M' as in Marvell) or at disk partition with + GPT name ``MARVELL BOOT PARTITION``. + - PARTNUM For Armada37x0 only, the boot partition number, default is 0. -- cgit v1.2.3 From 711a6bb79bf17203607507b004266db661e96ab5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 27 Jan 2021 18:04:32 +0100 Subject: docs: marvell: Update info about WTMI_IMG option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Default WTMI_IMG value was documented incorrectly. Also WTMI_IMG name may be misleading as this option does not specify full WTMI image, just a main loop (e.g. fuse.bin or custom RTOS image) without hardware initialization code (DDR, CPU and clocks). Signed-off-by: Pali Rohár Change-Id: I3de4a27ce2165b962fa628c992fd8f80151efd7c --- docs/plat/marvell/armada/build.rst | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 750bf6682..10d30aec9 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -185,12 +185,17 @@ There are several build options: - WTMI_IMG - For Armada37x0 only, the path of the WTMI image can point to an image which + For Armada37x0 only, the path of the binary can point to an image which does nothing, an image which supports EFUSE or a customized CM3 firmware - binary. The default image is wtmi.bin that built from sources in WTP + binary. The default image is ``fuse.bin`` that built from sources in WTP folder, which is the next option. If the default image is OK, then this option should be skipped. + Please note that this is not a full WTMI image, just a main loop without + hardware initialization code. Final WTMI image is built from this WTMI_IMG + binary and sys-init code from the WTP directory which sets DDR and CPU + clocks according to DDR_TOPOLOGY and CLOCKSPRESET options. + - WTP For Armada37x0 only, use this parameter to point to wtptools source code -- cgit v1.2.3 From 24e6e10b996ff000733ae7ac4b0e835b5babd0f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 1 Feb 2021 12:22:37 +0100 Subject: docs: marvell: Move Supported Marvell platforms to PLAT build option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reformat list of boards, remove unsupported OcteonTX2 and mention supported Turris MOX board. Signed-off-by: Pali Rohár Change-Id: I22cea7f77fd078554c7f0ed4108781626209e563 --- docs/plat/marvell/armada/build.rst | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 29fe4d452..a7181c7c7 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -51,6 +51,18 @@ Install ARM 32-bit cross compiler, which is required for building WTMI image for There are several build options: +- PLAT + + Supported Marvell platforms are: + + - a3700 - A3720 DB, EspressoBin and Turris MOX + - a70x0 + - a70x0_amc - AMC board + - a80x0 + - a80x0_mcbin - MacchiatoBin + - a80x0_puzzle - IEI Puzzle-M801 + - t9130 - CN913x + - DEBUG Default is without debug information (=0). in order to enable it use ``DEBUG=1``. @@ -236,15 +248,6 @@ You can build TF-A for the Globalscale ESPRESSObin-Ultra board (DDR4, 1 GB) by r CRYPTOPP_PATH=/path/to/cryptopp/ BL33=/path/to/u-boot.bin \ all fip mrvl_bootimage mrvl_flash -Supported MARVELL_PLATFORM are: - - a3700 (for both A3720 DB and EspressoBin) - - a70x0 - - a70x0_amc (for AMC board) - - a80x0 - - a80x0_mcbin (for MacchiatoBin) - - a80x0_puzzle (for IEI Puzzle-M801) - - t9130 (OcteonTX2 CN913x) - Special Build Flags -------------------- -- cgit v1.2.3 From 9c3fffdc8673db8038608cba515931aac298f7e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 1 Feb 2021 12:23:31 +0100 Subject: docs: marvell: Reformat DDR_TOPOLOGY option and mention EspressoBin-Ultra board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Pali Rohár Change-Id: I96c2d9d5bc6c69a1a66a29bf586a23375d63ab5a --- docs/plat/marvell/armada/build.rst | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index a7181c7c7..2715f2601 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -148,15 +148,15 @@ There are several build options: For Armada37x0 only, the DDR topology map index/name, default is 0. Supported Options: - - 0 - DDR3 1CS: DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) - - 1 - DDR4 1CS: DB-88F3720-DDR4-Modular (512MB) - - 2 - DDR3 2CS: EspressoBIN V3-V5 (1GB 2CS) - - 3 - DDR4 2CS: DB-88F3720-DDR4-Modular (4GB) - - 4 - DDR3 1CS: DB-88F3720-DDR3-Modular (1GB); EspressoBIN V3-V5 (1GB 1CS) - - 5 - DDR4 1CS: EspressoBin V7 (1GB) - - 6 - DDR4 2CS: EspressoBin V7 (2GB) - - 7 - DDR3 2CS: EspressoBin V3-V5 (2GB) - - CUST - CUSTOMER: Customer board, DDR3 1CS 512MB + - 0 - DDR3 1CS 512MB (DB-88F3720-DDR3-Modular, EspressoBin V3-V5) + - 1 - DDR4 1CS 512MB (DB-88F3720-DDR4-Modular) + - 2 - DDR3 2CS 1GB (EspressoBin V3-V5) + - 3 - DDR4 2CS 4GB (DB-88F3720-DDR4-Modular) + - 4 - DDR3 1CS 1GB (DB-88F3720-DDR3-Modular, EspressoBin V3-V5) + - 5 - DDR4 1CS 1GB (EspressoBin V7, EspressoBin-Ultra) + - 6 - DDR4 2CS 2GB (EspressoBin V7) + - 7 - DDR3 2CS 2GB (EspressoBin V3-V5) + - CUST - CUSTOMER BOARD (Customer board settings) - CLOCKSPRESET -- cgit v1.2.3 From 23abf07ce46b897a9460aea88eb3e8a0bc67a0b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 1 Feb 2021 12:24:42 +0100 Subject: docs: marvell: Add information into CLOCKSPRESET option how to identify CPU frequency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Pali Rohár Change-Id: I5310c30051703bbf9f377762a00eb6a8188c6fa1 --- docs/plat/marvell/armada/build.rst | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 2715f2601..a4116cd4e 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -168,6 +168,13 @@ There are several build options: - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz + Look at Armada37x0 chip package marking on board to identify correct CPU frequency. + The last line on package marking (next line after the 88F37x0 line) should contain: + + - C080 or I080 - chip with 800 MHz CPU - use ``CLOCKSPRESET=CPU_800_DDR_800`` + - C100 or I100 - chip with 1000 MHz CPU - use ``CLOCKSPRESET=CPU_1000_DDR_800`` + - C120 - chip with 1200 MHz CPU - use ``CLOCKSPRESET=CPU_1200_DDR_750`` + - BOOTDEV For Armada37x0 only, the flash boot device, default is ``SPINOR``. -- cgit v1.2.3 From f60f1e848dfdbc8180b323187630ef866318647a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 1 Feb 2021 12:25:46 +0100 Subject: docs: marvell: Fix description of flash-image.bin image MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Pali Rohár Change-Id: I192acab2a7f42cd80069faeac2d7823a05558dc6 --- docs/plat/marvell/armada/build.rst | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index a4116cd4e..7793af47d 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -277,14 +277,15 @@ Build output ------------ Marvell's TF-A compilation generates 8 files: - - ble.bin - BLe image + - ble.bin - BLe image (not available for Armada37x0) - bl1.bin - BL1 image - bl2.bin - BL2 image - bl31.bin - BL31 image - fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images) - boot-image.bin - TF-A image (contains BL1 and FIP images) - - flash-image.bin - Image which contains boot-image.bin and SPL image. - Should be placed on the boot flash/device. + - flash-image.bin - Flashable Marvell firmware image. For Armada37x0 it + contains TIM, WTMI and boot-image.bin images. For other platforms it contains + BLe and boot-image.bin images. Should be placed on the boot flash/device. - uart-images.tgz.bin - GZIPed TAR archive which contains Armada37x0 images for booting via UART. Could be loaded via Marvell's WtpDownload tool from A3700-utils-marvell repository. -- cgit v1.2.3 From ff46a41dc27a2bb9813842c918eca295c18f070b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 1 Feb 2021 12:32:36 +0100 Subject: docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example how to build production release of Marvell firmware image MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ESPRESSObin-Ultra TF-A build example was now just a copy+paste of previous mentioned example. It produced debug binary with custom log level, which was not described. So rather replace this duplicate build example by a full example with all steps how to build production release of Marvell firmware image for EspressoBin with 1GHz CPU and 1GB DDR4 RAM. Signed-off-by: Pali Rohár Change-Id: Ief1b8bc96a3035ebd8421bd68dca5eb5c8d8fd52 --- docs/plat/marvell/armada/build.rst | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'docs/plat') diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index 7793af47d..8001c3613 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -245,15 +245,24 @@ To build just TF-A without WTMI image (useful for A3720 Turris MOX board), run f > make USE_COHERENT_MEM=0 PLAT=a3700 CM3_SYSTEM_RESET=1 BL33=/path/to/u-boot.bin \ CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage -You can build TF-A for the Globalscale ESPRESSObin-Ultra board (DDR4, 1 GB) by running the following command: +Here is full example how to build production release of Marvell firmware image (concatenated +binary of Marvell secure firmware, TF-A and U-Boot) for EspressoBin board (PLAT=a3700) with +1GHz CPU (CLOCKSPRESET=CPU_1000_DDR_800) and 1GB DDR4 RAM (DDR_TOPOLOGY=5): .. code:: shell - > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1200_DDR_750 \ - MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=5 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 \ - MV_DDR_PATH=/path/to/mv-ddr-marvell/ WTP=/path/to/A3700-utils-marvell/ \ - CRYPTOPP_PATH=/path/to/cryptopp/ BL33=/path/to/u-boot.bin \ - all fip mrvl_bootimage mrvl_flash + > git clone https://review.trustedfirmware.org/TF-A/trusted-firmware-a + > git clone https://gitlab.denx.de/u-boot/u-boot.git + > git clone https://github.com/weidai11/cryptopp.git + > git clone https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git -b master + > git clone https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git -b master + > make -C u-boot CROSS_COMPILE=aarch64-linux-gnu- mvebu_espressobin-88f3720_defconfig u-boot.bin + > make -C trusted-firmware-a CROSS_COMPILE=aarch64-linux-gnu- CROSS_CM3=arm-linux-gnueabi- \ + USE_COHERENT_MEM=0 PLAT=a3700 CLOCKSPRESET=CPU_1000_DDR_800 DDR_TOPOLOGY=5 \ + MV_DDR_PATH=$PWD/mv-ddr-marvell/ WTP=$PWD/A3700-utils-marvell/ CRYPTOPP_PATH=$PWD/cryptopp/ \ + BL33=$PWD/u-boot/u-boot.bin mrvl_flash + +Produced Marvell firmware flash image: ``trusted-firmware-a/build/a3700/release/flash-image.bin`` Special Build Flags -------------------- -- cgit v1.2.3 From d30a6615d1cc267164b3bf6d71e0e15b2ec4f8a1 Mon Sep 17 00:00:00 2001 From: Manish V Badarkhe Date: Sun, 24 Jan 2021 20:39:39 +0000 Subject: doc: Build option to protect GICR frame Added a build option 'FVP_GICR_REGION_PROTECTION' to make redistributor frame of fused/unused cores as read only. Change-Id: Ie85f86e2465b93321a92a888ce8712a3144e4ccb Signed-off-by: Manish V Badarkhe --- docs/plat/arm/fvp/index.rst | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'docs/plat') diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index ea72962e8..235b7b687 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -142,6 +142,11 @@ Arm FVP Platform Specific Build Options HW_CONFIG blob instead of the DTS file. This option is useful to override the default HW_CONFIG selected by the build system. +- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of + inactive/fused CPU cores as read-only. The default value of this option + is ``0``, which means the redistributor pages of all CPU cores are marked + as read and write. + Booting Firmware Update images ------------------------------ -- cgit v1.2.3