From fea24b88e40e899bb7d0e15362c46a7154b76b71 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 30 Jul 2019 22:18:17 +0800 Subject: intel: stratix10: Fix reliance on hard coded clock information Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by: Hadi Asyrafi Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03 --- plat/intel/soc/stratix10/bl2_plat_setup.c | 6 +- .../soc/stratix10/include/s10_clock_manager.h | 22 ++-- .../soc/stratix10/include/s10_system_manager.h | 3 + .../soc/stratix10/include/stratix10_private.h | 4 +- plat/intel/soc/stratix10/soc/s10_clock_manager.c | 126 +++++++++++++++++---- 5 files changed, 120 insertions(+), 41 deletions(-) diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 8e8b582fc..f24bbdec4 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -73,9 +73,9 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, deassert_peripheral_reset(); config_hps_hs_before_warm_reset(); - watchdog_init(get_wdt_clk(&reverse_handoff_ptr)); + watchdog_init(get_wdt_clk()); - console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, + console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, &console); socfpga_delay_timer_init(); @@ -107,7 +107,7 @@ void bl2_el3_plat_arch_setup(void) enable_mmu_el3(0); - dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000); + dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); info.mmc_dev_type = MMC_IS_SD; info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; diff --git a/plat/intel/soc/stratix10/include/s10_clock_manager.h b/plat/intel/soc/stratix10/include/s10_clock_manager.h index 99eb7a6c3..c800b9cf7 100644 --- a/plat/intel/soc/stratix10/include/s10_clock_manager.h +++ b/plat/intel/soc/stratix10/include/s10_clock_manager.h @@ -50,10 +50,13 @@ #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff) #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00) -#define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC(x) (((x) & 0x00030000) >> 16) -#define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1 0x0 -#define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC 0x1 -#define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S 0x2 +#define ALT_CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) +#define ALT_CLKMGR_SRC_MAIN 0 +#define ALT_CLKMGR_SRC_PER 1 + +#define ALT_CLKMGR_PLLGLOB_PSRC_EOSC1 0x0 +#define ALT_CLKMGR_PLLGLOB_PSRC_INTOSC 0x1 +#define ALT_CLKMGR_PLLGLOB_PSRC_F2S 0x2 #define ALT_CLKMGR_PERPLL 0xffd100a4 #define ALT_CLKMGR_PERPLL_EN 0x0 @@ -83,14 +86,11 @@ #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00) #define ALT_CLKMGR_PERPLL_VCOCALIB 0x58 - -typedef struct { - uint32_t clk_freq_of_eosc1; - uint32_t clk_freq_of_f2h_free; - uint32_t clk_freq_of_cb_intosc_ls; -} CLOCK_SOURCE_CONFIG; +#define ALT_CLKMGR_INTOSC_HZ 460000000 void config_clkmgr_handoff(handoff *hoff_ptr); -int get_wdt_clk(handoff *hoff_ptr); +uint32_t get_wdt_clk(void); +uint32_t get_uart_clk(void); +uint32_t get_mmc_clk(void); #endif diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h index 4500c6fbd..a67d689fa 100644 --- a/plat/intel/soc/stratix10/include/s10_system_manager.h +++ b/plat/intel/soc/stratix10/include/s10_system_manager.h @@ -62,6 +62,9 @@ #define S10_SYSMGR_CORE(x) (0xffd12000 + (x)) #define SYSMGR_MMC 0x28 #define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0) +#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 +#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 +#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 #define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) diff --git a/plat/intel/soc/stratix10/include/stratix10_private.h b/plat/intel/soc/stratix10/include/stratix10_private.h index f437202fa..85aff3aa7 100644 --- a/plat/intel/soc/stratix10/include/stratix10_private.h +++ b/plat/intel/soc/stratix10/include/stratix10_private.h @@ -10,9 +10,9 @@ #define S10_MMC_REG_BASE 0xff808000 #define EMMC_DESC_SIZE (1<<20) -#define EMMC_INIT_PARAMS(base) \ +#define EMMC_INIT_PARAMS(base, clk) \ { .bus_width = MMC_BUS_WIDTH_4, \ - .clk_rate = 50000000, \ + .clk_rate = (clk), \ .desc_base = (base), \ .desc_size = EMMC_DESC_SIZE, \ .flags = 0, \ diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c index b4d057354..ed65c2ba8 100644 --- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c @@ -13,15 +13,8 @@ #include "s10_clock_manager.h" #include "s10_handoff.h" +#include "s10_system_manager.h" -static const CLOCK_SOURCE_CONFIG clk_source = { - /* clk_freq_of_eosc1 */ - (uint32_t) 25000000, - /* clk_freq_of_f2h_free */ - (uint32_t) 460000000, - /* clk_freq_of_cb_intosc_ls */ - (uint32_t) 50000000, -}; void wait_pll_lock(void) { @@ -195,24 +188,32 @@ void config_clkmgr_handoff(handoff *hoff_ptr) mmio_write_32(ALT_CLKMGR + ALT_CLKMGR_INTRCLR, ALT_CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK | ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK); + + /* Pass clock source frequency into scratch register */ + mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1), + hoff_ptr->hps_osc_clk_h); + mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2), + hoff_ptr->fpga_clk_hz); + } -int get_wdt_clk(handoff *hoff_ptr) +/* Extract reference clock from platform clock source */ +uint32_t get_ref_clk(uint32_t pllglob) { - int main_noc_base_clk, l3_main_free_clk, l4_sys_free_clk; - int data32, mdiv, refclkdiv, ref_clk; + uint32_t data32, mdiv, refclkdiv, ref_clk; + uint32_t scr_reg; - data32 = mmio_read_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB); - - switch (ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC(data32)) { - case ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1: - ref_clk = clk_source.clk_freq_of_eosc1; + switch (ALT_CLKMGR_PSRC(pllglob)) { + case ALT_CLKMGR_PLLGLOB_PSRC_EOSC1: + scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1); + ref_clk = mmio_read_32(scr_reg); break; - case ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC: - ref_clk = clk_source.clk_freq_of_cb_intosc_ls; + case ALT_CLKMGR_PLLGLOB_PSRC_INTOSC: + ref_clk = ALT_CLKMGR_INTOSC_HZ; break; - case ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S: - ref_clk = clk_source.clk_freq_of_f2h_free; + case ALT_CLKMGR_PLLGLOB_PSRC_F2S: + scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2); + ref_clk = mmio_read_32(scr_reg); break; default: ref_clk = 0; @@ -220,14 +221,89 @@ int get_wdt_clk(handoff *hoff_ptr) break; } - refclkdiv = ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(data32); + refclkdiv = ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(pllglob); data32 = mmio_read_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_FDBCK); mdiv = ALT_CLKMGR_MAINPLL_FDBCK_MDIV(data32); + ref_clk = (ref_clk / refclkdiv) * (6 + mdiv); - main_noc_base_clk = ref_clk / (hoff_ptr->main_pll_pllc1 & 0xff); - l3_main_free_clk = main_noc_base_clk / (hoff_ptr->main_pll_nocclk + 1); - l4_sys_free_clk = l3_main_free_clk / 4; + return ref_clk; +} + +/* Calculate L3 interconnect main clock */ +uint32_t get_l3_clk(uint32_t ref_clk) +{ + uint32_t noc_base_clk, l3_clk, noc_clk, data32; + uint32_t pllc1_reg; + + noc_clk = mmio_read_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCCLK); + + switch (ALT_CLKMGR_PSRC(noc_clk)) { + case ALT_CLKMGR_SRC_MAIN: + pllc1_reg = ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC1; + break; + case ALT_CLKMGR_SRC_PER: + pllc1_reg = ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLC1; + break; + default: + pllc1_reg = 0; + assert(0); + break; + } + + data32 = mmio_read_32(pllc1_reg); + noc_base_clk = ref_clk / (data32 & 0xff); + l3_clk = noc_base_clk / (noc_clk + 1); + + return l3_clk; +} + +/* Calculate clock frequency to be used for watchdog timer */ +uint32_t get_wdt_clk(void) +{ + uint32_t data32, ref_clk, l3_clk, l4_sys_clk; + + data32 = mmio_read_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB); + ref_clk = get_ref_clk(data32); + + l3_clk = get_l3_clk(ref_clk); + + l4_sys_clk = l3_clk / 4; + + return l4_sys_clk; +} + +/* Calculate clock frequency to be used for UART driver */ +uint32_t get_uart_clk(void) +{ + uint32_t data32, ref_clk, l3_clk, l4_sp_clk; + + data32 = mmio_read_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLGLOB); + ref_clk = get_ref_clk(data32); + + l3_clk = get_l3_clk(ref_clk); + + data32 = mmio_read_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCDIV); + data32 = (data32 >> 16) & 0x3; + data32 = 1 << data32; + + l4_sp_clk = (l3_clk / data32); + + return l4_sp_clk; +} + +/* Calculate clock frequency to be used for SDMMC driver */ +uint32_t get_mmc_clk(void) +{ + uint32_t data32, ref_clk, l3_clk, mmc_clk; + + data32 = mmio_read_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLGLOB); + ref_clk = get_ref_clk(data32); + + l3_clk = get_l3_clk(ref_clk); + + data32 = mmio_read_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR6CLK); + mmc_clk = (l3_clk / (data32 + 1)) / 4; - return l4_sys_free_clk; + return mmc_clk; } -- cgit v1.2.3 From 8075fc5910113cb1838c84a8595654512c142e19 Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Mon, 29 Jul 2019 10:40:17 +0100 Subject: Juno: add basic support for dynamic config Add the disable_auth dynamic parameter, that allows to disable the authentication when TBBR is enabled. This parameter is for development only. Change-Id: Ic24ad16738517f7e07c4f506dcf69a1ae8df7d2d Signed-off-by: Louis Mayencourt --- plat/arm/board/juno/fdts/juno_tb_fw_config.dts | 14 ++++++++++++++ plat/arm/board/juno/platform.mk | 8 +++++++- 2 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 plat/arm/board/juno/fdts/juno_tb_fw_config.dts diff --git a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts new file mode 100644 index 000000000..b16f5ccc4 --- /dev/null +++ b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +/ { + /* Platform Config */ + compatible = "arm,tb_fw"; + /* Disable authentication for development */ + disable_auth = <0x0>; +}; diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index ea7f85172..bd6bae536 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk @@ -150,8 +150,14 @@ else endif endif +# Add the FDT_SOURCES and options for Dynamic Config +FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts +TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb + +# Add the TB_FW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config)) + include plat/arm/board/common/board_common.mk include plat/arm/common/arm_common.mk include plat/arm/soc/common/soc_css.mk include plat/arm/css/common/css_common.mk - -- cgit v1.2.3 From 9580f9bdc24e2c493d338256f3cbf2ee9dc79c4f Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Wed, 31 Jul 2019 15:03:44 +0100 Subject: Juno: Use shared mbedtls heap between bl1 and bl2 Change-Id: Ia1ecad58ebf9de3f3a44b17ad1de57424b431125 Signed-off-by: Louis Mayencourt --- plat/arm/board/juno/fdts/juno_tb_fw_config.dts | 11 +++++++++++ plat/arm/board/juno/juno_common.c | 5 ++++- plat/arm/board/juno/juno_security.c | 6 +++++- 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts index b16f5ccc4..a8ab6c5f9 100644 --- a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts +++ b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts @@ -11,4 +11,15 @@ compatible = "arm,tb_fw"; /* Disable authentication for development */ disable_auth = <0x0>; + /* + * The following two entries are placeholders for Mbed TLS + * heap information. The default values don't matter since + * they will be overwritten by BL1. + * In case of having shared Mbed TLS heap between BL1 and BL2, + * BL1 will populate these two properties with the respective + * info about the shared heap. This info will be available for + * BL2 in order to locate and re-use the heap. + */ + mbedtls_heap_addr = <0x0 0x0>; + mbedtls_heap_size = <0x0>; }; diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c index 118c19ab7..be9f32bd1 100644 --- a/plat/arm/board/juno/juno_common.c +++ b/plat/arm/board/juno/juno_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,6 +46,9 @@ const mmap_region_t plat_arm_mmap[] = { #ifdef SPD_opteed ARM_MAP_OPTEE_CORE_MEM, ARM_OPTEE_PAGEABLE_LOAD_MEM, +#endif +#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3 + ARM_MAP_BL1_RW, #endif {0} }; diff --git a/plat/arm/board/juno/juno_security.c b/plat/arm/board/juno/juno_security.c index 6566b15c8..32823e01c 100644 --- a/plat/arm/board/juno/juno_security.c +++ b/plat/arm/board/juno/juno_security.c @@ -3,6 +3,7 @@ * * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include @@ -149,6 +150,9 @@ void plat_arm_security_setup(void) #if TRUSTED_BOARD_BOOT int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) { - return get_mbedtls_heap_helper(heap_addr, heap_size); + assert(heap_addr != NULL); + assert(heap_size != NULL); + + return arm_get_mbedtls_heap(heap_addr, heap_size); } #endif -- cgit v1.2.3 From 544c092b9c77ebe8c23f0fee96e3342dd80f5a6d Mon Sep 17 00:00:00 2001 From: Ambroise Vincent Date: Wed, 29 May 2019 14:04:16 +0100 Subject: tegra: add support for multi console interface This patch updates all Tegra platforms to use the new multi console API. Change-Id: I27c0c7830a86e26491dea9991a689f0b01e4dbf0 Signed-off-by: Ambroise Vincent Signed-off-by: Julius Werner --- plat/nvidia/tegra/common/aarch64/tegra_helpers.S | 45 +------- .../tegra/common/drivers/spe/shared_console.S | 113 ++++++++++++++------- plat/nvidia/tegra/common/tegra_bl31_setup.c | 18 ++-- plat/nvidia/tegra/common/tegra_common.mk | 4 +- plat/nvidia/tegra/common/tegra_pm.c | 21 +--- plat/nvidia/tegra/include/tegra_private.h | 3 +- 6 files changed, 95 insertions(+), 109 deletions(-) diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index b47be6dc4..13ca6aaa2 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -218,49 +218,6 @@ func platform_mem_init ret endfunc platform_mem_init - /* --------------------------------------------- - * int plat_crash_console_init(void) - * Function to initialize the crash console - * without a C Runtime to print crash report. - * Clobber list : x0 - x4 - * --------------------------------------------- - */ -func plat_crash_console_init - mov x0, #0 - adr x1, tegra_console_base - ldr x1, [x1] - cbz x1, 1f - mov w0, #1 -1: ret -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(void) - * Function to print a character on the crash - * console without a C Runtime. - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - adr x1, tegra_console_base - ldr x1, [x1] - b console_core_putc -endfunc plat_crash_console_putc - - /* --------------------------------------------- - * int plat_crash_console_flush() - * Function to force a write of all buffered - * data that hasn't been output. - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func plat_crash_console_flush - adr x0, tegra_console_base - ldr x0, [x0] - b console_core_flush -endfunc plat_crash_console_flush - /* --------------------------------------------------- * Function to handle a platform reset and store * input parameters passed by BL2. diff --git a/plat/nvidia/tegra/common/drivers/spe/shared_console.S b/plat/nvidia/tegra/common/drivers/spe/shared_console.S index c1fbc842f..a3e110ec9 100644 --- a/plat/nvidia/tegra/common/drivers/spe/shared_console.S +++ b/plat/nvidia/tegra/common/drivers/spe/shared_console.S @@ -1,9 +1,10 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include +#include #define CONSOLE_NUM_BYTES_SHIFT 24 #define CONSOLE_FLUSH_DATA_TO_PORT (1 << 26) @@ -20,37 +21,43 @@ * finally displays everything on the UART port. */ - .globl console_core_init - .globl console_core_putc - .globl console_core_getc - .globl console_core_flush - - /* ----------------------------------------------- - * int console_core_init(uintptr_t base_addr, - * unsigned int uart_clk, unsigned int baud_rate) - * Function to initialize the console without a - * C Runtime to print debug information. This - * function will be accessed by console_init and - * crash reporting. - * In: x0 - console base address - * w1 - Uart clock in Hz + .globl console_spe_core_init + .globl console_spe_core_putc + .globl console_spe_core_getc + .globl console_spe_core_flush + .globl console_spe_putc + .globl console_spe_getc + .globl console_spe_flush + .globl console_spe_register + + /* ------------------------------------------------- + * int console_spe_register(uintptr_t baseaddr, + * uint32_t clock, uint32_t baud, + * console_spe_t *console); + * Function to initialize and register a new spe + * console. Storage passed in for the console struct + * *must* be persistent (i.e. not from the stack). + * In: x0 - UART register base address + * w1 - UART clock in Hz * w2 - Baud rate - * Out: return 1 on success else 0 on error - * Clobber list : x1, x2 - * ----------------------------------------------- + * x3 - pointer to empty console_spe_t struct + * Out: return 1 on success, 0 on error + * Clobber list : x0, x1, x2, x6, x7, x14 + * ------------------------------------------------- */ -func console_core_init - /* Check the input base address */ - cbz x0, core_init_fail - mov w0, #1 - ret -core_init_fail: +func console_spe_register + cbz x3, register_fail + str x0, [x3, #CONSOLE_T_DRVDATA] + mov x0, x3 + finish_console_register spe putc=1, getc=1, flush=1 + +register_fail: mov w0, wzr ret -endfunc console_core_init +endfunc console_spe_register /* -------------------------------------------------------- - * int console_core_putc(int c, uintptr_t base_addr) + * int console_spe_core_putc(int c, uintptr_t base_addr) * Function to output a character over the console. It * returns the character printed on success or -1 on error. * In : w0 - character to be printed @@ -59,7 +66,7 @@ endfunc console_core_init * Clobber list : x2 * -------------------------------------------------------- */ -func console_core_putc +func console_spe_core_putc /* Check the input parameter */ cbz x1, putc_error @@ -95,32 +102,48 @@ func console_core_putc putc_error: mov w0, #-1 ret -endfunc console_core_putc +endfunc console_spe_core_putc + + /* -------------------------------------------------------- + * int console_spe_putc(int c, console_spe_t *console) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - pointer to console_t structure + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_spe_putc + ldr x1, [x1, #CONSOLE_T_DRVDATA] + b console_spe_core_putc +endfunc console_spe_putc /* --------------------------------------------- - * int console_core_getc(uintptr_t base_addr) + * int console_spe_getc(console_spe_t *console) * Function to get a character from the console. * It returns the character grabbed on success - * or -1 on error. - * In : x0 - console base address + * or -1 if no character is available. + * In : x0 - pointer to console_t structure + * Out: w0 - character if available, else -1 * Clobber list : x0, x1 * --------------------------------------------- */ -func console_core_getc +func console_spe_getc mov w0, #-1 ret -endfunc console_core_getc +endfunc console_spe_getc - /* --------------------------------------------- - * int console_core_flush(uintptr_t base_addr) + /* ------------------------------------------------- + * int console_spe_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address * Out : return -1 on error else return 0. * Clobber list : x0, x1 - * --------------------------------------------- + * ------------------------------------------------- */ -func console_core_flush +func console_spe_core_flush cbz x0, flush_error /* flush console */ @@ -131,4 +154,18 @@ func console_core_flush flush_error: mov w0, #-1 ret -endfunc console_core_flush +endfunc console_spe_core_flush + + /* --------------------------------------------- + * int console_spe_flush(console_spe_t *console) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - pointer to console_t structure + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_spe_flush + ldr x0, [x0, #CONSOLE_T_DRVDATA] + b console_spe_core_flush +endfunc console_spe_flush diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index a9d037f19..f89e77a34 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -49,7 +49,6 @@ IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START); IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END); extern uint64_t tegra_bl31_phys_base; -extern uint64_t tegra_console_base; static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { @@ -130,9 +129,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; image_info_t bl32_img_info = { {0} }; - uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; + uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end, console_base; uint32_t console_clock; int32_t ret; + static console_16550_t console; /* * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so @@ -194,14 +194,18 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, * Get the base address of the UART controller to be used for the * console */ - tegra_console_base = plat_get_console_from_id(plat_params->uart_id); + console_base = plat_get_console_from_id(plat_params->uart_id); - if (tegra_console_base != 0U) { + if (console_base != 0U) { /* * Configure the UART port to be used as the console */ - (void)console_init(tegra_console_base, console_clock, - TEGRA_CONSOLE_BAUDRATE); + (void)console_16550_register(console_base, + console_clock, + TEGRA_CONSOLE_BAUDRATE, + &console); + console_set_scope(&console.console, CONSOLE_FLAG_BOOT | + CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); } /* diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk index 2a2f2782d..34b5638ec 100644 --- a/plat/nvidia/tegra/common/tegra_common.mk +++ b/plat/nvidia/tegra/common/tegra_common.mk @@ -20,9 +20,9 @@ TEGRA_GICv2_SOURCES := drivers/arm/gic/common/gic_common.c \ plat/common/plat_gicv2.c \ ${COMMON_DIR}/tegra_gicv2.c -BL31_SOURCES += drivers/console/aarch64/console.S \ - drivers/delay_timer/delay_timer.c \ +BL31_SOURCES += drivers/delay_timer/delay_timer.c \ drivers/io/io_storage.c \ + plat/common/aarch64/crash_console_helpers.S \ ${TEGRA_GICv2_SOURCES} \ ${COMMON_DIR}/aarch64/tegra_helpers.S \ ${COMMON_DIR}/drivers/pmc/pmc.c \ diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index e06a116e4..8ba02d6f5 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -26,7 +26,6 @@ extern uint64_t tegra_bl31_phys_base; extern uint64_t tegra_sec_entry_point; -extern uint64_t tegra_console_base; /* * tegra_fake_system_suspend acts as a boolean var controlling whether @@ -219,7 +218,8 @@ void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) /* Disable console if we are entering deep sleep. */ if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == PSTATE_ID_SOC_POWERDN) { - (void)console_uninit(); + (void)console_flush(); + console_switch_state(0); } /* disable GICC */ @@ -269,7 +269,6 @@ __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) { const plat_params_from_bl2_t *plat_params; - uint32_t console_clock; /* * Initialize the GIC cpu and distributor interfaces @@ -282,20 +281,8 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == PSTATE_ID_SOC_POWERDN) { - /* - * Reference clock used by the FPGAs is a lot slower. - */ - if (tegra_platform_is_fpga()) { - console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; - } else { - console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; - } - - /* Initialize the runtime console */ - if (tegra_console_base != 0ULL) { - (void)console_init(tegra_console_base, console_clock, - TEGRA_CONSOLE_BAUDRATE); - } + /* Restart console output. */ + console_switch_state(CONSOLE_FLAG_RUNTIME); /* * Restore Memory Controller settings as it loses state diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index cdd9e08c1..34a096cfb 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,7 @@ #include #include +#include #include #include -- cgit v1.2.3 From ef430ff495aaf1c4bb5142570761351c6fe4b402 Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Mon, 29 Jul 2019 17:22:53 +0100 Subject: FVP_Base_AEMv8A platform: Fix cache maintenance operations This patch fixes FVP_Base_AEMv8A model hang issue with ARMv8.4+ with cache modelling enabled configuration. Incorrect L1 cache flush operation to PoU, using CLIDR_EL1 LoUIS field, which is required by the architecture to be zero for ARMv8.4-A with ARMv8.4-S2FWB feature is replaced with L1 to L2 and L2 to L3 (if L3 is present) cache flushes. FVP_Base_AEMv8A model can be configured with L3 enabled by setting `cluster0.l3cache-size` and `cluster1.l3cache-size` to non-zero values, and presence of L3 is checked in `aem_generic_core_pwr_dwn` function by reading CLIDR_EL1.Ctype3 field value. Change-Id: If3de3d4eb5ed409e5b4ccdbc2fe6d5a01894a9af Signed-off-by: Alexei Fedorov --- include/arch/aarch64/arch.h | 1 + lib/cpus/aarch64/aem_generic.S | 38 +++++++++++++++++++++++++++++++++----- 2 files changed, 34 insertions(+), 5 deletions(-) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index fa857fb1b..2b4ae1ad7 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -112,6 +112,7 @@ /* CLIDR definitions */ #define LOUIS_SHIFT U(21) #define LOC_SHIFT U(24) +#define CTYPE_SHIFT(n) U(3 * (n - 1)) #define CLIDR_FIELD_WIDTH U(3) /* CSSELR definitions */ diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S index 51b5ce91c..6291e43e1 100644 --- a/lib/cpus/aarch64/aem_generic.S +++ b/lib/cpus/aarch64/aem_generic.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,15 +18,43 @@ func aem_generic_core_pwr_dwn msr sctlr_el3, x1 isb + /* --------------------------------------------- + * AEM model supports L3 caches in which case L2 + * will be private per core caches and flush + * from L1 to L2 is not sufficient. + * --------------------------------------------- + */ + mrs x1, clidr_el1 + + /* --------------------------------------------- + * Check if L3 cache is implemented. + * --------------------------------------------- + */ + tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3) + + /* --------------------------------------------- + * There is no L3 cache, flush L1 to L2 only. + * --------------------------------------------- + */ mov x0, #DCCISW + b.eq dcsw_op_level1 + + mov x18, x30 /* --------------------------------------------- - * Flush L1 cache to PoU. + * Flush L1 cache to L2. * --------------------------------------------- */ - b dcsw_op_louis -endfunc aem_generic_core_pwr_dwn + bl dcsw_op_level1 + mov x30, x18 + /* --------------------------------------------- + * Flush L2 cache to L3. + * --------------------------------------------- + */ + mov x0, #DCCISW + b dcsw_op_level2 +endfunc aem_generic_core_pwr_dwn func aem_generic_cluster_pwr_dwn /* --------------------------------------------- @@ -39,7 +67,7 @@ func aem_generic_cluster_pwr_dwn isb /* --------------------------------------------- - * Flush L1 and L2 caches to PoC. + * Flush all caches to PoC. * --------------------------------------------- */ mov x0, #DCCISW -- cgit v1.2.3 From 65ec13bce1367795bb0926561caca27de210e534 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Mon, 12 Aug 2019 12:19:21 +0100 Subject: Reduce the number of memory leaks in cert_create The valgrind checks for cert_create have not been run in a long while - as such there are a few memory leaks present. This patch fixes a few of the major ones reported by valgrind. However, a few do remain. Change-Id: Iab002fb2b0090043287d43fb54a4d18928c2ed85 Signed-off-by: Justin Chadwell --- tools/cert_create/src/ext.c | 3 ++- tools/cert_create/src/key.c | 3 ++- tools/cert_create/src/main.c | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/tools/cert_create/src/ext.c b/tools/cert_create/src/ext.c index 055ddbfd0..57fb47d1d 100644 --- a/tools/cert_create/src/ext.c +++ b/tools/cert_create/src/ext.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -284,6 +284,7 @@ X509_EXTENSION *ext_new_key(int nid, int crit, EVP_PKEY *k) ex = ext_new(nid, crit, p, sz); /* Clean up */ + BIO_free(mem); OPENSSL_free(p); return ex; diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c index 871f9ee8b..fece77085 100644 --- a/tools/cert_create/src/key.c +++ b/tools/cert_create/src/key.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -73,6 +73,7 @@ static int key_create_rsa(key_t *key) goto err; } + BN_free(e); return 1; err: RSA_free(rsa); diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c index ed566207c..0f588cc8c 100644 --- a/tools/cert_create/src/main.c +++ b/tools/cert_create/src/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -- cgit v1.2.3 From 7c103d608d12c11a6657ac9558c7367c45429c6c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Aug 2019 18:58:38 +0200 Subject: rcar_gen3: plat: Factor out PRR_ macros into rcar_def.h Pull out the PRR_* macros into rcar_def.h and remove multiple copies of it. Now that there are still RCAR_* macros in rcar_def.h too and they have the exact same meaning as the PRR_* macros, but that's for another patch. Signed-off-by: Marek Vasut Change-Id: Icb7f61b971b1a23102bd1b9f58cda580660a55fc --- drivers/renesas/rcar/pfc/pfc_init.c | 16 +--------------- drivers/renesas/rcar/pfc/pfc_regs.h | 1 - drivers/renesas/rcar/qos/qos_init.c | 17 +---------------- drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c | 1 + .../renesas/rcar/ddr/ddr_b/boot_init_dram_config.c | 1 - .../renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h | 13 ------------- drivers/staging/renesas/rcar/ddr/dram_sub_func.c | 14 ++------------ plat/renesas/rcar/include/rcar_def.h | 17 ++++++++++++++++- 8 files changed, 21 insertions(+), 59 deletions(-) diff --git a/drivers/renesas/rcar/pfc/pfc_init.c b/drivers/renesas/rcar/pfc/pfc_init.c index e9455af51..aedc7d980 100644 --- a/drivers/renesas/rcar/pfc/pfc_init.c +++ b/drivers/renesas/rcar/pfc/pfc_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,20 +37,6 @@ #include "D3/pfc_init_d3.h" #endif - /* Product Register */ -#define PRR (0xFFF00044U) -#define PRR_PRODUCT_MASK (0x00007F00U) -#define PRR_CUT_MASK (0x000000FFU) -#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ -#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ -#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */ -#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ -#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */ -#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */ -#define PRR_PRODUCT_10 (0x00U) -#define PRR_PRODUCT_11 (0x01U) -#define PRR_PRODUCT_20 (0x10U) - #define PRR_PRODUCT_ERR(reg) \ do { \ ERROR("LSI Product ID(PRR=0x%x) PFC initialize not supported.\n", \ diff --git a/drivers/renesas/rcar/pfc/pfc_regs.h b/drivers/renesas/rcar/pfc/pfc_regs.h index e7dd54397..418773366 100644 --- a/drivers/renesas/rcar/pfc/pfc_regs.h +++ b/drivers/renesas/rcar/pfc/pfc_regs.h @@ -115,7 +115,6 @@ #define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U) #define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U) #define GPIO_OUTDT6 (GPIO_BASE + 0x5408U) -#define GPIO_INDT6 (GPIO_BASE + 0x540CU) #define GPIO_INTDT6 (GPIO_BASE + 0x5410U) #define GPIO_INTCLR6 (GPIO_BASE + 0x5414U) #define GPIO_INTMSK6 (GPIO_BASE + 0x5418U) diff --git a/drivers/renesas/rcar/qos/qos_init.c b/drivers/renesas/rcar/qos/qos_init.c index 884e031ca..d0f17309b 100644 --- a/drivers/renesas/rcar/qos/qos_init.c +++ b/drivers/renesas/rcar/qos/qos_init.c @@ -12,6 +12,7 @@ #include "qos_init.h" #include "qos_common.h" #include "qos_reg.h" +#include "rcar_def.h" #if RCAR_LSI == RCAR_AUTO #include "H3/qos_init_h3_v10.h" #include "H3/qos_init_h3_v11.h" @@ -50,22 +51,6 @@ #include "D3/qos_init_d3.h" #endif - /* Product Register */ -#define PRR 0xFFF00044U -#define PRR_PRODUCT_MASK 0x00007F00U -#define PRR_CUT_MASK 0x000000FFU -#define PRR_PRODUCT_H3 0x00004F00U /* R-Car H3 */ -#define PRR_PRODUCT_M3 0x00005200U /* R-Car M3 */ -#define PRR_PRODUCT_V3M 0x00005400U /* R-Car V3M */ -#define PRR_PRODUCT_M3N 0x00005500U /* R-Car M3N */ -#define PRR_PRODUCT_E3 0x00005700U /* R-Car E3 */ -#define PRR_PRODUCT_D3 0x00005800U /* R-Car D3 */ -#define PRR_PRODUCT_10 0x00U -#define PRR_PRODUCT_11 0x01U -#define PRR_PRODUCT_20 0x10U -#define PRR_PRODUCT_21 0x11U -#define PRR_PRODUCT_30 0x20U - #if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M) #define DRAM_CH_CNT 0x04 diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index 89d666ce6..2cce65339 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -20,6 +20,7 @@ #include "boot_init_dram.h" #include "dram_sub_func.h" #include "micro_delay.h" +#include "rcar_def.h" #define DDR_BACKUPMODE #define FATAL_MSG(x) NOTICE(x) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index 5d1b078c9..aaa5f008b 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -1622,7 +1622,6 @@ static const uint32_t TermcodeBySample[20][3] = { #define PFC_PUD5 0xE6060454U #define PFC_PUD6 0xE6060458U #define GPIO_INDT5 0xE605500CU -#define GPIO_INDT6 0xE605540CU #define GPIO_GPSR6 0xE6060118U #if (RCAR_GEN3_ULCB == 0) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h index a1cbfbf9c..abddf0cf2 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h @@ -55,19 +55,6 @@ #define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x)) -/* Product Register */ -#define PRR (0xFFF00044U) -#define PRR_PRODUCT_MASK (0x00007F00U) -#define PRR_CUT_MASK (0x000000FFU) -#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ -#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3-W */ -#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3-N */ -#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */ -#define PRR_PRODUCT_10 (0x00U) /* Ver.1.0 */ -#define PRR_PRODUCT_11 (0x01U) /* Ver.1.1 */ -#define PRR_PRODUCT_20 (0x10U) /* Ver.2.0 */ -#define PRR_PRODUCT_30 (0x20U) /* Ver.3.0 */ - /* DBSC registers */ #define DBSC_DBSYSCONF1 0xE6790004U #define DBSC_DBPHYCONF0 0xE6790010U diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c index 6739b0dd3..c6ab44abc 100644 --- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c +++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,15 +8,7 @@ #include #include "dram_sub_func.h" - -#define PRR (0xFFF00044U) -#define PRR_PRODUCT_MASK (0x00007F00U) -#define PRR_CUT_MASK (0x000000FFU) -#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ -#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ -#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ -#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */ -#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */ +#include "rcar_def.h" #if RCAR_SYSTEM_SUSPEND /* Local defines */ @@ -32,11 +24,9 @@ #endif #define GPIO_OUTDT1 (0xE6051008U) -#define GPIO_INDT1 (0xE605100CU) #define GPIO_OUTDT3 (0xE6053008U) #define GPIO_INDT3 (0xE605300CU) #define GPIO_OUTDT6 (0xE6055408U) -#define GPIO_INDT6 (0xE605540CU) #if DRAM_BACKUP_GPIO_USE == 1 #define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U) /* GP1_9 (BKUP_REQB) */ diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h index ac7dc1767..6d60b5025 100644 --- a/plat/renesas/rcar/include/rcar_def.h +++ b/plat/renesas/rcar/include/rcar_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -172,6 +172,21 @@ #define RCAR_PRODUCT_H3_CUT20 (RCAR_PRODUCT_H3 | U(0x10)) /* 2.0 */ #define RCAR_PRODUCT_M3_CUT10 (RCAR_PRODUCT_M3 | U(0x00)) /* 1.0 */ #define RCAR_PRODUCT_M3_CUT11 (RCAR_PRODUCT_M3 | U(0x10)) +#define PRR 0xFFF00044U +#define PRR_PRODUCT_MASK 0x00007F00U +#define PRR_CUT_MASK 0x000000FFU +#define PRR_PRODUCT_H3 0x00004F00U /* R-Car H3 */ +#define PRR_PRODUCT_M3 0x00005200U /* R-Car M3-W */ +#define PRR_PRODUCT_V3M 0x00005400U /* R-Car V3M */ +#define PRR_PRODUCT_M3N 0x00005500U /* R-Car M3-N */ +#define PRR_PRODUCT_V3H 0x00005600U /* R-Car V3H */ +#define PRR_PRODUCT_E3 0x00005700U /* R-Car E3 */ +#define PRR_PRODUCT_D3 0x00005800U /* R-Car D3 */ +#define PRR_PRODUCT_10 0x00U /* Ver.1.0 */ +#define PRR_PRODUCT_11 0x01U /* Ver.1.1 */ +#define PRR_PRODUCT_20 0x10U /* Ver.2.0 */ +#define PRR_PRODUCT_21 0x11U /* Ver.2.1 */ +#define PRR_PRODUCT_30 0x20U /* Ver.3.0 */ #define RCAR_CPU_MASK_CA57 U(0x80000000) #define RCAR_CPU_MASK_CA53 U(0x04000000) #define RCAR_CPU_HAVE_CA57 U(0x00000000) -- cgit v1.2.3 From df51d8fe7e26405db64be686c58da9292e1d4f4c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Aug 2019 19:13:22 +0200 Subject: rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_* Rename RCAR_PRODUCT_* to PRR_PRODUCT_* and drop the duplicate RCAR_PRODUCT_* macro. Signed-off-by: Marek Vasut Change-Id: I6b2789790b85edb79c026f0860d70f323d113d96 --- drivers/renesas/rcar/emmc/emmc_interrupt.c | 14 ++--- drivers/renesas/rcar/emmc/emmc_mount.c | 14 ++--- drivers/renesas/rcar/iic_dvfs/iic_dvfs.c | 6 +- drivers/renesas/rcar/pfc/M3/pfc_init_m3.c | 10 +-- drivers/renesas/rcar/pfc/pfc_init.c | 10 +-- drivers/renesas/rcar/pwrc/pwrc.c | 32 +++++----- drivers/renesas/rcar/rom/rom_api.c | 22 +++---- drivers/renesas/rcar/rpc/rpc_driver.c | 6 +- drivers/renesas/rcar/watchdog/swdt.c | 6 +- plat/renesas/rcar/bl2_cpg_init.c | 36 +++++------ plat/renesas/rcar/bl2_plat_setup.c | 98 +++++++++++++++--------------- plat/renesas/rcar/bl31_plat_setup.c | 4 +- plat/renesas/rcar/include/rcar_def.h | 24 ++------ 13 files changed, 135 insertions(+), 147 deletions(-) diff --git a/drivers/renesas/rcar/emmc/emmc_interrupt.c b/drivers/renesas/rcar/emmc/emmc_interrupt.c index 37a3cf9d4..2557280cf 100644 --- a/drivers/renesas/rcar/emmc/emmc_interrupt.c +++ b/drivers/renesas/rcar/emmc/emmc_interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights * reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -26,17 +26,17 @@ uint32_t emmc_interrupt(void) uint32_t end_bit; prr_data = mmio_read_32((uintptr_t) RCAR_PRR); - cut_ver = prr_data & RCAR_CUT_MASK; - if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_H3) { - if (cut_ver == RCAR_CUT_VER10) { + cut_ver = prr_data & PRR_CUT_MASK; + if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_H3) { + if (cut_ver == PRR_PRODUCT_10) { end_bit = BIT17; - } else if (cut_ver == RCAR_CUT_VER11) { + } else if (cut_ver == PRR_PRODUCT_11) { end_bit = BIT17; } else { end_bit = BIT20; } - } else if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_M3) { - if (cut_ver == RCAR_CUT_VER10) { + } else if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_M3) { + if (cut_ver == PRR_PRODUCT_10) { end_bit = BIT17; } else { end_bit = BIT20; diff --git a/drivers/renesas/rcar/emmc/emmc_mount.c b/drivers/renesas/rcar/emmc/emmc_mount.c index dd57b0c24..df8203ea8 100644 --- a/drivers/renesas/rcar/emmc/emmc_mount.c +++ b/drivers/renesas/rcar/emmc/emmc_mount.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,14 +29,14 @@ static void emmc_set_bootpartition(void) { uint32_t reg; - reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); - if (reg == RCAR_PRODUCT_M3_CUT10) { + reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); + if (reg == PRR_PRODUCT_M3_CUT10) { mmc_drv_obj.boot_partition_en = (EMMC_PARTITION_ID) ((mmc_drv_obj.ext_csd_data[179] & EMMC_BOOT_PARTITION_EN_MASK) >> EMMC_BOOT_PARTITION_EN_SHIFT); - } else if ((reg == RCAR_PRODUCT_H3_CUT20) - || (reg == RCAR_PRODUCT_M3_CUT11)) { + } else if ((reg == PRR_PRODUCT_H3_CUT20) + || (reg == PRR_PRODUCT_M3_CUT11)) { mmc_drv_obj.boot_partition_en = mmc_drv_obj.partition_access; } else { if ((mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION) != @@ -460,8 +460,8 @@ static void emmc_get_partition_access(void) uint32_t reg; EMMC_ERROR_CODE result; - reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); - if ((reg == RCAR_PRODUCT_H3_CUT20) || (reg == RCAR_PRODUCT_M3_CUT11)) { + reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); + if ((reg == PRR_PRODUCT_H3_CUT20) || (reg == PRR_PRODUCT_M3_CUT11)) { SETR_32(SD_OPTION, 0x000060EEU); /* 8 bits width */ /* CMD8 (EXT_CSD) */ emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c index 39b9bb4e3..28b56c10e 100644 --- a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c +++ b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -189,8 +189,8 @@ IIC_DVFS_FUNC(start, DVFS_STATE_T * state) mode = mmio_read_8(IIC_DVFS_REG_ICCR) | IIC_DVFS_BIT_ICCR_ENABLE; mmio_write_8(IIC_DVFS_REG_ICCR, mode); - lsi_product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; - if (lsi_product == RCAR_PRODUCT_E3) + lsi_product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK; + if (lsi_product == PRR_PRODUCT_E3) goto start; reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14; diff --git a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c index 0aa3bffce..7684c624a 100644 --- a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c +++ b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c @@ -615,8 +615,8 @@ static void start_rtdma0_descriptor(void) uint32_t reg; reg = mmio_read_32(RCAR_PRR); - reg &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); - if (reg == (RCAR_PRODUCT_M3_CUT10)) { + reg &= (PRR_PRODUCT_MASK | PRR_CUT_MASK); + if (reg == (PRR_PRODUCT_M3_CUT10)) { /* Enable clock supply to RTDMAC. */ mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC); @@ -654,14 +654,14 @@ static void pfc_reg_write(uint32_t addr, uint32_t data) uint32_t prr; prr = mmio_read_32(RCAR_PRR); - prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK); mmio_write_32(PFC_PMMR, ~data); - if (prr == (RCAR_PRODUCT_M3_CUT10)) { + if (prr == (PRR_PRODUCT_M3_CUT10)) { mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ } mmio_write_32((uintptr_t)addr, data); - if (prr == (RCAR_PRODUCT_M3_CUT10)) { + if (prr == (PRR_PRODUCT_M3_CUT10)) { mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ } } diff --git a/drivers/renesas/rcar/pfc/pfc_init.c b/drivers/renesas/rcar/pfc/pfc_init.c index aedc7d980..88106676a 100644 --- a/drivers/renesas/rcar/pfc/pfc_init.c +++ b/drivers/renesas/rcar/pfc/pfc_init.c @@ -57,8 +57,8 @@ void rcar_pfc_init(void) reg = mmio_read_32(RCAR_PRR); #if RCAR_LSI == RCAR_AUTO - switch (reg & RCAR_PRODUCT_MASK) { - case RCAR_PRODUCT_H3: + switch (reg & PRR_PRODUCT_MASK) { + case PRR_PRODUCT_H3: switch (reg & PRR_CUT_MASK) { case PRR_PRODUCT_10: /* H3 Ver.1.0 */ pfc_init_h3_v1(); @@ -71,13 +71,13 @@ void rcar_pfc_init(void) break; } break; - case RCAR_PRODUCT_M3: + case PRR_PRODUCT_M3: pfc_init_m3(); break; - case RCAR_PRODUCT_M3N: + case PRR_PRODUCT_M3N: pfc_init_m3n(); break; - case RCAR_PRODUCT_V3M: + case PRR_PRODUCT_V3M: pfc_init_v3m(); break; default: diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c index 32e04a73a..2ce6b6139 100644 --- a/drivers/renesas/rcar/pwrc/pwrc.c +++ b/drivers/renesas/rcar/pwrc/pwrc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -314,16 +314,16 @@ void rcar_pwrc_clusteroff(uint64_t mpidr) rcar_lock_get(); reg = mmio_read_32(RCAR_PRR); - product = reg & RCAR_PRODUCT_MASK; - cut = reg & RCAR_CUT_MASK; + product = reg & PRR_PRODUCT_MASK; + cut = reg & PRR_CUT_MASK; c = rcar_pwrc_get_mpidr_cluster(mpidr); dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR; - if (RCAR_PRODUCT_M3 == product && cut < RCAR_CUT_VER30) + if (PRR_PRODUCT_M3 == product && cut < PRR_PRODUCT_30) goto done; - if (RCAR_PRODUCT_H3 == product && cut <= RCAR_CUT_VER20) + if (PRR_PRODUCT_H3 == product && cut <= PRR_PRODUCT_20) goto done; /* all of the CPUs in the cluster is in the CoreStandby mode */ @@ -424,13 +424,13 @@ static void __attribute__ ((section(".system_ram"))) uint32_t reg = mmio_read_32(RCAR_PRR); uint32_t cut, product; - product = reg & RCAR_PRODUCT_MASK; - cut = reg & RCAR_CUT_MASK; + product = reg & PRR_PRODUCT_MASK; + cut = reg & PRR_CUT_MASK; - if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30) + if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) goto self_refresh; - if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20) + if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) goto self_refresh; mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE); @@ -445,16 +445,16 @@ self_refresh: /* Set the Self-Refresh mode */ mmio_write_32(DBSC4_REG_DBACEN, 0); - if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20) + if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) rcar_micro_delay(100); - else if (product == RCAR_PRODUCT_H3) { + else if (product == PRR_PRODUCT_H3) { mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); DBCAM_FLUSH(0); DBCAM_FLUSH(1); DBCAM_FLUSH(2); DBCAM_FLUSH(3); mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0); - } else if (product == RCAR_PRODUCT_M3) { + } else if (product == PRR_PRODUCT_M3) { mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); DBCAM_FLUSH(0); DBCAM_FLUSH(1); @@ -499,10 +499,10 @@ self_refresh: mmio_write_32(DBSC4_REG_DBRFEN, 0U); rcar_micro_delay(1U); - if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30) + if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) return; - if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20) + if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) return; mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE); @@ -648,9 +648,9 @@ void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline)) uint32_t reg, product; reg = mmio_read_32(RCAR_PRR); - product = reg & RCAR_PRODUCT_MASK; + product = reg & PRR_PRODUCT_MASK; - if (product != RCAR_PRODUCT_E3) + if (product != PRR_PRODUCT_E3) rcar_pwrc_set_self_refresh(); else rcar_pwrc_set_self_refresh_e3(); diff --git a/drivers/renesas/rcar/rom/rom_api.c b/drivers/renesas/rcar/rom/rom_api.c index c9f8f5fe8..fda28150e 100644 --- a/drivers/renesas/rcar/rom/rom_api.c +++ b/drivers/renesas/rcar/rom/rom_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,30 +30,30 @@ static uint32_t get_table_index(void) uint32_t cut_ver; uint32_t index; - product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; - cut_ver = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK; + product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK; + cut_ver = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK; switch (product) { - case RCAR_PRODUCT_H3: - if (cut_ver == RCAR_CUT_VER10) + case PRR_PRODUCT_H3: + if (cut_ver == PRR_PRODUCT_10) index = OLD_API_TABLE1; - else if (cut_ver == RCAR_CUT_VER11) + else if (cut_ver == PRR_PRODUCT_11) index = OLD_API_TABLE1; - else if (cut_ver == RCAR_CUT_VER20) + else if (cut_ver == PRR_PRODUCT_20) index = OLD_API_TABLE2; else /* Later than H3 Ver.2.0 */ index = NEW_API_TABLE; break; - case RCAR_PRODUCT_M3: - if (cut_ver == RCAR_CUT_VER10) + case PRR_PRODUCT_M3: + if (cut_ver == PRR_PRODUCT_10) index = OLD_API_TABLE3; else /* M3 Ver.1.1 or later */ index = NEW_API_TABLE; break; - case RCAR_PRODUCT_V3M: - if (cut_ver == RCAR_CUT_VER10) + case PRR_PRODUCT_V3M: + if (cut_ver == PRR_PRODUCT_10) /* V3M WS1.0 */ index = NEW_API_TABLE2; else diff --git a/drivers/renesas/rcar/rpc/rpc_driver.c b/drivers/renesas/rcar/rpc/rpc_driver.c index 5c11b62de..63de5b851 100644 --- a/drivers/renesas/rcar/rpc/rpc_driver.c +++ b/drivers/renesas/rcar/rpc/rpc_driver.c @@ -34,10 +34,10 @@ static void rpc_setup(void) if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT) mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT); - product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; - cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK; + product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK; + cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK; - if ((product == RCAR_PRODUCT_M3) && (cut < RCAR_CUT_VER30)) + if ((product == PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30)) phy_strtim = RPC_PHYCNT_STRTIM_M3V1; else phy_strtim = RPC_PHYCNT_STRTIM; diff --git a/drivers/renesas/rcar/watchdog/swdt.c b/drivers/renesas/rcar/watchdog/swdt.c index 8b2943cc6..111e65174 100644 --- a/drivers/renesas/rcar/watchdog/swdt.c +++ b/drivers/renesas/rcar/watchdog/swdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -82,7 +82,7 @@ void rcar_swdt_init(void) uint32_t reg, val, product_cut, chk_data; reg = mmio_read_32(RCAR_PRR); - product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); reg = mmio_read_32(RCAR_MODEMR); chk_data = reg & CHECK_MD13_MD14; @@ -108,7 +108,7 @@ void rcar_swdt_init(void) val |= WTCNT_COUNT_8p22k; break; case MD14_MD13_TYPE_3: - val |= product_cut == (RCAR_PRODUCT_H3 | RCAR_CUT_VER10) ? + val |= product_cut == (PRR_PRODUCT_H3 | PRR_PRODUCT_10) ? WTCNT_COUNT_8p13k_H3VER10 : WTCNT_COUNT_8p13k; break; default: diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c index ed9b7724d..c3ca9ea16 100644 --- a/plat/renesas/rcar/bl2_cpg_init.c +++ b/plat/renesas/rcar/bl2_cpg_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -109,12 +109,12 @@ static void bl2_secure_cpg_init(void) #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) static void bl2_realtime_cpg_init_h3(void) { - uint32_t cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK; + uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK; uint32_t cr0, cr8; - cr0 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ? + cr0 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ? 0x00200000U : 0x00210000U; - cr8 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ? + cr8 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ? 0x01F1FFF4U : 0x01F1FFF7U; cpg_write(RMSTPCR0, cr0); @@ -329,7 +329,7 @@ void bl2_cpg_init(void) { uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK; #if RCAR_LSI == RCAR_AUTO - uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; + uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK; #endif bl2_secure_cpg_init(); @@ -338,22 +338,22 @@ void bl2_cpg_init(void) #if RCAR_LSI == RCAR_AUTO switch (product) { - case RCAR_PRODUCT_H3: + case PRR_PRODUCT_H3: bl2_realtime_cpg_init_h3(); break; - case RCAR_PRODUCT_M3: + case PRR_PRODUCT_M3: bl2_realtime_cpg_init_m3(); break; - case RCAR_PRODUCT_M3N: + case PRR_PRODUCT_M3N: bl2_realtime_cpg_init_m3n(); break; - case RCAR_PRODUCT_V3M: + case PRR_PRODUCT_V3M: bl2_realtime_cpg_init_v3m(); break; - case RCAR_PRODUCT_E3: + case PRR_PRODUCT_E3: bl2_realtime_cpg_init_e3(); break; - case RCAR_PRODUCT_D3: + case PRR_PRODUCT_D3: bl2_realtime_cpg_init_d3(); break; default: @@ -381,25 +381,25 @@ void bl2_cpg_init(void) void bl2_system_cpg_init(void) { #if RCAR_LSI == RCAR_AUTO - uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; + uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK; switch (product) { - case RCAR_PRODUCT_H3: + case PRR_PRODUCT_H3: bl2_system_cpg_init_h3(); break; - case RCAR_PRODUCT_M3: + case PRR_PRODUCT_M3: bl2_system_cpg_init_m3(); break; - case RCAR_PRODUCT_M3N: + case PRR_PRODUCT_M3N: bl2_system_cpg_init_m3n(); break; - case RCAR_PRODUCT_V3M: + case PRR_PRODUCT_V3M: bl2_system_cpg_init_v3m(); break; - case RCAR_PRODUCT_E3: + case PRR_PRODUCT_E3: bl2_system_cpg_init_e3(); break; - case RCAR_PRODUCT_D3: + case PRR_PRODUCT_D3: bl2_system_cpg_init_d3(); break; default: diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 3c9b56f4e..ebe6dddc9 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -65,22 +65,22 @@ static void bl2_init_generic_timer(void); /* R-Car Gen3 product check */ #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) -#define TARGET_PRODUCT RCAR_PRODUCT_H3 +#define TARGET_PRODUCT PRR_PRODUCT_H3 #define TARGET_NAME "R-Car H3" #elif RCAR_LSI == RCAR_M3 -#define TARGET_PRODUCT RCAR_PRODUCT_M3 +#define TARGET_PRODUCT PRR_PRODUCT_M3 #define TARGET_NAME "R-Car M3" #elif RCAR_LSI == RCAR_M3N -#define TARGET_PRODUCT RCAR_PRODUCT_M3N +#define TARGET_PRODUCT PRR_PRODUCT_M3N #define TARGET_NAME "R-Car M3N" #elif RCAR_LSI == RCAR_V3M -#define TARGET_PRODUCT RCAR_PRODUCT_V3M +#define TARGET_PRODUCT PRR_PRODUCT_V3M #define TARGET_NAME "R-Car V3M" #elif RCAR_LSI == RCAR_E3 -#define TARGET_PRODUCT RCAR_PRODUCT_E3 +#define TARGET_PRODUCT PRR_PRODUCT_E3 #define TARGET_NAME "R-Car E3" #elif RCAR_LSI == RCAR_D3 -#define TARGET_PRODUCT RCAR_PRODUCT_D3 +#define TARGET_PRODUCT PRR_PRODUCT_D3 #define TARGET_NAME "R-Car D3" #elif RCAR_LSI == RCAR_AUTO #define TARGET_NAME "R-Car H3/M3/M3N/V3M" @@ -238,17 +238,17 @@ void bl2_plat_flush_bl31_params(void) bl2_secure_setting(); reg = mmio_read_32(RCAR_PRR); - product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); - product = reg & RCAR_PRODUCT_MASK; - cut = reg & RCAR_CUT_MASK; + product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); + product = reg & PRR_PRODUCT_MASK; + cut = reg & PRR_CUT_MASK; - if (product == RCAR_PRODUCT_M3 && RCAR_CUT_VER30 > cut) + if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut) goto tlb; - if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) + if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut) goto tlb; - if (product == RCAR_PRODUCT_D3) + if (product == PRR_PRODUCT_D3) goto tlb; /* Disable MFIS write protection */ @@ -261,28 +261,28 @@ tlb: boot_cpu != MODEMR_BOOT_CPU_CA53) goto mmu; - if (product_cut == RCAR_PRODUCT_H3_CUT20) { + if (product_cut == PRR_PRODUCT_H3_CUT20) { mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); - } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || - product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) { + } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || + product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); - } else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) || - (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) { + } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || + (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); } - if (product_cut == (RCAR_PRODUCT_H3_CUT20) || - product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || - product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) || - product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { + if (product_cut == (PRR_PRODUCT_H3_CUT20) || + product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || + product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || + product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); @@ -458,28 +458,28 @@ static void bl2_populate_compatible_string(void *fdt) } reg = mmio_read_32(RCAR_PRR); - switch (reg & RCAR_PRODUCT_MASK) { - case RCAR_PRODUCT_H3: + switch (reg & PRR_PRODUCT_MASK) { + case PRR_PRODUCT_H3: ret = fdt_appendprop_string(fdt, 0, "compatible", "renesas,r8a7795"); break; - case RCAR_PRODUCT_M3: + case PRR_PRODUCT_M3: ret = fdt_appendprop_string(fdt, 0, "compatible", "renesas,r8a7796"); break; - case RCAR_PRODUCT_M3N: + case PRR_PRODUCT_M3N: ret = fdt_appendprop_string(fdt, 0, "compatible", "renesas,r8a77965"); break; - case RCAR_PRODUCT_V3M: + case PRR_PRODUCT_V3M: ret = fdt_appendprop_string(fdt, 0, "compatible", "renesas,r8a77970"); break; - case RCAR_PRODUCT_E3: + case PRR_PRODUCT_E3: ret = fdt_appendprop_string(fdt, 0, "compatible", "renesas,r8a77990"); break; - case RCAR_PRODUCT_D3: + case PRR_PRODUCT_D3: ret = fdt_appendprop_string(fdt, 0, "compatible", "renesas,r8a77995"); break; @@ -572,7 +572,7 @@ static void bl2_advertise_dram_size(uint32_t product) }; switch (product) { - case RCAR_PRODUCT_H3: + case PRR_PRODUCT_H3: #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) /* 4GB(1GBx4) */ dram_config[1] = 0x40000000ULL; @@ -594,7 +594,7 @@ static void bl2_advertise_dram_size(uint32_t product) #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ break; - case RCAR_PRODUCT_M3: + case PRR_PRODUCT_M3: #if (RCAR_GEN3_ULCB == 1) /* 2GB(1GBx2 2ch split) */ dram_config[1] = 0x40000000ULL; @@ -606,17 +606,17 @@ static void bl2_advertise_dram_size(uint32_t product) #endif break; - case RCAR_PRODUCT_M3N: + case PRR_PRODUCT_M3N: /* 2GB(1GBx2) */ dram_config[1] = 0x80000000ULL; break; - case RCAR_PRODUCT_V3M: + case PRR_PRODUCT_V3M: /* 1GB(512MBx2) */ dram_config[1] = 0x40000000ULL; break; - case RCAR_PRODUCT_E3: + case PRR_PRODUCT_E3: #if (RCAR_DRAM_DDR3L_MEMCONF == 0) /* 1GB(512MBx2) */ dram_config[1] = 0x40000000ULL; @@ -629,7 +629,7 @@ static void bl2_advertise_dram_size(uint32_t product) #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ break; - case RCAR_PRODUCT_D3: + case PRR_PRODUCT_D3: /* 512MB */ dram_config[1] = 0x20000000ULL; break; @@ -716,26 +716,26 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, version_of_renesas); reg = mmio_read_32(RCAR_PRR); - product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); - product = reg & RCAR_PRODUCT_MASK; + product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); + product = reg & PRR_PRODUCT_MASK; switch (product) { - case RCAR_PRODUCT_H3: + case PRR_PRODUCT_H3: str = product_h3; break; - case RCAR_PRODUCT_M3: + case PRR_PRODUCT_M3: str = product_m3; break; - case RCAR_PRODUCT_M3N: + case PRR_PRODUCT_M3N: str = product_m3n; break; - case RCAR_PRODUCT_V3M: + case PRR_PRODUCT_V3M: str = product_v3m; break; - case RCAR_PRODUCT_E3: + case PRR_PRODUCT_E3: str = product_e3; break; - case RCAR_PRODUCT_D3: + case PRR_PRODUCT_D3: str = product_d3; break; default: @@ -743,9 +743,9 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, break; } - if ((RCAR_PRODUCT_M3 == product) && - (RCAR_CUT_VER20 == (reg & RCAR_MAJOR_MASK))) { - if (RCAR_M3_CUT_VER11 == (reg & RCAR_CUT_MASK)) { + if ((PRR_PRODUCT_M3 == product) && + (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) { + if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) { /* M3 Ver.1.1 or Ver.1.2 */ NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str); @@ -761,7 +761,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); } - if (product == RCAR_PRODUCT_E3) { + if (product == PRR_PRODUCT_E3) { reg = mmio_read_32(RCAR_MODEMR); sscg = reg & RCAR_SSCG_MASK; str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; @@ -930,7 +930,7 @@ lcm_state: mmio_write_32(CPG_CA53DBGRCR, DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); - if (product_cut == RCAR_PRODUCT_H3_CUT10) { + if (product_cut == PRR_PRODUCT_H3_CUT10) { reg = mmio_read_32(CPG_PLL2CR); reg &= ~((uint32_t) 1 << 5); mmio_write_32(CPG_PLL2CR, reg); @@ -1016,7 +1016,7 @@ static void bl2_init_generic_timer(void) /* Set frequency data in CNTFID0 */ reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; - reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); switch (modemr_pll) { case MD14_MD13_TYPE_0: rcar_get_board_type(&board_type, &board_rev); @@ -1025,7 +1025,7 @@ static void bl2_init_generic_timer(void) } break; case MD14_MD13_TYPE_3: - if (RCAR_PRODUCT_H3_CUT10 == reg) { + if (PRR_PRODUCT_H3_CUT10 == reg) { reg_cntfid = reg_cntfid >> 1U; } break; diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c index 4fff233e7..bd83c415e 100644 --- a/plat/renesas/rcar/bl31_plat_setup.c +++ b/plat/renesas/rcar/bl31_plat_setup.c @@ -44,9 +44,9 @@ void plat_cci_init(void) { uint32_t prd; - prd = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + prd = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); - if (RCAR_PRODUCT_H3_CUT10 == prd || RCAR_PRODUCT_H3_CUT11 == prd) { + if (PRR_PRODUCT_H3_CUT10 == prd || PRR_PRODUCT_H3_CUT11 == prd) { cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX; cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX; } diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h index 6d60b5025..a60f9b68e 100644 --- a/plat/renesas/rcar/include/rcar_def.h +++ b/plat/renesas/rcar/include/rcar_def.h @@ -147,31 +147,19 @@ #define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */ /* Product register */ #define RCAR_PRR U(0xFFF00044) -#define RCAR_PRODUCT_MASK U(0x00007F00) -#define RCAR_CUT_MASK U(0x000000FF) -#define RCAR_PRODUCT_H3 U(0x00004F00) -#define RCAR_PRODUCT_M3 U(0x00005200) -#define RCAR_PRODUCT_V3M U(0x00005400) -#define RCAR_PRODUCT_M3N U(0x00005500) -#define RCAR_PRODUCT_E3 U(0x00005700) -#define RCAR_PRODUCT_D3 U(0x00005800) -#define RCAR_CUT_VER10 U(0x00000000) -#define RCAR_CUT_VER11 U(0x00000001) /* H3/M3N/E3 Ver.1.1 */ #define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */ -#define RCAR_CUT_VER20 U(0x00000010) -#define RCAR_CUT_VER30 U(0x00000020) #define RCAR_MAJOR_MASK U(0x000000F0) #define RCAR_MINOR_MASK U(0x0000000F) -#define RCAR_PRODUCT_SHIFT U(8) +#define PRR_PRODUCT_SHIFT U(8) #define RCAR_MAJOR_SHIFT U(4) #define RCAR_MINOR_SHIFT U(0) #define RCAR_MAJOR_OFFSET U(1) #define RCAR_M3_MINOR_OFFSET U(2) -#define RCAR_PRODUCT_H3_CUT10 (RCAR_PRODUCT_H3 | U(0x00)) /* 1.0 */ -#define RCAR_PRODUCT_H3_CUT11 (RCAR_PRODUCT_H3 | U(0x01)) /* 1.1 */ -#define RCAR_PRODUCT_H3_CUT20 (RCAR_PRODUCT_H3 | U(0x10)) /* 2.0 */ -#define RCAR_PRODUCT_M3_CUT10 (RCAR_PRODUCT_M3 | U(0x00)) /* 1.0 */ -#define RCAR_PRODUCT_M3_CUT11 (RCAR_PRODUCT_M3 | U(0x10)) +#define PRR_PRODUCT_H3_CUT10 (PRR_PRODUCT_H3 | U(0x00)) /* 1.0 */ +#define PRR_PRODUCT_H3_CUT11 (PRR_PRODUCT_H3 | U(0x01)) /* 1.1 */ +#define PRR_PRODUCT_H3_CUT20 (PRR_PRODUCT_H3 | U(0x10)) /* 2.0 */ +#define PRR_PRODUCT_M3_CUT10 (PRR_PRODUCT_M3 | U(0x00)) /* 1.0 */ +#define PRR_PRODUCT_M3_CUT11 (PRR_PRODUCT_M3 | U(0x10)) #define PRR 0xFFF00044U #define PRR_PRODUCT_MASK 0x00007F00U #define PRR_CUT_MASK 0x000000FFU -- cgit v1.2.3 From 1b597c227e5f4d05fa514235280c5a631de97bcb Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Fri, 16 Aug 2019 14:15:59 +0100 Subject: FVP: Add Delay Timer driver to BL1 and BL31 SMMUv3 driver functions which are called from BL1 and BL31 currently use counter-based poll method for testing status bits. Adding Delay Timer driver to BL1 and BL31 is required for timeout-based implementation using timer delay functions for SMMU and other drivers. This patch adds new function `fvp_timer_init()` which initialises either System level generic or SP804 timer based on FVP_USE_SP804_TIMER build flag. In BL2U `bl2u_early_platform_setup()` function the call to `arm_bl2u_early_platform_setup()` (which calls `generic_delay_timer_init()` ignoring FVP_USE_SP804_TIMER flag), is replaced with `arm_console_boot_init()` and `fvp_timer_init()`. Change-Id: Ifd8dcebf4019e877b9bc5641551deef77a44c0d1 Signed-off-by: Alexei Fedorov --- plat/arm/board/fvp/fvp_bl1_setup.c | 3 +++ plat/arm/board/fvp/fvp_bl2_setup.c | 15 +++------------ plat/arm/board/fvp/fvp_bl2u_setup.c | 5 ++++- plat/arm/board/fvp/fvp_bl31_setup.c | 5 ++++- plat/arm/board/fvp/fvp_common.c | 22 ++++++++++++++++++++++ plat/arm/board/fvp/fvp_private.h | 1 + plat/arm/board/fvp/platform.mk | 18 ++++++++++++++++++ 7 files changed, 55 insertions(+), 14 deletions(-) diff --git a/plat/arm/board/fvp/fvp_bl1_setup.c b/plat/arm/board/fvp/fvp_bl1_setup.c index b90ddcd33..8f6170daa 100644 --- a/plat/arm/board/fvp/fvp_bl1_setup.c +++ b/plat/arm/board/fvp/fvp_bl1_setup.c @@ -48,6 +48,9 @@ void bl1_platform_setup(void) { arm_bl1_platform_setup(); + /* Initialize System level generic or SP804 timer */ + fvp_timer_init(); + /* On FVP RevC, initialize SMMUv3 */ if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) smmuv3_security_init(PLAT_FVP_SMMUV3_BASE); diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c index d28094993..89636d18a 100644 --- a/plat/arm/board/fvp/fvp_bl2_setup.c +++ b/plat/arm/board/fvp/fvp_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,15 +25,6 @@ void bl2_platform_setup(void) { arm_bl2_platform_setup(); -#if FVP_USE_SP804_TIMER - /* Enable the clock override for SP804 timer 0, which means that no - * clock dividers are applied and the raw (35 MHz) clock will be used */ - mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); - - /* Initialize delay timer driver using SP804 dual timer 0 */ - sp804_timer_init(V2M_SP804_TIMER0_BASE, - SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); -#else - generic_delay_timer_init(); -#endif /* FVP_USE_SP804_TIMER */ + /* Initialize System level generic or SP804 timer */ + fvp_timer_init(); } diff --git a/plat/arm/board/fvp/fvp_bl2u_setup.c b/plat/arm/board/fvp/fvp_bl2u_setup.c index a8db05567..fd73767c6 100644 --- a/plat/arm/board/fvp/fvp_bl2u_setup.c +++ b/plat/arm/board/fvp/fvp_bl2u_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,9 @@ void bl2u_early_platform_setup(struct meminfo *mem_layout, void *plat_info) { arm_bl2u_early_platform_setup(mem_layout, plat_info); + /* Initialize System level generic or SP804 timer */ + fvp_timer_init(); + /* Initialize the platform config for future decision making */ fvp_config_setup(); } diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c index 3f92d3772..8627c5ef0 100644 --- a/plat/arm/board/fvp/fvp_bl31_setup.c +++ b/plat/arm/board/fvp/fvp_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -34,6 +34,9 @@ void __init bl31_early_platform_setup2(u_register_t arg0, */ fvp_interconnect_enable(); + /* Initialize System level generic or SP804 timer */ + fvp_timer_init(); + /* On FVP RevC, initialize SMMUv3 */ if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) smmuv3_init(PLAT_FVP_SMMUV3_BASE); diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index 36cd5009a..a94879624 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include #include #include @@ -407,3 +409,23 @@ int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) return arm_get_mbedtls_heap(heap_addr, heap_size); } #endif + +void fvp_timer_init(void) +{ +#if FVP_USE_SP804_TIMER + /* Enable the clock override for SP804 timer 0, which means that no + * clock dividers are applied and the raw (35MHz) clock will be used. + */ + mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); + + /* Initialize delay timer driver using SP804 dual timer 0 */ + sp804_timer_init(V2M_SP804_TIMER0_BASE, + SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); +#else + generic_delay_timer_init(); + + /* Enable System level generic timer */ + mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, + CNTCR_FCREQ(0U) | CNTCR_EN); +#endif /* FVP_USE_SP804_TIMER */ +} diff --git a/plat/arm/board/fvp/fvp_private.h b/plat/arm/board/fvp/fvp_private.h index 5067d3a2f..3590370df 100644 --- a/plat/arm/board/fvp/fvp_private.h +++ b/plat/arm/board/fvp/fvp_private.h @@ -18,6 +18,7 @@ void fvp_config_setup(void); void fvp_interconnect_init(void); void fvp_interconnect_enable(void); void fvp_interconnect_disable(void); +void fvp_timer_init(void); void tsp_early_platform_setup(void); #endif /* FVP_PRIVATE_H */ diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 0eb62c44a..617da2d69 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -127,6 +127,7 @@ endif BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ drivers/arm/sp805/sp805.c \ + drivers/delay_timer/delay_timer.c \ drivers/io/io_semihosting.c \ lib/semihosting/semihosting.c \ lib/semihosting/${ARCH}/semihosting_call.S \ @@ -138,6 +139,12 @@ BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ ${FVP_CPU_LIBS} \ ${FVP_INTERCONNECT_SOURCES} +ifeq (${FVP_USE_SP804_TIMER},1) +BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c +else +BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c +endif + BL2_SOURCES += drivers/arm/sp805/sp805.c \ drivers/io/io_semihosting.c \ @@ -167,8 +174,13 @@ endif BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ ${FVP_SECURITY_SOURCES} +ifeq (${FVP_USE_SP804_TIMER},1) +BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c +endif + BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ drivers/arm/smmu/smmu_v3.c \ + drivers/delay_timer/delay_timer.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/board/fvp/fvp_bl31_setup.c \ @@ -181,6 +193,12 @@ BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ ${FVP_INTERCONNECT_SOURCES} \ ${FVP_SECURITY_SOURCES} +ifeq (${FVP_USE_SP804_TIMER},1) +BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c +else +BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c +endif + # Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) ifdef UNIX_MK FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts -- cgit v1.2.3 From 41af05154abe136938bcfb5f26c969933784bbef Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Thu, 15 Aug 2019 00:56:46 +0300 Subject: Coverity fix: Remove GGC ignore -Warray-bounds GCC diagnostics were added to ignore array boundaries, instead of ignoring GCC warning current code will check for array boundaries and perform and array update only for valid elements. Resolves: `CID 246574` `CID 246710` `CID 246651` Signed-off-by: Deepika Bhavnani Change-Id: I7530ecf7a1707351c6ee87e90cc3d33574088f57 --- lib/psci/psci_common.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 5d24356c9..022c87751 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -198,21 +198,17 @@ static unsigned int get_power_on_target_pwrlvl(void) /****************************************************************************** * Helper function to update the requested local power state array. This array * does not store the requested state for the CPU power level. Hence an - * assertion is added to prevent us from accessing the wrong index. + * assertion is added to prevent us from accessing the CPU power level. *****************************************************************************/ static void psci_set_req_local_pwr_state(unsigned int pwrlvl, unsigned int cpu_idx, plat_local_state_t req_pwr_state) { - /* - * This should never happen, we have this here to avoid - * "array subscript is above array bounds" errors in GCC. - */ assert(pwrlvl > PSCI_CPU_PWR_LVL); -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Warray-bounds" - psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state; -#pragma GCC diagnostic pop + if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && + (cpu_idx < PLATFORM_CORE_COUNT)) { + psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state; + } } /****************************************************************************** @@ -245,7 +241,11 @@ static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, { assert(pwrlvl > PSCI_CPU_PWR_LVL); - return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx]; + if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && + (cpu_idx < PLATFORM_CORE_COUNT)) { + return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx]; + } else + return NULL; } /* -- cgit v1.2.3 From 960a12b3fb4699cad83973c853fb5064ed6a75d0 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Fri, 16 Aug 2019 11:08:14 +0800 Subject: intel: agilex: Clear PLL lostlock bypass mode To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1 --- plat/intel/soc/agilex/include/agilex_clock_manager.h | 3 +++ plat/intel/soc/agilex/soc/agilex_clock_manager.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h index 73e6c4e19..0822290aa 100644 --- a/plat/intel/soc/agilex/include/agilex_clock_manager.h +++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h @@ -33,6 +33,7 @@ #define CLKMGR_MAINPLL_PLLC2 0x40 #define CLKMGR_MAINPLL_PLLC3 0x44 #define CLKMGR_MAINPLL_PLLM 0x48 +#define CLKMGR_MAINPLL_LOSTLOCK 0x54 /* Peripheral PLL Group */ #define CLKMGR_PERPLL 0xffd1007c @@ -50,6 +51,7 @@ #define CLKMGR_PERPLL_PLLC2 0x3c #define CLKMGR_PERPLL_PLLC3 0x40 #define CLKMGR_PERPLL_PLLM 0x44 +#define CLKMGR_PERPLL_LOSTLOCK 0x50 /* Altera Group */ #define CLKMGR_ALTERA 0xffd100d0 @@ -112,6 +114,7 @@ #define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) #define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000) +#define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000 typedef struct { uint32_t clk_freq_of_eosc1; diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c index 218676a98..06891ff93 100644 --- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c +++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c @@ -222,6 +222,16 @@ void config_clkmgr_handoff(handoff *hoff_ptr) mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_PSIREFCTR, hoff_ptr->alt_psirefctr); + /* Clear lost lock bypass mode */ + mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_LOSTLOCK, 0x1); + mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_LOSTLOCK, 0x1); + + mmio_setbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_CLR_LOSTLOCK_BYPASS); + + mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB, + CLKMGR_CLR_LOSTLOCK_BYPASS); + /* Take all PLLs out of bypass */ mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_BYPASS, 0); wait_fsm(); -- cgit v1.2.3 From f51df47572fb9d5e6808a07ccf5a7e6a5170554d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 23 Jul 2019 12:32:58 +0900 Subject: console: add a flag to prepend '\r' in the multi-console framework Currently, console drivers prepend '\r' to '\n' by themselves. This is common enough to be supported in the framework. Add a new flag, CONSOLE_FLAG_TRANSLATE_CRLF. A driver can set this flag to ask the framework to transform LF into CRLF instead of doing it by itself. Change-Id: I4f5c5887591bc0a8749a105abe62b6562eaf503b Signed-off-by: Masahiro Yamada --- drivers/console/multi_console.c | 16 +++++++++++++++- include/drivers/console.h | 5 +++-- plat/common/aarch64/crash_console_helpers.S | 11 ++++++++++- 3 files changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c index d9eba7f02..215f49517 100644 --- a/drivers/console/multi_console.c +++ b/drivers/console/multi_console.c @@ -70,6 +70,20 @@ void console_set_scope(console_t *console, unsigned int scope) console->flags = (console->flags & ~CONSOLE_FLAG_SCOPE_MASK) | scope; } +static int do_putc(int c, console_t *console) +{ + int ret; + + if ((c == '\n') && + ((console->flags & CONSOLE_FLAG_TRANSLATE_CRLF) != 0)) { + ret = console->putc('\r', console); + if (ret < 0) + return ret; + } + + return console->putc(c, console); +} + int console_putc(int c) { int err = ERROR_NO_VALID_CONSOLE; @@ -77,7 +91,7 @@ int console_putc(int c) for (console = console_list; console != NULL; console = console->next) if ((console->flags & console_state) && console->putc) { - int ret = console->putc(c, console); + int ret = do_putc(c, console); if ((err == ERROR_NO_VALID_CONSOLE) || (ret < err)) err = ret; } diff --git a/include/drivers/console.h b/include/drivers/console.h index cada771b4..a4859d80f 100644 --- a/include/drivers/console.h +++ b/include/drivers/console.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,7 +21,8 @@ #define CONSOLE_FLAG_CRASH (U(1) << 2) /* Bits 3 to 7 reserved for additional scopes in future expansion. */ #define CONSOLE_FLAG_SCOPE_MASK ((U(1) << 8) - 1) -/* Bits 8 to 31 reserved for non-scope use in future expansion. */ +/* Bits 8 to 31 for non-scope use. */ +#define CONSOLE_FLAG_TRANSLATE_CRLF (U(1) << 8) /* Returned by getc callbacks when receive FIFO is empty. */ #define ERROR_NO_PENDING_CHAR (-1) diff --git a/plat/common/aarch64/crash_console_helpers.S b/plat/common/aarch64/crash_console_helpers.S index 2a48baf0a..e2950f5f7 100644 --- a/plat/common/aarch64/crash_console_helpers.S +++ b/plat/common/aarch64/crash_console_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -125,9 +125,18 @@ putc_loop: b.eq putc_continue ldr x2, [x15, #CONSOLE_T_PUTC] cbz x2, putc_continue + cmp w14, #'\n' + b.ne putc + tst w1, #CONSOLE_FLAG_TRANSLATE_CRLF + b.eq putc mov x1, x15 + mov w0, #'\r' blr x2 + ldr x2, [x15, #CONSOLE_T_PUTC] +putc: + mov x1, x15 mov w0, w14 + blr x2 putc_continue: ldr x15, [x15] /* X15 = next struct */ b putc_loop -- cgit v1.2.3 From 24d16a2e40dc6b38bd89faed20e7a1651d834871 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Fri, 16 Aug 2019 17:07:42 +0800 Subject: intel: agilex: HMC driver calculate DDR size Driver will calculate DDR size instead of using hardcoded value Signed-off-by: Hadi Asyrafi Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde --- plat/intel/soc/agilex/soc/agilex_memory_controller.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/plat/intel/soc/agilex/soc/agilex_memory_controller.c b/plat/intel/soc/agilex/soc/agilex_memory_controller.c index f09238c1c..5f3cae7be 100644 --- a/plat/intel/soc/agilex/soc/agilex_memory_controller.c +++ b/plat/intel/soc/agilex/soc/agilex_memory_controller.c @@ -160,8 +160,6 @@ int init_hard_memory_controller(void) return status; } -/* mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, AGX_RSTMGR_BRGMODRST_DDRSCH);*/ - status = mem_calibration(); if (status) { ERROR("DDR: Memory Calibration Failed\n"); @@ -169,7 +167,6 @@ int init_hard_memory_controller(void) } configure_hmc_adaptor_regs(); -/* configure_ddr_sched_ctrl_regs();*/ return 0; } @@ -359,16 +356,17 @@ void configure_hmc_adaptor_regs(void) mmio_write_32(AGX_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data); /* Enable nonsecure access to DDR */ - mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, - AGX_DDR_SIZE - 1); - mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, - 0x1f); + data = get_physical_dram_size(); - mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, - AGX_DDR_SIZE - 1); + if (data < AGX_DDR_SIZE) + data = AGX_DDR_SIZE; - mmio_write_32(AGX_SOC_NOC_FW_DDR_SCR_ENABLESET, BIT(0) | BIT(8)); + mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, data - 1); + mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, 0x1f); + mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, data - 1); + + mmio_write_32(AGX_SOC_NOC_FW_DDR_SCR_ENABLESET, BIT(0) | BIT(8)); /* ECC enablement */ data = mmio_read_32(AGX_MPFE_IOHMC_REG_CTRLCFG1); -- cgit v1.2.3 From a33ec1e75a03074ea9abcb2d0bf878da6beab5e4 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Mon, 19 Aug 2019 11:06:18 -0500 Subject: Fix for N1 1043202 Errata Workaround ISB instruction was removed from the N1 1043202 Errata Workaround [1], this fix is adding the ISB instruction back in. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Signed-off-by: Lauren Wehrmeister Change-Id: I74eac7f6ad38991c36d423ad6aa44558033ad388 --- lib/cpus/aarch64/neoverse_n1.S | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index b143a2e7b..31e7a3a71 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -43,6 +43,7 @@ func errata_n1_1043202_wa msr CPUPMR_EL3, x0 ldr x0, =0x800200071 msr CPUPCR_EL3, x0 + isb 1: ret x17 endfunc errata_n1_1043202_wa -- cgit v1.2.3 From 7bdc469895b694670643e2acbf2ad2318992bab6 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Wed, 28 Nov 2018 11:20:37 +0000 Subject: plat/arm: Introduce corstone700 platform. This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey --- fdts/corstone700.dts | 147 +++++++++++++ plat/arm/board/corstone700/corstone700_helpers.S | 100 +++++++++ plat/arm/board/corstone700/corstone700_plat.c | 34 +++ plat/arm/board/corstone700/corstone700_pm.c | 22 ++ plat/arm/board/corstone700/corstone700_security.c | 16 ++ plat/arm/board/corstone700/corstone700_topology.c | 43 ++++ plat/arm/board/corstone700/include/platform_def.h | 228 +++++++++++++++++++++ plat/arm/board/corstone700/platform.mk | 49 +++++ .../corstone700/sp_min/corstone700_sp_min_setup.c | 13 ++ .../board/corstone700/sp_min/sp_min-corstone700.mk | 18 ++ 10 files changed, 670 insertions(+) create mode 100644 fdts/corstone700.dts create mode 100644 plat/arm/board/corstone700/corstone700_helpers.S create mode 100644 plat/arm/board/corstone700/corstone700_plat.c create mode 100644 plat/arm/board/corstone700/corstone700_pm.c create mode 100644 plat/arm/board/corstone700/corstone700_security.c create mode 100644 plat/arm/board/corstone700/corstone700_topology.c create mode 100644 plat/arm/board/corstone700/include/platform_def.h create mode 100644 plat/arm/board/corstone700/platform.mk create mode 100644 plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c create mode 100644 plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk diff --git a/fdts/corstone700.dts b/fdts/corstone700.dts new file mode 100644 index 000000000..16cf41227 --- /dev/null +++ b/fdts/corstone700.dts @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +/ { + model = "corstone700"; + compatible = "arm,Corstone-700"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs = "console=ttyAMA0 root=/dev/vda2 rw loglevel=9"; + linux,initrd-start = <0x02a00000>; + linux,initrd-end = <0x04000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0>; + next-level-cache = <&L2_0>; + }; + + }; + + memory@2000000 { + device_type = "memory"; + reg = <0x02000000 0x02000000>; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; + interrupts = <1 9 0xf08>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + + refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + smbclk: refclk24mhzx2 { + /* Reference 24MHz clock x 2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "smclk"; + }; + + + serial0: uart@1a510000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a510000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 19 4>; + clocks = <&refclk100mhz>, <&smbclk>; + clock-names = "apb_pclk", "smclk"; + }; + + serial1: uart@1a520000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a520000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 20 4>; + clocks = <&refclk100mhz>, <&smbclk>; + clock-names = "apb_pclk", "smclk"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + mbox_es0mhu0: mhu@1b000000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b000000 0x1000>, + <0x1b010000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <0 12 4>; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-es0-mhu0"; + }; + + mbox_es0mhu1: mhu@1b020000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b020000 0x1000>, + <0x1b030000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <0 47 4>; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-es0-mhu1"; + }; + + mbox_semhu1: mhu@1b820000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b820000 0x1000>, + <0x1b830000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <0 45 4>; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-se-mhu1"; + }; + + client { + compatible = "arm,client"; + mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>; + mbox-names = "es0mhu0", "es0mhu1", "semhu1"; + }; + + extsys0: extsys@1A010310 { + compatible = "arm,extsys_ctrl"; + reg = <0x1A010310 0x4>, + <0x1A010314 0x4>; + reg-names = "rstreg", "streg"; + }; + +}; diff --git a/plat/arm/board/corstone700/corstone700_helpers.S b/plat/arm/board/corstone700/corstone700_helpers.S new file mode 100644 index 000000000..c713f4f1a --- /dev/null +++ b/plat/arm/board/corstone700/corstone700_helpers.S @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + .globl plat_arm_calc_core_pos + + /* -------------------------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * For AArch32, cold-booting secondary CPUs is not yet + * implemented and they panic. + * -------------------------------------------------------------------- + */ +func plat_secondary_cold_boot_setup +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * unsigned long plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and warm + * boot. On Corstone700, this information can be queried from the power + * controller. The Power Control SYS Status Register (PSYSR) indicates + * the wake-up reason for the CPU. + * + * For a cold boot, return 0. + * For a warm boot, Not yet supported. + * + * TODO: PSYSR is a common register and should be + * accessed using locks. Since it is not possible + * to use locks immediately after a cold reset + * we are relying on the fact that after a cold + * reset all cpus will read the same WK field + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* TODO support warm boot */ + /* Cold reset */ + mov r0, #0 + bx lr +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current CPU is the primary + * CPU. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + ldcopr r0, MPIDR + ldr r1, =MPIDR_AFFINITY_MASK + and r0, r1 + cmp r0, #0 + moveq r0, #1 + movne r0, #0 + bx lr +endfunc plat_is_my_cpu_primary + + /* --------------------------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) + * + * Function to calculate the core position on Corstone700. + * + * (ClusterId * MAX_CPUS_PER_CLUSTER * MAX_PE_PER_CPU) + + * (CPUId * MAX_PE_PER_CPU) + + * ThreadId + * + * which can be simplified as: + * + * ((ClusterId * MAX_CPUS_PER_CLUSTER + CPUId) * MAX_PE_PER_CPU) + * + ThreadId + * --------------------------------------------------------------------- + */ +func plat_arm_calc_core_pos + mov r3, r0 + + /* Extract individual affinity fields from MPIDR */ + ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS + ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS + ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS + + /* Compute linear position */ + mov r3, #CORSTONE700_MAX_CPUS_PER_CLUSTER + mla r1, r2, r3, r1 + mov r3, #CORSTONE700_MAX_PE_PER_CPU + mla r0, r1, r3, r0 + + bx lr +endfunc plat_arm_calc_core_pos diff --git a/plat/arm/board/corstone700/corstone700_plat.c b/plat/arm/board/corstone700/corstone700_plat.c new file mode 100644 index 000000000..cee6fd618 --- /dev/null +++ b/plat/arm/board/corstone700/corstone700_plat.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +/* + * Table of regions to map using the MMU. + * Replace or extend the below regions as required + */ + +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + ARM_MAP_NS_DRAM1, + CORSTONE700_MAP_DEVICE, + {0} +}; + +/* Corstone700 only has one always-on power domain and there + * is no power control present + */ +void __init plat_arm_pwrc_setup(void) +{ +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return CORSTONE700_TIMER_BASE_FREQUENCY; +} diff --git a/plat/arm/board/corstone700/corstone700_pm.c b/plat/arm/board/corstone700/corstone700_pm.c new file mode 100644 index 000000000..4884ea519 --- /dev/null +++ b/plat/arm/board/corstone700/corstone700_pm.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +/******************************************************************************* + * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard + * platform layer will take care of registering the handlers with PSCI. + ******************************************************************************/ +plat_psci_ops_t plat_arm_psci_pm_ops = { + /* dummy struct */ + .validate_ns_entrypoint = NULL +}; + +const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) +{ + return ops; +} diff --git a/plat/arm/board/corstone700/corstone700_security.c b/plat/arm/board/corstone700/corstone700_security.c new file mode 100644 index 000000000..39b2fc902 --- /dev/null +++ b/plat/arm/board/corstone700/corstone700_security.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * We assume that all security programming is done by the primary core. + */ +void plat_arm_security_setup(void) +{ + /* + * If the platform had additional peripheral specific security + * configurations, those would be configured here. + */ +} diff --git a/plat/arm/board/corstone700/corstone700_topology.c b/plat/arm/board/corstone700/corstone700_topology.c new file mode 100644 index 000000000..d9445e0c5 --- /dev/null +++ b/plat/arm/board/corstone700/corstone700_topology.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +/* The Corstone700 power domain tree descriptor */ +static unsigned char corstone700_power_domain_tree_desc + [PLAT_ARM_CLUSTER_COUNT + 2]; +/******************************************************************************* + * This function dynamically constructs the topology according to + * CLUSTER_COUNT and returns it. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + int i; + + /* + * The highest level is the system level. The next level is constituted + * by clusters and then cores in clusters. + */ + corstone700_power_domain_tree_desc[0] = 1; + corstone700_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT; + + for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++) + corstone700_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT; + + return corstone700_power_domain_tree_desc; +} + +/****************************************************************************** + * This function implements a part of the critical interface between the PSCI + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is + * returned in case the MPIDR is invalid. + *****************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + return plat_arm_calc_core_pos(mpidr); +} diff --git a/plat/arm/board/corstone700/include/platform_def.h b/plat/arm/board/corstone700/include/platform_def.h new file mode 100644 index 000000000..de99b06ad --- /dev/null +++ b/plat/arm/board/corstone700/include/platform_def.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include +#include +#include +#include + +/* Core/Cluster/Thread counts for Corstone700 */ +#define CORSTONE700_CLUSTER_COUNT 1 +#define CORSTONE700_MAX_CPUS_PER_CLUSTER 4 +#define CORSTONE700_MAX_PE_PER_CPU 1 +#define CORSTONE700_CORE_COUNT (CORSTONE700_CLUSTER_COUNT * \ + CORSTONE700_MAX_CPUS_PER_CLUSTER * \ + CORSTONE700_MAX_PE_PER_CPU) +#define PLATFORM_CORE_COUNT CORSTONE700_CORE_COUNT +#define PLAT_ARM_CLUSTER_COUNT CORSTONE700_CLUSTER_COUNT + +/* UART related constants */ +#define PLAT_ARM_BOOT_UART_BASE 0x1a510000 +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ +#define PLAT_ARM_RUN_UART_BASE 0x1a520000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ +#define ARM_CONSOLE_BAUDRATE 115200 +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ + +/* Memory related constants */ +#define ARM_DRAM1_BASE UL(0x80000000) +#define ARM_DRAM1_SIZE UL(0x80000000) +#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - 1) +#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE +#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ + ARM_NS_DRAM1_SIZE - 1) +#define ARM_TRUSTED_SRAM_BASE UL(0x02000000) +#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE +#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ +#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ + +/* The remaining Trusted SRAM is used to load the BL images */ +#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ + ARM_SHARED_RAM_SIZE) +#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ + ARM_SHARED_RAM_SIZE) + +/* + * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding + * the page reserved for fw_configs) to BL32 + */ +#define BL32_BASE (ARM_BL_RAM_BASE + PAGE_SIZE) +#define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) +#define ARM_CACHE_WRITEBACK_SHIFT 6 + +/* + * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base + * and limit. Leave enough space for BL2 meminfo. + */ +#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) +#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U)) + +/* + * The max number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#define ARM_BL_REGIONS 2 +#define PLAT_ARM_MMAP_ENTRIES 8 +#define MAX_XLAT_TABLES 5 +#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ + ARM_BL_REGIONS) + +/* GIC related constants */ +#define PLAT_ARM_GICD_BASE 0x1C010000 +#define PLAT_ARM_GICC_BASE 0x1C02F000 + +/* Timer/watchdog related constants */ +#define ARM_SYS_CNTCTL_BASE UL(0x1a200000) +#define ARM_SYS_CNTREAD_BASE UL(0x1a210000) +#define ARM_SYS_TIMCTL_BASE UL(0x1a220000) +#define CORSTONE700_TIMER_BASE_FREQUENCY UL(24000000) +#define CORSTONE700_IRQ_TZ_WDOG 32 +#define CORSTONE700_IRQ_SEC_SYS_TIMER 34 + +#define PLAT_MAX_PWR_LVL 2 +/* + * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The + * power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +#define ARM_PWR_LVL0 MPIDR_AFFLVL0 +#define ARM_PWR_LVL1 MPIDR_AFFLVL1 +#define ARM_PWR_LVL2 MPIDR_AFFLVL2 + +/* + * Macros for local power states in ARM platforms encoded by State-ID field + * within the power-state parameter. + */ +/* Local power state for power domains in Run state. */ +#define ARM_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define ARM_LOCAL_STATE_RET U(1) +/* Local power state for OFF/power-down. Valid for CPU and cluster + * power domains + */ +#define ARM_LOCAL_STATE_OFF U(2) + +#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE +#define PLAT_ARM_NSTIMER_FRAME_ID U(1) + +#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000)) + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +/* + * This macro defines the deepest retention state possible. A higher state + * ID will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE 1 + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE 2 + +#define PLATFORM_STACK_SIZE UL(0x440) + +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, \ + ARM_SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, \ + ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END \ + - BL_CODE_BASE, \ + MT_CODE | MT_SECURE), \ + MAP_REGION_FLAT( \ + BL_RO_DATA_BASE, \ + BL_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) +#if USE_COHERENT_MEM +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#define CORSTONE700_DEVICE_BASE (0x1A000000) +#define CORSTONE700_DEVICE_SIZE (0x26000000) +#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \ + CORSTONE700_DEVICE_BASE, \ + CORSTONE700_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE) + +#define ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE) + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) \ + +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/corstone700/platform.mk b/plat/arm/board/corstone700/platform.mk new file mode 100644 index 000000000..bff3589eb --- /dev/null +++ b/plat/arm/board/corstone700/platform.mk @@ -0,0 +1,49 @@ +# +# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +CORSTONE700_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S + +BL32_SOURCES += plat/arm/common/aarch32/arm_helpers.S \ + plat/arm/common/arm_console.c \ + plat/arm/common/arm_common.c \ + lib/xlat_tables/aarch32/xlat_tables.c \ + lib/xlat_tables/xlat_tables_common.c \ + ${CORSTONE700_CPU_LIBS} + +PLAT_INCLUDES := -Iplat/arm/board/corstone700/include + +NEED_BL32 := yes + +CORSTONE700_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c \ + plat/arm/common/arm_gicv2.c + +# BL1/BL2 Image not a part of the capsule Image for Corstone700 +override NEED_BL1 := no +override NEED_BL2 := no +override NEED_BL2U := no + +#TFA for Corstone700 starts from BL32 +override RESET_TO_SP_MIN := 1 + +#Device tree +CORSTONE700_HW_CONFIG_DTS := fdts/corstone700.dts +CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb +FDT_SOURCES += ${CORSTONE700_HW_CONFIG_DTS} +$(eval CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(CORSTONE700_HW_CONFIG_DTS))) + +# Add the HW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE700_HW_CONFIG},--hw-config)) + +# Check for Linux kernel as a BL33 image by default +$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) + ifndef ARM_PRELOADED_DTB_BASE + $(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.") + endif + $(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) +include plat/arm/board/common/board_common.mk diff --git a/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c b/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c new file mode 100644 index 000000000..2fc0e0dec --- /dev/null +++ b/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); +} diff --git a/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk new file mode 100644 index 000000000..57e1ec3e4 --- /dev/null +++ b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk @@ -0,0 +1,18 @@ +# +# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# SP_MIN source files specific to FVP platform +BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \ + lib/utils/mem_region.c \ + plat/arm/board/corstone700/corstone700_helpers.S \ + plat/arm/board/corstone700/corstone700_topology.c \ + plat/arm/board/corstone700/corstone700_security.c \ + plat/arm/board/corstone700/corstone700_plat.c \ + plat/arm/board/corstone700/corstone700_pm.c \ + plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c \ + ${CORSTONE700_GIC_SOURCES} + +include plat/arm/common/sp_min/arm_sp_min.mk -- cgit v1.2.3 From e290a8fcbc836d51566da1607add8a320d0f1a20 Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Tue, 13 Aug 2019 15:17:53 +0100 Subject: AArch64: Disable Secure Cycle Counter This patch fixes an issue when secure world timing information can be leaked because Secure Cycle Counter is not disabled. For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR_EL0.DP bit. 'include\aarch64\arch.h' header file was tided up and new ARMv8.5-PMU related definitions were added. Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa Signed-off-by: Alexei Fedorov --- bl1/aarch64/bl1_exceptions.S | 10 ++++- bl31/aarch64/ea_delegate.S | 14 +++++++ bl31/aarch64/runtime_exceptions.S | 22 ++++++++++ include/arch/aarch64/arch.h | 30 +++++++------ include/arch/aarch64/el3_common_macros.S | 34 ++++++++++++++- include/lib/el3_runtime/aarch64/context.h | 19 ++++----- lib/el3_runtime/aarch64/context.S | 65 +++++++++++++++++++++++++--- lib/el3_runtime/aarch64/context_mgmt.c | 70 ++++++++++++++++--------------- 8 files changed, 200 insertions(+), 64 deletions(-) diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index 19a0ac27a..ed7c27a18 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -223,6 +223,14 @@ smc_handler: */ bl save_gp_registers + /* ----------------------------------------------------- + * If Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, save PMCR_EL0 and + * disable all event counters and cycle counter. + * ----------------------------------------------------- + */ + bl save_pmcr_disable_pmu + /* ----------------------------------------------------- * Populate the parameters for the SMC handler. We * already have x0-x4 in place. x5 will point to a diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S index 40c3191ac..8dca10cf9 100644 --- a/bl31/aarch64/ea_delegate.S +++ b/bl31/aarch64/ea_delegate.S @@ -68,6 +68,13 @@ func enter_lower_el_sync_ea /* Save GP registers */ bl save_gp_registers + /* + * If Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, save PMCR_EL0 and + * disable all event counters and cycle counter. + */ + bl save_pmcr_disable_pmu + /* Save ARMv8.3-PAuth registers and load firmware key */ #if CTX_INCLUDE_PAUTH_REGS bl pauth_context_save @@ -106,6 +113,13 @@ func enter_lower_el_async_ea /* Save GP registers */ bl save_gp_registers + /* + * If Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, save PMCR_EL0 and + * disable all event counters and cycle counter. + */ + bl save_pmcr_disable_pmu + /* Save ARMv8.3-PAuth registers and load firmware key */ #if CTX_INCLUDE_PAUTH_REGS bl pauth_context_save diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 6ffd99555..fd7656e2c 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -67,6 +67,14 @@ /* Save GP registers and restore them afterwards */ bl save_gp_registers + + /* + * If Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, save PMCR_EL0 and + * disable all event counters and cycle counter. + */ + bl save_pmcr_disable_pmu + bl handle_lower_el_ea_esb bl restore_gp_registers @@ -123,6 +131,13 @@ bl save_gp_registers + /* + * If Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, save PMCR_EL0 and + * disable all event counters and cycle counter. + */ + bl save_pmcr_disable_pmu + /* Save ARMv8.3-PAuth registers and load firmware key */ #if CTX_INCLUDE_PAUTH_REGS bl pauth_context_save @@ -335,6 +350,13 @@ smc_handler64: /* Save general purpose registers */ bl save_gp_registers + /* + * If Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, save PMCR_EL0 and + * disable all event counters and cycle counter. + */ + bl save_pmcr_disable_pmu + /* Save ARMv8.3-PAuth registers and load firmware key */ #if CTX_INCLUDE_PAUTH_REGS bl pauth_context_save diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index fa857fb1b..98a8590b3 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -132,12 +132,13 @@ #define ID_AA64PFR0_EL2_SHIFT U(8) #define ID_AA64PFR0_EL3_SHIFT U(12) #define ID_AA64PFR0_AMU_SHIFT U(44) -#define ID_AA64PFR0_AMU_LENGTH U(4) #define ID_AA64PFR0_AMU_MASK ULL(0xf) #define ID_AA64PFR0_ELX_MASK ULL(0xf) +#define ID_AA64PFR0_GIC_SHIFT U(24) +#define ID_AA64PFR0_GIC_WIDTH U(4) +#define ID_AA64PFR0_GIC_MASK ULL(0xf) #define ID_AA64PFR0_SVE_SHIFT U(32) #define ID_AA64PFR0_SVE_MASK ULL(0xf) -#define ID_AA64PFR0_SVE_LENGTH U(4) #define ID_AA64PFR0_MPAM_SHIFT U(40) #define ID_AA64PFR0_MPAM_MASK ULL(0xf) #define ID_AA64PFR0_DIT_SHIFT U(48) @@ -148,18 +149,14 @@ #define ID_AA64PFR0_CSV2_MASK ULL(0xf) #define ID_AA64PFR0_CSV2_LENGTH U(4) -/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ -#define ID_AA64DFR0_PMS_SHIFT U(32) -#define ID_AA64DFR0_PMS_LENGTH U(4) -#define ID_AA64DFR0_PMS_MASK ULL(0xf) - +/* Exception level handling */ #define EL_IMPL_NONE ULL(0) #define EL_IMPL_A64ONLY ULL(1) #define EL_IMPL_A64_A32 ULL(2) -#define ID_AA64PFR0_GIC_SHIFT U(24) -#define ID_AA64PFR0_GIC_WIDTH U(4) -#define ID_AA64PFR0_GIC_MASK ULL(0xf) +/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ +#define ID_AA64DFR0_PMS_SHIFT U(32) +#define ID_AA64DFR0_PMS_MASK ULL(0xf) /* ID_AA64ISAR1_EL1 definitions */ #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 @@ -304,20 +301,25 @@ #define SCR_RESET_VAL SCR_RES1_BITS /* MDCR_EL3 definitions */ +#define MDCR_SCCD_BIT (ULL(1) << 23) +#define MDCR_SPME_BIT (ULL(1) << 17) +#define MDCR_SDD_BIT (ULL(1) << 16) #define MDCR_SPD32(x) ((x) << 14) #define MDCR_SPD32_LEGACY ULL(0x0) #define MDCR_SPD32_DISABLE ULL(0x2) #define MDCR_SPD32_ENABLE ULL(0x3) -#define MDCR_SDD_BIT (ULL(1) << 16) #define MDCR_NSPB(x) ((x) << 12) #define MDCR_NSPB_EL1 ULL(0x3) #define MDCR_TDOSA_BIT (ULL(1) << 10) #define MDCR_TDA_BIT (ULL(1) << 9) #define MDCR_TPM_BIT (ULL(1) << 6) -#define MDCR_SCCD_BIT (ULL(1) << 23) #define MDCR_EL3_RESET_VAL ULL(0x0) /* MDCR_EL2 definitions */ +#define MDCR_EL2_HLP (U(1) << 26) +#define MDCR_EL2_HCCD (U(1) << 23) +#define MDCR_EL2_TTRF (U(1) << 19) +#define MDCR_EL2_HPMD (U(1) << 17) #define MDCR_EL2_TPMS (U(1) << 14) #define MDCR_EL2_E2PB(x) ((x) << 12) #define MDCR_EL2_E2PB_EL1 U(0x3) @@ -677,10 +679,14 @@ #define PMCR_EL0_N_SHIFT U(11) #define PMCR_EL0_N_MASK U(0x1f) #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) +#define PMCR_EL0_LP_BIT (U(1) << 7) #define PMCR_EL0_LC_BIT (U(1) << 6) #define PMCR_EL0_DP_BIT (U(1) << 5) #define PMCR_EL0_X_BIT (U(1) << 4) #define PMCR_EL0_D_BIT (U(1) << 3) +#define PMCR_EL0_C_BIT (U(1) << 2) +#define PMCR_EL0_P_BIT (U(1) << 1) +#define PMCR_EL0_E_BIT (U(1) << 0) /******************************************************************************* * Definitions for system register interface to SVE diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 22b32b491..a36b7da79 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -116,11 +116,41 @@ * --------------------------------------------------------------------- */ mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ - MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) \ - & ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT)) + MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \ + ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT)) msr mdcr_el3, x0 + /* --------------------------------------------------------------------- + * Initialise PMCR_EL0 setting all fields rather than relying + * on hw. Some fields are architecturally UNKNOWN on reset. + * + * PMCR_EL0.LP: Set to one so that event counter overflow, that + * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment + * that changes PMEVCNTR_EL0[63] from 1 to 0, when ARMv8.5-PMU + * is implemented. This bit is RES0 in versions of the architecture + * earlier than ARMv8.5, setting it to 1 doesn't have any effect + * on them. + * + * PMCR_EL0.LC: Set to one so that cycle counter overflow, that + * is recorded in PMOVSCLR_EL0[31], occurs on the increment + * that changes PMCCNTR_EL0[63] from 1 to 0. + * + * PMCR_EL0.DP: Set to one so that the cycle counter, + * PMCCNTR_EL0 does not count when event counting is prohibited. + * + * PMCR_EL0.X: Set to zero to disable export of events. + * + * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 + * counts on every clock cycle. + * --------------------------------------------------------------------- + */ + mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ + PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ + ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) + + msr pmcr_el0, x0 + /* --------------------------------------------------------------------- * Enable External Aborts and SError Interrupts now that the exception * vectors have been setup. diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index a76a59b78..64fa8a9ea 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -59,7 +59,7 @@ #define CTX_RUNTIME_SP U(0x10) #define CTX_SPSR_EL3 U(0x18) #define CTX_ELR_EL3 U(0x20) -#define CTX_UNUSED U(0x28) +#define CTX_PMCR_EL0 U(0x28) #define CTX_EL3STATE_END U(0x30) /******************************************************************************* @@ -91,22 +91,21 @@ #define CTX_AFSR1_EL1 U(0x98) #define CTX_CONTEXTIDR_EL1 U(0xa0) #define CTX_VBAR_EL1 U(0xa8) -#define CTX_PMCR_EL0 U(0xb0) /* * If the platform is AArch64-only, there is no need to save and restore these * AArch32 registers. */ #if CTX_INCLUDE_AARCH32_REGS -#define CTX_SPSR_ABT U(0xc0) /* Align to the next 16 byte boundary */ -#define CTX_SPSR_UND U(0xc8) -#define CTX_SPSR_IRQ U(0xd0) -#define CTX_SPSR_FIQ U(0xd8) -#define CTX_DACR32_EL2 U(0xe0) -#define CTX_IFSR32_EL2 U(0xe8) -#define CTX_AARCH32_END U(0xf0) /* Align to the next 16 byte boundary */ +#define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */ +#define CTX_SPSR_UND U(0xb8) +#define CTX_SPSR_IRQ U(0xc0) +#define CTX_SPSR_FIQ U(0xc8) +#define CTX_DACR32_EL2 U(0xd0) +#define CTX_IFSR32_EL2 U(0xd8) +#define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */ #else -#define CTX_AARCH32_END U(0xc0) /* Align to the next 16 byte boundary */ +#define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */ #endif /* CTX_INCLUDE_AARCH32_REGS */ /* diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index e6ab19bcc..53dc02e64 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -24,8 +24,44 @@ .global save_gp_registers .global restore_gp_registers .global restore_gp_registers_eret + .global save_pmcr_disable_pmu .global el3_exit +/* ----------------------------------------------------- + * If ARMv8.5-PMU is implemented, cycle counting is + * disabled by seting MDCR_EL3.SCCD to 1. + * ----------------------------------------------------- + */ +func save_pmcr_disable_pmu + /* ----------------------------------------------------- + * Check if earlier initialization MDCR_EL3.SCCD to 1 + * failed, meaning that ARMv8-PMU is not implemented and + * PMCR_EL0 should be saved in non-secure context. + * ----------------------------------------------------- + */ + mrs x9, mdcr_el3 + tst x9, #MDCR_SCCD_BIT + bne 1f + + /* Secure Cycle Counter is not disabled */ + mrs x9, pmcr_el0 + + /* Check caller's security state */ + mrs x10, scr_el3 + tst x10, #SCR_NS_BIT + beq 2f + + /* Save PMCR_EL0 if called from Non-secure state */ + str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] + + /* Disable cycle counter when event counting is prohibited */ +2: orr x9, x9, #PMCR_EL0_DP_BIT + msr pmcr_el0, x9 + + isb +1: ret +endfunc save_pmcr_disable_pmu + /* ----------------------------------------------------- * The following function strictly follows the AArch64 * PCS to use x9-x17 (temporary caller-saved registers) @@ -80,9 +116,6 @@ func el1_sysregs_context_save mrs x9, vbar_el1 stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] - mrs x10, pmcr_el0 - str x10, [x0, #CTX_PMCR_EL0] - /* Save AArch32 system registers if the build has instructed so */ #if CTX_INCLUDE_AARCH32_REGS mrs x11, spsr_abt @@ -169,9 +202,6 @@ func el1_sysregs_context_restore msr contextidr_el1, x17 msr vbar_el1, x9 - ldr x10, [x0, #CTX_PMCR_EL0] - msr pmcr_el0, x10 - /* Restore AArch32 system registers if the build has instructed so */ #if CTX_INCLUDE_AARCH32_REGS ldp x11, x12, [x0, #CTX_SPSR_ABT] @@ -503,6 +533,29 @@ func el3_exit msr spsr_el3, x16 msr elr_el3, x17 + /* ----------------------------------------------------- + * Restore PMCR_EL0 when returning to Non-secure state + * if Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented + * ----------------------------------------------------- + */ + tst x18, #SCR_NS_BIT + beq 2f + + /* ----------------------------------------------------- + * Back to Non-secure state. + * Check if earlier initialization MDCR_EL3.SCCD to 1 + * failed, meaning that ARMv8-PMU is not implemented and + * PMCR_EL0 should be restored from non-secure context. + * ----------------------------------------------------- + */ + mrs x17, mdcr_el3 + tst x17, #MDCR_SCCD_BIT + bne 2f + ldr x17, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] + msr pmcr_el0, x17 +2: + #if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 /* Restore mitigation state as it was on entry to EL3 */ ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE] diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 05ba5ed6c..bd5b3aa6c 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -66,7 +66,7 @@ void __init cm_init(void) void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) { unsigned int security_state; - uint32_t scr_el3, pmcr_el0; + uint32_t scr_el3; el3_state_t *state; gp_regs_t *gp_regs; unsigned long sctlr_elx, actlr_elx; @@ -225,31 +225,10 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) actlr_elx = read_actlr_el1(); write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); - if (security_state == SECURE) { - /* - * Initialise PMCR_EL0 for secure context only, setting all - * fields rather than relying on hw. Some fields are - * architecturally UNKNOWN on reset. - * - * PMCR_EL0.LC: Set to one so that cycle counter overflow, that - * is recorded in PMOVSCLR_EL0[31], occurs on the increment - * that changes PMCCNTR_EL0[63] from 1 to 0. - * - * PMCR_EL0.DP: Set to one so that the cycle counter, - * PMCCNTR_EL0 does not count when event counting is prohibited. - * - * PMCR_EL0.X: Set to zero to disable export of events. - * - * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 - * counts on every clock cycle. - */ - pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT - | PMCR_EL0_DP_BIT) - & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); - write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); - } - - /* Populate EL3 state so that we've the right context before doing ERET */ + /* + * Populate EL3 state so that we've the right context + * before doing ERET + */ state = get_el3state_ctx(ctx); write_ctx_reg(state, CTX_SCR_EL3, scr_el3); write_ctx_reg(state, CTX_ELR_EL3, ep->pc); @@ -441,6 +420,29 @@ void cm_prepare_el3_exit(uint32_t security_state) * relying on hw. Some fields are architecturally * UNKNOWN on reset. * + * MDCR_EL2.HLP: Set to one so that event counter + * overflow, that is recorded in PMOVSCLR_EL0[0-30], + * occurs on the increment that changes + * PMEVCNTR_EL0[63] from 1 to 0, when ARMv8.5-PMU is + * implemented. This bit is RES0 in versions of the + * architecture earlier than ARMv8.5, setting it to 1 + * doesn't have any effect on them. + * + * MDCR_EL2.TTRF: Set to zero so that access to Trace + * Filter Control register TRFCR_EL1 at EL1 is not + * trapped to EL2. This bit is RES0 in versions of + * the architecture earlier than ARMv8.4. + * + * MDCR_EL2.HPMD: Set to one so that event counting is + * prohibited at EL2. This bit is RES0 in versions of + * the architecture earlier than ARMv8.1, setting it + * to 1 doesn't have any effect on them. + * + * MDCR_EL2.TPMS: Set to zero so that accesses to + * Statistical Profiling control registers from EL1 + * do not trap to EL2. This bit is RES0 when SPE is + * not implemented. + * * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and * EL1 System register accesses to the Debug ROM * registers are not trapped to EL2. @@ -469,13 +471,15 @@ void cm_prepare_el3_exit(uint32_t security_state) * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the * architecturally-defined reset value. */ - mdcr_el2 = ((MDCR_EL2_RESET_VAL | - ((read_pmcr_el0() & PMCR_EL0_N_BITS) - >> PMCR_EL0_N_SHIFT)) & - ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT - | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT - | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT - | MDCR_EL2_TPMCR_BIT)); + mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | + MDCR_EL2_HPMD) | + ((read_pmcr_el0() & PMCR_EL0_N_BITS) + >> PMCR_EL0_N_SHIFT)) & + ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | + MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | + MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | + MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | + MDCR_EL2_TPMCR_BIT); write_mdcr_el2(mdcr_el2); -- cgit v1.2.3 From 40c711a3608e5529bb212c97afc24caebc7fe2ac Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 7 Aug 2019 18:05:05 +0200 Subject: rcar_get3: drivers: ddr: Clean up common code Do minor coding style changes to the common DDR init code to make it checkpatch compliant and move macros out into rcar_def.h. Signed-off-by: Marek Vasut Change-Id: I67eadf8099e4ff8702105c9e07b13f308d9dbe3d --- drivers/staging/renesas/rcar/ddr/boot_init_dram.h | 12 +-- drivers/staging/renesas/rcar/ddr/dram_sub_func.c | 93 ++++++++++------------- drivers/staging/renesas/rcar/ddr/dram_sub_func.h | 10 +-- plat/renesas/rcar/include/rcar_def.h | 12 ++- 4 files changed, 61 insertions(+), 66 deletions(-) diff --git a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h b/drivers/staging/renesas/rcar/ddr/boot_init_dram.h index 4b0a9ebe4..ac237b2ef 100644 --- a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h +++ b/drivers/staging/renesas/rcar/ddr/boot_init_dram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,10 +9,10 @@ extern int32_t rcar_dram_init(void); -#define INITDRAM_OK (0) -#define INITDRAM_NG (0xffffffff) -#define INITDRAM_ERR_I (0xffffffff) -#define INITDRAM_ERR_O (0xfffffffe) -#define INITDRAM_ERR_T (0xfffffff0) +#define INITDRAM_OK 0 +#define INITDRAM_NG 0xffffffff +#define INITDRAM_ERR_I 0xffffffff +#define INITDRAM_ERR_O 0xfffffffe +#define INITDRAM_ERR_T 0xfffffff0 #endif /* BOOT_INIT_DRAM_H */ diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c index c6ab44abc..ab8eabbc6 100644 --- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c +++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c @@ -12,38 +12,30 @@ #if RCAR_SYSTEM_SUSPEND /* Local defines */ -#define DRAM_BACKUP_GPIO_USE (0) +#define DRAM_BACKUP_GPIO_USE 0 #include "iic_dvfs.h" #if PMIC_ROHM_BD9571 -#define PMIC_SLAVE_ADDR (0x30U) -#define PMIC_BKUP_MODE_CNT (0x20U) -#define PMIC_QLLM_CNT (0x27U) -#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U)) -#define BIT_QLLM_DDR0_EN ((uint8_t)(1U << 0U)) -#define BIT_QLLM_DDR1_EN ((uint8_t)(1U << 1U)) +#define PMIC_SLAVE_ADDR 0x30U +#define PMIC_BKUP_MODE_CNT 0x20U +#define PMIC_QLLM_CNT 0x27U +#define BIT_BKUP_CTRL_OUT BIT(4) +#define BIT_QLLM_DDR0_EN BIT(0) +#define BIT_QLLM_DDR1_EN BIT(1) #endif -#define GPIO_OUTDT1 (0xE6051008U) -#define GPIO_OUTDT3 (0xE6053008U) -#define GPIO_INDT3 (0xE605300CU) -#define GPIO_OUTDT6 (0xE6055408U) +#define GPIO_BKUP_REQB_SHIFT_SALVATOR 9U /* GP1_9 (BKUP_REQB) */ +#define GPIO_BKUP_TRG_SHIFT_SALVATOR 8U /* GP1_8 (BKUP_TRG) */ +#define GPIO_BKUP_REQB_SHIFT_EBISU 14U /* GP6_14(BKUP_REQB) */ +#define GPIO_BKUP_TRG_SHIFT_EBISU 13U /* GP6_13(BKUP_TRG) */ +#define GPIO_BKUP_REQB_SHIFT_CONDOR 1U /* GP3_1 (BKUP_REQB) */ +#define GPIO_BKUP_TRG_SHIFT_CONDOR 0U /* GP3_0 (BKUP_TRG) */ -#if DRAM_BACKUP_GPIO_USE == 1 -#define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U) /* GP1_9 (BKUP_REQB) */ -#define GPIO_BKUP_REQB_SHIFT_EBISU (14U) /* GP6_14(BKUP_REQB) */ -#define GPIO_BKUP_REQB_SHIFT_CONDOR (1U) /* GP3_1 (BKUP_REQB) */ -#endif -#define GPIO_BKUP_TRG_SHIFT_SALVATOR (8U) /* GP1_8 (BKUP_TRG) */ -#define GPIO_BKUP_TRG_SHIFT_EBISU (13U) /* GP6_13(BKUP_TRG) */ -#define GPIO_BKUP_TRG_SHIFT_CONDOR (0U) /* GP3_0 (BKUP_TRG) */ - -#define DRAM_BKUP_TRG_LOOP_CNT (1000U) +#define DRAM_BKUP_TRG_LOOP_CNT 1000U #endif -void rcar_dram_get_boot_status(uint32_t * status) +void rcar_dram_get_boot_status(uint32_t *status) { #if RCAR_SYSTEM_SUSPEND - uint32_t reg_data; uint32_t product; uint32_t shift; @@ -62,11 +54,10 @@ void rcar_dram_get_boot_status(uint32_t * status) } reg_data = mmio_read_32(gpio); - if (0U != (reg_data & ((uint32_t)1U << shift))) { + if (reg_data & BIT(shift)) *status = DRAM_BOOT_STATUS_WARM; - } else { + else *status = DRAM_BOOT_STATUS_COLD; - } #else /* RCAR_SYSTEM_SUSPEND */ *status = DRAM_BOOT_STATUS_COLD; #endif /* RCAR_SYSTEM_SUSPEND */ @@ -116,55 +107,55 @@ int32_t rcar_dram_update_boot_status(uint32_t status) } if (status == DRAM_BOOT_STATUS_WARM) { -#if DRAM_BACKUP_GPIO_USE==1 - mmio_setbits_32(outd, 1U << reqb); +#if DRAM_BACKUP_GPIO_USE == 1 + mmio_setbits_32(outd, BIT(reqb)); #else #if PMIC_ROHM_BD9571 /* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */ i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR, - PMIC_BKUP_MODE_CNT, &bkup_mode_cnt); - if (0 != i2c_dvfs_ret) { + PMIC_BKUP_MODE_CNT, + &bkup_mode_cnt); + if (i2c_dvfs_ret) { ERROR("BKUP mode cnt READ ERROR.\n"); ret = DRAM_UPDATE_STATUS_ERR; } else { bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT; i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR, - PMIC_BKUP_MODE_CNT, bkup_mode_cnt); - if (0 != i2c_dvfs_ret) { - ERROR("BKUP mode cnt WRITE ERROR. " - "value = %d\n", bkup_mode_cnt); + PMIC_BKUP_MODE_CNT, + bkup_mode_cnt); + if (i2c_dvfs_ret) { + ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", + bkup_mode_cnt); ret = DRAM_UPDATE_STATUS_ERR; } } #endif /* PMIC_ROHM_BD9571 */ -#endif /* DRAM_BACKUP_GPIO_USE==1 */ +#endif /* DRAM_BACKUP_GPIO_USE == 1 */ /* Wait BKUP_TRG=Low */ loop_count = DRAM_BKUP_TRG_LOOP_CNT; - while (0U < loop_count) { + while (loop_count > 0) { reg_data = mmio_read_32(gpio); - if ((reg_data & - ((uint32_t)1U << trg)) == 0U) { + if (!(reg_data & BIT(trg))) break; - } loop_count--; } - if (0U == loop_count) { - ERROR( "\nWarm booting...\n" \ - " The potential of BKUP_TRG did not switch " \ - "to Low.\n If you expect the operation of " \ - "cold boot,\n check the board configuration" \ - " (ex, Dip-SW) and/or the H/W failure.\n"); + + if (!loop_count) { + ERROR("\nWarm booting...\n" + " The potential of BKUP_TRG did not switch to Low.\n" + " If you expect the operation of cold boot,\n" + " check the board configuration (ex, Dip-SW) and/or the H/W failure.\n"); ret = DRAM_UPDATE_STATUS_ERR; } } #if PMIC_ROHM_BD9571 - if(0 == ret) { - qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN); + if (!ret) { + qllm_cnt = BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN; i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR, - PMIC_QLLM_CNT, qllm_cnt); - if (0 != i2c_dvfs_ret) { - ERROR("QLLM cnt WRITE ERROR. " - "value = %d\n", qllm_cnt); + PMIC_QLLM_CNT, + qllm_cnt); + if (i2c_dvfs_ret) { + ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm_cnt); ret = DRAM_UPDATE_STATUS_ERR; } } diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h b/drivers/staging/renesas/rcar/ddr/dram_sub_func.h index 7e88f4222..69c4d8605 100644 --- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h +++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,11 +7,11 @@ #ifndef DRAM_SUB_FUNC_H #define DRAM_SUB_FUNC_H -#define DRAM_UPDATE_STATUS_ERR (-1) -#define DRAM_BOOT_STATUS_COLD (0) -#define DRAM_BOOT_STATUS_WARM (1) +#define DRAM_UPDATE_STATUS_ERR -1 +#define DRAM_BOOT_STATUS_COLD 0 +#define DRAM_BOOT_STATUS_WARM 1 int32_t rcar_dram_update_boot_status(uint32_t status); -void rcar_dram_get_boot_status(uint32_t * status); +void rcar_dram_get_boot_status(uint32_t *status); #endif /* DRAM_SUB_FUNC_H */ diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h index a60f9b68e..e2dae9bc9 100644 --- a/plat/renesas/rcar/include/rcar_def.h +++ b/plat/renesas/rcar/include/rcar_def.h @@ -267,11 +267,15 @@ #define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT) #define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT) /* for SuspendToRAM */ -#define GPIO_BASE (0xE6050000U) -#define GPIO_INDT1 (GPIO_BASE + 0x100CU) +#define GPIO_BASE (0xE6050000U) +#define GPIO_INDT1 (GPIO_BASE + 0x100CU) +#define GPIO_INDT3 (GPIO_BASE + 0x300CU) #define GPIO_INDT6 (GPIO_BASE + 0x540CU) -#define RCAR_COLD_BOOT (0x00U) -#define RCAR_WARM_BOOT (0x01U) +#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U) +#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U) +#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U) +#define RCAR_COLD_BOOT (0x00U) +#define RCAR_WARM_BOOT (0x01U) #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR #define KEEP10_MAGIC (0x55U) #endif -- cgit v1.2.3 From f12039be9532f4ff1e9bc01feda61e9b3bb31667 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 7 Aug 2019 18:19:26 +0200 Subject: rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B The ddr_a and ddr_b register macros are the same for the most part, unify them into a single header. Signed-off-by: Marek Vasut Change-Id: I8f55d6d779837215339ac0010e8c8ab5f6748d75 --- .../renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h | 285 +--- .../staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c | 768 +++++------ .../staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c | 1385 ++++++++++---------- .../staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c | 385 +++--- .../renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h | 205 +-- drivers/staging/renesas/rcar/ddr/ddr_regs.h | 257 ++++ plat/renesas/rcar/include/rcar_def.h | 2 + 7 files changed, 1531 insertions(+), 1756 deletions(-) create mode 100644 drivers/staging/renesas/rcar/ddr/ddr_regs.h diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h index 397bde04e..0f89b4350 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h @@ -5,287 +5,4 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef BOOT_INIT_DRAM_REGDEF_H_ -#define BOOT_INIT_DRAM_REGDEF_H_ - -/* DBSC registers */ -#define DBSC_DBSYSCONF0 0xE6790000U -#define DBSC_DBSYSCONF1 0xE6790004U -#define DBSC_DBPHYCONF0 0xE6790010U -#define DBSC_DBKIND 0xE6790020U -#define DBSC_DBMEMCONF00 0xE6790030U -#define DBSC_DBMEMCONF01 0xE6790034U -#define DBSC_DBMEMCONF02 0xE6790038U -#define DBSC_DBMEMCONF03 0xE679003CU -#define DBSC_DBMEMCONF10 0xE6790040U -#define DBSC_DBMEMCONF11 0xE6790044U -#define DBSC_DBMEMCONF12 0xE6790048U -#define DBSC_DBMEMCONF13 0xE679004CU -#define DBSC_DBMEMCONF20 0xE6790050U -#define DBSC_DBMEMCONF21 0xE6790054U -#define DBSC_DBMEMCONF22 0xE6790058U -#define DBSC_DBMEMCONF23 0xE679005CU -#define DBSC_DBMEMCONF30 0xE6790060U -#define DBSC_DBMEMCONF31 0xE6790064U -#define DBSC_DBMEMCONF32 0xE6790068U -#define DBSC_DBMEMCONF33 0xE679006CU -#define DBSC_DBSYSCNT0 0xE6790100U -#define DBSC_DBSVCR1 0xE6790104U -#define DBSC_DBSTATE0 0xE6790108U -#define DBSC_DBSTATE1 0xE679010CU -#define DBSC_DBINTEN 0xE6790180U -#define DBSC_DBINTSTAT0 0xE6790184U -#define DBSC_DBACEN 0xE6790200U -#define DBSC_DBRFEN 0xE6790204U -#define DBSC_DBCMD 0xE6790208U -#define DBSC_DBWAIT 0xE6790210U -#define DBSC_DBSYSCTRL0 0xE6790280U -#define DBSC_DBTR0 0xE6790300U -#define DBSC_DBTR1 0xE6790304U -#define DBSC_DBTR2 0xE6790308U -#define DBSC_DBTR3 0xE679030CU -#define DBSC_DBTR4 0xE6790310U -#define DBSC_DBTR5 0xE6790314U -#define DBSC_DBTR6 0xE6790318U -#define DBSC_DBTR7 0xE679031CU -#define DBSC_DBTR8 0xE6790320U -#define DBSC_DBTR9 0xE6790324U -#define DBSC_DBTR10 0xE6790328U -#define DBSC_DBTR11 0xE679032CU -#define DBSC_DBTR12 0xE6790330U -#define DBSC_DBTR13 0xE6790334U -#define DBSC_DBTR14 0xE6790338U -#define DBSC_DBTR15 0xE679033CU -#define DBSC_DBTR16 0xE6790340U -#define DBSC_DBTR17 0xE6790344U -#define DBSC_DBTR18 0xE6790348U -#define DBSC_DBTR19 0xE679034CU -#define DBSC_DBTR20 0xE6790350U -#define DBSC_DBTR21 0xE6790354U -#define DBSC_DBTR22 0xE6790358U -#define DBSC_DBTR23 0xE679035CU -#define DBSC_DBTR24 0xE6790360U -#define DBSC_DBTR25 0xE6790364U -#define DBSC_DBBL 0xE6790400U -#define DBSC_DBRFCNF1 0xE6790414U -#define DBSC_DBRFCNF2 0xE6790418U -#define DBSC_DBTSPCNF 0xE6790420U -#define DBSC_DBCALCNF 0xE6790424U -#define DBSC_DBRNK2 0xE6790438U -#define DBSC_DBRNK3 0xE679043CU -#define DBSC_DBRNK4 0xE6790440U -#define DBSC_DBRNK5 0xE6790444U -#define DBSC_DBPDNCNF 0xE6790450U -#define DBSC_DBODT0 0xE6790460U -#define DBSC_DBODT1 0xE6790464U -#define DBSC_DBODT2 0xE6790468U -#define DBSC_DBODT3 0xE679046CU -#define DBSC_DBODT4 0xE6790470U -#define DBSC_DBODT5 0xE6790474U -#define DBSC_DBODT6 0xE6790478U -#define DBSC_DBODT7 0xE679047CU -#define DBSC_DBADJ0 0xE6790500U -#define DBSC_DBDBICNT 0xE6790518U -#define DBSC_DBDFIPMSTRCNF 0xE6790520U -#define DBSC_DBDFIPMSTRSTAT 0xE6790524U -#define DBSC_DBDFILPCNF 0xE6790528U -#define DBSC_DBDFICUPDCNF 0xE679052CU -#define DBSC_DBDFISTAT0 0xE6790600U -#define DBSC_DBDFICNT0 0xE6790604U -#define DBSC_DBPDCNT00 0xE6790610U -#define DBSC_DBPDCNT01 0xE6790614U -#define DBSC_DBPDCNT02 0xE6790618U -#define DBSC_DBPDCNT03 0xE679061CU -#define DBSC_DBPDLK0 0xE6790620U -#define DBSC_DBPDRGA0 0xE6790624U -#define DBSC_DBPDRGD0 0xE6790628U -#define DBSC_DBPDSTAT00 0xE6790630U -#define DBSC_DBDFISTAT1 0xE6790640U -#define DBSC_DBDFICNT1 0xE6790644U -#define DBSC_DBPDCNT10 0xE6790650U -#define DBSC_DBPDCNT11 0xE6790654U -#define DBSC_DBPDCNT12 0xE6790658U -#define DBSC_DBPDCNT13 0xE679065CU -#define DBSC_DBPDLK1 0xE6790660U -#define DBSC_DBPDRGA1 0xE6790664U -#define DBSC_DBPDRGD1 0xE6790668U -#define DBSC_DBPDSTAT10 0xE6790670U -#define DBSC_DBDFISTAT2 0xE6790680U -#define DBSC_DBDFICNT2 0xE6790684U -#define DBSC_DBPDCNT20 0xE6790690U -#define DBSC_DBPDCNT21 0xE6790694U -#define DBSC_DBPDCNT22 0xE6790698U -#define DBSC_DBPDCNT23 0xE679069CU -#define DBSC_DBPDLK2 0xE67906A0U -#define DBSC_DBPDRGA2 0xE67906A4U -#define DBSC_DBPDRGD2 0xE67906A8U -#define DBSC_DBPDSTAT20 0xE67906B0U -#define DBSC_DBDFISTAT3 0xE67906C0U -#define DBSC_DBDFICNT3 0xE67906C4U -#define DBSC_DBPDCNT30 0xE67906D0U -#define DBSC_DBPDCNT31 0xE67906D4U -#define DBSC_DBPDCNT32 0xE67906D8U -#define DBSC_DBPDCNT33 0xE67906DCU -#define DBSC_DBPDLK3 0xE67906E0U -#define DBSC_DBPDRGA3 0xE67906E4U -#define DBSC_DBPDRGD3 0xE67906E8U -#define DBSC_DBPDSTAT30 0xE67906F0U -#define DBSC_DBBUS0CNF0 0xE6790800U -#define DBSC_DBBUS0CNF1 0xE6790804U -#define DBSC_DBCAM0CNF1 0xE6790904U -#define DBSC_DBCAM0CNF2 0xE6790908U -#define DBSC_DBCAM0CNF3 0xE679090CU -#define DBSC_DBCAM0CTRL0 0xE6790940U -#define DBSC_DBCAM0STAT0 0xE6790980U -#define DBSC_DBCAM1STAT0 0xE6790990U -#define DBSC_DBBCAMSWAP 0xE67909F0U -#define DBSC_DBBCAMDIS 0xE67909FCU -#define DBSC_DBSCHCNT0 0xE6791000U -#define DBSC_DBSCHCNT1 0xE6791004U -#define DBSC_DBSCHSZ0 0xE6791010U -#define DBSC_DBSCHRW0 0xE6791020U -#define DBSC_DBSCHRW1 0xE6791024U -#define DBSC_DBSCHQOS00 0xE6791030U -#define DBSC_DBSCHQOS01 0xE6791034U -#define DBSC_DBSCHQOS02 0xE6791038U -#define DBSC_DBSCHQOS03 0xE679103CU -#define DBSC_DBSCHQOS10 0xE6791040U -#define DBSC_DBSCHQOS11 0xE6791044U -#define DBSC_DBSCHQOS12 0xE6791048U -#define DBSC_DBSCHQOS13 0xE679104CU -#define DBSC_DBSCHQOS20 0xE6791050U -#define DBSC_DBSCHQOS21 0xE6791054U -#define DBSC_DBSCHQOS22 0xE6791058U -#define DBSC_DBSCHQOS23 0xE679105CU -#define DBSC_DBSCHQOS30 0xE6791060U -#define DBSC_DBSCHQOS31 0xE6791064U -#define DBSC_DBSCHQOS32 0xE6791068U -#define DBSC_DBSCHQOS33 0xE679106CU -#define DBSC_DBSCHQOS40 0xE6791070U -#define DBSC_DBSCHQOS41 0xE6791074U -#define DBSC_DBSCHQOS42 0xE6791078U -#define DBSC_DBSCHQOS43 0xE679107CU -#define DBSC_DBSCHQOS50 0xE6791080U -#define DBSC_DBSCHQOS51 0xE6791084U -#define DBSC_DBSCHQOS52 0xE6791088U -#define DBSC_DBSCHQOS53 0xE679108CU -#define DBSC_DBSCHQOS60 0xE6791090U -#define DBSC_DBSCHQOS61 0xE6791094U -#define DBSC_DBSCHQOS62 0xE6791098U -#define DBSC_DBSCHQOS63 0xE679109CU -#define DBSC_DBSCHQOS70 0xE67910A0U -#define DBSC_DBSCHQOS71 0xE67910A4U -#define DBSC_DBSCHQOS72 0xE67910A8U -#define DBSC_DBSCHQOS73 0xE67910ACU -#define DBSC_DBSCHQOS80 0xE67910B0U -#define DBSC_DBSCHQOS81 0xE67910B4U -#define DBSC_DBSCHQOS82 0xE67910B8U -#define DBSC_DBSCHQOS83 0xE67910BCU -#define DBSC_DBSCHQOS90 0xE67910C0U -#define DBSC_DBSCHQOS91 0xE67910C4U -#define DBSC_DBSCHQOS92 0xE67910C8U -#define DBSC_DBSCHQOS93 0xE67910CCU -#define DBSC_DBSCHQOS100 0xE67910D0U -#define DBSC_DBSCHQOS101 0xE67910D4U -#define DBSC_DBSCHQOS102 0xE67910D8U -#define DBSC_DBSCHQOS103 0xE67910DCU -#define DBSC_DBSCHQOS110 0xE67910E0U -#define DBSC_DBSCHQOS111 0xE67910E4U -#define DBSC_DBSCHQOS112 0xE67910E8U -#define DBSC_DBSCHQOS113 0xE67910ECU -#define DBSC_DBSCHQOS120 0xE67910F0U -#define DBSC_DBSCHQOS121 0xE67910F4U -#define DBSC_DBSCHQOS122 0xE67910F8U -#define DBSC_DBSCHQOS123 0xE67910FCU -#define DBSC_DBSCHQOS130 0xE6791100U -#define DBSC_DBSCHQOS131 0xE6791104U -#define DBSC_DBSCHQOS132 0xE6791108U -#define DBSC_DBSCHQOS133 0xE679110CU -#define DBSC_DBSCHQOS140 0xE6791110U -#define DBSC_DBSCHQOS141 0xE6791114U -#define DBSC_DBSCHQOS142 0xE6791118U -#define DBSC_DBSCHQOS143 0xE679111CU -#define DBSC_DBSCHQOS150 0xE6791120U -#define DBSC_DBSCHQOS151 0xE6791124U -#define DBSC_DBSCHQOS152 0xE6791128U -#define DBSC_DBSCHQOS153 0xE679112CU -#define DBSC_SCFCTST0 0xE6791700U -#define DBSC_SCFCTST1 0xE6791708U -#define DBSC_SCFCTST2 0xE679170CU -#define DBSC_DBMRRDR0 0xE6791800U -#define DBSC_DBMRRDR1 0xE6791804U -#define DBSC_DBMRRDR2 0xE6791808U -#define DBSC_DBMRRDR3 0xE679180CU -#define DBSC_DBMRRDR4 0xE6791810U -#define DBSC_DBMRRDR5 0xE6791814U -#define DBSC_DBMRRDR6 0xE6791818U -#define DBSC_DBMRRDR7 0xE679181CU -#define DBSC_DBDTMP0 0xE6791820U -#define DBSC_DBDTMP1 0xE6791824U -#define DBSC_DBDTMP2 0xE6791828U -#define DBSC_DBDTMP3 0xE679182CU -#define DBSC_DBDTMP4 0xE6791830U -#define DBSC_DBDTMP5 0xE6791834U -#define DBSC_DBDTMP6 0xE6791838U -#define DBSC_DBDTMP7 0xE679183CU -#define DBSC_DBDQSOSC00 0xE6791840U -#define DBSC_DBDQSOSC01 0xE6791844U -#define DBSC_DBDQSOSC10 0xE6791848U -#define DBSC_DBDQSOSC11 0xE679184CU -#define DBSC_DBDQSOSC20 0xE6791850U -#define DBSC_DBDQSOSC21 0xE6791854U -#define DBSC_DBDQSOSC30 0xE6791858U -#define DBSC_DBDQSOSC31 0xE679185CU -#define DBSC_DBDQSOSC40 0xE6791860U -#define DBSC_DBDQSOSC41 0xE6791864U -#define DBSC_DBDQSOSC50 0xE6791868U -#define DBSC_DBDQSOSC51 0xE679186CU -#define DBSC_DBDQSOSC60 0xE6791870U -#define DBSC_DBDQSOSC61 0xE6791874U -#define DBSC_DBDQSOSC70 0xE6791878U -#define DBSC_DBDQSOSC71 0xE679187CU -#define DBSC_DBOSCTHH00 0xE6791880U -#define DBSC_DBOSCTHH01 0xE6791884U -#define DBSC_DBOSCTHH10 0xE6791888U -#define DBSC_DBOSCTHH11 0xE679188CU -#define DBSC_DBOSCTHH20 0xE6791890U -#define DBSC_DBOSCTHH21 0xE6791894U -#define DBSC_DBOSCTHH30 0xE6791898U -#define DBSC_DBOSCTHH31 0xE679189CU -#define DBSC_DBOSCTHH40 0xE67918A0U -#define DBSC_DBOSCTHH41 0xE67918A4U -#define DBSC_DBOSCTHH50 0xE67918A8U -#define DBSC_DBOSCTHH51 0xE67918ACU -#define DBSC_DBOSCTHH60 0xE67918B0U -#define DBSC_DBOSCTHH61 0xE67918B4U -#define DBSC_DBOSCTHH70 0xE67918B8U -#define DBSC_DBOSCTHH71 0xE67918BCU -#define DBSC_DBOSCTHL00 0xE67918C0U -#define DBSC_DBOSCTHL01 0xE67918C4U -#define DBSC_DBOSCTHL10 0xE67918C8U -#define DBSC_DBOSCTHL11 0xE67918CCU -#define DBSC_DBOSCTHL20 0xE67918D0U -#define DBSC_DBOSCTHL21 0xE67918D4U -#define DBSC_DBOSCTHL30 0xE67918D8U -#define DBSC_DBOSCTHL31 0xE67918DCU -#define DBSC_DBOSCTHL40 0xE67918E0U -#define DBSC_DBOSCTHL41 0xE67918E4U -#define DBSC_DBOSCTHL50 0xE67918E8U -#define DBSC_DBOSCTHL51 0xE67918ECU -#define DBSC_DBOSCTHL60 0xE67918F0U -#define DBSC_DBOSCTHL61 0xE67918F4U -#define DBSC_DBOSCTHL70 0xE67918F8U -#define DBSC_DBOSCTHL71 0xE67918FCU -#define DBSC_DBMEMSWAPCONF0 0xE6792000U - -/* CPG registers */ -#define CPG_SRCR4 0xE61500BCU -#define CPG_PLLECR 0xE61500D0U -#define CPG_CPGWPR 0xE6150900U -#define CPG_CPGWPCR 0xE6150904U -#define CPG_SRSTCLR4 0xE6150950U - -/* MODE Monitor registers */ -#define RST_MODEMR 0xE6160060U - -#endif /* BOOT_INIT_DRAM_REGDEF_H_*/ +#include "../ddr_regs.h" diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c index d03b1b965..a49510ed5 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c @@ -8,8 +8,8 @@ #include #include #include - -#include "boot_init_dram_regdef.h" +#include "rcar_def.h" +#include "../ddr_regs.h" #define RCAR_DDR_VERSION "rev.0.01" @@ -23,7 +23,7 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); mmio_write_32(DBSC_DBKIND, 0x00000007); - mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01); + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); mmio_write_32(DBSC_DBTR0, 0x0000000D); mmio_write_32(DBSC_DBTR1, 0x00000009); @@ -51,249 +51,249 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBODT0, 0x00000001); mmio_write_32(DBSC_DBADJ0, 0x00000001); mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); mmio_write_32(DBSC_SCFCTST0, 0x0D020D04); mmio_write_32(DBSC_SCFCTST1, 0x0306040C); - mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01000001); mmio_write_32(DBSC_DBCMD, 0x08000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058A04); - mmio_write_32(DBSC_DBPDRGA0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD0, 0x0A206F89); - mmio_write_32(DBSC_DBPDRGA0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000023); - mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77); - mmio_write_32(DBSC_DBPDRGA0, 0x00000024); - mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28); - mmio_write_32(DBSC_DBPDRGA0, 0x00000025); - mmio_write_32(DBSC_DBPDRGD0, 0x30005E00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000026); - mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49); - mmio_write_32(DBSC_DBPDRGA0, 0x00000027); - mmio_write_32(DBSC_DBPDRGD0, 0x00000F14); - mmio_write_32(DBSC_DBPDRGA0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - - mmio_write_32(DBSC_DBPDRGA0, 0x0000000E); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9; + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9; r3 = (r2 << 16) + (r2 << 8) + r2; r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; - mmio_write_32(DBSC_DBPDRGA0, 0x00000011); - mmio_write_32(DBSC_DBPDRGD0, r3); - mmio_write_32(DBSC_DBPDRGA0, 0x00000012); - mmio_write_32(DBSC_DBPDRGD0, r3); - mmio_write_32(DBSC_DBPDRGA0, 0x00000016); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000017); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000018); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000019); - mmio_write_32(DBSC_DBPDRGD0, r6); - - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000011); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000012); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000016); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000017); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000018); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000019); + mmio_write_32(DBSC_DBPDRGD_0, r6); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); mmio_write_32(DBSC_DBCMD, 0x08000001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r7); - - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + (r5 << 1)) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x0001F001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000AF); - r2 = mmio_read_32(DBSC_DBPDRGD0); - mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - mmio_write_32(DBSC_DBPDRGA0, 0x000000CF); - r2 = mmio_read_32(DBSC_DBPDRGD0); - mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8); - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; r12 = (r5 >> 0x2); if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); mmio_write_32(DBSC_DBCALCNF, 0x0100401B); @@ -302,7 +302,7 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); mmio_write_32(DBSC_DBRFEN, 0x00000001); mmio_write_32(DBSC_DBACEN, 0x00000001); - mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #ifdef ddr_qos_init_setting // only for non qos_init @@ -348,7 +348,7 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); mmio_write_32(DBSC_DBKIND, 0x00000007); - mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01); + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); mmio_write_32(DBSC_DBTR0, 0x0000000B); mmio_write_32(DBSC_DBTR1, 0x00000008); @@ -376,248 +376,248 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBODT0, 0x00000001); mmio_write_32(DBSC_DBADJ0, 0x00000001); mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); mmio_write_32(DBSC_SCFCTST0, 0x0D020C04); mmio_write_32(DBSC_SCFCTST1, 0x0305040C); - mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01000001); mmio_write_32(DBSC_DBCMD, 0x08000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058904); - mmio_write_32(DBSC_DBPDRGA0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD0, 0x08C05FF0); - mmio_write_32(DBSC_DBPDRGA0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000023); - mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); - mmio_write_32(DBSC_DBPDRGA0, 0x00000024); - mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400); - mmio_write_32(DBSC_DBPDRGA0, 0x00000025); - mmio_write_32(DBSC_DBPDRGD0, 0x30005200); - mmio_write_32(DBSC_DBPDRGA0, 0x00000026); - mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); - mmio_write_32(DBSC_DBPDRGA0, 0x00000027); - mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); - mmio_write_32(DBSC_DBPDRGA0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD0, 0x00000098); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000098); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - - mmio_write_32(DBSC_DBPDRGA0, 0x0000000E); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9; + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9; r3 = (r2 << 16) + (r2 << 8) + r2; r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; - mmio_write_32(DBSC_DBPDRGA0, 0x00000011); - mmio_write_32(DBSC_DBPDRGD0, r3); - mmio_write_32(DBSC_DBPDRGA0, 0x00000012); - mmio_write_32(DBSC_DBPDRGD0, r3); - mmio_write_32(DBSC_DBPDRGA0, 0x00000016); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000017); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000018); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000019); - mmio_write_32(DBSC_DBPDRGD0, r6); - - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000011); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000012); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000016); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000017); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000018); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000019); + mmio_write_32(DBSC_DBPDRGD_0, r6); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); mmio_write_32(DBSC_DBCMD, 0x08000001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r7); - - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + (r5 << 1)) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x0001F001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000AF); - r2 = mmio_read_32(DBSC_DBPDRGD0); - mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - mmio_write_32(DBSC_DBPDRGA0, 0x000000CF); - r2 = mmio_read_32(DBSC_DBPDRGD0); - mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; r12 = (r5 >> 0x2); if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); mmio_write_32(DBSC_DBCALCNF, 0x0100401B); @@ -626,7 +626,7 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); mmio_write_32(DBSC_DBRFEN, 0x00000001); mmio_write_32(DBSC_DBACEN, 0x00000001); - mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #ifdef ddr_qos_init_setting // only for non qos_init diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c index 7aedc88d6..fc278ef57 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c @@ -11,7 +11,8 @@ #include #include "boot_init_dram.h" -#include "boot_init_dram_regdef.h" +#include "rcar_def.h" +#include "../ddr_regs.h" #include "../dram_sub_func.h" @@ -78,9 +79,9 @@ uint32_t init_ddr(void) mmio_write_32(DBSC_DBKIND, 0x00000007); #if RCAR_DRAM_DDR3L_MEMCONF == 0 - mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); /* 1GB */ + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); /* 1GB */ #else - mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); /* 2GB(default) */ + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); /* 2GB(default) */ #endif #if RCAR_DRAM_DDR3L_MEMDUAL == 1 @@ -157,7 +158,7 @@ uint32_t init_ddr(void) mmio_write_32(DBSC_DBODT0, 0x00000001); mmio_write_32(DBSC_DBADJ0, 0x00000001); mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); @@ -173,231 +174,231 @@ uint32_t init_ddr(void) /* * Initial_Step0( INITBYP ) */ - mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01840001); mmio_write_32(DBSC_DBCMD, 0x08840000); NOTICE("BL2: [COLD_BOOT]\n"); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training ) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058904); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058A04); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04); - mmio_write_32(DBSC_DBPDRGA0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); - - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step2( DRAMRST/DRAMINT training ) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD0, 0x0780C720); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720); else - mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000004); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); /* Select setting value in bps */ if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) - + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) - + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) - 400 + 0x0A300000); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000023); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77); + mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); - mmio_write_32(DBSC_DBPDRGA0, 0x00000024); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); - mmio_write_32(DBSC_DBPDRGA0, 0x00000025); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x30005200); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x30005E00); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000026); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); - mmio_write_32(DBSC_DBPDRGA0, 0x00000027); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x00000F14); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); - mmio_write_32(DBSC_DBPDRGA0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA0, 0x00000029); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); /* Select setting value in bps */ if (ddr_md == 0) { /* 1584Mbps */ if (REFRESH_RATE > 3900) /* [7]SRT=0 */ - mmio_write_32(DBSC_DBPDRGD0, 0x18); + mmio_write_32(DBSC_DBPDRGD_0, 0x18); else /* [7]SRT=1 */ - mmio_write_32(DBSC_DBPDRGD0, 0x98); + mmio_write_32(DBSC_DBPDRGD_0, 0x98); } else { /* 1856Mbps */ if (REFRESH_RATE > 3900) /* [7]SRT=0 */ - mmio_write_32(DBSC_DBPDRGD0, 0x20); + mmio_write_32(DBSC_DBPDRGD_0, 0x20); else /* [7]SRT=1 */ - mmio_write_32(DBSC_DBPDRGD0, 0xA0); + mmio_write_32(DBSC_DBPDRGD_0, 0xA0); } - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000107); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000108); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000109); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); mmio_write_32(DBSC_DBCMD, 0x08840001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step3( WL/QSG training ) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r7); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + ((r5) << 1)) & 0xFF)); } @@ -406,191 +407,191 @@ uint32_t init_ddr(void) /* * Initial_Step4( WLADJ training ) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step5(Read Data Bit Deskew) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00011001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00011001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } /* * Initial_Step6(Write Data Bit Deskew) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00012001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00012001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step7(Read Data Eye Training) */ if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00014001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00014001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } /* * Initial_Step8(Write Data Eye Training) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00018001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00018001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step3_2( DQS Gate Training ) */ - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8); - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; r12 = (r5 >> 0x2); if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 + r5 + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); } } @@ -599,40 +600,40 @@ uint32_t init_ddr(void) * Initial_Step5-2_7-2( Rd bit Rd eye ) */ if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (lcdl_ctl == 1) { for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; bdlcount_0c_div2 = bdlcount_0c >> 1; bdlcount_0c_div4 = bdlcount_0c >> 2; @@ -657,43 +658,43 @@ uint32_t init_ddr(void) continue; if (dqsgd_0c <= lcdl_judge2) { - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGD_0, (dqsgd_0c - bdlcount_0c_div8) | regval); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGD0, regval | + mmio_write_32(DBSC_DBPDRGD_0, regval | (gatesl_0c + 1)); - mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD0)); + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); rdqsd_0c = (regval & 0xFF00) >> 8; rdqsnd_0c = (regval & 0xFF0000) >> 16; - mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, (regval & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)); - mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD0)); + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); rbd_0c[0] = (regval) & 0x1f; rbd_0c[1] = (regval >> 8) & 0x1f; rbd_0c[2] = (regval >> 16) & 0x1f; rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xE0E0E0E0; for (j = 0; j < 4; j++) { rbd_0c[j] = rbd_0c[j] + @@ -702,15 +703,15 @@ uint32_t init_ddr(void) rbd_0c[j] = 0x1F; regval = regval | (rbd_0c[j] << 8 * j); } - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD0)); + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); rbd_0c[0] = (regval) & 0x1f; rbd_0c[1] = (regval >> 8) & 0x1f; rbd_0c[2] = (regval >> 16) & 0x1f; rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xE0E0E0E0; for (j = 0; j < 4; j++) { rbd_0c[j] = rbd_0c[j] + @@ -719,25 +720,25 @@ uint32_t init_ddr(void) rbd_0c[j] = 0x1F; regval = regval | (rbd_0c[j] << 8 * j); } - mmio_write_32(DBSC_DBPDRGD0, regval); + mmio_write_32(DBSC_DBPDRGD_0, regval); } } - mmio_write_32(DBSC_DBPDRGA0, 0x2); - mmio_write_32(DBSC_DBPDRGD0, 0x7D81E37); + mmio_write_32(DBSC_DBPDRGA_0, 0x2); + mmio_write_32(DBSC_DBPDRGD_0, 0x7D81E37); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD0, 0x0380C720); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720); else - mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000); @@ -758,34 +759,34 @@ uint32_t init_ddr(void) if (pdqsr_ctl == 1) { mmio_write_32(0xE67F0018, 0x00000001); regval = mmio_read_32(0x40000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000000); - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } /* * Initial_Step9( Initial End ) */ - mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #ifdef ddr_qos_init_setting /* only for non qos_init */ @@ -881,9 +882,9 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) mmio_write_32(DBSC_DBKIND, 0x00000007); #if RCAR_DRAM_DDR3L_MEMCONF == 0 - mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); #else - mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); #endif #if RCAR_DRAM_DDR3L_MEMDUAL == 1 @@ -960,7 +961,7 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) mmio_write_32(DBSC_DBODT0, 0x00000001); mmio_write_32(DBSC_DBADJ0, 0x00000001); mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); @@ -976,143 +977,143 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) /* * recovery_Step1(PHY setting 1) */ - mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01840001); mmio_write_32(DBSC_DBCMD, 0x0A840000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000008); /* DDR_PLLCR */ - mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); /* DDR_PGCR1 */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); /* DDR_PLLCR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); /* DDR_PGCR1 */ if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD0, 0x0780C720); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720); else - mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); - - mmio_write_32(DBSC_DBPDRGA0, 0x00000020); /* DDR_DXCCR */ - mmio_write_32(DBSC_DBPDRGD0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); /* DDR_ACIOCR0 */ - mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); /* DDR_DXCCR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); /* DDR_ACIOCR0 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000004); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); /* Select setting value in bps */ if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) - + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) - + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) - 400 + 0x0A300000); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000023); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77); + mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); - mmio_write_32(DBSC_DBPDRGA0, 0x00000024); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); - mmio_write_32(DBSC_DBPDRGA0, 0x00000025); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x30005200); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x30005E00); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000026); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); - mmio_write_32(DBSC_DBPDRGA0, 0x00000027); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x00000F14); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); - mmio_write_32(DBSC_DBPDRGA0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA0, 0x00000029); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); /* Select setting value in bps */ if (ddr_md == 0) { /* 1584Mbps */ if (REFRESH_RATE > 3900) - mmio_write_32(DBSC_DBPDRGD0, 0x18); /* [7]SRT=0 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x18); /* [7]SRT=0 */ else - mmio_write_32(DBSC_DBPDRGD0, 0x98); /* [7]SRT=1 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x98); /* [7]SRT=1 */ } else { /* 1856Mbps */ if (REFRESH_RATE > 3900) - mmio_write_32(DBSC_DBPDRGD0, 0x20); /* [7]SRT=0 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x20); /* [7]SRT=0 */ else - mmio_write_32(DBSC_DBPDRGD0, 0xA0); /* [7]SRT=1 */ + mmio_write_32(DBSC_DBPDRGD_0, 0xA0); /* [7]SRT=1 */ } - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); /* DDR_DSGCR */ - mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); /* DDR_DSGCR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x40010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x40010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ - mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ - mmio_write_32(DBSC_DBPDRGD0, 0xC4285FBF); - mmio_write_32(DBSC_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ - mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000092); /* DDR_ZQ0DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000096); /* DDR_ZQ1DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0xC4285FBF); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A); /* DDR_ZQ2DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x00050001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00050001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* ddr backupmode end */ @@ -1127,87 +1128,87 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) return INITDRAM_ERR_I; } - mmio_write_32(DBSC_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ - mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ - mmio_write_32(DBSC_DBPDRGD0, 0x04285FBF); - mmio_write_32(DBSC_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ - mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000092); /* DDR_ZQ0DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000096); /* DDR_ZQ1DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04285FBF); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A); /* DDR_ZQ2DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x08000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x08000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x00000003); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00000003); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x0000000C); - mmio_write_32(DBSC_DBPDRGD0, 0x18000040); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000000C); + mmio_write_32(DBSC_DBPDRGD_0, 0x18000040); /* * recovery_Step2(PHY setting 2) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000107); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000108); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000109); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); @@ -1233,258 +1234,258 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) while (mmio_read_32(DBSC_DBWAIT) & BIT(0)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x00010701); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00010701); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r7); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + (r5 << 1)) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00011001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00011001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00012001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00012001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00014001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00014001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00018001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00018001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8); - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; r12 = r5 >> 0x2; if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); } } if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (lcdl_ctl == 1) { for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20); - dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x000000FF; - mmio_write_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20); - bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0x000000B0 + i * 0x20); + dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x000000FF; + mmio_write_32(DBSC_DBPDRGA_0, 0x000000B1 + i * 0x20); + bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 8; bdlcount_0c_div2 = (bdlcount_0c >> 1); bdlcount_0c_div4 = (bdlcount_0c >> 2); @@ -1509,43 +1510,43 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) continue; if (dqsgd_0c <= lcdl_judge2) { - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGD_0, (dqsgd_0c - bdlcount_0c_div8) | regval); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGD_0, regval | (gatesl_0c + 1)); - mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0); + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0); rdqsd_0c = (regval & 0xFF00) >> 8; rdqsnd_0c = (regval & 0xFF0000) >> 16; - mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, (regval & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)); - mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD0)); + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); rbd_0c[0] = (regval) & 0x1f; rbd_0c[1] = (regval >> 8) & 0x1f; rbd_0c[2] = (regval >> 16) & 0x1f; rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xE0E0E0E0; for (j = 0; j < 4; j++) { rbd_0c[j] = rbd_0c[j] + @@ -1554,15 +1555,15 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) rbd_0c[j] = 0x1F; regval = regval | (rbd_0c[j] << 8 * j); } - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD0)); + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); rbd_0c[0] = regval & 0x1f; rbd_0c[1] = (regval >> 8) & 0x1f; rbd_0c[2] = (regval >> 16) & 0x1f; rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xE0E0E0E0; for (j = 0; j < 4; j++) { rbd_0c[j] = rbd_0c[j] + @@ -1571,24 +1572,24 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) rbd_0c[j] = 0x1F; regval = regval | (rbd_0c[j] << 8 * j); } - mmio_write_32(DBSC_DBPDRGD0, regval); + mmio_write_32(DBSC_DBPDRGD_0, regval); } } - mmio_write_32(DBSC_DBPDRGA0, 0x00000002); - mmio_write_32(DBSC_DBPDRGD0, 0x07D81E37); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000002); + mmio_write_32(DBSC_DBPDRGD_0, 0x07D81E37); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD0, 0x0380C720); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720); else - mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); /* * recovery_Step3(DBSC Setting 2) @@ -1599,31 +1600,31 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) if (pdqsr_ctl == 1) { mmio_write_32(0xE67F0018, 0x00000001); regval = mmio_read_32(0x40000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000000); - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } - mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #ifdef ddr_qos_init_setting /* only for non qos_init */ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c index 00e1903ce..5410771c9 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c @@ -9,7 +9,8 @@ #include #include #include "boot_init_dram.h" -#include "boot_init_dram_regdef.h" +#include "rcar_def.h" +#include "../ddr_regs.h" static uint32_t init_ddr_v3m_1600(void) { @@ -18,9 +19,9 @@ static uint32_t init_ddr_v3m_1600(void) mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); mmio_write_32(DBSC_DBKIND, 0x00000007); #if RCAR_DRAM_DDR3L_MEMCONF == 0 - mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); // 1GB: Eagle + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); // 1GB: Eagle #else - mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); // 2GB: V3MSK + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); // 2GB: V3MSK #endif mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); mmio_write_32(DBSC_DBTR0, 0x0000000B); @@ -79,243 +80,243 @@ static uint32_t init_ddr_v3m_1600(void) mmio_write_32(DBSC_DBCAM0CNF2, 0x000001c4); mmio_write_32(DBSC_DBSCHSZ0, 0x00000003); mmio_write_32(DBSC_DBSCHRW1, 0x001a0080); - mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); - mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01000001); mmio_write_32(DBSC_DBCMD, 0x08000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058904); - mmio_write_32(DBSC_DBPDRGA0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD0, 0x08C0C170); - mmio_write_32(DBSC_DBPDRGA0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000023); - mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); - mmio_write_32(DBSC_DBPDRGA0, 0x00000024); - mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400); - mmio_write_32(DBSC_DBPDRGA0, 0x00000025); - mmio_write_32(DBSC_DBPDRGD0, 0x30005200); - mmio_write_32(DBSC_DBPDRGA0, 0x00000026); - mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); - mmio_write_32(DBSC_DBPDRGA0, 0x00000027); - mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); - mmio_write_32(DBSC_DBPDRGA0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD0, 0x00000004); - mmio_write_32(DBSC_DBPDRGA0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD0, 0x00000018); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD0, 0x13C03C10); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD_0, 0x08C0C170); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000018); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x13C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000107); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000108); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000109); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); mmio_write_32(DBSC_DBCMD, 0x08000001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r7); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (((r5 << 1) + r6) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00A0); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00A0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00B8); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x0001F001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00B8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF); + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF); - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = (mmio_read_32(DBSC_DBPDRGD0) & 0x7); + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x7); r12 = (r5 >> 2); if (r6 - r12 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, ((r6 - r12) & 0xFF) | r2); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, ((r6 - r12) & 0xFF) | r2); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, (r7 & 0x7) | r2); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, (r7 & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000000); mmio_write_32(DBSC_DBBUS0CNF0, 0x00010001); @@ -325,7 +326,7 @@ static uint32_t init_ddr_v3m_1600(void) mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); mmio_write_32(DBSC_DBRFEN, 0x00000001); mmio_write_32(DBSC_DBACEN, 0x00000001); - mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); mmio_write_32(0xE67F0024, 0x00000001); mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h index abddf0cf2..0bc2bc160 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h @@ -32,7 +32,6 @@ #define DBSC_REFINTS (0x0) /* system registers */ -#define CPG_BASE (0xE6150000U) #define CPG_FRQCRB (CPG_BASE + 0x0004U) #define CPG_PLLECR (CPG_BASE + 0x00D0U) @@ -56,179 +55,7 @@ #define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x)) /* DBSC registers */ -#define DBSC_DBSYSCONF1 0xE6790004U -#define DBSC_DBPHYCONF0 0xE6790010U -#define DBSC_DBKIND 0xE6790020U - -#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) -#define DBSC_DBMEMCONF_0_0 0xE6790030U -#define DBSC_DBMEMCONF_0_1 0xE6790034U -#define DBSC_DBMEMCONF_0_2 0xE6790038U -#define DBSC_DBMEMCONF_0_3 0xE679003CU -#define DBSC_DBMEMCONF_1_2 0xE6790048U -#define DBSC_DBMEMCONF_1_3 0xE679004CU -#define DBSC_DBMEMCONF_1_0 0xE6790040U -#define DBSC_DBMEMCONF_1_1 0xE6790044U -#define DBSC_DBMEMCONF_2_0 0xE6790050U -#define DBSC_DBMEMCONF_2_1 0xE6790054U -#define DBSC_DBMEMCONF_2_2 0xE6790058U -#define DBSC_DBMEMCONF_2_3 0xE679005CU -#define DBSC_DBMEMCONF_3_0 0xE6790060U -#define DBSC_DBMEMCONF_3_1 0xE6790064U -#define DBSC_DBMEMCONF_3_2 0xE6790068U -#define DBSC_DBMEMCONF_3_3 0xE679006CU - -#define DBSC_DBSYSCNT0 0xE6790100U - -#define DBSC_DBACEN 0xE6790200U -#define DBSC_DBRFEN 0xE6790204U -#define DBSC_DBCMD 0xE6790208U -#define DBSC_DBWAIT 0xE6790210U -#define DBSC_DBSYSCTRL0 0xE6790280U - -#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x)) -#define DBSC_DBTR0 0xE6790300U -#define DBSC_DBTR1 0xE6790304U -#define DBSC_DBTR3 0xE679030CU -#define DBSC_DBTR4 0xE6790310U -#define DBSC_DBTR5 0xE6790314U -#define DBSC_DBTR6 0xE6790318U -#define DBSC_DBTR7 0xE679031CU -#define DBSC_DBTR8 0xE6790320U -#define DBSC_DBTR9 0xE6790324U -#define DBSC_DBTR10 0xE6790328U -#define DBSC_DBTR11 0xE679032CU -#define DBSC_DBTR12 0xE6790330U -#define DBSC_DBTR13 0xE6790334U -#define DBSC_DBTR14 0xE6790338U -#define DBSC_DBTR15 0xE679033CU -#define DBSC_DBTR16 0xE6790340U -#define DBSC_DBTR17 0xE6790344U -#define DBSC_DBTR18 0xE6790348U -#define DBSC_DBTR19 0xE679034CU -#define DBSC_DBTR20 0xE6790350U -#define DBSC_DBTR21 0xE6790354U -#define DBSC_DBTR22 0xE6790358U -#define DBSC_DBTR23 0xE679035CU -#define DBSC_DBTR24 0xE6790360U -#define DBSC_DBTR25 0xE6790364U -#define DBSC_DBTR26 0xE6790368U - -#define DBSC_DBBL 0xE6790400U -#define DBSC_DBRFCNF1 0xE6790414U -#define DBSC_DBRFCNF2 0xE6790418U -#define DBSC_DBTSPCNF 0xE6790420U -#define DBSC_DBCALCNF 0xE6790424U -#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x)) -#define DBSC_DBRNK2 0xE6790438U -#define DBSC_DBRNK3 0xE679043CU -#define DBSC_DBRNK4 0xE6790440U -#define DBSC_DBRNK5 0xE6790444U -#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x)) - -#define DBSC_DBADJ0 0xE6790500U -#define DBSC_DBDBICNT 0xE6790518U -#define DBSC_DBDFIPMSTRCNF 0xE6790520U -#define DBSC_DBDFICUPDCNF 0xE679052CU - -#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch)) -#define DBSC_DBDFISTAT_0 0xE6790600U -#define DBSC_DBDFISTAT_1 0xE6790640U -#define DBSC_DBDFISTAT_2 0xE6790680U -#define DBSC_DBDFISTAT_3 0xE67906C0U - -#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch)) -#define DBSC_DBDFICNT_0 0xE6790604U -#define DBSC_DBDFICNT_1 0xE6790644U -#define DBSC_DBDFICNT_2 0xE6790684U -#define DBSC_DBDFICNT_3 0xE67906C4U - -#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch)) -#define DBSC_DBPDCNT0_0 0xE6790610U -#define DBSC_DBPDCNT0_1 0xE6790650U -#define DBSC_DBPDCNT0_2 0xE6790690U -#define DBSC_DBPDCNT0_3 0xE67906D0U - -#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch)) -#define DBSC_DBPDCNT1_0 0xE6790614U -#define DBSC_DBPDCNT1_1 0xE6790654U -#define DBSC_DBPDCNT1_2 0xE6790694U -#define DBSC_DBPDCNT1_3 0xE67906D4U - -#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch)) -#define DBSC_DBPDCNT2_0 0xE6790618U -#define DBSC_DBPDCNT2_1 0xE6790658U -#define DBSC_DBPDCNT2_2 0xE6790698U -#define DBSC_DBPDCNT2_3 0xE67906D8U - -#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch)) -#define DBSC_DBPDCNT3_0 0xE679061CU -#define DBSC_DBPDCNT3_1 0xE679065CU -#define DBSC_DBPDCNT3_2 0xE679069CU -#define DBSC_DBPDCNT3_3 0xE67906DCU - -#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch)) -#define DBSC_DBPDLK_0 0xE6790620U -#define DBSC_DBPDLK_1 0xE6790660U -#define DBSC_DBPDLK_2 0xE67906a0U -#define DBSC_DBPDLK_3 0xE67906e0U - -#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch)) -#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch)) -#define DBSC_DBPDRGA_0 0xE6790624U -#define DBSC_DBPDRGD_0 0xE6790628U -#define DBSC_DBPDRGA_1 0xE6790664U -#define DBSC_DBPDRGD_1 0xE6790668U -#define DBSC_DBPDRGA_2 0xE67906A4U -#define DBSC_DBPDRGD_2 0xE67906A8U -#define DBSC_DBPDRGA_3 0xE67906E4U -#define DBSC_DBPDRGD_3 0xE67906E8U - -#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch)) -#define DBSC_DBPDSTAT_0 0xE6790630U -#define DBSC_DBPDSTAT_1 0xE6790670U -#define DBSC_DBPDSTAT_2 0xE67906B0U -#define DBSC_DBPDSTAT_3 0xE67906F0U - -#define DBSC_DBBUS0CNF0 0xE6790800U -#define DBSC_DBBUS0CNF1 0xE6790804U - -#define DBSC_DBCAM0CNF1 0xE6790904U -#define DBSC_DBCAM0CNF2 0xE6790908U -#define DBSC_DBCAM0CNF3 0xE679090CU -#define DBSC_DBBSWAP 0xE67909F0U -#define DBSC_DBBCAMDIS 0xE67909FCU -#define DBSC_DBSCHCNT0 0xE6791000U -#define DBSC_DBSCHCNT1 0xE6791004U -#define DBSC_DBSCHSZ0 0xE6791010U -#define DBSC_DBSCHRW0 0xE6791020U -#define DBSC_DBSCHRW1 0xE6791024U - -#define DBSC_DBSCHQOS_0(x) (0xE6791030U +0x10U * (x)) -#define DBSC_DBSCHQOS_1(x) (0xE6791034U +0x10U * (x)) -#define DBSC_DBSCHQOS_2(x) (0xE6791038U +0x10U * (x)) -#define DBSC_DBSCHQOS_3(x) (0xE679103CU +0x10U * (x)) - -#define DBSC_DBSCTR0 0xE6791700U -#define DBSC_DBSCTR1 0xE6791708U -#define DBSC_DBSCHRW2 0xE679170CU - -#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x)) -#define DBSC_SCFCTST0 0xE6791700U -#define DBSC_SCFCTST1 0xE6791708U -#define DBSC_SCFCTST2 0xE679170CU - -#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab)) -#define DBSC_DBMRRDR_0 0xE6791800U -#define DBSC_DBMRRDR_1 0xE6791804U -#define DBSC_DBMRRDR_2 0xE6791808U -#define DBSC_DBMRRDR_3 0xE679180CU -#define DBSC_DBMRRDR_4 0xE6791810U -#define DBSC_DBMRRDR_5 0xE6791814U -#define DBSC_DBMRRDR_6 0xE6791818U -#define DBSC_DBMRRDR_7 0xE679181CU - -#define DBSC_DBMEMSWAPCONF0 0xE6792000U +#include "../ddr_regs.h" #define DBSC_DBMONCONF4 0xE6793010U @@ -264,33 +91,3 @@ /* other module */ #define THS1_THCTR 0xE6198020U #define THS1_TEMP 0xE6198028U - -#define DBSC_BASE (0xE6790000U) -#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U) -#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U) -#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U) -#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU) -#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U) -#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U) -#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U) -#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU) -#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U) -#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U) -#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U) -#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU) -#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U) -#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U) -#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U) -#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU) -#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U) -#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U) -#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U) -#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU) -#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U) -#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U) -#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U) -#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU) -#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U) -#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U) -#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U) -#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_regs.h b/drivers/staging/renesas/rcar/ddr/ddr_regs.h new file mode 100644 index 000000000..ba26c69c8 --- /dev/null +++ b/drivers/staging/renesas/rcar/ddr/ddr_regs.h @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOOT_INIT_DRAM_REGDEF_H_ +#define BOOT_INIT_DRAM_REGDEF_H_ + +/* DBSC registers */ +#define DBSC_DBSYSCONF0 0xE6790000U +#define DBSC_DBSYSCONF1 0xE6790004U +#define DBSC_DBPHYCONF0 0xE6790010U +#define DBSC_DBKIND 0xE6790020U +#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) +#define DBSC_DBMEMCONF_0_0 0xE6790030U +#define DBSC_DBMEMCONF_0_1 0xE6790034U +#define DBSC_DBMEMCONF_0_2 0xE6790038U +#define DBSC_DBMEMCONF_0_3 0xE679003CU +#define DBSC_DBMEMCONF_1_2 0xE6790048U +#define DBSC_DBMEMCONF_1_3 0xE679004CU +#define DBSC_DBMEMCONF_1_0 0xE6790040U +#define DBSC_DBMEMCONF_1_1 0xE6790044U +#define DBSC_DBMEMCONF_2_0 0xE6790050U +#define DBSC_DBMEMCONF_2_1 0xE6790054U +#define DBSC_DBMEMCONF_2_2 0xE6790058U +#define DBSC_DBMEMCONF_2_3 0xE679005CU +#define DBSC_DBMEMCONF_3_0 0xE6790060U +#define DBSC_DBMEMCONF_3_1 0xE6790064U +#define DBSC_DBMEMCONF_3_2 0xE6790068U +#define DBSC_DBMEMCONF_3_3 0xE679006CU +#define DBSC_DBSYSCNT0 0xE6790100U +#define DBSC_DBSVCR1 0xE6790104U +#define DBSC_DBSTATE0 0xE6790108U +#define DBSC_DBSTATE1 0xE679010CU +#define DBSC_DBINTEN 0xE6790180U +#define DBSC_DBINTSTAT0 0xE6790184U +#define DBSC_DBACEN 0xE6790200U +#define DBSC_DBRFEN 0xE6790204U +#define DBSC_DBCMD 0xE6790208U +#define DBSC_DBWAIT 0xE6790210U +#define DBSC_DBSYSCTRL0 0xE6790280U +#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x)) +#define DBSC_DBTR0 0xE6790300U +#define DBSC_DBTR1 0xE6790304U +#define DBSC_DBTR2 0xE6790308U +#define DBSC_DBTR3 0xE679030CU +#define DBSC_DBTR4 0xE6790310U +#define DBSC_DBTR5 0xE6790314U +#define DBSC_DBTR6 0xE6790318U +#define DBSC_DBTR7 0xE679031CU +#define DBSC_DBTR8 0xE6790320U +#define DBSC_DBTR9 0xE6790324U +#define DBSC_DBTR10 0xE6790328U +#define DBSC_DBTR11 0xE679032CU +#define DBSC_DBTR12 0xE6790330U +#define DBSC_DBTR13 0xE6790334U +#define DBSC_DBTR14 0xE6790338U +#define DBSC_DBTR15 0xE679033CU +#define DBSC_DBTR16 0xE6790340U +#define DBSC_DBTR17 0xE6790344U +#define DBSC_DBTR18 0xE6790348U +#define DBSC_DBTR19 0xE679034CU +#define DBSC_DBTR20 0xE6790350U +#define DBSC_DBTR21 0xE6790354U +#define DBSC_DBTR22 0xE6790358U +#define DBSC_DBTR23 0xE679035CU +#define DBSC_DBTR24 0xE6790360U +#define DBSC_DBTR25 0xE6790364U +#define DBSC_DBTR26 0xE6790368U +#define DBSC_DBBL 0xE6790400U +#define DBSC_DBRFCNF1 0xE6790414U +#define DBSC_DBRFCNF2 0xE6790418U +#define DBSC_DBTSPCNF 0xE6790420U +#define DBSC_DBCALCNF 0xE6790424U +#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x)) +#define DBSC_DBRNK2 0xE6790438U +#define DBSC_DBRNK3 0xE679043CU +#define DBSC_DBRNK4 0xE6790440U +#define DBSC_DBRNK5 0xE6790444U +#define DBSC_DBPDNCNF 0xE6790450U +#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x)) +#define DBSC_DBODT0 0xE6790460U +#define DBSC_DBODT1 0xE6790464U +#define DBSC_DBODT2 0xE6790468U +#define DBSC_DBODT3 0xE679046CU +#define DBSC_DBODT4 0xE6790470U +#define DBSC_DBODT5 0xE6790474U +#define DBSC_DBODT6 0xE6790478U +#define DBSC_DBODT7 0xE679047CU +#define DBSC_DBADJ0 0xE6790500U +#define DBSC_DBDBICNT 0xE6790518U +#define DBSC_DBDFIPMSTRCNF 0xE6790520U +#define DBSC_DBDFICUPDCNF 0xE679052CU +#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch)) +#define DBSC_DBDFISTAT_0 0xE6790600U +#define DBSC_DBDFISTAT_1 0xE6790640U +#define DBSC_DBDFISTAT_2 0xE6790680U +#define DBSC_DBDFISTAT_3 0xE67906C0U +#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch)) +#define DBSC_DBDFICNT_0 0xE6790604U +#define DBSC_DBDFICNT_1 0xE6790644U +#define DBSC_DBDFICNT_2 0xE6790684U +#define DBSC_DBDFICNT_3 0xE67906C4U +#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch)) +#define DBSC_DBPDCNT0_0 0xE6790610U +#define DBSC_DBPDCNT0_1 0xE6790650U +#define DBSC_DBPDCNT0_2 0xE6790690U +#define DBSC_DBPDCNT0_3 0xE67906D0U +#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch)) +#define DBSC_DBPDCNT1_0 0xE6790614U +#define DBSC_DBPDCNT1_1 0xE6790654U +#define DBSC_DBPDCNT1_2 0xE6790694U +#define DBSC_DBPDCNT1_3 0xE67906D4U +#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch)) +#define DBSC_DBPDCNT2_0 0xE6790618U +#define DBSC_DBPDCNT2_1 0xE6790658U +#define DBSC_DBPDCNT2_2 0xE6790698U +#define DBSC_DBPDCNT2_3 0xE67906D8U +#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch)) +#define DBSC_DBPDCNT3_0 0xE679061CU +#define DBSC_DBPDCNT3_1 0xE679065CU +#define DBSC_DBPDCNT3_2 0xE679069CU +#define DBSC_DBPDCNT3_3 0xE67906DCU +#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch)) +#define DBSC_DBPDLK_0 0xE6790620U +#define DBSC_DBPDLK_1 0xE6790660U +#define DBSC_DBPDLK_2 0xE67906a0U +#define DBSC_DBPDLK_3 0xE67906e0U +#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch)) +#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch)) +#define DBSC_DBPDRGA_0 0xE6790624U +#define DBSC_DBPDRGD_0 0xE6790628U +#define DBSC_DBPDRGA_1 0xE6790664U +#define DBSC_DBPDRGD_1 0xE6790668U +#define DBSC_DBPDRGA_2 0xE67906A4U +#define DBSC_DBPDRGD_2 0xE67906A8U +#define DBSC_DBPDRGA_3 0xE67906E4U +#define DBSC_DBPDRGD_3 0xE67906E8U +#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch)) +#define DBSC_DBPDSTAT_0 0xE6790630U +#define DBSC_DBPDSTAT_1 0xE6790670U +#define DBSC_DBPDSTAT_2 0xE67906B0U +#define DBSC_DBPDSTAT_3 0xE67906F0U +#define DBSC_DBBUS0CNF0 0xE6790800U +#define DBSC_DBBUS0CNF1 0xE6790804U +#define DBSC_DBCAM0CNF1 0xE6790904U +#define DBSC_DBCAM0CNF2 0xE6790908U +#define DBSC_DBCAM0CNF3 0xE679090CU +#define DBSC_DBBSWAP 0xE67909F0U +#define DBSC_DBBCAMDIS 0xE67909FCU +#define DBSC_DBSCHCNT0 0xE6791000U +#define DBSC_DBSCHCNT1 0xE6791004U +#define DBSC_DBSCHSZ0 0xE6791010U +#define DBSC_DBSCHRW0 0xE6791020U +#define DBSC_DBSCHRW1 0xE6791024U +#define DBSC_DBSCHQOS_0(x) (0xE6791030U + 0x10U * (x)) +#define DBSC_DBSCHQOS_1(x) (0xE6791034U + 0x10U * (x)) +#define DBSC_DBSCHQOS_2(x) (0xE6791038U + 0x10U * (x)) +#define DBSC_DBSCHQOS_3(x) (0xE679103CU + 0x10U * (x)) +#define DBSC_DBSCHQOS00 0xE6791030U +#define DBSC_DBSCHQOS01 0xE6791034U +#define DBSC_DBSCHQOS02 0xE6791038U +#define DBSC_DBSCHQOS03 0xE679103CU +#define DBSC_DBSCHQOS10 0xE6791040U +#define DBSC_DBSCHQOS11 0xE6791044U +#define DBSC_DBSCHQOS12 0xE6791048U +#define DBSC_DBSCHQOS13 0xE679104CU +#define DBSC_DBSCHQOS20 0xE6791050U +#define DBSC_DBSCHQOS21 0xE6791054U +#define DBSC_DBSCHQOS22 0xE6791058U +#define DBSC_DBSCHQOS23 0xE679105CU +#define DBSC_DBSCHQOS30 0xE6791060U +#define DBSC_DBSCHQOS31 0xE6791064U +#define DBSC_DBSCHQOS32 0xE6791068U +#define DBSC_DBSCHQOS33 0xE679106CU +#define DBSC_DBSCHQOS40 0xE6791070U +#define DBSC_DBSCHQOS41 0xE6791074U +#define DBSC_DBSCHQOS42 0xE6791078U +#define DBSC_DBSCHQOS43 0xE679107CU +#define DBSC_DBSCHQOS50 0xE6791080U +#define DBSC_DBSCHQOS51 0xE6791084U +#define DBSC_DBSCHQOS52 0xE6791088U +#define DBSC_DBSCHQOS53 0xE679108CU +#define DBSC_DBSCHQOS60 0xE6791090U +#define DBSC_DBSCHQOS61 0xE6791094U +#define DBSC_DBSCHQOS62 0xE6791098U +#define DBSC_DBSCHQOS63 0xE679109CU +#define DBSC_DBSCHQOS70 0xE67910A0U +#define DBSC_DBSCHQOS71 0xE67910A4U +#define DBSC_DBSCHQOS72 0xE67910A8U +#define DBSC_DBSCHQOS73 0xE67910ACU +#define DBSC_DBSCHQOS80 0xE67910B0U +#define DBSC_DBSCHQOS81 0xE67910B4U +#define DBSC_DBSCHQOS82 0xE67910B8U +#define DBSC_DBSCHQOS83 0xE67910BCU +#define DBSC_DBSCHQOS90 0xE67910C0U +#define DBSC_DBSCHQOS91 0xE67910C4U +#define DBSC_DBSCHQOS92 0xE67910C8U +#define DBSC_DBSCHQOS93 0xE67910CCU +#define DBSC_DBSCHQOS100 0xE67910D0U +#define DBSC_DBSCHQOS101 0xE67910D4U +#define DBSC_DBSCHQOS102 0xE67910D8U +#define DBSC_DBSCHQOS103 0xE67910DCU +#define DBSC_DBSCHQOS110 0xE67910E0U +#define DBSC_DBSCHQOS111 0xE67910E4U +#define DBSC_DBSCHQOS112 0xE67910E8U +#define DBSC_DBSCHQOS113 0xE67910ECU +#define DBSC_DBSCHQOS120 0xE67910F0U +#define DBSC_DBSCHQOS121 0xE67910F4U +#define DBSC_DBSCHQOS122 0xE67910F8U +#define DBSC_DBSCHQOS123 0xE67910FCU +#define DBSC_DBSCHQOS130 0xE6791100U +#define DBSC_DBSCHQOS131 0xE6791104U +#define DBSC_DBSCHQOS132 0xE6791108U +#define DBSC_DBSCHQOS133 0xE679110CU +#define DBSC_DBSCHQOS140 0xE6791110U +#define DBSC_DBSCHQOS141 0xE6791114U +#define DBSC_DBSCHQOS142 0xE6791118U +#define DBSC_DBSCHQOS143 0xE679111CU +#define DBSC_DBSCHQOS150 0xE6791120U +#define DBSC_DBSCHQOS151 0xE6791124U +#define DBSC_DBSCHQOS152 0xE6791128U +#define DBSC_DBSCHQOS153 0xE679112CU +#define DBSC_DBSCTR0 0xE6791700U +#define DBSC_DBSCTR1 0xE6791708U +#define DBSC_DBSCHRW2 0xE679170CU +#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x)) +#define DBSC_SCFCTST0 0xE6791700U +#define DBSC_SCFCTST1 0xE6791708U +#define DBSC_SCFCTST2 0xE679170CU +#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab)) +#define DBSC_DBMRRDR_0 0xE6791800U +#define DBSC_DBMRRDR_1 0xE6791804U +#define DBSC_DBMRRDR_2 0xE6791808U +#define DBSC_DBMRRDR_3 0xE679180CU +#define DBSC_DBMRRDR_4 0xE6791810U +#define DBSC_DBMRRDR_5 0xE6791814U +#define DBSC_DBMRRDR_6 0xE6791818U +#define DBSC_DBMRRDR_7 0xE679181CU +#define DBSC_DBMEMSWAPCONF0 0xE6792000U + +/* CPG registers */ +#define CPG_BASE 0xE6150000U +#define CPG_FRQCRB (CPG_BASE + 0x0004U) +#define CPG_PLLECR (CPG_BASE + 0x00D0U) +#define CPG_MSTPSR5 (CPG_BASE + 0x003CU) +#define CPG_SRCR4 (CPG_BASE + 0x00BCU) +#define CPG_PLL3CR (CPG_BASE + 0x00DCU) +#define CPG_ZB3CKCR (CPG_BASE + 0x0380U) +#define CPG_FRQCRD (CPG_BASE + 0x00E4U) +#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) +#define CPG_CPGWPR (CPG_BASE + 0x0900U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U) + +#endif /* BOOT_INIT_DRAM_REGDEF_H_*/ diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h index e2dae9bc9..0ffbfe979 100644 --- a/plat/renesas/rcar/include/rcar_def.h +++ b/plat/renesas/rcar/include/rcar_def.h @@ -221,9 +221,11 @@ #define CPG_PLL0CR (CPG_BASE + 0x00D8U) #define CPG_PLL2CR (CPG_BASE + 0x002CU) #define CPG_PLL4CR (CPG_BASE + 0x01F4U) +#define CPG_CPGWPCR (CPG_BASE + 0x0904U) /* RST Registers */ #define RST_BASE (0xE6160000U) #define RST_WDTRSTCR (RST_BASE + 0x0054U) +#define RST_MODEMR (RST_BASE + 0x0060U) #define WDTRSTCR_PASSWORD (0xA55A0000U) #define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U) /* MFIS Registers */ -- cgit v1.2.3 From a8497fdb72a904162fce823af6555ccb12dbce82 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 7 Aug 2019 19:02:26 +0200 Subject: rcar_get3: drivers: ddr_b: Basic checkpatch fixes Do basic automated checkpatch fixes on the ddr_b, no functional change. Signed-off-by: Marek Vasut Change-Id: Ie401ec049a05d2c4c8044749994391adea171679 --- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 169 ++++---- .../renesas/rcar/ddr/ddr_b/boot_init_dram_config.c | 450 ++++++++++----------- .../staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h | 8 +- 3 files changed, 318 insertions(+), 309 deletions(-) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index 2cce65339..c8e9ae802 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -45,30 +45,30 @@ #ifndef RCAR_LSI #define RCAR_LSI RCAR_AUTO #endif -#if(RCAR_LSI==RCAR_AUTO) +#if (RCAR_LSI == RCAR_AUTO) static uint32_t Prr_Product; static uint32_t Prr_Cut; #else -#if(RCAR_LSI==RCAR_H3) +#if (RCAR_LSI == RCAR_H3) static const uint32_t Prr_Product = PRR_PRODUCT_H3; -#elif(RCAR_LSI==RCAR_M3) +#elif(RCAR_LSI == RCAR_M3) static const uint32_t Prr_Product = PRR_PRODUCT_M3; -#elif(RCAR_LSI==RCAR_M3N) +#elif(RCAR_LSI == RCAR_M3N) static const uint32_t Prr_Product = PRR_PRODUCT_M3N; -#elif(RCAR_LSI==RCAR_H3N) +#elif(RCAR_LSI == RCAR_H3N) static const uint32_t Prr_Product = PRR_PRODUCT_H3; #endif /* RCAR_LSI */ #ifndef RCAR_LSI_CUT static uint32_t Prr_Cut; #else /* RCAR_LSI_CUT */ -#if(RCAR_LSI_CUT==RCAR_CUT_10) +#if (RCAR_LSI_CUT == RCAR_CUT_10) static const uint32_t Prr_Cut = PRR_PRODUCT_10; -#elif(RCAR_LSI_CUT==RCAR_CUT_11) +#elif(RCAR_LSI_CUT == RCAR_CUT_11) static const uint32_t Prr_Cut = PRR_PRODUCT_11; -#elif(RCAR_LSI_CUT==RCAR_CUT_20) +#elif(RCAR_LSI_CUT == RCAR_CUT_20) static const uint32_t Prr_Cut = PRR_PRODUCT_20; -#elif(RCAR_LSI_CUT==RCAR_CUT_30) +#elif(RCAR_LSI_CUT == RCAR_CUT_30) static const uint32_t Prr_Cut = PRR_PRODUCT_30; #endif /* RCAR_LSI_CUT */ #endif /* RCAR_LSI_CUT */ @@ -130,7 +130,7 @@ uint32_t ddrBackup; #define OPERATING_FREQ (400U) /* Mhz */ #define BASE_SUB_SLOT_NUM (0x6U) #define SUB_SLOT_CYCLE (0x7EU) /* 126 */ -#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ +#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) /* unit:ns */ uint32_t get_refperiod(void) { @@ -249,21 +249,21 @@ static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); static void ddr_setval_ach(uint32_t regdef, uint32_t val); static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); -static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p); -static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p); -static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size); -static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val); -static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef); +static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p); +static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p); +static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size); +static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); +static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); static uint32_t ddrphy_regif_chk(void); -static inline void ddrphy_regif_idle(); +static inline void ddrphy_regif_idle(void); static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps, uint16_t cyc); static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, - uint16_t * js2); + uint16_t *js2); static int16_t _f_scale_adj(int16_t ps); static void ddrtbl_load(void); static void ddr_config_sub(void); -static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz); +static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz); static void ddr_config_sub_h3v1x(void); static void ddr_config(void); static void dbsc_regset(void); @@ -297,6 +297,7 @@ struct DdrtData { uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */ }; + struct DdrtData tcal; static void pvtcode_update(void); @@ -341,10 +342,10 @@ static inline uint32_t vch_nxt(uint32_t pos) } #define foreach_vch(ch) \ -for(ch=vch_nxt(0);ch cyc) - return (uint16_t) div; + return (uint16_t)div; return cyc; } static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, - uint16_t * js2) + uint16_t *js2) { int i; @@ -1046,11 +1048,11 @@ static int16_t _f_scale_adj(int16_t ps) = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 */ tmp = - (int32_t) 4 *(int32_t) ps *(int32_t) ddr_mbps / - (int32_t) ddr_mbpsdiv; - tmp = (int32_t) tmp / (int32_t) 15625; + (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps / + (int32_t)ddr_mbpsdiv; + tmp = (int32_t)tmp / (int32_t)15625; - return (int16_t) tmp; + return (int16_t)tmp; } const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = { @@ -1180,7 +1182,7 @@ static void regif_pll_wa(void) } reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), - _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]); + _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]); /* protect register interface */ ddrphy_regif_idle(); @@ -1219,8 +1221,8 @@ static void regif_pll_wa(void) dsb_sev(); foreach_ech(ch) - if (((Boardcnf->phyvalid) & (1U << ch))) - while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) ; + if (((Boardcnf->phyvalid) & (1U << ch))) + while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f); dsb_sev(); } @@ -1245,7 +1247,7 @@ static void ddrtbl_load(void) if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) break; } - if (JS1_USABLEC_SPEC_HI < i) + if (i > JS1_USABLEC_SPEC_HI) js1_ind = JS1_USABLEC_SPEC_HI; else js1_ind = i; @@ -1533,7 +1535,7 @@ static void ddrtbl_load(void) FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) ***********************************************************************/ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); /*********************************************************************** @@ -1624,6 +1626,7 @@ static void ddr_config_sub(void) uint32_t tmp; uint8_t high_byte[SLICE_CNT]; const uint32_t _par_CALVL_DEVICE_MAP = 1; + foreach_vch(ch) { /*********************************************************************** BOARD SETTINGS (DQ,DM,VREF_DRIVING) @@ -1747,11 +1750,12 @@ static void ddr_config_sub(void) } } -static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz) +static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) { uint32_t slice; uint32_t tmp; uint32_t tgt; + if (ddr_csn / 2) { tgt = 3; } else { @@ -1920,7 +1924,7 @@ static void ddr_config(void) _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( + ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), _cnf_DDR_PHY_ADR_V_REGSET[ ddr_regdef_adr( @@ -1935,7 +1939,7 @@ static void ddr_config(void) _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( + ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), _cnf_DDR_PHY_ADR_G_REGSET[ ddr_regdef_adr( @@ -1952,7 +1956,7 @@ static void ddr_config(void) _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( + ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + 0x0100, _cnf_DDR_PHY_ADR_V_REGSET[ @@ -1964,7 +1968,7 @@ static void ddr_config(void) } reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); /*********************************************************************** WDQDM DLY @@ -2037,7 +2041,7 @@ static void dbsc_regset_pre(void) * set all ranks as density=0(4Gb) for PHY initialization */ foreach_vch(ch) - for (csab = 0; csab < 4; csab++) + for (csab = 0; csab < 4; csab++) mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0)); if (Prr_Product == PRR_PRODUCT_M3) { @@ -2275,11 +2279,11 @@ static void dbsc_regset(void) if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { mmio_write_32(DBSC_DBSCHRW1, tmp[0] + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps - 3); + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps - 3); } else { mmio_write_32(DBSC_DBSCHRW1, tmp[0] + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps); + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps); } /*********************************************************************** @@ -2651,6 +2655,7 @@ static uint32_t set_term_code(void) uint32_t pvtr; uint32_t pvtp; uint32_t pvtn; + term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_DATA_TERM); override = 0; @@ -2801,6 +2806,7 @@ static inline uint32_t wait_freqchgreq(uint32_t assert) uint32_t dataL; uint32_t count; uint32_t ch; + count = 100000; /* H3 Ver.1.x cannot see frqchg_req */ @@ -2833,6 +2839,7 @@ static inline void set_freqchgack(uint32_t assert) { uint32_t ch; uint32_t dataL; + if (assert) dataL = 0x0CF20000; else @@ -2845,6 +2852,7 @@ static inline void set_freqchgack(uint32_t assert) static inline void set_dfifrequency(uint32_t freq) { uint32_t ch; + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { foreach_vch(ch) mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq); @@ -3404,7 +3412,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); wdqdm_le[ch][cs][slice][i] = dataL; win = - (int32_t) wdqdm_te[ch][cs][slice][i] - + (int32_t)wdqdm_te[ch][cs][slice][i] - wdqdm_le[ch][cs][slice][i]; if (min_win > win) min_win = win; @@ -3825,7 +3833,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) dataL; win = - (int32_t) rdqdm_te[ch][cs][slice + + (int32_t)rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] - rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; @@ -3881,7 +3889,7 @@ static uint32_t rdqdm_man1(void) if (ch_have_this_cs[ddr_csn] & (1U << ch)) { for (slice = 0; slice < SLICE_CNT; slice++) { if (ddr_getval_s(ch, slice, - _reg_PHY_RDLVL_STATUS_OBS) != + _reg_PHY_RDLVL_STATUS_OBS) != 0x0D00FFFF) { err = (1U << ch) | (0x10U << slice); @@ -4043,7 +4051,7 @@ static uint32_t rx_offset_cal(void) ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp); } dsb_sev(); - ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *) tmp_ach_as); + ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as); foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { @@ -4100,7 +4108,7 @@ static uint32_t rx_offset_cal_hw(void) ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); } foreach_vch(ch) - for (slice = 0; slice < SLICE_CNT; slice++) + for (slice = 0; slice < SLICE_CNT; slice++) tmp_ach_as[ch][slice] = ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]); @@ -4140,6 +4148,7 @@ static void adjust_rddqs_latency(void) uint32_t maxlatx2; uint32_t tmp; uint32_t rdlat_adjx2[SLICE_CNT]; + foreach_vch(ch) { maxlatx2 = 0; for (slice = 0; slice < SLICE_CNT; slice++) { @@ -4236,7 +4245,7 @@ int32_t rcar_dram_init(void) Judge product and cut ***********************************************************************/ #ifdef RCAR_DDR_FIXED_LSI_TYPE -#if(RCAR_LSI==RCAR_AUTO) +#if (RCAR_LSI == RCAR_AUTO) Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; #else /* RCAR_LSI */ @@ -4304,7 +4313,7 @@ int32_t rcar_dram_init(void) } foreach_ech(ch) - for (cs = 0; cs < CS_CNT; cs++) + for (cs = 0; cs < CS_CNT; cs++) ddr_density[ch][cs] = 0xff; foreach_vch(ch) { @@ -4340,9 +4349,8 @@ int32_t rcar_dram_init(void) ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); - ddr_mul = - CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, - brd_clkdiv * (brd_clkdiva + 1)); + ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, + brd_clkdiv * (brd_clkdiva + 1)); /*********************************************************************** Adjust tccd @@ -4487,6 +4495,7 @@ void pvtcode_update(void) void pvtcode_update2(void) { uint32_t ch; + foreach_vch(ch) { reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), tcal.init_cal[ch] | 0x00020000); @@ -4522,27 +4531,27 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) dataL = mmio_read_32(THS1_TEMP); if (dataL < 2800) { tcal.init_temp = - (143 * (int32_t) dataL - 359000) / 1000; + (143 * (int32_t)dataL - 359000) / 1000; } else { tcal.init_temp = - (121 * (int32_t) dataL - 296300) / 1000; + (121 * (int32_t)dataL - 296300) / 1000; } foreach_vch(ch) { pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F; pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F; - if ((int32_t) pvtp > + if ((int32_t)pvtp > ((tcal.init_temp * 29 - 3625) / 1000)) pvtp = - (int32_t) pvtp + + (int32_t)pvtp + ((3625 - tcal.init_temp * 29) / 1000); else pvtp = 0; - if ((int32_t) pvtn > + if ((int32_t)pvtn > ((tcal.init_temp * 54 - 6750) / 1000)) pvtn = - (int32_t) pvtn + + (int32_t)pvtn + ((6750 - tcal.init_temp * 54) / 1000); else pvtn = 0; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index aaa5f008b..58c9a7a4f 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -115,7 +115,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } + } } }, /* boardcnf[1] RENESAS KRIEK board with M3-W/SoC */ @@ -126,8 +126,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00345201, 0x3201, @@ -147,7 +147,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00302154, 0x2310, @@ -166,8 +166,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[2] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 1rank) */ { @@ -177,8 +177,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { -320, 0x300, 0x0a0, - { - { + { + { {0x02, 0xff}, 0x00543210, 0x3210, @@ -198,7 +198,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x3102, @@ -218,7 +218,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x0213, @@ -238,7 +238,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x0213, @@ -257,8 +257,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[3] RENESAS Starter Kit board with M3-W/SIP(8Gbit 1rank) */ { @@ -268,8 +268,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x0300, 0x00a0, - { - { + { + { {0x02, 0xFF}, 0x00543210U, 0x3201, @@ -289,7 +289,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xFF}, 0x00543210, 0x2310, @@ -308,8 +308,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[4] RENESAS SALVATOR-M(1rank) board with H3 Ver.1.x/SoC */ { @@ -319,8 +319,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { -320, 0x300, 0x0a0, - { - { + { + { {0x02, 0xff}, 0x00315024, 0x3120, @@ -340,7 +340,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00025143, 0x3210, @@ -360,7 +360,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00523104, 0x2301, @@ -380,7 +380,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00153402, 0x2031, @@ -399,8 +399,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[5] RENESAS KRIEK-1rank board with M3-W/SoC */ { @@ -410,8 +410,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0xff}, 0x00345201, 0x3201, @@ -431,7 +431,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00302154, 0x2310, @@ -450,8 +450,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[6] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 2rank) */ { @@ -461,8 +461,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { -320, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00543210, 0x3210, @@ -482,7 +482,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00543210, 0x3102, @@ -502,7 +502,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00543210, 0x0213, @@ -522,7 +522,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00543210, 0x0213, @@ -541,8 +541,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[7] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 1rank) */ { @@ -552,8 +552,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0xff}, 0x00543210, 0x2310, @@ -573,7 +573,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00105432, 0x3210, @@ -593,7 +593,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x2301, @@ -613,7 +613,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x2301, @@ -632,8 +632,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[8] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 2rank) */ { @@ -647,8 +647,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00543210, 0x2310, @@ -669,7 +669,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2)) - { + { {0x02, 0x02}, 0x00543210, 0x2301, @@ -690,7 +690,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #else - { + { {0x02, 0x02}, 0x00105432, 0x3210, @@ -711,7 +711,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #endif - { + { {0x02, 0x02}, 0x00543210, 0x2301, @@ -731,7 +731,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00543210, 0x2301, @@ -750,8 +750,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[9] RENESAS SALVATOR-MS(1rank) board with H3 Ver.2.0 or later/SoC */ { @@ -761,8 +761,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0xff}, 0x00543210, 0x3210, @@ -782,7 +782,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x2301, @@ -802,7 +802,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00452103, 0x3210, @@ -822,7 +822,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00520413, 0x2301, @@ -841,8 +841,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[10] RENESAS Kriek(2rank) board with M3-N/SoC */ { @@ -852,8 +852,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00345201, 0x3201, @@ -872,8 +872,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[11] RENESAS SALVATOR-X board with M3-N/SIP(8Gbit 2rank) */ { @@ -883,8 +883,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { #if (RCAR_DRAM_LPDDR4_MEMCONF == 2) {0x04, 0x04}, #else @@ -907,8 +907,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[12] RENESAS CONDOR board with V3H/SoC */ { @@ -918,8 +918,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00501342, 0x3201, @@ -938,8 +938,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[13] RENESAS KRIEK board with PM3/SoC */ { @@ -949,8 +949,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { -320, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00345201, 0x3201, @@ -970,7 +970,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00302154, 0x2310, @@ -990,7 +990,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00302154, 0x2310, @@ -1010,7 +1010,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0xff, 0xff}, 0, 0, @@ -1029,8 +1029,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[14] SALVATOR-X board with H3 Ver.2.0 or later/SIP(16Gbit 1rank) */ { @@ -1044,8 +1044,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x04, 0xff}, 0x00543210, 0x2310, @@ -1066,7 +1066,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2)) - { + { {0x04, 0xff}, 0x00543210, 0x2301, @@ -1087,7 +1087,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #else - { + { {0x04, 0xff}, 0x00105432, 0x3210, @@ -1108,7 +1108,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #endif - { + { {0x04, 0xff}, 0x00543210, 0x2301, @@ -1128,7 +1128,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x04, 0xff}, 0x00543210, 0x2301, @@ -1147,8 +1147,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[15] RENESAS KRIEK board with H3N */ { @@ -1158,8 +1158,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00345201, 0x3201, @@ -1179,7 +1179,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00302154, 0x2310, @@ -1199,7 +1199,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00302154, 0x2310, @@ -1219,7 +1219,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0xff, 0xff}, 0, 0, @@ -1238,8 +1238,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */ { @@ -1249,8 +1249,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x0300, 0x00a0, - { - { + { + { {0x04, 0x04}, 0x520314FFFF523041, 0x3201, @@ -1270,7 +1270,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x04, 0x04}, 0x314250FFFF312405, 0x2310, @@ -1289,8 +1289,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */ { @@ -1300,8 +1300,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x0300, 0x00a0, - { - { + { + { {0x04, 0x04}, 0x520314FFFF523041, 0x3201, @@ -1320,8 +1320,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) */ { @@ -1331,8 +1331,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x0300, 0x00a0, - { - { + { + { {0x04, 0x04}, 0x00543210, 0x3201, @@ -1352,7 +1352,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x04, 0x04}, 0x00543210, 0x2310, @@ -1371,19 +1371,19 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */ - { - 0x03, - 0x01, - 0x02c0, - 0, - 0x0300, - 0x00a0, - { - { + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { {0x04, 0xff}, 0x00543210, 0x3201, @@ -1403,7 +1403,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x04, 0xff}, 0x00543210, 0x2310, @@ -1422,114 +1422,114 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */ - { - 0x03, - 0x01, - 0x02c0, - 0, - 0x0300, - 0x00a0, - { - { - {0x04, 0x04}, - 0x00345201, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0x04}, + 0x00345201, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { {0x04, 0x04}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, /* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */ - { - 0x03, - 0x01, - 0x02c0, - 0, - 0x0300, - 0x00a0, - { - { - {0x04, 0xff}, - 0x00345201, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x04, 0xff}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - } + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0xff}, + 0x00345201, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x04, 0xff}, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + } }; -void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div) +void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) { uint32_t md; @@ -1560,7 +1560,7 @@ void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div) (void)brd; } -void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div) +void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) { uint32_t md; @@ -1616,13 +1616,13 @@ static const uint32_t TermcodeBySample[20][3] = { /* * SAMPLE board detect function */ -#define PFC_PMMR 0xE6060000U +#define PFC_PMMR 0xE6060000U #define PFC_PUEN5 0xE6060414U #define PFC_PUEN6 0xE6060418U #define PFC_PUD5 0xE6060454U #define PFC_PUD6 0xE6060458U #define GPIO_INDT5 0xE605500CU -#define GPIO_GPSR6 0xE6060118U +#define GPIO_GPSR6 0xE6060118U #if (RCAR_GEN3_ULCB == 0) static void pfc_write_and_poll(uint32_t a, uint32_t v) @@ -1630,7 +1630,7 @@ static void pfc_write_and_poll(uint32_t a, uint32_t v) mmio_write_32(PFC_PMMR, ~v); v = ~mmio_read_32(PFC_PMMR); mmio_write_32(a, v); - while (v != mmio_read_32(a)) ; + while (v != mmio_read_32(a)); dsb_sev(); } #endif @@ -1699,7 +1699,7 @@ static uint32_t opencheck_SSI_WS6(void) static uint32_t _board_judge(void) { uint32_t brd; -#if (RCAR_GEN3_ULCB==1) +#if (RCAR_GEN3_ULCB == 1) /* Starter Kit */ if (Prr_Product == PRR_PRODUCT_H3) { if (Prr_Cut <= PRR_PRODUCT_11) { @@ -1725,7 +1725,7 @@ static uint32_t _board_judge(void) usb2_ovc_open = opencheck_SSI_WS6(); - /* RENESAS Eva-borad */ + /* RENESAS Eva-board */ brd = 99; if (Prr_Product == PRR_PRODUCT_V3H) { /* RENESAS Condor board */ @@ -1738,7 +1738,7 @@ static uint32_t _board_judge(void) /* RENESAS Kriek board with M3-W */ brd = 1; } else if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut<=PRR_PRODUCT_11)) { + && (Prr_Cut <= PRR_PRODUCT_11)) { /* RENESAS Kriek board with PM3 */ brd = 13; } else if ((Prr_Product == PRR_PRODUCT_H3) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h index bad1de90f..7f27b3989 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h @@ -1178,9 +1178,9 @@ #define _reg_PI_TSDO_F1 0x00000493U #define _reg_PI_TSDO_F2 0x00000494U -#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff) -#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff) -#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff) +#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffff) +#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xff) +#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xff) static const uint32_t DDR_REGDEF_TBL[4][1173] = { { @@ -5882,5 +5882,5 @@ static const uint32_t DDR_REGDEF_TBL[4][1173] = { /*0492*/ 0x0808031dU, /*0493*/ 0x1008031dU, /*0494*/ 0x1808031dU, - } + } }; -- cgit v1.2.3 From fcd81d6f93c3f187ed29afae9c55a120d6225d94 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 7 Aug 2019 19:17:42 +0200 Subject: rcar_gen3: drivers: ddr_b: Clean up camel case Signed-off-by: Marek Vasut Change-Id: Ifda28578f326b1d4518560384d50ae98806db26e --- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 1194 ++++++++++---------- .../renesas/rcar/ddr/ddr_b/boot_init_dram_config.c | 38 +- 2 files changed, 616 insertions(+), 616 deletions(-) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index c8e9ae802..244caf6e5 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -31,10 +31,10 @@ #ifdef RCAR_DDR_FIXED_LSI_TYPE #ifndef RCAR_AUTO #define RCAR_AUTO 99 -#define RCAR_H3 0 -#define RCAR_M3 1 +#define RCAR_H3 0 +#define RCAR_M3 1 #define RCAR_M3N 2 -#define RCAR_E3 3 /* NON */ +#define RCAR_E3 3 /* NON */ #define RCAR_H3N 4 #define RCAR_CUT_10 0 @@ -45,42 +45,41 @@ #ifndef RCAR_LSI #define RCAR_LSI RCAR_AUTO #endif + #if (RCAR_LSI == RCAR_AUTO) -static uint32_t Prr_Product; -static uint32_t Prr_Cut; +static uint32_t prr_product; +static uint32_t prr_cut; #else #if (RCAR_LSI == RCAR_H3) -static const uint32_t Prr_Product = PRR_PRODUCT_H3; +static const uint32_t prr_product = PRR_PRODUCT_H3; #elif(RCAR_LSI == RCAR_M3) -static const uint32_t Prr_Product = PRR_PRODUCT_M3; +static const uint32_t prr_product = PRR_PRODUCT_M3; #elif(RCAR_LSI == RCAR_M3N) -static const uint32_t Prr_Product = PRR_PRODUCT_M3N; +static const uint32_t prr_product = PRR_PRODUCT_M3N; #elif(RCAR_LSI == RCAR_H3N) -static const uint32_t Prr_Product = PRR_PRODUCT_H3; +static const uint32_t prr_product = PRR_PRODUCT_H3; #endif /* RCAR_LSI */ #ifndef RCAR_LSI_CUT -static uint32_t Prr_Cut; +static uint32_t prr_cut; #else /* RCAR_LSI_CUT */ #if (RCAR_LSI_CUT == RCAR_CUT_10) -static const uint32_t Prr_Cut = PRR_PRODUCT_10; +static const uint32_t prr_cut = PRR_PRODUCT_10; #elif(RCAR_LSI_CUT == RCAR_CUT_11) -static const uint32_t Prr_Cut = PRR_PRODUCT_11; +static const uint32_t prr_cut = PRR_PRODUCT_11; #elif(RCAR_LSI_CUT == RCAR_CUT_20) -static const uint32_t Prr_Cut = PRR_PRODUCT_20; +static const uint32_t prr_cut = PRR_PRODUCT_20; #elif(RCAR_LSI_CUT == RCAR_CUT_30) -static const uint32_t Prr_Cut = PRR_PRODUCT_30; +static const uint32_t prr_cut = PRR_PRODUCT_30; #endif /* RCAR_LSI_CUT */ #endif /* RCAR_LSI_CUT */ #endif /* RCAR_AUTO_NON */ #else /* RCAR_DDR_FIXED_LSI_TYPE */ -static uint32_t Prr_Product; -static uint32_t Prr_Cut; +static uint32_t prr_product; +static uint32_t prr_cut; #endif /* RCAR_DDR_FIXED_LSI_TYPE */ -char *pRCAR_DDR_VERSION; -uint32_t _cnf_BOARDTYPE; -static const uint32_t *pDDR_REGDEF_TBL; +static const uint32_t *p_ddr_regdef_tbl; static uint32_t brd_clk; static uint32_t brd_clkdiv; static uint32_t brd_clkdiva; @@ -88,7 +87,7 @@ static uint32_t ddr_mbps; static uint32_t ddr_mbpsdiv; static uint32_t ddr_tccd; static uint32_t ddr_phycaslice; -static const struct _boardcnf *Boardcnf; +static const struct _boardcnf *board_cnf; static uint32_t ddr_phyvalid; static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; static uint32_t ch_have_this_cs[CS_CNT] __attribute__ ((aligned(64))); @@ -119,10 +118,10 @@ static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX]; static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; -static uint32_t Pll3Mode; +static uint32_t pll3_mode; static uint32_t loop_max; #ifdef DDR_BACKUPMODE -uint32_t ddrBackup; +uint32_t ddr_backup; /* #define DDR_BACKUPMODE_HALF //for Half channel(ch0,1 only) */ #endif @@ -292,13 +291,13 @@ static uint32_t rx_offset_cal_hw(void); static void adjust_rddqs_latency(void); static void adjust_wpath_latency(void); -struct DdrtData { +struct ddrt_data { int32_t init_temp; /* Initial Temperature (do) */ uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */ }; -struct DdrtData tcal; +static struct ddrt_data tcal; static void pvtcode_update(void); static void pvtcode_update2(void); @@ -363,129 +362,129 @@ static void cpg_write_32(uint32_t a, uint32_t v) static void pll3_control(uint32_t high) { - uint32_t dataL, dataDIV, dataMUL, tmpDIV; + uint32_t data_l, data_div, data_mul, tmp_div; if (high) { - tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) / + tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr_mul) / 2; - dataMUL = (((ddr_mul * tmpDIV) - 1) << 24) | + data_mul = (((ddr_mul * tmp_div) - 1) << 24) | (brd_clkdiva << 7); - Pll3Mode = 1; + pll3_mode = 1; loop_max = 2; } else { - tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) / + tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr0800_mul) / 2; - dataMUL = (((ddr0800_mul * tmpDIV) - 1) << 24) | + data_mul = (((ddr0800_mul * tmp_div) - 1) << 24) | (brd_clkdiva << 7); - Pll3Mode = 0; + pll3_mode = 0; loop_max = 8; } - switch (tmpDIV) { + switch (tmp_div) { case 1: - dataDIV = 0; + data_div = 0; break; case 2: case 3: case 4: - dataDIV = tmpDIV; + data_div = tmp_div; break; default: - dataDIV = 6; - dataMUL = (dataMUL * tmpDIV) / 3; + data_div = 6; + data_mul = (data_mul * tmp_div) / 3; break; } - dataMUL = dataMUL | (brd_clkdiva << 7); + data_mul = data_mul | (brd_clkdiva << 7); /* PLL3 disable */ - dataL = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; - cpg_write_32(CPG_PLLECR, dataL); + data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; + cpg_write_32(CPG_PLLECR, data_l); dsb_sev(); - if ((Prr_Product == PRR_PRODUCT_M3) || - ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_20))) { + if ((prr_product == PRR_PRODUCT_M3) || + ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) { /* PLL3 DIV resetting(Lowest value:3) */ - dataL = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); + data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, data_l); dsb_sev(); /* zb3 clk stop */ - dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); - cpg_write_32(CPG_ZB3CKCR, dataL); + data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); + cpg_write_32(CPG_ZB3CKCR, data_l); dsb_sev(); /* PLL3 enable */ - dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); - cpg_write_32(CPG_PLLECR, dataL); + data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); + cpg_write_32(CPG_PLLECR, data_l); dsb_sev(); do { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); dsb_sev(); /* PLL3 DIV resetting (Highest value:0) */ - dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); + data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, data_l); dsb_sev(); /* DIV SET KICK */ - dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, dataL); + data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, data_l); dsb_sev(); /* PLL3 multiplie set */ - cpg_write_32(CPG_PLL3CR, dataMUL); + cpg_write_32(CPG_PLL3CR, data_mul); dsb_sev(); do { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); dsb_sev(); /* PLL3 DIV resetting(Target value) */ - dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); + data_l = (data_div << 16) | data_div | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, data_l); dsb_sev(); /* DIV SET KICK */ - dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, dataL); + data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, data_l); dsb_sev(); do { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); dsb_sev(); /* zb3 clk start */ - dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); - cpg_write_32(CPG_ZB3CKCR, dataL); + data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); + cpg_write_32(CPG_ZB3CKCR, data_l); dsb_sev(); } else { /* H3Ver.3.0/M3N/V3H */ /* PLL3 multiplie set */ - cpg_write_32(CPG_PLL3CR, dataMUL); + cpg_write_32(CPG_PLL3CR, data_mul); dsb_sev(); /* PLL3 DIV set(Target value) */ - dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); + data_l = (data_div << 16) | data_div | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, data_l); /* DIV SET KICK */ - dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, dataL); + data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, data_l); dsb_sev(); /* PLL3 enable */ - dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); - cpg_write_32(CPG_PLLECR, dataL); + data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); + cpg_write_32(CPG_PLLECR, data_l); dsb_sev(); do { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); dsb_sev(); } } @@ -503,15 +502,15 @@ static inline void dsb_sev(void) ******************************************************************************/ static void wait_dbcmd(void) { - uint32_t dataL; + uint32_t data_l; /* dummy read */ - dataL = mmio_read_32(DBSC_DBCMD); + data_l = mmio_read_32(DBSC_DBCMD); dsb_sev(); while (1) { /* wait DBCMD 1=busy, 0=ready */ - dataL = mmio_read_32(DBSC_DBWAIT); + data_l = mmio_read_32(DBSC_DBWAIT); dsb_sev(); - if ((dataL & 0x00000001) == 0x00) + if ((data_l & 0x00000001) == 0x00) break; } } @@ -533,8 +532,8 @@ static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) uint32_t loop; val = 0; - if ((Prr_Product != PRR_PRODUCT_M3N) - && (Prr_Product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) + && (prr_product != PRR_PRODUCT_V3H)) { mmio_write_32(DBSC_DBPDRGA(phyno), regadd); dsb_sev(); @@ -580,8 +579,8 @@ static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) uint32_t val; uint32_t loop; - if ((Prr_Product != PRR_PRODUCT_M3N) - && (Prr_Product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) + && (prr_product != PRR_PRODUCT_V3H)) { mmio_write_32(DBSC_DBPDRGA(phyno), regadd); dsb_sev(); for (loop = 0; loop < loop_max; loop++) { @@ -629,8 +628,8 @@ static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) uint32_t val; uint32_t loop; - if ((Prr_Product != PRR_PRODUCT_M3N) - && (Prr_Product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) + && (prr_product != PRR_PRODUCT_V3H)) { foreach_vch(ch) { mmio_write_32(DBSC_DBPDRGA(ch), regadd); dsb_sev(); @@ -668,17 +667,17 @@ static inline void ddrphy_regif_idle(void) ******************************************************************************/ static inline uint32_t ddr_regdef(uint32_t _regdef) { - return pDDR_REGDEF_TBL[_regdef]; + return p_ddr_regdef_tbl[_regdef]; } static inline uint32_t ddr_regdef_adr(uint32_t _regdef) { - return DDR_REGDEF_ADR(pDDR_REGDEF_TBL[_regdef]); + return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]); } static inline uint32_t ddr_regdef_lsb(uint32_t _regdef) { - return DDR_REGDEF_LSB(pDDR_REGDEF_TBL[_regdef]); + return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]); } static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, @@ -864,8 +863,8 @@ static uint32_t ddrphy_regif_chk(void) uint32_t err; uint32_t PI_VERSION_CODE; - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3)) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3)) { PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ } else { PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ @@ -885,11 +884,11 @@ static uint32_t ddrphy_regif_chk(void) ******************************************************************************/ struct _jedec_spec1 { uint16_t fx3; - uint8_t RLwoDBI; - uint8_t RLwDBI; + uint8_t rlwodbi; + uint8_t rlwdbi; uint8_t WL; - uint8_t nWR; - uint8_t nRTP; + uint8_t nwr; + uint8_t nrtp; uint8_t MR1; uint8_t MR2; }; @@ -915,33 +914,33 @@ struct _jedec_spec2 { uint16_t cyc; }; -#define JS2_tSR 0 -#define JS2_tXP 1 -#define JS2_tRTP 2 -#define JS2_tRCD 3 -#define JS2_tRPpb 4 -#define JS2_tRPab 5 -#define JS2_tRAS 6 -#define JS2_tWR 7 -#define JS2_tWTR 8 -#define JS2_tRRD 9 -#define JS2_tPPD 10 -#define JS2_tFAW 11 -#define JS2_tDQSCK 12 -#define JS2_tCKEHCMD 13 -#define JS2_tCKELCMD 14 -#define JS2_tCKELPD 15 -#define JS2_tMRR 16 -#define JS2_tMRW 17 -#define JS2_tMRD 18 -#define JS2_tZQCALns 19 -#define JS2_tZQLAT 20 -#define JS2_tIEdly 21 +#define js2_tsr 0 +#define js2_txp 1 +#define js2_trtp 2 +#define js2_trcd 3 +#define js2_trppb 4 +#define js2_trpab 5 +#define js2_tras 6 +#define js2_twr 7 +#define js2_twtr 8 +#define js2_trrd 9 +#define js2_tppd 10 +#define js2_tfaw 11 +#define js2_tdqsck 12 +#define js2_tckehcmd 13 +#define js2_tckelcmd 14 +#define js2_tckelpd 15 +#define js2_tmrr 16 +#define js2_tmrw 17 +#define js2_tmrd 18 +#define js2_tzqcalns 19 +#define js2_tzqlat 20 +#define js2_tiedly 21 #define JS2_TBLCNT 22 -#define JS2_tRCpb (JS2_TBLCNT) -#define JS2_tRCab (JS2_TBLCNT + 1) -#define JS2_tRFCab (JS2_TBLCNT + 2) +#define js2_trcpb (JS2_TBLCNT) +#define js2_trcab (JS2_TBLCNT + 1) +#define js2_trfcab (JS2_TBLCNT + 2) #define JS2_CNT (JS2_TBLCNT + 3) #ifndef JS2_DERATE @@ -997,7 +996,7 @@ const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { } }; -const uint16_t jedec_spec2_tRFC_ab[7] = { +const uint16_t jedec_spec2_trfc_ab[7] = { /* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */ 130, 180, 180, 280, 280, 560, 560 }; @@ -1034,8 +1033,8 @@ static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, jedec_spec2[JS2_DERATE][i].cyc); } - js2[JS2_tRCpb] = js2[JS2_tRAS] + js2[JS2_tRPpb]; - js2[JS2_tRCab] = js2[JS2_tRAS] + js2[JS2_tRPab]; + js2[js2_trcpb] = js2[js2_tras] + js2[js2_trppb]; + js2[js2_trcab] = js2[js2_tras] + js2[js2_trpab]; } /* scaler for DELAY value */ @@ -1055,7 +1054,7 @@ static int16_t _f_scale_adj(int16_t ps) return (int16_t)tmp; } -const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = { +static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR1_DATA_F0_0, _reg_PI_MR1_DATA_F0_1, @@ -1068,7 +1067,7 @@ const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = { _reg_PI_MR1_DATA_F1_3} }; -const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = { +static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR2_DATA_F0_0, _reg_PI_MR2_DATA_F0_1, @@ -1081,7 +1080,7 @@ const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = { _reg_PI_MR2_DATA_F1_3} }; -const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = { +static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR3_DATA_F0_0, _reg_PI_MR3_DATA_F0_1, @@ -1094,7 +1093,7 @@ const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = { _reg_PI_MR3_DATA_F1_3} }; -const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = { +const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR11_DATA_F0_0, _reg_PI_MR11_DATA_F0_1, @@ -1107,7 +1106,7 @@ const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = { _reg_PI_MR11_DATA_F1_3} }; -const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = { +const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR12_DATA_F0_0, _reg_PI_MR12_DATA_F0_1, @@ -1120,7 +1119,7 @@ const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = { _reg_PI_MR12_DATA_F1_3} }; -const uint32_t _reg_PI_MR14_DATA_Fx_CSx[2][CSAB_CNT] = { +const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR14_DATA_F0_0, _reg_PI_MR14_DATA_F0_1, @@ -1140,7 +1139,7 @@ static void regif_pll_wa(void) { uint32_t ch; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { // PLL setting for PHY : H3 Ver.1.x reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), (0x0064U << @@ -1188,7 +1187,7 @@ static void regif_pll_wa(void) ddrphy_regif_idle(); pll3_control(0); - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { /* non */ } else { reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN), @@ -1221,7 +1220,7 @@ static void regif_pll_wa(void) dsb_sev(); foreach_ech(ch) - if (((Boardcnf->phyvalid) & (1U << ch))) + if (((board_cnf->phyvalid) & (1U << ch))) while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f); dsb_sev(); } @@ -1235,7 +1234,7 @@ static void ddrtbl_load(void) uint32_t slice; uint32_t csab; uint32_t adr; - uint32_t dataL; + uint32_t data_l; uint32_t tmp[3]; uint16_t dataS; @@ -1252,10 +1251,10 @@ static void ddrtbl_load(void) else js1_ind = i; - if (Boardcnf->dbi_en) - RL = js1[js1_ind].RLwDBI; + if (board_cnf->dbi_en) + RL = js1[js1_ind].rlwdbi; else - RL = js1[js1_ind].RLwoDBI; + RL = js1[js1_ind].rlwodbi; WL = js1[js1_ind].WL; @@ -1265,8 +1264,8 @@ static void ddrtbl_load(void) /*********************************************************************** PREPARE TBL ***********************************************************************/ - if (Prr_Product == PRR_PRODUCT_H3) { - if (Prr_Cut <= PRR_PRODUCT_11) { + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { /* H3 Ver.1.x */ _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, DDR_PHY_SLICE_REGSET_H3, @@ -1342,7 +1341,7 @@ static void ddrtbl_load(void) DDR_PHY_ADR_I_NUM = 0; } - } else if (Prr_Product == PRR_PRODUCT_M3) { + } else if (prr_product == PRR_PRODUCT_M3) { /* M3-W */ _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3); @@ -1408,7 +1407,7 @@ static void ddrtbl_load(void) /*********************************************************************** PLL CODE CHANGE ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, 0x1142); ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, @@ -1418,7 +1417,7 @@ static void ddrtbl_load(void) /*********************************************************************** on fly gate adjust ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10)) { + if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) { ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_ON_FLY_GATE_ADJUST_EN, 0x00); } @@ -1430,7 +1429,7 @@ static void ddrtbl_load(void) for (i = 0; i < 2; i++) { for (csab = 0; csab < CSAB_CNT; csab++) { ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR11_DATA_Fx_CSx[i][csab], + reg_pi_mr11_data_fx_csx[i][csab], _def_LPDDR4_ODT); } } @@ -1440,43 +1439,43 @@ static void ddrtbl_load(void) for (i = 0; i < 2; i++) { for (csab = 0; csab < CSAB_CNT; csab++) { ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR12_DATA_Fx_CSx[i][csab], + reg_pi_mr12_data_fx_csx[i][csab], _def_LPDDR4_VREFCA); } } #endif /* _def_LPDDR4_VREFCA */ - if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { - js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; - if (js2[JS2_tIEdly] > (RL)) - js2[JS2_tIEdly] = RL; - } else if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_11)) { - js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; - } else if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { - js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); - } - - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { - if ((js2[JS2_tIEdly]) >= 0x1e) + if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { + js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; + if (js2[js2_tiedly] > (RL)) + js2[js2_tiedly] = RL; + } else if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_11)) { + js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; + } else if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { + js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); + } + + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { + if ((js2[js2_tiedly]) >= 0x1e) dataS = 0x1e; else - dataS = js2[JS2_tIEdly]; + dataS = js2[js2_tiedly]; } else { - if ((js2[JS2_tIEdly]) >= 0x0e) + if ((js2[js2_tiedly]) >= 0x0e) dataS = 0x0e; else - dataS = js2[JS2_tIEdly]; + dataS = js2[js2_tiedly]; } ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, (dataS - 2)); - if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_OE_DLY, dataS); } @@ -1484,14 +1483,14 @@ static void ddrtbl_load(void) if (ddrtbl_getval (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) { - dataL = WL - 1; + data_l = WL - 1; } else { - dataL = WL; + data_l = WL; } - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, dataL - 2); - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, dataL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l); - if (Boardcnf->dbi_en) { + if (board_cnf->dbi_en) { ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 0x01); ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, @@ -1505,27 +1504,27 @@ static void ddrtbl_load(void) tmp[0] = js1[js1_ind].MR1; tmp[1] = js1[js1_ind].MR2; - dataL = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); - if (Boardcnf->dbi_en) - tmp[2] = dataL | 0xc0; + data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); + if (board_cnf->dbi_en) + tmp[2] = data_l | 0xc0; else - tmp[2] = dataL & (~0xc0); + tmp[2] = data_l & (~0xc0); for (i = 0; i < 2; i++) { for (csab = 0; csab < CSAB_CNT; csab++) { ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR1_DATA_Fx_CSx[i][csab], tmp[0]); + reg_pi_mr1_data_fx_csx[i][csab], tmp[0]); ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR2_DATA_Fx_CSx[i][csab], tmp[1]); + reg_pi_mr2_data_fx_csx[i][csab], tmp[1]); ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR3_DATA_Fx_CSx[i][csab], tmp[2]); + reg_pi_mr3_data_fx_csx[i][csab], tmp[2]); } } /*********************************************************************** DDRPHY INT START ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { /* non */ } else { regif_pll_wa(); @@ -1559,9 +1558,9 @@ static void ddrtbl_load(void) reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); } - if (((Prr_Product == PRR_PRODUCT_M3) - || (Prr_Product == PRR_PRODUCT_M3N)) && - ((0x00ffffff & (uint32_t)((Boardcnf->ch[0].ca_swap) >> 40)) + if (((prr_product == PRR_PRODUCT_M3) + || (prr_product == PRR_PRODUCT_M3N)) && + ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40)) != 0x00)) { adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE; for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { @@ -1576,7 +1575,7 @@ static void ddrtbl_load(void) for (i = 0; i < 2; i++) { for (csab = 0; csab < CSAB_CNT; csab++) { ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR11_DATA_Fx_CSx[i][csab], + reg_pi_mr11_data_fx_csx[i][csab], 0x66); } } @@ -1622,7 +1621,7 @@ static void ddr_config_sub(void) { uint32_t i; uint32_t ch, slice; - uint32_t dataL; + uint32_t data_l; uint32_t tmp; uint8_t high_byte[SLICE_CNT]; const uint32_t _par_CALVL_DEVICE_MAP = 1; @@ -1633,11 +1632,11 @@ static void ddr_config_sub(void) ***********************************************************************/ for (slice = 0; slice < SLICE_CNT; slice++) { high_byte[slice] = - (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) % 2; + (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2; ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, - Boardcnf->ch[ch].dq_swap[slice]); + board_cnf->ch[ch].dq_swap[slice]); ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, - Boardcnf->ch[ch].dm_swap[slice]); + board_cnf->ch[ch].dm_swap[slice]); if (high_byte[slice]) { /* HIGHER 16 BYTE */ ddr_setval_s(ch, slice, @@ -1654,56 +1653,56 @@ static void ddr_config_sub(void) /*********************************************************************** BOARD SETTINGS (CA,ADDR_SEL) ***********************************************************************/ - dataL = (0x00ffffff & (uint32_t)(Boardcnf->ch[ch].ca_swap)) | + data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) | 0x00888888; /* --- ADR_CALVL_SWIZZLE --- */ - if (Prr_Product == PRR_PRODUCT_M3) { - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL); + if (prr_product == PRR_PRODUCT_M3) { + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l); ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l); ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); } else { - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l); ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); } /* --- ADR_ADDR_SEL --- */ - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_11)) { - dataL = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap; + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_11)) { + data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; } else { - dataL = 0; - tmp = Boardcnf->ch[ch].ca_swap; + data_l = 0; + tmp = board_cnf->ch[ch].ca_swap; for (i = 0; i < 6; i++) { - dataL |= ((tmp & 0x0f) << (i * 5)); + data_l |= ((tmp & 0x0f) << (i * 5)); tmp = tmp >> 4; } } - ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, dataL); + ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l); if (ddr_phycaslice == 1) { /* ----------- adr slice2 swap ----------- */ - tmp = (uint32_t)((Boardcnf->ch[ch].ca_swap) >> 40); - dataL = (tmp & 0x00ffffff) | 0x00888888; + tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40); + data_l = (tmp & 0x00ffffff) | 0x00888888; /* --- ADR_CALVL_SWIZZLE --- */ - if (Prr_Product == PRR_PRODUCT_M3) { - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL); + if (prr_product == PRR_PRODUCT_M3) { + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l); ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL); + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l); ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); } else { - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL); + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l); ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); ddr_setval_s(ch, 2, _reg_PHY_CALVL_DEVICE_MAP, @@ -1711,42 +1710,42 @@ static void ddr_config_sub(void) } /* --- ADR_ADDR_SEL --- */ - dataL = 0; + data_l = 0; for (i = 0; i < 6; i++) { - dataL |= ((tmp & 0x0f) << (i * 5)); + data_l |= ((tmp & 0x0f) << (i * 5)); tmp = tmp >> 4; } - ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, dataL); + ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l); } /*********************************************************************** BOARD SETTINGS (BYTE_ORDER_SEL) ***********************************************************************/ - if (Prr_Product == PRR_PRODUCT_M3) { + if (prr_product == PRR_PRODUCT_M3) { /* --- DATA_BYTE_SWAP --- */ - dataL = 0; - tmp = Boardcnf->ch[ch].dqs_swap; + data_l = 0; + tmp = board_cnf->ch[ch].dqs_swap; for (i = 0; i < 4; i++) { - dataL |= ((tmp & 0x03) << (i * 2)); + data_l |= ((tmp & 0x03) << (i * 2)); tmp = tmp >> 4; } } else { /* --- DATA_BYTE_SWAP --- */ - dataL = Boardcnf->ch[ch].dqs_swap; + data_l = board_cnf->ch[ch].dqs_swap; ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01); ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, - (dataL) & 0x0f); + (data_l) & 0x0f); ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, - (dataL >> 4 * 1) & 0x0f); + (data_l >> 4 * 1) & 0x0f); ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2, - (dataL >> 4 * 2) & 0x0f); + (data_l >> 4 * 2) & 0x0f); ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3, - (dataL >> 4 * 3) & 0x0f); + (data_l >> 4 * 3) & 0x0f); ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00); } - ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, dataL); + ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l); } } @@ -1763,11 +1762,11 @@ static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) } for (slice = 0; slice < SLICE_CNT; slice++) { - tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (tgt == tmp) break; } - tmp = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap; + tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; if (slice % 2) tmp |= 0x00888888; *p_swz = tmp; @@ -1776,7 +1775,7 @@ static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) static void ddr_config_sub_h3v1x(void) { uint32_t ch, slice; - uint32_t dataL; + uint32_t data_l; uint32_t tmp; uint8_t high_byte[SLICE_CNT]; uint32_t ca_swizzle; @@ -1798,14 +1797,14 @@ static void ddr_config_sub_h3v1x(void) ***********************************************************************/ csmap = 0; for (slice = 0; slice < SLICE_CNT; slice++) { - tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; high_byte[slice] = tmp % 2; if (tmp == 1 && (slice >= 2)) csmap |= 0x05; if (tmp == 3 && (slice >= 2)) csmap |= 0x50; ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING, - Boardcnf->ch[ch].dq_swap[slice]); + board_cnf->ch[ch].dq_swap[slice]); if (high_byte[slice]) { /* HIGHER 16 BYTE */ ddr_setval_s(ch, slice, @@ -1821,7 +1820,7 @@ static void ddr_config_sub_h3v1x(void) /*********************************************************************** BOARD SETTINGS (CA,ADDR_SEL) ***********************************************************************/ - ca = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap; + ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca); ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap); @@ -1844,7 +1843,7 @@ static void ddr_config_sub_h3v1x(void) else o_inv = o_mr15; - tmp = Boardcnf->ch[ch].dq_swap[slice]; + tmp = board_cnf->ch[ch].dq_swap[slice]; inv = 0; j = 0; for (bit_soc = 0; bit_soc < 8; bit_soc++) { @@ -1853,13 +1852,13 @@ static void ddr_config_sub_h3v1x(void) if (o_inv & (1U << bit_mem)) inv |= (1U << bit_soc); } - dataL = o_mr32_mr40; + data_l = o_mr32_mr40; if (!high_byte[slice]) - dataL |= (inv << 24); + data_l |= (inv << 24); if (high_byte[slice]) - dataL |= (inv << 16); + data_l |= (inv << 16); ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8, - dataL); + data_l); } } } @@ -1868,7 +1867,7 @@ static void ddr_config(void) { int32_t i; uint32_t ch, slice; - uint32_t dataL; + uint32_t data_l; uint32_t tmp; int8_t _adj; int16_t adj; @@ -1882,7 +1881,7 @@ static void ddr_config(void) /*********************************************************************** configure ddrphy registers ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_config_sub_h3v1x(); } else { ddr_config_sub(); /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ @@ -1895,7 +1894,7 @@ static void ddr_config(void) for (slice = 0; slice < SLICE_CNT; slice++) { patm = 0; for (i = 0; i < 16; i++) { - tmp = Boardcnf->ch[ch].wdqlvl_patt[i]; + tmp = board_cnf->ch[ch].wdqlvl_patt[i]; patt.ui8[i] = tmp & 0xff; if (tmp & 0x100) patm |= (1U << i); @@ -1915,14 +1914,14 @@ static void ddr_config(void) /*********************************************************************** CACS DLY ***********************************************************************/ - dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); + data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U); foreach_vch(ch) { for (i = 0; i < (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i++) { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj); + data_l + adj); reg_ddrphy_write(ch, ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), @@ -1934,10 +1933,10 @@ static void ddr_config(void) for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj); + data_l + adj); reg_ddrphy_write(ch, ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), @@ -1950,11 +1949,11 @@ static void ddr_config(void) if (ddr_phycaslice == 1) { for (i = 0; i < 6; i++) { adj = _f_scale_adj( - Boardcnf->ch[ch].cacs_adj[ + board_cnf->ch[ch].cacs_adj[ i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj); + data_l + adj); reg_ddrphy_write(ch, ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + @@ -1973,19 +1972,19 @@ static void ddr_config(void) /*********************************************************************** WDQDM DLY ***********************************************************************/ - dataL = Boardcnf->dqdm_dly_w; + data_l = board_cnf->dqdm_dly_w; foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { for (i = 0; i <= 8; i++) { dq = slice * 8 + i; if (i == 8) - _adj = Boardcnf->ch[ch].dm_adj_w[slice]; + _adj = board_cnf->ch[ch].dm_adj_w[slice]; else - _adj = Boardcnf->ch[ch].dq_adj_w[dq]; + _adj = board_cnf->ch[ch].dq_adj_w[dq]; adj = _f_scale_adj(_adj); ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], - dataL + adj); + data_l + adj); } } } @@ -1993,22 +1992,22 @@ static void ddr_config(void) /*********************************************************************** RDQDM DLY ***********************************************************************/ - dataL = Boardcnf->dqdm_dly_r; + data_l = board_cnf->dqdm_dly_r; foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { for (i = 0; i <= 8; i++) { dq = slice * 8 + i; if (i == 8) - _adj = Boardcnf->ch[ch].dm_adj_r[slice]; + _adj = board_cnf->ch[ch].dm_adj_r[slice]; else - _adj = Boardcnf->ch[ch].dq_adj_r[dq]; + _adj = board_cnf->ch[ch].dq_adj_r[dq]; adj = _f_scale_adj(_adj); ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY - [i], dataL + adj); + [i], data_l + adj); ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY - [i], dataL + adj); + [i], data_l + adj); } } } @@ -2020,7 +2019,7 @@ static void ddr_config(void) static void dbsc_regset_pre(void) { uint32_t ch, csab; - uint32_t dataL; + uint32_t data_l; /*********************************************************************** PRIMARY SETTINGS @@ -2034,7 +2033,7 @@ static void dbsc_regset_pre(void) mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); /* Chanel map (H3 Ver.1.x) */ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); /* DRAM SIZE REGISTER: @@ -2044,20 +2043,20 @@ static void dbsc_regset_pre(void) for (csab = 0; csab < 4; csab++) mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0)); - if (Prr_Product == PRR_PRODUCT_M3) { - dataL = 0xe4e4e4e4; + if (prr_product == PRR_PRODUCT_M3) { + data_l = 0xe4e4e4e4; foreach_ech(ch) { if ((ddr_phyvalid & (1U << ch))) - dataL = (dataL & (~(0x000000FF << (ch * 8)))) - | (((Boardcnf->ch[ch].dqs_swap & 0x0003) - | ((Boardcnf->ch[ch].dqs_swap & 0x0030) + data_l = (data_l & (~(0x000000FF << (ch * 8)))) + | (((board_cnf->ch[ch].dqs_swap & 0x0003) + | ((board_cnf->ch[ch].dqs_swap & 0x0030) >> 2) - | ((Boardcnf->ch[ch].dqs_swap & 0x0300) + | ((board_cnf->ch[ch].dqs_swap & 0x0300) >> 4) - | ((Boardcnf->ch[ch].dqs_swap & 0x3000) + | ((board_cnf->ch[ch].dqs_swap & 0x3000) >> 6)) << (ch * 8)); } - mmio_write_32(DBSC_DBBSWAP, dataL); + mmio_write_32(DBSC_DBBSWAP, data_l); } } @@ -2065,20 +2064,20 @@ static void dbsc_regset(void) { int32_t i; uint32_t ch; - uint32_t dataL; - uint32_t dataL2; + uint32_t data_l; + uint32_t data_l2; uint32_t tmp[4]; /* RFC */ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_20) + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) && (max_density == 0)) { - js2[JS2_tRFCab] = + js2[js2_trfcab] = _f_scale(ddr_mbps, ddr_mbpsdiv, - 1UL * jedec_spec2_tRFC_ab[1] * 1000, 0); + 1UL * jedec_spec2_trfc_ab[1] * 1000, 0); } else { - js2[JS2_tRFCab] = + js2[js2_trfcab] = _f_scale(ddr_mbps, ddr_mbpsdiv, - 1UL * jedec_spec2_tRFC_ab[max_density] * + 1UL * jedec_spec2_trfc_ab[max_density] * 1000, 0); } @@ -2092,46 +2091,46 @@ static void dbsc_regset(void) mmio_write_32(DBSC_DBTR(2), 0); /* DBTR3.TRCD: tRCD */ - mmio_write_32(DBSC_DBTR(3), js2[JS2_tRCD]); + mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]); /* DBTR4.TRPA,TRP: tRPab,tRPpb */ - mmio_write_32(DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]); + mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]); /* DBTR5.TRC : use tRCpb */ - mmio_write_32(DBSC_DBTR(5), js2[JS2_tRCpb]); + mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]); /* DBTR6.TRAS : tRAS */ - mmio_write_32(DBSC_DBTR(6), js2[JS2_tRAS]); + mmio_write_32(DBSC_DBTR(6), js2[js2_tras]); /* DBTR7.TRRD : tRRD */ - mmio_write_32(DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]); + mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]); /* DBTR8.TFAW : tFAW */ - mmio_write_32(DBSC_DBTR(8), js2[JS2_tFAW]); + mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]); /* DBTR9.TRDPR : tRTP */ - mmio_write_32(DBSC_DBTR(9), js2[JS2_tRTP]); + mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]); - /* DBTR10.TWR : nWR */ - mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nWR); + /* DBTR10.TWR : nwr */ + mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr); /* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */ mmio_write_32(DBSC_DBTR(11), - RL + js2[JS2_tDQSCK] + (16 / 2) + 1 - WL + 2 + 2); + RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2); /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ - dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR]; - mmio_write_32(DBSC_DBTR(12), (dataL << 16) | dataL); + data_l = WL + 1 + (16 / 2) + js2[js2_twtr]; + mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l); /* DBTR13.TRFCAB : tRFCab */ - mmio_write_32(DBSC_DBTR(13), (js2[JS2_tRFCab])); + mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab])); /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */ mmio_write_32(DBSC_DBTR(14), - (js2[JS2_tCKEHCMD] << 16) | (js2[JS2_tCKEHCMD])); + (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd])); /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */ - mmio_write_32(DBSC_DBTR(15), (js2[JS2_tSR] << 16) | (js2[JS2_tCKELPD])); + mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd])); /* DBTR16 */ /* WDQL : tphy_wrlat + tphy_wrdata */ @@ -2154,13 +2153,13 @@ static void dbsc_regset(void) /* WRCSGAP = 5 */ tmp[1] = 5; /* RDCSLAT = RDLAT_ADJ +2 */ - if (Prr_Product == PRR_PRODUCT_M3) { + if (prr_product == PRR_PRODUCT_M3) { tmp[2] = tmp[3]; } else { tmp[2] = tmp[3] + 2; } /* RDCSGAP = 6 */ - if (Prr_Product == PRR_PRODUCT_M3) { + if (prr_product == PRR_PRODUCT_M3) { tmp[3] = 4; } else { tmp[3] = 6; @@ -2170,7 +2169,7 @@ static void dbsc_regset(void) /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */ mmio_write_32(DBSC_DBTR(17), - (js2[JS2_tMRR] << 24) | (js2[JS2_tMRD] << 16)); + (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16)); /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ mmio_write_32(DBSC_DBTR(18), 0); @@ -2179,32 +2178,32 @@ static void dbsc_regset(void) mmio_write_32(DBSC_DBTR(19), 0); /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ - dataL = js2[JS2_tRFCab] + js2[JS2_tCKEHCMD]; - mmio_write_32(DBSC_DBTR(20), (dataL << 16) | dataL); + data_l = js2[js2_trfcab] + js2[js2_tckehcmd]; + mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l); /* DBTR21.TCCD */ /* DBTR23.TCCD */ /* H3 Ver.1.0 cannot use TBTR23 feature */ if (ddr_tccd == 8 && - !((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_10)) + !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10)) ) { - dataL = 8; - mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); + data_l = 8; + mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); mmio_write_32(DBSC_DBTR(23), 0x00000002); } else if (ddr_tccd <= 11) { - dataL = 11; - mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); + data_l = 11; + mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); mmio_write_32(DBSC_DBTR(23), 0x00000000); } else { - dataL = ddr_tccd; - mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); + data_l = ddr_tccd; + mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); mmio_write_32(DBSC_DBTR(23), 0x00000000); } /* DBTR22.ZQLAT : */ - dataL = js2[JS2_tZQCALns] * 100; /* 1000 * 1000 ps */ - dataL = (dataL << 16) | (js2[JS2_tZQLAT] + 24 + 20); - mmio_write_32(DBSC_DBTR(22), dataL); + data_l = js2[js2_tzqcalns] * 100; /* 1000 * 1000 ps */ + data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20); + mmio_write_32(DBSC_DBTR(22), data_l); /* DBTR25 : do not use in LPDDR4 */ mmio_write_32(DBSC_DBTR(25), 0); @@ -2219,16 +2218,16 @@ static void dbsc_regset(void) #define _par_DBRNK_VAL (0x7007) for (i = 0; i < 4; i++) { - dataL = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_11) && (i == 0)) { - dataL += 1; + data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_11) && (i == 0)) { + data_l += 1; } - dataL2 = 0; + data_l2 = 0; foreach_vch(ch) { - dataL2 = dataL2 | (dataL << (4 * ch)); + data_l2 = data_l2 | (data_l << (4 * ch)); } - mmio_write_32(DBSC_DBRNK(2 + i), dataL2); + mmio_write_32(DBSC_DBRNK(2 + i), data_l2); } mmio_write_32(DBSC_DBADJ0, 0x00000000); @@ -2237,17 +2236,17 @@ static void dbsc_regset(void) ***********************************************************************/ /* SCFCTST0 */ /* SCFCTST0 ACT-ACT */ - tmp[3] = 1UL * js2[JS2_tRCpb] * 800 * ddr_mbpsdiv / ddr_mbps; + tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps; /* SCFCTST0 RDA-ACT */ tmp[2] = - 1UL * ((16 / 2) + js2[JS2_tRTP] - 8 + - js2[JS2_tRPpb]) * 800 * ddr_mbpsdiv / ddr_mbps; + 1UL * ((16 / 2) + js2[js2_trtp] - 8 + + js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps; /* SCFCTST0 WRA-ACT */ tmp[1] = 1UL * (WL + 1 + (16 / 2) + - js1[js1_ind].nWR) * 800 * ddr_mbpsdiv / ddr_mbps; + js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps; /* SCFCTST0 PRE-ACT */ - tmp[0] = 1UL * js2[JS2_tRPpb]; + tmp[0] = 1UL * js2[js2_trppb]; mmio_write_32(DBSC_SCFCTST0, (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); @@ -2261,7 +2260,7 @@ static void dbsc_regset(void) 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv / ddr_mbps; /* SCFCTST1 ACT-RD/WR */ - tmp[1] = 1UL * js2[JS2_tRCD] * 800 * ddr_mbpsdiv / ddr_mbps; + tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps; /* SCFCTST1 ASYNCOFS */ tmp[0] = 12; mmio_write_32(DBSC_SCFCTST1, @@ -2269,14 +2268,14 @@ static void dbsc_regset(void) /* DBSCHRW1 */ /* DBSCHRW1 SCTRFCAB */ - tmp[0] = 1UL * js2[JS2_tRFCab] * 800 * ddr_mbpsdiv / ddr_mbps; - dataL = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) + tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps; + data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; - if (tmp[0] < dataL) - tmp[0] = dataL; + if (tmp[0] < data_l) + tmp[0] = data_l; - if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { + if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { mmio_write_32(DBSC_DBSCHRW1, tmp[0] + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps - 3); @@ -2334,18 +2333,18 @@ static void dbsc_regset(void) mmio_write_32(QOSCTRL_RAEN, 0x00000001U); #endif /* ddr_qos_init_setting */ /* H3 Ver.1.1 need to set monitor function */ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { mmio_write_32(DBSC_DBMONCONF4, 0x00700000); } - if (Prr_Product == PRR_PRODUCT_H3) { - if (Prr_Cut == PRR_PRODUCT_10) { + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut == PRR_PRODUCT_10) { /* resrdis, simple mode, sc off */ mmio_write_32(DBSC_DBBCAMDIS, 0x00000007); - } else if (Prr_Cut == PRR_PRODUCT_11) { + } else if (prr_cut == PRR_PRODUCT_11) { /* resrdis, simple mode */ mmio_write_32(DBSC_DBBCAMDIS, 0x00000005); - } else if (Prr_Cut < PRR_PRODUCT_30) { + } else if (prr_cut < PRR_PRODUCT_30) { /* H3 Ver.2.0 */ /* resrdis */ mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); @@ -2362,7 +2361,7 @@ static void dbsc_regset(void) static void dbsc_regset_post(void) { uint32_t ch, cs; - uint32_t dataL; + uint32_t data_l; uint32_t slice, rdlat_max, rdlat_min; rdlat_max = 0; @@ -2374,18 +2373,18 @@ static void dbsc_regset_post(void) ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_LATENCY_ADJUST); - if (dataL > rdlat_max) - rdlat_max = dataL; - if (dataL < rdlat_min) - rdlat_min = dataL; + if (data_l > rdlat_max) + rdlat_max = data_l; + if (data_l < rdlat_min) + rdlat_min = data_l; } } } } - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) { mmio_write_32(DBSC_DBTR(24), ((rdlat_max * 2 - rdlat_min + 4) << 24) + ((rdlat_min + 2) << 16) + @@ -2415,24 +2414,24 @@ static void dbsc_regset_post(void) mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); /*set DBI */ - if (Boardcnf->dbi_en) + if (board_cnf->dbi_en) mmio_write_32(DBSC_DBDBICNT, 0x00000003); /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */ - if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en)) + if ((((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) && (board_cnf->dbi_en)) reg_ddrphy_write_a(0x00001010, 0x01000000); /*set REFCYCLE */ - dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; - mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff)); + data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; + mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff)); mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); #ifdef DDR_BACKUPMODE - if (ddrBackup == DRAM_BOOT_STATUS_WARM) { + if (ddr_backup == DRAM_BOOT_STATUS_WARM) { #ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */ - PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1); + DEBUG(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1); send_dbcmd(0x08040001); wait_dbcmd(); send_dbcmd(0x0A040001); @@ -2440,7 +2439,7 @@ static void dbsc_regset_post(void) send_dbcmd(0x04040010); wait_dbcmd(); - if (Prr_Product == PRR_PRODUCT_H3) { + if (prr_product == PRR_PRODUCT_H3) { send_dbcmd(0x08140001); wait_dbcmd(); send_dbcmd(0x0A140001); @@ -2462,8 +2461,8 @@ static void dbsc_regset_post(void) #if RCAR_REWT_TRAINING != 0 /* Periodic-WriteDQ Training seeting */ - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10))) { /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ } else { /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H -> Periodic-WriteDQ Training seeting */ @@ -2487,7 +2486,7 @@ static void dbsc_regset_post(void) ddr_setval_ach(_reg_PI_TREF_F1, 0x0000); ddr_setval_ach(_reg_PI_TREF_F2, 0x0000); - if (Prr_Product == PRR_PRODUCT_M3) { + if (prr_product == PRR_PRODUCT_M3) { ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02); } else { ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02); @@ -2500,13 +2499,13 @@ static void dbsc_regset_post(void) #endif /* RCAR_REWT_TRAINING */ /* periodic dram zqcal and phy ctrl update enable */ mmio_write_32(DBSC_DBCALCNF, 0x01000010); - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { #if RCAR_DRAM_SPLIT == 2 - if ((Prr_Product == PRR_PRODUCT_H3) - && (Boardcnf->phyvalid == 0x05)) + if ((prr_product == PRR_PRODUCT_H3) + && (board_cnf->phyvalid == 0x05)) mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); else mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); @@ -2531,10 +2530,10 @@ static uint32_t dfi_init_start(void) uint32_t ch; uint32_t phytrainingok; uint32_t retry; - uint32_t dataL; + uint32_t data_l; const uint32_t RETRY_MAX = 0x10000; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { /*********************************************************************** PLL3 Disable ***********************************************************************/ @@ -2584,8 +2583,8 @@ static uint32_t dfi_init_start(void) retry = 0; while (retry++ < RETRY_MAX) { foreach_vch(ch) { - dataL = mmio_read_32(DBSC_DBDFISTAT(ch)); - if (dataL & 0x00000001) + data_l = mmio_read_32(DBSC_DBDFISTAT(ch)); + if (data_l & 0x00000001) phytrainingok |= (1U << ch); } dsb_sev(); @@ -2621,7 +2620,7 @@ static void change_lpddr4_en(uint32_t mode) { uint32_t ch; uint32_t i; - uint32_t dataL; + uint32_t data_l; const uint32_t _reg_PHY_PAD_DRIVE_X[3] = { _reg_PHY_PAD_ADDR_DRIVE, _reg_PHY_PAD_CLK_DRIVE, @@ -2630,13 +2629,13 @@ static void change_lpddr4_en(uint32_t mode) foreach_vch(ch) { for (i = 0; i < 3; i++) { - dataL = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); + data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); if (mode) { - dataL |= (1U << 14); + data_l |= (1U << 14); } else { - dataL &= ~(1U << 14); + data_l &= ~(1U << 14); } - ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], dataL); + ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l); } } } @@ -2648,7 +2647,7 @@ static uint32_t set_term_code(void) { int32_t i; uint32_t ch, index; - uint32_t dataL; + uint32_t data_l; uint32_t chip_id[2]; uint32_t term_code; uint32_t override; @@ -2664,12 +2663,12 @@ static uint32_t set_term_code(void) index = 0; while (1) { - if (TermcodeBySample[index][0] == 0xffffffff) { + if (termcode_by_sample[index][0] == 0xffffffff) { break; } - if ((TermcodeBySample[index][0] == chip_id[0]) - && (TermcodeBySample[index][1] == chip_id[1])) { - term_code = TermcodeBySample[index][2]; + if ((termcode_by_sample[index][0] == chip_id[0]) + && (termcode_by_sample[index][1] == chip_id[1])) { + term_code = termcode_by_sample[index][2]; override = 1; break; } @@ -2678,14 +2677,14 @@ static uint32_t set_term_code(void) if (override) { for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { - dataL = + data_l = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_TERM_X[index]); - dataL = (dataL & 0xfffe0000) | term_code; - ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], dataL); + data_l = (data_l & 0xfffe0000) | term_code; + ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l); } - } else if ((Prr_Product == PRR_PRODUCT_M3) - && (Prr_Cut == PRR_PRODUCT_10)) { + } else if ((prr_product == PRR_PRODUCT_M3) + && (prr_cut == PRR_PRODUCT_10)) { /* non */ } else { ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], @@ -2696,55 +2695,55 @@ static uint32_t set_term_code(void) ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01); foreach_vch(ch) { do { - dataL = + data_l = ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); - } while (!(dataL & 0x00800000)); + } while (!(data_l & 0x00800000)); } - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { - dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); - pvtr = (dataL >> 12) & 0x1f; + data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); + pvtr = (data_l >> 12) & 0x1f; pvtr += 8; if (pvtr > 0x1f) pvtr = 0x1f; - dataL = + data_l = ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); - pvtn = (dataL >> 6) & 0x03f; - pvtp = (dataL >> 0) & 0x03f; + pvtn = (data_l >> 6) & 0x03f; + pvtp = (data_l >> 0) & 0x03f; for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { - dataL = + data_l = ddrtbl_getval (_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_TERM_X[index]); - dataL = (dataL & 0xfffe0000) + data_l = (data_l & 0xfffe0000) | (pvtr << 12) | (pvtn << 6) | (pvtp); ddr_setval(ch, _reg_PHY_PAD_TERM_X[index], - dataL); + data_l); } } } else { /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ foreach_vch(ch) { for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { - dataL = + data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X [index]); ddr_setval(ch, _reg_PHY_PAD_TERM_X[index], - (dataL & 0xFFFE0FFF) | + (data_l & 0xFFFE0FFF) | 0x00015000); } } } } - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { /* non */ } else { ddr_padcal_tcompensate_getinit(override); @@ -2766,32 +2765,32 @@ static void ddr_register_set(void) tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr1_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840100 | tmp); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr2_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840200 | tmp); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr3_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840300 | tmp); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr11_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840b00 | tmp); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr12_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840c00 | tmp); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr14_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840e00 | tmp); /* MR22 */ send_dbcmd(0x0e841616); @@ -2803,33 +2802,33 @@ static void ddr_register_set(void) ******************************************************************************/ static inline uint32_t wait_freqchgreq(uint32_t assert) { - uint32_t dataL; + uint32_t data_l; uint32_t count; uint32_t ch; count = 100000; /* H3 Ver.1.x cannot see frqchg_req */ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { return 0; } if (assert) { do { - dataL = 1; + data_l = 1; foreach_vch(ch) { - dataL &= mmio_read_32(DBSC_DBPDSTAT(ch)); + data_l &= mmio_read_32(DBSC_DBPDSTAT(ch)); } count = count - 1; - } while (((dataL & 0x01) != 0x01) & (count != 0)); + } while (((data_l & 0x01) != 0x01) & (count != 0)); } else { do { - dataL = 0; + data_l = 0; foreach_vch(ch) { - dataL |= mmio_read_32(DBSC_DBPDSTAT(ch)); + data_l |= mmio_read_32(DBSC_DBPDSTAT(ch)); } count = count - 1; - } while (((dataL & 0x01) != 0x00) & (count != 0)); + } while (((data_l & 0x01) != 0x00) & (count != 0)); } return (count == 0); @@ -2838,22 +2837,22 @@ static inline uint32_t wait_freqchgreq(uint32_t assert) static inline void set_freqchgack(uint32_t assert) { uint32_t ch; - uint32_t dataL; + uint32_t data_l; if (assert) - dataL = 0x0CF20000; + data_l = 0x0CF20000; else - dataL = 0x00000000; + data_l = 0x00000000; foreach_vch(ch) - mmio_write_32(DBSC_DBPDCNT2(ch), dataL); + mmio_write_32(DBSC_DBPDCNT2(ch), data_l); } static inline void set_dfifrequency(uint32_t freq) { uint32_t ch; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq); } else { @@ -2904,7 +2903,7 @@ static void update_dly(void) static uint32_t pi_training_go(void) { uint32_t flag; - uint32_t dataL; + uint32_t data_l; uint32_t retry; const uint32_t RETRY_MAX = 4096 * 16; uint32_t ch; @@ -2939,8 +2938,8 @@ static uint32_t pi_training_go(void) frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; /* H3 Ver.1.x cannot see frqchg_req */ - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { if ((retry % 4096) == 1) { frqchg_req = 1; } else { @@ -2965,9 +2964,9 @@ static uint32_t pi_training_go(void) foreach_vch(ch) { if (complete & (1U << ch)) continue; - dataL = + data_l = ddr_getval(ch, _reg_PI_INT_STATUS); - if (dataL & 0x01) { + if (data_l & 0x01) { complete |= (1U << ch); } } @@ -2978,9 +2977,9 @@ static uint32_t pi_training_go(void) } while (--retry); foreach_vch(ch) { /* dummy read */ - dataL = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); - dataL = ddr_getval(ch, _reg_PI_INT_STATUS); - ddr_setval(ch, _reg_PI_INT_ACK, dataL); + data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); + data_l = ddr_getval(ch, _reg_PI_INT_STATUS); + ddr_setval(ch, _reg_PI_INT_ACK, data_l); } if (ddrphy_regif_chk()) { return (0xfd); @@ -2994,7 +2993,7 @@ static uint32_t pi_training_go(void) static uint32_t init_ddr(void) { int32_t i; - uint32_t dataL; + uint32_t data_l; uint32_t phytrainingok; uint32_t ch, slice; uint32_t err; @@ -3003,7 +3002,7 @@ static uint32_t init_ddr(void) MSG_LF("init_ddr:0\n"); #ifdef DDR_BACKUPMODE - rcar_dram_get_boot_status(&ddrBackup); + rcar_dram_get_boot_status(&ddr_backup); #endif /*********************************************************************** @@ -3014,9 +3013,9 @@ static uint32_t init_ddr(void) mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); dsb_sev(); - if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en)) + if ((((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) && (board_cnf->dbi_en)) reg_ddrphy_write_a(0x00001010, 0x01000001); else reg_ddrphy_write_a(0x00001010, 0x00000001); @@ -3069,12 +3068,12 @@ static uint32_t init_ddr(void) ddr backupmode end ***********************************************************************/ #ifdef DDR_BACKUPMODE - if (ddrBackup) { + if (ddr_backup) { NOTICE("BL2: [WARM_BOOT]\n"); } else { NOTICE("BL2: [COLD_BOOT]\n"); } - err = rcar_dram_update_boot_status(ddrBackup); + err = rcar_dram_update_boot_status(ddr_backup); if (err) { NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); return INITDRAM_ERR_I; @@ -3094,8 +3093,8 @@ static uint32_t init_ddr(void) /*********************************************************************** rx offset calibration ***********************************************************************/ - if ((Prr_Cut > PRR_PRODUCT_11) || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { err = rx_offset_cal_hw(); } else { err = rx_offset_cal(); @@ -3139,8 +3138,8 @@ static uint32_t init_ddr(void) Thermal sensor setting ***********************************************************************/ /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ - dataL = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; - mmio_write_32(THS1_THCTR, dataL); + data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; + mmio_write_32(THS1_THCTR, data_l); /* LPDDR4 MODE */ change_lpddr4_en(1); @@ -3151,10 +3150,10 @@ static uint32_t init_ddr(void) mask CS_MAP if RANKx is not found ***********************************************************************/ foreach_vch(ch) { - dataL = ddr_getval(ch, _reg_PI_CS_MAP); + data_l = ddr_getval(ch, _reg_PI_CS_MAP); if (!(ch_have_this_cs[1] & (1U << ch))) - dataL = dataL & 0x05; - ddr_setval(ch, _reg_PI_CS_MAP, dataL); + data_l = data_l & 0x05; + ddr_setval(ch, _reg_PI_CS_MAP, data_l); } /*********************************************************************** @@ -3164,7 +3163,7 @@ static uint32_t init_ddr(void) BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); } else { foreach_vch(ch) { @@ -3188,19 +3187,19 @@ static uint32_t init_ddr(void) /*********************************************************************** CACS DLY ADJUST ***********************************************************************/ - dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); + data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); foreach_vch(ch) { for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj); + data_l + adj); } if (ddr_phycaslice == 1) { for (i = 0; i < 6; i++) { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); ddr_setval_s(ch, 2, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj + data_l + adj ); } } @@ -3212,7 +3211,7 @@ static uint32_t init_ddr(void) /*********************************************************************** H3 fix rd latency to avoid bug in elasitic buffe ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { adjust_rddqs_latency(); } @@ -3255,9 +3254,9 @@ static uint32_t init_ddr(void) /*********************************************************************** training complete, setup dbsc ***********************************************************************/ - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); } @@ -3274,7 +3273,7 @@ static uint32_t init_ddr(void) static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) { uint32_t ch; - uint32_t dataL; + uint32_t data_l; uint32_t retry; uint32_t waiting; uint32_t err; @@ -3303,8 +3302,8 @@ static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) foreach_vch(ch) { if (!(waiting & (1U << ch))) continue; - dataL = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); - if (dataL & 0x01) + data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); + if (data_l & 0x01) waiting &= ~(1U << ch); } retry--; @@ -3329,15 +3328,15 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) { int32_t i, k; uint32_t cs, slice; - uint32_t dataL; + uint32_t data_l; /*********************************************************************** clr of training results buffer ***********************************************************************/ cs = ddr_csn % 2; - dataL = Boardcnf->dqdm_dly_w; + data_l = board_cnf->dqdm_dly_w; for (slice = 0; slice < SLICE_CNT; slice++) { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) continue; @@ -3346,7 +3345,7 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) wdqdm_dly[ch][cs][slice][i] = wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; else - wdqdm_dly[ch][cs][slice][i] = dataL; + wdqdm_dly[ch][cs][slice][i] = data_l; wdqdm_le[ch][cs][slice][i] = 0; wdqdm_te[ch][cs][slice][i] = 0; } @@ -3359,7 +3358,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) { int32_t i, k; uint32_t cs, slice; - uint32_t dataL; + uint32_t data_l; uint32_t err; const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0; @@ -3374,7 +3373,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) ***********************************************************************/ err = 0; for (slice = 0; slice < SLICE_CNT; slice += 1) { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) continue; @@ -3383,44 +3382,44 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) for (i = 0; i < 9; i++) { dq = slice * 8 + i; if (i == 8) - _adj = Boardcnf->ch[ch].dm_adj_w[slice]; + _adj = board_cnf->ch[ch].dm_adj_w[slice]; else - _adj = Boardcnf->ch[ch].dq_adj_w[dq]; + _adj = board_cnf->ch[ch].dq_adj_w[dq]; adj = _f_scale_adj(_adj); - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj; ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], - dataL); - wdqdm_dly[ch][cs][slice][i] = dataL; + data_l); + wdqdm_dly[ch][cs][slice][i] = data_l; } ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); - dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); - wdqdm_st[ch][cs][slice] = dataL; + data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); + wdqdm_st[ch][cs][slice] = data_l; min_win = INT_LEAST32_MAX; for (i = 0; i <= 8; i++) { ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT, i); - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS); - wdqdm_te[ch][cs][slice][i] = dataL; - dataL = + wdqdm_te[ch][cs][slice][i] = data_l; + data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); - wdqdm_le[ch][cs][slice][i] = dataL; + wdqdm_le[ch][cs][slice][i] = data_l; win = (int32_t)wdqdm_te[ch][cs][slice][i] - wdqdm_le[ch][cs][slice][i]; if (min_win > win) min_win = win; - if (dataL >= _par_WDQLVL_RETRY_THRES) + if (data_l >= _par_WDQLVL_RETRY_THRES) err = 2; } wdqdm_win[ch][cs][slice] = min_win; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01); } else { ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, @@ -3474,7 +3473,7 @@ static uint32_t wdqdm_man1(void) int32_t k; uint32_t ch, cs, slice; uint32_t ddr_csn; - uint32_t dataL; + uint32_t data_l; uint32_t err; uint32_t high_dq[DRAM_CH_CNT]; uint32_t mr14_csab0_bak[DRAM_CH_CNT]; @@ -3485,11 +3484,11 @@ static uint32_t wdqdm_man1(void) /*********************************************************************** manual execution of training ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { high_dq[ch] = 0; for (slice = 0; slice < SLICE_CNT; slice++) { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (k >= 2) high_dq[ch] |= (1U << slice); } @@ -3500,10 +3499,10 @@ static uint32_t wdqdm_man1(void) /* CLEAR PREV RESULT */ for (cs = 0; cs < CS_CNT; cs++) { ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); - if (((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01); } else { @@ -3517,33 +3516,33 @@ static uint32_t wdqdm_man1(void) err_flg = 0; #endif/* DDR_FAST_INIT */ for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { - dataL = mmio_read_32(DBSC_DBDFICNT(ch)); - dataL &= ~(0x00ffU << 16); + data_l = mmio_read_32(DBSC_DBDFICNT(ch)); + data_l &= ~(0x00ffU << 16); if (ddr_csn >= 2) k = (high_dq[ch] ^ 0x0f); else k = high_dq[ch]; - dataL |= (k << 16); - mmio_write_32(DBSC_DBDFICNT(ch), dataL); + data_l |= (k << 16); + mmio_write_32(DBSC_DBDFICNT(ch), data_l); ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k); } } - if (((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) - && (Prr_Cut == PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) + && (prr_cut == PRR_PRODUCT_10))) { wdqdm_cp(ddr_csn, 0); } foreach_vch(ch) { - dataL = + data_l = ddr_getval(ch, - _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn]); - ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], dataL); + reg_pi_mr14_data_fx_csx[1][ddr_csn]); + ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l); } /* KICK WDQLVL */ @@ -3554,10 +3553,10 @@ static uint32_t wdqdm_man1(void) if (ddr_csn == 0) foreach_vch(ch) { mr14_csab0_bak[ch] = - ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0]); + ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]); } else foreach_vch(ch) { - ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], + ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], mr14_csab0_bak[ch]); } #ifndef DDR_FAST_INIT @@ -3577,12 +3576,12 @@ err_exit: #ifndef DDR_FAST_INIT err |= err_flg; #endif/* DDR_FAST_INIT */ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01); foreach_vch(ch) { - dataL = mmio_read_32(DBSC_DBDFICNT(ch)); - dataL &= ~(0x00ffU << 16); - mmio_write_32(DBSC_DBDFICNT(ch), dataL); + data_l = mmio_read_32(DBSC_DBDFICNT(ch)); + data_l &= ~(0x00ffU << 16); + mmio_write_32(DBSC_DBDFICNT(ch), data_l); ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00); } } @@ -3596,9 +3595,9 @@ static uint32_t wdqdm_man(void) uint32_t ch, ddr_csn, mr14_bkup[4][4]; ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12); - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, (DBSC_DBTR(12) & 0xFF) + 1); } else { @@ -3610,15 +3609,15 @@ static uint32_t wdqdm_man(void) retry_cnt = 0; err = 0; do { - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { err = wdqdm_man1(); } else { ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x01); - if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x0C); } else { @@ -3630,14 +3629,14 @@ static uint32_t wdqdm_man(void) for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { mr14_bkup[ch][ddr_csn] = ddr_getval(ch, - _reg_PI_MR14_DATA_Fx_CSx + reg_pi_mr14_data_fx_csx [1][ddr_csn]); dsb_sev(); } } - if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x04); } else { @@ -3650,10 +3649,10 @@ static uint32_t wdqdm_man(void) mr14_bkup[ch][ddr_csn] = (mr14_bkup[ch][ddr_csn] + ddr_getval(ch, - _reg_PI_MR14_DATA_Fx_CSx + reg_pi_mr14_data_fx_csx [1][ddr_csn])) / 2; ddr_setval(ch, - _reg_PI_MR14_DATA_Fx_CSx[1] + reg_pi_mr14_data_fx_csx[1] [ddr_csn], mr14_bkup[ch][ddr_csn]); } @@ -3661,8 +3660,8 @@ static uint32_t wdqdm_man(void) ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x00); - if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x00); ddr_setval_ach @@ -3689,8 +3688,8 @@ static uint32_t wdqdm_man(void) } } while (err && (++retry_cnt < retry_max)); - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) { wdqdm_cp(0, 1); } @@ -3705,15 +3704,15 @@ static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) { int32_t i, k; uint32_t cs, slice; - uint32_t dataL; + uint32_t data_l; /*********************************************************************** clr of training results buffer ***********************************************************************/ cs = ddr_csn % 2; - dataL = Boardcnf->dqdm_dly_r; + data_l = board_cnf->dqdm_dly_r; for (slice = 0; slice < SLICE_CNT; slice++) { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) continue; @@ -3726,8 +3725,8 @@ static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) SLICE_CNT] [i]; } else { - rdqdm_dly[ch][cs][slice][i] = dataL; - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL; + rdqdm_dly[ch][cs][slice][i] = data_l; + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l; } rdqdm_le[ch][cs][slice][i] = 0; rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; @@ -3745,7 +3744,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) { int32_t i, k; uint32_t cs, slice; - uint32_t dataL; + uint32_t data_l; uint32_t err; int8_t _adj; int16_t adj; @@ -3759,7 +3758,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) ***********************************************************************/ err = 0; for (slice = 0; slice < SLICE_CNT; slice++) { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) continue; @@ -3773,36 +3772,36 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) for (i = 0; i <= 8; i++) { dq = slice * 8 + i; if (i == 8) - _adj = Boardcnf->ch[ch].dm_adj_r[slice]; + _adj = board_cnf->ch[ch].dm_adj_r[slice]; else - _adj = Boardcnf->ch[ch].dq_adj_r[dq]; + _adj = board_cnf->ch[ch].dq_adj_r[dq]; adj = _f_scale_adj(_adj); - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], - dataL); - rdqdm_dly[ch][cs][slice][i] = dataL; + data_l); + rdqdm_dly[ch][cs][slice][i] = data_l; - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], - dataL); - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL; + data_l); + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l; } min_win = INT_LEAST32_MAX; for (i = 0; i <= 8; i++) { - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS); - rdqdm_st[ch][cs][slice] = dataL; - rdqdm_st[ch][cs][slice + SLICE_CNT] = dataL; + rdqdm_st[ch][cs][slice] = data_l; + rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l; /* k : rise/fall */ for (k = 0; k < 2; k++) { if (i == 8) { @@ -3814,23 +3813,23 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT, rdq_status_obs_select); - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = - dataL; + data_l; - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = - dataL; + data_l; - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS); rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = - dataL; + data_l; win = (int32_t)rdqdm_te[ch][cs][slice + @@ -3858,7 +3857,7 @@ static uint32_t rdqdm_man1(void) uint32_t ddr_csn; #ifdef DDR_FAST_INIT uint32_t slice; - uint32_t i, adj, dataL; + uint32_t i, adj, data_l; #endif/* DDR_FAST_INIT */ uint32_t err; @@ -3897,26 +3896,26 @@ static uint32_t rdqdm_man1(void) } } } - if (((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) - && (Prr_Cut <= PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) + && (prr_cut <= PRR_PRODUCT_10))) { for (slice = 0; slice < SLICE_CNT; slice++) { for (i = 0; i <= 8; i++) { if (i == 8) - adj = _f_scale_adj(Boardcnf->ch[ch].dm_adj_r[slice]); + adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]); else - adj = _f_scale_adj(Boardcnf->ch[ch].dq_adj_r[slice * 8 + i]); + adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]); ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn); - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], dataL); - rdqdm_dly[ch][ddr_csn][slice][i] = dataL; - rdqdm_dly[ch][ddr_csn | 1][slice][i] = dataL; - - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], dataL); - rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = dataL; - rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = dataL; + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l); + rdqdm_dly[ch][ddr_csn][slice][i] = data_l; + rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l; + + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l); + rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l; + rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l; } } } @@ -4003,7 +4002,7 @@ static uint32_t _rx_offset_cal_updn(uint32_t code) const uint32_t CODE_MAX = 0x40; uint32_t tmp; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { if (code == 0) tmp = (1U << 6) | (CODE_MAX - 1); else if (code <= 0x20) @@ -4117,10 +4116,10 @@ static uint32_t rx_offset_cal_hw(void) for (slice = 0; slice < SLICE_CNT; slice++) { tmp = tmp_ach_as[ch][slice]; tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); - if (((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { if (tmp != 0x3E) complete = 0; } else { @@ -4222,60 +4221,61 @@ static void adjust_wpath_latency(void) int32_t rcar_dram_init(void) { uint32_t ch, cs; - uint32_t dataL; + uint32_t data_l; uint32_t bus_mbps, bus_mbpsdiv; uint32_t tmp_tccd; uint32_t failcount; + uint32_t cnf_boardtype; /*********************************************************************** Thermal sensor setting ***********************************************************************/ - dataL = mmio_read_32(CPG_MSTPSR5); - if (dataL & BIT(22)) { /* case THS/TSC Standby */ - dataL &= ~(BIT(22)); - cpg_write_32(CPG_SMSTPCR5, dataL); + data_l = mmio_read_32(CPG_MSTPSR5); + if (data_l & BIT(22)) { /* case THS/TSC Standby */ + data_l &= ~(BIT(22)); + cpg_write_32(CPG_SMSTPCR5, data_l); while ((BIT(22)) & mmio_read_32(CPG_MSTPSR5)); /* wait bit=0 */ } /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ - dataL = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; - mmio_write_32(THS1_THCTR, dataL); + data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; + mmio_write_32(THS1_THCTR, data_l); /*********************************************************************** Judge product and cut ***********************************************************************/ #ifdef RCAR_DDR_FIXED_LSI_TYPE #if (RCAR_LSI == RCAR_AUTO) - Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; - Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; + prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; #else /* RCAR_LSI */ #ifndef RCAR_LSI_CUT - Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; + prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; #endif /* RCAR_LSI_CUT */ #endif /* RCAR_LSI */ #else /* RCAR_DDR_FIXED_LSI_TYPE */ - Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; - Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; + prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; #endif /* RCAR_DDR_FIXED_LSI_TYPE */ - if (Prr_Product == PRR_PRODUCT_H3) { - if (Prr_Cut <= PRR_PRODUCT_11) { - pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[0][0]; + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { + p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[0][0]; } else { - pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[2][0]; + p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[2][0]; } - } else if (Prr_Product == PRR_PRODUCT_M3) { - pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[1][0]; - } else if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { - pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[3][0]; + } else if (prr_product == PRR_PRODUCT_M3) { + p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[1][0]; + } else if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { + p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[3][0]; } else { FATAL_MSG("BL2: DDR:Unknown Product\n"); return 0xff; } - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); @@ -4284,26 +4284,26 @@ int32_t rcar_dram_init(void) /*********************************************************************** Judge board type ***********************************************************************/ - _cnf_BOARDTYPE = boardcnf_get_brd_type(); - if (_cnf_BOARDTYPE >= BOARDNUM) { + cnf_boardtype = boardcnf_get_brd_type(); + if (cnf_boardtype >= BOARDNUM) { FATAL_MSG("BL2: DDR:Unknown Board\n"); return 0xff; } - Boardcnf = (const struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE]; + board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype]; /* RCAR_DRAM_SPLIT_2CH (2U) */ #if RCAR_DRAM_SPLIT == 2 /*********************************************************************** H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Boardcnf->phyvalid == 0x05)) { + if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) { mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); ddr_phyvalid = 0x03; } else { - ddr_phyvalid = Boardcnf->phyvalid; + ddr_phyvalid = board_cnf->phyvalid; } #else /* RCAR_DRAM_SPLIT_2CH */ - ddr_phyvalid = Boardcnf->phyvalid; + ddr_phyvalid = board_cnf->phyvalid; #endif /* RCAR_DRAM_SPLIT_2CH */ max_density = 0; @@ -4318,15 +4318,15 @@ int32_t rcar_dram_init(void) foreach_vch(ch) { for (cs = 0; cs < CS_CNT; cs++) { - dataL = Boardcnf->ch[ch].ddr_density[cs]; - ddr_density[ch][cs] = dataL; + data_l = board_cnf->ch[ch].ddr_density[cs]; + ddr_density[ch][cs] = data_l; - if (dataL == 0xff) + if (data_l == 0xff) continue; - if (dataL > max_density) - max_density = dataL; - if ((cs == 1) && (Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) + if (data_l > max_density) + max_density = data_l; + if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) continue; ch_have_this_cs[cs] |= (1U << ch); } @@ -4335,7 +4335,7 @@ int32_t rcar_dram_init(void) /*********************************************************************** Judge board clock frequency (in MHz) ***********************************************************************/ - boardcnf_get_brd_clk(_cnf_BOARDTYPE, &brd_clk, &brd_clkdiv); + boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv); if ((brd_clk / brd_clkdiv) > 25) { brd_clkdiva = 1; } else { @@ -4345,7 +4345,7 @@ int32_t rcar_dram_init(void) /*********************************************************************** Judge ddr operating frequency clock(in Mbps) ***********************************************************************/ - boardcnf_get_ddr_mbps(_cnf_BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv); + boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv); ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); @@ -4355,10 +4355,10 @@ int32_t rcar_dram_init(void) /*********************************************************************** Adjust tccd ***********************************************************************/ - dataL = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; + data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; bus_mbps = 0; bus_mbpsdiv = 0; - switch (dataL) { + switch (data_l) { case 0: bus_mbps = brd_clk * 0x60 * 2; bus_mbpsdiv = brd_clkdiv * 1; @@ -4401,8 +4401,8 @@ int32_t rcar_dram_init(void) /*********************************************************************** initialize DDR ***********************************************************************/ - dataL = init_ddr(); - if (dataL == ddr_phyvalid) { + data_l = init_ddr(); + if (data_l == ddr_phyvalid) { failcount = 0; } else { failcount = 1; @@ -4410,8 +4410,8 @@ int32_t rcar_dram_init(void) foreach_vch(ch) mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); @@ -4427,7 +4427,7 @@ int32_t rcar_dram_init(void) void pvtcode_update(void) { uint32_t ch; - uint32_t dataL; + uint32_t data_l; uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init; int32_t pvtp_tmp, pvtn_tmp; @@ -4453,41 +4453,41 @@ void pvtcode_update(void) pvtn_init) / (pvtn_tmp) + 6 * pvtp_tmp + pvtp_init; } - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { - dataL = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000); + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { + data_l = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), - dataL | 0x00020000); + data_l | 0x00020000); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), - dataL); + data_l); } else { - dataL = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000; + data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000; reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), - dataL | 0x00020000); + data_l | 0x00020000); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), - dataL); + data_l); } } } @@ -4513,7 +4513,7 @@ void pvtcode_update2(void) void ddr_padcal_tcompensate_getinit(uint32_t override) { uint32_t ch; - uint32_t dataL; + uint32_t data_l; uint32_t pvtp, pvtn; tcal.init_temp = 0; @@ -4528,13 +4528,13 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) } if (!override) { - dataL = mmio_read_32(THS1_TEMP); - if (dataL < 2800) { + data_l = mmio_read_32(THS1_TEMP); + if (data_l < 2800) { tcal.init_temp = - (143 * (int32_t)dataL - 359000) / 1000; + (143 * (int32_t)data_l - 359000) / 1000; } else { tcal.init_temp = - (121 * (int32_t)dataL - 296300) / 1000; + (121 * (int32_t)data_l - 296300) / 1000; } foreach_vch(ch) { @@ -4556,8 +4556,8 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) else pvtn = 0; - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { tcal.init_cal[ch] = (tcal. init_cal[ch] & 0xfffff000) | (pvtn << 6) | diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index 58c9a7a4f..cb3a482eb 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -1533,7 +1533,7 @@ void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) { uint32_t md; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_10)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_10)) { *clk = 50; *div = 3; } else { @@ -1599,7 +1599,7 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) #define M3_SAMPLE_SS_E28 0xB866CC10, 0x3C231421 #define M3_SAMPLE_SS_E32 0xB866CC10, 0x3C241421 -static const uint32_t TermcodeBySample[20][3] = { +static const uint32_t termcode_by_sample[20][3] = { {M3_SAMPLE_TT_A84, 0x000158D5}, {M3_SAMPLE_TT_A85, 0x00015955}, {M3_SAMPLE_TT_A86, 0x00015955}, @@ -1701,8 +1701,8 @@ static uint32_t _board_judge(void) uint32_t brd; #if (RCAR_GEN3_ULCB == 1) /* Starter Kit */ - if (Prr_Product == PRR_PRODUCT_H3) { - if (Prr_Cut <= PRR_PRODUCT_11) { + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { /* RENESAS Starter Kit(H3 Ver.1.x/SIP) board */ brd = 2; } else { @@ -1713,7 +1713,7 @@ static uint32_t _board_judge(void) brd = 8; #endif } - } else if (Prr_Product == PRR_PRODUCT_M3) { + } else if (prr_product == PRR_PRODUCT_M3) { /* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */ brd = 3; } else { @@ -1727,31 +1727,31 @@ static uint32_t _board_judge(void) /* RENESAS Eva-board */ brd = 99; - if (Prr_Product == PRR_PRODUCT_V3H) { + if (prr_product == PRR_PRODUCT_V3H) { /* RENESAS Condor board */ brd = 12; } else if (usb2_ovc_open) { - if (Prr_Product == PRR_PRODUCT_M3N) { + if (prr_product == PRR_PRODUCT_M3N) { /* RENESAS Kriek board with M3-N */ brd = 10; - } else if (Prr_Product == PRR_PRODUCT_M3) { + } else if (prr_product == PRR_PRODUCT_M3) { /* RENESAS Kriek board with M3-W */ brd = 1; - } else if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + } else if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { /* RENESAS Kriek board with PM3 */ brd = 13; - } else if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_20)) { + } else if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_20)) { /* RENESAS Kriek board with H3N */ brd = 15; } } else { - if (Prr_Product == PRR_PRODUCT_H3) { - if (Prr_Cut <= PRR_PRODUCT_11) { + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { /* RENESAS SALVATOR-X (H3 Ver.1.x/SIP) */ brd = 2; - } else if (Prr_Cut < PRR_PRODUCT_30) { + } else if (prr_cut < PRR_PRODUCT_30) { /* RENESAS SALVATOR-X (H3 Ver.2.0/SIP) */ brd = 7; // 8Gbit/1rank } else { @@ -1762,16 +1762,16 @@ static uint32_t _board_judge(void) brd = 8; #endif } - } else if (Prr_Product == PRR_PRODUCT_M3N) { + } else if (prr_product == PRR_PRODUCT_M3N) { /* RENESAS SALVATOR-X (M3-N/SIP) */ brd = 11; - } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20)) { + } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_20)) { /* RENESAS SALVATOR-X (M3-W/SIP) */ brd = 0; - } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { + } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { /* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */ brd = 19; - } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) { + } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut >= PRR_PRODUCT_30)) { /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */ brd = 18; } -- cgit v1.2.3 From 087561475e17afca1884afa729c3c88384453afc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 7 Aug 2019 19:56:09 +0200 Subject: rcar_gen3: drivers: ddr_b: Further checkpatch cleanups Address more checkpatch CHECKs and ERRORs, no functional change. Signed-off-by: Marek Vasut Change-Id: Ife682288cef3afa860571b2aca647c9ffe936125 --- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 752 ++++++++------------- .../renesas/rcar/ddr/ddr_b/boot_init_dram_config.c | 19 +- 2 files changed, 291 insertions(+), 480 deletions(-) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index 244caf6e5..d10687296 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -25,9 +25,7 @@ #define DDR_BACKUPMODE #define FATAL_MSG(x) NOTICE(x) -/******************************************************************************* - * variables - ******************************************************************************/ +/* variables */ #ifdef RCAR_DDR_FIXED_LSI_TYPE #ifndef RCAR_AUTO #define RCAR_AUTO 99 @@ -90,7 +88,7 @@ static uint32_t ddr_phycaslice; static const struct _boardcnf *board_cnf; static uint32_t ddr_phyvalid; static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; -static uint32_t ch_have_this_cs[CS_CNT] __attribute__ ((aligned(64))); +static uint32_t ch_have_this_cs[CS_CNT] __aligned(64); static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; static uint32_t max_density; static uint32_t ddr0800_mul; @@ -129,7 +127,9 @@ uint32_t ddr_backup; #define OPERATING_FREQ (400U) /* Mhz */ #define BASE_SUB_SLOT_NUM (0x6U) #define SUB_SLOT_CYCLE (0x7EU) /* 126 */ -#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) /* unit:ns */ +#define QOSWT_WTSET0_CYCLE \ + ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \ + OPERATING_FREQ) /* unit:ns */ uint32_t get_refperiod(void) { @@ -155,8 +155,7 @@ static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { }; #define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 -static const uint32_t - _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, @@ -170,8 +169,7 @@ static const uint32_t }; #define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 -static const uint32_t - _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, @@ -184,8 +182,7 @@ static const uint32_t }; #define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 -static const uint32_t - _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, @@ -210,8 +207,7 @@ static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { }; #define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 -static const uint32_t - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { +static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, @@ -225,9 +221,7 @@ static const uint32_t _reg_PHY_GRP_SLAVE_DELAY_3 }; -/******************************************************************************* - * Prototypes - ******************************************************************************/ +/* Prototypes */ static inline uint32_t vch_nxt(uint32_t pos); static void cpg_write_32(uint32_t a, uint32_t v); static void pll3_control(uint32_t high); @@ -292,9 +286,9 @@ static void adjust_rddqs_latency(void); static void adjust_wpath_latency(void); struct ddrt_data { - int32_t init_temp; /* Initial Temperature (do) */ - uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ - uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */ + int32_t init_temp; /* Initial Temperature (do) */ + uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ + uint32_t tcomp_cal[4]; /* Temp. compensated io-code (4 is for H3) */ }; static struct ddrt_data tcal; @@ -303,9 +297,7 @@ static void pvtcode_update(void); static void pvtcode_update2(void); static void ddr_padcal_tcompensate_getinit(uint32_t override); -/******************************************************************************* - * load board configuration - ******************************************************************************/ +/* load board configuration */ #include "boot_init_dram_config.c" #ifndef DDR_FAST_INIT @@ -326,9 +318,7 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn); static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn); #endif/* DDR_FAST_INIT */ -/******************************************************************************* - * macro for channel selection loop - ******************************************************************************/ +/* macro for channel selection loop */ static inline uint32_t vch_nxt(uint32_t pos) { uint32_t posn; @@ -346,14 +336,10 @@ for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1)) #define foreach_ech(ch) \ for (ch = 0; ch < DRAM_CH_CNT; ch++) -/******************************************************************************* - * Printing functions - ******************************************************************************/ +/* Printing functions */ #define MSG_LF(...) -/******************************************************************************* - * clock settings, reset control - ******************************************************************************/ +/* clock settings, reset control */ static void cpg_write_32(uint32_t a, uint32_t v) { mmio_write_32(CPG_CPGWPR, ~v); @@ -443,7 +429,8 @@ static void pll3_control(uint32_t high) dsb_sev(); /* PLL3 DIV resetting(Target value) */ - data_l = (data_div << 16) | data_div | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + data_l = (data_div << 16) | data_div | + (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); cpg_write_32(CPG_FRQCRD, data_l); dsb_sev(); @@ -469,7 +456,8 @@ static void pll3_control(uint32_t high) dsb_sev(); /* PLL3 DIV set(Target value) */ - data_l = (data_div << 16) | data_div | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + data_l = (data_div << 16) | data_div | + (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); cpg_write_32(CPG_FRQCRD, data_l); /* DIV SET KICK */ @@ -489,17 +477,13 @@ static void pll3_control(uint32_t high) } } -/******************************************************************************* - * barrier - ******************************************************************************/ +/* barrier */ static inline void dsb_sev(void) { __asm__ __volatile__("dsb sy"); } -/******************************************************************************* - * DDR memory register access - ******************************************************************************/ +/* DDR memory register access */ static void wait_dbcmd(void) { uint32_t data_l; @@ -523,17 +507,15 @@ static void send_dbcmd(uint32_t cmd) dsb_sev(); } -/******************************************************************************* - * DDRPHY register access (raw) - ******************************************************************************/ +/* DDRPHY register access (raw) */ static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) { uint32_t val; uint32_t loop; val = 0; - if ((prr_product != PRR_PRODUCT_M3N) - && (prr_product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) && + (prr_product != PRR_PRODUCT_V3H)) { mmio_write_32(DBSC_DBPDRGA(phyno), regadd); dsb_sev(); @@ -579,8 +561,8 @@ static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) uint32_t val; uint32_t loop; - if ((prr_product != PRR_PRODUCT_M3N) - && (prr_product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) && + (prr_product != PRR_PRODUCT_V3H)) { mmio_write_32(DBSC_DBPDRGA(phyno), regadd); dsb_sev(); for (loop = 0; loop < loop_max; loop++) { @@ -628,8 +610,8 @@ static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) uint32_t val; uint32_t loop; - if ((prr_product != PRR_PRODUCT_M3N) - && (prr_product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) && + (prr_product != PRR_PRODUCT_V3H)) { foreach_vch(ch) { mmio_write_32(DBSC_DBPDRGA(ch), regadd); dsb_sev(); @@ -662,9 +644,7 @@ static inline void ddrphy_regif_idle(void) (void)val; } -/******************************************************************************* - * DDRPHY register access (field modify) - ******************************************************************************/ +/* DDRPHY register access (field modify) */ static inline uint32_t ddr_regdef(uint32_t _regdef) { return p_ddr_regdef_tbl[_regdef]; @@ -780,9 +760,7 @@ static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p) return p[0]; } -/******************************************************************************* - * handling functions for setteing ddrphy value table - ******************************************************************************/ +/* handling functions for setteing ddrphy value table */ static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size) { uint32_t i; @@ -853,9 +831,7 @@ static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef) return tmp; } -/******************************************************************************* - * DDRPHY register access handling - ******************************************************************************/ +/* DDRPHY register access handling */ static uint32_t ddrphy_regif_chk(void) { uint32_t tmp_ach[DRAM_CH_CNT]; @@ -863,11 +839,11 @@ static uint32_t ddrphy_regif_chk(void) uint32_t err; uint32_t PI_VERSION_CODE; - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3)) { - PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3)) { + PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ } else { - PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ + PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ } ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach); @@ -879,9 +855,7 @@ static uint32_t ddrphy_regif_chk(void) return err; } -/******************************************************************************* - * functions and parameters for timing setting - ******************************************************************************/ +/* functions and parameters for timing setting */ struct _jedec_spec1 { uint16_t fx3; uint8_t rlwodbi; @@ -1042,9 +1016,9 @@ static int16_t _f_scale_adj(int16_t ps) { int32_t tmp; /* - tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000; - = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125 - = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 + * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000; + * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125 + * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 */ tmp = (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps / @@ -1132,9 +1106,9 @@ const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = { _reg_PI_MR14_DATA_F1_3} }; -/******************************************************************************* +/* * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA ) - *******************************************************************************/ + */ static void regif_pll_wa(void) { uint32_t ch; @@ -1177,11 +1151,14 @@ static void regif_pll_wa(void) reg_ddrphy_write_a(ddr_regdef_adr (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL), ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_LP4_BOOT_TOP_PLL_CTRL)); + _reg_PHY_LP4_BOOT_TOP_PLL_CTRL + )); } reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), - _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]); + _cnf_DDR_PHY_ADR_G_REGSET + [ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - + DDR_PHY_ADR_G_REGSET_OFS]); /* protect register interface */ ddrphy_regif_idle(); @@ -1196,9 +1173,7 @@ static void regif_pll_wa(void) ddrphy_regif_idle(); } - /*********************************************************************** - init start - ***********************************************************************/ + /* init start */ /* dbdficnt0: * dfi_dram_clk_disable=1 * dfi_frequency = 0 @@ -1220,14 +1195,13 @@ static void regif_pll_wa(void) dsb_sev(); foreach_ech(ch) - if (((board_cnf->phyvalid) & (1U << ch))) - while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f); + if ((board_cnf->phyvalid) & BIT(ch)) + while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) + ; dsb_sev(); } -/******************************************************************************* - * load table data into DDR registers - ******************************************************************************/ +/* load table data into DDR registers */ static void ddrtbl_load(void) { uint32_t i; @@ -1238,9 +1212,7 @@ static void ddrtbl_load(void) uint32_t tmp[3]; uint16_t dataS; - /*********************************************************************** - TIMING REGISTERS - ***********************************************************************/ + /* TIMING REGISTERS */ /* search jedec_spec1 index */ for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) { if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) @@ -1261,9 +1233,7 @@ static void ddrtbl_load(void) /* calculate jedec_spec2 */ _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); - /*********************************************************************** - PREPARE TBL - ***********************************************************************/ + /* PREPARE TBL */ if (prr_product == PRR_PRODUCT_H3) { if (prr_cut <= PRR_PRODUCT_11) { /* H3 Ver.1.x */ @@ -1404,9 +1374,7 @@ static void ddrtbl_load(void) DDR_PHY_ADR_I_NUM = 2; } - /*********************************************************************** - PLL CODE CHANGE - ***********************************************************************/ + /* PLL CODE CHANGE */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, 0x1142); @@ -1414,17 +1382,13 @@ static void ddrtbl_load(void) _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142); } - /*********************************************************************** - on fly gate adjust - ***********************************************************************/ + /* on fly gate adjust */ if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) { ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_ON_FLY_GATE_ADJUST_EN, 0x00); } - /*********************************************************************** - Adjust PI parameters - ***********************************************************************/ + /* Adjust PI parameters */ #ifdef _def_LPDDR4_ODT for (i = 0; i < 2; i++) { for (csab = 0; csab < CSAB_CNT; csab++) { @@ -1444,22 +1408,22 @@ static void ddrtbl_load(void) } } #endif /* _def_LPDDR4_VREFCA */ - if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; if (js2[js2_tiedly] > (RL)) js2[js2_tiedly] = RL; - } else if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_11)) { + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) { js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; - } else if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); } - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { if ((js2[js2_tiedly]) >= 0x1e) dataS = 0x1e; else @@ -1474,8 +1438,8 @@ static void ddrtbl_load(void) ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, (dataS - 2)); - if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_OE_DLY, dataS); } @@ -1521,25 +1485,19 @@ static void ddrtbl_load(void) } } - /*********************************************************************** - DDRPHY INT START - ***********************************************************************/ + /* DDRPHY INT START */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { /* non */ } else { regif_pll_wa(); } - /*********************************************************************** - FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) - ***********************************************************************/ + /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); - /*********************************************************************** - SET DATA SLICE TABLE - ***********************************************************************/ + /* SET DATA SLICE TABLE */ for (slice = 0; slice < SLICE_CNT; slice++) { adr = DDR_PHY_SLICE_REGSET_OFS + @@ -1550,16 +1508,14 @@ static void ddrtbl_load(void) } } - /*********************************************************************** - SET ADR SLICE TABLE - ***********************************************************************/ + /* SET ADR SLICE TABLE */ adr = DDR_PHY_ADR_V_REGSET_OFS; for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); } - if (((prr_product == PRR_PRODUCT_M3) - || (prr_product == PRR_PRODUCT_M3N)) && + if (((prr_product == PRR_PRODUCT_M3) || + (prr_product == PRR_PRODUCT_M3N)) && ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40)) != 0x00)) { adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE; @@ -1597,26 +1553,20 @@ static void ddrtbl_load(void) } } - /*********************************************************************** - SET ADRCTRL SLICE TABLE - ***********************************************************************/ + /* SET ADRCTRL SLICE TABLE */ adr = DDR_PHY_ADR_G_REGSET_OFS; for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) { reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); } - /*********************************************************************** - SET PI REGISTERS - ***********************************************************************/ + /* SET PI REGISTERS */ adr = DDR_PI_REGSET_OFS; for (i = 0; i < DDR_PI_REGSET_NUM; i++) { reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); } } -/******************************************************************************* - * CONFIGURE DDR REGISTERS - ******************************************************************************/ +/* CONFIGURE DDR REGISTERS */ static void ddr_config_sub(void) { uint32_t i; @@ -1627,9 +1577,7 @@ static void ddr_config_sub(void) const uint32_t _par_CALVL_DEVICE_MAP = 1; foreach_vch(ch) { - /*********************************************************************** - BOARD SETTINGS (DQ,DM,VREF_DRIVING) - ***********************************************************************/ + /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ for (slice = 0; slice < SLICE_CNT; slice++) { high_byte[slice] = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2; @@ -1650,9 +1598,7 @@ static void ddr_config_sub(void) } } - /*********************************************************************** - BOARD SETTINGS (CA,ADDR_SEL) - ***********************************************************************/ + /* BOARD SETTINGS (CA,ADDR_SEL) */ data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) | 0x00888888; @@ -1674,8 +1620,8 @@ static void ddr_config_sub(void) } /* --- ADR_ADDR_SEL --- */ - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) { data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; } else { data_l = 0; @@ -1719,9 +1665,7 @@ static void ddr_config_sub(void) ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l); } - /*********************************************************************** - BOARD SETTINGS (BYTE_ORDER_SEL) - ***********************************************************************/ + /* BOARD SETTINGS (BYTE_ORDER_SEL) */ if (prr_product == PRR_PRODUCT_M3) { /* --- DATA_BYTE_SWAP --- */ data_l = 0; @@ -1792,9 +1736,7 @@ static void ddr_config_sub_h3v1x(void) const uint16_t o_mr32_mr40 = 0x5a3c; foreach_vch(ch) { - /*********************************************************************** - BOARD SETTINGS (DQ,DM,VREF_DRIVING) - ***********************************************************************/ + /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ csmap = 0; for (slice = 0; slice < SLICE_CNT; slice++) { tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; @@ -1817,9 +1759,7 @@ static void ddr_config_sub_h3v1x(void) 0x01); } } - /*********************************************************************** - BOARD SETTINGS (CA,ADDR_SEL) - ***********************************************************************/ + /* BOARD SETTINGS (CA,ADDR_SEL) */ ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca); ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap); @@ -1878,18 +1818,14 @@ static void ddr_config(void) } patt; uint16_t patm; - /*********************************************************************** - configure ddrphy registers - ***********************************************************************/ + /* configure ddrphy registers */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_config_sub_h3v1x(); } else { ddr_config_sub(); /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ } - /*********************************************************************** - WDQ_USER_PATT - ***********************************************************************/ + /* WDQ_USER_PATT */ foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { patm = 0; @@ -1911,9 +1847,7 @@ static void ddr_config(void) } } - /*********************************************************************** - CACS DLY - ***********************************************************************/ + /* CACS DLY */ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U); foreach_vch(ch) { @@ -1923,11 +1857,11 @@ static void ddr_config(void) _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], data_l + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), - _cnf_DDR_PHY_ADR_V_REGSET[ - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - + ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), + _cnf_DDR_PHY_ADR_V_REGSET + [ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_V_REGSET_OFS]); } @@ -1938,29 +1872,30 @@ static void ddr_config(void) _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], data_l + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), - _cnf_DDR_PHY_ADR_G_REGSET[ - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - + ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), + _cnf_DDR_PHY_ADR_G_REGSET + [ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_G_REGSET_OFS]); } if (ddr_phycaslice == 1) { for (i = 0; i < 6; i++) { - adj = _f_scale_adj( - board_cnf->ch[ch].cacs_adj[ - i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); + adj = _f_scale_adj + (board_cnf->ch[ch].cacs_adj + [i + + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], data_l + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + + ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + 0x0100, - _cnf_DDR_PHY_ADR_V_REGSET[ - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - + _cnf_DDR_PHY_ADR_V_REGSET + [ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_V_REGSET_OFS]); } } @@ -1969,9 +1904,7 @@ static void ddr_config(void) reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); - /*********************************************************************** - WDQDM DLY - ***********************************************************************/ + /* WDQDM DLY */ data_l = board_cnf->dqdm_dly_w; foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { @@ -1989,9 +1922,7 @@ static void ddr_config(void) } } - /*********************************************************************** - RDQDM DLY - ***********************************************************************/ + /* RDQDM DLY */ data_l = board_cnf->dqdm_dly_r; foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { @@ -2013,17 +1944,13 @@ static void ddr_config(void) } } -/******************************************************************************* - * DBSC register setting functions - ******************************************************************************/ +/* DBSC register setting functions */ static void dbsc_regset_pre(void) { uint32_t ch, csab; uint32_t data_l; - /*********************************************************************** - PRIMARY SETTINGS - ***********************************************************************/ + /* PRIMARY SETTINGS */ /* LPDDR4, BL=16, DFI interface */ mmio_write_32(DBSC_DBKIND, 0x0000000a); mmio_write_32(DBSC_DBBL, 0x00000002); @@ -2069,8 +1996,8 @@ static void dbsc_regset(void) uint32_t tmp[4]; /* RFC */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) - && (max_density == 0)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) && + (max_density == 0)) { js2[js2_trfcab] = _f_scale(ddr_mbps, ddr_mbpsdiv, 1UL * jedec_spec2_trfc_ab[1] * 1000, 0); @@ -2219,8 +2146,8 @@ static void dbsc_regset(void) for (i = 0; i < 4; i++) { data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_11) && (i == 0)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11) && (i == 0)) { data_l += 1; } data_l2 = 0; @@ -2231,9 +2158,7 @@ static void dbsc_regset(void) } mmio_write_32(DBSC_DBADJ0, 0x00000000); - /*********************************************************************** - timing registers for Scheduler - ***********************************************************************/ + /* timing registers for Scheduler */ /* SCFCTST0 */ /* SCFCTST0 ACT-ACT */ tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps; @@ -2285,9 +2210,7 @@ static void dbsc_regset(void) * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps); } - /*********************************************************************** - QOS and CAM - ***********************************************************************/ + /* QOS and CAM */ #ifdef ddr_qos_init_setting /* only for non qos_init */ /*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */ mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); @@ -2418,9 +2341,11 @@ static void dbsc_regset_post(void) mmio_write_32(DBSC_DBDBICNT, 0x00000003); /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */ - if ((((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) && (board_cnf->dbi_en)) + if ((((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) && + board_cnf->dbi_en) reg_ddrphy_write_a(0x00001010, 0x01000000); /*set REFCYCLE */ @@ -2461,11 +2386,16 @@ static void dbsc_regset_post(void) #if RCAR_REWT_TRAINING != 0 /* Periodic-WriteDQ Training seeting */ - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut == PRR_PRODUCT_10))) { /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ } else { - /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H -> Periodic-WriteDQ Training seeting */ + /* + * H3 Ver.2.0 or later/M3-W Ver.1.1 or + * later/M3-N/V3H -> Periodic-WriteDQ Training seeting + */ /* Periodic WriteDQ Training seeting */ mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000); @@ -2499,13 +2429,15 @@ static void dbsc_regset_post(void) #endif /* RCAR_REWT_TRAINING */ /* periodic dram zqcal and phy ctrl update enable */ mmio_write_32(DBSC_DBCALCNF, 0x01000010); - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { #if RCAR_DRAM_SPLIT == 2 - if ((prr_product == PRR_PRODUCT_H3) - && (board_cnf->phyvalid == 0x05)) + if ((prr_product == PRR_PRODUCT_H3) && + (board_cnf->phyvalid == 0x05)) mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); else mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); @@ -2522,9 +2454,7 @@ static void dbsc_regset_post(void) } -/******************************************************************************* - * DFI_INIT_START - ******************************************************************************/ +/* DFI_INIT_START */ static uint32_t dfi_init_start(void) { uint32_t ch; @@ -2534,17 +2464,13 @@ static uint32_t dfi_init_start(void) const uint32_t RETRY_MAX = 0x10000; if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - /*********************************************************************** - PLL3 Disable - ***********************************************************************/ + /* PLL3 Disable */ /* protect register interface */ ddrphy_regif_idle(); pll3_control(0); - /*********************************************************************** - init start - ***********************************************************************/ + /* init start */ /* dbdficnt0: * dfi_dram_clk_disable=1 * dfi_frequency = 0 @@ -2576,9 +2502,7 @@ static uint32_t dfi_init_start(void) mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01); dsb_sev(); - /*********************************************************************** - wait init_complete - ***********************************************************************/ + /* wait init_complete */ phytrainingok = 0; retry = 0; while (retry++ < RETRY_MAX) { @@ -2594,12 +2518,10 @@ static uint32_t dfi_init_start(void) ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); } - /*********************************************************************** - all ch ok? - ***********************************************************************/ - if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) { - return (0xff); - } + /* all ch ok? */ + if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) + return 0xff; + /* dbdficnt0: * dfi_dram_clk_disable=0 * dfi_frequency = 0 @@ -2613,9 +2535,7 @@ static uint32_t dfi_init_start(void) return 0; } -/******************************************************************************* - * drivablity setting : CMOS MODE ON/OFF - ******************************************************************************/ +/* drivablity setting : CMOS MODE ON/OFF */ static void change_lpddr4_en(uint32_t mode) { uint32_t ch; @@ -2640,9 +2560,7 @@ static void change_lpddr4_en(uint32_t mode) } } -/******************************************************************************* - * drivablity setting - ******************************************************************************/ +/* drivablity setting */ static uint32_t set_term_code(void) { int32_t i; @@ -2666,8 +2584,8 @@ static uint32_t set_term_code(void) if (termcode_by_sample[index][0] == 0xffffffff) { break; } - if ((termcode_by_sample[index][0] == chip_id[0]) - && (termcode_by_sample[index][1] == chip_id[1])) { + if ((termcode_by_sample[index][0] == chip_id[0]) && + (termcode_by_sample[index][1] == chip_id[1])) { term_code = termcode_by_sample[index][2]; override = 1; break; @@ -2683,8 +2601,8 @@ static uint32_t set_term_code(void) data_l = (data_l & 0xfffe0000) | term_code; ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l); } - } else if ((prr_product == PRR_PRODUCT_M3) - && (prr_cut == PRR_PRODUCT_10)) { + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut == PRR_PRODUCT_10)) { /* non */ } else { ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], @@ -2699,8 +2617,8 @@ static uint32_t set_term_code(void) ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); } while (!(data_l & 0x00800000)); } - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); pvtr = (data_l >> 12) & 0x1f; @@ -2743,17 +2661,17 @@ static uint32_t set_term_code(void) } } } + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - /* non */ + /* non */ } else { ddr_padcal_tcompensate_getinit(override); } + return 0; } -/******************************************************************************* - * DDR mode register setting - ******************************************************************************/ +/* DDR mode register setting */ static void ddr_register_set(void) { int32_t fspwp; @@ -2797,9 +2715,7 @@ static void ddr_register_set(void) } } -/******************************************************************************* - * Training handshake functions - ******************************************************************************/ +/* Training handshake functions */ static inline uint32_t wait_freqchgreq(uint32_t assert) { uint32_t data_l; @@ -2871,7 +2787,7 @@ static uint32_t pll3_freq(uint32_t on) timeout = wait_freqchgreq(1); if (timeout) { - return (1); + return 1; } pll3_control(on); @@ -2883,23 +2799,19 @@ static uint32_t pll3_freq(uint32_t on) if (timeout) { FATAL_MSG("BL2: Time out[2]\n"); - return (1); + return 1; } - return (0); + return 0; } -/******************************************************************************* - * update dly - ******************************************************************************/ +/* update dly */ static void update_dly(void) { ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01); ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01); } -/******************************************************************************* - * training by pi - ******************************************************************************/ +/* training by pi */ static uint32_t pi_training_go(void) { uint32_t flag; @@ -2913,11 +2825,7 @@ static uint32_t pi_training_go(void) uint32_t complete; uint32_t frqchg_req; - /* ********************************************************************* */ - - /*********************************************************************** - pi_start - ***********************************************************************/ + /* pi_start */ ddr_setval_ach(_reg_PI_START, 0x01); foreach_vch(ch) ddr_getval(ch, _reg_PI_INT_STATUS); @@ -2926,9 +2834,7 @@ static uint32_t pi_training_go(void) mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001); dsb_sev(); - /*********************************************************************** - wait pi_int_status[0] - ***********************************************************************/ + /* wait pi_int_status[0] */ mst_ch = 0; flag = 0; complete = 0; @@ -2938,8 +2844,8 @@ static uint32_t pi_training_go(void) frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; /* H3 Ver.1.x cannot see frqchg_req */ - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { if ((retry % 4096) == 1) { frqchg_req = 1; } else { @@ -2982,14 +2888,12 @@ static uint32_t pi_training_go(void) ddr_setval(ch, _reg_PI_INT_ACK, data_l); } if (ddrphy_regif_chk()) { - return (0xfd); + return 0xfd; } return complete; } -/******************************************************************************* - * Initialize ddr - ******************************************************************************/ +/* Initialize DDR */ static uint32_t init_ddr(void) { int32_t i; @@ -3005,68 +2909,51 @@ static uint32_t init_ddr(void) rcar_dram_get_boot_status(&ddr_backup); #endif - /*********************************************************************** - unlock phy - ***********************************************************************/ + /* unlock phy */ /* Unlock DDRPHY register(AGAIN) */ foreach_vch(ch) mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); dsb_sev(); - if ((((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) && (board_cnf->dbi_en)) + if ((((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) && board_cnf->dbi_en) reg_ddrphy_write_a(0x00001010, 0x01000001); else reg_ddrphy_write_a(0x00001010, 0x00000001); - /*********************************************************************** - dbsc register pre-setting - ***********************************************************************/ + /* DBSC register pre-setting */ dbsc_regset_pre(); - /*********************************************************************** - load ddrphy registers - ***********************************************************************/ + /* load ddrphy registers */ ddrtbl_load(); - /*********************************************************************** - configure ddrphy registers - ***********************************************************************/ + /* configure ddrphy registers */ ddr_config(); - /*********************************************************************** - dfi_reset assert - ***********************************************************************/ + /* dfi_reset assert */ foreach_vch(ch) mmio_write_32(DBSC_DBPDCNT0(ch), 0x01); dsb_sev(); - /*********************************************************************** - dbsc register set - ***********************************************************************/ + /* dbsc register set */ dbsc_regset(); MSG_LF("init_ddr:1\n"); - /*********************************************************************** - dfi_reset negate - ***********************************************************************/ + /* dfi_reset negate */ foreach_vch(ch) mmio_write_32(DBSC_DBPDCNT0(ch), 0x00); dsb_sev(); - /*********************************************************************** - dfi_init_start (start ddrphy) - ***********************************************************************/ + /* dfi_init_start (start ddrphy) */ err = dfi_init_start(); if (err) { return INITDRAM_ERR_I; } MSG_LF("init_ddr:2\n"); - /*********************************************************************** - ddr backupmode end - ***********************************************************************/ + /* ddr backupmode end */ #ifdef DDR_BACKUPMODE if (ddr_backup) { NOTICE("BL2: [WARM_BOOT]\n"); @@ -3081,47 +2968,37 @@ static uint32_t init_ddr(void) #endif MSG_LF("init_ddr:3\n"); - /*********************************************************************** - override term code after dfi_init_complete - ***********************************************************************/ + /* override term code after dfi_init_complete */ err = set_term_code(); if (err) { return INITDRAM_ERR_I; } MSG_LF("init_ddr:4\n"); - /*********************************************************************** - rx offset calibration - ***********************************************************************/ - if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + /* rx offset calibration */ + if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { err = rx_offset_cal_hw(); } else { err = rx_offset_cal(); } if (err) - return (INITDRAM_ERR_O); + return INITDRAM_ERR_O; MSG_LF("init_ddr:5\n"); /* PDX */ send_dbcmd(0x08840001); - /*********************************************************************** - check register i/f is alive - ***********************************************************************/ + /* check register i/f is alive */ err = ddrphy_regif_chk(); if (err) { - return (INITDRAM_ERR_O); + return INITDRAM_ERR_O; } MSG_LF("init_ddr:6\n"); - /*********************************************************************** - phy initialize end - ***********************************************************************/ + /* phy initialize end */ - /*********************************************************************** - setup DDR mode registers - ***********************************************************************/ + /* setup DDR mode registers */ /* CMOS MODE */ change_lpddr4_en(0); @@ -3134,9 +3011,7 @@ static uint32_t init_ddr(void) /* ZQLAT */ send_dbcmd(0x0d840051); - /*********************************************************************** - Thermal sensor setting - ***********************************************************************/ + /* Thermal sensor setting */ /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; mmio_write_32(THS1_THCTR, data_l); @@ -3146,9 +3021,7 @@ static uint32_t init_ddr(void) MSG_LF("init_ddr:7\n"); - /*********************************************************************** - mask CS_MAP if RANKx is not found - ***********************************************************************/ + /* mask CS_MAP if RANKx is not found */ foreach_vch(ch) { data_l = ddr_getval(ch, _reg_PI_CS_MAP); if (!(ch_have_this_cs[1] & (1U << ch))) @@ -3156,9 +3029,7 @@ static uint32_t init_ddr(void) ddr_setval(ch, _reg_PI_CS_MAP, data_l); } - /*********************************************************************** - exec pi_training - ***********************************************************************/ + /* exec pi_training */ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); @@ -3179,14 +3050,12 @@ static uint32_t init_ddr(void) phytrainingok = pi_training_go(); if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) { - return (INITDRAM_ERR_T | phytrainingok); + return INITDRAM_ERR_T | phytrainingok; } MSG_LF("init_ddr:8\n"); - /*********************************************************************** - CACS DLY ADJUST - ***********************************************************************/ + /* CACS DLY ADJUST */ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); foreach_vch(ch) { for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { @@ -3208,23 +3077,17 @@ static uint32_t init_ddr(void) update_dly(); MSG_LF("init_ddr:9\n"); - /*********************************************************************** - H3 fix rd latency to avoid bug in elasitic buffe - ***********************************************************************/ + /* H3 fix rd latency to avoid bug in elasitic buffer */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { adjust_rddqs_latency(); } - /*********************************************************************** - Adjust Write path latency - ***********************************************************************/ + /* Adjust Write path latency */ if (ddrtbl_getval (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) adjust_wpath_latency(); - /*********************************************************************** - RDQLVL Training - ***********************************************************************/ + /* RDQLVL Training */ if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) { ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); } @@ -3236,27 +3099,23 @@ static uint32_t init_ddr(void) } if (err) { - return (INITDRAM_ERR_T); + return INITDRAM_ERR_T; } update_dly(); MSG_LF("init_ddr:10\n"); - /*********************************************************************** - WDQLVL Training - ***********************************************************************/ + /* WDQLVL Training */ err = wdqdm_man(); if (err) { - return (INITDRAM_ERR_T); + return INITDRAM_ERR_T; } update_dly(); MSG_LF("init_ddr:11\n"); - /*********************************************************************** - training complete, setup dbsc - ***********************************************************************/ - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + /* training complete, setup DBSC */ + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); } @@ -3267,9 +3126,7 @@ static uint32_t init_ddr(void) return phytrainingok; } -/******************************************************************************* - * SW LEVELING COMMON - ******************************************************************************/ +/* SW LEVELING COMMON */ static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) { uint32_t ch; @@ -3320,9 +3177,7 @@ static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) return err; } -/******************************************************************************* - * WDQ TRAINING - ******************************************************************************/ +/* WDQ TRAINING */ #ifndef DDR_FAST_INIT static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) { @@ -3330,9 +3185,7 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) uint32_t cs, slice; uint32_t data_l; - /*********************************************************************** - clr of training results buffer - ***********************************************************************/ + /* clr of training results buffer */ cs = ddr_csn % 2; data_l = board_cnf->dqdm_dly_w; for (slice = 0; slice < SLICE_CNT; slice++) { @@ -3368,9 +3221,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) int16_t adj; uint32_t dq; - /*********************************************************************** - analysis of training results - ***********************************************************************/ + /* analysis of training results */ err = 0; for (slice = 0; slice < SLICE_CNT; slice += 1) { k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; @@ -3437,9 +3288,7 @@ static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore) uint32_t tgt_cs, src_cs; uint32_t tmp_r; - /*********************************************************************** - copy of training results - ***********************************************************************/ + /* copy of training results */ foreach_vch(ch) { for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) { for (slice = 0; slice < SLICE_CNT; slice++) { @@ -3481,9 +3330,7 @@ static uint32_t wdqdm_man1(void) uint32_t err_flg; #endif/* DDR_FAST_INIT */ - /*********************************************************************** - manual execution of training - ***********************************************************************/ + /* manual execution of training */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { high_dq[ch] = 0; @@ -3499,10 +3346,10 @@ static uint32_t wdqdm_man1(void) /* CLEAR PREV RESULT */ for (cs = 0; cs < CS_CNT; cs++) { ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); - if (((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01); } else { @@ -3516,8 +3363,8 @@ static uint32_t wdqdm_man1(void) err_flg = 0; #endif/* DDR_FAST_INIT */ for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { data_l = mmio_read_32(DBSC_DBDFICNT(ch)); data_l &= ~(0x00ffU << 16); @@ -3531,10 +3378,10 @@ static uint32_t wdqdm_man1(void) ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k); } } - if (((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) - && (prr_cut == PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut == PRR_PRODUCT_10))) { wdqdm_cp(ddr_csn, 0); } @@ -3585,7 +3432,7 @@ err_exit: ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00); } } - return (err); + return err; } static uint32_t wdqdm_man(void) @@ -3595,9 +3442,9 @@ static uint32_t wdqdm_man(void) uint32_t ch, ddr_csn, mr14_bkup[4][4]; ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12); - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, (DBSC_DBTR(12) & 0xFF) + 1); } else { @@ -3609,15 +3456,15 @@ static uint32_t wdqdm_man(void) retry_cnt = 0; err = 0; do { - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { err = wdqdm_man1(); } else { ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x01); - if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x0C); } else { @@ -3635,8 +3482,8 @@ static uint32_t wdqdm_man(void) } } - if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x04); } else { @@ -3660,8 +3507,8 @@ static uint32_t wdqdm_man(void) ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x00); - if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x00); ddr_setval_ach @@ -3688,17 +3535,15 @@ static uint32_t wdqdm_man(void) } } while (err && (++retry_cnt < retry_max)); - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) { wdqdm_cp(0, 1); } return (retry_cnt >= retry_max); } -/******************************************************************************* - * RDQ TRAINING - ******************************************************************************/ +/* RDQ TRAINING */ #ifndef DDR_FAST_INIT static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) { @@ -3706,9 +3551,7 @@ static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) uint32_t cs, slice; uint32_t data_l; - /*********************************************************************** - clr of training results buffer - ***********************************************************************/ + /* clr of training results buffer */ cs = ddr_csn % 2; data_l = board_cnf->dqdm_dly_r; for (slice = 0; slice < SLICE_CNT; slice++) { @@ -3753,9 +3596,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) int32_t win; uint32_t rdq_status_obs_select; - /*********************************************************************** - analysis of training results - ***********************************************************************/ + /* analysis of training results */ err = 0; for (slice = 0; slice < SLICE_CNT; slice++) { k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; @@ -3847,7 +3688,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) err = 2; } } - return (err); + return err; } #endif/* DDR_FAST_INIT */ @@ -3861,9 +3702,7 @@ static uint32_t rdqdm_man1(void) #endif/* DDR_FAST_INIT */ uint32_t err; - /*********************************************************************** - manual execution of training - ***********************************************************************/ + /* manual execution of training */ err = 0; for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { @@ -3896,10 +3735,10 @@ static uint32_t rdqdm_man1(void) } } } - if (((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) - && (prr_cut <= PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut <= PRR_PRODUCT_10))) { for (slice = 0; slice < SLICE_CNT; slice++) { for (i = 0; i <= 8; i++) { if (i == 8) @@ -3926,7 +3765,7 @@ static uint32_t rdqdm_man1(void) } err_exit: - return (err); + return err; } static uint32_t rdqdm_man(void) @@ -3968,9 +3807,7 @@ static uint32_t rdqdm_man(void) return (retry_cnt >= retry_max); } -/******************************************************************************* - * rx offset calibration - ******************************************************************************/ +/* rx offset calibration */ static int32_t _find_change(uint64_t val, uint32_t dir) { int32_t i; @@ -3983,17 +3820,17 @@ static int32_t _find_change(uint64_t val, uint32_t dir) for (i = 1; i <= VAL_END; i++) { curval = (val >> i) & 0x01; if (curval != startval) - return (i); + return i; } - return (VAL_END); + return VAL_END; } else { startval = (val >> dir) & 0x01; for (i = dir - 1; i >= 0; i--) { curval = (val >> i) & 0x01; if (curval != startval) - return (i); + return i; } - return (0); + return 0; } } @@ -4116,10 +3953,10 @@ static uint32_t rx_offset_cal_hw(void) for (slice = 0; slice < SLICE_CNT; slice++) { tmp = tmp_ach_as[ch][slice]; tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); - if (((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { if (tmp != 0x3E) complete = 0; } else { @@ -4137,9 +3974,7 @@ static uint32_t rx_offset_cal_hw(void) return (complete == 0); } -/******************************************************************************* - * adjust rddqs latency - ******************************************************************************/ +/* adjust rddqs latency */ static void adjust_rddqs_latency(void) { uint32_t ch, slice; @@ -4180,9 +4015,7 @@ static void adjust_rddqs_latency(void) } } -/******************************************************************************* - * adjust wpath latency - ******************************************************************************/ +/* adjust wpath latency */ static void adjust_wpath_latency(void) { uint32_t ch, cs, slice; @@ -4215,9 +4048,7 @@ static void adjust_wpath_latency(void) } } -/******************************************************************************* - * DDR Initialize entry - ******************************************************************************/ +/* DDR Initialize entry */ int32_t rcar_dram_init(void) { uint32_t ch, cs; @@ -4227,23 +4058,20 @@ int32_t rcar_dram_init(void) uint32_t failcount; uint32_t cnf_boardtype; - /*********************************************************************** - Thermal sensor setting - ***********************************************************************/ + /* Thermal sensor setting */ data_l = mmio_read_32(CPG_MSTPSR5); if (data_l & BIT(22)) { /* case THS/TSC Standby */ - data_l &= ~(BIT(22)); + data_l &= ~BIT(22); cpg_write_32(CPG_SMSTPCR5, data_l); - while ((BIT(22)) & mmio_read_32(CPG_MSTPSR5)); /* wait bit=0 */ + while (mmio_read_32(CPG_MSTPSR5) & BIT(22)) + ; /* wait bit=0 */ } /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; mmio_write_32(THS1_THCTR, data_l); - /*********************************************************************** - Judge product and cut - ***********************************************************************/ + /* Judge product and cut */ #ifdef RCAR_DDR_FIXED_LSI_TYPE #if (RCAR_LSI == RCAR_AUTO) prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; @@ -4266,24 +4094,22 @@ int32_t rcar_dram_init(void) } } else if (prr_product == PRR_PRODUCT_M3) { p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[1][0]; - } else if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + } else if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[3][0]; } else { FATAL_MSG("BL2: DDR:Unknown Product\n"); return 0xff; } - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); } - /*********************************************************************** - Judge board type - ***********************************************************************/ + /* Judge board type */ cnf_boardtype = boardcnf_get_brd_type(); if (cnf_boardtype >= BOARDNUM) { FATAL_MSG("BL2: DDR:Unknown Board\n"); @@ -4293,9 +4119,7 @@ int32_t rcar_dram_init(void) /* RCAR_DRAM_SPLIT_2CH (2U) */ #if RCAR_DRAM_SPLIT == 2 - /*********************************************************************** - H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split - ***********************************************************************/ + /* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */ if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) { mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); ddr_phyvalid = 0x03; @@ -4325,16 +4149,14 @@ int32_t rcar_dram_init(void) continue; if (data_l > max_density) max_density = data_l; - if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) + if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) continue; ch_have_this_cs[cs] |= (1U << ch); } } - /*********************************************************************** - Judge board clock frequency (in MHz) - ***********************************************************************/ + /* Judge board clock frequency (in MHz) */ boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv); if ((brd_clk / brd_clkdiv) > 25) { brd_clkdiva = 1; @@ -4342,9 +4164,7 @@ int32_t rcar_dram_init(void) brd_clkdiva = 0; } - /*********************************************************************** - Judge ddr operating frequency clock(in Mbps) - ***********************************************************************/ + /* Judge ddr operating frequency clock(in Mbps) */ boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv); ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); @@ -4352,9 +4172,7 @@ int32_t rcar_dram_init(void) ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); - /*********************************************************************** - Adjust tccd - ***********************************************************************/ + /* Adjust tccd */ data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; bus_mbps = 0; bus_mbpsdiv = 0; @@ -4393,14 +4211,10 @@ int32_t rcar_dram_init(void) MSG_LF("Start\n"); - /*********************************************************************** - PLL Setting - ***********************************************************************/ + /* PLL Setting */ pll3_control(1); - /*********************************************************************** - initialize DDR - ***********************************************************************/ + /* initialize DDR */ data_l = init_ddr(); if (data_l == ddr_phyvalid) { failcount = 0; @@ -4410,8 +4224,8 @@ int32_t rcar_dram_init(void) foreach_vch(ch) mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); @@ -4453,8 +4267,8 @@ void pvtcode_update(void) pvtn_init) / (pvtn_tmp) + 6 * pvtp_tmp + pvtp_init; } - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { data_l = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), @@ -4556,8 +4370,8 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) else pvtn = 0; - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { tcal.init_cal[ch] = (tcal. init_cal[ch] & 0xfffff000) | (pvtn << 6) | @@ -4578,7 +4392,3 @@ uint8_t get_boardcnf_phyvalid(void) return ddr_phyvalid; } #endif /* ddr_qos_init_setting */ - -/******************************************************************************* - * END - ******************************************************************************/ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index cb3a482eb..52dbac321 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -17,7 +17,7 @@ static uint32_t boardcnf_get_brd_type(void) #else static uint32_t boardcnf_get_brd_type(void) { - return (1); + return 1; } #endif @@ -1630,7 +1630,8 @@ static void pfc_write_and_poll(uint32_t a, uint32_t v) mmio_write_32(PFC_PMMR, ~v); v = ~mmio_read_32(PFC_PMMR); mmio_write_32(a, v); - while (v != mmio_read_32(a)); + while (v != mmio_read_32(a)) + ; dsb_sev(); } #endif @@ -1688,10 +1689,10 @@ static uint32_t opencheck_SSI_WS6(void) if (down == up) { /* Same = Connect */ return 0; - } else { - /* Diff = Open */ - return 1; } + + /* Diff = Open */ + return 1; } #endif @@ -1737,12 +1738,12 @@ static uint32_t _board_judge(void) } else if (prr_product == PRR_PRODUCT_M3) { /* RENESAS Kriek board with M3-W */ brd = 1; - } else if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { /* RENESAS Kriek board with PM3 */ brd = 13; - } else if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_20)) { + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_20)) { /* RENESAS Kriek board with H3N */ brd = 15; } -- cgit v1.2.3 From 4ca57bae2749cfffee64899358a9f7f62772bc68 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 8 Aug 2019 16:34:22 +0200 Subject: rcar_gen3: drivers: ddr_b: Fix line-over-80s Fix as many line-over-80s as possible. There are still a few remaining, which would need further refactoring. Signed-off-by: Marek Vasut Change-Id: I7225d9fab658d05e3315d8c3fa3c9f3bbb1ab40d --- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 229 ++++++++++++--------- .../renesas/rcar/ddr/ddr_b/boot_init_dram_config.c | 22 +- 2 files changed, 152 insertions(+), 99 deletions(-) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index d10687296..9c7f9c8ab 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -155,7 +156,8 @@ static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { }; #define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 -static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY + [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, @@ -169,7 +171,8 @@ static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_ }; #define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 -static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY + [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, @@ -182,7 +185,8 @@ static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SL }; #define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 -static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY + [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, @@ -207,7 +211,8 @@ static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { }; #define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 -static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { +static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X + [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, @@ -755,8 +760,8 @@ static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p) pp = p; foreach_vch(ch) - for (slice = 0; slice < SLICE_CNT; slice++) - *pp++ = ddr_getval_s(ch, slice, regdef); + for (slice = 0; slice < SLICE_CNT; slice++) + *pp++ = ddr_getval_s(ch, slice, regdef); return p[0]; } @@ -873,14 +878,22 @@ struct _jedec_spec1 { #define JS1_MR1(f) (0x04 | ((f) << 4)) #define JS1_MR2(f) (0x00 | ((f) << 3) | (f)) const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { - { 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40 }, /* 533.333Mbps */ - { 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40 }, /* 1066.666Mbps */ - { 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40 }, /* 1600.000Mbps */ - { 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) }, /* 2133.333Mbps */ - { 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) }, /* 2666.666Mbps */ - { 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) }, /* 3200.000Mbps */ - { 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) }, /* 3733.333Mbps */ - { 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) } /* 4266.666Mbps */ + /* 533.333Mbps */ + { 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40 }, + /* 1066.666Mbps */ + { 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40 }, + /* 1600.000Mbps */ + { 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40 }, + /* 2133.333Mbps */ + { 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) }, + /* 2666.666Mbps */ + { 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) }, + /* 3200.000Mbps */ + { 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) }, + /* 3733.333Mbps */ + { 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) }, + /* 4266.666Mbps */ + { 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) } }; struct _jedec_spec2 { @@ -1494,7 +1507,7 @@ static void ddrtbl_load(void) /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); /* SET DATA SLICE TABLE */ @@ -1523,7 +1536,8 @@ static void ddrtbl_load(void) reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); } - ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_ADR_DISABLE, 0x02); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_ADR_DISABLE, 0x02); DDR_PHY_ADR_I_NUM -= 1; ddr_phycaslice = 1; @@ -1639,19 +1653,30 @@ static void ddr_config_sub(void) /* --- ADR_CALVL_SWIZZLE --- */ if (prr_product == PRR_PRODUCT_M3) { - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_0, + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE0_0, + data_l); + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_1, + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE0_1, + data_l); + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_DEVICE_MAP, + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); } else { - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1, + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE0, + data_l); + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); - ddr_setval_s(ch, 2, _reg_PHY_CALVL_DEVICE_MAP, + ddr_setval_s(ch, 2, + _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); } @@ -1739,7 +1764,8 @@ static void ddr_config_sub_h3v1x(void) /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ csmap = 0; for (slice = 0; slice < SLICE_CNT; slice++) { - tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & + 0x0f; high_byte[slice] = tmp % 2; if (tmp == 1 && (slice >= 2)) csmap |= 0x05; @@ -1821,8 +1847,8 @@ static void ddr_config(void) /* configure ddrphy registers */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_config_sub_h3v1x(); - } else { - ddr_config_sub(); /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ + } else { /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ + ddr_config_sub(); } /* WDQ_USER_PATT */ @@ -1849,9 +1875,10 @@ static void ddr_config(void) /* CACS DLY */ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), + 0x00U); foreach_vch(ch) { - for (i = 0; i < (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i++) { + for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4; i++) { adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], @@ -1887,7 +1914,8 @@ static void ddr_config(void) [i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], + _reg_PHY_CLK_CACS_SLAVE_DELAY_X + [i], data_l + adj); reg_ddrphy_write(ch, ddr_regdef_adr @@ -1902,7 +1930,7 @@ static void ddr_config(void) } reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); /* WDQDM DLY */ data_l = board_cnf->dqdm_dly_w; @@ -1966,9 +1994,12 @@ static void dbsc_regset_pre(void) /* DRAM SIZE REGISTER: * set all ranks as density=0(4Gb) for PHY initialization */ - foreach_vch(ch) - for (csab = 0; csab < 4; csab++) - mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0)); + foreach_vch(ch) { + for (csab = 0; csab < 4; csab++) { + mmio_write_32(DBSC_DBMEMCONF(ch, csab), + DBMEMCONF_REGD(0)); + } + } if (prr_product == PRR_PRODUCT_M3) { data_l = 0xe4e4e4e4; @@ -2203,11 +2234,13 @@ static void dbsc_regset(void) if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { mmio_write_32(DBSC_DBSCHRW1, tmp[0] + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps - 3); + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / + ddr_mbps - 3); } else { mmio_write_32(DBSC_DBSCHRW1, tmp[0] + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps); + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / + ddr_mbps); } /* QOS and CAM */ @@ -2296,9 +2329,8 @@ static void dbsc_regset_post(void) ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); - data_l = - ddr_getval_s(ch, slice, - _reg_PHY_RDDQS_LATENCY_ADJUST); + data_l = ddr_getval_s(ch, slice, + _reg_PHY_RDDQS_LATENCY_ADJUST); if (data_l > rdlat_max) rdlat_max = data_l; if (data_l < rdlat_min) @@ -2424,7 +2456,8 @@ static void dbsc_regset_post(void) ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01); /* DFI_PHYMSTR_ACK , WTmode setting */ - mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); /* DFI_PHYMSTR_ACK: WTmode =b'01 */ + /* DFI_PHYMSTR_ACK: WTmode =b'01 */ + mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); } #endif /* RCAR_REWT_TRAINING */ /* periodic dram zqcal and phy ctrl update enable */ @@ -2450,8 +2483,7 @@ static void dbsc_regset_post(void) /* dram access enable */ mmio_write_32(DBSC_DBACEN, 0x00000001); - MSG_LF("dbsc_regset_post(done)"); - + MSG_LF(__func__ "(done)"); } /* DFI_INIT_START */ @@ -2645,7 +2677,8 @@ static uint32_t set_term_code(void) data_l); } } - } else { /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ + } else { + /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ foreach_vch(ch) { for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { @@ -2903,7 +2936,7 @@ static uint32_t init_ddr(void) uint32_t err; int16_t adj; - MSG_LF("init_ddr:0\n"); + MSG_LF(__func__ ":0\n"); #ifdef DDR_BACKUPMODE rcar_dram_get_boot_status(&ddr_backup); @@ -2939,7 +2972,7 @@ static uint32_t init_ddr(void) /* dbsc register set */ dbsc_regset(); - MSG_LF("init_ddr:1\n"); + MSG_LF(__func__ ":1\n"); /* dfi_reset negate */ foreach_vch(ch) @@ -2951,7 +2984,7 @@ static uint32_t init_ddr(void) if (err) { return INITDRAM_ERR_I; } - MSG_LF("init_ddr:2\n"); + MSG_LF(__func__ ":2\n"); /* ddr backupmode end */ #ifdef DDR_BACKUPMODE @@ -2966,14 +2999,14 @@ static uint32_t init_ddr(void) return INITDRAM_ERR_I; } #endif - MSG_LF("init_ddr:3\n"); + MSG_LF(__func__ ":3\n"); /* override term code after dfi_init_complete */ err = set_term_code(); if (err) { return INITDRAM_ERR_I; } - MSG_LF("init_ddr:4\n"); + MSG_LF(__func__ ":4\n"); /* rx offset calibration */ if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) || @@ -2984,7 +3017,7 @@ static uint32_t init_ddr(void) } if (err) return INITDRAM_ERR_O; - MSG_LF("init_ddr:5\n"); + MSG_LF(__func__ ":5\n"); /* PDX */ send_dbcmd(0x08840001); @@ -2994,7 +3027,7 @@ static uint32_t init_ddr(void) if (err) { return INITDRAM_ERR_O; } - MSG_LF("init_ddr:6\n"); + MSG_LF(__func__ ":6\n"); /* phy initialize end */ @@ -3019,7 +3052,7 @@ static uint32_t init_ddr(void) /* LPDDR4 MODE */ change_lpddr4_en(1); - MSG_LF("init_ddr:7\n"); + MSG_LF(__func__ ":7\n"); /* mask CS_MAP if RANKx is not found */ foreach_vch(ch) { @@ -3035,7 +3068,7 @@ static uint32_t init_ddr(void) ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); } else { foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { @@ -3053,7 +3086,7 @@ static uint32_t init_ddr(void) return INITDRAM_ERR_T | phytrainingok; } - MSG_LF("init_ddr:8\n"); + MSG_LF(__func__ ":8\n"); /* CACS DLY ADJUST */ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); @@ -3066,8 +3099,12 @@ static uint32_t init_ddr(void) if (ddr_phycaslice == 1) { for (i = 0; i < 6; i++) { - adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); - ddr_setval_s(ch, 2, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj + [i + + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); + ddr_setval_s(ch, 2, + _reg_PHY_CLK_CACS_SLAVE_DELAY_X + [i], data_l + adj ); } @@ -3075,12 +3112,11 @@ static uint32_t init_ddr(void) } update_dly(); - MSG_LF("init_ddr:9\n"); + MSG_LF(__func__ ":9\n"); /* H3 fix rd latency to avoid bug in elasitic buffer */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) adjust_rddqs_latency(); - } /* Adjust Write path latency */ if (ddrtbl_getval @@ -3088,21 +3124,19 @@ static uint32_t init_ddr(void) adjust_wpath_latency(); /* RDQLVL Training */ - if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) { + if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); - } err = rdqdm_man(); - if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) { + if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00); - } if (err) { return INITDRAM_ERR_T; } update_dly(); - MSG_LF("init_ddr:10\n"); + MSG_LF(__func__ ":10\n"); /* WDQLVL Training */ err = wdqdm_man(); @@ -3110,7 +3144,7 @@ static uint32_t init_ddr(void) return INITDRAM_ERR_T; } update_dly(); - MSG_LF("init_ddr:11\n"); + MSG_LF(__func__ ":11\n"); /* training complete, setup DBSC */ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || @@ -3121,7 +3155,7 @@ static uint32_t init_ddr(void) } dbsc_regset_post(); - MSG_LF("init_ddr:12\n"); + MSG_LF(__func__ ":12\n"); return phytrainingok; } @@ -3270,8 +3304,10 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) err = 2; } wdqdm_win[ch][cs][slice] = min_win; - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01); + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, + 0x01); } else { ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, ((ch_have_this_cs[1]) >> ch) & 0x01); @@ -3335,7 +3371,8 @@ static uint32_t wdqdm_man1(void) foreach_vch(ch) { high_dq[ch] = 0; for (slice = 0; slice < SLICE_CNT; slice++) { - k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> + (4 * slice)) & 0x0f; if (k >= 2) high_dq[ch] |= (1U << slice); } @@ -3569,7 +3606,8 @@ static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) [i]; } else { rdqdm_dly[ch][cs][slice][i] = data_l; - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l; + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = + data_l; } rdqdm_le[ch][cs][slice][i] = 0; rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; @@ -3674,8 +3712,8 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) win = (int32_t)rdqdm_te[ch][cs][slice + - SLICE_CNT * - k][i] - + SLICE_CNT * + k][i] - rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; if (i != 8) { if (min_win > win) @@ -3823,15 +3861,15 @@ static int32_t _find_change(uint64_t val, uint32_t dir) return i; } return VAL_END; - } else { - startval = (val >> dir) & 0x01; - for (i = dir - 1; i >= 0; i--) { - curval = (val >> i) & 0x01; - if (curval != startval) - return i; - } - return 0; } + + startval = (val >> dir) & 0x01; + for (i = dir - 1; i >= 0; i--) { + curval = (val >> i) & 0x01; + if (curval != startval) + return i; + } + return 0; } static uint32_t _rx_offset_cal_updn(uint32_t code) @@ -3875,9 +3913,8 @@ static uint32_t rx_offset_cal(void) ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01); foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) val[ch][slice][index] = 0; - } } } @@ -3907,7 +3944,8 @@ static uint32_t rx_offset_cal(void) } foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; + index++) { tmpval = val[ch][slice][index]; lsb = _find_change(tmpval, 0); msb = @@ -4088,15 +4126,19 @@ int32_t rcar_dram_init(void) if (prr_product == PRR_PRODUCT_H3) { if (prr_cut <= PRR_PRODUCT_11) { - p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[0][0]; + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[0][0]; } else { - p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[2][0]; + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[2][0]; } } else if (prr_product == PRR_PRODUCT_M3) { - p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[1][0]; + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[1][0]; } else if ((prr_product == PRR_PRODUCT_M3N) || (prr_product == PRR_PRODUCT_V3H)) { - p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[3][0]; + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[3][0]; } else { FATAL_MSG("BL2: DDR:Unknown Product\n"); return 0xff; @@ -4269,7 +4311,8 @@ void pvtcode_update(void) } if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - data_l = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000); + data_l = pvtp[ch] | (pvtn[ch] << 6) | + (tcal.tcomp_cal[ch] & 0xfffff000); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), data_l | 0x00020000); @@ -4373,12 +4416,12 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { tcal.init_cal[ch] = - (tcal. - init_cal[ch] & 0xfffff000) | (pvtn << 6) | - (pvtp); + (tcal.init_cal[ch] & 0xfffff000) | + (pvtn << 6) | + pvtp; } else { tcal.init_cal[ch] = - 0x00015000 | (pvtn << 6) | (pvtp); + 0x00015000 | (pvtn << 6) | pvtp; } } tcal.init_temp = 125; @@ -4386,7 +4429,7 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) } #ifndef ddr_qos_init_setting -/* for QoS init */ +/* For QoS init */ uint8_t get_boardcnf_phyvalid(void) { return ddr_phyvalid; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index 52dbac321..f8caade27 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -544,7 +545,10 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { } } }, -/* boardcnf[7] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 1rank) */ +/* + * boardcnf[7] RENESAS SALVATOR-X board with + * H3 Ver.2.0 or later/SIP(8Gbit 1rank) + */ { 0x0f, 0x01, @@ -635,7 +639,10 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { } } }, -/* boardcnf[8] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 2rank) */ +/* + * boardcnf[8] RENESAS SALVATOR-X board with + * H3 Ver.2.0 or later/SIP(8Gbit 2rank) + */ { #if RCAR_DRAM_CHANNEL == 5 0x05, @@ -1766,13 +1773,16 @@ static uint32_t _board_judge(void) } else if (prr_product == PRR_PRODUCT_M3N) { /* RENESAS SALVATOR-X (M3-N/SIP) */ brd = 11; - } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_20)) { + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut <= PRR_PRODUCT_20)) { /* RENESAS SALVATOR-X (M3-W/SIP) */ brd = 0; - } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut < PRR_PRODUCT_30)) { /* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */ brd = 19; - } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut >= PRR_PRODUCT_30)) { + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut >= PRR_PRODUCT_30)) { /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */ brd = 18; } -- cgit v1.2.3 From f3f5aba6e886b95923ac500e8e71c19551143d28 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 8 Aug 2019 17:13:03 +0200 Subject: rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers Clean up the DDR B header files and remove checkpatch errors. Signed-off-by: Marek Vasut Change-Id: I9648ef5511df299688fd5284513812d32a1f8064 --- .../renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h | 26 +- .../staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h | 3 +- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h | 807 +++++++------- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h | 1003 +++++++++--------- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h | 861 +++++++-------- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h | 1099 ++++++++++---------- 6 files changed, 1903 insertions(+), 1896 deletions(-) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h index 0bc2bc160..8eb3859a3 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h @@ -1,13 +1,14 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #define RCAR_DDR_VERSION "rev.0.36" -#define DRAM_CH_CNT (0x04) -#define SLICE_CNT (0x04) -#define CS_CNT (0x02) +#define DRAM_CH_CNT 0x04 +#define SLICE_CNT 0x04 +#define CS_CNT 0x02 /* order : CS0A, CS0B, CS1A, CS1B */ #define CSAB_CNT (CS_CNT * 2) @@ -16,15 +17,16 @@ #define CHAB_CNT (DRAM_CH_CNT * 2) /* pll setting */ -#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) /((b) * (diva))) +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) #define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) /* for ddr deisity setting */ -#define DBMEMCONF_REG(d3, row, bank, col, dw) \ +#define DBMEMCONF_REG(d3, row, bank, col, dw) \ ((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw)) -#define DBMEMCONF_REGD(density) \ -(DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (29-3-10-2), 3, 10, 2)) +#define DBMEMCONF_REGD(density) \ + (DBMEMCONF_REG((density) % 2, ((density) + 1) / \ + 2 + (29 - 3 - 10 - 2), 3, 10, 2)) #define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) @@ -44,10 +46,10 @@ #define CPG_CPGWPR (CPG_BASE + 0x0900U) #define CPG_SRSTCLR4 (CPG_BASE + 0x0950U) -#define CPG_FRQCRB_KICK_BIT (1U<<31) -#define CPG_PLLECR_PLL3E_BIT (1U<<3) -#define CPG_PLLECR_PLL3ST_BIT (1U<<11) -#define CPG_ZB3CKCR_ZB3ST_BIT (1U<<11) +#define CPG_FRQCRB_KICK_BIT BIT(31) +#define CPG_PLLECR_PLL3E_BIT BIT(3) +#define CPG_PLLECR_PLL3ST_BIT BIT(11) +#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11) #define RST_BASE (0xE6160000U) #define RST_MODEMR (RST_BASE + 0x0060U) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h index 7f27b3989..adf8dab18 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h index 6fa9ab99d..69db2a73d 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,418 +24,418 @@ #define DDR_PI_REGSET_NUM_H3 181 static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = { -/*0400*/ 0x000004f0, -/*0401*/ 0x00000000, -/*0402*/ 0x00000000, -/*0403*/ 0x00000100, -/*0404*/ 0x01003c0c, -/*0405*/ 0x02003c0c, -/*0406*/ 0x00010300, -/*0407*/ 0x04000100, -/*0408*/ 0x00000300, -/*0409*/ 0x000700c0, -/*040a*/ 0x00b00201, -/*040b*/ 0x00000020, -/*040c*/ 0x00000000, -/*040d*/ 0x00000000, -/*040e*/ 0x00000000, -/*040f*/ 0x00000000, -/*0410*/ 0x00000000, -/*0411*/ 0x00000000, -/*0412*/ 0x00000000, -/*0413*/ 0x09000000, -/*0414*/ 0x04080000, -/*0415*/ 0x04080400, -/*0416*/ 0x00000000, -/*0417*/ 0x32103210, -/*0418*/ 0x00800708, -/*0419*/ 0x000f000c, -/*041a*/ 0x00000100, -/*041b*/ 0x55aa55aa, -/*041c*/ 0x33cc33cc, -/*041d*/ 0x0ff00ff0, -/*041e*/ 0x0f0ff0f0, -/*041f*/ 0x00008e38, -/*0420*/ 0x76543210, -/*0421*/ 0x00000001, -/*0422*/ 0x00000000, -/*0423*/ 0x00000000, -/*0424*/ 0x00000000, -/*0425*/ 0x00000000, -/*0426*/ 0x00000000, -/*0427*/ 0x00000000, -/*0428*/ 0x00000000, -/*0429*/ 0x00000000, -/*042a*/ 0x00000000, -/*042b*/ 0x00000000, -/*042c*/ 0x00000000, -/*042d*/ 0x00000000, -/*042e*/ 0x00000000, -/*042f*/ 0x00000000, -/*0430*/ 0x00000000, -/*0431*/ 0x00000000, -/*0432*/ 0x00000000, -/*0433*/ 0x00200000, -/*0434*/ 0x08200820, -/*0435*/ 0x08200820, -/*0436*/ 0x08200820, -/*0437*/ 0x08200820, -/*0438*/ 0x08200820, -/*0439*/ 0x00000820, -/*043a*/ 0x03000300, -/*043b*/ 0x03000300, -/*043c*/ 0x03000300, -/*043d*/ 0x03000300, -/*043e*/ 0x00000300, -/*043f*/ 0x00000000, -/*0440*/ 0x00000000, -/*0441*/ 0x00000000, -/*0442*/ 0x00000000, -/*0443*/ 0x00a000a0, -/*0444*/ 0x00a000a0, -/*0445*/ 0x00a000a0, -/*0446*/ 0x00a000a0, -/*0447*/ 0x00a000a0, -/*0448*/ 0x00a000a0, -/*0449*/ 0x00a000a0, -/*044a*/ 0x00a000a0, -/*044b*/ 0x00a000a0, -/*044c*/ 0x01040109, -/*044d*/ 0x00000200, -/*044e*/ 0x01000000, -/*044f*/ 0x00000200, -/*0450*/ 0x4041a141, -/*0451*/ 0xc00141a0, -/*0452*/ 0x0e0100c0, -/*0453*/ 0x0010000c, -/*0454*/ 0x0c064208, -/*0455*/ 0x000f0c18, -/*0456*/ 0x00e00140, -/*0457*/ 0x00000c20 + /*0400*/ 0x000004f0, + /*0401*/ 0x00000000, + /*0402*/ 0x00000000, + /*0403*/ 0x00000100, + /*0404*/ 0x01003c0c, + /*0405*/ 0x02003c0c, + /*0406*/ 0x00010300, + /*0407*/ 0x04000100, + /*0408*/ 0x00000300, + /*0409*/ 0x000700c0, + /*040a*/ 0x00b00201, + /*040b*/ 0x00000020, + /*040c*/ 0x00000000, + /*040d*/ 0x00000000, + /*040e*/ 0x00000000, + /*040f*/ 0x00000000, + /*0410*/ 0x00000000, + /*0411*/ 0x00000000, + /*0412*/ 0x00000000, + /*0413*/ 0x09000000, + /*0414*/ 0x04080000, + /*0415*/ 0x04080400, + /*0416*/ 0x00000000, + /*0417*/ 0x32103210, + /*0418*/ 0x00800708, + /*0419*/ 0x000f000c, + /*041a*/ 0x00000100, + /*041b*/ 0x55aa55aa, + /*041c*/ 0x33cc33cc, + /*041d*/ 0x0ff00ff0, + /*041e*/ 0x0f0ff0f0, + /*041f*/ 0x00008e38, + /*0420*/ 0x76543210, + /*0421*/ 0x00000001, + /*0422*/ 0x00000000, + /*0423*/ 0x00000000, + /*0424*/ 0x00000000, + /*0425*/ 0x00000000, + /*0426*/ 0x00000000, + /*0427*/ 0x00000000, + /*0428*/ 0x00000000, + /*0429*/ 0x00000000, + /*042a*/ 0x00000000, + /*042b*/ 0x00000000, + /*042c*/ 0x00000000, + /*042d*/ 0x00000000, + /*042e*/ 0x00000000, + /*042f*/ 0x00000000, + /*0430*/ 0x00000000, + /*0431*/ 0x00000000, + /*0432*/ 0x00000000, + /*0433*/ 0x00200000, + /*0434*/ 0x08200820, + /*0435*/ 0x08200820, + /*0436*/ 0x08200820, + /*0437*/ 0x08200820, + /*0438*/ 0x08200820, + /*0439*/ 0x00000820, + /*043a*/ 0x03000300, + /*043b*/ 0x03000300, + /*043c*/ 0x03000300, + /*043d*/ 0x03000300, + /*043e*/ 0x00000300, + /*043f*/ 0x00000000, + /*0440*/ 0x00000000, + /*0441*/ 0x00000000, + /*0442*/ 0x00000000, + /*0443*/ 0x00a000a0, + /*0444*/ 0x00a000a0, + /*0445*/ 0x00a000a0, + /*0446*/ 0x00a000a0, + /*0447*/ 0x00a000a0, + /*0448*/ 0x00a000a0, + /*0449*/ 0x00a000a0, + /*044a*/ 0x00a000a0, + /*044b*/ 0x00a000a0, + /*044c*/ 0x01040109, + /*044d*/ 0x00000200, + /*044e*/ 0x01000000, + /*044f*/ 0x00000200, + /*0450*/ 0x4041a141, + /*0451*/ 0xc00141a0, + /*0452*/ 0x0e0100c0, + /*0453*/ 0x0010000c, + /*0454*/ 0x0c064208, + /*0455*/ 0x000f0c18, + /*0456*/ 0x00e00140, + /*0457*/ 0x00000c20 }; static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = { -/*0600*/ 0x00000000, -/*0601*/ 0x00000000, -/*0602*/ 0x00000000, -/*0603*/ 0x00000000, -/*0604*/ 0x00000000, -/*0605*/ 0x00000000, -/*0606*/ 0x00000002, -/*0607*/ 0x00000000, -/*0608*/ 0x00000000, -/*0609*/ 0x00000000, -/*060a*/ 0x00400320, -/*060b*/ 0x00000040, -/*060c*/ 0x00dcba98, -/*060d*/ 0x00000000, -/*060e*/ 0x00dcba98, -/*060f*/ 0x01000000, -/*0610*/ 0x00020003, -/*0611*/ 0x00000000, -/*0612*/ 0x00000000, -/*0613*/ 0x00000000, -/*0614*/ 0x00002a01, -/*0615*/ 0x00000015, -/*0616*/ 0x00000015, -/*0617*/ 0x0000002a, -/*0618*/ 0x00000033, -/*0619*/ 0x0000000c, -/*061a*/ 0x0000000c, -/*061b*/ 0x00000033, -/*061c*/ 0x00418820, -/*061d*/ 0x003f0000, -/*061e*/ 0x0000003f, -/*061f*/ 0x0002006e, -/*0620*/ 0x02000200, -/*0621*/ 0x02000200, -/*0622*/ 0x00000200, -/*0623*/ 0x42080010, -/*0624*/ 0x00000003 + /*0600*/ 0x00000000, + /*0601*/ 0x00000000, + /*0602*/ 0x00000000, + /*0603*/ 0x00000000, + /*0604*/ 0x00000000, + /*0605*/ 0x00000000, + /*0606*/ 0x00000002, + /*0607*/ 0x00000000, + /*0608*/ 0x00000000, + /*0609*/ 0x00000000, + /*060a*/ 0x00400320, + /*060b*/ 0x00000040, + /*060c*/ 0x00dcba98, + /*060d*/ 0x00000000, + /*060e*/ 0x00dcba98, + /*060f*/ 0x01000000, + /*0610*/ 0x00020003, + /*0611*/ 0x00000000, + /*0612*/ 0x00000000, + /*0613*/ 0x00000000, + /*0614*/ 0x00002a01, + /*0615*/ 0x00000015, + /*0616*/ 0x00000015, + /*0617*/ 0x0000002a, + /*0618*/ 0x00000033, + /*0619*/ 0x0000000c, + /*061a*/ 0x0000000c, + /*061b*/ 0x00000033, + /*061c*/ 0x00418820, + /*061d*/ 0x003f0000, + /*061e*/ 0x0000003f, + /*061f*/ 0x0002006e, + /*0620*/ 0x02000200, + /*0621*/ 0x02000200, + /*0622*/ 0x00000200, + /*0623*/ 0x42080010, + /*0624*/ 0x00000003 }; static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = { -/*0680*/ 0x04040404, -/*0681*/ 0x00000404, -/*0682*/ 0x00000000, -/*0683*/ 0x00000000, -/*0684*/ 0x00000000, -/*0685*/ 0x00000000, -/*0686*/ 0x00000002, -/*0687*/ 0x00000000, -/*0688*/ 0x00000000, -/*0689*/ 0x00000000, -/*068a*/ 0x00400320, -/*068b*/ 0x00000040, -/*068c*/ 0x00000000, -/*068d*/ 0x00000000, -/*068e*/ 0x00000000, -/*068f*/ 0x01000000, -/*0690*/ 0x00020003, -/*0691*/ 0x00000000, -/*0692*/ 0x00000000, -/*0693*/ 0x00000000, -/*0694*/ 0x00002a01, -/*0695*/ 0x00000015, -/*0696*/ 0x00000015, -/*0697*/ 0x0000002a, -/*0698*/ 0x00000033, -/*0699*/ 0x0000000c, -/*069a*/ 0x0000000c, -/*069b*/ 0x00000033, -/*069c*/ 0x00000000, -/*069d*/ 0x00000000, -/*069e*/ 0x00000000, -/*069f*/ 0x0002006e, -/*06a0*/ 0x02000200, -/*06a1*/ 0x02000200, -/*06a2*/ 0x00000200, -/*06a3*/ 0x42080010, -/*06a4*/ 0x00000003 + /*0680*/ 0x04040404, + /*0681*/ 0x00000404, + /*0682*/ 0x00000000, + /*0683*/ 0x00000000, + /*0684*/ 0x00000000, + /*0685*/ 0x00000000, + /*0686*/ 0x00000002, + /*0687*/ 0x00000000, + /*0688*/ 0x00000000, + /*0689*/ 0x00000000, + /*068a*/ 0x00400320, + /*068b*/ 0x00000040, + /*068c*/ 0x00000000, + /*068d*/ 0x00000000, + /*068e*/ 0x00000000, + /*068f*/ 0x01000000, + /*0690*/ 0x00020003, + /*0691*/ 0x00000000, + /*0692*/ 0x00000000, + /*0693*/ 0x00000000, + /*0694*/ 0x00002a01, + /*0695*/ 0x00000015, + /*0696*/ 0x00000015, + /*0697*/ 0x0000002a, + /*0698*/ 0x00000033, + /*0699*/ 0x0000000c, + /*069a*/ 0x0000000c, + /*069b*/ 0x00000033, + /*069c*/ 0x00000000, + /*069d*/ 0x00000000, + /*069e*/ 0x00000000, + /*069f*/ 0x0002006e, + /*06a0*/ 0x02000200, + /*06a1*/ 0x02000200, + /*06a2*/ 0x00000200, + /*06a3*/ 0x42080010, + /*06a4*/ 0x00000003 }; static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = { -/*0700*/ 0x00000001, -/*0701*/ 0x00000000, -/*0702*/ 0x00000005, -/*0703*/ 0x04000f00, -/*0704*/ 0x00020080, -/*0705*/ 0x00020055, -/*0706*/ 0x00000000, -/*0707*/ 0x00000000, -/*0708*/ 0x00000000, -/*0709*/ 0x00000050, -/*070a*/ 0x00000000, -/*070b*/ 0x01010100, -/*070c*/ 0x00000200, -/*070d*/ 0x00001102, -/*070e*/ 0x00000000, -/*070f*/ 0x000f1f00, -/*0710*/ 0x0f1f0f1f, -/*0711*/ 0x0f1f0f1f, -/*0712*/ 0x00020003, -/*0713*/ 0x02000200, -/*0714*/ 0x00000200, -/*0715*/ 0x00001102, -/*0716*/ 0x00000064, -/*0717*/ 0x00000000, -/*0718*/ 0x00000000, -/*0719*/ 0x00000502, -/*071a*/ 0x027f6e00, -/*071b*/ 0x007f007f, -/*071c*/ 0x00007f3c, -/*071d*/ 0x00047f6e, -/*071e*/ 0x0003154f, -/*071f*/ 0x0001154f, -/*0720*/ 0x0001154f, -/*0721*/ 0x0001154f, -/*0722*/ 0x0001154f, -/*0723*/ 0x00003fee, -/*0724*/ 0x0001154f, -/*0725*/ 0x00003fee, -/*0726*/ 0x0001154f, -/*0727*/ 0x00007f3c, -/*0728*/ 0x0001154f, -/*0729*/ 0x00000000, -/*072a*/ 0x00000000, -/*072b*/ 0x00000000, -/*072c*/ 0x65000000, -/*072d*/ 0x00000000, -/*072e*/ 0x00000000, -/*072f*/ 0x00000201, -/*0730*/ 0x00000000, -/*0731*/ 0x00000000, -/*0732*/ 0x00000000, -/*0733*/ 0x00000000, -/*0734*/ 0x00000000, -/*0735*/ 0x00000000, -/*0736*/ 0x00000000, -/*0737*/ 0x00000000, -/*0738*/ 0x00000000, -/*0739*/ 0x00000000, -/*073a*/ 0x00000000 + /*0700*/ 0x00000001, + /*0701*/ 0x00000000, + /*0702*/ 0x00000005, + /*0703*/ 0x04000f00, + /*0704*/ 0x00020080, + /*0705*/ 0x00020055, + /*0706*/ 0x00000000, + /*0707*/ 0x00000000, + /*0708*/ 0x00000000, + /*0709*/ 0x00000050, + /*070a*/ 0x00000000, + /*070b*/ 0x01010100, + /*070c*/ 0x00000200, + /*070d*/ 0x00001102, + /*070e*/ 0x00000000, + /*070f*/ 0x000f1f00, + /*0710*/ 0x0f1f0f1f, + /*0711*/ 0x0f1f0f1f, + /*0712*/ 0x00020003, + /*0713*/ 0x02000200, + /*0714*/ 0x00000200, + /*0715*/ 0x00001102, + /*0716*/ 0x00000064, + /*0717*/ 0x00000000, + /*0718*/ 0x00000000, + /*0719*/ 0x00000502, + /*071a*/ 0x027f6e00, + /*071b*/ 0x007f007f, + /*071c*/ 0x00007f3c, + /*071d*/ 0x00047f6e, + /*071e*/ 0x0003154f, + /*071f*/ 0x0001154f, + /*0720*/ 0x0001154f, + /*0721*/ 0x0001154f, + /*0722*/ 0x0001154f, + /*0723*/ 0x00003fee, + /*0724*/ 0x0001154f, + /*0725*/ 0x00003fee, + /*0726*/ 0x0001154f, + /*0727*/ 0x00007f3c, + /*0728*/ 0x0001154f, + /*0729*/ 0x00000000, + /*072a*/ 0x00000000, + /*072b*/ 0x00000000, + /*072c*/ 0x65000000, + /*072d*/ 0x00000000, + /*072e*/ 0x00000000, + /*072f*/ 0x00000201, + /*0730*/ 0x00000000, + /*0731*/ 0x00000000, + /*0732*/ 0x00000000, + /*0733*/ 0x00000000, + /*0734*/ 0x00000000, + /*0735*/ 0x00000000, + /*0736*/ 0x00000000, + /*0737*/ 0x00000000, + /*0738*/ 0x00000000, + /*0739*/ 0x00000000, + /*073a*/ 0x00000000 }; static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = { -/*0200*/ 0x00000b00, -/*0201*/ 0x00000100, -/*0202*/ 0x00000000, -/*0203*/ 0x0000ffff, -/*0204*/ 0x00000000, -/*0205*/ 0x0000ffff, -/*0206*/ 0x00000000, -/*0207*/ 0x304cffff, -/*0208*/ 0x00000200, -/*0209*/ 0x00000200, -/*020a*/ 0x00000200, -/*020b*/ 0x00000200, -/*020c*/ 0x0000304c, -/*020d*/ 0x00000200, -/*020e*/ 0x00000200, -/*020f*/ 0x00000200, -/*0210*/ 0x00000200, -/*0211*/ 0x0000304c, -/*0212*/ 0x00000200, -/*0213*/ 0x00000200, -/*0214*/ 0x00000200, -/*0215*/ 0x00000200, -/*0216*/ 0x00010000, -/*0217*/ 0x00000003, -/*0218*/ 0x01000001, -/*0219*/ 0x00000000, -/*021a*/ 0x00000000, -/*021b*/ 0x00000000, -/*021c*/ 0x00000000, -/*021d*/ 0x00000000, -/*021e*/ 0x00000000, -/*021f*/ 0x00000000, -/*0220*/ 0x00000000, -/*0221*/ 0x00000000, -/*0222*/ 0x00000000, -/*0223*/ 0x00000000, -/*0224*/ 0x00000000, -/*0225*/ 0x00000000, -/*0226*/ 0x00000000, -/*0227*/ 0x00000000, -/*0228*/ 0x00000000, -/*0229*/ 0x0f000101, -/*022a*/ 0x08492d25, -/*022b*/ 0x500e0c04, -/*022c*/ 0x0002500e, -/*022d*/ 0x00460003, -/*022e*/ 0x182600cf, -/*022f*/ 0x182600cf, -/*0230*/ 0x00000005, -/*0231*/ 0x00000000, -/*0232*/ 0x00000000, -/*0233*/ 0x00000000, -/*0234*/ 0x00000000, -/*0235*/ 0x00000000, -/*0236*/ 0x00000000, -/*0237*/ 0x00000000, -/*0238*/ 0x01000000, -/*0239*/ 0x00040404, -/*023a*/ 0x01280a00, -/*023b*/ 0x00000000, -/*023c*/ 0x000f0000, -/*023d*/ 0x00001803, -/*023e*/ 0x00000000, -/*023f*/ 0x00000000, -/*0240*/ 0x00060002, -/*0241*/ 0x00010001, -/*0242*/ 0x01000101, -/*0243*/ 0x04020201, -/*0244*/ 0x00080804, -/*0245*/ 0x00000000, -/*0246*/ 0x08030000, -/*0247*/ 0x15150408, -/*0248*/ 0x00000000, -/*0249*/ 0x00000000, -/*024a*/ 0x00000000, -/*024b*/ 0x001e0f0f, -/*024c*/ 0x00000000, -/*024d*/ 0x01000300, -/*024e*/ 0x00000000, -/*024f*/ 0x00000000, -/*0250*/ 0x01000000, -/*0251*/ 0x00010101, -/*0252*/ 0x000e0e0e, -/*0253*/ 0x000c0c0c, -/*0254*/ 0x02060601, -/*0255*/ 0x00000000, -/*0256*/ 0x00000003, -/*0257*/ 0x00181703, -/*0258*/ 0x00280006, -/*0259*/ 0x00280016, -/*025a*/ 0x00000016, -/*025b*/ 0x00000000, -/*025c*/ 0x00000000, -/*025d*/ 0x00000000, -/*025e*/ 0x140a0000, -/*025f*/ 0x0005010a, -/*0260*/ 0x03018d03, -/*0261*/ 0x000a018d, -/*0262*/ 0x00060100, -/*0263*/ 0x01000006, -/*0264*/ 0x018e018e, -/*0265*/ 0x018e0100, -/*0266*/ 0x1111018e, -/*0267*/ 0x10010204, -/*0268*/ 0x09090650, -/*0269*/ 0x20110202, -/*026a*/ 0x00201000, -/*026b*/ 0x00201000, -/*026c*/ 0x04041000, -/*026d*/ 0x18020100, -/*026e*/ 0x00010118, -/*026f*/ 0x004b004a, -/*0270*/ 0x050f0000, -/*0271*/ 0x0c01021e, -/*0272*/ 0x34000000, -/*0273*/ 0x00000000, -/*0274*/ 0x00000000, -/*0275*/ 0x00000000, -/*0276*/ 0x312ed400, -/*0277*/ 0xd4111132, -/*0278*/ 0x1132312e, -/*0279*/ 0x312ed411, -/*027a*/ 0x00111132, -/*027b*/ 0x32312ed4, -/*027c*/ 0x2ed41111, -/*027d*/ 0x11113231, -/*027e*/ 0x32312ed4, -/*027f*/ 0xd4001111, -/*0280*/ 0x1132312e, -/*0281*/ 0x312ed411, -/*0282*/ 0xd4111132, -/*0283*/ 0x1132312e, -/*0284*/ 0x2ed40011, -/*0285*/ 0x11113231, -/*0286*/ 0x32312ed4, -/*0287*/ 0x2ed41111, -/*0288*/ 0x11113231, -/*0289*/ 0x00020000, -/*028a*/ 0x018d018d, -/*028b*/ 0x0c08018d, -/*028c*/ 0x1f121d22, -/*028d*/ 0x4301b344, -/*028e*/ 0x10172006, -/*028f*/ 0x121d220c, -/*0290*/ 0x01b3441f, -/*0291*/ 0x17200643, -/*0292*/ 0x1d220c10, -/*0293*/ 0x00001f12, -/*0294*/ 0x4301b344, -/*0295*/ 0x10172006, -/*0296*/ 0x00020002, -/*0297*/ 0x00020002, -/*0298*/ 0x00020002, -/*0299*/ 0x00020002, -/*029a*/ 0x00020002, -/*029b*/ 0x00000000, -/*029c*/ 0x00000000, -/*029d*/ 0x00000000, -/*029e*/ 0x00000000, -/*029f*/ 0x00000000, -/*02a0*/ 0x00000000, -/*02a1*/ 0x00000000, -/*02a2*/ 0x00000000, -/*02a3*/ 0x00000000, -/*02a4*/ 0x00000000, -/*02a5*/ 0x00000000, -/*02a6*/ 0x00000000, -/*02a7*/ 0x01000400, -/*02a8*/ 0x00304c00, -/*02a9*/ 0x0001e2f8, -/*02aa*/ 0x0000304c, -/*02ab*/ 0x0001e2f8, -/*02ac*/ 0x0000304c, -/*02ad*/ 0x0001e2f8, -/*02ae*/ 0x08000000, -/*02af*/ 0x00000100, -/*02b0*/ 0x00000000, -/*02b1*/ 0x00000000, -/*02b2*/ 0x00000000, -/*02b3*/ 0x00000000, -/*02b4*/ 0x00000002 + /*0200*/ 0x00000b00, + /*0201*/ 0x00000100, + /*0202*/ 0x00000000, + /*0203*/ 0x0000ffff, + /*0204*/ 0x00000000, + /*0205*/ 0x0000ffff, + /*0206*/ 0x00000000, + /*0207*/ 0x304cffff, + /*0208*/ 0x00000200, + /*0209*/ 0x00000200, + /*020a*/ 0x00000200, + /*020b*/ 0x00000200, + /*020c*/ 0x0000304c, + /*020d*/ 0x00000200, + /*020e*/ 0x00000200, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x0000304c, + /*0212*/ 0x00000200, + /*0213*/ 0x00000200, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00010000, + /*0217*/ 0x00000003, + /*0218*/ 0x01000001, + /*0219*/ 0x00000000, + /*021a*/ 0x00000000, + /*021b*/ 0x00000000, + /*021c*/ 0x00000000, + /*021d*/ 0x00000000, + /*021e*/ 0x00000000, + /*021f*/ 0x00000000, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x0f000101, + /*022a*/ 0x08492d25, + /*022b*/ 0x500e0c04, + /*022c*/ 0x0002500e, + /*022d*/ 0x00460003, + /*022e*/ 0x182600cf, + /*022f*/ 0x182600cf, + /*0230*/ 0x00000005, + /*0231*/ 0x00000000, + /*0232*/ 0x00000000, + /*0233*/ 0x00000000, + /*0234*/ 0x00000000, + /*0235*/ 0x00000000, + /*0236*/ 0x00000000, + /*0237*/ 0x00000000, + /*0238*/ 0x01000000, + /*0239*/ 0x00040404, + /*023a*/ 0x01280a00, + /*023b*/ 0x00000000, + /*023c*/ 0x000f0000, + /*023d*/ 0x00001803, + /*023e*/ 0x00000000, + /*023f*/ 0x00000000, + /*0240*/ 0x00060002, + /*0241*/ 0x00010001, + /*0242*/ 0x01000101, + /*0243*/ 0x04020201, + /*0244*/ 0x00080804, + /*0245*/ 0x00000000, + /*0246*/ 0x08030000, + /*0247*/ 0x15150408, + /*0248*/ 0x00000000, + /*0249*/ 0x00000000, + /*024a*/ 0x00000000, + /*024b*/ 0x001e0f0f, + /*024c*/ 0x00000000, + /*024d*/ 0x01000300, + /*024e*/ 0x00000000, + /*024f*/ 0x00000000, + /*0250*/ 0x01000000, + /*0251*/ 0x00010101, + /*0252*/ 0x000e0e0e, + /*0253*/ 0x000c0c0c, + /*0254*/ 0x02060601, + /*0255*/ 0x00000000, + /*0256*/ 0x00000003, + /*0257*/ 0x00181703, + /*0258*/ 0x00280006, + /*0259*/ 0x00280016, + /*025a*/ 0x00000016, + /*025b*/ 0x00000000, + /*025c*/ 0x00000000, + /*025d*/ 0x00000000, + /*025e*/ 0x140a0000, + /*025f*/ 0x0005010a, + /*0260*/ 0x03018d03, + /*0261*/ 0x000a018d, + /*0262*/ 0x00060100, + /*0263*/ 0x01000006, + /*0264*/ 0x018e018e, + /*0265*/ 0x018e0100, + /*0266*/ 0x1111018e, + /*0267*/ 0x10010204, + /*0268*/ 0x09090650, + /*0269*/ 0x20110202, + /*026a*/ 0x00201000, + /*026b*/ 0x00201000, + /*026c*/ 0x04041000, + /*026d*/ 0x18020100, + /*026e*/ 0x00010118, + /*026f*/ 0x004b004a, + /*0270*/ 0x050f0000, + /*0271*/ 0x0c01021e, + /*0272*/ 0x34000000, + /*0273*/ 0x00000000, + /*0274*/ 0x00000000, + /*0275*/ 0x00000000, + /*0276*/ 0x312ed400, + /*0277*/ 0xd4111132, + /*0278*/ 0x1132312e, + /*0279*/ 0x312ed411, + /*027a*/ 0x00111132, + /*027b*/ 0x32312ed4, + /*027c*/ 0x2ed41111, + /*027d*/ 0x11113231, + /*027e*/ 0x32312ed4, + /*027f*/ 0xd4001111, + /*0280*/ 0x1132312e, + /*0281*/ 0x312ed411, + /*0282*/ 0xd4111132, + /*0283*/ 0x1132312e, + /*0284*/ 0x2ed40011, + /*0285*/ 0x11113231, + /*0286*/ 0x32312ed4, + /*0287*/ 0x2ed41111, + /*0288*/ 0x11113231, + /*0289*/ 0x00020000, + /*028a*/ 0x018d018d, + /*028b*/ 0x0c08018d, + /*028c*/ 0x1f121d22, + /*028d*/ 0x4301b344, + /*028e*/ 0x10172006, + /*028f*/ 0x121d220c, + /*0290*/ 0x01b3441f, + /*0291*/ 0x17200643, + /*0292*/ 0x1d220c10, + /*0293*/ 0x00001f12, + /*0294*/ 0x4301b344, + /*0295*/ 0x10172006, + /*0296*/ 0x00020002, + /*0297*/ 0x00020002, + /*0298*/ 0x00020002, + /*0299*/ 0x00020002, + /*029a*/ 0x00020002, + /*029b*/ 0x00000000, + /*029c*/ 0x00000000, + /*029d*/ 0x00000000, + /*029e*/ 0x00000000, + /*029f*/ 0x00000000, + /*02a0*/ 0x00000000, + /*02a1*/ 0x00000000, + /*02a2*/ 0x00000000, + /*02a3*/ 0x00000000, + /*02a4*/ 0x00000000, + /*02a5*/ 0x00000000, + /*02a6*/ 0x00000000, + /*02a7*/ 0x01000400, + /*02a8*/ 0x00304c00, + /*02a9*/ 0x0001e2f8, + /*02aa*/ 0x0000304c, + /*02ab*/ 0x0001e2f8, + /*02ac*/ 0x0000304c, + /*02ad*/ 0x0001e2f8, + /*02ae*/ 0x08000000, + /*02af*/ 0x00000100, + /*02b0*/ 0x00000000, + /*02b1*/ 0x00000000, + /*02b2*/ 0x00000000, + /*02b3*/ 0x00000000, + /*02b4*/ 0x00000002 }; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h index 6e4c30eb8..b94f308fb 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,516 +23,516 @@ #define DDR_PHY_ADR_G_REGSET_NUM_H3VER2 79 #define DDR_PI_REGSET_NUM_H3VER2 245 -static const uint32_t - DDR_PHY_SLICE_REGSET_H3VER2[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = { -/*0400*/ 0x76543210, -/*0401*/ 0x0004f008, -/*0402*/ 0x00020133, -/*0403*/ 0x00000000, -/*0404*/ 0x00000000, -/*0405*/ 0x00010000, -/*0406*/ 0x016e6e0e, -/*0407*/ 0x026e6e0e, -/*0408*/ 0x00010300, -/*0409*/ 0x04000100, -/*040a*/ 0x01000000, -/*040b*/ 0x00000000, -/*040c*/ 0x00000000, -/*040d*/ 0x00000100, -/*040e*/ 0x001700c0, -/*040f*/ 0x020100b0, -/*0410*/ 0x00030020, -/*0411*/ 0x00000000, -/*0412*/ 0x00000000, -/*0413*/ 0x00000000, -/*0414*/ 0x00000000, -/*0415*/ 0x00000000, -/*0416*/ 0x00000000, -/*0417*/ 0x00000000, -/*0418*/ 0x09000000, -/*0419*/ 0x04080000, -/*041a*/ 0x04080400, -/*041b*/ 0x08000000, -/*041c*/ 0x0c008007, -/*041d*/ 0x00000f00, -/*041e*/ 0x00000100, -/*041f*/ 0x55aa55aa, -/*0420*/ 0x33cc33cc, -/*0421*/ 0x0ff00ff0, -/*0422*/ 0x0f0ff0f0, -/*0423*/ 0x00018e38, -/*0424*/ 0x00000000, -/*0425*/ 0x00000000, -/*0426*/ 0x00000000, -/*0427*/ 0x00000000, -/*0428*/ 0x00000000, -/*0429*/ 0x00000000, -/*042a*/ 0x00000000, -/*042b*/ 0x00000000, -/*042c*/ 0x00000000, -/*042d*/ 0x00000000, -/*042e*/ 0x00000000, -/*042f*/ 0x00000000, -/*0430*/ 0x00000000, -/*0431*/ 0x00000000, -/*0432*/ 0x00000000, -/*0433*/ 0x00000000, -/*0434*/ 0x00000000, -/*0435*/ 0x00000000, -/*0436*/ 0x00000000, -/*0437*/ 0x00000000, -/*0438*/ 0x00000104, -/*0439*/ 0x00082020, -/*043a*/ 0x08200820, -/*043b*/ 0x08200820, -/*043c*/ 0x08200820, -/*043d*/ 0x08200820, -/*043e*/ 0x08200820, -/*043f*/ 0x00000000, -/*0440*/ 0x00000000, -/*0441*/ 0x03000300, -/*0442*/ 0x03000300, -/*0443*/ 0x03000300, -/*0444*/ 0x03000300, -/*0445*/ 0x00000300, -/*0446*/ 0x00000000, -/*0447*/ 0x00000000, -/*0448*/ 0x00000000, -/*0449*/ 0x00000000, -/*044a*/ 0x00000000, -/*044b*/ 0x00a000a0, -/*044c*/ 0x00a000a0, -/*044d*/ 0x00a000a0, -/*044e*/ 0x00a000a0, -/*044f*/ 0x00a000a0, -/*0450*/ 0x00a000a0, -/*0451*/ 0x00a000a0, -/*0452*/ 0x00a000a0, -/*0453*/ 0x00a000a0, -/*0454*/ 0x01040109, -/*0455*/ 0x00000200, -/*0456*/ 0x01000000, -/*0457*/ 0x00000200, -/*0458*/ 0x00000004, -/*0459*/ 0x4041a141, -/*045a*/ 0xc00141a0, -/*045b*/ 0x0e0000c0, -/*045c*/ 0x0010000c, -/*045d*/ 0x063e4208, -/*045e*/ 0x0f0c180c, -/*045f*/ 0x00e00140, -/*0460*/ 0x00000c20 +static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2 + [DDR_PHY_SLICE_REGSET_NUM_H3VER2] = { + /*0400*/ 0x76543210, + /*0401*/ 0x0004f008, + /*0402*/ 0x00020133, + /*0403*/ 0x00000000, + /*0404*/ 0x00000000, + /*0405*/ 0x00010000, + /*0406*/ 0x016e6e0e, + /*0407*/ 0x026e6e0e, + /*0408*/ 0x00010300, + /*0409*/ 0x04000100, + /*040a*/ 0x01000000, + /*040b*/ 0x00000000, + /*040c*/ 0x00000000, + /*040d*/ 0x00000100, + /*040e*/ 0x001700c0, + /*040f*/ 0x020100b0, + /*0410*/ 0x00030020, + /*0411*/ 0x00000000, + /*0412*/ 0x00000000, + /*0413*/ 0x00000000, + /*0414*/ 0x00000000, + /*0415*/ 0x00000000, + /*0416*/ 0x00000000, + /*0417*/ 0x00000000, + /*0418*/ 0x09000000, + /*0419*/ 0x04080000, + /*041a*/ 0x04080400, + /*041b*/ 0x08000000, + /*041c*/ 0x0c008007, + /*041d*/ 0x00000f00, + /*041e*/ 0x00000100, + /*041f*/ 0x55aa55aa, + /*0420*/ 0x33cc33cc, + /*0421*/ 0x0ff00ff0, + /*0422*/ 0x0f0ff0f0, + /*0423*/ 0x00018e38, + /*0424*/ 0x00000000, + /*0425*/ 0x00000000, + /*0426*/ 0x00000000, + /*0427*/ 0x00000000, + /*0428*/ 0x00000000, + /*0429*/ 0x00000000, + /*042a*/ 0x00000000, + /*042b*/ 0x00000000, + /*042c*/ 0x00000000, + /*042d*/ 0x00000000, + /*042e*/ 0x00000000, + /*042f*/ 0x00000000, + /*0430*/ 0x00000000, + /*0431*/ 0x00000000, + /*0432*/ 0x00000000, + /*0433*/ 0x00000000, + /*0434*/ 0x00000000, + /*0435*/ 0x00000000, + /*0436*/ 0x00000000, + /*0437*/ 0x00000000, + /*0438*/ 0x00000104, + /*0439*/ 0x00082020, + /*043a*/ 0x08200820, + /*043b*/ 0x08200820, + /*043c*/ 0x08200820, + /*043d*/ 0x08200820, + /*043e*/ 0x08200820, + /*043f*/ 0x00000000, + /*0440*/ 0x00000000, + /*0441*/ 0x03000300, + /*0442*/ 0x03000300, + /*0443*/ 0x03000300, + /*0444*/ 0x03000300, + /*0445*/ 0x00000300, + /*0446*/ 0x00000000, + /*0447*/ 0x00000000, + /*0448*/ 0x00000000, + /*0449*/ 0x00000000, + /*044a*/ 0x00000000, + /*044b*/ 0x00a000a0, + /*044c*/ 0x00a000a0, + /*044d*/ 0x00a000a0, + /*044e*/ 0x00a000a0, + /*044f*/ 0x00a000a0, + /*0450*/ 0x00a000a0, + /*0451*/ 0x00a000a0, + /*0452*/ 0x00a000a0, + /*0453*/ 0x00a000a0, + /*0454*/ 0x01040109, + /*0455*/ 0x00000200, + /*0456*/ 0x01000000, + /*0457*/ 0x00000200, + /*0458*/ 0x00000004, + /*0459*/ 0x4041a141, + /*045a*/ 0xc00141a0, + /*045b*/ 0x0e0000c0, + /*045c*/ 0x0010000c, + /*045d*/ 0x063e4208, + /*045e*/ 0x0f0c180c, + /*045f*/ 0x00e00140, + /*0460*/ 0x00000c20 }; static const uint32_t - DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = { -/*0600*/ 0x00000000, -/*0601*/ 0x00000000, -/*0602*/ 0x00000000, -/*0603*/ 0x00000000, -/*0604*/ 0x00000000, -/*0605*/ 0x00000000, -/*0606*/ 0x00000000, -/*0607*/ 0x00010000, -/*0608*/ 0x00000200, -/*0609*/ 0x00000000, -/*060a*/ 0x00000000, -/*060b*/ 0x00000000, -/*060c*/ 0x00400320, -/*060d*/ 0x00000040, -/*060e*/ 0x00dcba98, -/*060f*/ 0x03000000, -/*0610*/ 0x00000200, -/*0611*/ 0x00000000, -/*0612*/ 0x00000000, -/*0613*/ 0x00000000, -/*0614*/ 0x0000002a, -/*0615*/ 0x00000015, -/*0616*/ 0x00000015, -/*0617*/ 0x0000002a, -/*0618*/ 0x00000033, -/*0619*/ 0x0000000c, -/*061a*/ 0x0000000c, -/*061b*/ 0x00000033, -/*061c*/ 0x00418820, -/*061d*/ 0x003f0000, -/*061e*/ 0x0000003f, -/*061f*/ 0x0002c06e, -/*0620*/ 0x02c002c0, -/*0621*/ 0x02c002c0, -/*0622*/ 0x000002c0, -/*0623*/ 0x42080010, -/*0624*/ 0x0000033e + DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = { + /*0600*/ 0x00000000, + /*0601*/ 0x00000000, + /*0602*/ 0x00000000, + /*0603*/ 0x00000000, + /*0604*/ 0x00000000, + /*0605*/ 0x00000000, + /*0606*/ 0x00000000, + /*0607*/ 0x00010000, + /*0608*/ 0x00000200, + /*0609*/ 0x00000000, + /*060a*/ 0x00000000, + /*060b*/ 0x00000000, + /*060c*/ 0x00400320, + /*060d*/ 0x00000040, + /*060e*/ 0x00dcba98, + /*060f*/ 0x03000000, + /*0610*/ 0x00000200, + /*0611*/ 0x00000000, + /*0612*/ 0x00000000, + /*0613*/ 0x00000000, + /*0614*/ 0x0000002a, + /*0615*/ 0x00000015, + /*0616*/ 0x00000015, + /*0617*/ 0x0000002a, + /*0618*/ 0x00000033, + /*0619*/ 0x0000000c, + /*061a*/ 0x0000000c, + /*061b*/ 0x00000033, + /*061c*/ 0x00418820, + /*061d*/ 0x003f0000, + /*061e*/ 0x0000003f, + /*061f*/ 0x0002c06e, + /*0620*/ 0x02c002c0, + /*0621*/ 0x02c002c0, + /*0622*/ 0x000002c0, + /*0623*/ 0x42080010, + /*0624*/ 0x0000033e }; static const uint32_t - DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = { -/*0640*/ 0x00000000, -/*0641*/ 0x00000000, -/*0642*/ 0x00000000, -/*0643*/ 0x00000000, -/*0644*/ 0x00000000, -/*0645*/ 0x00000000, -/*0646*/ 0x00000000, -/*0647*/ 0x00000000, -/*0648*/ 0x00000000, -/*0649*/ 0x00000000, -/*064a*/ 0x00000000, -/*064b*/ 0x00000000, -/*064c*/ 0x00000000, -/*064d*/ 0x00000000, -/*064e*/ 0x00000000, -/*064f*/ 0x00000000, -/*0650*/ 0x00000000, -/*0651*/ 0x00000000, -/*0652*/ 0x00000000, -/*0653*/ 0x00000000, -/*0654*/ 0x00000000, -/*0655*/ 0x00000000, -/*0656*/ 0x00000000, -/*0657*/ 0x00000000, -/*0658*/ 0x00000000, -/*0659*/ 0x00000000, -/*065a*/ 0x00000000, -/*065b*/ 0x00000000, -/*065c*/ 0x00000000, -/*065d*/ 0x00000000, -/*065e*/ 0x00000000, -/*065f*/ 0x00000000, -/*0660*/ 0x00000000, -/*0661*/ 0x00000000, -/*0662*/ 0x00000000, -/*0663*/ 0x00000000, -/*0664*/ 0x00000000 + DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = { + /*0640*/ 0x00000000, + /*0641*/ 0x00000000, + /*0642*/ 0x00000000, + /*0643*/ 0x00000000, + /*0644*/ 0x00000000, + /*0645*/ 0x00000000, + /*0646*/ 0x00000000, + /*0647*/ 0x00000000, + /*0648*/ 0x00000000, + /*0649*/ 0x00000000, + /*064a*/ 0x00000000, + /*064b*/ 0x00000000, + /*064c*/ 0x00000000, + /*064d*/ 0x00000000, + /*064e*/ 0x00000000, + /*064f*/ 0x00000000, + /*0650*/ 0x00000000, + /*0651*/ 0x00000000, + /*0652*/ 0x00000000, + /*0653*/ 0x00000000, + /*0654*/ 0x00000000, + /*0655*/ 0x00000000, + /*0656*/ 0x00000000, + /*0657*/ 0x00000000, + /*0658*/ 0x00000000, + /*0659*/ 0x00000000, + /*065a*/ 0x00000000, + /*065b*/ 0x00000000, + /*065c*/ 0x00000000, + /*065d*/ 0x00000000, + /*065e*/ 0x00000000, + /*065f*/ 0x00000000, + /*0660*/ 0x00000000, + /*0661*/ 0x00000000, + /*0662*/ 0x00000000, + /*0663*/ 0x00000000, + /*0664*/ 0x00000000 }; static const uint32_t - DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = { -/*0680*/ 0x00000000, -/*0681*/ 0x00000100, -/*0682*/ 0x00000000, -/*0683*/ 0x00050000, -/*0684*/ 0x0f000000, -/*0685*/ 0x00800400, -/*0686*/ 0x00020032, -/*0687*/ 0x00020055, -/*0688*/ 0x00000000, -/*0689*/ 0x00000000, -/*068a*/ 0x00000000, -/*068b*/ 0x00000050, -/*068c*/ 0x00000000, -/*068d*/ 0x01010100, -/*068e*/ 0x01000200, -/*068f*/ 0x00000000, -/*0690*/ 0x00010100, -/*0691*/ 0x00000000, -/*0692*/ 0x00000000, -/*0693*/ 0x00000000, -/*0694*/ 0x00000000, -/*0695*/ 0x00005064, -/*0696*/ 0x01421142, -/*0697*/ 0x00000142, -/*0698*/ 0x00000000, -/*0699*/ 0x000f1100, -/*069a*/ 0x0f110f11, -/*069b*/ 0x09000f11, -/*069c*/ 0x00000003, -/*069d*/ 0x0002c000, -/*069e*/ 0x02c002c0, -/*069f*/ 0x000002c0, -/*06a0*/ 0x03421342, -/*06a1*/ 0x00000342, -/*06a2*/ 0x00000000, -/*06a3*/ 0x00000000, -/*06a4*/ 0x05020000, -/*06a5*/ 0x14000000, -/*06a6*/ 0x027f6e00, -/*06a7*/ 0x047f027f, -/*06a8*/ 0x00027f6e, -/*06a9*/ 0x00047f6e, -/*06aa*/ 0x0003554f, -/*06ab*/ 0x0001554f, -/*06ac*/ 0x0001554f, -/*06ad*/ 0x0001554f, -/*06ae*/ 0x0001554f, -/*06af*/ 0x00003fee, -/*06b0*/ 0x0001554f, -/*06b1*/ 0x00003fee, -/*06b2*/ 0x0001554f, -/*06b3*/ 0x00027f6e, -/*06b4*/ 0x0001554f, -/*06b5*/ 0x00004011, -/*06b6*/ 0x00004410, -/*06b7*/ 0x00000000, -/*06b8*/ 0x00000000, -/*06b9*/ 0x00000000, -/*06ba*/ 0x00000065, -/*06bb*/ 0x00000000, -/*06bc*/ 0x00020201, -/*06bd*/ 0x00000000, -/*06be*/ 0x03000000, -/*06bf*/ 0x00000008, -/*06c0*/ 0x00000000, -/*06c1*/ 0x00000000, -/*06c2*/ 0x00000000, -/*06c3*/ 0x00000000, -/*06c4*/ 0x00000001, -/*06c5*/ 0x00000000, -/*06c6*/ 0x00000000, -/*06c7*/ 0x00000000, -/*06c8*/ 0x000000e4, -/*06c9*/ 0x00010198, -/*06ca*/ 0x00000000, -/*06cb*/ 0x00000000, -/*06cc*/ 0x07010000, -/*06cd*/ 0x00000104, -/*06ce*/ 0x00000000 + DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = { + /*0680*/ 0x00000000, + /*0681*/ 0x00000100, + /*0682*/ 0x00000000, + /*0683*/ 0x00050000, + /*0684*/ 0x0f000000, + /*0685*/ 0x00800400, + /*0686*/ 0x00020032, + /*0687*/ 0x00020055, + /*0688*/ 0x00000000, + /*0689*/ 0x00000000, + /*068a*/ 0x00000000, + /*068b*/ 0x00000050, + /*068c*/ 0x00000000, + /*068d*/ 0x01010100, + /*068e*/ 0x01000200, + /*068f*/ 0x00000000, + /*0690*/ 0x00010100, + /*0691*/ 0x00000000, + /*0692*/ 0x00000000, + /*0693*/ 0x00000000, + /*0694*/ 0x00000000, + /*0695*/ 0x00005064, + /*0696*/ 0x01421142, + /*0697*/ 0x00000142, + /*0698*/ 0x00000000, + /*0699*/ 0x000f1100, + /*069a*/ 0x0f110f11, + /*069b*/ 0x09000f11, + /*069c*/ 0x00000003, + /*069d*/ 0x0002c000, + /*069e*/ 0x02c002c0, + /*069f*/ 0x000002c0, + /*06a0*/ 0x03421342, + /*06a1*/ 0x00000342, + /*06a2*/ 0x00000000, + /*06a3*/ 0x00000000, + /*06a4*/ 0x05020000, + /*06a5*/ 0x14000000, + /*06a6*/ 0x027f6e00, + /*06a7*/ 0x047f027f, + /*06a8*/ 0x00027f6e, + /*06a9*/ 0x00047f6e, + /*06aa*/ 0x0003554f, + /*06ab*/ 0x0001554f, + /*06ac*/ 0x0001554f, + /*06ad*/ 0x0001554f, + /*06ae*/ 0x0001554f, + /*06af*/ 0x00003fee, + /*06b0*/ 0x0001554f, + /*06b1*/ 0x00003fee, + /*06b2*/ 0x0001554f, + /*06b3*/ 0x00027f6e, + /*06b4*/ 0x0001554f, + /*06b5*/ 0x00004011, + /*06b6*/ 0x00004410, + /*06b7*/ 0x00000000, + /*06b8*/ 0x00000000, + /*06b9*/ 0x00000000, + /*06ba*/ 0x00000065, + /*06bb*/ 0x00000000, + /*06bc*/ 0x00020201, + /*06bd*/ 0x00000000, + /*06be*/ 0x03000000, + /*06bf*/ 0x00000008, + /*06c0*/ 0x00000000, + /*06c1*/ 0x00000000, + /*06c2*/ 0x00000000, + /*06c3*/ 0x00000000, + /*06c4*/ 0x00000001, + /*06c5*/ 0x00000000, + /*06c6*/ 0x00000000, + /*06c7*/ 0x00000000, + /*06c8*/ 0x000000e4, + /*06c9*/ 0x00010198, + /*06ca*/ 0x00000000, + /*06cb*/ 0x00000000, + /*06cc*/ 0x07010000, + /*06cd*/ 0x00000104, + /*06ce*/ 0x00000000 }; static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = { -/*0200*/ 0x00000b00, -/*0201*/ 0x00000100, -/*0202*/ 0x00640000, -/*0203*/ 0x00000000, -/*0204*/ 0x0000ffff, -/*0205*/ 0x00000000, -/*0206*/ 0x0000ffff, -/*0207*/ 0x00000000, -/*0208*/ 0x0000ffff, -/*0209*/ 0x0000304c, -/*020a*/ 0x00000200, -/*020b*/ 0x00000200, -/*020c*/ 0x00000200, -/*020d*/ 0x00000200, -/*020e*/ 0x0000304c, -/*020f*/ 0x00000200, -/*0210*/ 0x00000200, -/*0211*/ 0x00000200, -/*0212*/ 0x00000200, -/*0213*/ 0x0000304c, -/*0214*/ 0x00000200, -/*0215*/ 0x00000200, -/*0216*/ 0x00000200, -/*0217*/ 0x00000200, -/*0218*/ 0x00010000, -/*0219*/ 0x00000003, -/*021a*/ 0x01000001, -/*021b*/ 0x00000000, -/*021c*/ 0x00000000, -/*021d*/ 0x00000000, -/*021e*/ 0x00000000, -/*021f*/ 0x00000000, -/*0220*/ 0x00000000, -/*0221*/ 0x00000000, -/*0222*/ 0x00000000, -/*0223*/ 0x00000000, -/*0224*/ 0x00000000, -/*0225*/ 0x00000000, -/*0226*/ 0x00000000, -/*0227*/ 0x00000000, -/*0228*/ 0x00000000, -/*0229*/ 0x00000000, -/*022a*/ 0x00000000, -/*022b*/ 0x0f000101, -/*022c*/ 0x08492d25, -/*022d*/ 0x500e0c04, -/*022e*/ 0x0002500e, -/*022f*/ 0x00000301, -/*0230*/ 0x00000046, -/*0231*/ 0x000000cf, -/*0232*/ 0x00001826, -/*0233*/ 0x000000cf, -/*0234*/ 0x00001826, -/*0235*/ 0x00000005, -/*0236*/ 0x00000000, -/*0237*/ 0x00000000, -/*0238*/ 0x00000000, -/*0239*/ 0x00000000, -/*023a*/ 0x00000000, -/*023b*/ 0x00000000, -/*023c*/ 0x00000000, -/*023d*/ 0x00000000, -/*023e*/ 0x04010000, -/*023f*/ 0x00000404, -/*0240*/ 0x0101280a, -/*0241*/ 0x00000000, -/*0242*/ 0x00000000, -/*0243*/ 0x0003000f, -/*0244*/ 0x00000018, -/*0245*/ 0x00000000, -/*0246*/ 0x00000000, -/*0247*/ 0x00060002, -/*0248*/ 0x00010001, -/*0249*/ 0x01000101, -/*024a*/ 0x04020201, -/*024b*/ 0x00080804, -/*024c*/ 0x00000000, -/*024d*/ 0x08030000, -/*024e*/ 0x15150408, -/*024f*/ 0x00000000, -/*0250*/ 0x00000000, -/*0251*/ 0x00000000, -/*0252*/ 0x0f0f0000, -/*0253*/ 0x0000001e, -/*0254*/ 0x00000000, -/*0255*/ 0x01000300, -/*0256*/ 0x00000100, -/*0257*/ 0x00000000, -/*0258*/ 0x00000000, -/*0259*/ 0x01000000, -/*025a*/ 0x00000101, -/*025b*/ 0x55555a5a, -/*025c*/ 0x55555a5a, -/*025d*/ 0x55555a5a, -/*025e*/ 0x55555a5a, -/*025f*/ 0x0e0e0001, -/*0260*/ 0x0c0c000e, -/*0261*/ 0x0601000c, -/*0262*/ 0x17170106, -/*0263*/ 0x00020202, -/*0264*/ 0x03000000, -/*0265*/ 0x00000000, -/*0266*/ 0x00181703, -/*0267*/ 0x00280006, -/*0268*/ 0x00280016, -/*0269*/ 0x00000016, -/*026a*/ 0x00000000, -/*026b*/ 0x00000000, -/*026c*/ 0x00000000, -/*026d*/ 0x0a000000, -/*026e*/ 0x00010a14, -/*026f*/ 0x00030005, -/*0270*/ 0x0003018d, -/*0271*/ 0x000a018d, -/*0272*/ 0x00060100, -/*0273*/ 0x01000006, -/*0274*/ 0x018e018e, -/*0275*/ 0x018e0100, -/*0276*/ 0x1111018e, -/*0277*/ 0x10010204, -/*0278*/ 0x09090650, -/*0279*/ 0xff110202, -/*027a*/ 0x00ff1000, -/*027b*/ 0x00ff1000, -/*027c*/ 0x04041000, -/*027d*/ 0x18020100, -/*027e*/ 0x01010018, -/*027f*/ 0x004a004a, -/*0280*/ 0x004b004a, -/*0281*/ 0x050f0000, -/*0282*/ 0x0c01021e, -/*0283*/ 0x34000000, -/*0284*/ 0x00000000, -/*0285*/ 0x00000000, -/*0286*/ 0x00000000, -/*0287*/ 0x00000000, -/*0288*/ 0x36312ed4, -/*0289*/ 0x2ed41111, -/*028a*/ 0x11113631, -/*028b*/ 0x36312ed4, -/*028c*/ 0xd4001111, -/*028d*/ 0x1136312e, -/*028e*/ 0x312ed411, -/*028f*/ 0xd4111136, -/*0290*/ 0x1136312e, -/*0291*/ 0x2ed40011, -/*0292*/ 0x11113631, -/*0293*/ 0x36312ed4, -/*0294*/ 0x2ed41111, -/*0295*/ 0x11113631, -/*0296*/ 0x312ed400, -/*0297*/ 0xd4111136, -/*0298*/ 0x1136312e, -/*0299*/ 0x312ed411, -/*029a*/ 0x00111136, -/*029b*/ 0x018d0200, -/*029c*/ 0x018d018d, -/*029d*/ 0x1d220c08, -/*029e*/ 0x00001f12, -/*029f*/ 0x4301b344, -/*02a0*/ 0x10172006, -/*02a1*/ 0x121d220c, -/*02a2*/ 0x01b3441f, -/*02a3*/ 0x17200643, -/*02a4*/ 0x1d220c10, -/*02a5*/ 0x00001f12, -/*02a6*/ 0x4301b344, -/*02a7*/ 0x10172006, -/*02a8*/ 0x00020002, -/*02a9*/ 0x00020002, -/*02aa*/ 0x00020002, -/*02ab*/ 0x00020002, -/*02ac*/ 0x00020002, -/*02ad*/ 0x00000000, -/*02ae*/ 0x00000000, -/*02af*/ 0x00000000, -/*02b0*/ 0x00000000, -/*02b1*/ 0x00000000, -/*02b2*/ 0x00000000, -/*02b3*/ 0x00000000, -/*02b4*/ 0x00000000, -/*02b5*/ 0x00000000, -/*02b6*/ 0x00000000, -/*02b7*/ 0x00000000, -/*02b8*/ 0x00000000, -/*02b9*/ 0x00000400, -/*02ba*/ 0x05040302, -/*02bb*/ 0x01000f0e, -/*02bc*/ 0x07060504, -/*02bd*/ 0x03020100, -/*02be*/ 0x02010000, -/*02bf*/ 0x00000103, -/*02c0*/ 0x0000304c, -/*02c1*/ 0x0001e2f8, -/*02c2*/ 0x0000304c, -/*02c3*/ 0x0001e2f8, -/*02c4*/ 0x0000304c, -/*02c5*/ 0x0001e2f8, -/*02c6*/ 0x08000000, -/*02c7*/ 0x00000100, -/*02c8*/ 0x00000000, -/*02c9*/ 0x00000000, -/*02ca*/ 0x00000000, -/*02cb*/ 0x00000000, -/*02cc*/ 0x00010000, -/*02cd*/ 0x00000000, -/*02ce*/ 0x00000000, -/*02cf*/ 0x00000000, -/*02d0*/ 0x00000000, -/*02d1*/ 0x00000000, -/*02d2*/ 0x00000000, -/*02d3*/ 0x00000000, -/*02d4*/ 0x00000000, -/*02d5*/ 0x00000000, -/*02d6*/ 0x00000000, -/*02d7*/ 0x00000000, -/*02d8*/ 0x00000000, -/*02d9*/ 0x00000000, -/*02da*/ 0x00000000, -/*02db*/ 0x00000000, -/*02dc*/ 0x00000000, -/*02dd*/ 0x00000000, -/*02de*/ 0x00000000, -/*02df*/ 0x00000000, -/*02e0*/ 0x00000000, -/*02e1*/ 0x00000000, -/*02e2*/ 0x00000000, -/*02e3*/ 0x00000000, -/*02e4*/ 0x00000000, -/*02e5*/ 0x00000000, -/*02e6*/ 0x00000000, -/*02e7*/ 0x00000000, -/*02e8*/ 0x00000000, -/*02e9*/ 0x00000000, -/*02ea*/ 0x00000000, -/*02eb*/ 0x00000000, -/*02ec*/ 0x00000000, -/*02ed*/ 0x00000000, -/*02ee*/ 0x00000002, -/*02ef*/ 0x00000000, -/*02f0*/ 0x00000000, -/*02f1*/ 0x00000000, -/*02f2*/ 0x00000000, -/*02f3*/ 0x00000000, -/*02f4*/ 0x00000000 + /*0200*/ 0x00000b00, + /*0201*/ 0x00000100, + /*0202*/ 0x00640000, + /*0203*/ 0x00000000, + /*0204*/ 0x0000ffff, + /*0205*/ 0x00000000, + /*0206*/ 0x0000ffff, + /*0207*/ 0x00000000, + /*0208*/ 0x0000ffff, + /*0209*/ 0x0000304c, + /*020a*/ 0x00000200, + /*020b*/ 0x00000200, + /*020c*/ 0x00000200, + /*020d*/ 0x00000200, + /*020e*/ 0x0000304c, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x00000200, + /*0212*/ 0x00000200, + /*0213*/ 0x0000304c, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00000200, + /*0217*/ 0x00000200, + /*0218*/ 0x00010000, + /*0219*/ 0x00000003, + /*021a*/ 0x01000001, + /*021b*/ 0x00000000, + /*021c*/ 0x00000000, + /*021d*/ 0x00000000, + /*021e*/ 0x00000000, + /*021f*/ 0x00000000, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x00000000, + /*022a*/ 0x00000000, + /*022b*/ 0x0f000101, + /*022c*/ 0x08492d25, + /*022d*/ 0x500e0c04, + /*022e*/ 0x0002500e, + /*022f*/ 0x00000301, + /*0230*/ 0x00000046, + /*0231*/ 0x000000cf, + /*0232*/ 0x00001826, + /*0233*/ 0x000000cf, + /*0234*/ 0x00001826, + /*0235*/ 0x00000005, + /*0236*/ 0x00000000, + /*0237*/ 0x00000000, + /*0238*/ 0x00000000, + /*0239*/ 0x00000000, + /*023a*/ 0x00000000, + /*023b*/ 0x00000000, + /*023c*/ 0x00000000, + /*023d*/ 0x00000000, + /*023e*/ 0x04010000, + /*023f*/ 0x00000404, + /*0240*/ 0x0101280a, + /*0241*/ 0x00000000, + /*0242*/ 0x00000000, + /*0243*/ 0x0003000f, + /*0244*/ 0x00000018, + /*0245*/ 0x00000000, + /*0246*/ 0x00000000, + /*0247*/ 0x00060002, + /*0248*/ 0x00010001, + /*0249*/ 0x01000101, + /*024a*/ 0x04020201, + /*024b*/ 0x00080804, + /*024c*/ 0x00000000, + /*024d*/ 0x08030000, + /*024e*/ 0x15150408, + /*024f*/ 0x00000000, + /*0250*/ 0x00000000, + /*0251*/ 0x00000000, + /*0252*/ 0x0f0f0000, + /*0253*/ 0x0000001e, + /*0254*/ 0x00000000, + /*0255*/ 0x01000300, + /*0256*/ 0x00000100, + /*0257*/ 0x00000000, + /*0258*/ 0x00000000, + /*0259*/ 0x01000000, + /*025a*/ 0x00000101, + /*025b*/ 0x55555a5a, + /*025c*/ 0x55555a5a, + /*025d*/ 0x55555a5a, + /*025e*/ 0x55555a5a, + /*025f*/ 0x0e0e0001, + /*0260*/ 0x0c0c000e, + /*0261*/ 0x0601000c, + /*0262*/ 0x17170106, + /*0263*/ 0x00020202, + /*0264*/ 0x03000000, + /*0265*/ 0x00000000, + /*0266*/ 0x00181703, + /*0267*/ 0x00280006, + /*0268*/ 0x00280016, + /*0269*/ 0x00000016, + /*026a*/ 0x00000000, + /*026b*/ 0x00000000, + /*026c*/ 0x00000000, + /*026d*/ 0x0a000000, + /*026e*/ 0x00010a14, + /*026f*/ 0x00030005, + /*0270*/ 0x0003018d, + /*0271*/ 0x000a018d, + /*0272*/ 0x00060100, + /*0273*/ 0x01000006, + /*0274*/ 0x018e018e, + /*0275*/ 0x018e0100, + /*0276*/ 0x1111018e, + /*0277*/ 0x10010204, + /*0278*/ 0x09090650, + /*0279*/ 0xff110202, + /*027a*/ 0x00ff1000, + /*027b*/ 0x00ff1000, + /*027c*/ 0x04041000, + /*027d*/ 0x18020100, + /*027e*/ 0x01010018, + /*027f*/ 0x004a004a, + /*0280*/ 0x004b004a, + /*0281*/ 0x050f0000, + /*0282*/ 0x0c01021e, + /*0283*/ 0x34000000, + /*0284*/ 0x00000000, + /*0285*/ 0x00000000, + /*0286*/ 0x00000000, + /*0287*/ 0x00000000, + /*0288*/ 0x36312ed4, + /*0289*/ 0x2ed41111, + /*028a*/ 0x11113631, + /*028b*/ 0x36312ed4, + /*028c*/ 0xd4001111, + /*028d*/ 0x1136312e, + /*028e*/ 0x312ed411, + /*028f*/ 0xd4111136, + /*0290*/ 0x1136312e, + /*0291*/ 0x2ed40011, + /*0292*/ 0x11113631, + /*0293*/ 0x36312ed4, + /*0294*/ 0x2ed41111, + /*0295*/ 0x11113631, + /*0296*/ 0x312ed400, + /*0297*/ 0xd4111136, + /*0298*/ 0x1136312e, + /*0299*/ 0x312ed411, + /*029a*/ 0x00111136, + /*029b*/ 0x018d0200, + /*029c*/ 0x018d018d, + /*029d*/ 0x1d220c08, + /*029e*/ 0x00001f12, + /*029f*/ 0x4301b344, + /*02a0*/ 0x10172006, + /*02a1*/ 0x121d220c, + /*02a2*/ 0x01b3441f, + /*02a3*/ 0x17200643, + /*02a4*/ 0x1d220c10, + /*02a5*/ 0x00001f12, + /*02a6*/ 0x4301b344, + /*02a7*/ 0x10172006, + /*02a8*/ 0x00020002, + /*02a9*/ 0x00020002, + /*02aa*/ 0x00020002, + /*02ab*/ 0x00020002, + /*02ac*/ 0x00020002, + /*02ad*/ 0x00000000, + /*02ae*/ 0x00000000, + /*02af*/ 0x00000000, + /*02b0*/ 0x00000000, + /*02b1*/ 0x00000000, + /*02b2*/ 0x00000000, + /*02b3*/ 0x00000000, + /*02b4*/ 0x00000000, + /*02b5*/ 0x00000000, + /*02b6*/ 0x00000000, + /*02b7*/ 0x00000000, + /*02b8*/ 0x00000000, + /*02b9*/ 0x00000400, + /*02ba*/ 0x05040302, + /*02bb*/ 0x01000f0e, + /*02bc*/ 0x07060504, + /*02bd*/ 0x03020100, + /*02be*/ 0x02010000, + /*02bf*/ 0x00000103, + /*02c0*/ 0x0000304c, + /*02c1*/ 0x0001e2f8, + /*02c2*/ 0x0000304c, + /*02c3*/ 0x0001e2f8, + /*02c4*/ 0x0000304c, + /*02c5*/ 0x0001e2f8, + /*02c6*/ 0x08000000, + /*02c7*/ 0x00000100, + /*02c8*/ 0x00000000, + /*02c9*/ 0x00000000, + /*02ca*/ 0x00000000, + /*02cb*/ 0x00000000, + /*02cc*/ 0x00010000, + /*02cd*/ 0x00000000, + /*02ce*/ 0x00000000, + /*02cf*/ 0x00000000, + /*02d0*/ 0x00000000, + /*02d1*/ 0x00000000, + /*02d2*/ 0x00000000, + /*02d3*/ 0x00000000, + /*02d4*/ 0x00000000, + /*02d5*/ 0x00000000, + /*02d6*/ 0x00000000, + /*02d7*/ 0x00000000, + /*02d8*/ 0x00000000, + /*02d9*/ 0x00000000, + /*02da*/ 0x00000000, + /*02db*/ 0x00000000, + /*02dc*/ 0x00000000, + /*02dd*/ 0x00000000, + /*02de*/ 0x00000000, + /*02df*/ 0x00000000, + /*02e0*/ 0x00000000, + /*02e1*/ 0x00000000, + /*02e2*/ 0x00000000, + /*02e3*/ 0x00000000, + /*02e4*/ 0x00000000, + /*02e5*/ 0x00000000, + /*02e6*/ 0x00000000, + /*02e7*/ 0x00000000, + /*02e8*/ 0x00000000, + /*02e9*/ 0x00000000, + /*02ea*/ 0x00000000, + /*02eb*/ 0x00000000, + /*02ec*/ 0x00000000, + /*02ed*/ 0x00000000, + /*02ee*/ 0x00000002, + /*02ef*/ 0x00000000, + /*02f0*/ 0x00000000, + /*02f1*/ 0x00000000, + /*02f2*/ 0x00000000, + /*02f3*/ 0x00000000, + /*02f4*/ 0x00000000 }; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h index 3c62107ed..a09b00412 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,445 +24,445 @@ #define DDR_PI_REGSET_NUM_M3 202 static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = { -/*0800*/ 0x76543210, -/*0801*/ 0x0004f008, -/*0802*/ 0x00000000, -/*0803*/ 0x00000000, -/*0804*/ 0x00010000, -/*0805*/ 0x036e6e0e, -/*0806*/ 0x026e6e0e, -/*0807*/ 0x00010300, -/*0808*/ 0x04000100, -/*0809*/ 0x00000300, -/*080a*/ 0x001700c0, -/*080b*/ 0x00b00201, -/*080c*/ 0x00030020, -/*080d*/ 0x00000000, -/*080e*/ 0x00000000, -/*080f*/ 0x00000000, -/*0810*/ 0x00000000, -/*0811*/ 0x00000000, -/*0812*/ 0x00000000, -/*0813*/ 0x00000000, -/*0814*/ 0x09000000, -/*0815*/ 0x04080000, -/*0816*/ 0x04080400, -/*0817*/ 0x00000000, -/*0818*/ 0x32103210, -/*0819*/ 0x00800708, -/*081a*/ 0x000f000c, -/*081b*/ 0x00000100, -/*081c*/ 0x55aa55aa, -/*081d*/ 0x33cc33cc, -/*081e*/ 0x0ff00ff0, -/*081f*/ 0x0f0ff0f0, -/*0820*/ 0x00018e38, -/*0821*/ 0x00000000, -/*0822*/ 0x00000000, -/*0823*/ 0x00000000, -/*0824*/ 0x00000000, -/*0825*/ 0x00000000, -/*0826*/ 0x00000000, -/*0827*/ 0x00000000, -/*0828*/ 0x00000000, -/*0829*/ 0x00000000, -/*082a*/ 0x00000000, -/*082b*/ 0x00000000, -/*082c*/ 0x00000000, -/*082d*/ 0x00000000, -/*082e*/ 0x00000000, -/*082f*/ 0x00000000, -/*0830*/ 0x00000000, -/*0831*/ 0x00000000, -/*0832*/ 0x00000000, -/*0833*/ 0x00200000, -/*0834*/ 0x08200820, -/*0835*/ 0x08200820, -/*0836*/ 0x08200820, -/*0837*/ 0x08200820, -/*0838*/ 0x08200820, -/*0839*/ 0x00000820, -/*083a*/ 0x03000300, -/*083b*/ 0x03000300, -/*083c*/ 0x03000300, -/*083d*/ 0x03000300, -/*083e*/ 0x00000300, -/*083f*/ 0x00000000, -/*0840*/ 0x00000000, -/*0841*/ 0x00000000, -/*0842*/ 0x00000000, -/*0843*/ 0x00a00000, -/*0844*/ 0x00a000a0, -/*0845*/ 0x00a000a0, -/*0846*/ 0x00a000a0, -/*0847*/ 0x00a000a0, -/*0848*/ 0x00a000a0, -/*0849*/ 0x00a000a0, -/*084a*/ 0x00a000a0, -/*084b*/ 0x00a000a0, -/*084c*/ 0x010900a0, -/*084d*/ 0x02000104, -/*084e*/ 0x00000000, -/*084f*/ 0x00010000, -/*0850*/ 0x00000200, -/*0851*/ 0x4041a141, -/*0852*/ 0xc00141a0, -/*0853*/ 0x0e0100c0, -/*0854*/ 0x0010000c, -/*0855*/ 0x0c064208, -/*0856*/ 0x000f0c18, -/*0857*/ 0x00e00140, -/*0858*/ 0x00000c20 + /*0800*/ 0x76543210, + /*0801*/ 0x0004f008, + /*0802*/ 0x00000000, + /*0803*/ 0x00000000, + /*0804*/ 0x00010000, + /*0805*/ 0x036e6e0e, + /*0806*/ 0x026e6e0e, + /*0807*/ 0x00010300, + /*0808*/ 0x04000100, + /*0809*/ 0x00000300, + /*080a*/ 0x001700c0, + /*080b*/ 0x00b00201, + /*080c*/ 0x00030020, + /*080d*/ 0x00000000, + /*080e*/ 0x00000000, + /*080f*/ 0x00000000, + /*0810*/ 0x00000000, + /*0811*/ 0x00000000, + /*0812*/ 0x00000000, + /*0813*/ 0x00000000, + /*0814*/ 0x09000000, + /*0815*/ 0x04080000, + /*0816*/ 0x04080400, + /*0817*/ 0x00000000, + /*0818*/ 0x32103210, + /*0819*/ 0x00800708, + /*081a*/ 0x000f000c, + /*081b*/ 0x00000100, + /*081c*/ 0x55aa55aa, + /*081d*/ 0x33cc33cc, + /*081e*/ 0x0ff00ff0, + /*081f*/ 0x0f0ff0f0, + /*0820*/ 0x00018e38, + /*0821*/ 0x00000000, + /*0822*/ 0x00000000, + /*0823*/ 0x00000000, + /*0824*/ 0x00000000, + /*0825*/ 0x00000000, + /*0826*/ 0x00000000, + /*0827*/ 0x00000000, + /*0828*/ 0x00000000, + /*0829*/ 0x00000000, + /*082a*/ 0x00000000, + /*082b*/ 0x00000000, + /*082c*/ 0x00000000, + /*082d*/ 0x00000000, + /*082e*/ 0x00000000, + /*082f*/ 0x00000000, + /*0830*/ 0x00000000, + /*0831*/ 0x00000000, + /*0832*/ 0x00000000, + /*0833*/ 0x00200000, + /*0834*/ 0x08200820, + /*0835*/ 0x08200820, + /*0836*/ 0x08200820, + /*0837*/ 0x08200820, + /*0838*/ 0x08200820, + /*0839*/ 0x00000820, + /*083a*/ 0x03000300, + /*083b*/ 0x03000300, + /*083c*/ 0x03000300, + /*083d*/ 0x03000300, + /*083e*/ 0x00000300, + /*083f*/ 0x00000000, + /*0840*/ 0x00000000, + /*0841*/ 0x00000000, + /*0842*/ 0x00000000, + /*0843*/ 0x00a00000, + /*0844*/ 0x00a000a0, + /*0845*/ 0x00a000a0, + /*0846*/ 0x00a000a0, + /*0847*/ 0x00a000a0, + /*0848*/ 0x00a000a0, + /*0849*/ 0x00a000a0, + /*084a*/ 0x00a000a0, + /*084b*/ 0x00a000a0, + /*084c*/ 0x010900a0, + /*084d*/ 0x02000104, + /*084e*/ 0x00000000, + /*084f*/ 0x00010000, + /*0850*/ 0x00000200, + /*0851*/ 0x4041a141, + /*0852*/ 0xc00141a0, + /*0853*/ 0x0e0100c0, + /*0854*/ 0x0010000c, + /*0855*/ 0x0c064208, + /*0856*/ 0x000f0c18, + /*0857*/ 0x00e00140, + /*0858*/ 0x00000c20 }; static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = { -/*0a00*/ 0x00000000, -/*0a01*/ 0x00000000, -/*0a02*/ 0x00000000, -/*0a03*/ 0x00000000, -/*0a04*/ 0x00000000, -/*0a05*/ 0x00000000, -/*0a06*/ 0x00000002, -/*0a07*/ 0x00000000, -/*0a08*/ 0x00000000, -/*0a09*/ 0x00000000, -/*0a0a*/ 0x00400320, -/*0a0b*/ 0x00000040, -/*0a0c*/ 0x00dcba98, -/*0a0d*/ 0x00000000, -/*0a0e*/ 0x00dcba98, -/*0a0f*/ 0x01000000, -/*0a10*/ 0x00020003, -/*0a11*/ 0x00000000, -/*0a12*/ 0x00000000, -/*0a13*/ 0x00000000, -/*0a14*/ 0x0000002a, -/*0a15*/ 0x00000015, -/*0a16*/ 0x00000015, -/*0a17*/ 0x0000002a, -/*0a18*/ 0x00000033, -/*0a19*/ 0x0000000c, -/*0a1a*/ 0x0000000c, -/*0a1b*/ 0x00000033, -/*0a1c*/ 0x0a418820, -/*0a1d*/ 0x003f0000, -/*0a1e*/ 0x0000003f, -/*0a1f*/ 0x0002c06e, -/*0a20*/ 0x02c002c0, -/*0a21*/ 0x02c002c0, -/*0a22*/ 0x000002c0, -/*0a23*/ 0x42080010, -/*0a24*/ 0x00000003 + /*0a00*/ 0x00000000, + /*0a01*/ 0x00000000, + /*0a02*/ 0x00000000, + /*0a03*/ 0x00000000, + /*0a04*/ 0x00000000, + /*0a05*/ 0x00000000, + /*0a06*/ 0x00000002, + /*0a07*/ 0x00000000, + /*0a08*/ 0x00000000, + /*0a09*/ 0x00000000, + /*0a0a*/ 0x00400320, + /*0a0b*/ 0x00000040, + /*0a0c*/ 0x00dcba98, + /*0a0d*/ 0x00000000, + /*0a0e*/ 0x00dcba98, + /*0a0f*/ 0x01000000, + /*0a10*/ 0x00020003, + /*0a11*/ 0x00000000, + /*0a12*/ 0x00000000, + /*0a13*/ 0x00000000, + /*0a14*/ 0x0000002a, + /*0a15*/ 0x00000015, + /*0a16*/ 0x00000015, + /*0a17*/ 0x0000002a, + /*0a18*/ 0x00000033, + /*0a19*/ 0x0000000c, + /*0a1a*/ 0x0000000c, + /*0a1b*/ 0x00000033, + /*0a1c*/ 0x0a418820, + /*0a1d*/ 0x003f0000, + /*0a1e*/ 0x0000003f, + /*0a1f*/ 0x0002c06e, + /*0a20*/ 0x02c002c0, + /*0a21*/ 0x02c002c0, + /*0a22*/ 0x000002c0, + /*0a23*/ 0x42080010, + /*0a24*/ 0x00000003 }; static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = { -/*0a80*/ 0x04040404, -/*0a81*/ 0x00000404, -/*0a82*/ 0x00000000, -/*0a83*/ 0x00000000, -/*0a84*/ 0x00000000, -/*0a85*/ 0x00000000, -/*0a86*/ 0x00000002, -/*0a87*/ 0x00000000, -/*0a88*/ 0x00000000, -/*0a89*/ 0x00000000, -/*0a8a*/ 0x00400320, -/*0a8b*/ 0x00000040, -/*0a8c*/ 0x00000000, -/*0a8d*/ 0x00000000, -/*0a8e*/ 0x00000000, -/*0a8f*/ 0x01000000, -/*0a90*/ 0x00020003, -/*0a91*/ 0x00000000, -/*0a92*/ 0x00000000, -/*0a93*/ 0x00000000, -/*0a94*/ 0x0000002a, -/*0a95*/ 0x00000015, -/*0a96*/ 0x00000015, -/*0a97*/ 0x0000002a, -/*0a98*/ 0x00000033, -/*0a99*/ 0x0000000c, -/*0a9a*/ 0x0000000c, -/*0a9b*/ 0x00000033, -/*0a9c*/ 0x00000000, -/*0a9d*/ 0x00000000, -/*0a9e*/ 0x00000000, -/*0a9f*/ 0x0002c06e, -/*0aa0*/ 0x02c002c0, -/*0aa1*/ 0x02c002c0, -/*0aa2*/ 0x000002c0, -/*0aa3*/ 0x42080010, -/*0aa4*/ 0x00000003 + /*0a80*/ 0x04040404, + /*0a81*/ 0x00000404, + /*0a82*/ 0x00000000, + /*0a83*/ 0x00000000, + /*0a84*/ 0x00000000, + /*0a85*/ 0x00000000, + /*0a86*/ 0x00000002, + /*0a87*/ 0x00000000, + /*0a88*/ 0x00000000, + /*0a89*/ 0x00000000, + /*0a8a*/ 0x00400320, + /*0a8b*/ 0x00000040, + /*0a8c*/ 0x00000000, + /*0a8d*/ 0x00000000, + /*0a8e*/ 0x00000000, + /*0a8f*/ 0x01000000, + /*0a90*/ 0x00020003, + /*0a91*/ 0x00000000, + /*0a92*/ 0x00000000, + /*0a93*/ 0x00000000, + /*0a94*/ 0x0000002a, + /*0a95*/ 0x00000015, + /*0a96*/ 0x00000015, + /*0a97*/ 0x0000002a, + /*0a98*/ 0x00000033, + /*0a99*/ 0x0000000c, + /*0a9a*/ 0x0000000c, + /*0a9b*/ 0x00000033, + /*0a9c*/ 0x00000000, + /*0a9d*/ 0x00000000, + /*0a9e*/ 0x00000000, + /*0a9f*/ 0x0002c06e, + /*0aa0*/ 0x02c002c0, + /*0aa1*/ 0x02c002c0, + /*0aa2*/ 0x000002c0, + /*0aa3*/ 0x42080010, + /*0aa4*/ 0x00000003 }; static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = { -/*0b80*/ 0x00000001, -/*0b81*/ 0x00000000, -/*0b82*/ 0x00000005, -/*0b83*/ 0x04000f00, -/*0b84*/ 0x00020080, -/*0b85*/ 0x00020055, -/*0b86*/ 0x00000000, -/*0b87*/ 0x00000000, -/*0b88*/ 0x00000000, -/*0b89*/ 0x00000050, -/*0b8a*/ 0x00000000, -/*0b8b*/ 0x01010100, -/*0b8c*/ 0x00000600, -/*0b8d*/ 0x50640000, -/*0b8e*/ 0x01421142, -/*0b8f*/ 0x00000142, -/*0b90*/ 0x00000000, -/*0b91*/ 0x000f1600, -/*0b92*/ 0x0f160f16, -/*0b93*/ 0x0f160f16, -/*0b94*/ 0x00000003, -/*0b95*/ 0x0002c000, -/*0b96*/ 0x02c002c0, -/*0b97*/ 0x000002c0, -/*0b98*/ 0x03421342, -/*0b99*/ 0x00000342, -/*0b9a*/ 0x00000000, -/*0b9b*/ 0x00000000, -/*0b9c*/ 0x05020000, -/*0b9d*/ 0x00000000, -/*0b9e*/ 0x00027f6e, -/*0b9f*/ 0x047f027f, -/*0ba0*/ 0x00027f6e, -/*0ba1*/ 0x00047f6e, -/*0ba2*/ 0x0003554f, -/*0ba3*/ 0x0001554f, -/*0ba4*/ 0x0001554f, -/*0ba5*/ 0x0001554f, -/*0ba6*/ 0x0001554f, -/*0ba7*/ 0x00003fee, -/*0ba8*/ 0x0001554f, -/*0ba9*/ 0x00003fee, -/*0baa*/ 0x0001554f, -/*0bab*/ 0x00027f6e, -/*0bac*/ 0x0001554f, -/*0bad*/ 0x00000000, -/*0bae*/ 0x00000000, -/*0baf*/ 0x00000000, -/*0bb0*/ 0x65000000, -/*0bb1*/ 0x00000000, -/*0bb2*/ 0x00000000, -/*0bb3*/ 0x00000201, -/*0bb4*/ 0x00000000, -/*0bb5*/ 0x00000000, -/*0bb6*/ 0x00000000, -/*0bb7*/ 0x00000000, -/*0bb8*/ 0x00000000, -/*0bb9*/ 0x00000000, -/*0bba*/ 0x00000000, -/*0bbb*/ 0x00000000, -/*0bbc*/ 0x06e40000, -/*0bbd*/ 0x00000000, -/*0bbe*/ 0x00000000, -/*0bbf*/ 0x00010000 + /*0b80*/ 0x00000001, + /*0b81*/ 0x00000000, + /*0b82*/ 0x00000005, + /*0b83*/ 0x04000f00, + /*0b84*/ 0x00020080, + /*0b85*/ 0x00020055, + /*0b86*/ 0x00000000, + /*0b87*/ 0x00000000, + /*0b88*/ 0x00000000, + /*0b89*/ 0x00000050, + /*0b8a*/ 0x00000000, + /*0b8b*/ 0x01010100, + /*0b8c*/ 0x00000600, + /*0b8d*/ 0x50640000, + /*0b8e*/ 0x01421142, + /*0b8f*/ 0x00000142, + /*0b90*/ 0x00000000, + /*0b91*/ 0x000f1600, + /*0b92*/ 0x0f160f16, + /*0b93*/ 0x0f160f16, + /*0b94*/ 0x00000003, + /*0b95*/ 0x0002c000, + /*0b96*/ 0x02c002c0, + /*0b97*/ 0x000002c0, + /*0b98*/ 0x03421342, + /*0b99*/ 0x00000342, + /*0b9a*/ 0x00000000, + /*0b9b*/ 0x00000000, + /*0b9c*/ 0x05020000, + /*0b9d*/ 0x00000000, + /*0b9e*/ 0x00027f6e, + /*0b9f*/ 0x047f027f, + /*0ba0*/ 0x00027f6e, + /*0ba1*/ 0x00047f6e, + /*0ba2*/ 0x0003554f, + /*0ba3*/ 0x0001554f, + /*0ba4*/ 0x0001554f, + /*0ba5*/ 0x0001554f, + /*0ba6*/ 0x0001554f, + /*0ba7*/ 0x00003fee, + /*0ba8*/ 0x0001554f, + /*0ba9*/ 0x00003fee, + /*0baa*/ 0x0001554f, + /*0bab*/ 0x00027f6e, + /*0bac*/ 0x0001554f, + /*0bad*/ 0x00000000, + /*0bae*/ 0x00000000, + /*0baf*/ 0x00000000, + /*0bb0*/ 0x65000000, + /*0bb1*/ 0x00000000, + /*0bb2*/ 0x00000000, + /*0bb3*/ 0x00000201, + /*0bb4*/ 0x00000000, + /*0bb5*/ 0x00000000, + /*0bb6*/ 0x00000000, + /*0bb7*/ 0x00000000, + /*0bb8*/ 0x00000000, + /*0bb9*/ 0x00000000, + /*0bba*/ 0x00000000, + /*0bbb*/ 0x00000000, + /*0bbc*/ 0x06e40000, + /*0bbd*/ 0x00000000, + /*0bbe*/ 0x00000000, + /*0bbf*/ 0x00010000 }; static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = { -/*0200*/ 0x00000b00, -/*0201*/ 0x00000100, -/*0202*/ 0x00000000, -/*0203*/ 0x0000ffff, -/*0204*/ 0x00000000, -/*0205*/ 0x0000ffff, -/*0206*/ 0x00000000, -/*0207*/ 0x304cffff, -/*0208*/ 0x00000200, -/*0209*/ 0x00000200, -/*020a*/ 0x00000200, -/*020b*/ 0x00000200, -/*020c*/ 0x0000304c, -/*020d*/ 0x00000200, -/*020e*/ 0x00000200, -/*020f*/ 0x00000200, -/*0210*/ 0x00000200, -/*0211*/ 0x0000304c, -/*0212*/ 0x00000200, -/*0213*/ 0x00000200, -/*0214*/ 0x00000200, -/*0215*/ 0x00000200, -/*0216*/ 0x00010000, -/*0217*/ 0x00000003, -/*0218*/ 0x01000001, -/*0219*/ 0x00000000, -/*021a*/ 0x00000000, -/*021b*/ 0x00000000, -/*021c*/ 0x00000000, -/*021d*/ 0x00000000, -/*021e*/ 0x00000000, -/*021f*/ 0x00000000, -/*0220*/ 0x00000000, -/*0221*/ 0x00000000, -/*0222*/ 0x00000000, -/*0223*/ 0x00000000, -/*0224*/ 0x00000000, -/*0225*/ 0x00000000, -/*0226*/ 0x00000000, -/*0227*/ 0x00000000, -/*0228*/ 0x00000000, -/*0229*/ 0x0f000101, -/*022a*/ 0x08492d25, -/*022b*/ 0x0e0c0004, -/*022c*/ 0x000e5000, -/*022d*/ 0x00000250, -/*022e*/ 0x00460003, -/*022f*/ 0x182600cf, -/*0230*/ 0x182600cf, -/*0231*/ 0x00000005, -/*0232*/ 0x00000000, -/*0233*/ 0x00000000, -/*0234*/ 0x00000000, -/*0235*/ 0x00000000, -/*0236*/ 0x00000000, -/*0237*/ 0x00000000, -/*0238*/ 0x00000000, -/*0239*/ 0x01000000, -/*023a*/ 0x00040404, -/*023b*/ 0x01280a00, -/*023c*/ 0x00000000, -/*023d*/ 0x000f0000, -/*023e*/ 0x00001803, -/*023f*/ 0x00000000, -/*0240*/ 0x00000000, -/*0241*/ 0x00060002, -/*0242*/ 0x00010001, -/*0243*/ 0x01000101, -/*0244*/ 0x04020201, -/*0245*/ 0x00080804, -/*0246*/ 0x00000000, -/*0247*/ 0x08030000, -/*0248*/ 0x15150408, -/*0249*/ 0x00000000, -/*024a*/ 0x00000000, -/*024b*/ 0x00000000, -/*024c*/ 0x000f0f00, -/*024d*/ 0x0000001e, -/*024e*/ 0x00000000, -/*024f*/ 0x01000300, -/*0250*/ 0x00000000, -/*0251*/ 0x00000000, -/*0252*/ 0x01000000, -/*0253*/ 0x00010101, -/*0254*/ 0x000e0e0e, -/*0255*/ 0x000c0c0c, -/*0256*/ 0x02060601, -/*0257*/ 0x00000000, -/*0258*/ 0x00000003, -/*0259*/ 0x00181703, -/*025a*/ 0x00280006, -/*025b*/ 0x00280016, -/*025c*/ 0x00000016, -/*025d*/ 0x00000000, -/*025e*/ 0x00000000, -/*025f*/ 0x00000000, -/*0260*/ 0x140a0000, -/*0261*/ 0x0005010a, -/*0262*/ 0x03018d03, -/*0263*/ 0x000a018d, -/*0264*/ 0x00060100, -/*0265*/ 0x01000006, -/*0266*/ 0x018e018e, -/*0267*/ 0x018e0100, -/*0268*/ 0x1111018e, -/*0269*/ 0x10010204, -/*026a*/ 0x09090650, -/*026b*/ 0x20110202, -/*026c*/ 0x00201000, -/*026d*/ 0x00201000, -/*026e*/ 0x04041000, -/*026f*/ 0x18020100, -/*0270*/ 0x00010118, -/*0271*/ 0x004b004a, -/*0272*/ 0x050f0000, -/*0273*/ 0x0c01021e, -/*0274*/ 0x34000000, -/*0275*/ 0x00000000, -/*0276*/ 0x00000000, -/*0277*/ 0x00000000, -/*0278*/ 0x0000d400, -/*0279*/ 0x0031002e, -/*027a*/ 0x00111136, -/*027b*/ 0x002e00d4, -/*027c*/ 0x11360031, -/*027d*/ 0x0000d411, -/*027e*/ 0x0031002e, -/*027f*/ 0x00111136, -/*0280*/ 0x002e00d4, -/*0281*/ 0x11360031, -/*0282*/ 0x0000d411, -/*0283*/ 0x0031002e, -/*0284*/ 0x00111136, -/*0285*/ 0x002e00d4, -/*0286*/ 0x11360031, -/*0287*/ 0x00d40011, -/*0288*/ 0x0031002e, -/*0289*/ 0x00111136, -/*028a*/ 0x002e00d4, -/*028b*/ 0x11360031, -/*028c*/ 0x0000d411, -/*028d*/ 0x0031002e, -/*028e*/ 0x00111136, -/*028f*/ 0x002e00d4, -/*0290*/ 0x11360031, -/*0291*/ 0x0000d411, -/*0292*/ 0x0031002e, -/*0293*/ 0x00111136, -/*0294*/ 0x002e00d4, -/*0295*/ 0x11360031, -/*0296*/ 0x02000011, -/*0297*/ 0x018d018d, -/*0298*/ 0x0c08018d, -/*0299*/ 0x1f121d22, -/*029a*/ 0x4301b344, -/*029b*/ 0x10172006, -/*029c*/ 0x1d220c10, -/*029d*/ 0x00001f12, -/*029e*/ 0x4301b344, -/*029f*/ 0x10172006, -/*02a0*/ 0x1d220c10, -/*02a1*/ 0x00001f12, -/*02a2*/ 0x4301b344, -/*02a3*/ 0x10172006, -/*02a4*/ 0x02000210, -/*02a5*/ 0x02000200, -/*02a6*/ 0x02000200, -/*02a7*/ 0x02000200, -/*02a8*/ 0x02000200, -/*02a9*/ 0x00000000, -/*02aa*/ 0x00000000, -/*02ab*/ 0x00000000, -/*02ac*/ 0x00000000, -/*02ad*/ 0x00000000, -/*02ae*/ 0x00000000, -/*02af*/ 0x00000000, -/*02b0*/ 0x00000000, -/*02b1*/ 0x00000000, -/*02b2*/ 0x00000000, -/*02b3*/ 0x00000000, -/*02b4*/ 0x00000000, -/*02b5*/ 0x00000400, -/*02b6*/ 0x15141312, -/*02b7*/ 0x11100f0e, -/*02b8*/ 0x080b0c0d, -/*02b9*/ 0x05040a09, -/*02ba*/ 0x01000706, -/*02bb*/ 0x00000302, -/*02bc*/ 0x01030201, -/*02bd*/ 0x00304c00, -/*02be*/ 0x0001e2f8, -/*02bf*/ 0x0000304c, -/*02c0*/ 0x0001e2f8, -/*02c1*/ 0x0000304c, -/*02c2*/ 0x0001e2f8, -/*02c3*/ 0x08000000, -/*02c4*/ 0x00000100, -/*02c5*/ 0x00000000, -/*02c6*/ 0x00000000, -/*02c7*/ 0x00000000, -/*02c8*/ 0x00000000, -/*02c9*/ 0x00000002 + /*0200*/ 0x00000b00, + /*0201*/ 0x00000100, + /*0202*/ 0x00000000, + /*0203*/ 0x0000ffff, + /*0204*/ 0x00000000, + /*0205*/ 0x0000ffff, + /*0206*/ 0x00000000, + /*0207*/ 0x304cffff, + /*0208*/ 0x00000200, + /*0209*/ 0x00000200, + /*020a*/ 0x00000200, + /*020b*/ 0x00000200, + /*020c*/ 0x0000304c, + /*020d*/ 0x00000200, + /*020e*/ 0x00000200, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x0000304c, + /*0212*/ 0x00000200, + /*0213*/ 0x00000200, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00010000, + /*0217*/ 0x00000003, + /*0218*/ 0x01000001, + /*0219*/ 0x00000000, + /*021a*/ 0x00000000, + /*021b*/ 0x00000000, + /*021c*/ 0x00000000, + /*021d*/ 0x00000000, + /*021e*/ 0x00000000, + /*021f*/ 0x00000000, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x0f000101, + /*022a*/ 0x08492d25, + /*022b*/ 0x0e0c0004, + /*022c*/ 0x000e5000, + /*022d*/ 0x00000250, + /*022e*/ 0x00460003, + /*022f*/ 0x182600cf, + /*0230*/ 0x182600cf, + /*0231*/ 0x00000005, + /*0232*/ 0x00000000, + /*0233*/ 0x00000000, + /*0234*/ 0x00000000, + /*0235*/ 0x00000000, + /*0236*/ 0x00000000, + /*0237*/ 0x00000000, + /*0238*/ 0x00000000, + /*0239*/ 0x01000000, + /*023a*/ 0x00040404, + /*023b*/ 0x01280a00, + /*023c*/ 0x00000000, + /*023d*/ 0x000f0000, + /*023e*/ 0x00001803, + /*023f*/ 0x00000000, + /*0240*/ 0x00000000, + /*0241*/ 0x00060002, + /*0242*/ 0x00010001, + /*0243*/ 0x01000101, + /*0244*/ 0x04020201, + /*0245*/ 0x00080804, + /*0246*/ 0x00000000, + /*0247*/ 0x08030000, + /*0248*/ 0x15150408, + /*0249*/ 0x00000000, + /*024a*/ 0x00000000, + /*024b*/ 0x00000000, + /*024c*/ 0x000f0f00, + /*024d*/ 0x0000001e, + /*024e*/ 0x00000000, + /*024f*/ 0x01000300, + /*0250*/ 0x00000000, + /*0251*/ 0x00000000, + /*0252*/ 0x01000000, + /*0253*/ 0x00010101, + /*0254*/ 0x000e0e0e, + /*0255*/ 0x000c0c0c, + /*0256*/ 0x02060601, + /*0257*/ 0x00000000, + /*0258*/ 0x00000003, + /*0259*/ 0x00181703, + /*025a*/ 0x00280006, + /*025b*/ 0x00280016, + /*025c*/ 0x00000016, + /*025d*/ 0x00000000, + /*025e*/ 0x00000000, + /*025f*/ 0x00000000, + /*0260*/ 0x140a0000, + /*0261*/ 0x0005010a, + /*0262*/ 0x03018d03, + /*0263*/ 0x000a018d, + /*0264*/ 0x00060100, + /*0265*/ 0x01000006, + /*0266*/ 0x018e018e, + /*0267*/ 0x018e0100, + /*0268*/ 0x1111018e, + /*0269*/ 0x10010204, + /*026a*/ 0x09090650, + /*026b*/ 0x20110202, + /*026c*/ 0x00201000, + /*026d*/ 0x00201000, + /*026e*/ 0x04041000, + /*026f*/ 0x18020100, + /*0270*/ 0x00010118, + /*0271*/ 0x004b004a, + /*0272*/ 0x050f0000, + /*0273*/ 0x0c01021e, + /*0274*/ 0x34000000, + /*0275*/ 0x00000000, + /*0276*/ 0x00000000, + /*0277*/ 0x00000000, + /*0278*/ 0x0000d400, + /*0279*/ 0x0031002e, + /*027a*/ 0x00111136, + /*027b*/ 0x002e00d4, + /*027c*/ 0x11360031, + /*027d*/ 0x0000d411, + /*027e*/ 0x0031002e, + /*027f*/ 0x00111136, + /*0280*/ 0x002e00d4, + /*0281*/ 0x11360031, + /*0282*/ 0x0000d411, + /*0283*/ 0x0031002e, + /*0284*/ 0x00111136, + /*0285*/ 0x002e00d4, + /*0286*/ 0x11360031, + /*0287*/ 0x00d40011, + /*0288*/ 0x0031002e, + /*0289*/ 0x00111136, + /*028a*/ 0x002e00d4, + /*028b*/ 0x11360031, + /*028c*/ 0x0000d411, + /*028d*/ 0x0031002e, + /*028e*/ 0x00111136, + /*028f*/ 0x002e00d4, + /*0290*/ 0x11360031, + /*0291*/ 0x0000d411, + /*0292*/ 0x0031002e, + /*0293*/ 0x00111136, + /*0294*/ 0x002e00d4, + /*0295*/ 0x11360031, + /*0296*/ 0x02000011, + /*0297*/ 0x018d018d, + /*0298*/ 0x0c08018d, + /*0299*/ 0x1f121d22, + /*029a*/ 0x4301b344, + /*029b*/ 0x10172006, + /*029c*/ 0x1d220c10, + /*029d*/ 0x00001f12, + /*029e*/ 0x4301b344, + /*029f*/ 0x10172006, + /*02a0*/ 0x1d220c10, + /*02a1*/ 0x00001f12, + /*02a2*/ 0x4301b344, + /*02a3*/ 0x10172006, + /*02a4*/ 0x02000210, + /*02a5*/ 0x02000200, + /*02a6*/ 0x02000200, + /*02a7*/ 0x02000200, + /*02a8*/ 0x02000200, + /*02a9*/ 0x00000000, + /*02aa*/ 0x00000000, + /*02ab*/ 0x00000000, + /*02ac*/ 0x00000000, + /*02ad*/ 0x00000000, + /*02ae*/ 0x00000000, + /*02af*/ 0x00000000, + /*02b0*/ 0x00000000, + /*02b1*/ 0x00000000, + /*02b2*/ 0x00000000, + /*02b3*/ 0x00000000, + /*02b4*/ 0x00000000, + /*02b5*/ 0x00000400, + /*02b6*/ 0x15141312, + /*02b7*/ 0x11100f0e, + /*02b8*/ 0x080b0c0d, + /*02b9*/ 0x05040a09, + /*02ba*/ 0x01000706, + /*02bb*/ 0x00000302, + /*02bc*/ 0x01030201, + /*02bd*/ 0x00304c00, + /*02be*/ 0x0001e2f8, + /*02bf*/ 0x0000304c, + /*02c0*/ 0x0001e2f8, + /*02c1*/ 0x0000304c, + /*02c2*/ 0x0001e2f8, + /*02c3*/ 0x08000000, + /*02c4*/ 0x00000100, + /*02c5*/ 0x00000000, + /*02c6*/ 0x00000000, + /*02c7*/ 0x00000000, + /*02c8*/ 0x00000000, + /*02c9*/ 0x00000002 }; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h index 42c335196..996d91448 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,564 +24,564 @@ #define DDR_PI_REGSET_NUM_M3N 286 static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = { -/*0800*/ 0x76543210, -/*0801*/ 0x0004f008, -/*0802*/ 0x00020200, -/*0803*/ 0x00000000, -/*0804*/ 0x00000000, -/*0805*/ 0x00010000, -/*0806*/ 0x036e6e0e, -/*0807*/ 0x026e6e0e, -/*0808*/ 0x00000103, -/*0809*/ 0x00040001, -/*080a*/ 0x00000103, -/*080b*/ 0x00000001, -/*080c*/ 0x00000000, -/*080d*/ 0x00000000, -/*080e*/ 0x00000100, -/*080f*/ 0x001800c0, -/*0810*/ 0x020100b0, -/*0811*/ 0x00030020, -/*0812*/ 0x00000000, -/*0813*/ 0x00000000, -/*0814*/ 0x0000aaaa, -/*0815*/ 0x00005555, -/*0816*/ 0x0000b5b5, -/*0817*/ 0x00004a4a, -/*0818*/ 0x00000000, -/*0819*/ 0x09000000, -/*081a*/ 0x04080000, -/*081b*/ 0x08040000, -/*081c*/ 0x00000004, -/*081d*/ 0x00800710, -/*081e*/ 0x000f000c, -/*081f*/ 0x00000100, -/*0820*/ 0x55aa55aa, -/*0821*/ 0x33cc33cc, -/*0822*/ 0x0ff00ff0, -/*0823*/ 0x0f0ff0f0, -/*0824*/ 0x00018e38, -/*0825*/ 0x00000000, -/*0826*/ 0x00000000, -/*0827*/ 0x00000000, -/*0828*/ 0x00000000, -/*0829*/ 0x00000000, -/*082a*/ 0x00000000, -/*082b*/ 0x00000000, -/*082c*/ 0x00000000, -/*082d*/ 0x00000000, -/*082e*/ 0x00000000, -/*082f*/ 0x00000000, -/*0830*/ 0x00000000, -/*0831*/ 0x00000000, -/*0832*/ 0x00000000, -/*0833*/ 0x00000000, -/*0834*/ 0x00000000, -/*0835*/ 0x00000000, -/*0836*/ 0x00000000, -/*0837*/ 0x00000000, -/*0838*/ 0x00000000, -/*0839*/ 0x00000000, -/*083a*/ 0x00000104, -/*083b*/ 0x00082020, -/*083c*/ 0x08200820, -/*083d*/ 0x08200820, -/*083e*/ 0x08200820, -/*083f*/ 0x08200820, -/*0840*/ 0x08200820, -/*0841*/ 0x00000000, -/*0842*/ 0x00000000, -/*0843*/ 0x03000300, -/*0844*/ 0x03000300, -/*0845*/ 0x03000300, -/*0846*/ 0x03000300, -/*0847*/ 0x00000300, -/*0848*/ 0x00000000, -/*0849*/ 0x00000000, -/*084a*/ 0x00000000, -/*084b*/ 0x00000000, -/*084c*/ 0x00000000, -/*084d*/ 0x00a000a0, -/*084e*/ 0x00a000a0, -/*084f*/ 0x00a000a0, -/*0850*/ 0x00a000a0, -/*0851*/ 0x00a000a0, -/*0852*/ 0x00a000a0, -/*0853*/ 0x00a000a0, -/*0854*/ 0x00a000a0, -/*0855*/ 0x00a000a0, -/*0856*/ 0x01040119, -/*0857*/ 0x00000200, -/*0858*/ 0x01000000, -/*0859*/ 0x00000200, -/*085a*/ 0x00000004, -/*085b*/ 0x4041a141, -/*085c*/ 0x0141c0a0, -/*085d*/ 0x0000c0c0, -/*085e*/ 0x0e0c000e, -/*085f*/ 0x10001000, -/*0860*/ 0x0c073e42, -/*0861*/ 0x000f0c28, -/*0862*/ 0x00e00140, -/*0863*/ 0x000c0020, -/*0864*/ 0x00000203 + /*0800*/ 0x76543210, + /*0801*/ 0x0004f008, + /*0802*/ 0x00020200, + /*0803*/ 0x00000000, + /*0804*/ 0x00000000, + /*0805*/ 0x00010000, + /*0806*/ 0x036e6e0e, + /*0807*/ 0x026e6e0e, + /*0808*/ 0x00000103, + /*0809*/ 0x00040001, + /*080a*/ 0x00000103, + /*080b*/ 0x00000001, + /*080c*/ 0x00000000, + /*080d*/ 0x00000000, + /*080e*/ 0x00000100, + /*080f*/ 0x001800c0, + /*0810*/ 0x020100b0, + /*0811*/ 0x00030020, + /*0812*/ 0x00000000, + /*0813*/ 0x00000000, + /*0814*/ 0x0000aaaa, + /*0815*/ 0x00005555, + /*0816*/ 0x0000b5b5, + /*0817*/ 0x00004a4a, + /*0818*/ 0x00000000, + /*0819*/ 0x09000000, + /*081a*/ 0x04080000, + /*081b*/ 0x08040000, + /*081c*/ 0x00000004, + /*081d*/ 0x00800710, + /*081e*/ 0x000f000c, + /*081f*/ 0x00000100, + /*0820*/ 0x55aa55aa, + /*0821*/ 0x33cc33cc, + /*0822*/ 0x0ff00ff0, + /*0823*/ 0x0f0ff0f0, + /*0824*/ 0x00018e38, + /*0825*/ 0x00000000, + /*0826*/ 0x00000000, + /*0827*/ 0x00000000, + /*0828*/ 0x00000000, + /*0829*/ 0x00000000, + /*082a*/ 0x00000000, + /*082b*/ 0x00000000, + /*082c*/ 0x00000000, + /*082d*/ 0x00000000, + /*082e*/ 0x00000000, + /*082f*/ 0x00000000, + /*0830*/ 0x00000000, + /*0831*/ 0x00000000, + /*0832*/ 0x00000000, + /*0833*/ 0x00000000, + /*0834*/ 0x00000000, + /*0835*/ 0x00000000, + /*0836*/ 0x00000000, + /*0837*/ 0x00000000, + /*0838*/ 0x00000000, + /*0839*/ 0x00000000, + /*083a*/ 0x00000104, + /*083b*/ 0x00082020, + /*083c*/ 0x08200820, + /*083d*/ 0x08200820, + /*083e*/ 0x08200820, + /*083f*/ 0x08200820, + /*0840*/ 0x08200820, + /*0841*/ 0x00000000, + /*0842*/ 0x00000000, + /*0843*/ 0x03000300, + /*0844*/ 0x03000300, + /*0845*/ 0x03000300, + /*0846*/ 0x03000300, + /*0847*/ 0x00000300, + /*0848*/ 0x00000000, + /*0849*/ 0x00000000, + /*084a*/ 0x00000000, + /*084b*/ 0x00000000, + /*084c*/ 0x00000000, + /*084d*/ 0x00a000a0, + /*084e*/ 0x00a000a0, + /*084f*/ 0x00a000a0, + /*0850*/ 0x00a000a0, + /*0851*/ 0x00a000a0, + /*0852*/ 0x00a000a0, + /*0853*/ 0x00a000a0, + /*0854*/ 0x00a000a0, + /*0855*/ 0x00a000a0, + /*0856*/ 0x01040119, + /*0857*/ 0x00000200, + /*0858*/ 0x01000000, + /*0859*/ 0x00000200, + /*085a*/ 0x00000004, + /*085b*/ 0x4041a141, + /*085c*/ 0x0141c0a0, + /*085d*/ 0x0000c0c0, + /*085e*/ 0x0e0c000e, + /*085f*/ 0x10001000, + /*0860*/ 0x0c073e42, + /*0861*/ 0x000f0c28, + /*0862*/ 0x00e00140, + /*0863*/ 0x000c0020, + /*0864*/ 0x00000203 }; static const uint32_t DDR_PHY_ADR_V_REGSET_M3N[DDR_PHY_ADR_V_REGSET_NUM_M3N] = { -/*0a00*/ 0x00000000, -/*0a01*/ 0x00000000, -/*0a02*/ 0x00000000, -/*0a03*/ 0x00000000, -/*0a04*/ 0x00000000, -/*0a05*/ 0x00000000, -/*0a06*/ 0x00000000, -/*0a07*/ 0x01000000, -/*0a08*/ 0x00020000, -/*0a09*/ 0x00000000, -/*0a0a*/ 0x00000000, -/*0a0b*/ 0x00000000, -/*0a0c*/ 0x00400000, -/*0a0d*/ 0x00000080, -/*0a0e*/ 0x00dcba98, -/*0a0f*/ 0x03000000, -/*0a10*/ 0x00000200, -/*0a11*/ 0x00000000, -/*0a12*/ 0x00000000, -/*0a13*/ 0x00000000, -/*0a14*/ 0x0000002a, -/*0a15*/ 0x00000015, -/*0a16*/ 0x00000015, -/*0a17*/ 0x0000002a, -/*0a18*/ 0x00000033, -/*0a19*/ 0x0000000c, -/*0a1a*/ 0x0000000c, -/*0a1b*/ 0x00000033, -/*0a1c*/ 0x0a418820, -/*0a1d*/ 0x003f0000, -/*0a1e*/ 0x0000013f, -/*0a1f*/ 0x0002c06e, -/*0a20*/ 0x02c002c0, -/*0a21*/ 0x02c002c0, -/*0a22*/ 0x000002c0, -/*0a23*/ 0x42080010, -/*0a24*/ 0x0000033e + /*0a00*/ 0x00000000, + /*0a01*/ 0x00000000, + /*0a02*/ 0x00000000, + /*0a03*/ 0x00000000, + /*0a04*/ 0x00000000, + /*0a05*/ 0x00000000, + /*0a06*/ 0x00000000, + /*0a07*/ 0x01000000, + /*0a08*/ 0x00020000, + /*0a09*/ 0x00000000, + /*0a0a*/ 0x00000000, + /*0a0b*/ 0x00000000, + /*0a0c*/ 0x00400000, + /*0a0d*/ 0x00000080, + /*0a0e*/ 0x00dcba98, + /*0a0f*/ 0x03000000, + /*0a10*/ 0x00000200, + /*0a11*/ 0x00000000, + /*0a12*/ 0x00000000, + /*0a13*/ 0x00000000, + /*0a14*/ 0x0000002a, + /*0a15*/ 0x00000015, + /*0a16*/ 0x00000015, + /*0a17*/ 0x0000002a, + /*0a18*/ 0x00000033, + /*0a19*/ 0x0000000c, + /*0a1a*/ 0x0000000c, + /*0a1b*/ 0x00000033, + /*0a1c*/ 0x0a418820, + /*0a1d*/ 0x003f0000, + /*0a1e*/ 0x0000013f, + /*0a1f*/ 0x0002c06e, + /*0a20*/ 0x02c002c0, + /*0a21*/ 0x02c002c0, + /*0a22*/ 0x000002c0, + /*0a23*/ 0x42080010, + /*0a24*/ 0x0000033e }; static const uint32_t DDR_PHY_ADR_I_REGSET_M3N[DDR_PHY_ADR_I_REGSET_NUM_M3N] = { -/*0a80*/ 0x00000000, -/*0a81*/ 0x00000000, -/*0a82*/ 0x00000000, -/*0a83*/ 0x00000000, -/*0a84*/ 0x00000000, -/*0a85*/ 0x00000000, -/*0a86*/ 0x00000000, -/*0a87*/ 0x01000000, -/*0a88*/ 0x00020000, -/*0a89*/ 0x00000000, -/*0a8a*/ 0x00000000, -/*0a8b*/ 0x00000000, -/*0a8c*/ 0x00400000, -/*0a8d*/ 0x00000080, -/*0a8e*/ 0x00000000, -/*0a8f*/ 0x03000000, -/*0a90*/ 0x00000200, -/*0a91*/ 0x00000000, -/*0a92*/ 0x00000000, -/*0a93*/ 0x00000000, -/*0a94*/ 0x0000002a, -/*0a95*/ 0x00000015, -/*0a96*/ 0x00000015, -/*0a97*/ 0x0000002a, -/*0a98*/ 0x00000033, -/*0a99*/ 0x0000000c, -/*0a9a*/ 0x0000000c, -/*0a9b*/ 0x00000033, -/*0a9c*/ 0x00000000, -/*0a9d*/ 0x00000000, -/*0a9e*/ 0x00000000, -/*0a9f*/ 0x0002c06e, -/*0aa0*/ 0x02c002c0, -/*0aa1*/ 0x02c002c0, -/*0aa2*/ 0x000002c0, -/*0aa3*/ 0x42080010, -/*0aa4*/ 0x0000033e + /*0a80*/ 0x00000000, + /*0a81*/ 0x00000000, + /*0a82*/ 0x00000000, + /*0a83*/ 0x00000000, + /*0a84*/ 0x00000000, + /*0a85*/ 0x00000000, + /*0a86*/ 0x00000000, + /*0a87*/ 0x01000000, + /*0a88*/ 0x00020000, + /*0a89*/ 0x00000000, + /*0a8a*/ 0x00000000, + /*0a8b*/ 0x00000000, + /*0a8c*/ 0x00400000, + /*0a8d*/ 0x00000080, + /*0a8e*/ 0x00000000, + /*0a8f*/ 0x03000000, + /*0a90*/ 0x00000200, + /*0a91*/ 0x00000000, + /*0a92*/ 0x00000000, + /*0a93*/ 0x00000000, + /*0a94*/ 0x0000002a, + /*0a95*/ 0x00000015, + /*0a96*/ 0x00000015, + /*0a97*/ 0x0000002a, + /*0a98*/ 0x00000033, + /*0a99*/ 0x0000000c, + /*0a9a*/ 0x0000000c, + /*0a9b*/ 0x00000033, + /*0a9c*/ 0x00000000, + /*0a9d*/ 0x00000000, + /*0a9e*/ 0x00000000, + /*0a9f*/ 0x0002c06e, + /*0aa0*/ 0x02c002c0, + /*0aa1*/ 0x02c002c0, + /*0aa2*/ 0x000002c0, + /*0aa3*/ 0x42080010, + /*0aa4*/ 0x0000033e }; static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = { -/*0b80*/ 0x00000000, -/*0b81*/ 0x00000100, -/*0b82*/ 0x00000000, -/*0b83*/ 0x00050000, -/*0b84*/ 0x00000000, -/*0b85*/ 0x0004000f, -/*0b86*/ 0x00280080, -/*0b87*/ 0x02005502, -/*0b88*/ 0x00000000, -/*0b89*/ 0x00000000, -/*0b8a*/ 0x00000000, -/*0b8b*/ 0x00000050, -/*0b8c*/ 0x00000000, -/*0b8d*/ 0x01010100, -/*0b8e*/ 0x00010000, -/*0b8f*/ 0x00000000, -/*0b90*/ 0x00000101, -/*0b91*/ 0x00000000, -/*0b92*/ 0x00000000, -/*0b93*/ 0x00000000, -/*0b94*/ 0x00000000, -/*0b95*/ 0x00005064, -/*0b96*/ 0x01421142, -/*0b97*/ 0x00000142, -/*0b98*/ 0x00000000, -/*0b99*/ 0x000f1600, -/*0b9a*/ 0x0f160f16, -/*0b9b*/ 0x0f160f16, -/*0b9c*/ 0x00000003, -/*0b9d*/ 0x0002c000, -/*0b9e*/ 0x02c002c0, -/*0b9f*/ 0x000002c0, -/*0ba0*/ 0x08040201, -/*0ba1*/ 0x03421342, -/*0ba2*/ 0x00000342, -/*0ba3*/ 0x00000000, -/*0ba4*/ 0x00000000, -/*0ba5*/ 0x05030000, -/*0ba6*/ 0x00010700, -/*0ba7*/ 0x00000014, -/*0ba8*/ 0x00027f6e, -/*0ba9*/ 0x047f027f, -/*0baa*/ 0x00027f6e, -/*0bab*/ 0x00047f6e, -/*0bac*/ 0x0003554f, -/*0bad*/ 0x0001554f, -/*0bae*/ 0x0001554f, -/*0baf*/ 0x0001554f, -/*0bb0*/ 0x0001554f, -/*0bb1*/ 0x00003fee, -/*0bb2*/ 0x0001554f, -/*0bb3*/ 0x00003fee, -/*0bb4*/ 0x0001554f, -/*0bb5*/ 0x00027f6e, -/*0bb6*/ 0x0001554f, -/*0bb7*/ 0x00004011, -/*0bb8*/ 0x00004410, -/*0bb9*/ 0x00000000, -/*0bba*/ 0x00000000, -/*0bbb*/ 0x00000000, -/*0bbc*/ 0x00000265, -/*0bbd*/ 0x00000000, -/*0bbe*/ 0x00040401, -/*0bbf*/ 0x00000000, -/*0bc0*/ 0x03000000, -/*0bc1*/ 0x00000020, -/*0bc2*/ 0x00000000, -/*0bc3*/ 0x00000000, -/*0bc4*/ 0x04102006, -/*0bc5*/ 0x00041020, -/*0bc6*/ 0x01c98c98, -/*0bc7*/ 0x00400000, -/*0bc8*/ 0x00000000, -/*0bc9*/ 0x0001ffff, -/*0bca*/ 0x00000000, -/*0bcb*/ 0x00000000, -/*0bcc*/ 0x00000001, -/*0bcd*/ 0x00000000, -/*0bce*/ 0x00000000, -/*0bcf*/ 0x00000000, -/*0bd0*/ 0x76543210, -/*0bd1*/ 0x06010198, -/*0bd2*/ 0x00000000, -/*0bd3*/ 0x00000000, -/*0bd4*/ 0x04070000, -/*0bd5*/ 0x00000001, -/*0bd6*/ 0x00000f00 + /*0b80*/ 0x00000000, + /*0b81*/ 0x00000100, + /*0b82*/ 0x00000000, + /*0b83*/ 0x00050000, + /*0b84*/ 0x00000000, + /*0b85*/ 0x0004000f, + /*0b86*/ 0x00280080, + /*0b87*/ 0x02005502, + /*0b88*/ 0x00000000, + /*0b89*/ 0x00000000, + /*0b8a*/ 0x00000000, + /*0b8b*/ 0x00000050, + /*0b8c*/ 0x00000000, + /*0b8d*/ 0x01010100, + /*0b8e*/ 0x00010000, + /*0b8f*/ 0x00000000, + /*0b90*/ 0x00000101, + /*0b91*/ 0x00000000, + /*0b92*/ 0x00000000, + /*0b93*/ 0x00000000, + /*0b94*/ 0x00000000, + /*0b95*/ 0x00005064, + /*0b96*/ 0x01421142, + /*0b97*/ 0x00000142, + /*0b98*/ 0x00000000, + /*0b99*/ 0x000f1600, + /*0b9a*/ 0x0f160f16, + /*0b9b*/ 0x0f160f16, + /*0b9c*/ 0x00000003, + /*0b9d*/ 0x0002c000, + /*0b9e*/ 0x02c002c0, + /*0b9f*/ 0x000002c0, + /*0ba0*/ 0x08040201, + /*0ba1*/ 0x03421342, + /*0ba2*/ 0x00000342, + /*0ba3*/ 0x00000000, + /*0ba4*/ 0x00000000, + /*0ba5*/ 0x05030000, + /*0ba6*/ 0x00010700, + /*0ba7*/ 0x00000014, + /*0ba8*/ 0x00027f6e, + /*0ba9*/ 0x047f027f, + /*0baa*/ 0x00027f6e, + /*0bab*/ 0x00047f6e, + /*0bac*/ 0x0003554f, + /*0bad*/ 0x0001554f, + /*0bae*/ 0x0001554f, + /*0baf*/ 0x0001554f, + /*0bb0*/ 0x0001554f, + /*0bb1*/ 0x00003fee, + /*0bb2*/ 0x0001554f, + /*0bb3*/ 0x00003fee, + /*0bb4*/ 0x0001554f, + /*0bb5*/ 0x00027f6e, + /*0bb6*/ 0x0001554f, + /*0bb7*/ 0x00004011, + /*0bb8*/ 0x00004410, + /*0bb9*/ 0x00000000, + /*0bba*/ 0x00000000, + /*0bbb*/ 0x00000000, + /*0bbc*/ 0x00000265, + /*0bbd*/ 0x00000000, + /*0bbe*/ 0x00040401, + /*0bbf*/ 0x00000000, + /*0bc0*/ 0x03000000, + /*0bc1*/ 0x00000020, + /*0bc2*/ 0x00000000, + /*0bc3*/ 0x00000000, + /*0bc4*/ 0x04102006, + /*0bc5*/ 0x00041020, + /*0bc6*/ 0x01c98c98, + /*0bc7*/ 0x00400000, + /*0bc8*/ 0x00000000, + /*0bc9*/ 0x0001ffff, + /*0bca*/ 0x00000000, + /*0bcb*/ 0x00000000, + /*0bcc*/ 0x00000001, + /*0bcd*/ 0x00000000, + /*0bce*/ 0x00000000, + /*0bcf*/ 0x00000000, + /*0bd0*/ 0x76543210, + /*0bd1*/ 0x06010198, + /*0bd2*/ 0x00000000, + /*0bd3*/ 0x00000000, + /*0bd4*/ 0x04070000, + /*0bd5*/ 0x00000001, + /*0bd6*/ 0x00000f00 }; static const uint32_t DDR_PI_REGSET_M3N[DDR_PI_REGSET_NUM_M3N] = { -/*0200*/ 0x00000b00, -/*0201*/ 0x00000101, -/*0202*/ 0x01640000, -/*0203*/ 0x00000014, -/*0204*/ 0x00000014, -/*0205*/ 0x00000014, -/*0206*/ 0x00000014, -/*0207*/ 0x00000000, -/*0208*/ 0x00000000, -/*0209*/ 0x0000ffff, -/*020a*/ 0x00000000, -/*020b*/ 0x0000ffff, -/*020c*/ 0x00000000, -/*020d*/ 0x0000ffff, -/*020e*/ 0x0000304c, -/*020f*/ 0x00000200, -/*0210*/ 0x00000200, -/*0211*/ 0x00000200, -/*0212*/ 0x00000200, -/*0213*/ 0x0000304c, -/*0214*/ 0x00000200, -/*0215*/ 0x00000200, -/*0216*/ 0x00000200, -/*0217*/ 0x00000200, -/*0218*/ 0x0000304c, -/*0219*/ 0x00000200, -/*021a*/ 0x00000200, -/*021b*/ 0x00000200, -/*021c*/ 0x00000200, -/*021d*/ 0x00010000, -/*021e*/ 0x00000003, -/*021f*/ 0x01000001, -/*0220*/ 0x00000000, -/*0221*/ 0x00000000, -/*0222*/ 0x00000000, -/*0223*/ 0x00000000, -/*0224*/ 0x00000000, -/*0225*/ 0x00000000, -/*0226*/ 0x00000000, -/*0227*/ 0x00000000, -/*0228*/ 0x00000000, -/*0229*/ 0x00000000, -/*022a*/ 0x00000000, -/*022b*/ 0x00000000, -/*022c*/ 0x00000000, -/*022d*/ 0x00000000, -/*022e*/ 0x00000000, -/*022f*/ 0x00000000, -/*0230*/ 0x0f000101, -/*0231*/ 0x084d3129, -/*0232*/ 0x0e0c0004, -/*0233*/ 0x000e5000, -/*0234*/ 0x01000250, -/*0235*/ 0x00000003, -/*0236*/ 0x00000046, -/*0237*/ 0x000000cf, -/*0238*/ 0x00001826, -/*0239*/ 0x000000cf, -/*023a*/ 0x00001826, -/*023b*/ 0x00000000, -/*023c*/ 0x00000000, -/*023d*/ 0x00000000, -/*023e*/ 0x00000000, -/*023f*/ 0x00000000, -/*0240*/ 0x00000000, -/*0241*/ 0x00000000, -/*0242*/ 0x00000000, -/*0243*/ 0x00000000, -/*0244*/ 0x00000000, -/*0245*/ 0x01000000, -/*0246*/ 0x00040404, -/*0247*/ 0x01280a00, -/*0248*/ 0x00000001, -/*0249*/ 0x00000000, -/*024a*/ 0x03000f00, -/*024b*/ 0x00200020, -/*024c*/ 0x00000020, -/*024d*/ 0x00000000, -/*024e*/ 0x00000000, -/*024f*/ 0x00010002, -/*0250*/ 0x01010001, -/*0251*/ 0x02010100, -/*0252*/ 0x08040402, -/*0253*/ 0x00000008, -/*0254*/ 0x00000000, -/*0255*/ 0x04080803, -/*0256*/ 0x00001515, -/*0257*/ 0x00000000, -/*0258*/ 0x000000aa, -/*0259*/ 0x00000055, -/*025a*/ 0x000000b5, -/*025b*/ 0x0000004a, -/*025c*/ 0x00000056, -/*025d*/ 0x000000a9, -/*025e*/ 0x000000a9, -/*025f*/ 0x000000b5, -/*0260*/ 0x00000000, -/*0261*/ 0x00000000, -/*0262*/ 0x0f000000, -/*0263*/ 0x00001e0f, -/*0264*/ 0x000007d0, -/*0265*/ 0x01000300, -/*0266*/ 0x00000100, -/*0267*/ 0x00000000, -/*0268*/ 0x00000000, -/*0269*/ 0x01000000, -/*026a*/ 0x00010101, -/*026b*/ 0x000e0e0e, -/*026c*/ 0x000c0c0c, -/*026d*/ 0x01060601, -/*026e*/ 0x04041717, -/*026f*/ 0x00000004, -/*0270*/ 0x00000300, -/*0271*/ 0x17030000, -/*0272*/ 0x00060018, -/*0273*/ 0x00160028, -/*0274*/ 0x00160028, -/*0275*/ 0x00000000, -/*0276*/ 0x00000000, -/*0277*/ 0x00000000, -/*0278*/ 0x0a000000, -/*0279*/ 0x00010a14, -/*027a*/ 0x00030005, -/*027b*/ 0x0003018d, -/*027c*/ 0x000a018d, -/*027d*/ 0x00060100, -/*027e*/ 0x01000006, -/*027f*/ 0x018e018e, -/*0280*/ 0x018e0100, -/*0281*/ 0x1e1a018e, -/*0282*/ 0x1e1a1e1a, -/*0283*/ 0x01010204, -/*0284*/ 0x06501001, -/*0285*/ 0x090d0a07, -/*0286*/ 0x090d0a07, -/*0287*/ 0x0811180f, -/*0288*/ 0x00ff1102, -/*0289*/ 0x00ff1000, -/*028a*/ 0x00ff1000, -/*028b*/ 0x04041000, -/*028c*/ 0x18020100, -/*028d*/ 0x01010018, -/*028e*/ 0x005f005f, -/*028f*/ 0x005f005f, -/*0290*/ 0x050f0000, -/*0291*/ 0x051e051e, -/*0292*/ 0x0c01021e, -/*0293*/ 0x00000c0c, -/*0294*/ 0x00003400, -/*0295*/ 0x00000000, -/*0296*/ 0x00000000, -/*0297*/ 0x00000000, -/*0298*/ 0x00000000, -/*0299*/ 0x002e00d4, -/*029a*/ 0x11360031, -/*029b*/ 0x00d41611, -/*029c*/ 0x0031002e, -/*029d*/ 0x16111136, -/*029e*/ 0x002e00d4, -/*029f*/ 0x11360031, -/*02a0*/ 0x00001611, -/*02a1*/ 0x002e00d4, -/*02a2*/ 0x11360031, -/*02a3*/ 0x00d41611, -/*02a4*/ 0x0031002e, -/*02a5*/ 0x16111136, -/*02a6*/ 0x002e00d4, -/*02a7*/ 0x11360031, -/*02a8*/ 0x00001611, -/*02a9*/ 0x002e00d4, -/*02aa*/ 0x11360031, -/*02ab*/ 0x00d41611, -/*02ac*/ 0x0031002e, -/*02ad*/ 0x16111136, -/*02ae*/ 0x002e00d4, -/*02af*/ 0x11360031, -/*02b0*/ 0x00001611, -/*02b1*/ 0x002e00d4, -/*02b2*/ 0x11360031, -/*02b3*/ 0x00d41611, -/*02b4*/ 0x0031002e, -/*02b5*/ 0x16111136, -/*02b6*/ 0x002e00d4, -/*02b7*/ 0x11360031, -/*02b8*/ 0x00001611, -/*02b9*/ 0x00018d00, -/*02ba*/ 0x018d018d, -/*02bb*/ 0x1d220c08, -/*02bc*/ 0x00001f12, -/*02bd*/ 0x4301b344, -/*02be*/ 0x17032006, -/*02bf*/ 0x220c1010, -/*02c0*/ 0x001f121d, -/*02c1*/ 0x4301b344, -/*02c2*/ 0x17062006, -/*02c3*/ 0x220c1010, -/*02c4*/ 0x001f121d, -/*02c5*/ 0x4301b344, -/*02c6*/ 0x17182006, -/*02c7*/ 0x00021010, -/*02c8*/ 0x00020002, -/*02c9*/ 0x00020002, -/*02ca*/ 0x00020002, -/*02cb*/ 0x00020002, -/*02cc*/ 0x00000002, -/*02cd*/ 0x00000000, -/*02ce*/ 0x00000000, -/*02cf*/ 0x00000000, -/*02d0*/ 0x00000000, -/*02d1*/ 0x00000000, -/*02d2*/ 0x00000000, -/*02d3*/ 0x00000000, -/*02d4*/ 0x00000000, -/*02d5*/ 0x00000000, -/*02d6*/ 0x00000000, -/*02d7*/ 0x00000000, -/*02d8*/ 0x00000000, -/*02d9*/ 0x00000400, -/*02da*/ 0x15141312, -/*02db*/ 0x11100f0e, -/*02dc*/ 0x080b0c0d, -/*02dd*/ 0x05040a09, -/*02de*/ 0x01000706, -/*02df*/ 0x00000302, -/*02e0*/ 0x01030201, -/*02e1*/ 0x00304c08, -/*02e2*/ 0x0001e2f8, -/*02e3*/ 0x0000304c, -/*02e4*/ 0x0001e2f8, -/*02e5*/ 0x0000304c, -/*02e6*/ 0x0001e2f8, -/*02e7*/ 0x08000000, -/*02e8*/ 0x00000100, -/*02e9*/ 0x00000000, -/*02ea*/ 0x00000000, -/*02eb*/ 0x00000000, -/*02ec*/ 0x00000000, -/*02ed*/ 0x00010000, -/*02ee*/ 0x00000000, -/*02ef*/ 0x00000000, -/*02f0*/ 0x00000000, -/*02f1*/ 0x00000000, -/*02f2*/ 0x00000000, -/*02f3*/ 0x00000000, -/*02f4*/ 0x00000000, -/*02f5*/ 0x00000000, -/*02f6*/ 0x00000000, -/*02f7*/ 0x00000000, -/*02f8*/ 0x00000000, -/*02f9*/ 0x00000000, -/*02fa*/ 0x00000000, -/*02fb*/ 0x00000000, -/*02fc*/ 0x00000000, -/*02fd*/ 0x00000000, -/*02fe*/ 0x00000000, -/*02ff*/ 0x00000000, -/*0300*/ 0x00000000, -/*0301*/ 0x00000000, -/*0302*/ 0x00000000, -/*0303*/ 0x00000000, -/*0304*/ 0x00000000, -/*0305*/ 0x00000000, -/*0306*/ 0x00000000, -/*0307*/ 0x00000000, -/*0308*/ 0x00000000, -/*0309*/ 0x00000000, -/*030a*/ 0x00000000, -/*030b*/ 0x00000000, -/*030c*/ 0x00000000, -/*030d*/ 0x00000000, -/*030e*/ 0x00000000, -/*030f*/ 0x00050002, -/*0310*/ 0x015c0057, -/*0311*/ 0x01000100, -/*0312*/ 0x01020001, -/*0313*/ 0x00010300, -/*0314*/ 0x05000104, -/*0315*/ 0x01060001, -/*0316*/ 0x00010700, -/*0317*/ 0x00000000, -/*0318*/ 0x00000000, -/*0319*/ 0x00000001, -/*031a*/ 0x00000000, -/*031b*/ 0x00000000, -/*031c*/ 0x00000000, -/*031d*/ 0x20080101 + /*0200*/ 0x00000b00, + /*0201*/ 0x00000101, + /*0202*/ 0x01640000, + /*0203*/ 0x00000014, + /*0204*/ 0x00000014, + /*0205*/ 0x00000014, + /*0206*/ 0x00000014, + /*0207*/ 0x00000000, + /*0208*/ 0x00000000, + /*0209*/ 0x0000ffff, + /*020a*/ 0x00000000, + /*020b*/ 0x0000ffff, + /*020c*/ 0x00000000, + /*020d*/ 0x0000ffff, + /*020e*/ 0x0000304c, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x00000200, + /*0212*/ 0x00000200, + /*0213*/ 0x0000304c, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00000200, + /*0217*/ 0x00000200, + /*0218*/ 0x0000304c, + /*0219*/ 0x00000200, + /*021a*/ 0x00000200, + /*021b*/ 0x00000200, + /*021c*/ 0x00000200, + /*021d*/ 0x00010000, + /*021e*/ 0x00000003, + /*021f*/ 0x01000001, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x00000000, + /*022a*/ 0x00000000, + /*022b*/ 0x00000000, + /*022c*/ 0x00000000, + /*022d*/ 0x00000000, + /*022e*/ 0x00000000, + /*022f*/ 0x00000000, + /*0230*/ 0x0f000101, + /*0231*/ 0x084d3129, + /*0232*/ 0x0e0c0004, + /*0233*/ 0x000e5000, + /*0234*/ 0x01000250, + /*0235*/ 0x00000003, + /*0236*/ 0x00000046, + /*0237*/ 0x000000cf, + /*0238*/ 0x00001826, + /*0239*/ 0x000000cf, + /*023a*/ 0x00001826, + /*023b*/ 0x00000000, + /*023c*/ 0x00000000, + /*023d*/ 0x00000000, + /*023e*/ 0x00000000, + /*023f*/ 0x00000000, + /*0240*/ 0x00000000, + /*0241*/ 0x00000000, + /*0242*/ 0x00000000, + /*0243*/ 0x00000000, + /*0244*/ 0x00000000, + /*0245*/ 0x01000000, + /*0246*/ 0x00040404, + /*0247*/ 0x01280a00, + /*0248*/ 0x00000001, + /*0249*/ 0x00000000, + /*024a*/ 0x03000f00, + /*024b*/ 0x00200020, + /*024c*/ 0x00000020, + /*024d*/ 0x00000000, + /*024e*/ 0x00000000, + /*024f*/ 0x00010002, + /*0250*/ 0x01010001, + /*0251*/ 0x02010100, + /*0252*/ 0x08040402, + /*0253*/ 0x00000008, + /*0254*/ 0x00000000, + /*0255*/ 0x04080803, + /*0256*/ 0x00001515, + /*0257*/ 0x00000000, + /*0258*/ 0x000000aa, + /*0259*/ 0x00000055, + /*025a*/ 0x000000b5, + /*025b*/ 0x0000004a, + /*025c*/ 0x00000056, + /*025d*/ 0x000000a9, + /*025e*/ 0x000000a9, + /*025f*/ 0x000000b5, + /*0260*/ 0x00000000, + /*0261*/ 0x00000000, + /*0262*/ 0x0f000000, + /*0263*/ 0x00001e0f, + /*0264*/ 0x000007d0, + /*0265*/ 0x01000300, + /*0266*/ 0x00000100, + /*0267*/ 0x00000000, + /*0268*/ 0x00000000, + /*0269*/ 0x01000000, + /*026a*/ 0x00010101, + /*026b*/ 0x000e0e0e, + /*026c*/ 0x000c0c0c, + /*026d*/ 0x01060601, + /*026e*/ 0x04041717, + /*026f*/ 0x00000004, + /*0270*/ 0x00000300, + /*0271*/ 0x17030000, + /*0272*/ 0x00060018, + /*0273*/ 0x00160028, + /*0274*/ 0x00160028, + /*0275*/ 0x00000000, + /*0276*/ 0x00000000, + /*0277*/ 0x00000000, + /*0278*/ 0x0a000000, + /*0279*/ 0x00010a14, + /*027a*/ 0x00030005, + /*027b*/ 0x0003018d, + /*027c*/ 0x000a018d, + /*027d*/ 0x00060100, + /*027e*/ 0x01000006, + /*027f*/ 0x018e018e, + /*0280*/ 0x018e0100, + /*0281*/ 0x1e1a018e, + /*0282*/ 0x1e1a1e1a, + /*0283*/ 0x01010204, + /*0284*/ 0x06501001, + /*0285*/ 0x090d0a07, + /*0286*/ 0x090d0a07, + /*0287*/ 0x0811180f, + /*0288*/ 0x00ff1102, + /*0289*/ 0x00ff1000, + /*028a*/ 0x00ff1000, + /*028b*/ 0x04041000, + /*028c*/ 0x18020100, + /*028d*/ 0x01010018, + /*028e*/ 0x005f005f, + /*028f*/ 0x005f005f, + /*0290*/ 0x050f0000, + /*0291*/ 0x051e051e, + /*0292*/ 0x0c01021e, + /*0293*/ 0x00000c0c, + /*0294*/ 0x00003400, + /*0295*/ 0x00000000, + /*0296*/ 0x00000000, + /*0297*/ 0x00000000, + /*0298*/ 0x00000000, + /*0299*/ 0x002e00d4, + /*029a*/ 0x11360031, + /*029b*/ 0x00d41611, + /*029c*/ 0x0031002e, + /*029d*/ 0x16111136, + /*029e*/ 0x002e00d4, + /*029f*/ 0x11360031, + /*02a0*/ 0x00001611, + /*02a1*/ 0x002e00d4, + /*02a2*/ 0x11360031, + /*02a3*/ 0x00d41611, + /*02a4*/ 0x0031002e, + /*02a5*/ 0x16111136, + /*02a6*/ 0x002e00d4, + /*02a7*/ 0x11360031, + /*02a8*/ 0x00001611, + /*02a9*/ 0x002e00d4, + /*02aa*/ 0x11360031, + /*02ab*/ 0x00d41611, + /*02ac*/ 0x0031002e, + /*02ad*/ 0x16111136, + /*02ae*/ 0x002e00d4, + /*02af*/ 0x11360031, + /*02b0*/ 0x00001611, + /*02b1*/ 0x002e00d4, + /*02b2*/ 0x11360031, + /*02b3*/ 0x00d41611, + /*02b4*/ 0x0031002e, + /*02b5*/ 0x16111136, + /*02b6*/ 0x002e00d4, + /*02b7*/ 0x11360031, + /*02b8*/ 0x00001611, + /*02b9*/ 0x00018d00, + /*02ba*/ 0x018d018d, + /*02bb*/ 0x1d220c08, + /*02bc*/ 0x00001f12, + /*02bd*/ 0x4301b344, + /*02be*/ 0x17032006, + /*02bf*/ 0x220c1010, + /*02c0*/ 0x001f121d, + /*02c1*/ 0x4301b344, + /*02c2*/ 0x17062006, + /*02c3*/ 0x220c1010, + /*02c4*/ 0x001f121d, + /*02c5*/ 0x4301b344, + /*02c6*/ 0x17182006, + /*02c7*/ 0x00021010, + /*02c8*/ 0x00020002, + /*02c9*/ 0x00020002, + /*02ca*/ 0x00020002, + /*02cb*/ 0x00020002, + /*02cc*/ 0x00000002, + /*02cd*/ 0x00000000, + /*02ce*/ 0x00000000, + /*02cf*/ 0x00000000, + /*02d0*/ 0x00000000, + /*02d1*/ 0x00000000, + /*02d2*/ 0x00000000, + /*02d3*/ 0x00000000, + /*02d4*/ 0x00000000, + /*02d5*/ 0x00000000, + /*02d6*/ 0x00000000, + /*02d7*/ 0x00000000, + /*02d8*/ 0x00000000, + /*02d9*/ 0x00000400, + /*02da*/ 0x15141312, + /*02db*/ 0x11100f0e, + /*02dc*/ 0x080b0c0d, + /*02dd*/ 0x05040a09, + /*02de*/ 0x01000706, + /*02df*/ 0x00000302, + /*02e0*/ 0x01030201, + /*02e1*/ 0x00304c08, + /*02e2*/ 0x0001e2f8, + /*02e3*/ 0x0000304c, + /*02e4*/ 0x0001e2f8, + /*02e5*/ 0x0000304c, + /*02e6*/ 0x0001e2f8, + /*02e7*/ 0x08000000, + /*02e8*/ 0x00000100, + /*02e9*/ 0x00000000, + /*02ea*/ 0x00000000, + /*02eb*/ 0x00000000, + /*02ec*/ 0x00000000, + /*02ed*/ 0x00010000, + /*02ee*/ 0x00000000, + /*02ef*/ 0x00000000, + /*02f0*/ 0x00000000, + /*02f1*/ 0x00000000, + /*02f2*/ 0x00000000, + /*02f3*/ 0x00000000, + /*02f4*/ 0x00000000, + /*02f5*/ 0x00000000, + /*02f6*/ 0x00000000, + /*02f7*/ 0x00000000, + /*02f8*/ 0x00000000, + /*02f9*/ 0x00000000, + /*02fa*/ 0x00000000, + /*02fb*/ 0x00000000, + /*02fc*/ 0x00000000, + /*02fd*/ 0x00000000, + /*02fe*/ 0x00000000, + /*02ff*/ 0x00000000, + /*0300*/ 0x00000000, + /*0301*/ 0x00000000, + /*0302*/ 0x00000000, + /*0303*/ 0x00000000, + /*0304*/ 0x00000000, + /*0305*/ 0x00000000, + /*0306*/ 0x00000000, + /*0307*/ 0x00000000, + /*0308*/ 0x00000000, + /*0309*/ 0x00000000, + /*030a*/ 0x00000000, + /*030b*/ 0x00000000, + /*030c*/ 0x00000000, + /*030d*/ 0x00000000, + /*030e*/ 0x00000000, + /*030f*/ 0x00050002, + /*0310*/ 0x015c0057, + /*0311*/ 0x01000100, + /*0312*/ 0x01020001, + /*0313*/ 0x00010300, + /*0314*/ 0x05000104, + /*0315*/ 0x01060001, + /*0316*/ 0x00010700, + /*0317*/ 0x00000000, + /*0318*/ 0x00000000, + /*0319*/ 0x00000001, + /*031a*/ 0x00000000, + /*031b*/ 0x00000000, + /*031c*/ 0x00000000, + /*031d*/ 0x20080101 }; -- cgit v1.2.3 From bf881832e81e1057153a8de4b0ab707cce3536cd Mon Sep 17 00:00:00 2001 From: Yoshifumi Hosoya Date: Mon, 1 Jul 2019 19:45:41 +0900 Subject: rcar_gen3: drivers: qos: update QoS setting [IPL/QoS] - Update M3 Ver.3.0 QoS setting rev.0.04. Signed-off-by: Yoshifumi Hosoya Signed-off-by: Marek Vasut Change-Id: I798401f417df6a352d94311ea07a1e96ba562f6a --- drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c | 2 +- drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h | 6 +++--- drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c index e300fd541..43d21d71c 100644 --- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c +++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c @@ -12,7 +12,7 @@ #include "../qos_reg.h" #include "qos_init_m3_v30.h" -#define RCAR_QOS_VERSION "rev.0.03" +#define RCAR_QOS_VERSION "rev.0.04" #define QOSWT_TIME_BANK0 20000000U /* unit:ns */ diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h index cd820e85e..2ab14dad3 100644 --- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h +++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h @@ -32,8 +32,8 @@ static uint64_t mstat_fix[] = { /* 0x00c0, */ 0x000C04020000FFFFUL, /* 0x00c8, */ 0x000C04010000FFFFUL, /* 0x00d0, */ 0x000C04010000FFFFUL, - /* 0x00d8, */ 0x000C100D0000FFFFUL, - /* 0x00e0, */ 0x000C1C1B0000FFFFUL, + /* 0x00d8, */ 0x000C08050000FFFFUL, + /* 0x00e0, */ 0x000C10100000FFFFUL, /* 0x00e8, */ 0x0000000000000000UL, /* 0x00f0, */ 0x001024090000FFFFUL, /* 0x00f8, */ 0x0000000000000000UL, @@ -41,7 +41,7 @@ static uint64_t mstat_fix[] = { /* 0x0108, */ 0x0000000000000000UL, /* 0x0110, */ 0x00100C090000FFFFUL, /* 0x0118, */ 0x0000000000000000UL, - /* 0x0120, */ 0x000C1C1B0000FFFFUL, + /* 0x0120, */ 0x000C10100000FFFFUL, /* 0x0128, */ 0x0000000000000000UL, /* 0x0130, */ 0x0000000000000000UL, /* 0x0138, */ 0x00100C0B0000FFFFUL, diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h index e9037e1fd..faac3d9fb 100644 --- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h +++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h @@ -32,8 +32,8 @@ static uint64_t mstat_fix[] = { /* 0x00c0, */ 0x000C08040000FFFFUL, /* 0x00c8, */ 0x000C04020000FFFFUL, /* 0x00d0, */ 0x000C04020000FFFFUL, - /* 0x00d8, */ 0x000C1C1A0000FFFFUL, - /* 0x00e0, */ 0x000C38360000FFFFUL, + /* 0x00d8, */ 0x000C0C0A0000FFFFUL, + /* 0x00e0, */ 0x000C201F0000FFFFUL, /* 0x00e8, */ 0x0000000000000000UL, /* 0x00f0, */ 0x001044110000FFFFUL, /* 0x00f8, */ 0x0000000000000000UL, @@ -41,7 +41,7 @@ static uint64_t mstat_fix[] = { /* 0x0108, */ 0x0000000000000000UL, /* 0x0110, */ 0x001014110000FFFFUL, /* 0x0118, */ 0x0000000000000000UL, - /* 0x0120, */ 0x000C38360000FFFFUL, + /* 0x0120, */ 0x000C201F0000FFFFUL, /* 0x0128, */ 0x0000000000000000UL, /* 0x0130, */ 0x0000000000000000UL, /* 0x0138, */ 0x001018150000FFFFUL, -- cgit v1.2.3 From fbee88fbb039c2d2a5f5c78fac74a1942146de95 Mon Sep 17 00:00:00 2001 From: Chiaki Fujii Date: Mon, 8 Jul 2019 23:44:56 +0900 Subject: rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N [IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.37. Signed-off-by: Chiaki Fujii Signed-off-by: Marek Vasut Change-Id: I072c0f61cd896e74e4e1eee39d313f82cf2f7295 --- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 39 ++++++++++++---------- .../renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h | 2 +- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h | 2 +- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h | 2 +- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h | 2 +- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h | 2 +- 6 files changed, 27 insertions(+), 22 deletions(-) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index 9c7f9c8ab..9f7c95490 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -90,7 +90,7 @@ static const struct _boardcnf *board_cnf; static uint32_t ddr_phyvalid; static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; static uint32_t ch_have_this_cs[CS_CNT] __aligned(64); -static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; +static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9]; static uint32_t max_density; static uint32_t ddr0800_mul; static uint32_t ddr_mul; @@ -358,15 +358,13 @@ static void pll3_control(uint32_t high) if (high) { tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr_mul) / 2; - data_mul = (((ddr_mul * tmp_div) - 1) << 24) | - (brd_clkdiva << 7); + data_mul = ((ddr_mul * tmp_div) - 1) << 24; pll3_mode = 1; loop_max = 2; } else { tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr0800_mul) / 2; - data_mul = (((ddr0800_mul * tmp_div) - 1) << 24) | - (brd_clkdiva << 7); + data_mul = ((ddr0800_mul * tmp_div) - 1) << 24; pll3_mode = 0; loop_max = 8; } @@ -2711,8 +2709,8 @@ static void ddr_register_set(void) uint32_t tmp; for (fspwp = 1; fspwp >= 0; fspwp--) { - /*MR13,fspwp */ - send_dbcmd(0x0e840d08 | (fspwp << 6)); + /*MR13, fspwp */ + send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6)); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, @@ -2745,7 +2743,16 @@ static void ddr_register_set(void) send_dbcmd(0x0e840e00 | tmp); /* MR22 */ send_dbcmd(0x0e841616); + + /* ZQCAL start */ + send_dbcmd(0x0d84004F); + + /* ZQLAT */ + send_dbcmd(0x0d840051); } + + /* MR13, fspwp */ + send_dbcmd(0x0e840d08); } /* Training handshake functions */ @@ -3038,12 +3045,6 @@ static uint32_t init_ddr(void) /* MRS */ ddr_register_set(); - /* ZQCAL start */ - send_dbcmd(0x0d84004F); - - /* ZQLAT */ - send_dbcmd(0x0d840051); - /* Thermal sensor setting */ /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; @@ -3478,17 +3479,21 @@ static uint32_t wdqdm_man(void) const uint32_t retry_max = 0x10; uint32_t ch, ddr_csn, mr14_bkup[4][4]; - ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12); + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, + (mmio_read_32(DBSC_DBTR(11)) & 0xFF) + 19); if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || (prr_product == PRR_PRODUCT_M3N) || (prr_product == PRR_PRODUCT_V3H)) { + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0, + (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, - (DBSC_DBTR(12) & 0xFF) + 1); + (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); } else { ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR, - (DBSC_DBTR(12) & 0xFF) + 1); + (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); } - ddr_setval_ach(_reg_PI_TRFC_F1, (DBSC_DBTR(13) & 0x1FF)); + ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); + ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); retry_cnt = 0; err = 0; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h index 8eb3859a3..5047e5cc2 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#define RCAR_DDR_VERSION "rev.0.36" +#define RCAR_DDR_VERSION "rev.0.37" #define DRAM_CH_CNT 0x04 #define SLICE_CNT 0x04 #define CS_CNT 0x02 diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h index 69db2a73d..357f8bad0 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h @@ -104,7 +104,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = { /*044d*/ 0x00000200, /*044e*/ 0x01000000, /*044f*/ 0x00000200, - /*0450*/ 0x4041a141, + /*0450*/ 0x4041a151, /*0451*/ 0xc00141a0, /*0452*/ 0x0e0100c0, /*0453*/ 0x0010000c, diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h index b94f308fb..e5258af6c 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h @@ -114,7 +114,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2 /*0456*/ 0x01000000, /*0457*/ 0x00000200, /*0458*/ 0x00000004, - /*0459*/ 0x4041a141, + /*0459*/ 0x4041a151, /*045a*/ 0xc00141a0, /*045b*/ 0x0e0000c0, /*045c*/ 0x0010000c, diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h index a09b00412..b491f0e91 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h @@ -105,7 +105,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = { /*084e*/ 0x00000000, /*084f*/ 0x00010000, /*0850*/ 0x00000200, - /*0851*/ 0x4041a141, + /*0851*/ 0x4041a151, /*0852*/ 0xc00141a0, /*0853*/ 0x0e0100c0, /*0854*/ 0x0010000c, diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h index 996d91448..8d80842fd 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h @@ -115,7 +115,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = { /*0858*/ 0x01000000, /*0859*/ 0x00000200, /*085a*/ 0x00000004, - /*085b*/ 0x4041a141, + /*085b*/ 0x4041a151, /*085c*/ 0x0141c0a0, /*085d*/ 0x0000c0c0, /*085e*/ 0x0e0c000e, -- cgit v1.2.3 From 53d7e003fef908db02bc78fb889aa4ab58c9af25 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Tue, 20 Aug 2019 10:58:49 +0100 Subject: Move assembly newline function into common debug code Printing a newline is a relatively common functionality for code to want to do. Therefore, this patch now moves this function into a common part of the code that anyone can use. Change-Id: I2cad699fde00ef8d2aabf8bf35742ddd88d090ba Signed-off-by: Justin Chadwell --- bl31/aarch64/crash_reporting.S | 12 ++---------- common/aarch64/debug.S | 10 ++++++++++ 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S index 2c4102981..f2c12961d 100644 --- a/bl31/aarch64/crash_reporting.S +++ b/bl31/aarch64/crash_reporting.S @@ -61,14 +61,6 @@ excpt_msg: intr_excpt_msg: .asciz "Unhandled Interrupt Exception in EL3.\nx30" - /* - * Helper function to print newline to console. - */ -func print_newline - mov x0, '\n' - b plat_crash_console_putc -endfunc print_newline - /* * Helper function to print from crash buf. * The print loop is controlled by the buf size and @@ -101,7 +93,7 @@ test_size_list: bl print_alignment ldr x4, [x7], #REGSZ bl asm_print_hex - bl print_newline + bl asm_print_newline b test_size_list exit_size_print: mov x30, sp @@ -253,7 +245,7 @@ func do_crash_reporting /* report x30 first from the crash buf */ ldr x4, [x0, #REGSZ * 7] bl asm_print_hex - bl print_newline + bl asm_print_newline /* Load the crash buf address */ mrs x0, tpidr_el3 /* Now mov x7 into crash buf */ diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S index ac47cbe9e..e6e329853 100644 --- a/common/aarch64/debug.S +++ b/common/aarch64/debug.S @@ -11,6 +11,7 @@ .globl asm_print_str .globl asm_print_hex .globl asm_print_hex_bits + .globl asm_print_newline .globl asm_assert .globl do_panic @@ -130,6 +131,15 @@ asm_print_hex_bits: ret x3 endfunc asm_print_hex +/* + * Helper function to print newline to console + * Clobber: x0 + */ +func asm_print_newline + mov x0, '\n' + b plat_crash_console_putc +endfunc asm_print_newline + /*********************************************************** * The common implementation of do_panic for all BL stages ***********************************************************/ -- cgit v1.2.3 From 532791127684b444c5aa59a6547624466a57b9a3 Mon Sep 17 00:00:00 2001 From: Artsem Artsemenka Date: Thu, 29 Aug 2019 13:47:53 +0100 Subject: Added SPCI to the glossary Change-Id: I576ae161477f4a69336d15a7741e566bb103124a Signed-off-by: Artsem Artsemenka --- docs/global_substitutions.txt | 1 + docs/glossary.rst | 3 +++ 2 files changed, 4 insertions(+) diff --git a/docs/global_substitutions.txt b/docs/global_substitutions.txt index 242e62c7c..fdca9c3f4 100644 --- a/docs/global_substitutions.txt +++ b/docs/global_substitutions.txt @@ -38,6 +38,7 @@ .. |SMCCC| replace:: :term:`SMCCC` .. |SoC| replace:: :term:`SoC` .. |SP| replace:: :term:`SP` +.. |SPCI| replace:: :term:`SPCI` .. |SPD| replace:: :term:`SPD` .. |SPM| replace:: :term:`SPM` .. |SVE| replace:: :term:`SVE` diff --git a/docs/glossary.rst b/docs/glossary.rst index afe0acf75..45caf4629 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -129,6 +129,9 @@ You can find additional definitions in the `Arm Glossary`_. SP Secure Partition + SPCI + Secure Partition Client Interface + SPD Secure Payload Dispatcher -- cgit v1.2.3 From 73680c230f8503a8e0f625834bc987b90e065b03 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 4 Jun 2019 18:06:34 +0200 Subject: stm32mp1: add watchdog support Introduce driver for STM32 IWDG peripheral (Independent Watchdog). It is configured according to device tree content and should be enabled from there. The watchdog is not started by default. It can be started after an HW reset if the dedicated OTP is fused. The watchdog also needs to be frozen if a debugger is attached. This is done by configuring the correct bits in DBGMCU. This configuration is allowed by checking BSEC properties. An increase of BL2 size is also required when adding this new code. Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f Signed-off-by: Yann Gautier Signed-off-by: Lionel Debieve Signed-off-by: Nicolas Le Bayon --- drivers/st/iwdg/stm32_iwdg.c | 150 +++++++++++++++++++++++++++++ include/drivers/st/stm32_iwdg.h | 19 ++++ plat/st/common/include/stm32mp_common.h | 11 +++ plat/st/stm32mp1/bl2_plat_setup.c | 12 +++ plat/st/stm32mp1/include/stm32mp1_dbgmcu.h | 17 ++++ plat/st/stm32mp1/platform.mk | 2 + plat/st/stm32mp1/sp_min/sp_min_setup.c | 5 + plat/st/stm32mp1/stm32mp1_dbgmcu.c | 66 +++++++++++++ plat/st/stm32mp1/stm32mp1_def.h | 26 ++++- plat/st/stm32mp1/stm32mp1_private.c | 76 +++++++++++++++ 10 files changed, 382 insertions(+), 2 deletions(-) create mode 100644 drivers/st/iwdg/stm32_iwdg.c create mode 100644 include/drivers/st/stm32_iwdg.h create mode 100644 plat/st/stm32mp1/include/stm32mp1_dbgmcu.h create mode 100644 plat/st/stm32mp1/stm32mp1_dbgmcu.c diff --git a/drivers/st/iwdg/stm32_iwdg.c b/drivers/st/iwdg/stm32_iwdg.c new file mode 100644 index 000000000..ea6fbb2b9 --- /dev/null +++ b/drivers/st/iwdg/stm32_iwdg.c @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* IWDG registers offsets */ +#define IWDG_KR_OFFSET 0x00U + +/* Registers values */ +#define IWDG_KR_RELOAD_KEY 0xAAAA + +struct stm32_iwdg_instance { + uintptr_t base; + unsigned long clock; + uint8_t flags; + int num_irq; +}; + +static struct stm32_iwdg_instance stm32_iwdg[IWDG_MAX_INSTANCE]; + +static int stm32_iwdg_get_dt_node(struct dt_node_info *info, int offset) +{ + int node; + + node = dt_get_node(info, offset, DT_IWDG_COMPAT); + if (node < 0) { + if (offset == -1) { + VERBOSE("%s: No IDWG found\n", __func__); + } + return -FDT_ERR_NOTFOUND; + } + + return node; +} + +void stm32_iwdg_refresh(void) +{ + uint8_t i; + + for (i = 0U; i < IWDG_MAX_INSTANCE; i++) { + struct stm32_iwdg_instance *iwdg = &stm32_iwdg[i]; + + /* 0x00000000 is not a valid address for IWDG peripherals */ + if (iwdg->base != 0U) { + stm32mp_clk_enable(iwdg->clock); + + mmio_write_32(iwdg->base + IWDG_KR_OFFSET, + IWDG_KR_RELOAD_KEY); + + stm32mp_clk_disable(iwdg->clock); + } + } +} + +int stm32_iwdg_init(void) +{ + int node = -1; + struct dt_node_info dt_info; + void *fdt; + uint32_t __unused count = 0; + + if (fdt_get_address(&fdt) == 0) { + panic(); + } + + for (node = stm32_iwdg_get_dt_node(&dt_info, node); + node != -FDT_ERR_NOTFOUND; + node = stm32_iwdg_get_dt_node(&dt_info, node)) { + struct stm32_iwdg_instance *iwdg; + uint32_t hw_init; + uint32_t idx; + + count++; + + idx = stm32_iwdg_get_instance(dt_info.base); + iwdg = &stm32_iwdg[idx]; + iwdg->base = dt_info.base; + iwdg->clock = (unsigned long)dt_info.clock; + + /* DT can specify low power cases */ + if (fdt_getprop(fdt, node, "stm32,enable-on-stop", NULL) == + NULL) { + iwdg->flags |= IWDG_DISABLE_ON_STOP; + } + + if (fdt_getprop(fdt, node, "stm32,enable-on-standby", NULL) == + NULL) { + iwdg->flags |= IWDG_DISABLE_ON_STANDBY; + } + + /* Explicit list of supported bit flags */ + hw_init = stm32_iwdg_get_otp_config(idx); + + if ((hw_init & IWDG_HW_ENABLED) != 0) { + if (dt_info.status == DT_DISABLED) { + ERROR("OTP enabled but iwdg%u DT-disabled\n", + idx + 1U); + panic(); + } + iwdg->flags |= IWDG_HW_ENABLED; + } + + if (dt_info.status == DT_DISABLED) { + zeromem((void *)iwdg, + sizeof(struct stm32_iwdg_instance)); + continue; + } + + if ((hw_init & IWDG_DISABLE_ON_STOP) != 0) { + iwdg->flags |= IWDG_DISABLE_ON_STOP; + } + + if ((hw_init & IWDG_DISABLE_ON_STANDBY) != 0) { + iwdg->flags |= IWDG_DISABLE_ON_STANDBY; + } + + VERBOSE("IWDG%u found, %ssecure\n", idx + 1U, + ((dt_info.status & DT_NON_SECURE) != 0) ? + "non-" : ""); + +#if defined(IMAGE_BL2) + if (stm32_iwdg_shadow_update(idx, iwdg->flags) != BSEC_OK) { + return -1; + } +#endif + } + + VERBOSE("%u IWDG instance%s found\n", count, (count > 1U) ? "s" : ""); + + return 0; +} diff --git a/include/drivers/st/stm32_iwdg.h b/include/drivers/st/stm32_iwdg.h new file mode 100644 index 000000000..bad25244a --- /dev/null +++ b/include/drivers/st/stm32_iwdg.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_IWDG_H +#define STM32_IWDG_H + +#include + +#define IWDG_HW_ENABLED BIT(0) +#define IWDG_DISABLE_ON_STOP BIT(1) +#define IWDG_DISABLE_ON_STANDBY BIT(2) + +int stm32_iwdg_init(void); +void stm32_iwdg_refresh(void); + +#endif /* STM32_IWDG_H */ diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index 4bbc4dba5..f8b5e7bad 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -28,6 +28,17 @@ uintptr_t stm32mp_pwr_base(void); /* Return the base address of the RCC peripheral */ uintptr_t stm32mp_rcc_base(void); +/* Get IWDG platform instance ID from peripheral IO memory base address */ +uint32_t stm32_iwdg_get_instance(uintptr_t base); + +/* Return bitflag mask for expected IWDG configuration from OTP content */ +uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst); + +#if defined(IMAGE_BL2) +/* Update OTP shadow registers with IWDG configuration from device tree */ +uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags); +#endif + /* * Platform util functions for the GPIO driver * @bank: Target GPIO bank ID as per DT bindings diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index 27d298e8d..7de264ba0 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,7 @@ #include #include +#include static struct console_stm32 console; @@ -276,6 +278,16 @@ void bl2_el3_plat_arch_setup(void) } skip_console_init: + if (stm32_iwdg_init() < 0) { + panic(); + } + + stm32_iwdg_refresh(); + + result = stm32mp1_dbgmcu_freeze_iwdg2(); + if (result != 0) { + INFO("IWDG2 freeze error : %i\n", result); + } if (stm32_save_boot_interface(boot_context->boot_interface_selected, boot_context->boot_interface_instance) != diff --git a/plat/st/stm32mp1/include/stm32mp1_dbgmcu.h b/plat/st/stm32mp1/include/stm32mp1_dbgmcu.h new file mode 100644 index 000000000..a878308ba --- /dev/null +++ b/plat/st/stm32mp1/include/stm32mp1_dbgmcu.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_DBGMCU_H +#define STM32MP1_DBGMCU_H + +/* + * Freeze watchdog when a debugger is attached, if the security configuration + * allows it. + * Return 0 on success, a negative error value otherwise. + */ +int stm32mp1_dbgmcu_freeze_iwdg2(void); + +#endif /* STM32MP1_DBGMCU_H */ diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index 0ea7bbb8e..83d977039 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -57,11 +57,13 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \ drivers/st/ddr/stm32mp1_ddr_helpers.c \ drivers/st/gpio/stm32_gpio.c \ drivers/st/i2c/stm32_i2c.c \ + drivers/st/iwdg/stm32_iwdg.c \ drivers/st/pmic/stm32mp_pmic.c \ drivers/st/pmic/stpmic1.c \ drivers/st/reset/stm32mp1_reset.c \ plat/st/common/stm32mp_dt.c \ plat/st/stm32mp1/stm32mp1_context.c \ + plat/st/stm32mp1/stm32mp1_dbgmcu.c \ plat/st/stm32mp1/stm32mp1_helper.S \ plat/st/stm32mp1/stm32mp1_security.c \ plat/st/stm32mp1/stm32mp1_syscfg.c diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c index 329ff688a..5ad219085 100644 --- a/plat/st/stm32mp1/sp_min/sp_min_setup.c +++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -157,6 +158,10 @@ void sp_min_platform_setup(void) for (uint32_t pin = 0U; pin < STM32MP_GPIOZ_PIN_MAX_COUNT; pin++) { set_gpio_secure_cfg(GPIO_BANK_Z, pin, false); } + + if (stm32_iwdg_init() < 0) { + panic(); + } } void sp_min_plat_arch_setup(void) diff --git a/plat/st/stm32mp1/stm32mp1_dbgmcu.c b/plat/st/stm32mp1/stm32mp1_dbgmcu.c new file mode 100644 index 000000000..a614267db --- /dev/null +++ b/plat/st/stm32mp1/stm32mp1_dbgmcu.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include + +#include + +#define DBGMCU_APB4FZ1 U(0x2C) +#define DBGMCU_APB4FZ1_IWDG2 BIT(2) + +static uintptr_t get_rcc_base(void) +{ + /* This is called before stm32mp_rcc_base() is available */ + return RCC_BASE; +} + +static int stm32mp1_dbgmcu_init(void) +{ + uint32_t dbg_conf; + uintptr_t rcc_base = get_rcc_base(); + + dbg_conf = bsec_read_debug_conf(); + + if ((dbg_conf & BSEC_DBGSWGEN) == 0U) { + uint32_t result = bsec_write_debug_conf(dbg_conf | + BSEC_DBGSWGEN); + + if (result != BSEC_OK) { + ERROR("Error enabling DBGSWGEN\n"); + return -1; + } + } + + mmio_setbits_32(rcc_base + RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + + return 0; +} + +int stm32mp1_dbgmcu_freeze_iwdg2(void) +{ + uint32_t dbg_conf; + + if (stm32mp1_dbgmcu_init() != 0) { + return -EPERM; + } + + dbg_conf = bsec_read_debug_conf(); + + if ((dbg_conf & (BSEC_SPIDEN | BSEC_SPINDEN)) != 0U) { + mmio_setbits_32(DBGMCU_BASE + DBGMCU_APB4FZ1, + DBGMCU_APB4FZ1_IWDG2); + } + + return 0; +} diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 37941aa74..34e6e3cc8 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -15,6 +15,7 @@ #include #ifndef __ASSEMBLER__ +#include #include #include @@ -87,9 +88,9 @@ enum ddr_type { #endif #else #if STACK_PROTECTOR_ENABLED -#define STM32MP_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */ +#define STM32MP_BL2_SIZE U(0x00018000) /* 96 Ko for BL2 */ #else -#define STM32MP_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */ +#define STM32MP_BL2_SIZE U(0x00016000) /* 88 Ko for BL2 */ #endif #endif @@ -245,6 +246,11 @@ enum ddr_type { /* DATA0 */ #define DATA0_OTP_SECURED BIT(6) +/* IWDG OTP */ +#define HW2_OTP_IWDG_HW_POS U(3) +#define HW2_OTP_IWDG_FZ_STOP_POS U(5) +#define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) + /* HW2 OTP */ #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) @@ -271,14 +277,30 @@ static inline uint32_t tamp_bkpr(uint32_t idx) ******************************************************************************/ #define DDRPHYC_BASE U(0x5A004000) +/******************************************************************************* + * STM32MP1 IWDG + ******************************************************************************/ +#define IWDG_MAX_INSTANCE U(2) +#define IWDG1_INST U(0) +#define IWDG2_INST U(1) + +#define IWDG1_BASE U(0x5C003000) +#define IWDG2_BASE U(0x5A002000) + /******************************************************************************* * STM32MP1 I2C4 ******************************************************************************/ #define I2C4_BASE U(0x5C002000) +/******************************************************************************* + * STM32MP1 DBGMCU + ******************************************************************************/ +#define DBGMCU_BASE U(0x50081000) + /******************************************************************************* * Device Tree defines ******************************************************************************/ +#define DT_IWDG_COMPAT "st,stm32mp1-iwdg" #define DT_PWR_COMPAT "st,stm32mp1-pwr" #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index 340c7fba3..886a8f310 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -8,6 +8,7 @@ #include +#include #include #define MAP_SRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ @@ -66,3 +67,78 @@ unsigned long stm32_get_gpio_bank_clock(unsigned int bank) return GPIOA + (bank - GPIO_BANK_A); } + +uint32_t stm32_iwdg_get_instance(uintptr_t base) +{ + switch (base) { + case IWDG1_BASE: + return IWDG1_INST; + case IWDG2_BASE: + return IWDG2_INST; + default: + panic(); + } +} + +uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) +{ + uint32_t iwdg_cfg = 0U; + uint32_t otp_value; + +#if defined(IMAGE_BL2) + if (bsec_shadow_register(HW2_OTP) != BSEC_OK) { + panic(); + } +#endif + + if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) { + panic(); + } + + if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { + iwdg_cfg |= IWDG_HW_ENABLED; + } + + if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { + iwdg_cfg |= IWDG_DISABLE_ON_STOP; + } + + if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { + iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; + } + + return iwdg_cfg; +} + +#if defined(IMAGE_BL2) +uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) +{ + uint32_t otp; + uint32_t result; + + if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) { + panic(); + } + + if ((flags & IWDG_DISABLE_ON_STOP) != 0U) { + otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); + } + + if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) { + otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); + } + + result = bsec_write_otp(otp, HW2_OTP); + if (result != BSEC_OK) { + return result; + } + + /* Sticky lock OTP_IWDG (read and write) */ + if (!bsec_write_sr_lock(HW2_OTP, 1U) || + !bsec_write_sw_lock(HW2_OTP, 1U)) { + return BSEC_LOCK_FAIL; + } + + return BSEC_OK; +} +#endif -- cgit v1.2.3 From dec286dd7d7b1aae486a05069a80b8791ab0ba55 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 4 Jun 2019 18:02:37 +0200 Subject: stm32mp1: print information about SoC This information is located in DBGMCU registers. Change-Id: I480aa046fed9992e3d9665b1f0520bc4b6cfdf30 Signed-off-by: Yann Gautier --- plat/st/common/include/stm32mp_common.h | 3 + plat/st/stm32mp1/bl2_plat_setup.c | 2 + plat/st/stm32mp1/include/stm32mp1_dbgmcu.h | 6 ++ plat/st/stm32mp1/stm32mp1_dbgmcu.c | 30 ++++++++ plat/st/stm32mp1/stm32mp1_def.h | 31 ++++++++ plat/st/stm32mp1/stm32mp1_private.c | 120 +++++++++++++++++++++++++++++ 6 files changed, 192 insertions(+) diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index f8b5e7bad..33638b5a5 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -56,6 +56,9 @@ uintptr_t stm32_get_gpio_bank_base(unsigned int bank); unsigned long stm32_get_gpio_bank_clock(unsigned int bank); uint32_t stm32_get_gpio_bank_offset(unsigned int bank); +/* Print CPU information */ +void stm32mp_print_cpuinfo(void); + /* * Util for clock gating and to get clock rate for stm32 and platform drivers * @id: Target clock ID, ID used in clock DT bindings diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index 7de264ba0..1926be313 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -272,6 +272,8 @@ void bl2_el3_plat_arch_setup(void) panic(); } + stm32mp_print_cpuinfo(); + board_model = dt_get_board_model(); if (board_model != NULL) { NOTICE("Model: %s\n", board_model); diff --git a/plat/st/stm32mp1/include/stm32mp1_dbgmcu.h b/plat/st/stm32mp1/include/stm32mp1_dbgmcu.h index a878308ba..498a4f210 100644 --- a/plat/st/stm32mp1/include/stm32mp1_dbgmcu.h +++ b/plat/st/stm32mp1/include/stm32mp1_dbgmcu.h @@ -7,6 +7,12 @@ #ifndef STM32MP1_DBGMCU_H #define STM32MP1_DBGMCU_H +#include + +/* Get chip version and ID from DBGMCU registers */ +int stm32mp1_dbgmcu_get_chip_version(uint32_t *chip_version); +int stm32mp1_dbgmcu_get_chip_dev_id(uint32_t *chip_dev_id); + /* * Freeze watchdog when a debugger is attached, if the security configuration * allows it. diff --git a/plat/st/stm32mp1/stm32mp1_dbgmcu.c b/plat/st/stm32mp1/stm32mp1_dbgmcu.c index a614267db..d0264968c 100644 --- a/plat/st/stm32mp1/stm32mp1_dbgmcu.c +++ b/plat/st/stm32mp1/stm32mp1_dbgmcu.c @@ -16,7 +16,13 @@ #include +#define DBGMCU_IDC U(0x00) #define DBGMCU_APB4FZ1 U(0x2C) + +#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) +#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) +#define DBGMCU_IDC_REV_ID_SHIFT 16 + #define DBGMCU_APB4FZ1_IWDG2 BIT(2) static uintptr_t get_rcc_base(void) @@ -47,6 +53,30 @@ static int stm32mp1_dbgmcu_init(void) return 0; } +int stm32mp1_dbgmcu_get_chip_version(uint32_t *chip_version) +{ + if (stm32mp1_dbgmcu_init() != 0) { + return -EPERM; + } + + *chip_version = (mmio_read_32(DBGMCU_BASE + DBGMCU_IDC) & + DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; + + return 0; +} + +int stm32mp1_dbgmcu_get_chip_dev_id(uint32_t *chip_dev_id) +{ + if (stm32mp1_dbgmcu_init() != 0) { + return -EPERM; + } + + *chip_dev_id = mmio_read_32(DBGMCU_BASE + DBGMCU_IDC) & + DBGMCU_IDC_DEV_ID_MASK; + + return 0; +} + int stm32mp1_dbgmcu_freeze_iwdg2(void) { uint32_t dbg_conf; diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 34e6e3cc8..6ee588432 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -22,9 +22,30 @@ #include #include #include +#include #include #endif +/******************************************************************************* + * CHIP ID + ******************************************************************************/ +#define STM32MP157C_PART_NB U(0x05000000) +#define STM32MP157A_PART_NB U(0x05000001) +#define STM32MP153C_PART_NB U(0x05000024) +#define STM32MP153A_PART_NB U(0x05000025) +#define STM32MP151C_PART_NB U(0x0500002E) +#define STM32MP151A_PART_NB U(0x0500002F) + +#define STM32MP1_REV_B U(0x2000) + +/******************************************************************************* + * PACKAGE ID + ******************************************************************************/ +#define PKG_AA_LFBGA448 U(4) +#define PKG_AB_LFBGA354 U(3) +#define PKG_AC_TFBGA361 U(2) +#define PKG_AD_TFBGA257 U(1) + /******************************************************************************* * STM32MP1 memory map related constants ******************************************************************************/ @@ -240,12 +261,22 @@ enum ddr_type { /* OTP offsets */ #define DATA0_OTP U(0) +#define PART_NUMBER_OTP U(1) +#define PACKAGE_OTP U(16) #define HW2_OTP U(18) /* OTP mask */ /* DATA0 */ #define DATA0_OTP_SECURED BIT(6) +/* PART NUMBER */ +#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) +#define PART_NUMBER_OTP_PART_SHIFT 0 + +/* PACKAGE */ +#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) +#define PACKAGE_OTP_PKG_SHIFT 27 + /* IWDG OTP */ #define HW2_OTP_IWDG_HW_POS U(3) #define HW2_OTP_IWDG_FZ_STOP_POS U(5) diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index 886a8f310..08fb815ce 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -68,6 +68,126 @@ unsigned long stm32_get_gpio_bank_clock(unsigned int bank) return GPIOA + (bank - GPIO_BANK_A); } +static int get_part_number(uint32_t *part_nb) +{ + uint32_t part_number; + uint32_t dev_id; + + if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { + return -1; + } + + if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) { + ERROR("BSEC: PART_NUMBER_OTP Error\n"); + return -1; + } + + part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> + PART_NUMBER_OTP_PART_SHIFT; + + *part_nb = part_number | (dev_id << 16); + + return 0; +} + +static int get_cpu_package(uint32_t *cpu_package) +{ + uint32_t package; + + if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { + ERROR("BSEC: PACKAGE_OTP Error\n"); + return -1; + } + + *cpu_package = (package & PACKAGE_OTP_PKG_MASK) >> + PACKAGE_OTP_PKG_SHIFT; + + return 0; +} + +void stm32mp_print_cpuinfo(void) +{ + const char *cpu_s, *cpu_r, *pkg; + uint32_t part_number; + uint32_t cpu_package; + uint32_t chip_dev_id; + int ret; + + /* MPUs Part Numbers */ + ret = get_part_number(&part_number); + if (ret < 0) { + WARN("Cannot get part number\n"); + return; + } + + switch (part_number) { + case STM32MP157C_PART_NB: + cpu_s = "157C"; + break; + case STM32MP157A_PART_NB: + cpu_s = "157A"; + break; + case STM32MP153C_PART_NB: + cpu_s = "153C"; + break; + case STM32MP153A_PART_NB: + cpu_s = "153A"; + break; + case STM32MP151C_PART_NB: + cpu_s = "151C"; + break; + case STM32MP151A_PART_NB: + cpu_s = "151A"; + break; + default: + cpu_s = "????"; + break; + } + + /* Package */ + ret = get_cpu_package(&cpu_package); + if (ret < 0) { + WARN("Cannot get CPU package\n"); + return; + } + + switch (cpu_package) { + case PKG_AA_LFBGA448: + pkg = "AA"; + break; + case PKG_AB_LFBGA354: + pkg = "AB"; + break; + case PKG_AC_TFBGA361: + pkg = "AC"; + break; + case PKG_AD_TFBGA257: + pkg = "AD"; + break; + default: + pkg = "??"; + break; + } + + /* REVISION */ + ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id); + if (ret < 0) { + WARN("Cannot get CPU version\n"); + return; + } + + switch (chip_dev_id) { + case STM32MP1_REV_B: + cpu_r = "B"; + break; + default: + cpu_r = "?"; + break; + } + + NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r); +} + uint32_t stm32_iwdg_get_instance(uintptr_t base) { switch (base) { -- cgit v1.2.3 From 10e7a9e904dfddd62ee839098e2d0737a3afad15 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Mon, 13 May 2019 18:34:48 +0200 Subject: stm32mp1: print information about board On STMicroelectronics boards, the board information is stored in OTP. This OTP is described in device tree, in BSEC board_id node. Change-Id: Ieccbdcb048343680faac8dc577b75c67ac106f5b Signed-off-by: Yann Gautier Signed-off-by: Lionel Debieve --- plat/st/common/include/stm32mp_common.h | 3 ++ plat/st/stm32mp1/bl2_plat_setup.c | 2 + plat/st/stm32mp1/stm32mp1_def.h | 1 + plat/st/stm32mp1/stm32mp1_private.c | 66 +++++++++++++++++++++++++++++++++ 4 files changed, 72 insertions(+) diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index 33638b5a5..f0573903d 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -59,6 +59,9 @@ uint32_t stm32_get_gpio_bank_offset(unsigned int bank); /* Print CPU information */ void stm32mp_print_cpuinfo(void); +/* Print board information */ +void stm32mp_print_boardinfo(void); + /* * Util for clock gating and to get clock rate for stm32 and platform drivers * @id: Target clock ID, ID used in clock DT bindings diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index 1926be313..75ae372ae 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -279,6 +279,8 @@ void bl2_el3_plat_arch_setup(void) NOTICE("Model: %s\n", board_model); } + stm32mp_print_boardinfo(); + skip_console_init: if (stm32_iwdg_init() < 0) { panic(); diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 6ee588432..77a95e68a 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -331,6 +331,7 @@ static inline uint32_t tamp_bkpr(uint32_t idx) /******************************************************************************* * Device Tree defines ******************************************************************************/ +#define DT_BSEC_COMPAT "st,stm32mp15-bsec" #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" #define DT_PWR_COMPAT "st,stm32mp1-pwr" #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index 08fb815ce..c334cd1e0 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -6,11 +6,30 @@ #include +#include + #include #include #include +/* Internal layout of the 32bit OTP word board_id */ +#define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) +#define BOARD_ID_BOARD_NB_SHIFT 16 +#define BOARD_ID_VARIANT_MASK GENMASK(15, 12) +#define BOARD_ID_VARIANT_SHIFT 12 +#define BOARD_ID_REVISION_MASK GENMASK(11, 8) +#define BOARD_ID_REVISION_SHIFT 8 +#define BOARD_ID_BOM_MASK GENMASK(3, 0) + +#define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ + BOARD_ID_BOARD_NB_SHIFT) +#define BOARD_ID2VAR(_id) (((_id) & BOARD_ID_VARIANT_MASK) >> \ + BOARD_ID_VARIANT_SHIFT) +#define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ + BOARD_ID_REVISION_SHIFT) +#define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) + #define MAP_SRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ STM32MP_SYSRAM_SIZE, \ MT_MEMORY | \ @@ -188,6 +207,53 @@ void stm32mp_print_cpuinfo(void) NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r); } +void stm32mp_print_boardinfo(void) +{ + uint32_t board_id; + uint32_t board_otp; + int bsec_node, bsec_board_id_node; + void *fdt; + const fdt32_t *cuint; + + if (fdt_get_address(&fdt) == 0) { + panic(); + } + + bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT); + if (bsec_node < 0) { + return; + } + + bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id"); + if (bsec_board_id_node <= 0) { + return; + } + + cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL); + if (cuint == NULL) { + panic(); + } + + board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t); + + if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) { + ERROR("BSEC: PART_NUMBER_OTP Error\n"); + return; + } + + if (board_id != 0U) { + char rev[2]; + + rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; + rev[1] = '\0'; + NOTICE("Board: MB%04x Var%d Rev.%s-%02d\n", + BOARD_ID2NB(board_id), + BOARD_ID2VAR(board_id), + rev, + BOARD_ID2BOM(board_id)); + } +} + uint32_t stm32_iwdg_get_instance(uintptr_t base) { switch (base) { -- cgit v1.2.3 From b2182cde098307a59ed389cff251bd4932654bf8 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 4 Jun 2019 18:23:10 +0200 Subject: stm32mp1: check if the SoC is single core Among the variants of STM32MP, the STM32MP151 is a single Cortex-A7 chip. A function is added to check the part number of the SoC. If it corresponds to STM32MP151A or STM32MP151C, then the chip has a single Cortex-A7. Change-Id: Icac2015c5d03ce0bcb8e99bbaf1ec8ada34be49c Signed-off-by: Yann Gautier Signed-off-by: Nicolas Le Bayon Signed-off-by: Lionel Debieve --- plat/st/common/include/stm32mp_common.h | 2 ++ plat/st/stm32mp1/stm32mp1_private.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index f0573903d..0d0a9c669 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -16,6 +16,8 @@ void stm32mp_save_boot_ctx_address(uintptr_t address); uintptr_t stm32mp_get_boot_ctx_address(void); +bool stm32mp_is_single_core(void); + /* Return the base address of the DDR controller */ uintptr_t stm32mp_ddrctrl_base(void); diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index c334cd1e0..38ebcef64 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -254,6 +254,30 @@ void stm32mp_print_boardinfo(void) } } +/* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ +bool stm32mp_is_single_core(void) +{ + uint32_t part_number; + bool ret = false; + + if (get_part_number(&part_number) < 0) { + ERROR("Invalid part number, assume single core chip"); + return true; + } + + switch (part_number) { + case STM32MP151A_PART_NB: + case STM32MP151C_PART_NB: + ret = true; + break; + + default: + break; + } + + return ret; +} + uint32_t stm32_iwdg_get_instance(uintptr_t base) { switch (base) { -- cgit v1.2.3 From 6cb45f8984af596fc5460204e9be1d85de79cf5e Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Mon, 20 May 2019 14:39:26 +0200 Subject: clk: stm32mp: enable RTCAPB clock for dual-core chips In order to correctly manage the bring-up of non boot CPUs, the RTCAPB clock needs to be enabled. It controls the access to backup registers, where the CPU entrypoint will be stored. Change-Id: Ifeeceb4faf64bc9e0778030444f437cc0bb27272 Signed-off-by: Yann Gautier Signed-off-by: Etienne Carriere Signed-off-by: Nicolas Le Bayon --- drivers/st/clk/stm32mp1_clk.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index 76e6e6fdc..f3b9f0cc3 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -1912,9 +1912,18 @@ static void stm32mp1_osc_init(void) } } +static void sync_earlyboot_clocks_state(void) +{ + if (!stm32mp_is_single_core()) { + stm32mp1_clk_enable_secure(RTCAPB); + } +} + int stm32mp1_clk_probe(void) { stm32mp1_osc_init(); + sync_earlyboot_clocks_state(); + return 0; } -- cgit v1.2.3 From e463d3f43e0115fbafd7a17f7ba550fc8e9a2ae0 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 22 May 2019 19:13:51 +0200 Subject: stm32mp1: use a common function to check spinlock is available To use spinlocks, MMU should be enabled, as well as data cache. A common function is created (moved from clock file). It is then used whenever a spinlock has to be taken, in BSEC and clock drivers. Change-Id: I94baed0114a2061ad71bd5287a91bf7f1c6821f6 Signed-off-by: Yann Gautier --- drivers/st/bsec/bsec.c | 10 ++-------- drivers/st/clk/stm32mp1_clk.c | 20 +++++--------------- plat/st/common/include/stm32mp_common.h | 3 +++ plat/st/common/stm32mp_common.c | 8 ++++++++ 4 files changed, 18 insertions(+), 23 deletions(-) diff --git a/drivers/st/bsec/bsec.c b/drivers/st/bsec/bsec.c index aaecf1f83..b3c15ee8b 100644 --- a/drivers/st/bsec/bsec.c +++ b/drivers/st/bsec/bsec.c @@ -32,20 +32,14 @@ static uintptr_t bsec_base; static void bsec_lock(void) { - const uint32_t mask = SCTLR_M_BIT | SCTLR_C_BIT; - - /* Lock is currently required only when MMU and cache are enabled */ - if ((read_sctlr() & mask) == mask) { + if (stm32mp_lock_available()) { spin_lock(&bsec_spinlock); } } static void bsec_unlock(void) { - const uint32_t mask = SCTLR_M_BIT | SCTLR_C_BIT; - - /* Unlock is required only when MMU and cache are enabled */ - if ((read_sctlr() & mask) == mask) { + if (stm32mp_lock_available()) { spin_unlock(&bsec_spinlock); } } diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index f3b9f0cc3..0cc87cc71 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -541,29 +541,19 @@ static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) return &stm32mp1_clk_pll[idx]; } -static int stm32mp1_lock_available(void) -{ - /* The spinlocks are used only when MMU is enabled */ - return (read_sctlr() & SCTLR_M_BIT) && (read_sctlr() & SCTLR_C_BIT); -} - static void stm32mp1_clk_lock(struct spinlock *lock) { - if (stm32mp1_lock_available() == 0U) { - return; + if (stm32mp_lock_available()) { + /* Assume interrupts are masked */ + spin_lock(lock); } - - /* Assume interrupts are masked */ - spin_lock(lock); } static void stm32mp1_clk_unlock(struct spinlock *lock) { - if (stm32mp1_lock_available() == 0U) { - return; + if (stm32mp_lock_available()) { + spin_unlock(lock); } - - spin_unlock(lock); } bool stm32mp1_rcc_is_secure(void) diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index 0d0a9c669..3dd6c567b 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -30,6 +30,9 @@ uintptr_t stm32mp_pwr_base(void); /* Return the base address of the RCC peripheral */ uintptr_t stm32mp_rcc_base(void); +/* Check MMU status to allow spinlock use */ +bool stm32mp_lock_available(void); + /* Get IWDG platform instance ID from peripheral IO memory base address */ uint32_t stm32_iwdg_get_instance(uintptr_t base); diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c index f95c7885d..5428a74ef 100644 --- a/plat/st/common/stm32mp_common.c +++ b/plat/st/common/stm32mp_common.c @@ -87,6 +87,14 @@ uintptr_t stm32mp_rcc_base(void) return rcc_base; } +bool stm32mp_lock_available(void) +{ + const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; + + /* The spinlocks are used only when MMU and data cache are enabled */ + return (read_sctlr() & c_m_bits) == c_m_bits; +} + uintptr_t stm32_get_gpio_bank_base(unsigned int bank) { if (bank == GPIO_BANK_Z) { -- cgit v1.2.3 From 4b549b215360bfed4d7cd14247d9c99a995ca217 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 16 Apr 2019 16:20:58 +0200 Subject: stm32mp1: add support for LpDDR3 This change enables LpDDR3 initialization with PMIC. Change-Id: I2409a808335dfacd69a8517cb8510cee98bb8161 Signed-off-by: Yann Gautier --- drivers/st/ddr/stm32mp1_ddr.c | 2 ++ drivers/st/pmic/stm32mp_pmic.c | 1 + plat/st/stm32mp1/stm32mp1_def.h | 1 + 3 files changed, 4 insertions(+) diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c index caf8eefa8..7d89d027e 100644 --- a/drivers/st/ddr/stm32mp1_ddr.c +++ b/drivers/st/ddr/stm32mp1_ddr.c @@ -717,6 +717,8 @@ void stm32mp1_ddr_init(struct ddr_info *priv, ret = board_ddr_power_init(STM32MP_DDR3); } else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) != 0U) { ret = board_ddr_power_init(STM32MP_LPDDR2); + } else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) != 0U) { + ret = board_ddr_power_init(STM32MP_LPDDR3); } else { ERROR("DDR type not supported\n"); } diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c index 6fe51f443..9e9dddc4d 100644 --- a/drivers/st/pmic/stm32mp_pmic.c +++ b/drivers/st/pmic/stm32mp_pmic.c @@ -299,6 +299,7 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) break; case STM32MP_LPDDR2: + case STM32MP_LPDDR3: /* * Set LDO3 to 1.8V * Set LDO3 to bypass mode if BUCK3 = 1.8V diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 77a95e68a..0eba8a645 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -66,6 +66,7 @@ enum ddr_type { STM32MP_DDR3, STM32MP_LPDDR2, + STM32MP_LPDDR3 }; #endif -- cgit v1.2.3 From 02f5d82052939c7bc004c0ac13544f87eac178a3 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Thu, 11 Jul 2019 10:45:09 +0200 Subject: stm32mp1: sp_min: initialize MMU and cache earlier This change enhances performance and security in BL32 stage. Change-Id: I64df5995fc6b04f6cf42d6a00a6d3d0f602b5407 Signed-off-by: Yann Gautier --- plat/st/stm32mp1/sp_min/sp_min_setup.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c index 5ad219085..e54249f74 100644 --- a/plat/st/stm32mp1/sp_min/sp_min_setup.c +++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c @@ -89,6 +89,12 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, /* Imprecise aborts can be masked in NonSecure */ write_scr(read_scr() | SCR_AW_BIT); + mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, + BL_CODE_END - BL_CODE_BASE, + MT_CODE | MT_SECURE); + + configure_mmu(); + assert(params_from_bl2 != NULL); assert(params_from_bl2->h.type == PARAM_BL_PARAMS); assert(params_from_bl2->h.version >= VERSION_2); @@ -136,12 +142,6 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, ******************************************************************************/ void sp_min_platform_setup(void) { - mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, - BL_CODE_END - BL_CODE_BASE, - MT_CODE | MT_SECURE); - - configure_mmu(); - /* Initialize tzc400 after DDR initialization */ stm32mp1_security_setup(); -- cgit v1.2.3 From 083bca2210e62cb8a3083158a6c500a30ecefffe Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 24 Apr 2019 16:14:22 +0200 Subject: stm32mp1: keep console during runtime The runtime console is only kept in DEBUG configuration. Change-Id: I0447dfcacb9a63a12bcdab7c55584d70c3220e5b Signed-off-by: Yann Gautier --- plat/st/stm32mp1/sp_min/sp_min_setup.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c index e54249f74..417115b65 100644 --- a/plat/st/stm32mp1/sp_min/sp_min_setup.c +++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c @@ -134,6 +134,11 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 0) { panic(); } + +#ifdef DEBUG + console_set_scope(&console.console, + CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); +#endif } } -- cgit v1.2.3 From 1e91952942f5063d57e21bd1e9a2e968003b935f Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Fri, 19 Apr 2019 10:48:36 +0200 Subject: stm32mp1: move check_header() to common code This function can be used on several stm32mp devices, it is then moved in plat/st/common/stm32mp_common.c. Change-Id: I862debe39604410f71a9ddc28713026362e9ecda Signed-off-by: Yann Gautier --- drivers/st/io/io_stm32image.c | 36 +-------------------------------- plat/st/common/include/stm32mp_common.h | 10 +++++++++ plat/st/common/stm32mp_common.c | 35 ++++++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+), 35 deletions(-) diff --git a/drivers/st/io/io_stm32image.c b/drivers/st/io/io_stm32image.c index dc2977d5a..971dcce53 100644 --- a/drivers/st/io/io_stm32image.c +++ b/drivers/st/io/io_stm32image.c @@ -242,40 +242,6 @@ static int stm32image_partition_size(io_entity_t *entity, size_t *length) return 0; } -static int check_header(boot_api_image_header_t *header, uintptr_t buffer) -{ - uint32_t i; - uint32_t img_checksum = 0; - - /* - * Check header/payload validity: - * - Header magic - * - Header version - * - Payload checksum - */ - if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) { - ERROR("Header magic\n"); - return -EINVAL; - } - - if (header->header_version != BOOT_API_HEADER_VERSION) { - ERROR("Header version\n"); - return -EINVAL; - } - - for (i = 0; i < header->image_length; i++) { - img_checksum += *(uint8_t *)(buffer + i); - } - - if (header->payload_checksum != img_checksum) { - ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum, - header->payload_checksum); - return -EINVAL; - } - - return 0; -} - /* Read data from a partition */ static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read) @@ -368,7 +334,7 @@ static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer, continue; } - result = check_header(header, buffer); + result = stm32mp_check_header(header, buffer); if (result != 0) { ERROR("Header check failed\n"); *length_read = 0; diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index 3dd6c567b..e20308ee2 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -10,6 +10,8 @@ #include +#include + #include /* Functions to save and get boot context address given by ROM code */ @@ -94,4 +96,12 @@ static inline bool timeout_elapsed(uint64_t expire) return read_cntpct_el0() > expire; } +/* + * Check that the STM32 header of a .stm32 binary image is valid + * @param header: pointer to the stm32 image header + * @param buffer: address of the binary image (payload) + * @return: 0 on success, negative value in case of error + */ +int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer); + #endif /* STM32MP_COMMON_H */ diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c index 5428a74ef..afa87f487 100644 --- a/plat/st/common/stm32mp_common.c +++ b/plat/st/common/stm32mp_common.c @@ -5,6 +5,7 @@ */ #include +#include #include @@ -116,3 +117,37 @@ uint32_t stm32_get_gpio_bank_offset(unsigned int bank) return bank * GPIO_BANK_OFFSET; } + +int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer) +{ + uint32_t i; + uint32_t img_checksum = 0U; + + /* + * Check header/payload validity: + * - Header magic + * - Header version + * - Payload checksum + */ + if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) { + ERROR("Header magic\n"); + return -EINVAL; + } + + if (header->header_version != BOOT_API_HEADER_VERSION) { + ERROR("Header version\n"); + return -EINVAL; + } + + for (i = 0U; i < header->image_length; i++) { + img_checksum += *(uint8_t *)(buffer + i); + } + + if (header->payload_checksum != img_checksum) { + ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum, + header->payload_checksum); + return -EINVAL; + } + + return 0; +} -- cgit v1.2.3 From 2c2c9f1eb1596793dd590cfc19d65488fd286dfc Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 28 May 2019 11:54:50 +0200 Subject: mmc: stm32_sdmmc2: manage max-frequency property from DT If the max-frequency property is provided in the device tree mmc node, it should be managed. The max allowed frequency will be the min between this property value and what the card can support. Change-Id: I885b676c3300d2670a0fe4c6ecab87758b5893ad Signed-off-by: Yann Gautier --- drivers/st/mmc/stm32_sdmmc2.c | 23 +++++++++++++++++++---- include/drivers/st/stm32_sdmmc2.h | 3 ++- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c index f453ce9a5..1be88502d 100644 --- a/drivers/st/mmc/stm32_sdmmc2.c +++ b/drivers/st/mmc/stm32_sdmmc2.c @@ -152,10 +152,14 @@ bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) static void stm32_sdmmc2_init(void) { uint32_t clock_div; + uint32_t freq = STM32MP_MMC_INIT_FREQ; uintptr_t base = sdmmc2_params.reg_base; - clock_div = div_round_up(sdmmc2_params.clk_rate, - STM32MP_MMC_INIT_FREQ * 2); + if (sdmmc2_params.max_freq != 0U) { + freq = MIN(sdmmc2_params.max_freq, freq); + } + + clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | sdmmc2_params.negedge | @@ -406,7 +410,7 @@ static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) { uintptr_t base = sdmmc2_params.reg_base; uint32_t bus_cfg = 0; - uint32_t clock_div, max_freq; + uint32_t clock_div, max_freq, freq; uint32_t clk_rate = sdmmc2_params.clk_rate; uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; @@ -438,7 +442,13 @@ static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) } } - clock_div = div_round_up(clk_rate, max_freq * 2); + if (sdmmc2_params.max_freq != 0U) { + freq = MIN(sdmmc2_params.max_freq, max_freq); + } else { + freq = max_freq; + } + + clock_div = div_round_up(clk_rate, freq * 2U); mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | @@ -692,6 +702,11 @@ static int stm32_sdmmc2_dt_get_config(void) } } + cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL); + if (cuint != NULL) { + sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); + } + return 0; } diff --git a/include/drivers/st/stm32_sdmmc2.h b/include/drivers/st/stm32_sdmmc2.h index aa9472c83..4853208c2 100644 --- a/include/drivers/st/stm32_sdmmc2.h +++ b/include/drivers/st/stm32_sdmmc2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,7 @@ struct stm32_sdmmc2_params { unsigned int dirpol; unsigned int clock_id; unsigned int reset_id; + unsigned int max_freq; bool use_dma; }; -- cgit v1.2.3 From d9d803e0be7af7785d8ea72e79b2926db581bb65 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 11 Jun 2019 20:03:07 +0200 Subject: mmc: stm32_sdmmc2: correctly manage block size DBLOCKSIZE should be filled such as the data size is 2^DBLOCKSIZE. Hence it is calculated with __builtin_ctz. Change-Id: Id6b5ff9b594afc4fc523a388011beed307e6abd1 Signed-off-by: Yann Gautier --- drivers/st/mmc/stm32_sdmmc2.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c index 1be88502d..24e6efe98 100644 --- a/drivers/st/mmc/stm32_sdmmc2.c +++ b/drivers/st/mmc/stm32_sdmmc2.c @@ -71,20 +71,14 @@ #define SDMMC_DCTRLR_DTEN BIT(0) #define SDMMC_DCTRLR_DTDIR BIT(1) #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) -#define SDMMC_DCTRLR_DBLOCKSIZE_0 BIT(4) -#define SDMMC_DCTRLR_DBLOCKSIZE_1 BIT(5) -#define SDMMC_DCTRLR_DBLOCKSIZE_3 BIT(7) #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) +#define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4 #define SDMMC_DCTRLR_FIFORST BIT(13) #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ SDMMC_DCTRLR_DTDIR | \ SDMMC_DCTRLR_DTMODE | \ SDMMC_DCTRLR_DBLOCKSIZE) -#define SDMMC_DBLOCKSIZE_8 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ - SDMMC_DCTRLR_DBLOCKSIZE_1) -#define SDMMC_DBLOCKSIZE_512 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ - SDMMC_DCTRLR_DBLOCKSIZE_3) /* SDMMC status register */ #define SDMMC_STAR_CCRCFAIL BIT(0) @@ -464,11 +458,14 @@ static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) int ret; uintptr_t base = sdmmc2_params.reg_base; uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; + uint32_t arg_size; - if (size == 8U) { - data_ctrl |= SDMMC_DBLOCKSIZE_8; + assert(size != 0U); + + if (size > MMC_BLOCK_SIZE) { + arg_size = MMC_BLOCK_SIZE; } else { - data_ctrl |= SDMMC_DBLOCKSIZE_512; + arg_size = size; } sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); @@ -487,12 +484,7 @@ static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) zeromem(&cmd, sizeof(struct mmc_cmd)); cmd.cmd_idx = MMC_CMD(16); - if (size > MMC_BLOCK_SIZE) { - cmd.cmd_arg = MMC_BLOCK_SIZE; - } else { - cmd.cmd_arg = size; - } - + cmd.cmd_arg = arg_size; cmd.resp_type = MMC_RESPONSE_R1; ret = stm32_sdmmc2_send_cmd(&cmd); @@ -514,6 +506,8 @@ static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) flush_dcache_range(buf, size); } + data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT; + mmio_clrsetbits_32(base + SDMMC_DCTRLR, SDMMC_DCTRLR_CLEAR_MASK, data_ctrl); -- cgit v1.2.3 From abfd5719741ff6a1b9f7f68c78154673b2fe98cc Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 23 Jul 2019 12:53:41 +0900 Subject: uniphier: set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driver This console driver sends '\r' before 'n', not after. It works, but the convention is "\r\n" (i.e. CRLF) Instead of fixing it in the driver, set CONSOLE_FLAG_TRANSLATE_CRLF to leave it to the framework. Change-Id: I2154e29313739a40dff70cfb5c0f8989136d4ad2 Signed-off-by: Masahiro Yamada --- plat/socionext/uniphier/uniphier_console.S | 10 ++-------- plat/socionext/uniphier/uniphier_console_setup.c | 3 ++- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/plat/socionext/uniphier/uniphier_console.S b/plat/socionext/uniphier/uniphier_console.S index 2c8dc8f84..1113c6e81 100644 --- a/plat/socionext/uniphier/uniphier_console.S +++ b/plat/socionext/uniphier/uniphier_console.S @@ -23,15 +23,9 @@ func uniphier_console_putc 0: ldr w2, [x1, #UNIPHIER_UART_LSR] tbz w2, #UNIPHIER_UART_LSR_THRE_BIT, 0b - mov w2, w0 + str w0, [x1, #UNIPHIER_UART_TX] -1: str w2, [x1, #UNIPHIER_UART_TX] - - cmp w2, #'\n' - b.ne 2f - mov w2, #'\r' /* Append '\r' to '\n' */ - b 1b -2: ret + ret endfunc uniphier_console_putc /* diff --git a/plat/socionext/uniphier/uniphier_console_setup.c b/plat/socionext/uniphier/uniphier_console_setup.c index 8185ec5a1..64ee79714 100644 --- a/plat/socionext/uniphier/uniphier_console_setup.c +++ b/plat/socionext/uniphier/uniphier_console_setup.c @@ -32,7 +32,8 @@ static struct uniphier_console uniphier_console = { #if DEBUG CONSOLE_FLAG_RUNTIME | #endif - CONSOLE_FLAG_CRASH, + CONSOLE_FLAG_CRASH | + CONSOLE_FLAG_TRANSLATE_CRLF, .putc = uniphier_console_putc, .getc = uniphier_console_getc, .flush = uniphier_console_flush, -- cgit v1.2.3 From 948a0c0d3c756a69dca56f76d02eed119956cc79 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 4 Sep 2019 14:09:07 +0900 Subject: mbedtls: use #include <...> instead of "..." The #include "mbedtls/check_config.h" directive first searches for the header in the relative path to mbedtls_config.h, i.e. include/drivers/auth/mbedtls/mbedtls/check_config.h Obviously, it does not exist since check_config.h is located in the mbedtls project. It is more sensible to use #include <...> form. Change-Id: If72a71381f84e7748a2c9f07dd1176559d9bb1d2 Signed-off-by: Masahiro Yamada --- include/drivers/auth/mbedtls/mbedtls_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config.h index acfde268a..f7248f984 100644 --- a/include/drivers/auth/mbedtls/mbedtls_config.h +++ b/include/drivers/auth/mbedtls/mbedtls_config.h @@ -89,7 +89,7 @@ #ifndef __ASSEMBLER__ /* System headers required to build mbed TLS with the current configuration */ #include -#include "mbedtls/check_config.h" +#include #endif /* -- cgit v1.2.3 From 6be8b610cd18431db2dafb6904c8c0323b2cbac4 Mon Sep 17 00:00:00 2001 From: zelalem-aweke Date: Wed, 4 Sep 2019 16:16:51 -0500 Subject: doc: Updated user guide with new Mbed TLS version number Signed-off-by: zelalem-aweke Change-Id: Ib12ecc0b283274c74cdfa57caf9e1a105dce3afe --- docs/getting_started/user-guide.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index b447f1493..012c8d9f1 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -1154,7 +1154,7 @@ images with support for these features: is important to use a version that is compatible with TF-A and fixes any known security vulnerabilities. See `mbed TLS Security Center`_ for more information. The latest version of TF-A is tested with tag - ``mbedtls-2.16.0``. + ``mbedtls-2.16.2``. The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS source files the modules depend upon. -- cgit v1.2.3 From 4a079c752beef8c2e8072b55a267d4b597b1e05b Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Fri, 23 Aug 2019 18:28:36 +0100 Subject: meson: Rename platform directory to amlogic Meson is the internal code name for the SoC family. The correct name for the platform should be Amlogic. Change the name of the platform directory. Signed-off-by: Carlo Caione Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d --- .gitignore | 2 +- docs/maintainers.rst | 8 +- drivers/amlogic/console/aarch64/meson_console.S | 263 ++++++++++++++++++++++++ drivers/amlogic/gxl/crypto/sha_dma.c | 185 +++++++++++++++++ drivers/meson/console/aarch64/meson_console.S | 263 ------------------------ drivers/meson/gxl/crypto/sha_dma.c | 185 ----------------- include/drivers/amlogic/gxl/crypto/sha_dma.h | 36 ++++ include/drivers/amlogic/meson_console.h | 37 ++++ include/drivers/meson/gxl/crypto/sha_dma.h | 36 ---- include/drivers/meson/meson_console.h | 37 ---- plat/amlogic/gxbb/aarch64/gxbb_helpers.S | 97 +++++++++ plat/amlogic/gxbb/gxbb_bl31_setup.c | 146 +++++++++++++ plat/amlogic/gxbb/gxbb_common.c | 145 +++++++++++++ plat/amlogic/gxbb/gxbb_def.h | 118 +++++++++++ plat/amlogic/gxbb/gxbb_efuse.c | 25 +++ plat/amlogic/gxbb/gxbb_mhu.c | 53 +++++ plat/amlogic/gxbb/gxbb_pm.c | 193 +++++++++++++++++ plat/amlogic/gxbb/gxbb_private.h | 38 ++++ plat/amlogic/gxbb/gxbb_scpi.c | 139 +++++++++++++ plat/amlogic/gxbb/gxbb_sip_svc.c | 68 ++++++ plat/amlogic/gxbb/gxbb_thermal.c | 27 +++ plat/amlogic/gxbb/gxbb_topology.c | 55 +++++ plat/amlogic/gxbb/include/plat_macros.S | 71 +++++++ plat/amlogic/gxbb/include/platform_def.h | 66 ++++++ plat/amlogic/gxbb/platform.mk | 69 +++++++ plat/amlogic/gxl/aarch64/gxl_helpers.S | 97 +++++++++ plat/amlogic/gxl/gxl_bl31_setup.c | 162 +++++++++++++++ plat/amlogic/gxl/gxl_common.c | 143 +++++++++++++ plat/amlogic/gxl/gxl_def.h | 128 ++++++++++++ plat/amlogic/gxl/gxl_efuse.c | 25 +++ plat/amlogic/gxl/gxl_mhu.c | 52 +++++ plat/amlogic/gxl/gxl_pm.c | 214 +++++++++++++++++++ plat/amlogic/gxl/gxl_private.h | 40 ++++ plat/amlogic/gxl/gxl_scpi.c | 211 +++++++++++++++++++ plat/amlogic/gxl/gxl_sip_svc.c | 66 ++++++ plat/amlogic/gxl/gxl_thermal.c | 27 +++ plat/amlogic/gxl/gxl_topology.c | 53 +++++ plat/amlogic/gxl/include/plat_macros.S | 71 +++++++ plat/amlogic/gxl/include/platform_def.h | 66 ++++++ plat/amlogic/gxl/platform.mk | 87 ++++++++ plat/meson/gxbb/aarch64/gxbb_helpers.S | 97 --------- plat/meson/gxbb/gxbb_bl31_setup.c | 146 ------------- plat/meson/gxbb/gxbb_common.c | 145 ------------- plat/meson/gxbb/gxbb_def.h | 118 ----------- plat/meson/gxbb/gxbb_efuse.c | 25 --- plat/meson/gxbb/gxbb_mhu.c | 53 ----- plat/meson/gxbb/gxbb_pm.c | 193 ----------------- plat/meson/gxbb/gxbb_private.h | 38 ---- plat/meson/gxbb/gxbb_scpi.c | 139 ------------- plat/meson/gxbb/gxbb_sip_svc.c | 68 ------ plat/meson/gxbb/gxbb_thermal.c | 27 --- plat/meson/gxbb/gxbb_topology.c | 55 ----- plat/meson/gxbb/include/plat_macros.S | 71 ------- plat/meson/gxbb/include/platform_def.h | 66 ------ plat/meson/gxbb/platform.mk | 69 ------- plat/meson/gxl/aarch64/gxl_helpers.S | 97 --------- plat/meson/gxl/gxl_bl31_setup.c | 162 --------------- plat/meson/gxl/gxl_common.c | 143 ------------- plat/meson/gxl/gxl_def.h | 128 ------------ plat/meson/gxl/gxl_efuse.c | 25 --- plat/meson/gxl/gxl_mhu.c | 52 ----- plat/meson/gxl/gxl_pm.c | 214 ------------------- plat/meson/gxl/gxl_private.h | 40 ---- plat/meson/gxl/gxl_scpi.c | 211 ------------------- plat/meson/gxl/gxl_sip_svc.c | 66 ------ plat/meson/gxl/gxl_thermal.c | 27 --- plat/meson/gxl/gxl_topology.c | 53 ----- plat/meson/gxl/include/plat_macros.S | 71 ------- plat/meson/gxl/include/platform_def.h | 66 ------ plat/meson/gxl/platform.mk | 87 -------- tools/amlogic/Makefile | 49 +++++ tools/amlogic/doimage.c | 94 +++++++++ tools/meson/Makefile | 49 ----- tools/meson/doimage.c | 94 --------- 74 files changed, 3421 insertions(+), 3421 deletions(-) create mode 100644 drivers/amlogic/console/aarch64/meson_console.S create mode 100644 drivers/amlogic/gxl/crypto/sha_dma.c delete mode 100644 drivers/meson/console/aarch64/meson_console.S delete mode 100644 drivers/meson/gxl/crypto/sha_dma.c create mode 100644 include/drivers/amlogic/gxl/crypto/sha_dma.h create mode 100644 include/drivers/amlogic/meson_console.h delete mode 100644 include/drivers/meson/gxl/crypto/sha_dma.h delete mode 100644 include/drivers/meson/meson_console.h create mode 100644 plat/amlogic/gxbb/aarch64/gxbb_helpers.S create mode 100644 plat/amlogic/gxbb/gxbb_bl31_setup.c create mode 100644 plat/amlogic/gxbb/gxbb_common.c create mode 100644 plat/amlogic/gxbb/gxbb_def.h create mode 100644 plat/amlogic/gxbb/gxbb_efuse.c create mode 100644 plat/amlogic/gxbb/gxbb_mhu.c create mode 100644 plat/amlogic/gxbb/gxbb_pm.c create mode 100644 plat/amlogic/gxbb/gxbb_private.h create mode 100644 plat/amlogic/gxbb/gxbb_scpi.c create mode 100644 plat/amlogic/gxbb/gxbb_sip_svc.c create mode 100644 plat/amlogic/gxbb/gxbb_thermal.c create mode 100644 plat/amlogic/gxbb/gxbb_topology.c create mode 100644 plat/amlogic/gxbb/include/plat_macros.S create mode 100644 plat/amlogic/gxbb/include/platform_def.h create mode 100644 plat/amlogic/gxbb/platform.mk create mode 100644 plat/amlogic/gxl/aarch64/gxl_helpers.S create mode 100644 plat/amlogic/gxl/gxl_bl31_setup.c create mode 100644 plat/amlogic/gxl/gxl_common.c create mode 100644 plat/amlogic/gxl/gxl_def.h create mode 100644 plat/amlogic/gxl/gxl_efuse.c create mode 100644 plat/amlogic/gxl/gxl_mhu.c create mode 100644 plat/amlogic/gxl/gxl_pm.c create mode 100644 plat/amlogic/gxl/gxl_private.h create mode 100644 plat/amlogic/gxl/gxl_scpi.c create mode 100644 plat/amlogic/gxl/gxl_sip_svc.c create mode 100644 plat/amlogic/gxl/gxl_thermal.c create mode 100644 plat/amlogic/gxl/gxl_topology.c create mode 100644 plat/amlogic/gxl/include/plat_macros.S create mode 100644 plat/amlogic/gxl/include/platform_def.h create mode 100644 plat/amlogic/gxl/platform.mk delete mode 100644 plat/meson/gxbb/aarch64/gxbb_helpers.S delete mode 100644 plat/meson/gxbb/gxbb_bl31_setup.c delete mode 100644 plat/meson/gxbb/gxbb_common.c delete mode 100644 plat/meson/gxbb/gxbb_def.h delete mode 100644 plat/meson/gxbb/gxbb_efuse.c delete mode 100644 plat/meson/gxbb/gxbb_mhu.c delete mode 100644 plat/meson/gxbb/gxbb_pm.c delete mode 100644 plat/meson/gxbb/gxbb_private.h delete mode 100644 plat/meson/gxbb/gxbb_scpi.c delete mode 100644 plat/meson/gxbb/gxbb_sip_svc.c delete mode 100644 plat/meson/gxbb/gxbb_thermal.c delete mode 100644 plat/meson/gxbb/gxbb_topology.c delete mode 100644 plat/meson/gxbb/include/plat_macros.S delete mode 100644 plat/meson/gxbb/include/platform_def.h delete mode 100644 plat/meson/gxbb/platform.mk delete mode 100644 plat/meson/gxl/aarch64/gxl_helpers.S delete mode 100644 plat/meson/gxl/gxl_bl31_setup.c delete mode 100644 plat/meson/gxl/gxl_common.c delete mode 100644 plat/meson/gxl/gxl_def.h delete mode 100644 plat/meson/gxl/gxl_efuse.c delete mode 100644 plat/meson/gxl/gxl_mhu.c delete mode 100644 plat/meson/gxl/gxl_pm.c delete mode 100644 plat/meson/gxl/gxl_private.h delete mode 100644 plat/meson/gxl/gxl_scpi.c delete mode 100644 plat/meson/gxl/gxl_sip_svc.c delete mode 100644 plat/meson/gxl/gxl_thermal.c delete mode 100644 plat/meson/gxl/gxl_topology.c delete mode 100644 plat/meson/gxl/include/plat_macros.S delete mode 100644 plat/meson/gxl/include/platform_def.h delete mode 100644 plat/meson/gxl/platform.mk create mode 100644 tools/amlogic/Makefile create mode 100644 tools/amlogic/doimage.c delete mode 100644 tools/meson/Makefile delete mode 100644 tools/meson/doimage.c diff --git a/.gitignore b/.gitignore index 6b1e05774..2abfffb40 100644 --- a/.gitignore +++ b/.gitignore @@ -22,7 +22,7 @@ tools/cert_create/src/**/*.o tools/cert_create/cert_create tools/cert_create/cert_create.exe tools/marvell/doimage/doimage -tools/meson/doimage +tools/amlogic/doimage tools/stm32image/*.o tools/stm32image/stm32image tools/stm32image/stm32image.exe diff --git a/docs/maintainers.rst b/docs/maintainers.rst index cbfc652fb..7731c72ec 100644 --- a/docs/maintainers.rst +++ b/docs/maintainers.rst @@ -37,16 +37,16 @@ Amlogic Meson S905 (GXBB) platform port :M: Andre Przywara :G: `Andre-ARM`_ :F: docs/plat/meson-gxbb.rst -:F: drivers/meson/ -:F: plat/meson/gxbb/ +:F: drivers/amlogic/ +:F: plat/amlogic/gxbb/ Amlogic Meson S905x (GXL) platform port --------------------------------------- :M: Remi Pommarel :G: `remi-triplefault`_ :F: docs/plat/meson-gxl.rst -:F: drivers/meson/gxl -:F: plat/meson/gxl/ +:F: drivers/amlogic/gxl +:F: plat/amlogic/gxl/ Armv7-A architecture port ------------------------- diff --git a/drivers/amlogic/console/aarch64/meson_console.S b/drivers/amlogic/console/aarch64/meson_console.S new file mode 100644 index 000000000..e645cbab8 --- /dev/null +++ b/drivers/amlogic/console/aarch64/meson_console.S @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + + .globl console_meson_register + .globl console_meson_init + .globl console_meson_putc + .globl console_meson_getc + .globl console_meson_flush + .globl console_meson_core_putc + .globl console_meson_core_getc + .globl console_meson_core_flush + + /* ----------------------------------------------- + * Hardware definitions + * ----------------------------------------------- + */ +#define MESON_WFIFO_OFFSET 0x0 +#define MESON_RFIFO_OFFSET 0x4 +#define MESON_CONTROL_OFFSET 0x8 +#define MESON_STATUS_OFFSET 0xC +#define MESON_MISC_OFFSET 0x10 +#define MESON_REG5_OFFSET 0x14 + +#define MESON_CONTROL_CLR_ERROR_BIT 24 +#define MESON_CONTROL_RX_RESET_BIT 23 +#define MESON_CONTROL_TX_RESET_BIT 22 +#define MESON_CONTROL_RX_ENABLE_BIT 13 +#define MESON_CONTROL_TX_ENABLE_BIT 12 + +#define MESON_STATUS_RX_EMPTY_BIT 20 +#define MESON_STATUS_TX_FULL_BIT 21 +#define MESON_STATUS_TX_EMPTY_BIT 22 + +#define MESON_REG5_USE_XTAL_CLK_BIT 24 +#define MESON_REG5_USE_NEW_RATE_BIT 23 +#define MESON_REG5_NEW_BAUD_RATE_MASK 0x7FFFFF + + /* ----------------------------------------------- + * int console_meson_register(uintptr_t base, + * uint32_t clk, uint32_t baud, + * console_meson_t *console); + * Function to initialize and register a new MESON + * console. Storage passed in for the console struct + * *must* be persistent (i.e. not from the stack). + * In: x0 - UART register base address + * w1 - UART clock in Hz + * w2 - Baud rate + * x3 - pointer to empty console_meson_t struct + * Out: return 1 on success, 0 on error + * Clobber list : x0, x1, x2, x6, x7, x14 + * ----------------------------------------------- + */ +func console_meson_register + mov x7, x30 + mov x6, x3 + cbz x6, register_fail + str x0, [x6, #CONSOLE_T_MESON_BASE] + + bl console_meson_init + cbz x0, register_fail + + mov x0, x6 + mov x30, x7 + finish_console_register meson putc=1, getc=1, flush=1 + +register_fail: + ret x7 +endfunc console_meson_register + + /* ----------------------------------------------- + * int console_meson_init(uintptr_t base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : x0-x3 + * ----------------------------------------------- + */ +func console_meson_init + cmp w0, #0 + beq init_fail + mov_imm w3, 24000000 /* TODO: This only works with a 24 MHz clock. */ + cmp w1, w3 + bne init_fail + cmp w2, #0 + beq init_fail + /* Set baud rate: value = ((clock / 3) / baudrate) - 1 */ + mov w3, #3 + udiv w3, w1, w3 + udiv w3, w3, w2 + sub w3, w3, #1 + orr w3, w3, #((1 << MESON_REG5_USE_XTAL_CLK_BIT) | \ + (1 << MESON_REG5_USE_NEW_RATE_BIT)) + str w3, [x0, #MESON_REG5_OFFSET] + /* Reset UART and clear error flag */ + ldr w3, [x0, #MESON_CONTROL_OFFSET] + orr w3, w3, #((1 << MESON_CONTROL_CLR_ERROR_BIT) | \ + (1 << MESON_CONTROL_RX_RESET_BIT) | \ + (1 << MESON_CONTROL_TX_RESET_BIT)) + str w3, [x0, #MESON_CONTROL_OFFSET] + bic w3, w3, #((1 << MESON_CONTROL_CLR_ERROR_BIT) | \ + (1 << MESON_CONTROL_RX_RESET_BIT) | \ + (1 << MESON_CONTROL_TX_RESET_BIT)) + str w3, [x0, #MESON_CONTROL_OFFSET] + /* Enable transfer and receive FIFO */ + orr w3, w3, #((1 << MESON_CONTROL_RX_ENABLE_BIT) | \ + (1 << MESON_CONTROL_TX_ENABLE_BIT)) + str w3, [x0, #MESON_CONTROL_OFFSET] + /* Success */ + mov w0, #1 + ret +init_fail: + mov w0, wzr + ret +endfunc console_meson_init + + /* -------------------------------------------------------- + * int console_meson_putc(int c, console_meson_t *console) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - pointer to console_t structure + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_meson_putc +#if ENABLE_ASSERTIONS + cmp x1, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x1, [x1, #CONSOLE_T_MESON_BASE] + b console_meson_core_putc +endfunc console_meson_putc + + /* -------------------------------------------------------- + * int console_meson_core_putc(int c, uintptr_t base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_meson_core_putc +#if ENABLE_ASSERTIONS + cmp x1, #0 + ASM_ASSERT(ne) +#endif + /* Prepend '\r' to '\n' */ + cmp w0, #0xA + b.ne 2f + /* Wait until the transmit FIFO isn't full */ +1: ldr w2, [x1, #MESON_STATUS_OFFSET] + tbnz w2, #MESON_STATUS_TX_FULL_BIT, 1b + /* Write '\r' if needed */ + mov w2, #0xD + str w2, [x1, #MESON_WFIFO_OFFSET] + /* Wait until the transmit FIFO isn't full */ +2: ldr w2, [x1, #MESON_STATUS_OFFSET] + tbnz w2, #MESON_STATUS_TX_FULL_BIT, 2b + /* Write input character */ + str w0, [x1, #MESON_WFIFO_OFFSET] + ret +endfunc console_meson_core_putc + + /* --------------------------------------------- + * int console_meson_getc(console_meson_t *console) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 if no character is available. + * In : x0 - pointer to console_t structure + * Out: w0 - character if available, else -1 + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_meson_getc +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x0, [x0, #CONSOLE_T_MESON_BASE] + b console_meson_core_getc +endfunc console_meson_getc + + /* --------------------------------------------- + * int console_meson_core_getc(uintptr_t base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 if no character is available. + * In : x0 - console base address + * Out: w0 - character if available, else -1 + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_meson_core_getc +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif + /* Is the receive FIFO empty? */ + ldr w1, [x0, #MESON_STATUS_OFFSET] + tbnz w1, #MESON_STATUS_RX_EMPTY_BIT, 1f + /* Read one character from the RX FIFO */ + ldr w0, [x0, #MESON_RFIFO_OFFSET] + ret +1: + mov w0, #ERROR_NO_PENDING_CHAR + ret +endfunc console_meson_core_getc + + /* --------------------------------------------- + * int console_meson_flush(console_meson_t *console) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - pointer to console_t structure + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_meson_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x0, [x0, #CONSOLE_T_MESON_BASE] + b console_meson_core_flush +endfunc console_meson_flush + + /* --------------------------------------------- + * int console_meson_core_flush(uintptr_t base_addr) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - console base address + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_meson_core_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif + /* Wait until the transmit FIFO is empty */ +1: ldr w1, [x0, #MESON_STATUS_OFFSET] + tbz w1, #MESON_STATUS_TX_EMPTY_BIT, 1b + mov w0, #0 + ret +endfunc console_meson_core_flush diff --git a/drivers/amlogic/gxl/crypto/sha_dma.c b/drivers/amlogic/gxl/crypto/sha_dma.c new file mode 100644 index 000000000..a969dea74 --- /dev/null +++ b/drivers/amlogic/gxl/crypto/sha_dma.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2019, Remi Pommarel + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#define AML_SHA_DMA_BASE 0xc883e000 + +#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08) +#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18) + +#define ASD_MODE_SHA224 0x7 +#define ASD_MODE_SHA256 0x6 + +/* SHA DMA descriptor */ +struct asd_desc { + uint32_t cfg; + uint32_t src; + uint32_t dst; +}; +#define ASD_DESC_GET(x, msk, off) (((x) >> (off)) & (msk)) +#define ASD_DESC_SET(x, v, msk, off) \ + ((x) = ((x) & ~((msk) << (off))) | (((v) & (msk)) << (off))) + +#define ASD_DESC_LEN_OFF 0 +#define ASD_DESC_LEN_MASK 0x1ffff +#define ASD_DESC_LEN(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF)) +#define ASD_DESC_LEN_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF)) + +#define ASD_DESC_IRQ_OFF 17 +#define ASD_DESC_IRQ_MASK 0x1 +#define ASD_DESC_IRQ(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF)) +#define ASD_DESC_IRQ_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF)) + +#define ASD_DESC_EOD_OFF 18 +#define ASD_DESC_EOD_MASK 0x1 +#define ASD_DESC_EOD(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF)) +#define ASD_DESC_EOD_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF)) + +#define ASD_DESC_LOOP_OFF 19 +#define ASD_DESC_LOOP_MASK 0x1 +#define ASD_DESC_LOOP(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF)) +#define ASD_DESC_LOOP_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF)) + +#define ASD_DESC_MODE_OFF 20 +#define ASD_DESC_MODE_MASK 0xf +#define ASD_DESC_MODE(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF)) +#define ASD_DESC_MODE_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF)) + +#define ASD_DESC_BEGIN_OFF 24 +#define ASD_DESC_BEGIN_MASK 0x1 +#define ASD_DESC_BEGIN(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_BEGIN_MASK, ASD_DESC_BEGIN_OFF)) +#define ASD_DESC_BEGIN_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_BEGIN_MASK, ASD_DESC_BEGIN_OFF)) + +#define ASD_DESC_END_OFF 25 +#define ASD_DESC_END_MASK 0x1 +#define ASD_DESC_END(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_END_MASK, ASD_DESC_END_OFF)) +#define ASD_DESC_END_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_END_MASK, ASD_DESC_END_OFF)) + +#define ASD_DESC_OP_OFF 26 +#define ASD_DESC_OP_MASK 0x2 +#define ASD_DESC_OP(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_OP_MASK, ASD_DESC_OP_OFF)) +#define ASD_DESC_OP_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_OP_MASK, ASD_DESC_OP_OFF)) + +#define ASD_DESC_ENCONLY_OFF 28 +#define ASD_DESC_ENCONLY_MASK 0x1 +#define ASD_DESC_ENCONLY(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_ENCONLY_MASK, ASD_DESC_ENCONLY_OFF)) +#define ASD_DESC_ENCONLY_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_ENCONLY_MASK, ASD_DESC_ENCONLY_OFF)) + +#define ASD_DESC_BLOCK_OFF 29 +#define ASD_DESC_BLOCK_MASK 0x1 +#define ASD_DESC_BLOCK(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_BLOCK_MASK, ASD_DESC_BLOCK_OFF)) +#define ASD_DESC_BLOCK_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_BLOCK_MASK, ASD_DESC_BLOCK_OFF)) + +#define ASD_DESC_ERR_OFF 30 +#define ASD_DESC_ERR_MASK 0x1 +#define ASD_DESC_ERR(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF)) +#define ASD_DESC_ERR_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF)) + +#define ASD_DESC_OWNER_OFF 31u +#define ASD_DESC_OWNER_MASK 0x1u +#define ASD_DESC_OWNER(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF)) +#define ASD_DESC_OWNER_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF)) + +static void asd_compute_sha(struct asd_ctx *ctx, void *data, size_t len, + int finalize) +{ + /* Make it cache line size aligned ? */ + struct asd_desc desc = { + .src = (uint32_t)(uintptr_t)data, + .dst = (uint32_t)(uintptr_t)ctx->digest, + }; + + /* Check data address is 32bit compatible */ + assert((uintptr_t)data == (uintptr_t)desc.src); + assert((uintptr_t)ctx->digest == (uintptr_t)desc.dst); + assert((uintptr_t)&desc == (uintptr_t)&desc); + + ASD_DESC_LEN_SET(&desc, len); + ASD_DESC_OWNER_SET(&desc, 1u); + ASD_DESC_ENCONLY_SET(&desc, 1); + ASD_DESC_EOD_SET(&desc, 1); + if (ctx->started == 0) { + ASD_DESC_BEGIN_SET(&desc, 1); + ctx->started = 1; + } + if (finalize) { + ASD_DESC_END_SET(&desc, 1); + ctx->started = 0; + } + if (ctx->mode == ASM_SHA224) + ASD_DESC_MODE_SET(&desc, ASD_MODE_SHA224); + else + ASD_DESC_MODE_SET(&desc, ASD_MODE_SHA256); + + flush_dcache_range((uintptr_t)&desc, sizeof(desc)); + flush_dcache_range((uintptr_t)data, len); + + mmio_write_32(AML_SHA_DMA_STATUS, 0xf); + mmio_write_32(AML_SHA_DMA_DESC, ((uintptr_t)&desc) | 2); + while (mmio_read_32(AML_SHA_DMA_STATUS) == 0) + continue; + flush_dcache_range((uintptr_t)ctx->digest, SHA256_HASHSZ); +} + +void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len) +{ + size_t nr; + + if (ctx->blocksz) { + nr = MIN(len, SHA256_BLOCKSZ - ctx->blocksz); + memcpy(ctx->block + ctx->blocksz, data, nr); + ctx->blocksz += nr; + len -= nr; + data += nr; + } + + if (ctx->blocksz == SHA256_BLOCKSZ) { + asd_compute_sha(ctx, ctx->block, SHA256_BLOCKSZ, 0); + ctx->blocksz = 0; + } + + asd_compute_sha(ctx, data, len & ~(SHA256_BLOCKSZ - 1), 0); + data += len & ~(SHA256_BLOCKSZ - 1); + + if (len & (SHA256_BLOCKSZ - 1)) { + nr = len & (SHA256_BLOCKSZ - 1); + memcpy(ctx->block + ctx->blocksz, data, nr); + ctx->blocksz += nr; + } +} + +void asd_sha_finalize(struct asd_ctx *ctx) +{ + asd_compute_sha(ctx, ctx->block, ctx->blocksz, 1); +} diff --git a/drivers/meson/console/aarch64/meson_console.S b/drivers/meson/console/aarch64/meson_console.S deleted file mode 100644 index 22d077332..000000000 --- a/drivers/meson/console/aarch64/meson_console.S +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - - .globl console_meson_register - .globl console_meson_init - .globl console_meson_putc - .globl console_meson_getc - .globl console_meson_flush - .globl console_meson_core_putc - .globl console_meson_core_getc - .globl console_meson_core_flush - - /* ----------------------------------------------- - * Hardware definitions - * ----------------------------------------------- - */ -#define MESON_WFIFO_OFFSET 0x0 -#define MESON_RFIFO_OFFSET 0x4 -#define MESON_CONTROL_OFFSET 0x8 -#define MESON_STATUS_OFFSET 0xC -#define MESON_MISC_OFFSET 0x10 -#define MESON_REG5_OFFSET 0x14 - -#define MESON_CONTROL_CLR_ERROR_BIT 24 -#define MESON_CONTROL_RX_RESET_BIT 23 -#define MESON_CONTROL_TX_RESET_BIT 22 -#define MESON_CONTROL_RX_ENABLE_BIT 13 -#define MESON_CONTROL_TX_ENABLE_BIT 12 - -#define MESON_STATUS_RX_EMPTY_BIT 20 -#define MESON_STATUS_TX_FULL_BIT 21 -#define MESON_STATUS_TX_EMPTY_BIT 22 - -#define MESON_REG5_USE_XTAL_CLK_BIT 24 -#define MESON_REG5_USE_NEW_RATE_BIT 23 -#define MESON_REG5_NEW_BAUD_RATE_MASK 0x7FFFFF - - /* ----------------------------------------------- - * int console_meson_register(uintptr_t base, - * uint32_t clk, uint32_t baud, - * console_meson_t *console); - * Function to initialize and register a new MESON - * console. Storage passed in for the console struct - * *must* be persistent (i.e. not from the stack). - * In: x0 - UART register base address - * w1 - UART clock in Hz - * w2 - Baud rate - * x3 - pointer to empty console_meson_t struct - * Out: return 1 on success, 0 on error - * Clobber list : x0, x1, x2, x6, x7, x14 - * ----------------------------------------------- - */ -func console_meson_register - mov x7, x30 - mov x6, x3 - cbz x6, register_fail - str x0, [x6, #CONSOLE_T_MESON_BASE] - - bl console_meson_init - cbz x0, register_fail - - mov x0, x6 - mov x30, x7 - finish_console_register meson putc=1, getc=1, flush=1 - -register_fail: - ret x7 -endfunc console_meson_register - - /* ----------------------------------------------- - * int console_meson_init(uintptr_t base_addr, - * unsigned int uart_clk, unsigned int baud_rate) - * Function to initialize the console without a - * C Runtime to print debug information. This - * function will be accessed by console_init and - * crash reporting. - * In: x0 - console base address - * w1 - Uart clock in Hz - * w2 - Baud rate - * Out: return 1 on success else 0 on error - * Clobber list : x0-x3 - * ----------------------------------------------- - */ -func console_meson_init - cmp w0, #0 - beq init_fail - mov_imm w3, 24000000 /* TODO: This only works with a 24 MHz clock. */ - cmp w1, w3 - bne init_fail - cmp w2, #0 - beq init_fail - /* Set baud rate: value = ((clock / 3) / baudrate) - 1 */ - mov w3, #3 - udiv w3, w1, w3 - udiv w3, w3, w2 - sub w3, w3, #1 - orr w3, w3, #((1 << MESON_REG5_USE_XTAL_CLK_BIT) | \ - (1 << MESON_REG5_USE_NEW_RATE_BIT)) - str w3, [x0, #MESON_REG5_OFFSET] - /* Reset UART and clear error flag */ - ldr w3, [x0, #MESON_CONTROL_OFFSET] - orr w3, w3, #((1 << MESON_CONTROL_CLR_ERROR_BIT) | \ - (1 << MESON_CONTROL_RX_RESET_BIT) | \ - (1 << MESON_CONTROL_TX_RESET_BIT)) - str w3, [x0, #MESON_CONTROL_OFFSET] - bic w3, w3, #((1 << MESON_CONTROL_CLR_ERROR_BIT) | \ - (1 << MESON_CONTROL_RX_RESET_BIT) | \ - (1 << MESON_CONTROL_TX_RESET_BIT)) - str w3, [x0, #MESON_CONTROL_OFFSET] - /* Enable transfer and receive FIFO */ - orr w3, w3, #((1 << MESON_CONTROL_RX_ENABLE_BIT) | \ - (1 << MESON_CONTROL_TX_ENABLE_BIT)) - str w3, [x0, #MESON_CONTROL_OFFSET] - /* Success */ - mov w0, #1 - ret -init_fail: - mov w0, wzr - ret -endfunc console_meson_init - - /* -------------------------------------------------------- - * int console_meson_putc(int c, console_meson_t *console) - * Function to output a character over the console. It - * returns the character printed on success or -1 on error. - * In : w0 - character to be printed - * x1 - pointer to console_t structure - * Out : return -1 on error else return character. - * Clobber list : x2 - * -------------------------------------------------------- - */ -func console_meson_putc -#if ENABLE_ASSERTIONS - cmp x1, #0 - ASM_ASSERT(ne) -#endif /* ENABLE_ASSERTIONS */ - ldr x1, [x1, #CONSOLE_T_MESON_BASE] - b console_meson_core_putc -endfunc console_meson_putc - - /* -------------------------------------------------------- - * int console_meson_core_putc(int c, uintptr_t base_addr) - * Function to output a character over the console. It - * returns the character printed on success or -1 on error. - * In : w0 - character to be printed - * x1 - console base address - * Out : return -1 on error else return character. - * Clobber list : x2 - * -------------------------------------------------------- - */ -func console_meson_core_putc -#if ENABLE_ASSERTIONS - cmp x1, #0 - ASM_ASSERT(ne) -#endif - /* Prepend '\r' to '\n' */ - cmp w0, #0xA - b.ne 2f - /* Wait until the transmit FIFO isn't full */ -1: ldr w2, [x1, #MESON_STATUS_OFFSET] - tbnz w2, #MESON_STATUS_TX_FULL_BIT, 1b - /* Write '\r' if needed */ - mov w2, #0xD - str w2, [x1, #MESON_WFIFO_OFFSET] - /* Wait until the transmit FIFO isn't full */ -2: ldr w2, [x1, #MESON_STATUS_OFFSET] - tbnz w2, #MESON_STATUS_TX_FULL_BIT, 2b - /* Write input character */ - str w0, [x1, #MESON_WFIFO_OFFSET] - ret -endfunc console_meson_core_putc - - /* --------------------------------------------- - * int console_meson_getc(console_meson_t *console) - * Function to get a character from the console. - * It returns the character grabbed on success - * or -1 if no character is available. - * In : x0 - pointer to console_t structure - * Out: w0 - character if available, else -1 - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func console_meson_getc -#if ENABLE_ASSERTIONS - cmp x0, #0 - ASM_ASSERT(ne) -#endif /* ENABLE_ASSERTIONS */ - ldr x0, [x0, #CONSOLE_T_MESON_BASE] - b console_meson_core_getc -endfunc console_meson_getc - - /* --------------------------------------------- - * int console_meson_core_getc(uintptr_t base_addr) - * Function to get a character from the console. - * It returns the character grabbed on success - * or -1 if no character is available. - * In : x0 - console base address - * Out: w0 - character if available, else -1 - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func console_meson_core_getc -#if ENABLE_ASSERTIONS - cmp x0, #0 - ASM_ASSERT(ne) -#endif - /* Is the receive FIFO empty? */ - ldr w1, [x0, #MESON_STATUS_OFFSET] - tbnz w1, #MESON_STATUS_RX_EMPTY_BIT, 1f - /* Read one character from the RX FIFO */ - ldr w0, [x0, #MESON_RFIFO_OFFSET] - ret -1: - mov w0, #ERROR_NO_PENDING_CHAR - ret -endfunc console_meson_core_getc - - /* --------------------------------------------- - * int console_meson_flush(console_meson_t *console) - * Function to force a write of all buffered - * data that hasn't been output. - * In : x0 - pointer to console_t structure - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func console_meson_flush -#if ENABLE_ASSERTIONS - cmp x0, #0 - ASM_ASSERT(ne) -#endif /* ENABLE_ASSERTIONS */ - ldr x0, [x0, #CONSOLE_T_MESON_BASE] - b console_meson_core_flush -endfunc console_meson_flush - - /* --------------------------------------------- - * int console_meson_core_flush(uintptr_t base_addr) - * Function to force a write of all buffered - * data that hasn't been output. - * In : x0 - console base address - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func console_meson_core_flush -#if ENABLE_ASSERTIONS - cmp x0, #0 - ASM_ASSERT(ne) -#endif - /* Wait until the transmit FIFO is empty */ -1: ldr w1, [x0, #MESON_STATUS_OFFSET] - tbz w1, #MESON_STATUS_TX_EMPTY_BIT, 1b - mov w0, #0 - ret -endfunc console_meson_core_flush diff --git a/drivers/meson/gxl/crypto/sha_dma.c b/drivers/meson/gxl/crypto/sha_dma.c deleted file mode 100644 index a969dea74..000000000 --- a/drivers/meson/gxl/crypto/sha_dma.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2019, Remi Pommarel - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -#define AML_SHA_DMA_BASE 0xc883e000 - -#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08) -#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18) - -#define ASD_MODE_SHA224 0x7 -#define ASD_MODE_SHA256 0x6 - -/* SHA DMA descriptor */ -struct asd_desc { - uint32_t cfg; - uint32_t src; - uint32_t dst; -}; -#define ASD_DESC_GET(x, msk, off) (((x) >> (off)) & (msk)) -#define ASD_DESC_SET(x, v, msk, off) \ - ((x) = ((x) & ~((msk) << (off))) | (((v) & (msk)) << (off))) - -#define ASD_DESC_LEN_OFF 0 -#define ASD_DESC_LEN_MASK 0x1ffff -#define ASD_DESC_LEN(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF)) -#define ASD_DESC_LEN_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF)) - -#define ASD_DESC_IRQ_OFF 17 -#define ASD_DESC_IRQ_MASK 0x1 -#define ASD_DESC_IRQ(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF)) -#define ASD_DESC_IRQ_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF)) - -#define ASD_DESC_EOD_OFF 18 -#define ASD_DESC_EOD_MASK 0x1 -#define ASD_DESC_EOD(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF)) -#define ASD_DESC_EOD_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF)) - -#define ASD_DESC_LOOP_OFF 19 -#define ASD_DESC_LOOP_MASK 0x1 -#define ASD_DESC_LOOP(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF)) -#define ASD_DESC_LOOP_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF)) - -#define ASD_DESC_MODE_OFF 20 -#define ASD_DESC_MODE_MASK 0xf -#define ASD_DESC_MODE(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF)) -#define ASD_DESC_MODE_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF)) - -#define ASD_DESC_BEGIN_OFF 24 -#define ASD_DESC_BEGIN_MASK 0x1 -#define ASD_DESC_BEGIN(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_BEGIN_MASK, ASD_DESC_BEGIN_OFF)) -#define ASD_DESC_BEGIN_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_BEGIN_MASK, ASD_DESC_BEGIN_OFF)) - -#define ASD_DESC_END_OFF 25 -#define ASD_DESC_END_MASK 0x1 -#define ASD_DESC_END(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_END_MASK, ASD_DESC_END_OFF)) -#define ASD_DESC_END_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_END_MASK, ASD_DESC_END_OFF)) - -#define ASD_DESC_OP_OFF 26 -#define ASD_DESC_OP_MASK 0x2 -#define ASD_DESC_OP(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_OP_MASK, ASD_DESC_OP_OFF)) -#define ASD_DESC_OP_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_OP_MASK, ASD_DESC_OP_OFF)) - -#define ASD_DESC_ENCONLY_OFF 28 -#define ASD_DESC_ENCONLY_MASK 0x1 -#define ASD_DESC_ENCONLY(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_ENCONLY_MASK, ASD_DESC_ENCONLY_OFF)) -#define ASD_DESC_ENCONLY_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_ENCONLY_MASK, ASD_DESC_ENCONLY_OFF)) - -#define ASD_DESC_BLOCK_OFF 29 -#define ASD_DESC_BLOCK_MASK 0x1 -#define ASD_DESC_BLOCK(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_BLOCK_MASK, ASD_DESC_BLOCK_OFF)) -#define ASD_DESC_BLOCK_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_BLOCK_MASK, ASD_DESC_BLOCK_OFF)) - -#define ASD_DESC_ERR_OFF 30 -#define ASD_DESC_ERR_MASK 0x1 -#define ASD_DESC_ERR(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF)) -#define ASD_DESC_ERR_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF)) - -#define ASD_DESC_OWNER_OFF 31u -#define ASD_DESC_OWNER_MASK 0x1u -#define ASD_DESC_OWNER(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF)) -#define ASD_DESC_OWNER_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF)) - -static void asd_compute_sha(struct asd_ctx *ctx, void *data, size_t len, - int finalize) -{ - /* Make it cache line size aligned ? */ - struct asd_desc desc = { - .src = (uint32_t)(uintptr_t)data, - .dst = (uint32_t)(uintptr_t)ctx->digest, - }; - - /* Check data address is 32bit compatible */ - assert((uintptr_t)data == (uintptr_t)desc.src); - assert((uintptr_t)ctx->digest == (uintptr_t)desc.dst); - assert((uintptr_t)&desc == (uintptr_t)&desc); - - ASD_DESC_LEN_SET(&desc, len); - ASD_DESC_OWNER_SET(&desc, 1u); - ASD_DESC_ENCONLY_SET(&desc, 1); - ASD_DESC_EOD_SET(&desc, 1); - if (ctx->started == 0) { - ASD_DESC_BEGIN_SET(&desc, 1); - ctx->started = 1; - } - if (finalize) { - ASD_DESC_END_SET(&desc, 1); - ctx->started = 0; - } - if (ctx->mode == ASM_SHA224) - ASD_DESC_MODE_SET(&desc, ASD_MODE_SHA224); - else - ASD_DESC_MODE_SET(&desc, ASD_MODE_SHA256); - - flush_dcache_range((uintptr_t)&desc, sizeof(desc)); - flush_dcache_range((uintptr_t)data, len); - - mmio_write_32(AML_SHA_DMA_STATUS, 0xf); - mmio_write_32(AML_SHA_DMA_DESC, ((uintptr_t)&desc) | 2); - while (mmio_read_32(AML_SHA_DMA_STATUS) == 0) - continue; - flush_dcache_range((uintptr_t)ctx->digest, SHA256_HASHSZ); -} - -void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len) -{ - size_t nr; - - if (ctx->blocksz) { - nr = MIN(len, SHA256_BLOCKSZ - ctx->blocksz); - memcpy(ctx->block + ctx->blocksz, data, nr); - ctx->blocksz += nr; - len -= nr; - data += nr; - } - - if (ctx->blocksz == SHA256_BLOCKSZ) { - asd_compute_sha(ctx, ctx->block, SHA256_BLOCKSZ, 0); - ctx->blocksz = 0; - } - - asd_compute_sha(ctx, data, len & ~(SHA256_BLOCKSZ - 1), 0); - data += len & ~(SHA256_BLOCKSZ - 1); - - if (len & (SHA256_BLOCKSZ - 1)) { - nr = len & (SHA256_BLOCKSZ - 1); - memcpy(ctx->block + ctx->blocksz, data, nr); - ctx->blocksz += nr; - } -} - -void asd_sha_finalize(struct asd_ctx *ctx) -{ - asd_compute_sha(ctx, ctx->block, ctx->blocksz, 1); -} diff --git a/include/drivers/amlogic/gxl/crypto/sha_dma.h b/include/drivers/amlogic/gxl/crypto/sha_dma.h new file mode 100644 index 000000000..52129a61f --- /dev/null +++ b/include/drivers/amlogic/gxl/crypto/sha_dma.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2019, Remi Pommarel + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef SHA_DMA_H +#define SHA_DMA_H + +#define SHA256_HASHSZ 32 +#define SHA256_BLOCKSZ 0x40 + +enum ASD_MODE { + ASM_INVAL, + ASM_SHA256, + ASM_SHA224, +}; + +struct asd_ctx { + uint8_t digest[SHA256_HASHSZ]; + uint8_t block[SHA256_BLOCKSZ]; + size_t blocksz; + enum ASD_MODE mode; + uint8_t started; +}; + +static inline void asd_sha_init(struct asd_ctx *ctx, enum ASD_MODE mode) +{ + ctx->started = 0; + ctx->mode = mode; + ctx->blocksz = 0; +} + +void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len); +void asd_sha_finalize(struct asd_ctx *ctx); + +#endif diff --git a/include/drivers/amlogic/meson_console.h b/include/drivers/amlogic/meson_console.h new file mode 100644 index 000000000..70e3b0bd4 --- /dev/null +++ b/include/drivers/amlogic/meson_console.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MESON_CONSOLE_H +#define MESON_CONSOLE_H + +#include + +#define CONSOLE_T_MESON_BASE CONSOLE_T_DRVDATA + +#ifndef __ASSEMBLER__ + +#include + +typedef struct { + console_t console; + uintptr_t base; +} console_meson_t; + +/* + * Initialize a new meson console instance and register it with the console + * framework. The |console| pointer must point to storage that will be valid + * for the lifetime of the console, such as a global or static local variable. + * Its contents will be reinitialized from scratch. + * + * NOTE: The clock is actually fixed to 24 MHz. The argument is only there in + * order to make this function future-proof. + */ +int console_meson_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, + console_meson_t *console); + +#endif /*__ASSEMBLER__*/ + +#endif /* MESON_CONSOLE_H */ diff --git a/include/drivers/meson/gxl/crypto/sha_dma.h b/include/drivers/meson/gxl/crypto/sha_dma.h deleted file mode 100644 index 52129a61f..000000000 --- a/include/drivers/meson/gxl/crypto/sha_dma.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2019, Remi Pommarel - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef SHA_DMA_H -#define SHA_DMA_H - -#define SHA256_HASHSZ 32 -#define SHA256_BLOCKSZ 0x40 - -enum ASD_MODE { - ASM_INVAL, - ASM_SHA256, - ASM_SHA224, -}; - -struct asd_ctx { - uint8_t digest[SHA256_HASHSZ]; - uint8_t block[SHA256_BLOCKSZ]; - size_t blocksz; - enum ASD_MODE mode; - uint8_t started; -}; - -static inline void asd_sha_init(struct asd_ctx *ctx, enum ASD_MODE mode) -{ - ctx->started = 0; - ctx->mode = mode; - ctx->blocksz = 0; -} - -void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len); -void asd_sha_finalize(struct asd_ctx *ctx); - -#endif diff --git a/include/drivers/meson/meson_console.h b/include/drivers/meson/meson_console.h deleted file mode 100644 index 70e3b0bd4..000000000 --- a/include/drivers/meson/meson_console.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef MESON_CONSOLE_H -#define MESON_CONSOLE_H - -#include - -#define CONSOLE_T_MESON_BASE CONSOLE_T_DRVDATA - -#ifndef __ASSEMBLER__ - -#include - -typedef struct { - console_t console; - uintptr_t base; -} console_meson_t; - -/* - * Initialize a new meson console instance and register it with the console - * framework. The |console| pointer must point to storage that will be valid - * for the lifetime of the console, such as a global or static local variable. - * Its contents will be reinitialized from scratch. - * - * NOTE: The clock is actually fixed to 24 MHz. The argument is only there in - * order to make this function future-proof. - */ -int console_meson_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_meson_t *console); - -#endif /*__ASSEMBLER__*/ - -#endif /* MESON_CONSOLE_H */ diff --git a/plat/amlogic/gxbb/aarch64/gxbb_helpers.S b/plat/amlogic/gxbb/aarch64/gxbb_helpers.S new file mode 100644 index 000000000..760d6c46d --- /dev/null +++ b/plat/amlogic/gxbb/aarch64/gxbb_helpers.S @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + + .globl plat_crash_console_flush + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl platform_mem_init + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_reset_handler + .globl plat_gxbb_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void); + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_gxbb_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); + * ----------------------------------------------------- + */ +func plat_gxbb_calc_core_pos + and x0, x0, #MPIDR_CPU_MASK + ret +endfunc plat_gxbb_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary(void); + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #GXBB_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + + /* --------------------------------------------- + * void platform_mem_init(void); + * --------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, GXBB_UART0_AO_BASE + mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ + mov_imm x2, GXBB_UART_BAUDRATE + b console_meson_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, GXBB_UART0_AO_BASE + b console_meson_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush() + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x0, GXBB_UART0_AO_BASE + b console_meson_core_flush +endfunc plat_crash_console_flush + + /* --------------------------------------------- + * void plat_reset_handler(void); + * --------------------------------------------- + */ +func plat_reset_handler + ret +endfunc plat_reset_handler diff --git a/plat/amlogic/gxbb/gxbb_bl31_setup.c b/plat/amlogic/gxbb/gxbb_bl31_setup.c new file mode 100644 index 000000000..b867a5846 --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_bl31_setup.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include + +#include "gxbb_private.h" + +/* + * Placeholder variables for copying the arguments that have been passed to + * BL31 from BL2. + */ +static entry_point_info_t bl33_image_ep_info; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(type == NON_SECURE); + + next_image_info = &bl33_image_ep_info; + + /* None of the images can have 0x0 as the entrypoint. */ + if (next_image_info->pc != 0U) { + return next_image_info; + } else { + return NULL; + } +} + +/******************************************************************************* + * Perform any BL31 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before + * they are lost (potentially). This needs to be done before the MMU is + * initialized so that the memory layout can be used while creating page + * tables. BL2 has flushed this information to memory, so we are guaranteed + * to pick up good data. + ******************************************************************************/ +struct gxbb_bl31_param { + param_header_t h; + image_info_t *bl31_image_info; + entry_point_info_t *bl32_ep_info; + image_info_t *bl32_image_info; + entry_point_info_t *bl33_ep_info; + image_info_t *bl33_image_info; +}; + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + struct gxbb_bl31_param *from_bl2; + + /* Initialize the console to provide early debug support */ + gxbb_console_init(); + + /* + * In debug builds, we pass a special value in 'arg1' to verify platform + * parameters from BL2 to BL31. In release builds it's not used. + */ + assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL); + + /* Check that params passed from BL2 are not NULL. */ + from_bl2 = (struct gxbb_bl31_param *) arg0; + + /* Check params passed from BL2 are not NULL. */ + assert(from_bl2 != NULL); + assert(from_bl2->h.type == PARAM_BL31); + assert(from_bl2->h.version >= VERSION_1); + + /* + * Copy BL33 entry point information. It is stored in Secure RAM, in + * BL2's address space. + */ + bl33_image_ep_info = *from_bl2->bl33_ep_info; + + if (bl33_image_ep_info.pc == 0U) { + ERROR("BL31: BL33 entrypoint not obtained from BL2\n"); + panic(); + } +} + +void bl31_plat_arch_setup(void) +{ + gxbb_setup_page_tables(); + + enable_mmu_el3(0); +} + +/******************************************************************************* + * GICv2 driver setup information + ******************************************************************************/ +static const interrupt_prop_t gxbb_interrupt_props[] = { + INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), +}; + +static const gicv2_driver_data_t gxbb_gic_data = { + .gicd_base = GXBB_GICD_BASE, + .gicc_base = GXBB_GICC_BASE, + .interrupt_props = gxbb_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), +}; + +void bl31_platform_setup(void) +{ + mhu_secure_init(); + + gicv2_driver_init(&gxbb_gic_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); + + gxbb_thermal_unknown(); +} diff --git a/plat/amlogic/gxbb/gxbb_common.c b/plat/amlogic/gxbb/gxbb_common.c new file mode 100644 index 000000000..eb688f772 --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_common.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Platform memory map regions + ******************************************************************************/ +#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \ + GXBB_NSDRAM0_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \ + GXBB_NSDRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \ + GXBB_SEC_DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \ + GXBB_SEC_DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \ + GXBB_TZRAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \ + GXBB_SEC_DEVICE2_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \ + GXBB_SEC_DEVICE3_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +static const mmap_region_t gxbb_mmap[] = { + MAP_NSDRAM0, + MAP_NSDRAM1, + MAP_SEC_DEVICE0, + MAP_SEC_DEVICE1, + MAP_TZRAM, + MAP_SEC_DEVICE2, + MAP_SEC_DEVICE3, + {0} +}; + +/******************************************************************************* + * Per-image regions + ******************************************************************************/ +#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \ + BL31_END - BL31_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) + +#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \ + BL_RO_DATA_END - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) + +#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/******************************************************************************* + * Function that sets up the translation tables. + ******************************************************************************/ +void gxbb_setup_page_tables(void) +{ +#if IMAGE_BL31 + const mmap_region_t gxbb_bl_mmap[] = { + MAP_BL31, + MAP_BL_CODE, + MAP_BL_RO_DATA, +#if USE_COHERENT_MEM + MAP_BL_COHERENT, +#endif + {0} + }; +#endif + + mmap_add(gxbb_bl_mmap); + + mmap_add(gxbb_mmap); + + init_xlat_tables(); +} + +/******************************************************************************* + * Function that sets up the console + ******************************************************************************/ +static console_meson_t gxbb_console; + +void gxbb_console_init(void) +{ + int rc = console_meson_register(GXBB_UART0_AO_BASE, + GXBB_UART0_AO_CLK_IN_HZ, + GXBB_UART_BAUDRATE, + &gxbb_console); + if (rc == 0) { + /* + * The crash console doesn't use the multi console API, it uses + * the core console functions directly. It is safe to call panic + * and let it print debug information. + */ + panic(); + } + + console_set_scope(&gxbb_console.console, + CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); +} + +/******************************************************************************* + * Function that returns the system counter frequency + ******************************************************************************/ +unsigned int plat_get_syscnt_freq2(void) +{ + uint32_t val; + + val = mmio_read_32(GXBB_SYS_CPU_CFG7); + val &= 0xFDFFFFFF; + mmio_write_32(GXBB_SYS_CPU_CFG7, val); + + val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL); + val &= 0xFFFFFE00; + mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val); + + return GXBB_OSC24M_CLK_IN_HZ; +} diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h new file mode 100644 index 000000000..3e27097c3 --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_def.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GXBB_DEF_H +#define GXBB_DEF_H + +#include + +/******************************************************************************* + * System oscillator + ******************************************************************************/ +#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ + +/******************************************************************************* + * Memory regions + ******************************************************************************/ +#define GXBB_NSDRAM0_BASE UL(0x01000000) +#define GXBB_NSDRAM0_SIZE UL(0x0F000000) + +#define GXBB_NSDRAM1_BASE UL(0x10000000) +#define GXBB_NSDRAM1_SIZE UL(0x00100000) + +#define BL31_BASE UL(0x10100000) +#define BL31_SIZE UL(0x000C0000) +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + +/* Shared memory used for SMC services */ +#define GXBB_SHARE_MEM_INPUT_BASE UL(0x100FE000) +#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x100FF000) + +#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000) +#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000) + +#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000) +#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000) + +#define GXBB_TZRAM_BASE UL(0xD9000000) +#define GXBB_TZRAM_SIZE UL(0x00014000) +/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ + +/* Mailboxes */ +#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) +#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) +#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00) + +#define GXBB_TZROM_BASE UL(0xD9040000) +#define GXBB_TZROM_SIZE UL(0x00010000) + +#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000) +#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000) + +#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000) +#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000) + +/******************************************************************************* + * GIC-400 and interrupt handling related constants + ******************************************************************************/ +#define GXBB_GICD_BASE UL(0xC4301000) +#define GXBB_GICC_BASE UL(0xC4302000) + +#define IRQ_SEC_PHY_TIMER 29 + +#define IRQ_SEC_SGI_0 8 +#define IRQ_SEC_SGI_1 9 +#define IRQ_SEC_SGI_2 10 +#define IRQ_SEC_SGI_3 11 +#define IRQ_SEC_SGI_4 12 +#define IRQ_SEC_SGI_5 13 +#define IRQ_SEC_SGI_6 14 +#define IRQ_SEC_SGI_7 15 + +/******************************************************************************* + * UART definitions + ******************************************************************************/ +#define GXBB_UART0_AO_BASE UL(0xC81004C0) +#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ +#define GXBB_UART_BAUDRATE U(115200) + +/******************************************************************************* + * Memory-mapped I/O Registers + ******************************************************************************/ +#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4) + +#define GXBB_SYS_CPU_CFG7 UL(0xC8834664) + +#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C) + +#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404) +#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408) +#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) +#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428) +#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) +#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430) + +/******************************************************************************* + * System Monitor Call IDs and arguments + ******************************************************************************/ +#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) +#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) + +#define GXBB_SM_EFUSE_READ U(0x82000030) +#define GXBB_SM_EFUSE_USER_MAX U(0x82000033) + +#define GXBB_SM_JTAG_ON U(0x82000040) +#define GXBB_SM_JTAG_OFF U(0x82000041) + +#define GXBB_JTAG_STATE_ON U(0) +#define GXBB_JTAG_STATE_OFF U(1) + +#define GXBB_JTAG_M3_AO U(0) +#define GXBB_JTAG_M3_EE U(1) +#define GXBB_JTAG_A53_AO U(2) +#define GXBB_JTAG_A53_EE U(3) + +#endif /* GXBB_DEF_H */ diff --git a/plat/amlogic/gxbb/gxbb_efuse.c b/plat/amlogic/gxbb/gxbb_efuse.c new file mode 100644 index 000000000..edea5426c --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_efuse.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "gxbb_private.h" + +#define EFUSE_BASE 0x140 +#define EFUSE_SIZE 0xC0 + +uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) +{ + if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) + return 0; + + return scpi_efuse_read(dst, offset + EFUSE_BASE, size); +} + +uint64_t gxbb_efuse_user_max(void) +{ + return EFUSE_SIZE; +} diff --git a/plat/amlogic/gxbb/gxbb_mhu.c b/plat/amlogic/gxbb/gxbb_mhu.c new file mode 100644 index 000000000..903ef411c --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_mhu.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +static DEFINE_BAKERY_LOCK(mhu_lock); + +void mhu_secure_message_start(void) +{ + bakery_lock_get(&mhu_lock); + + while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) + ; +} + +void mhu_secure_message_send(uint32_t msg) +{ + mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg); + + while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) + ; +} + +uint32_t mhu_secure_message_wait(void) +{ + uint32_t val; + + do { + val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0); + } while (val == 0); + + return val; +} + +void mhu_secure_message_end(void) +{ + mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); + + bakery_lock_release(&mhu_lock); +} + +void mhu_secure_init(void) +{ + bakery_lock_init(&mhu_lock); + + mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); +} diff --git a/plat/amlogic/gxbb/gxbb_pm.c b/plat/amlogic/gxbb/gxbb_pm.c new file mode 100644 index 000000000..59b9436fe --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_pm.c @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "gxbb_private.h" + +#define SCPI_POWER_ON 0 +#define SCPI_POWER_RETENTION 1 +#define SCPI_POWER_OFF 3 + +#define SCPI_SYSTEM_SHUTDOWN 0 +#define SCPI_SYSTEM_REBOOT 1 + +static uintptr_t gxbb_sec_entrypoint; +static volatile uint32_t gxbb_cpu0_go; + +static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value) +{ + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); + + mmio_write_64(cpu_mailbox_addr, value); + flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t)); +} + +static void __dead2 gxbb_system_reset(void) +{ + INFO("BL31: PSCI_SYSTEM_RESET\n"); + + uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3); + + NOTICE("BL31: Reboot reason: 0x%x\n", status); + + status &= 0xFFFF0FF0; + + console_flush(); + + mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); + + int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); + + if (ret != 0) { + ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret); + panic(); + } + + wfi(); + + ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n"); + panic(); +} + +static void __dead2 gxbb_system_off(void) +{ + INFO("BL31: PSCI_SYSTEM_OFF\n"); + + unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); + + if (ret != 0) { + ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret); + panic(); + } + + gxbb_program_mailbox(read_mpidr_el1(), 0); + + wfi(); + + ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n"); + panic(); +} + +static int32_t gxbb_pwr_domain_on(u_register_t mpidr) +{ + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + + /* CPU0 can't be turned OFF, emulate it with a WFE loop */ + if (core == GXBB_PRIMARY_CPU) { + VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); + + gxbb_cpu0_go = 1; + flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go)); + dsb(); + isb(); + + sev(); + + return PSCI_E_SUCCESS; + } + + gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint); + scpi_set_css_power_state(mpidr, + SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); + dmbsy(); + sev(); + + return PSCI_E_SUCCESS; +} + +static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + + assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == + PLAT_LOCAL_STATE_OFF); + + if (core == GXBB_PRIMARY_CPU) { + gxbb_cpu0_go = 0; + flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go)); + dsb(); + isb(); + } + + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4); + + mmio_write_32(addr, 0xFFFFFFFF); + flush_dcache_range(addr, sizeof(uint32_t)); + + gicv2_cpuif_disable(); + + /* CPU0 can't be turned OFF, emulate it with a WFE loop */ + if (core == GXBB_PRIMARY_CPU) + return; + + scpi_set_css_power_state(mpidr, + SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); +} + +static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t + *target_state) +{ + unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + + /* CPU0 can't be turned OFF, emulate it with a WFE loop */ + if (core == GXBB_PRIMARY_CPU) { + VERBOSE("BL31: CPU0 entering wait loop...\n"); + + while (gxbb_cpu0_go == 0) + wfe(); + + VERBOSE("BL31: CPU0 resumed.\n"); + + write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT); + } + + dsbsy(); + + for (;;) + wfi(); +} + +/******************************************************************************* + * Platform handlers and setup function. + ******************************************************************************/ +static const plat_psci_ops_t gxbb_ops = { + .pwr_domain_on = gxbb_pwr_domain_on, + .pwr_domain_on_finish = gxbb_pwr_domain_on_finish, + .pwr_domain_off = gxbb_pwr_domain_off, + .pwr_domain_pwr_down_wfi = gxbb_pwr_domain_pwr_down_wfi, + .system_off = gxbb_system_off, + .system_reset = gxbb_system_reset, +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + gxbb_sec_entrypoint = sec_entrypoint; + *psci_ops = &gxbb_ops; + gxbb_cpu0_go = 0; + return 0; +} diff --git a/plat/amlogic/gxbb/gxbb_private.h b/plat/amlogic/gxbb/gxbb_private.h new file mode 100644 index 000000000..910a42c1c --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_private.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GXBB_PRIVATE_H +#define GXBB_PRIVATE_H + +#include + +/* Utility functions */ +unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); +void gxbb_console_init(void); +void gxbb_setup_page_tables(void); + +/* MHU functions */ +void mhu_secure_message_start(void); +void mhu_secure_message_send(uint32_t msg); +uint32_t mhu_secure_message_wait(void); +void mhu_secure_message_end(void); +void mhu_secure_init(void); + +/* SCPI functions */ +void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state); +uint32_t scpi_sys_power_state(uint64_t system_state); +void scpi_jtag_set_state(uint32_t state, uint8_t select); +uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size); +void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3); + +/* Peripherals */ +void gxbb_thermal_unknown(void); +uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size); +uint64_t gxbb_efuse_user_max(void); + +#endif /* GXBB_PRIVATE_H */ diff --git a/plat/amlogic/gxbb/gxbb_scpi.c b/plat/amlogic/gxbb/gxbb_scpi.c new file mode 100644 index 000000000..83eeda29d --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_scpi.c @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include + +#include "gxbb_private.h" + +#define SIZE_SHIFT 20 +#define SIZE_MASK 0x1FF + +/* + * Note: The Amlogic SCP firmware uses the legacy SCPI protocol. + */ +#define SCPI_CMD_SET_CSS_POWER_STATE 0x04 +#define SCPI_CMD_SET_SYS_POWER_STATE 0x08 + +#define SCPI_CMD_JTAG_SET_STATE 0xC0 +#define SCPI_CMD_EFUSE_READ 0xC2 + +static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) +{ + return command | (size << SIZE_SHIFT); +} + +void scpi_secure_message_send(uint32_t command, uint32_t size) +{ + mhu_secure_message_send(scpi_cmd(command, size)); +} + +uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) +{ + uint32_t response = mhu_secure_message_wait(); + + size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; + + response &= ~(SIZE_MASK << SIZE_SHIFT); + + if (size_out != NULL) + *size_out = size; + + if (message_out != NULL) + *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD; + + return response; +} + +void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state) +{ + uint32_t state = (mpidr & 0x0F) | /* CPU ID */ + ((mpidr & 0xF00) >> 4) | /* Cluster ID */ + (cpu_state << 8) | + (cluster_state << 12) | + (css_state << 16); + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} + +uint32_t scpi_sys_power_state(uint64_t system_state) +{ + uint32_t *response; + size_t size; + + mhu_secure_message_start(); + mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); + scpi_secure_message_receive((void *)&response, &size); + mhu_secure_message_end(); + + return *response; +} + +void scpi_jtag_set_state(uint32_t state, uint8_t select) +{ + assert(state <= GXBB_JTAG_STATE_OFF); + + if (select > GXBB_JTAG_A53_EE) { + WARN("BL31: Invalid JTAG select (0x%x).\n", select); + return; + } + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, + (state << 8) | (uint32_t)select); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} + +uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) +{ + uint32_t *response; + size_t resp_size; + + if (size > 0x1FC) + return 0; + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); + scpi_secure_message_receive((void *)&response, &resp_size); + mhu_secure_message_end(); + + /* + * response[0] is the size of the response message. + * response[1 ... N] are the contents. + */ + if (*response != 0) + memcpy(dst, response + 1, *response); + + return *response; +} + +void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3) +{ + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); + mhu_secure_message_send(scpi_cmd(0xC3, 16)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} diff --git a/plat/amlogic/gxbb/gxbb_sip_svc.c b/plat/amlogic/gxbb/gxbb_sip_svc.c new file mode 100644 index 000000000..63c7dba15 --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_sip_svc.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include + +#include "gxbb_private.h" + +/******************************************************************************* + * This function is responsible for handling all SiP calls + ******************************************************************************/ +static uintptr_t gxbb_sip_handler(uint32_t smc_fid, + u_register_t x1, u_register_t x2, + u_register_t x3, u_register_t x4, + void *cookie, void *handle, + u_register_t flags) +{ + switch (smc_fid) { + + case GXBB_SM_GET_SHARE_MEM_INPUT_BASE: + SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE); + + case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE: + SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE); + + case GXBB_SM_EFUSE_READ: + { + void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; + uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2); + + SMC_RET1(handle, ret); + } + case GXBB_SM_EFUSE_USER_MAX: + SMC_RET1(handle, gxbb_efuse_user_max()); + + case GXBB_SM_JTAG_ON: + scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); + SMC_RET1(handle, 0); + + case GXBB_SM_JTAG_OFF: + scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1); + SMC_RET1(handle, 0); + + default: + ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid); + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +DECLARE_RT_SVC( + gxbb_sip_handler, + + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + gxbb_sip_handler +); diff --git a/plat/amlogic/gxbb/gxbb_thermal.c b/plat/amlogic/gxbb/gxbb_thermal.c new file mode 100644 index 000000000..b6048eee4 --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_thermal.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "gxbb_private.h" + +static int32_t modules_initialized = -1; + +/******************************************************************************* + * Unknown commands related to something thermal-related + ******************************************************************************/ +void gxbb_thermal_unknown(void) +{ + uint16_t ret; + + if (modules_initialized == -1) { + scpi_efuse_read(&ret, 0, 2); + modules_initialized = ret; + } + + scpi_unknown_thermal(10, 2, /* thermal */ + 13, 1); /* thermalver */ +} diff --git a/plat/amlogic/gxbb/gxbb_topology.c b/plat/amlogic/gxbb/gxbb_topology.c new file mode 100644 index 000000000..eec2d34d4 --- /dev/null +++ b/plat/amlogic/gxbb/gxbb_topology.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include "gxbb_private.h" + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first node */ + PLATFORM_CLUSTER0_CORE_COUNT +}; + +/******************************************************************************* + * This function returns the ARM default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) + return -1; + + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) + return -1; + + return plat_gxbb_calc_core_pos(mpidr); +} diff --git a/plat/amlogic/gxbb/include/plat_macros.S b/plat/amlogic/gxbb/include/plat_macros.S new file mode 100644 index 000000000..c721c21b6 --- /dev/null +++ b/plat/amlogic/gxbb/include/plat_macros.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include +#include + +.section .rodata.gic_reg_name, "aS" + +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + + /* GICC registers */ + + mov_imm x17, GXBB_GICC_BASE + + adr x6, gicc_regs + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + bl str_in_crash_buf_print + + /* GICD registers */ + + mov_imm x16, GXBB_GICD_BASE + + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str + +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/amlogic/gxbb/include/platform_def.h b/plat/amlogic/gxbb/include/platform_def.h new file mode 100644 index 000000000..da4aedde8 --- /dev/null +++ b/plat/amlogic/gxbb/include/platform_def.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include + +#include "../gxbb_def.h" + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) + +#define PLATFORM_STACK_SIZE UL(0x1000) + +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT + +#define GXBB_PRIMARY_CPU U(0) + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET U(1) +/* Local power state for power-down. Valid for CPU and cluster power domains. */ +#define PLAT_LOCAL_STATE_OFF U(2) + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH U(4) +#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +/* Memory-related defines */ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) + +#define MAX_MMAP_REGIONS 12 +#define MAX_XLAT_TABLES 5 + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk new file mode 100644 index 000000000..06aaaba3f --- /dev/null +++ b/plat/amlogic/gxbb/platform.mk @@ -0,0 +1,69 @@ +# +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include lib/xlat_tables_v2/xlat_tables.mk + +PLAT_INCLUDES := -Iplat/amlogic/gxbb/include + +GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c + +PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ + plat/amlogic/gxbb/gxbb_common.c \ + plat/amlogic/gxbb/gxbb_topology.c \ + ${XLAT_TABLES_LIB_SRCS} + +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + plat/common/plat_psci_common.c \ + plat/amlogic/gxbb/aarch64/gxbb_helpers.S \ + plat/amlogic/gxbb/gxbb_bl31_setup.c \ + plat/amlogic/gxbb/gxbb_efuse.c \ + plat/amlogic/gxbb/gxbb_mhu.c \ + plat/amlogic/gxbb/gxbb_pm.c \ + plat/amlogic/gxbb/gxbb_scpi.c \ + plat/amlogic/gxbb/gxbb_sip_svc.c \ + plat/amlogic/gxbb/gxbb_thermal.c \ + ${GXBB_GIC_SOURCES} + +# Tune compiler for Cortex-A53 +ifeq ($(notdir $(CC)),armclang) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else ifneq ($(findstring clang,$(notdir $(CC))),) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else + TF_CFLAGS_aarch64 += -mtune=cortex-a53 +endif + +# Build config flags +# ------------------ + +# Enable all errata workarounds for Cortex-A53 +ERRATA_A53_826319 := 1 +ERRATA_A53_835769 := 1 +ERRATA_A53_836870 := 1 +ERRATA_A53_843419 := 1 +ERRATA_A53_855873 := 1 + +WORKAROUND_CVE_2017_5715 := 0 + +# Have different sections for code and rodata +SEPARATE_CODE_AND_RODATA := 1 + +# Use Coherent memory +USE_COHERENT_MEM := 1 + +# Verify build config +# ------------------- + +ifneq (${RESET_TO_BL31}, 0) + $(error Error: gxbb needs RESET_TO_BL31=0) +endif + +ifeq (${ARCH},aarch32) + $(error Error: AArch32 not supported on gxbb) +endif diff --git a/plat/amlogic/gxl/aarch64/gxl_helpers.S b/plat/amlogic/gxl/aarch64/gxl_helpers.S new file mode 100644 index 000000000..760d6c46d --- /dev/null +++ b/plat/amlogic/gxl/aarch64/gxl_helpers.S @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + + .globl plat_crash_console_flush + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl platform_mem_init + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_reset_handler + .globl plat_gxbb_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void); + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_gxbb_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); + * ----------------------------------------------------- + */ +func plat_gxbb_calc_core_pos + and x0, x0, #MPIDR_CPU_MASK + ret +endfunc plat_gxbb_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary(void); + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #GXBB_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + + /* --------------------------------------------- + * void platform_mem_init(void); + * --------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, GXBB_UART0_AO_BASE + mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ + mov_imm x2, GXBB_UART_BAUDRATE + b console_meson_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, GXBB_UART0_AO_BASE + b console_meson_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush() + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x0, GXBB_UART0_AO_BASE + b console_meson_core_flush +endfunc plat_crash_console_flush + + /* --------------------------------------------- + * void plat_reset_handler(void); + * --------------------------------------------- + */ +func plat_reset_handler + ret +endfunc plat_reset_handler diff --git a/plat/amlogic/gxl/gxl_bl31_setup.c b/plat/amlogic/gxl/gxl_bl31_setup.c new file mode 100644 index 000000000..b1da7942b --- /dev/null +++ b/plat/amlogic/gxl/gxl_bl31_setup.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gxl_private.h" + +/* + * Placeholder variables for copying the arguments that have been passed to + * BL31 from BL2. + */ +static entry_point_info_t bl33_image_ep_info; +static image_info_t bl30_image_info; +static image_info_t bl301_image_info; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(type == NON_SECURE); + + next_image_info = &bl33_image_ep_info; + + /* None of the images can have 0x0 as the entrypoint. */ + if (next_image_info->pc != 0U) { + return next_image_info; + } else { + return NULL; + } +} + +/******************************************************************************* + * Perform any BL31 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before + * they are lost (potentially). This needs to be done before the MMU is + * initialized so that the memory layout can be used while creating page + * tables. BL2 has flushed this information to memory, so we are guaranteed + * to pick up good data. + ******************************************************************************/ +struct gxl_bl31_param { + param_header_t h; + image_info_t *bl31_image_info; + entry_point_info_t *bl32_ep_info; + image_info_t *bl32_image_info; + entry_point_info_t *bl33_ep_info; + image_info_t *bl33_image_info; + image_info_t *scp_image_info[]; +}; + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + struct gxl_bl31_param *from_bl2; + + /* Initialize the console to provide early debug support */ + gxbb_console_init(); + + /* Check that params passed from BL2 are not NULL. */ + from_bl2 = (struct gxl_bl31_param *) arg0; + + /* Check params passed from BL2 are not NULL. */ + assert(from_bl2 != NULL); + assert(from_bl2->h.type == PARAM_BL31); + assert(from_bl2->h.version >= VERSION_1); + + /* + * Copy BL33 entry point information. It is stored in Secure RAM, in + * BL2's address space. + */ + bl33_image_ep_info = *from_bl2->bl33_ep_info; + + if (bl33_image_ep_info.pc == 0U) { + ERROR("BL31: BL33 entrypoint not obtained from BL2\n"); + panic(); + } + + bl30_image_info = *from_bl2->scp_image_info[0]; + bl301_image_info = *from_bl2->scp_image_info[1]; +} + +void bl31_plat_arch_setup(void) +{ + gxbb_setup_page_tables(); + + enable_mmu_el3(0); +} + +static inline bool gxl_scp_ready(void) +{ + return GXBB_AO_RTI_SCP_IS_READY(mmio_read_32(GXBB_AO_RTI_SCP_STAT)); +} + +static inline void gxl_scp_boot(void) +{ + scpi_upload_scp_fw(bl30_image_info.image_base, + bl30_image_info.image_size, 0); + scpi_upload_scp_fw(bl301_image_info.image_base, + bl301_image_info.image_size, 1); + while (!gxl_scp_ready()) + ; +} + +/******************************************************************************* + * GICv2 driver setup information + ******************************************************************************/ +static const interrupt_prop_t gxbb_interrupt_props[] = { + INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), +}; + +static const gicv2_driver_data_t gxbb_gic_data = { + .gicd_base = GXBB_GICD_BASE, + .gicc_base = GXBB_GICC_BASE, + .interrupt_props = gxbb_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), +}; + +void bl31_platform_setup(void) +{ + mhu_secure_init(); + + gicv2_driver_init(&gxbb_gic_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); + + gxl_scp_boot(); + + gxbb_thermal_unknown(); +} diff --git a/plat/amlogic/gxl/gxl_common.c b/plat/amlogic/gxl/gxl_common.c new file mode 100644 index 000000000..e3bd6048a --- /dev/null +++ b/plat/amlogic/gxl/gxl_common.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Platform memory map regions + ******************************************************************************/ +#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \ + GXBB_NSDRAM0_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \ + GXBB_NSDRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \ + GXBB_SEC_DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \ + GXBB_SEC_DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \ + GXBB_TZRAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \ + GXBB_SEC_DEVICE2_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \ + GXBB_SEC_DEVICE3_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +static const mmap_region_t gxbb_mmap[] = { + MAP_NSDRAM0, + MAP_NSDRAM1, + MAP_SEC_DEVICE0, + MAP_SEC_DEVICE1, + MAP_TZRAM, + MAP_SEC_DEVICE2, + MAP_SEC_DEVICE3, + {0} +}; + +/******************************************************************************* + * Per-image regions + ******************************************************************************/ +#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \ + BL31_END - BL31_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) + +#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \ + BL_RO_DATA_END - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) + +#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/******************************************************************************* + * Function that sets up the translation tables. + ******************************************************************************/ +void gxbb_setup_page_tables(void) +{ +#if IMAGE_BL31 + const mmap_region_t gxbb_bl_mmap[] = { + MAP_BL31, + MAP_BL_CODE, + MAP_BL_RO_DATA, +#if USE_COHERENT_MEM + MAP_BL_COHERENT, +#endif + {0} + }; +#endif + + mmap_add(gxbb_bl_mmap); + + mmap_add(gxbb_mmap); + + init_xlat_tables(); +} + +/******************************************************************************* + * Function that sets up the console + ******************************************************************************/ +static console_meson_t gxbb_console; + +void gxbb_console_init(void) +{ + int rc = console_meson_register(GXBB_UART0_AO_BASE, + GXBB_UART0_AO_CLK_IN_HZ, + GXBB_UART_BAUDRATE, + &gxbb_console); + if (rc == 0) { + /* + * The crash console doesn't use the multi console API, it uses + * the core console functions directly. It is safe to call panic + * and let it print debug information. + */ + panic(); + } + + console_set_scope(&gxbb_console.console, + CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); +} + +/******************************************************************************* + * Function that returns the system counter frequency + ******************************************************************************/ +unsigned int plat_get_syscnt_freq2(void) +{ + uint32_t val; + + val = mmio_read_32(GXBB_SYS_CPU_CFG7); + val &= 0xFDFFFFFF; + mmio_write_32(GXBB_SYS_CPU_CFG7, val); + + val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL); + val &= 0xFFFFFE00; + mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val); + + return GXBB_OSC24M_CLK_IN_HZ; +} diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h new file mode 100644 index 000000000..089fa8db9 --- /dev/null +++ b/plat/amlogic/gxl/gxl_def.h @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GXBB_DEF_H +#define GXBB_DEF_H + +#include + +/******************************************************************************* + * System oscillator + ******************************************************************************/ +#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ + +/******************************************************************************* + * Memory regions + ******************************************************************************/ +#define GXBB_NSDRAM0_BASE UL(0x01000000) +#define GXBB_NSDRAM0_SIZE UL(0x0F000000) + +#define GXBB_NSDRAM1_BASE UL(0x10000000) +#define GXBB_NSDRAM1_SIZE UL(0x00100000) + +#define BL31_BASE UL(0x05100000) +#define BL31_SIZE UL(0x000C0000) +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + +/* Shared memory used for SMC services */ +#define GXBB_SHARE_MEM_INPUT_BASE UL(0x050FE000) +#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x050FF000) + +#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000) +#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000) + +#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000) +#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000) + +#define GXBB_TZRAM_BASE UL(0xD9000000) +#define GXBB_TZRAM_SIZE UL(0x00014000) +/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ + +/* Mailboxes */ +#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) +#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) +#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00) + +// * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) +// * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * +// * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) * + +#define GXBB_TZROM_BASE UL(0xD9040000) +#define GXBB_TZROM_SIZE UL(0x00010000) + +#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000) +#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000) + +#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000) +#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000) + +/******************************************************************************* + * GIC-400 and interrupt handling related constants + ******************************************************************************/ +#define GXBB_GICD_BASE UL(0xC4301000) +#define GXBB_GICC_BASE UL(0xC4302000) + +#define IRQ_SEC_PHY_TIMER 29 + +#define IRQ_SEC_SGI_0 8 +#define IRQ_SEC_SGI_1 9 +#define IRQ_SEC_SGI_2 10 +#define IRQ_SEC_SGI_3 11 +#define IRQ_SEC_SGI_4 12 +#define IRQ_SEC_SGI_5 13 +#define IRQ_SEC_SGI_6 14 +#define IRQ_SEC_SGI_7 15 + +/******************************************************************************* + * UART definitions + ******************************************************************************/ +#define GXBB_UART0_AO_BASE UL(0xC81004C0) +#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ +#define GXBB_UART_BAUDRATE U(115200) + +/******************************************************************************* + * Memory-mapped I/O Registers + ******************************************************************************/ +#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4) + +#define GXBB_SYS_CPU_CFG7 UL(0xC8834664) + +#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C) +#define GXBB_AO_RTI_SCP_STAT UL(0xDA10023C) +#define GXBB_AO_RTI_SCP_READY_OFF U(0x14) +#define GXBB_A0_RTI_SCP_READY_MASK U(3) +#define GXBB_AO_RTI_SCP_IS_READY(v) \ + ((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \ + GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK) + +#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404) +#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408) +#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) +#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428) +#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) +#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430) + +/******************************************************************************* + * System Monitor Call IDs and arguments + ******************************************************************************/ +#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) +#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) + +#define GXBB_SM_EFUSE_READ U(0x82000030) +#define GXBB_SM_EFUSE_USER_MAX U(0x82000033) + +#define GXBB_SM_JTAG_ON U(0x82000040) +#define GXBB_SM_JTAG_OFF U(0x82000041) + +#define GXBB_JTAG_STATE_ON U(0) +#define GXBB_JTAG_STATE_OFF U(1) + +#define GXBB_JTAG_M3_AO U(0) +#define GXBB_JTAG_M3_EE U(1) +#define GXBB_JTAG_A53_AO U(2) +#define GXBB_JTAG_A53_EE U(3) + +#endif /* GXBB_DEF_H */ diff --git a/plat/amlogic/gxl/gxl_efuse.c b/plat/amlogic/gxl/gxl_efuse.c new file mode 100644 index 000000000..b17d1b8e3 --- /dev/null +++ b/plat/amlogic/gxl/gxl_efuse.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "gxl_private.h" + +#define EFUSE_BASE 0x140 +#define EFUSE_SIZE 0xC0 + +uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) +{ + if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) + return 0; + + return scpi_efuse_read(dst, offset + EFUSE_BASE, size); +} + +uint64_t gxbb_efuse_user_max(void) +{ + return EFUSE_SIZE; +} diff --git a/plat/amlogic/gxl/gxl_mhu.c b/plat/amlogic/gxl/gxl_mhu.c new file mode 100644 index 000000000..4c1d5b600 --- /dev/null +++ b/plat/amlogic/gxl/gxl_mhu.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +static DEFINE_BAKERY_LOCK(mhu_lock); + +void mhu_secure_message_start(void) +{ + bakery_lock_get(&mhu_lock); + + while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) + ; +} + +void mhu_secure_message_send(uint32_t msg) +{ + mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg); + + while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) + ; +} + +uint32_t mhu_secure_message_wait(void) +{ + uint32_t val; + + do { + val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0); + } while (val == 0); + + return val; +} + +void mhu_secure_message_end(void) +{ + mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); + + bakery_lock_release(&mhu_lock); +} + +void mhu_secure_init(void) +{ + bakery_lock_init(&mhu_lock); + + mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); +} diff --git a/plat/amlogic/gxl/gxl_pm.c b/plat/amlogic/gxl/gxl_pm.c new file mode 100644 index 000000000..4a5d26e90 --- /dev/null +++ b/plat/amlogic/gxl/gxl_pm.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gxl_private.h" + +#define SCPI_POWER_ON 0 +#define SCPI_POWER_RETENTION 1 +#define SCPI_POWER_OFF 3 + +#define SCPI_SYSTEM_SHUTDOWN 0 +#define SCPI_SYSTEM_REBOOT 1 + +static uintptr_t gxbb_sec_entrypoint; +static volatile uint32_t gxbb_cpu0_go; + +static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value) +{ + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); + + mmio_write_64(cpu_mailbox_addr, value); +} + +static void gxl_pm_reset(u_register_t mpidr) +{ + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8; + + mmio_write_32(cpu_mailbox_addr, 0); +} + +static void __dead2 gxbb_system_reset(void) +{ + INFO("BL31: PSCI_SYSTEM_RESET\n"); + + u_register_t mpidr = read_mpidr_el1(); + uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3); + int ret; + + NOTICE("BL31: Reboot reason: 0x%x\n", status); + + status &= 0xFFFF0FF0; + + console_flush(); + + mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); + + ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); + + if (ret != 0) { + ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret); + panic(); + } + + gxl_pm_reset(mpidr); + + wfi(); + + ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n"); + panic(); +} + +static void __dead2 gxbb_system_off(void) +{ + INFO("BL31: PSCI_SYSTEM_OFF\n"); + + u_register_t mpidr = read_mpidr_el1(); + int ret; + + ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); + + if (ret != 0) { + ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret); + panic(); + } + + gxl_pm_set_reset_addr(mpidr, 0); + gxl_pm_reset(mpidr); + + wfi(); + + ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n"); + panic(); +} + +static int32_t gxbb_pwr_domain_on(u_register_t mpidr) +{ + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + + /* CPU0 can't be turned OFF, emulate it with a WFE loop */ + if (core == GXBB_PRIMARY_CPU) { + VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); + + gxbb_cpu0_go = 1; + flush_dcache_range((uintptr_t)&gxbb_cpu0_go, + sizeof(gxbb_cpu0_go)); + dsb(); + isb(); + + sev(); + + return PSCI_E_SUCCESS; + } + + gxl_pm_set_reset_addr(mpidr, gxbb_sec_entrypoint); + scpi_set_css_power_state(mpidr, + SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); + dmbsy(); + sev(); + + return PSCI_E_SUCCESS; +} + +static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + + assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == + PLAT_LOCAL_STATE_OFF); + + if (core == GXBB_PRIMARY_CPU) { + gxbb_cpu0_go = 0; + flush_dcache_range((uintptr_t)&gxbb_cpu0_go, + sizeof(gxbb_cpu0_go)); + dsb(); + isb(); + } + + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + + gicv2_cpuif_disable(); + + /* CPU0 can't be turned OFF, emulate it with a WFE loop */ + if (core == GXBB_PRIMARY_CPU) + return; + + scpi_set_css_power_state(mpidr, + SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); +} + +static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t + *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + + /* CPU0 can't be turned OFF, emulate it with a WFE loop */ + if (core == GXBB_PRIMARY_CPU) { + VERBOSE("BL31: CPU0 entering wait loop...\n"); + + while (gxbb_cpu0_go == 0) + wfe(); + + VERBOSE("BL31: CPU0 resumed.\n"); + + /* + * Because setting CPU0's warm reset entrypoint through PSCI + * mailbox and/or mmio mapped RVBAR (0xda834650) does not seem + * to work, jump to it manually. + * In order to avoid an assert, mmu has to be disabled. + */ + disable_mmu_el3(); + ((void(*)(void))gxbb_sec_entrypoint)(); + } + + dsbsy(); + gxl_pm_set_reset_addr(mpidr, 0); + gxl_pm_reset(mpidr); + + for (;;) + wfi(); +} + +/******************************************************************************* + * Platform handlers and setup function. + ******************************************************************************/ +static const plat_psci_ops_t gxbb_ops = { + .pwr_domain_on = gxbb_pwr_domain_on, + .pwr_domain_on_finish = gxbb_pwr_domain_on_finish, + .pwr_domain_off = gxbb_pwr_domain_off, + .pwr_domain_pwr_down_wfi = gxbb_pwr_domain_pwr_down_wfi, + .system_off = gxbb_system_off, + .system_reset = gxbb_system_reset, +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + gxbb_sec_entrypoint = sec_entrypoint; + *psci_ops = &gxbb_ops; + gxbb_cpu0_go = 0; + return 0; +} diff --git a/plat/amlogic/gxl/gxl_private.h b/plat/amlogic/gxl/gxl_private.h new file mode 100644 index 000000000..913cbf653 --- /dev/null +++ b/plat/amlogic/gxl/gxl_private.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GXBB_PRIVATE_H +#define GXBB_PRIVATE_H + +#include +#include + +/* Utility functions */ +unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); +void gxbb_console_init(void); +void gxbb_setup_page_tables(void); + +/* MHU functions */ +void mhu_secure_message_start(void); +void mhu_secure_message_send(uint32_t msg); +uint32_t mhu_secure_message_wait(void); +void mhu_secure_message_end(void); +void mhu_secure_init(void); + +/* SCPI functions */ +void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state); +uint32_t scpi_sys_power_state(uint64_t system_state); +void scpi_jtag_set_state(uint32_t state, uint8_t select); +uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size); +void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3); +void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); + +/* Peripherals */ +void gxbb_thermal_unknown(void); +uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size); +uint64_t gxbb_efuse_user_max(void); + +#endif /* GXBB_PRIVATE_H */ diff --git a/plat/amlogic/gxl/gxl_scpi.c b/plat/amlogic/gxl/gxl_scpi.c new file mode 100644 index 000000000..13d652436 --- /dev/null +++ b/plat/amlogic/gxl/gxl_scpi.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +#include "gxl_private.h" + +#define SIZE_SHIFT 20 +#define SIZE_MASK 0x1FF +#define SIZE_FWBLK 0x200UL + +/* + * Note: The Amlogic SCP firmware uses the legacy SCPI protocol. + */ +#define SCPI_CMD_SET_CSS_POWER_STATE 0x04 +#define SCPI_CMD_SET_SYS_POWER_STATE 0x08 + +#define SCPI_CMD_JTAG_SET_STATE 0xC0 +#define SCPI_CMD_EFUSE_READ 0xC2 + +#define SCPI_CMD_COPY_FW 0xd4 +#define SCPI_CMD_SET_FW_ADDR 0xd3 +#define SCPI_CMD_FW_SIZE 0xd2 + +static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) +{ + return command | (size << SIZE_SHIFT); +} + +static void scpi_secure_message_send(uint32_t command, uint32_t size) +{ + mhu_secure_message_send(scpi_cmd(command, size)); +} + +uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) +{ + uint32_t response = mhu_secure_message_wait(); + + size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; + + response &= ~(SIZE_MASK << SIZE_SHIFT); + + if (size_out != NULL) + *size_out = size; + + if (message_out != NULL) + *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD; + + return response; +} + +void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state) +{ + uint32_t state = (mpidr & 0x0F) | /* CPU ID */ + ((mpidr & 0xF00) >> 4) | /* Cluster ID */ + (cpu_state << 8) | + (cluster_state << 12) | + (css_state << 16); + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} + +uint32_t scpi_sys_power_state(uint64_t system_state) +{ + uint32_t *response; + size_t size; + + mhu_secure_message_start(); + mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); + scpi_secure_message_receive((void *)&response, &size); + mhu_secure_message_end(); + + return *response; +} + +void scpi_jtag_set_state(uint32_t state, uint8_t select) +{ + assert(state <= GXBB_JTAG_STATE_OFF); + + if (select > GXBB_JTAG_A53_EE) { + WARN("BL31: Invalid JTAG select (0x%x).\n", select); + return; + } + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, + (state << 8) | (uint32_t)select); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} + +uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) +{ + uint32_t *response; + size_t resp_size; + + if (size > 0x1FC) + return 0; + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); + scpi_secure_message_receive((void *)&response, &resp_size); + mhu_secure_message_end(); + + /* + * response[0] is the size of the response message. + * response[1 ... N] are the contents. + */ + if (*response != 0) + memcpy(dst, response + 1, *response); + + return *response; +} + +void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3) +{ + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); + mhu_secure_message_send(scpi_cmd(0xC3, 16)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} + +static inline void scpi_copy_scp_data(uint8_t *data, size_t len) +{ + void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + size_t sz; + + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); + scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); + mhu_secure_message_wait(); + + for (sz = 0; sz < len; sz += SIZE_FWBLK) { + memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz)); + mhu_secure_message_send(SCPI_CMD_COPY_FW); + } +} + +static inline void scpi_set_scp_addr(uint64_t addr, size_t len) +{ + volatile uint64_t *dst = (uint64_t *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + + /* + * It is ok as GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as + * non cachable + */ + *dst = addr; + scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr)); + mhu_secure_message_wait(); + + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); + scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); + mhu_secure_message_wait(); +} + +static inline void scpi_send_fw_hash(uint8_t hash[], size_t len) +{ + void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + + memcpy(dst, hash, len); + mhu_secure_message_send(0xd0); + mhu_secure_message_send(0xd1); + mhu_secure_message_send(0xd5); + mhu_secure_message_end(); +} + +/** + * Upload a FW to SCP. + * + * @param addr: firmware data address + * @param size: size of firmware + * @param send: If set, actually copy the firmware in SCP memory otherwise only + * send the firmware address. + */ +void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send) +{ + struct asd_ctx ctx; + + asd_sha_init(&ctx, ASM_SHA256); + asd_sha_update(&ctx, (void *)addr, size); + asd_sha_finalize(&ctx); + + mhu_secure_message_start(); + if (send == 0) + scpi_set_scp_addr(addr, size); + else + scpi_copy_scp_data((void *)addr, size); + + scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest)); +} diff --git a/plat/amlogic/gxl/gxl_sip_svc.c b/plat/amlogic/gxl/gxl_sip_svc.c new file mode 100644 index 000000000..74fbc80e4 --- /dev/null +++ b/plat/amlogic/gxl/gxl_sip_svc.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#include "gxl_private.h" + +/******************************************************************************* + * This function is responsible for handling all SiP calls + ******************************************************************************/ +static uintptr_t gxbb_sip_handler(uint32_t smc_fid, + u_register_t x1, u_register_t x2, + u_register_t x3, u_register_t x4, + void *cookie, void *handle, + u_register_t flags) +{ + switch (smc_fid) { + + case GXBB_SM_GET_SHARE_MEM_INPUT_BASE: + SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE); + + case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE: + SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE); + + case GXBB_SM_EFUSE_READ: + { + void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; + uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2); + + SMC_RET1(handle, ret); + } + case GXBB_SM_EFUSE_USER_MAX: + SMC_RET1(handle, gxbb_efuse_user_max()); + + case GXBB_SM_JTAG_ON: + scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); + SMC_RET1(handle, 0); + + case GXBB_SM_JTAG_OFF: + scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1); + SMC_RET1(handle, 0); + + default: + ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid); + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +DECLARE_RT_SVC( + gxbb_sip_handler, + + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + gxbb_sip_handler +); diff --git a/plat/amlogic/gxl/gxl_thermal.c b/plat/amlogic/gxl/gxl_thermal.c new file mode 100644 index 000000000..3af1c6dc6 --- /dev/null +++ b/plat/amlogic/gxl/gxl_thermal.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "gxl_private.h" + +static int32_t modules_initialized = -1; + +/******************************************************************************* + * Unknown commands related to something thermal-related + ******************************************************************************/ +void gxbb_thermal_unknown(void) +{ + uint16_t ret; + + if (modules_initialized == -1) { + scpi_efuse_read(&ret, 0, 2); + modules_initialized = ret; + } + + scpi_unknown_thermal(10, 2, /* thermal */ + 13, 1); /* thermalver */ +} diff --git a/plat/amlogic/gxl/gxl_topology.c b/plat/amlogic/gxl/gxl_topology.c new file mode 100644 index 000000000..cca3ead50 --- /dev/null +++ b/plat/amlogic/gxl/gxl_topology.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include "gxl_private.h" + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first node */ + PLATFORM_CLUSTER0_CORE_COUNT +}; + +/******************************************************************************* + * This function returns the ARM default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) + return -1; + + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) + return -1; + + return plat_gxbb_calc_core_pos(mpidr); +} diff --git a/plat/amlogic/gxl/include/plat_macros.S b/plat/amlogic/gxl/include/plat_macros.S new file mode 100644 index 000000000..c721c21b6 --- /dev/null +++ b/plat/amlogic/gxl/include/plat_macros.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include +#include + +.section .rodata.gic_reg_name, "aS" + +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + + /* GICC registers */ + + mov_imm x17, GXBB_GICC_BASE + + adr x6, gicc_regs + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + bl str_in_crash_buf_print + + /* GICD registers */ + + mov_imm x16, GXBB_GICD_BASE + + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str + +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/amlogic/gxl/include/platform_def.h b/plat/amlogic/gxl/include/platform_def.h new file mode 100644 index 000000000..b32ec56da --- /dev/null +++ b/plat/amlogic/gxl/include/platform_def.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include + +#include "../gxl_def.h" + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) + +#define PLATFORM_STACK_SIZE UL(0x1000) + +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT + +#define GXBB_PRIMARY_CPU U(0) + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET U(1) +/* Local power state for power-down. Valid for CPU and cluster power domains. */ +#define PLAT_LOCAL_STATE_OFF U(2) + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH U(4) +#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +/* Memory-related defines */ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) + +#define MAX_MMAP_REGIONS 12 +#define MAX_XLAT_TABLES 6 + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk new file mode 100644 index 000000000..9cdf37ac9 --- /dev/null +++ b/plat/amlogic/gxl/platform.mk @@ -0,0 +1,87 @@ +# +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include lib/xlat_tables_v2/xlat_tables.mk + +DOIMAGEPATH ?= tools/amlogic +DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage + +PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ + -Iinclude/drivers/amlogic/gxl \ + -Iplat/amlogic/gxl/include + +GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c + +PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ + plat/amlogic/gxl/gxl_common.c \ + plat/amlogic/gxl/gxl_topology.c \ + ${XLAT_TABLES_LIB_SRCS} + +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + plat/common/plat_psci_common.c \ + plat/amlogic/gxl/aarch64/gxl_helpers.S \ + plat/amlogic/gxl/gxl_bl31_setup.c \ + plat/amlogic/gxl/gxl_efuse.c \ + plat/amlogic/gxl/gxl_mhu.c \ + plat/amlogic/gxl/gxl_pm.c \ + plat/amlogic/gxl/gxl_scpi.c \ + plat/amlogic/gxl/gxl_sip_svc.c \ + plat/amlogic/gxl/gxl_thermal.c \ + drivers/amlogic/gxl/crypto/sha_dma.c \ + ${GXBB_GIC_SOURCES} + +# Tune compiler for Cortex-A53 +ifeq ($(notdir $(CC)),armclang) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else ifneq ($(findstring clang,$(notdir $(CC))),) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else + TF_CFLAGS_aarch64 += -mtune=cortex-a53 +endif + +# Build config flags +# ------------------ + +# Enable all errata workarounds for Cortex-A53 +ERRATA_A53_855873 := 1 +ERRATA_A53_819472 := 1 +ERRATA_A53_824069 := 1 +ERRATA_A53_827319 := 1 + +WORKAROUND_CVE_2017_5715 := 0 + +# Have different sections for code and rodata +SEPARATE_CODE_AND_RODATA := 1 + +# Use Coherent memory +USE_COHERENT_MEM := 1 + +# Verify build config +# ------------------- + +ifneq (${RESET_TO_BL31}, 0) + $(error Error: gxl needs RESET_TO_BL31=0) +endif + +ifeq (${ARCH},aarch32) + $(error Error: AArch32 not supported on gxl) +endif + +all: ${BUILD_PLAT}/bl31.img +distclean realclean clean: cleanimage + +cleanimage: + ${Q}${MAKE} -C ${DOIMAGEPATH} clean + +${DOIMAGETOOL}: + ${Q}${MAKE} -C ${DOIMAGEPATH} + +${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL} + ${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img + diff --git a/plat/meson/gxbb/aarch64/gxbb_helpers.S b/plat/meson/gxbb/aarch64/gxbb_helpers.S deleted file mode 100644 index 760d6c46d..000000000 --- a/plat/meson/gxbb/aarch64/gxbb_helpers.S +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - - .globl plat_crash_console_flush - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl platform_mem_init - .globl plat_is_my_cpu_primary - .globl plat_my_core_pos - .globl plat_reset_handler - .globl plat_gxbb_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_my_core_pos(void); - * ----------------------------------------------------- - */ -func plat_my_core_pos - mrs x0, mpidr_el1 - b plat_gxbb_calc_core_pos -endfunc plat_my_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); - * ----------------------------------------------------- - */ -func plat_gxbb_calc_core_pos - and x0, x0, #MPIDR_CPU_MASK - ret -endfunc plat_gxbb_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_is_my_cpu_primary(void); - * ----------------------------------------------------- - */ -func plat_is_my_cpu_primary - mrs x0, mpidr_el1 - and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #GXBB_PRIMARY_CPU - cset w0, eq - ret -endfunc plat_is_my_cpu_primary - - /* --------------------------------------------- - * void platform_mem_init(void); - * --------------------------------------------- - */ -func platform_mem_init - ret -endfunc platform_mem_init - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, GXBB_UART0_AO_BASE - mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ - mov_imm x2, GXBB_UART_BAUDRATE - b console_meson_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(int c) - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, GXBB_UART0_AO_BASE - b console_meson_core_putc -endfunc plat_crash_console_putc - - /* --------------------------------------------- - * int plat_crash_console_flush() - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func plat_crash_console_flush - mov_imm x0, GXBB_UART0_AO_BASE - b console_meson_core_flush -endfunc plat_crash_console_flush - - /* --------------------------------------------- - * void plat_reset_handler(void); - * --------------------------------------------- - */ -func plat_reset_handler - ret -endfunc plat_reset_handler diff --git a/plat/meson/gxbb/gxbb_bl31_setup.c b/plat/meson/gxbb/gxbb_bl31_setup.c deleted file mode 100644 index b867a5846..000000000 --- a/plat/meson/gxbb/gxbb_bl31_setup.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include -#include -#include - -#include "gxbb_private.h" - -/* - * Placeholder variables for copying the arguments that have been passed to - * BL31 from BL2. - */ -static entry_point_info_t bl33_image_ep_info; - -/******************************************************************************* - * Return a pointer to the 'entry_point_info' structure of the next image for - * the security state specified. BL33 corresponds to the non-secure image type - * while BL32 corresponds to the secure image type. A NULL pointer is returned - * if the image does not exist. - ******************************************************************************/ -entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) -{ - entry_point_info_t *next_image_info; - - assert(type == NON_SECURE); - - next_image_info = &bl33_image_ep_info; - - /* None of the images can have 0x0 as the entrypoint. */ - if (next_image_info->pc != 0U) { - return next_image_info; - } else { - return NULL; - } -} - -/******************************************************************************* - * Perform any BL31 early platform setup. Here is an opportunity to copy - * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before - * they are lost (potentially). This needs to be done before the MMU is - * initialized so that the memory layout can be used while creating page - * tables. BL2 has flushed this information to memory, so we are guaranteed - * to pick up good data. - ******************************************************************************/ -struct gxbb_bl31_param { - param_header_t h; - image_info_t *bl31_image_info; - entry_point_info_t *bl32_ep_info; - image_info_t *bl32_image_info; - entry_point_info_t *bl33_ep_info; - image_info_t *bl33_image_info; -}; - -void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, - u_register_t arg2, u_register_t arg3) -{ - struct gxbb_bl31_param *from_bl2; - - /* Initialize the console to provide early debug support */ - gxbb_console_init(); - - /* - * In debug builds, we pass a special value in 'arg1' to verify platform - * parameters from BL2 to BL31. In release builds it's not used. - */ - assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL); - - /* Check that params passed from BL2 are not NULL. */ - from_bl2 = (struct gxbb_bl31_param *) arg0; - - /* Check params passed from BL2 are not NULL. */ - assert(from_bl2 != NULL); - assert(from_bl2->h.type == PARAM_BL31); - assert(from_bl2->h.version >= VERSION_1); - - /* - * Copy BL33 entry point information. It is stored in Secure RAM, in - * BL2's address space. - */ - bl33_image_ep_info = *from_bl2->bl33_ep_info; - - if (bl33_image_ep_info.pc == 0U) { - ERROR("BL31: BL33 entrypoint not obtained from BL2\n"); - panic(); - } -} - -void bl31_plat_arch_setup(void) -{ - gxbb_setup_page_tables(); - - enable_mmu_el3(0); -} - -/******************************************************************************* - * GICv2 driver setup information - ******************************************************************************/ -static const interrupt_prop_t gxbb_interrupt_props[] = { - INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), -}; - -static const gicv2_driver_data_t gxbb_gic_data = { - .gicd_base = GXBB_GICD_BASE, - .gicc_base = GXBB_GICC_BASE, - .interrupt_props = gxbb_interrupt_props, - .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), -}; - -void bl31_platform_setup(void) -{ - mhu_secure_init(); - - gicv2_driver_init(&gxbb_gic_data); - gicv2_distif_init(); - gicv2_pcpu_distif_init(); - gicv2_cpuif_enable(); - - gxbb_thermal_unknown(); -} diff --git a/plat/meson/gxbb/gxbb_common.c b/plat/meson/gxbb/gxbb_common.c deleted file mode 100644 index 0ca15e860..000000000 --- a/plat/meson/gxbb/gxbb_common.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - -/******************************************************************************* - * Platform memory map regions - ******************************************************************************/ -#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \ - GXBB_NSDRAM0_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \ - GXBB_NSDRAM1_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \ - GXBB_SEC_DEVICE0_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \ - GXBB_SEC_DEVICE1_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \ - GXBB_TZRAM_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \ - GXBB_SEC_DEVICE2_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \ - GXBB_SEC_DEVICE3_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -static const mmap_region_t gxbb_mmap[] = { - MAP_NSDRAM0, - MAP_NSDRAM1, - MAP_SEC_DEVICE0, - MAP_SEC_DEVICE1, - MAP_TZRAM, - MAP_SEC_DEVICE2, - MAP_SEC_DEVICE3, - {0} -}; - -/******************************************************************************* - * Per-image regions - ******************************************************************************/ -#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \ - BL31_END - BL31_BASE, \ - MT_MEMORY | MT_RW | MT_SECURE) - -#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \ - BL_CODE_END - BL_CODE_BASE, \ - MT_CODE | MT_SECURE) - -#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \ - BL_RO_DATA_END - BL_RO_DATA_BASE, \ - MT_RO_DATA | MT_SECURE) - -#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \ - BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -/******************************************************************************* - * Function that sets up the translation tables. - ******************************************************************************/ -void gxbb_setup_page_tables(void) -{ -#if IMAGE_BL31 - const mmap_region_t gxbb_bl_mmap[] = { - MAP_BL31, - MAP_BL_CODE, - MAP_BL_RO_DATA, -#if USE_COHERENT_MEM - MAP_BL_COHERENT, -#endif - {0} - }; -#endif - - mmap_add(gxbb_bl_mmap); - - mmap_add(gxbb_mmap); - - init_xlat_tables(); -} - -/******************************************************************************* - * Function that sets up the console - ******************************************************************************/ -static console_meson_t gxbb_console; - -void gxbb_console_init(void) -{ - int rc = console_meson_register(GXBB_UART0_AO_BASE, - GXBB_UART0_AO_CLK_IN_HZ, - GXBB_UART_BAUDRATE, - &gxbb_console); - if (rc == 0) { - /* - * The crash console doesn't use the multi console API, it uses - * the core console functions directly. It is safe to call panic - * and let it print debug information. - */ - panic(); - } - - console_set_scope(&gxbb_console.console, - CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); -} - -/******************************************************************************* - * Function that returns the system counter frequency - ******************************************************************************/ -unsigned int plat_get_syscnt_freq2(void) -{ - uint32_t val; - - val = mmio_read_32(GXBB_SYS_CPU_CFG7); - val &= 0xFDFFFFFF; - mmio_write_32(GXBB_SYS_CPU_CFG7, val); - - val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL); - val &= 0xFFFFFE00; - mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val); - - return GXBB_OSC24M_CLK_IN_HZ; -} diff --git a/plat/meson/gxbb/gxbb_def.h b/plat/meson/gxbb/gxbb_def.h deleted file mode 100644 index 3e27097c3..000000000 --- a/plat/meson/gxbb/gxbb_def.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef GXBB_DEF_H -#define GXBB_DEF_H - -#include - -/******************************************************************************* - * System oscillator - ******************************************************************************/ -#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ - -/******************************************************************************* - * Memory regions - ******************************************************************************/ -#define GXBB_NSDRAM0_BASE UL(0x01000000) -#define GXBB_NSDRAM0_SIZE UL(0x0F000000) - -#define GXBB_NSDRAM1_BASE UL(0x10000000) -#define GXBB_NSDRAM1_SIZE UL(0x00100000) - -#define BL31_BASE UL(0x10100000) -#define BL31_SIZE UL(0x000C0000) -#define BL31_LIMIT (BL31_BASE + BL31_SIZE) - -/* Shared memory used for SMC services */ -#define GXBB_SHARE_MEM_INPUT_BASE UL(0x100FE000) -#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x100FF000) - -#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000) -#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000) - -#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000) -#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000) - -#define GXBB_TZRAM_BASE UL(0xD9000000) -#define GXBB_TZRAM_SIZE UL(0x00014000) -/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ - -/* Mailboxes */ -#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) -#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) -#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00) - -#define GXBB_TZROM_BASE UL(0xD9040000) -#define GXBB_TZROM_SIZE UL(0x00010000) - -#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000) -#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000) - -#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000) -#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000) - -/******************************************************************************* - * GIC-400 and interrupt handling related constants - ******************************************************************************/ -#define GXBB_GICD_BASE UL(0xC4301000) -#define GXBB_GICC_BASE UL(0xC4302000) - -#define IRQ_SEC_PHY_TIMER 29 - -#define IRQ_SEC_SGI_0 8 -#define IRQ_SEC_SGI_1 9 -#define IRQ_SEC_SGI_2 10 -#define IRQ_SEC_SGI_3 11 -#define IRQ_SEC_SGI_4 12 -#define IRQ_SEC_SGI_5 13 -#define IRQ_SEC_SGI_6 14 -#define IRQ_SEC_SGI_7 15 - -/******************************************************************************* - * UART definitions - ******************************************************************************/ -#define GXBB_UART0_AO_BASE UL(0xC81004C0) -#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ -#define GXBB_UART_BAUDRATE U(115200) - -/******************************************************************************* - * Memory-mapped I/O Registers - ******************************************************************************/ -#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4) - -#define GXBB_SYS_CPU_CFG7 UL(0xC8834664) - -#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C) - -#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404) -#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408) -#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) -#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428) -#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) -#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430) - -/******************************************************************************* - * System Monitor Call IDs and arguments - ******************************************************************************/ -#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) -#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) - -#define GXBB_SM_EFUSE_READ U(0x82000030) -#define GXBB_SM_EFUSE_USER_MAX U(0x82000033) - -#define GXBB_SM_JTAG_ON U(0x82000040) -#define GXBB_SM_JTAG_OFF U(0x82000041) - -#define GXBB_JTAG_STATE_ON U(0) -#define GXBB_JTAG_STATE_OFF U(1) - -#define GXBB_JTAG_M3_AO U(0) -#define GXBB_JTAG_M3_EE U(1) -#define GXBB_JTAG_A53_AO U(2) -#define GXBB_JTAG_A53_EE U(3) - -#endif /* GXBB_DEF_H */ diff --git a/plat/meson/gxbb/gxbb_efuse.c b/plat/meson/gxbb/gxbb_efuse.c deleted file mode 100644 index edea5426c..000000000 --- a/plat/meson/gxbb/gxbb_efuse.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include "gxbb_private.h" - -#define EFUSE_BASE 0x140 -#define EFUSE_SIZE 0xC0 - -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) -{ - if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) - return 0; - - return scpi_efuse_read(dst, offset + EFUSE_BASE, size); -} - -uint64_t gxbb_efuse_user_max(void) -{ - return EFUSE_SIZE; -} diff --git a/plat/meson/gxbb/gxbb_mhu.c b/plat/meson/gxbb/gxbb_mhu.c deleted file mode 100644 index 903ef411c..000000000 --- a/plat/meson/gxbb/gxbb_mhu.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -static DEFINE_BAKERY_LOCK(mhu_lock); - -void mhu_secure_message_start(void) -{ - bakery_lock_get(&mhu_lock); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -void mhu_secure_message_send(uint32_t msg) -{ - mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -uint32_t mhu_secure_message_wait(void) -{ - uint32_t val; - - do { - val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0); - } while (val == 0); - - return val; -} - -void mhu_secure_message_end(void) -{ - mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); - - bakery_lock_release(&mhu_lock); -} - -void mhu_secure_init(void) -{ - bakery_lock_init(&mhu_lock); - - mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); -} diff --git a/plat/meson/gxbb/gxbb_pm.c b/plat/meson/gxbb/gxbb_pm.c deleted file mode 100644 index 59b9436fe..000000000 --- a/plat/meson/gxbb/gxbb_pm.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "gxbb_private.h" - -#define SCPI_POWER_ON 0 -#define SCPI_POWER_RETENTION 1 -#define SCPI_POWER_OFF 3 - -#define SCPI_SYSTEM_SHUTDOWN 0 -#define SCPI_SYSTEM_REBOOT 1 - -static uintptr_t gxbb_sec_entrypoint; -static volatile uint32_t gxbb_cpu0_go; - -static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value) -{ - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); - - mmio_write_64(cpu_mailbox_addr, value); - flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t)); -} - -static void __dead2 gxbb_system_reset(void) -{ - INFO("BL31: PSCI_SYSTEM_RESET\n"); - - uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3); - - NOTICE("BL31: Reboot reason: 0x%x\n", status); - - status &= 0xFFFF0FF0; - - console_flush(); - - mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); - - int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); - - if (ret != 0) { - ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret); - panic(); - } - - wfi(); - - ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n"); - panic(); -} - -static void __dead2 gxbb_system_off(void) -{ - INFO("BL31: PSCI_SYSTEM_OFF\n"); - - unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); - - if (ret != 0) { - ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret); - panic(); - } - - gxbb_program_mailbox(read_mpidr_el1(), 0); - - wfi(); - - ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n"); - panic(); -} - -static int32_t gxbb_pwr_domain_on(u_register_t mpidr) -{ - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - - /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { - VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); - - gxbb_cpu0_go = 1; - flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go)); - dsb(); - isb(); - - sev(); - - return PSCI_E_SUCCESS; - } - - gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint); - scpi_set_css_power_state(mpidr, - SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); - dmbsy(); - sev(); - - return PSCI_E_SUCCESS; -} - -static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) -{ - unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); - - assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == - PLAT_LOCAL_STATE_OFF); - - if (core == GXBB_PRIMARY_CPU) { - gxbb_cpu0_go = 0; - flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go)); - dsb(); - isb(); - } - - gicv2_pcpu_distif_init(); - gicv2_cpuif_enable(); -} - -static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) -{ - u_register_t mpidr = read_mpidr_el1(); - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4); - - mmio_write_32(addr, 0xFFFFFFFF); - flush_dcache_range(addr, sizeof(uint32_t)); - - gicv2_cpuif_disable(); - - /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) - return; - - scpi_set_css_power_state(mpidr, - SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); -} - -static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t - *target_state) -{ - unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); - - /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { - VERBOSE("BL31: CPU0 entering wait loop...\n"); - - while (gxbb_cpu0_go == 0) - wfe(); - - VERBOSE("BL31: CPU0 resumed.\n"); - - write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT); - } - - dsbsy(); - - for (;;) - wfi(); -} - -/******************************************************************************* - * Platform handlers and setup function. - ******************************************************************************/ -static const plat_psci_ops_t gxbb_ops = { - .pwr_domain_on = gxbb_pwr_domain_on, - .pwr_domain_on_finish = gxbb_pwr_domain_on_finish, - .pwr_domain_off = gxbb_pwr_domain_off, - .pwr_domain_pwr_down_wfi = gxbb_pwr_domain_pwr_down_wfi, - .system_off = gxbb_system_off, - .system_reset = gxbb_system_reset, -}; - -int plat_setup_psci_ops(uintptr_t sec_entrypoint, - const plat_psci_ops_t **psci_ops) -{ - gxbb_sec_entrypoint = sec_entrypoint; - *psci_ops = &gxbb_ops; - gxbb_cpu0_go = 0; - return 0; -} diff --git a/plat/meson/gxbb/gxbb_private.h b/plat/meson/gxbb/gxbb_private.h deleted file mode 100644 index 910a42c1c..000000000 --- a/plat/meson/gxbb/gxbb_private.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef GXBB_PRIVATE_H -#define GXBB_PRIVATE_H - -#include - -/* Utility functions */ -unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); -void gxbb_console_init(void); -void gxbb_setup_page_tables(void); - -/* MHU functions */ -void mhu_secure_message_start(void); -void mhu_secure_message_send(uint32_t msg); -uint32_t mhu_secure_message_wait(void); -void mhu_secure_message_end(void); -void mhu_secure_init(void); - -/* SCPI functions */ -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state); -uint32_t scpi_sys_power_state(uint64_t system_state); -void scpi_jtag_set_state(uint32_t state, uint8_t select); -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size); -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3); - -/* Peripherals */ -void gxbb_thermal_unknown(void); -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size); -uint64_t gxbb_efuse_user_max(void); - -#endif /* GXBB_PRIVATE_H */ diff --git a/plat/meson/gxbb/gxbb_scpi.c b/plat/meson/gxbb/gxbb_scpi.c deleted file mode 100644 index 83eeda29d..000000000 --- a/plat/meson/gxbb/gxbb_scpi.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include -#include - -#include "gxbb_private.h" - -#define SIZE_SHIFT 20 -#define SIZE_MASK 0x1FF - -/* - * Note: The Amlogic SCP firmware uses the legacy SCPI protocol. - */ -#define SCPI_CMD_SET_CSS_POWER_STATE 0x04 -#define SCPI_CMD_SET_SYS_POWER_STATE 0x08 - -#define SCPI_CMD_JTAG_SET_STATE 0xC0 -#define SCPI_CMD_EFUSE_READ 0xC2 - -static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) -{ - return command | (size << SIZE_SHIFT); -} - -void scpi_secure_message_send(uint32_t command, uint32_t size) -{ - mhu_secure_message_send(scpi_cmd(command, size)); -} - -uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) -{ - uint32_t response = mhu_secure_message_wait(); - - size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; - - response &= ~(SIZE_MASK << SIZE_SHIFT); - - if (size_out != NULL) - *size_out = size; - - if (message_out != NULL) - *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD; - - return response; -} - -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state) -{ - uint32_t state = (mpidr & 0x0F) | /* CPU ID */ - ((mpidr & 0xF00) >> 4) | /* Cluster ID */ - (cpu_state << 8) | - (cluster_state << 12) | - (css_state << 16); - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_sys_power_state(uint64_t system_state) -{ - uint32_t *response; - size_t size; - - mhu_secure_message_start(); - mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); - scpi_secure_message_receive((void *)&response, &size); - mhu_secure_message_end(); - - return *response; -} - -void scpi_jtag_set_state(uint32_t state, uint8_t select) -{ - assert(state <= GXBB_JTAG_STATE_OFF); - - if (select > GXBB_JTAG_A53_EE) { - WARN("BL31: Invalid JTAG select (0x%x).\n", select); - return; - } - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, - (state << 8) | (uint32_t)select); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) -{ - uint32_t *response; - size_t resp_size; - - if (size > 0x1FC) - return 0; - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); - scpi_secure_message_receive((void *)&response, &resp_size); - mhu_secure_message_end(); - - /* - * response[0] is the size of the response message. - * response[1 ... N] are the contents. - */ - if (*response != 0) - memcpy(dst, response + 1, *response); - - return *response; -} - -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3) -{ - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); - mhu_secure_message_send(scpi_cmd(0xC3, 16)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} diff --git a/plat/meson/gxbb/gxbb_sip_svc.c b/plat/meson/gxbb/gxbb_sip_svc.c deleted file mode 100644 index 63c7dba15..000000000 --- a/plat/meson/gxbb/gxbb_sip_svc.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include - -#include "gxbb_private.h" - -/******************************************************************************* - * This function is responsible for handling all SiP calls - ******************************************************************************/ -static uintptr_t gxbb_sip_handler(uint32_t smc_fid, - u_register_t x1, u_register_t x2, - u_register_t x3, u_register_t x4, - void *cookie, void *handle, - u_register_t flags) -{ - switch (smc_fid) { - - case GXBB_SM_GET_SHARE_MEM_INPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE); - - case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE); - - case GXBB_SM_EFUSE_READ: - { - void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; - uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2); - - SMC_RET1(handle, ret); - } - case GXBB_SM_EFUSE_USER_MAX: - SMC_RET1(handle, gxbb_efuse_user_max()); - - case GXBB_SM_JTAG_ON: - scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); - SMC_RET1(handle, 0); - - case GXBB_SM_JTAG_OFF: - scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1); - SMC_RET1(handle, 0); - - default: - ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid); - break; - } - - SMC_RET1(handle, SMC_UNK); -} - -DECLARE_RT_SVC( - gxbb_sip_handler, - - OEN_SIP_START, - OEN_SIP_END, - SMC_TYPE_FAST, - NULL, - gxbb_sip_handler -); diff --git a/plat/meson/gxbb/gxbb_thermal.c b/plat/meson/gxbb/gxbb_thermal.c deleted file mode 100644 index b6048eee4..000000000 --- a/plat/meson/gxbb/gxbb_thermal.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include "gxbb_private.h" - -static int32_t modules_initialized = -1; - -/******************************************************************************* - * Unknown commands related to something thermal-related - ******************************************************************************/ -void gxbb_thermal_unknown(void) -{ - uint16_t ret; - - if (modules_initialized == -1) { - scpi_efuse_read(&ret, 0, 2); - modules_initialized = ret; - } - - scpi_unknown_thermal(10, 2, /* thermal */ - 13, 1); /* thermalver */ -} diff --git a/plat/meson/gxbb/gxbb_topology.c b/plat/meson/gxbb/gxbb_topology.c deleted file mode 100644 index eec2d34d4..000000000 --- a/plat/meson/gxbb/gxbb_topology.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include - -#include "gxbb_private.h" - -/* The power domain tree descriptor */ -static unsigned char power_domain_tree_desc[] = { - /* Number of root nodes */ - PLATFORM_CLUSTER_COUNT, - /* Number of children for the first node */ - PLATFORM_CLUSTER0_CORE_COUNT -}; - -/******************************************************************************* - * This function returns the ARM default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) - return -1; - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) - return -1; - - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) - return -1; - - return plat_gxbb_calc_core_pos(mpidr); -} diff --git a/plat/meson/gxbb/include/plat_macros.S b/plat/meson/gxbb/include/plat_macros.S deleted file mode 100644 index c721c21b6..000000000 --- a/plat/meson/gxbb/include/plat_macros.S +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLAT_MACROS_S -#define PLAT_MACROS_S - -#include -#include - -.section .rodata.gic_reg_name, "aS" - -gicc_regs: - .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" -gicd_pend_reg: - .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" -newline: - .asciz "\n" -spacer: - .asciz ":\t\t0x" - - /* --------------------------------------------- - * The below required platform porting macro - * prints out relevant GIC and CCI registers - * whenever an unhandled exception is taken in - * BL31. - * Clobbers: x0 - x10, x16, x17, sp - * --------------------------------------------- - */ - .macro plat_crash_print_regs - - /* GICC registers */ - - mov_imm x17, GXBB_GICC_BASE - - adr x6, gicc_regs - ldr w8, [x17, #GICC_HPPIR] - ldr w9, [x17, #GICC_AHPPIR] - ldr w10, [x17, #GICC_CTLR] - bl str_in_crash_buf_print - - /* GICD registers */ - - mov_imm x16, GXBB_GICD_BASE - - add x7, x16, #GICD_ISPENDR - adr x4, gicd_pend_reg - bl asm_print_str - -gicd_ispendr_loop: - sub x4, x7, x16 - cmp x4, #0x280 - b.eq exit_print_gic_regs - bl asm_print_hex - - adr x4, spacer - bl asm_print_str - - ldr x4, [x7], #8 - bl asm_print_hex - - adr x4, newline - bl asm_print_str - b gicd_ispendr_loop -exit_print_gic_regs: - - .endm - -#endif /* PLAT_MACROS_S */ diff --git a/plat/meson/gxbb/include/platform_def.h b/plat/meson/gxbb/include/platform_def.h deleted file mode 100644 index da4aedde8..000000000 --- a/plat/meson/gxbb/include/platform_def.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLATFORM_DEF_H -#define PLATFORM_DEF_H - -#include -#include - -#include "../gxbb_def.h" - -#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" -#define PLATFORM_LINKER_ARCH aarch64 - -/* Special value used to verify platform parameters from BL2 to BL31 */ -#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) - -#define PLATFORM_STACK_SIZE UL(0x1000) - -#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) -#define PLATFORM_CLUSTER_COUNT U(1) -#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT - -#define GXBB_PRIMARY_CPU U(0) - -#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 -#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ - PLATFORM_CORE_COUNT) - -#define PLAT_MAX_RET_STATE U(1) -#define PLAT_MAX_OFF_STATE U(2) - -/* Local power state for power domains in Run state. */ -#define PLAT_LOCAL_STATE_RUN U(0) -/* Local power state for retention. Valid only for CPU power domains */ -#define PLAT_LOCAL_STATE_RET U(1) -/* Local power state for power-down. Valid for CPU and cluster power domains. */ -#define PLAT_LOCAL_STATE_OFF U(2) - -/* - * Macros used to parse state information from State-ID if it is using the - * recommended encoding for State-ID. - */ -#define PLAT_LOCAL_PSTATE_WIDTH U(4) -#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) - -/* - * Some data must be aligned on the biggest cache line size in the platform. - * This is known only to the platform as it might have a combination of - * integrated and external caches. - */ -#define CACHE_WRITEBACK_SHIFT U(6) -#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) - -/* Memory-related defines */ -#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) -#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) - -#define MAX_MMAP_REGIONS 12 -#define MAX_XLAT_TABLES 5 - -#endif /* PLATFORM_DEF_H */ diff --git a/plat/meson/gxbb/platform.mk b/plat/meson/gxbb/platform.mk deleted file mode 100644 index 9e65040b9..000000000 --- a/plat/meson/gxbb/platform.mk +++ /dev/null @@ -1,69 +0,0 @@ -# -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -include lib/xlat_tables_v2/xlat_tables.mk - -PLAT_INCLUDES := -Iplat/meson/gxbb/include - -GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/v2/gicv2_helpers.c \ - plat/common/plat_gicv2.c - -PLAT_BL_COMMON_SOURCES := drivers/meson/console/aarch64/meson_console.S \ - plat/meson/gxbb/gxbb_common.c \ - plat/meson/gxbb/gxbb_topology.c \ - ${XLAT_TABLES_LIB_SRCS} - -BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ - plat/common/plat_psci_common.c \ - plat/meson/gxbb/aarch64/gxbb_helpers.S \ - plat/meson/gxbb/gxbb_bl31_setup.c \ - plat/meson/gxbb/gxbb_efuse.c \ - plat/meson/gxbb/gxbb_mhu.c \ - plat/meson/gxbb/gxbb_pm.c \ - plat/meson/gxbb/gxbb_scpi.c \ - plat/meson/gxbb/gxbb_sip_svc.c \ - plat/meson/gxbb/gxbb_thermal.c \ - ${GXBB_GIC_SOURCES} - -# Tune compiler for Cortex-A53 -ifeq ($(notdir $(CC)),armclang) - TF_CFLAGS_aarch64 += -mcpu=cortex-a53 -else ifneq ($(findstring clang,$(notdir $(CC))),) - TF_CFLAGS_aarch64 += -mcpu=cortex-a53 -else - TF_CFLAGS_aarch64 += -mtune=cortex-a53 -endif - -# Build config flags -# ------------------ - -# Enable all errata workarounds for Cortex-A53 -ERRATA_A53_826319 := 1 -ERRATA_A53_835769 := 1 -ERRATA_A53_836870 := 1 -ERRATA_A53_843419 := 1 -ERRATA_A53_855873 := 1 - -WORKAROUND_CVE_2017_5715 := 0 - -# Have different sections for code and rodata -SEPARATE_CODE_AND_RODATA := 1 - -# Use Coherent memory -USE_COHERENT_MEM := 1 - -# Verify build config -# ------------------- - -ifneq (${RESET_TO_BL31}, 0) - $(error Error: gxbb needs RESET_TO_BL31=0) -endif - -ifeq (${ARCH},aarch32) - $(error Error: AArch32 not supported on gxbb) -endif diff --git a/plat/meson/gxl/aarch64/gxl_helpers.S b/plat/meson/gxl/aarch64/gxl_helpers.S deleted file mode 100644 index 760d6c46d..000000000 --- a/plat/meson/gxl/aarch64/gxl_helpers.S +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - - .globl plat_crash_console_flush - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl platform_mem_init - .globl plat_is_my_cpu_primary - .globl plat_my_core_pos - .globl plat_reset_handler - .globl plat_gxbb_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_my_core_pos(void); - * ----------------------------------------------------- - */ -func plat_my_core_pos - mrs x0, mpidr_el1 - b plat_gxbb_calc_core_pos -endfunc plat_my_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); - * ----------------------------------------------------- - */ -func plat_gxbb_calc_core_pos - and x0, x0, #MPIDR_CPU_MASK - ret -endfunc plat_gxbb_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_is_my_cpu_primary(void); - * ----------------------------------------------------- - */ -func plat_is_my_cpu_primary - mrs x0, mpidr_el1 - and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #GXBB_PRIMARY_CPU - cset w0, eq - ret -endfunc plat_is_my_cpu_primary - - /* --------------------------------------------- - * void platform_mem_init(void); - * --------------------------------------------- - */ -func platform_mem_init - ret -endfunc platform_mem_init - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, GXBB_UART0_AO_BASE - mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ - mov_imm x2, GXBB_UART_BAUDRATE - b console_meson_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(int c) - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, GXBB_UART0_AO_BASE - b console_meson_core_putc -endfunc plat_crash_console_putc - - /* --------------------------------------------- - * int plat_crash_console_flush() - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func plat_crash_console_flush - mov_imm x0, GXBB_UART0_AO_BASE - b console_meson_core_flush -endfunc plat_crash_console_flush - - /* --------------------------------------------- - * void plat_reset_handler(void); - * --------------------------------------------- - */ -func plat_reset_handler - ret -endfunc plat_reset_handler diff --git a/plat/meson/gxl/gxl_bl31_setup.c b/plat/meson/gxl/gxl_bl31_setup.c deleted file mode 100644 index b1da7942b..000000000 --- a/plat/meson/gxl/gxl_bl31_setup.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "gxl_private.h" - -/* - * Placeholder variables for copying the arguments that have been passed to - * BL31 from BL2. - */ -static entry_point_info_t bl33_image_ep_info; -static image_info_t bl30_image_info; -static image_info_t bl301_image_info; - -/******************************************************************************* - * Return a pointer to the 'entry_point_info' structure of the next image for - * the security state specified. BL33 corresponds to the non-secure image type - * while BL32 corresponds to the secure image type. A NULL pointer is returned - * if the image does not exist. - ******************************************************************************/ -entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) -{ - entry_point_info_t *next_image_info; - - assert(type == NON_SECURE); - - next_image_info = &bl33_image_ep_info; - - /* None of the images can have 0x0 as the entrypoint. */ - if (next_image_info->pc != 0U) { - return next_image_info; - } else { - return NULL; - } -} - -/******************************************************************************* - * Perform any BL31 early platform setup. Here is an opportunity to copy - * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before - * they are lost (potentially). This needs to be done before the MMU is - * initialized so that the memory layout can be used while creating page - * tables. BL2 has flushed this information to memory, so we are guaranteed - * to pick up good data. - ******************************************************************************/ -struct gxl_bl31_param { - param_header_t h; - image_info_t *bl31_image_info; - entry_point_info_t *bl32_ep_info; - image_info_t *bl32_image_info; - entry_point_info_t *bl33_ep_info; - image_info_t *bl33_image_info; - image_info_t *scp_image_info[]; -}; - -void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, - u_register_t arg2, u_register_t arg3) -{ - struct gxl_bl31_param *from_bl2; - - /* Initialize the console to provide early debug support */ - gxbb_console_init(); - - /* Check that params passed from BL2 are not NULL. */ - from_bl2 = (struct gxl_bl31_param *) arg0; - - /* Check params passed from BL2 are not NULL. */ - assert(from_bl2 != NULL); - assert(from_bl2->h.type == PARAM_BL31); - assert(from_bl2->h.version >= VERSION_1); - - /* - * Copy BL33 entry point information. It is stored in Secure RAM, in - * BL2's address space. - */ - bl33_image_ep_info = *from_bl2->bl33_ep_info; - - if (bl33_image_ep_info.pc == 0U) { - ERROR("BL31: BL33 entrypoint not obtained from BL2\n"); - panic(); - } - - bl30_image_info = *from_bl2->scp_image_info[0]; - bl301_image_info = *from_bl2->scp_image_info[1]; -} - -void bl31_plat_arch_setup(void) -{ - gxbb_setup_page_tables(); - - enable_mmu_el3(0); -} - -static inline bool gxl_scp_ready(void) -{ - return GXBB_AO_RTI_SCP_IS_READY(mmio_read_32(GXBB_AO_RTI_SCP_STAT)); -} - -static inline void gxl_scp_boot(void) -{ - scpi_upload_scp_fw(bl30_image_info.image_base, - bl30_image_info.image_size, 0); - scpi_upload_scp_fw(bl301_image_info.image_base, - bl301_image_info.image_size, 1); - while (!gxl_scp_ready()) - ; -} - -/******************************************************************************* - * GICv2 driver setup information - ******************************************************************************/ -static const interrupt_prop_t gxbb_interrupt_props[] = { - INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, - GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), -}; - -static const gicv2_driver_data_t gxbb_gic_data = { - .gicd_base = GXBB_GICD_BASE, - .gicc_base = GXBB_GICC_BASE, - .interrupt_props = gxbb_interrupt_props, - .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), -}; - -void bl31_platform_setup(void) -{ - mhu_secure_init(); - - gicv2_driver_init(&gxbb_gic_data); - gicv2_distif_init(); - gicv2_pcpu_distif_init(); - gicv2_cpuif_enable(); - - gxl_scp_boot(); - - gxbb_thermal_unknown(); -} diff --git a/plat/meson/gxl/gxl_common.c b/plat/meson/gxl/gxl_common.c deleted file mode 100644 index e3bd6048a..000000000 --- a/plat/meson/gxl/gxl_common.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/******************************************************************************* - * Platform memory map regions - ******************************************************************************/ -#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \ - GXBB_NSDRAM0_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \ - GXBB_NSDRAM1_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \ - GXBB_SEC_DEVICE0_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \ - GXBB_SEC_DEVICE1_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \ - GXBB_TZRAM_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \ - GXBB_SEC_DEVICE2_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \ - GXBB_SEC_DEVICE3_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -static const mmap_region_t gxbb_mmap[] = { - MAP_NSDRAM0, - MAP_NSDRAM1, - MAP_SEC_DEVICE0, - MAP_SEC_DEVICE1, - MAP_TZRAM, - MAP_SEC_DEVICE2, - MAP_SEC_DEVICE3, - {0} -}; - -/******************************************************************************* - * Per-image regions - ******************************************************************************/ -#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \ - BL31_END - BL31_BASE, \ - MT_MEMORY | MT_RW | MT_SECURE) - -#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \ - BL_CODE_END - BL_CODE_BASE, \ - MT_CODE | MT_SECURE) - -#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \ - BL_RO_DATA_END - BL_RO_DATA_BASE, \ - MT_RO_DATA | MT_SECURE) - -#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \ - BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -/******************************************************************************* - * Function that sets up the translation tables. - ******************************************************************************/ -void gxbb_setup_page_tables(void) -{ -#if IMAGE_BL31 - const mmap_region_t gxbb_bl_mmap[] = { - MAP_BL31, - MAP_BL_CODE, - MAP_BL_RO_DATA, -#if USE_COHERENT_MEM - MAP_BL_COHERENT, -#endif - {0} - }; -#endif - - mmap_add(gxbb_bl_mmap); - - mmap_add(gxbb_mmap); - - init_xlat_tables(); -} - -/******************************************************************************* - * Function that sets up the console - ******************************************************************************/ -static console_meson_t gxbb_console; - -void gxbb_console_init(void) -{ - int rc = console_meson_register(GXBB_UART0_AO_BASE, - GXBB_UART0_AO_CLK_IN_HZ, - GXBB_UART_BAUDRATE, - &gxbb_console); - if (rc == 0) { - /* - * The crash console doesn't use the multi console API, it uses - * the core console functions directly. It is safe to call panic - * and let it print debug information. - */ - panic(); - } - - console_set_scope(&gxbb_console.console, - CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); -} - -/******************************************************************************* - * Function that returns the system counter frequency - ******************************************************************************/ -unsigned int plat_get_syscnt_freq2(void) -{ - uint32_t val; - - val = mmio_read_32(GXBB_SYS_CPU_CFG7); - val &= 0xFDFFFFFF; - mmio_write_32(GXBB_SYS_CPU_CFG7, val); - - val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL); - val &= 0xFFFFFE00; - mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val); - - return GXBB_OSC24M_CLK_IN_HZ; -} diff --git a/plat/meson/gxl/gxl_def.h b/plat/meson/gxl/gxl_def.h deleted file mode 100644 index 089fa8db9..000000000 --- a/plat/meson/gxl/gxl_def.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef GXBB_DEF_H -#define GXBB_DEF_H - -#include - -/******************************************************************************* - * System oscillator - ******************************************************************************/ -#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ - -/******************************************************************************* - * Memory regions - ******************************************************************************/ -#define GXBB_NSDRAM0_BASE UL(0x01000000) -#define GXBB_NSDRAM0_SIZE UL(0x0F000000) - -#define GXBB_NSDRAM1_BASE UL(0x10000000) -#define GXBB_NSDRAM1_SIZE UL(0x00100000) - -#define BL31_BASE UL(0x05100000) -#define BL31_SIZE UL(0x000C0000) -#define BL31_LIMIT (BL31_BASE + BL31_SIZE) - -/* Shared memory used for SMC services */ -#define GXBB_SHARE_MEM_INPUT_BASE UL(0x050FE000) -#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x050FF000) - -#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000) -#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000) - -#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000) -#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000) - -#define GXBB_TZRAM_BASE UL(0xD9000000) -#define GXBB_TZRAM_SIZE UL(0x00014000) -/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ - -/* Mailboxes */ -#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) -#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) -#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00) - -// * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) -// * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * -// * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) * - -#define GXBB_TZROM_BASE UL(0xD9040000) -#define GXBB_TZROM_SIZE UL(0x00010000) - -#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000) -#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000) - -#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000) -#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000) - -/******************************************************************************* - * GIC-400 and interrupt handling related constants - ******************************************************************************/ -#define GXBB_GICD_BASE UL(0xC4301000) -#define GXBB_GICC_BASE UL(0xC4302000) - -#define IRQ_SEC_PHY_TIMER 29 - -#define IRQ_SEC_SGI_0 8 -#define IRQ_SEC_SGI_1 9 -#define IRQ_SEC_SGI_2 10 -#define IRQ_SEC_SGI_3 11 -#define IRQ_SEC_SGI_4 12 -#define IRQ_SEC_SGI_5 13 -#define IRQ_SEC_SGI_6 14 -#define IRQ_SEC_SGI_7 15 - -/******************************************************************************* - * UART definitions - ******************************************************************************/ -#define GXBB_UART0_AO_BASE UL(0xC81004C0) -#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ -#define GXBB_UART_BAUDRATE U(115200) - -/******************************************************************************* - * Memory-mapped I/O Registers - ******************************************************************************/ -#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4) - -#define GXBB_SYS_CPU_CFG7 UL(0xC8834664) - -#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C) -#define GXBB_AO_RTI_SCP_STAT UL(0xDA10023C) -#define GXBB_AO_RTI_SCP_READY_OFF U(0x14) -#define GXBB_A0_RTI_SCP_READY_MASK U(3) -#define GXBB_AO_RTI_SCP_IS_READY(v) \ - ((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \ - GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK) - -#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404) -#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408) -#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) -#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428) -#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) -#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430) - -/******************************************************************************* - * System Monitor Call IDs and arguments - ******************************************************************************/ -#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) -#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) - -#define GXBB_SM_EFUSE_READ U(0x82000030) -#define GXBB_SM_EFUSE_USER_MAX U(0x82000033) - -#define GXBB_SM_JTAG_ON U(0x82000040) -#define GXBB_SM_JTAG_OFF U(0x82000041) - -#define GXBB_JTAG_STATE_ON U(0) -#define GXBB_JTAG_STATE_OFF U(1) - -#define GXBB_JTAG_M3_AO U(0) -#define GXBB_JTAG_M3_EE U(1) -#define GXBB_JTAG_A53_AO U(2) -#define GXBB_JTAG_A53_EE U(3) - -#endif /* GXBB_DEF_H */ diff --git a/plat/meson/gxl/gxl_efuse.c b/plat/meson/gxl/gxl_efuse.c deleted file mode 100644 index b17d1b8e3..000000000 --- a/plat/meson/gxl/gxl_efuse.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include "gxl_private.h" - -#define EFUSE_BASE 0x140 -#define EFUSE_SIZE 0xC0 - -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) -{ - if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) - return 0; - - return scpi_efuse_read(dst, offset + EFUSE_BASE, size); -} - -uint64_t gxbb_efuse_user_max(void) -{ - return EFUSE_SIZE; -} diff --git a/plat/meson/gxl/gxl_mhu.c b/plat/meson/gxl/gxl_mhu.c deleted file mode 100644 index 4c1d5b600..000000000 --- a/plat/meson/gxl/gxl_mhu.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -static DEFINE_BAKERY_LOCK(mhu_lock); - -void mhu_secure_message_start(void) -{ - bakery_lock_get(&mhu_lock); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -void mhu_secure_message_send(uint32_t msg) -{ - mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -uint32_t mhu_secure_message_wait(void) -{ - uint32_t val; - - do { - val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0); - } while (val == 0); - - return val; -} - -void mhu_secure_message_end(void) -{ - mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); - - bakery_lock_release(&mhu_lock); -} - -void mhu_secure_init(void) -{ - bakery_lock_init(&mhu_lock); - - mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); -} diff --git a/plat/meson/gxl/gxl_pm.c b/plat/meson/gxl/gxl_pm.c deleted file mode 100644 index 4a5d26e90..000000000 --- a/plat/meson/gxl/gxl_pm.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "gxl_private.h" - -#define SCPI_POWER_ON 0 -#define SCPI_POWER_RETENTION 1 -#define SCPI_POWER_OFF 3 - -#define SCPI_SYSTEM_SHUTDOWN 0 -#define SCPI_SYSTEM_REBOOT 1 - -static uintptr_t gxbb_sec_entrypoint; -static volatile uint32_t gxbb_cpu0_go; - -static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value) -{ - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); - - mmio_write_64(cpu_mailbox_addr, value); -} - -static void gxl_pm_reset(u_register_t mpidr) -{ - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8; - - mmio_write_32(cpu_mailbox_addr, 0); -} - -static void __dead2 gxbb_system_reset(void) -{ - INFO("BL31: PSCI_SYSTEM_RESET\n"); - - u_register_t mpidr = read_mpidr_el1(); - uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3); - int ret; - - NOTICE("BL31: Reboot reason: 0x%x\n", status); - - status &= 0xFFFF0FF0; - - console_flush(); - - mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); - - ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); - - if (ret != 0) { - ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret); - panic(); - } - - gxl_pm_reset(mpidr); - - wfi(); - - ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n"); - panic(); -} - -static void __dead2 gxbb_system_off(void) -{ - INFO("BL31: PSCI_SYSTEM_OFF\n"); - - u_register_t mpidr = read_mpidr_el1(); - int ret; - - ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); - - if (ret != 0) { - ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret); - panic(); - } - - gxl_pm_set_reset_addr(mpidr, 0); - gxl_pm_reset(mpidr); - - wfi(); - - ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n"); - panic(); -} - -static int32_t gxbb_pwr_domain_on(u_register_t mpidr) -{ - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - - /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { - VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); - - gxbb_cpu0_go = 1; - flush_dcache_range((uintptr_t)&gxbb_cpu0_go, - sizeof(gxbb_cpu0_go)); - dsb(); - isb(); - - sev(); - - return PSCI_E_SUCCESS; - } - - gxl_pm_set_reset_addr(mpidr, gxbb_sec_entrypoint); - scpi_set_css_power_state(mpidr, - SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); - dmbsy(); - sev(); - - return PSCI_E_SUCCESS; -} - -static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) -{ - unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); - - assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == - PLAT_LOCAL_STATE_OFF); - - if (core == GXBB_PRIMARY_CPU) { - gxbb_cpu0_go = 0; - flush_dcache_range((uintptr_t)&gxbb_cpu0_go, - sizeof(gxbb_cpu0_go)); - dsb(); - isb(); - } - - gicv2_pcpu_distif_init(); - gicv2_cpuif_enable(); -} - -static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) -{ - u_register_t mpidr = read_mpidr_el1(); - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - - gicv2_cpuif_disable(); - - /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) - return; - - scpi_set_css_power_state(mpidr, - SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); -} - -static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t - *target_state) -{ - u_register_t mpidr = read_mpidr_el1(); - unsigned int core = plat_gxbb_calc_core_pos(mpidr); - - /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { - VERBOSE("BL31: CPU0 entering wait loop...\n"); - - while (gxbb_cpu0_go == 0) - wfe(); - - VERBOSE("BL31: CPU0 resumed.\n"); - - /* - * Because setting CPU0's warm reset entrypoint through PSCI - * mailbox and/or mmio mapped RVBAR (0xda834650) does not seem - * to work, jump to it manually. - * In order to avoid an assert, mmu has to be disabled. - */ - disable_mmu_el3(); - ((void(*)(void))gxbb_sec_entrypoint)(); - } - - dsbsy(); - gxl_pm_set_reset_addr(mpidr, 0); - gxl_pm_reset(mpidr); - - for (;;) - wfi(); -} - -/******************************************************************************* - * Platform handlers and setup function. - ******************************************************************************/ -static const plat_psci_ops_t gxbb_ops = { - .pwr_domain_on = gxbb_pwr_domain_on, - .pwr_domain_on_finish = gxbb_pwr_domain_on_finish, - .pwr_domain_off = gxbb_pwr_domain_off, - .pwr_domain_pwr_down_wfi = gxbb_pwr_domain_pwr_down_wfi, - .system_off = gxbb_system_off, - .system_reset = gxbb_system_reset, -}; - -int plat_setup_psci_ops(uintptr_t sec_entrypoint, - const plat_psci_ops_t **psci_ops) -{ - gxbb_sec_entrypoint = sec_entrypoint; - *psci_ops = &gxbb_ops; - gxbb_cpu0_go = 0; - return 0; -} diff --git a/plat/meson/gxl/gxl_private.h b/plat/meson/gxl/gxl_private.h deleted file mode 100644 index 913cbf653..000000000 --- a/plat/meson/gxl/gxl_private.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef GXBB_PRIVATE_H -#define GXBB_PRIVATE_H - -#include -#include - -/* Utility functions */ -unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); -void gxbb_console_init(void); -void gxbb_setup_page_tables(void); - -/* MHU functions */ -void mhu_secure_message_start(void); -void mhu_secure_message_send(uint32_t msg); -uint32_t mhu_secure_message_wait(void); -void mhu_secure_message_end(void); -void mhu_secure_init(void); - -/* SCPI functions */ -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state); -uint32_t scpi_sys_power_state(uint64_t system_state); -void scpi_jtag_set_state(uint32_t state, uint8_t select); -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size); -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3); -void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); - -/* Peripherals */ -void gxbb_thermal_unknown(void); -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size); -uint64_t gxbb_efuse_user_max(void); - -#endif /* GXBB_PRIVATE_H */ diff --git a/plat/meson/gxl/gxl_scpi.c b/plat/meson/gxl/gxl_scpi.c deleted file mode 100644 index 13d652436..000000000 --- a/plat/meson/gxl/gxl_scpi.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -#include "gxl_private.h" - -#define SIZE_SHIFT 20 -#define SIZE_MASK 0x1FF -#define SIZE_FWBLK 0x200UL - -/* - * Note: The Amlogic SCP firmware uses the legacy SCPI protocol. - */ -#define SCPI_CMD_SET_CSS_POWER_STATE 0x04 -#define SCPI_CMD_SET_SYS_POWER_STATE 0x08 - -#define SCPI_CMD_JTAG_SET_STATE 0xC0 -#define SCPI_CMD_EFUSE_READ 0xC2 - -#define SCPI_CMD_COPY_FW 0xd4 -#define SCPI_CMD_SET_FW_ADDR 0xd3 -#define SCPI_CMD_FW_SIZE 0xd2 - -static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) -{ - return command | (size << SIZE_SHIFT); -} - -static void scpi_secure_message_send(uint32_t command, uint32_t size) -{ - mhu_secure_message_send(scpi_cmd(command, size)); -} - -uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) -{ - uint32_t response = mhu_secure_message_wait(); - - size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; - - response &= ~(SIZE_MASK << SIZE_SHIFT); - - if (size_out != NULL) - *size_out = size; - - if (message_out != NULL) - *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD; - - return response; -} - -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state) -{ - uint32_t state = (mpidr & 0x0F) | /* CPU ID */ - ((mpidr & 0xF00) >> 4) | /* Cluster ID */ - (cpu_state << 8) | - (cluster_state << 12) | - (css_state << 16); - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_sys_power_state(uint64_t system_state) -{ - uint32_t *response; - size_t size; - - mhu_secure_message_start(); - mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); - scpi_secure_message_receive((void *)&response, &size); - mhu_secure_message_end(); - - return *response; -} - -void scpi_jtag_set_state(uint32_t state, uint8_t select) -{ - assert(state <= GXBB_JTAG_STATE_OFF); - - if (select > GXBB_JTAG_A53_EE) { - WARN("BL31: Invalid JTAG select (0x%x).\n", select); - return; - } - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, - (state << 8) | (uint32_t)select); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) -{ - uint32_t *response; - size_t resp_size; - - if (size > 0x1FC) - return 0; - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); - scpi_secure_message_receive((void *)&response, &resp_size); - mhu_secure_message_end(); - - /* - * response[0] is the size of the response message. - * response[1 ... N] are the contents. - */ - if (*response != 0) - memcpy(dst, response + 1, *response); - - return *response; -} - -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3) -{ - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); - mhu_secure_message_send(scpi_cmd(0xC3, 16)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -static inline void scpi_copy_scp_data(uint8_t *data, size_t len) -{ - void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; - size_t sz; - - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); - scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); - mhu_secure_message_wait(); - - for (sz = 0; sz < len; sz += SIZE_FWBLK) { - memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz)); - mhu_secure_message_send(SCPI_CMD_COPY_FW); - } -} - -static inline void scpi_set_scp_addr(uint64_t addr, size_t len) -{ - volatile uint64_t *dst = (uint64_t *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; - - /* - * It is ok as GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as - * non cachable - */ - *dst = addr; - scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr)); - mhu_secure_message_wait(); - - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); - scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); - mhu_secure_message_wait(); -} - -static inline void scpi_send_fw_hash(uint8_t hash[], size_t len) -{ - void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; - - memcpy(dst, hash, len); - mhu_secure_message_send(0xd0); - mhu_secure_message_send(0xd1); - mhu_secure_message_send(0xd5); - mhu_secure_message_end(); -} - -/** - * Upload a FW to SCP. - * - * @param addr: firmware data address - * @param size: size of firmware - * @param send: If set, actually copy the firmware in SCP memory otherwise only - * send the firmware address. - */ -void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send) -{ - struct asd_ctx ctx; - - asd_sha_init(&ctx, ASM_SHA256); - asd_sha_update(&ctx, (void *)addr, size); - asd_sha_finalize(&ctx); - - mhu_secure_message_start(); - if (send == 0) - scpi_set_scp_addr(addr, size); - else - scpi_copy_scp_data((void *)addr, size); - - scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest)); -} diff --git a/plat/meson/gxl/gxl_sip_svc.c b/plat/meson/gxl/gxl_sip_svc.c deleted file mode 100644 index 74fbc80e4..000000000 --- a/plat/meson/gxl/gxl_sip_svc.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include - -#include "gxl_private.h" - -/******************************************************************************* - * This function is responsible for handling all SiP calls - ******************************************************************************/ -static uintptr_t gxbb_sip_handler(uint32_t smc_fid, - u_register_t x1, u_register_t x2, - u_register_t x3, u_register_t x4, - void *cookie, void *handle, - u_register_t flags) -{ - switch (smc_fid) { - - case GXBB_SM_GET_SHARE_MEM_INPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE); - - case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE); - - case GXBB_SM_EFUSE_READ: - { - void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; - uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2); - - SMC_RET1(handle, ret); - } - case GXBB_SM_EFUSE_USER_MAX: - SMC_RET1(handle, gxbb_efuse_user_max()); - - case GXBB_SM_JTAG_ON: - scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); - SMC_RET1(handle, 0); - - case GXBB_SM_JTAG_OFF: - scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1); - SMC_RET1(handle, 0); - - default: - ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid); - break; - } - - SMC_RET1(handle, SMC_UNK); -} - -DECLARE_RT_SVC( - gxbb_sip_handler, - - OEN_SIP_START, - OEN_SIP_END, - SMC_TYPE_FAST, - NULL, - gxbb_sip_handler -); diff --git a/plat/meson/gxl/gxl_thermal.c b/plat/meson/gxl/gxl_thermal.c deleted file mode 100644 index 3af1c6dc6..000000000 --- a/plat/meson/gxl/gxl_thermal.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include "gxl_private.h" - -static int32_t modules_initialized = -1; - -/******************************************************************************* - * Unknown commands related to something thermal-related - ******************************************************************************/ -void gxbb_thermal_unknown(void) -{ - uint16_t ret; - - if (modules_initialized == -1) { - scpi_efuse_read(&ret, 0, 2); - modules_initialized = ret; - } - - scpi_unknown_thermal(10, 2, /* thermal */ - 13, 1); /* thermalver */ -} diff --git a/plat/meson/gxl/gxl_topology.c b/plat/meson/gxl/gxl_topology.c deleted file mode 100644 index cca3ead50..000000000 --- a/plat/meson/gxl/gxl_topology.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include "gxl_private.h" - -/* The power domain tree descriptor */ -static unsigned char power_domain_tree_desc[] = { - /* Number of root nodes */ - PLATFORM_CLUSTER_COUNT, - /* Number of children for the first node */ - PLATFORM_CLUSTER0_CORE_COUNT -}; - -/******************************************************************************* - * This function returns the ARM default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) - return -1; - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) - return -1; - - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) - return -1; - - return plat_gxbb_calc_core_pos(mpidr); -} diff --git a/plat/meson/gxl/include/plat_macros.S b/plat/meson/gxl/include/plat_macros.S deleted file mode 100644 index c721c21b6..000000000 --- a/plat/meson/gxl/include/plat_macros.S +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLAT_MACROS_S -#define PLAT_MACROS_S - -#include -#include - -.section .rodata.gic_reg_name, "aS" - -gicc_regs: - .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" -gicd_pend_reg: - .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" -newline: - .asciz "\n" -spacer: - .asciz ":\t\t0x" - - /* --------------------------------------------- - * The below required platform porting macro - * prints out relevant GIC and CCI registers - * whenever an unhandled exception is taken in - * BL31. - * Clobbers: x0 - x10, x16, x17, sp - * --------------------------------------------- - */ - .macro plat_crash_print_regs - - /* GICC registers */ - - mov_imm x17, GXBB_GICC_BASE - - adr x6, gicc_regs - ldr w8, [x17, #GICC_HPPIR] - ldr w9, [x17, #GICC_AHPPIR] - ldr w10, [x17, #GICC_CTLR] - bl str_in_crash_buf_print - - /* GICD registers */ - - mov_imm x16, GXBB_GICD_BASE - - add x7, x16, #GICD_ISPENDR - adr x4, gicd_pend_reg - bl asm_print_str - -gicd_ispendr_loop: - sub x4, x7, x16 - cmp x4, #0x280 - b.eq exit_print_gic_regs - bl asm_print_hex - - adr x4, spacer - bl asm_print_str - - ldr x4, [x7], #8 - bl asm_print_hex - - adr x4, newline - bl asm_print_str - b gicd_ispendr_loop -exit_print_gic_regs: - - .endm - -#endif /* PLAT_MACROS_S */ diff --git a/plat/meson/gxl/include/platform_def.h b/plat/meson/gxl/include/platform_def.h deleted file mode 100644 index b32ec56da..000000000 --- a/plat/meson/gxl/include/platform_def.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLATFORM_DEF_H -#define PLATFORM_DEF_H - -#include -#include - -#include "../gxl_def.h" - -#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" -#define PLATFORM_LINKER_ARCH aarch64 - -/* Special value used to verify platform parameters from BL2 to BL31 */ -#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) - -#define PLATFORM_STACK_SIZE UL(0x1000) - -#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) -#define PLATFORM_CLUSTER_COUNT U(1) -#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT - -#define GXBB_PRIMARY_CPU U(0) - -#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 -#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ - PLATFORM_CORE_COUNT) - -#define PLAT_MAX_RET_STATE U(1) -#define PLAT_MAX_OFF_STATE U(2) - -/* Local power state for power domains in Run state. */ -#define PLAT_LOCAL_STATE_RUN U(0) -/* Local power state for retention. Valid only for CPU power domains */ -#define PLAT_LOCAL_STATE_RET U(1) -/* Local power state for power-down. Valid for CPU and cluster power domains. */ -#define PLAT_LOCAL_STATE_OFF U(2) - -/* - * Macros used to parse state information from State-ID if it is using the - * recommended encoding for State-ID. - */ -#define PLAT_LOCAL_PSTATE_WIDTH U(4) -#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) - -/* - * Some data must be aligned on the biggest cache line size in the platform. - * This is known only to the platform as it might have a combination of - * integrated and external caches. - */ -#define CACHE_WRITEBACK_SHIFT U(6) -#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) - -/* Memory-related defines */ -#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) -#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) - -#define MAX_MMAP_REGIONS 12 -#define MAX_XLAT_TABLES 6 - -#endif /* PLATFORM_DEF_H */ diff --git a/plat/meson/gxl/platform.mk b/plat/meson/gxl/platform.mk deleted file mode 100644 index a788e9639..000000000 --- a/plat/meson/gxl/platform.mk +++ /dev/null @@ -1,87 +0,0 @@ -# -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -include lib/xlat_tables_v2/xlat_tables.mk - -DOIMAGEPATH ?= tools/meson -DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage - -PLAT_INCLUDES := -Iinclude/drivers/meson/ \ - -Iinclude/drivers/meson/gxl \ - -Iplat/meson/gxl/include - -GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/v2/gicv2_helpers.c \ - plat/common/plat_gicv2.c - -PLAT_BL_COMMON_SOURCES := drivers/meson/console/aarch64/meson_console.S \ - plat/meson/gxl/gxl_common.c \ - plat/meson/gxl/gxl_topology.c \ - ${XLAT_TABLES_LIB_SRCS} - -BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ - plat/common/plat_psci_common.c \ - plat/meson/gxl/aarch64/gxl_helpers.S \ - plat/meson/gxl/gxl_bl31_setup.c \ - plat/meson/gxl/gxl_efuse.c \ - plat/meson/gxl/gxl_mhu.c \ - plat/meson/gxl/gxl_pm.c \ - plat/meson/gxl/gxl_scpi.c \ - plat/meson/gxl/gxl_sip_svc.c \ - plat/meson/gxl/gxl_thermal.c \ - drivers/meson/gxl/crypto/sha_dma.c \ - ${GXBB_GIC_SOURCES} - -# Tune compiler for Cortex-A53 -ifeq ($(notdir $(CC)),armclang) - TF_CFLAGS_aarch64 += -mcpu=cortex-a53 -else ifneq ($(findstring clang,$(notdir $(CC))),) - TF_CFLAGS_aarch64 += -mcpu=cortex-a53 -else - TF_CFLAGS_aarch64 += -mtune=cortex-a53 -endif - -# Build config flags -# ------------------ - -# Enable all errata workarounds for Cortex-A53 -ERRATA_A53_855873 := 1 -ERRATA_A53_819472 := 1 -ERRATA_A53_824069 := 1 -ERRATA_A53_827319 := 1 - -WORKAROUND_CVE_2017_5715 := 0 - -# Have different sections for code and rodata -SEPARATE_CODE_AND_RODATA := 1 - -# Use Coherent memory -USE_COHERENT_MEM := 1 - -# Verify build config -# ------------------- - -ifneq (${RESET_TO_BL31}, 0) - $(error Error: gxl needs RESET_TO_BL31=0) -endif - -ifeq (${ARCH},aarch32) - $(error Error: AArch32 not supported on gxl) -endif - -all: ${BUILD_PLAT}/bl31.img -distclean realclean clean: cleanimage - -cleanimage: - ${Q}${MAKE} -C ${DOIMAGEPATH} clean - -${DOIMAGETOOL}: - ${Q}${MAKE} -C ${DOIMAGEPATH} - -${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL} - ${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img - diff --git a/tools/amlogic/Makefile b/tools/amlogic/Makefile new file mode 100644 index 000000000..1a1d1f812 --- /dev/null +++ b/tools/amlogic/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2019 Remi Pommarel +# +# SPDX-License-Identifier: BSD-3-Clause +# https://spdx.org/licenses +# +MAKE_HELPERS_DIRECTORY := ../../make_helpers/ +include ${MAKE_HELPERS_DIRECTORY}build_macros.mk +include ${MAKE_HELPERS_DIRECTORY}build_env.mk + +PROJECT := doimage${BIN_EXT} +OBJECTS := doimage.o +V := 0 + +HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99 -D_GNU_SOURCE + +ifeq (${DEBUG},1) + HOSTCCFLAGS += -g -O0 -DDEBUG +else + HOSTCCFLAGS += -O2 +endif + +ifeq (${V},0) + Q := @ +else + Q := +endif + +HOSTCC := gcc + +.PHONY: all clean distclean + +all: ${PROJECT} + +${PROJECT}: ${OBJECTS} Makefile + @echo " HOSTLD $@" + ${Q}${HOSTCC} ${OBJECTS} -o $@ + @${ECHO_BLANK_LINE} + @echo "Built $@ successfully" + @${ECHO_BLANK_LINE} + +%.o: %.c Makefile + @echo " HOSTCC $<" + ${Q}${HOSTCC} -c ${HOSTCCFLAGS} $< -o $@ + +clean: + $(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS}) + +distclean: clean diff --git a/tools/amlogic/doimage.c b/tools/amlogic/doimage.c new file mode 100644 index 000000000..b304038d1 --- /dev/null +++ b/tools/amlogic/doimage.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2019, Remi Pommarel + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include +#include +#include +#include + +#define DEFAULT_PROGNAME "doimage" +#define PROGNAME(argc, argv) (((argc) >= 1) ? ((argv)[0]) : DEFAULT_PROGNAME) + +#define BL31_MAGIC 0x12348765 +#define BL31_LOADADDR 0x05100000 +#define BUFLEN 512 + +static inline void usage(char const *prog) +{ + fprintf(stderr, "Usage: %s \n", prog); +} + +static inline int fdwrite(int fd, uint8_t *data, size_t len) +{ + ssize_t nr; + size_t l; + int ret = -1; + + for (l = 0; l < len; l += nr) { + nr = write(fd, data + l, len - l); + if (nr < 0) { + perror("Cannot write to bl31.img"); + goto out; + } + } + + ret = 0; +out: + return ret; +} + +int main(int argc, char **argv) +{ + int fin, fout, ret = -1; + ssize_t len; + uint32_t data; + uint8_t buf[BUFLEN]; + + if (argc != 3) { + usage(PROGNAME(argc, argv)); + goto out; + } + + fin = open(argv[1], O_RDONLY); + if (fin < 0) { + perror("Cannot open bl31.bin"); + goto out; + } + + fout = open(argv[2], O_WRONLY | O_CREAT, 0660); + if (fout < 0) { + perror("Cannot open bl31.img"); + goto closefin; + } + + data = htole32(BL31_MAGIC); + if (fdwrite(fout, (uint8_t *)&data, sizeof(data)) < 0) + goto closefout; + + lseek(fout, 8, SEEK_SET); + data = htole32(BL31_LOADADDR); + if (fdwrite(fout, (uint8_t *)&data, sizeof(data)) < 0) + goto closefout; + + lseek(fout, 0x200, SEEK_SET); + while ((len = read(fin, buf, sizeof(buf))) > 0) + if (fdwrite(fout, buf, len) < 0) + goto closefout; + if (len < 0) { + perror("Cannot read bl31.bin"); + goto closefout; + } + + ret = 0; + +closefout: + close(fout); +closefin: + close(fin); +out: + return ret; +} diff --git a/tools/meson/Makefile b/tools/meson/Makefile deleted file mode 100644 index 1a1d1f812..000000000 --- a/tools/meson/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# Copyright (C) 2019 Remi Pommarel -# -# SPDX-License-Identifier: BSD-3-Clause -# https://spdx.org/licenses -# -MAKE_HELPERS_DIRECTORY := ../../make_helpers/ -include ${MAKE_HELPERS_DIRECTORY}build_macros.mk -include ${MAKE_HELPERS_DIRECTORY}build_env.mk - -PROJECT := doimage${BIN_EXT} -OBJECTS := doimage.o -V := 0 - -HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99 -D_GNU_SOURCE - -ifeq (${DEBUG},1) - HOSTCCFLAGS += -g -O0 -DDEBUG -else - HOSTCCFLAGS += -O2 -endif - -ifeq (${V},0) - Q := @ -else - Q := -endif - -HOSTCC := gcc - -.PHONY: all clean distclean - -all: ${PROJECT} - -${PROJECT}: ${OBJECTS} Makefile - @echo " HOSTLD $@" - ${Q}${HOSTCC} ${OBJECTS} -o $@ - @${ECHO_BLANK_LINE} - @echo "Built $@ successfully" - @${ECHO_BLANK_LINE} - -%.o: %.c Makefile - @echo " HOSTCC $<" - ${Q}${HOSTCC} -c ${HOSTCCFLAGS} $< -o $@ - -clean: - $(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS}) - -distclean: clean diff --git a/tools/meson/doimage.c b/tools/meson/doimage.c deleted file mode 100644 index b304038d1..000000000 --- a/tools/meson/doimage.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2019, Remi Pommarel - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include -#include -#include -#include -#include -#include - -#define DEFAULT_PROGNAME "doimage" -#define PROGNAME(argc, argv) (((argc) >= 1) ? ((argv)[0]) : DEFAULT_PROGNAME) - -#define BL31_MAGIC 0x12348765 -#define BL31_LOADADDR 0x05100000 -#define BUFLEN 512 - -static inline void usage(char const *prog) -{ - fprintf(stderr, "Usage: %s \n", prog); -} - -static inline int fdwrite(int fd, uint8_t *data, size_t len) -{ - ssize_t nr; - size_t l; - int ret = -1; - - for (l = 0; l < len; l += nr) { - nr = write(fd, data + l, len - l); - if (nr < 0) { - perror("Cannot write to bl31.img"); - goto out; - } - } - - ret = 0; -out: - return ret; -} - -int main(int argc, char **argv) -{ - int fin, fout, ret = -1; - ssize_t len; - uint32_t data; - uint8_t buf[BUFLEN]; - - if (argc != 3) { - usage(PROGNAME(argc, argv)); - goto out; - } - - fin = open(argv[1], O_RDONLY); - if (fin < 0) { - perror("Cannot open bl31.bin"); - goto out; - } - - fout = open(argv[2], O_WRONLY | O_CREAT, 0660); - if (fout < 0) { - perror("Cannot open bl31.img"); - goto closefin; - } - - data = htole32(BL31_MAGIC); - if (fdwrite(fout, (uint8_t *)&data, sizeof(data)) < 0) - goto closefout; - - lseek(fout, 8, SEEK_SET); - data = htole32(BL31_LOADADDR); - if (fdwrite(fout, (uint8_t *)&data, sizeof(data)) < 0) - goto closefout; - - lseek(fout, 0x200, SEEK_SET); - while ((len = read(fin, buf, sizeof(buf))) > 0) - if (fdwrite(fout, buf, len) < 0) - goto closefout; - if (len < 0) { - perror("Cannot read bl31.bin"); - goto closefout; - } - - ret = 0; - -closefout: - close(fout); -closefin: - close(fin); -out: - return ret; -} -- cgit v1.2.3 From 1b25019896abaf79053fa4c12c1df7029f1eb2f0 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Fri, 23 Aug 2019 19:34:44 +0100 Subject: amlogic: Introduce directory parameters in the makefiles Make the platform name a parameter for the source directories. Besides a cosmetic fix, this is going to be helpful when reusing the same Makefile for different SoCs. Signed-off-by: Carlo Caione Change-Id: I307897a21800cca8ad68a5ab8972d27e9356ff2a --- plat/amlogic/gxbb/platform.mk | 33 ++++++++++++++++++--------------- plat/amlogic/gxl/platform.mk | 39 +++++++++++++++++++++------------------ 2 files changed, 39 insertions(+), 33 deletions(-) diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk index 06aaaba3f..5ab4d5279 100644 --- a/plat/amlogic/gxbb/platform.mk +++ b/plat/amlogic/gxbb/platform.mk @@ -6,29 +6,32 @@ include lib/xlat_tables_v2/xlat_tables.mk -PLAT_INCLUDES := -Iplat/amlogic/gxbb/include +AML_PLAT := plat/amlogic +AML_PLAT_SOC := ${AML_PLAT}/${PLAT} -GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ +PLAT_INCLUDES := -I${AML_PLAT_SOC}/include + +GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/v2/gicv2_helpers.c \ plat/common/plat_gicv2.c PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ - plat/amlogic/gxbb/gxbb_common.c \ - plat/amlogic/gxbb/gxbb_topology.c \ + ${AML_PLAT_SOC}/gxbb_common.c \ + ${AML_PLAT_SOC}/gxbb_topology.c \ ${XLAT_TABLES_LIB_SRCS} BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ - plat/amlogic/gxbb/aarch64/gxbb_helpers.S \ - plat/amlogic/gxbb/gxbb_bl31_setup.c \ - plat/amlogic/gxbb/gxbb_efuse.c \ - plat/amlogic/gxbb/gxbb_mhu.c \ - plat/amlogic/gxbb/gxbb_pm.c \ - plat/amlogic/gxbb/gxbb_scpi.c \ - plat/amlogic/gxbb/gxbb_sip_svc.c \ - plat/amlogic/gxbb/gxbb_thermal.c \ - ${GXBB_GIC_SOURCES} + ${AML_PLAT_SOC}/aarch64/gxbb_helpers.S \ + ${AML_PLAT_SOC}/gxbb_bl31_setup.c \ + ${AML_PLAT_SOC}/gxbb_efuse.c \ + ${AML_PLAT_SOC}/gxbb_mhu.c \ + ${AML_PLAT_SOC}/gxbb_pm.c \ + ${AML_PLAT_SOC}/gxbb_scpi.c \ + ${AML_PLAT_SOC}/gxbb_sip_svc.c \ + ${AML_PLAT_SOC}/gxbb_thermal.c \ + ${GIC_SOURCES} # Tune compiler for Cortex-A53 ifeq ($(notdir $(CC)),armclang) @@ -61,9 +64,9 @@ USE_COHERENT_MEM := 1 # ------------------- ifneq (${RESET_TO_BL31}, 0) - $(error Error: gxbb needs RESET_TO_BL31=0) + $(error Error: ${PLAT} needs RESET_TO_BL31=0) endif ifeq (${ARCH},aarch32) - $(error Error: AArch32 not supported on gxbb) + $(error Error: AArch32 not supported on ${PLAT}) endif diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index 9cdf37ac9..41a62618b 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -6,35 +6,38 @@ include lib/xlat_tables_v2/xlat_tables.mk +AML_PLAT := plat/amlogic +AML_PLAT_SOC := ${AML_PLAT}/${PLAT} + DOIMAGEPATH ?= tools/amlogic DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ - -Iinclude/drivers/amlogic/gxl \ - -Iplat/amlogic/gxl/include + -Iinclude/drivers/amlogic/${PLAT} \ + -I${AML_PLAT_SOC}/include -GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ +GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/v2/gicv2_helpers.c \ plat/common/plat_gicv2.c -PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ - plat/amlogic/gxl/gxl_common.c \ - plat/amlogic/gxl/gxl_topology.c \ +PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ + ${AML_PLAT_SOC}/gxl_common.c \ + ${AML_PLAT_SOC}/gxl_topology.c \ ${XLAT_TABLES_LIB_SRCS} BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ - plat/amlogic/gxl/aarch64/gxl_helpers.S \ - plat/amlogic/gxl/gxl_bl31_setup.c \ - plat/amlogic/gxl/gxl_efuse.c \ - plat/amlogic/gxl/gxl_mhu.c \ - plat/amlogic/gxl/gxl_pm.c \ - plat/amlogic/gxl/gxl_scpi.c \ - plat/amlogic/gxl/gxl_sip_svc.c \ - plat/amlogic/gxl/gxl_thermal.c \ - drivers/amlogic/gxl/crypto/sha_dma.c \ - ${GXBB_GIC_SOURCES} + ${AML_PLAT_SOC}/aarch64/gxl_helpers.S \ + ${AML_PLAT_SOC}/gxl_bl31_setup.c \ + ${AML_PLAT_SOC}/gxl_efuse.c \ + ${AML_PLAT_SOC}/gxl_mhu.c \ + ${AML_PLAT_SOC}/gxl_pm.c \ + ${AML_PLAT_SOC}/gxl_scpi.c \ + ${AML_PLAT_SOC}/gxl_sip_svc.c \ + ${AML_PLAT_SOC}/gxl_thermal.c \ + drivers/amlogic/${PLAT}/crypto/sha_dma.c \ + ${GIC_SOURCES} # Tune compiler for Cortex-A53 ifeq ($(notdir $(CC)),armclang) @@ -66,11 +69,11 @@ USE_COHERENT_MEM := 1 # ------------------- ifneq (${RESET_TO_BL31}, 0) - $(error Error: gxl needs RESET_TO_BL31=0) + $(error Error: ${PLAT} needs RESET_TO_BL31=0) endif ifeq (${ARCH},aarch32) - $(error Error: AArch32 not supported on gxl) + $(error Error: AArch32 not supported on ${PLAT}) endif all: ${BUILD_PLAT}/bl31.img -- cgit v1.2.3 From 40fac1ab4cb14bdd27e076eef48b6290d8a9d454 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Fri, 23 Aug 2019 20:02:32 +0100 Subject: amlogic: Move assembly helpers to common directory The assembly helpers are common to all the amlogic SoCs. Move the .S file to the common directory. Signed-off-by: Carlo Caione Change-Id: I0d8616a7ae22dbcb14848cefd0149b6bb5814ea6 --- plat/amlogic/common/aarch64/aml_helpers.S | 97 +++++++++++++++++++++++++++++++ plat/amlogic/gxbb/aarch64/gxbb_helpers.S | 97 ------------------------------- plat/amlogic/gxbb/platform.mk | 3 +- plat/amlogic/gxl/aarch64/gxl_helpers.S | 97 ------------------------------- plat/amlogic/gxl/platform.mk | 3 +- 5 files changed, 101 insertions(+), 196 deletions(-) create mode 100644 plat/amlogic/common/aarch64/aml_helpers.S delete mode 100644 plat/amlogic/gxbb/aarch64/gxbb_helpers.S delete mode 100644 plat/amlogic/gxl/aarch64/gxl_helpers.S diff --git a/plat/amlogic/common/aarch64/aml_helpers.S b/plat/amlogic/common/aarch64/aml_helpers.S new file mode 100644 index 000000000..760d6c46d --- /dev/null +++ b/plat/amlogic/common/aarch64/aml_helpers.S @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + + .globl plat_crash_console_flush + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl platform_mem_init + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_reset_handler + .globl plat_gxbb_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void); + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_gxbb_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); + * ----------------------------------------------------- + */ +func plat_gxbb_calc_core_pos + and x0, x0, #MPIDR_CPU_MASK + ret +endfunc plat_gxbb_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary(void); + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #GXBB_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + + /* --------------------------------------------- + * void platform_mem_init(void); + * --------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, GXBB_UART0_AO_BASE + mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ + mov_imm x2, GXBB_UART_BAUDRATE + b console_meson_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, GXBB_UART0_AO_BASE + b console_meson_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush() + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x0, GXBB_UART0_AO_BASE + b console_meson_core_flush +endfunc plat_crash_console_flush + + /* --------------------------------------------- + * void plat_reset_handler(void); + * --------------------------------------------- + */ +func plat_reset_handler + ret +endfunc plat_reset_handler diff --git a/plat/amlogic/gxbb/aarch64/gxbb_helpers.S b/plat/amlogic/gxbb/aarch64/gxbb_helpers.S deleted file mode 100644 index 760d6c46d..000000000 --- a/plat/amlogic/gxbb/aarch64/gxbb_helpers.S +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - - .globl plat_crash_console_flush - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl platform_mem_init - .globl plat_is_my_cpu_primary - .globl plat_my_core_pos - .globl plat_reset_handler - .globl plat_gxbb_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_my_core_pos(void); - * ----------------------------------------------------- - */ -func plat_my_core_pos - mrs x0, mpidr_el1 - b plat_gxbb_calc_core_pos -endfunc plat_my_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); - * ----------------------------------------------------- - */ -func plat_gxbb_calc_core_pos - and x0, x0, #MPIDR_CPU_MASK - ret -endfunc plat_gxbb_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_is_my_cpu_primary(void); - * ----------------------------------------------------- - */ -func plat_is_my_cpu_primary - mrs x0, mpidr_el1 - and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #GXBB_PRIMARY_CPU - cset w0, eq - ret -endfunc plat_is_my_cpu_primary - - /* --------------------------------------------- - * void platform_mem_init(void); - * --------------------------------------------- - */ -func platform_mem_init - ret -endfunc platform_mem_init - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, GXBB_UART0_AO_BASE - mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ - mov_imm x2, GXBB_UART_BAUDRATE - b console_meson_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(int c) - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, GXBB_UART0_AO_BASE - b console_meson_core_putc -endfunc plat_crash_console_putc - - /* --------------------------------------------- - * int plat_crash_console_flush() - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func plat_crash_console_flush - mov_imm x0, GXBB_UART0_AO_BASE - b console_meson_core_flush -endfunc plat_crash_console_flush - - /* --------------------------------------------- - * void plat_reset_handler(void); - * --------------------------------------------- - */ -func plat_reset_handler - ret -endfunc plat_reset_handler diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk index 5ab4d5279..e69f3f631 100644 --- a/plat/amlogic/gxbb/platform.mk +++ b/plat/amlogic/gxbb/platform.mk @@ -8,6 +8,7 @@ include lib/xlat_tables_v2/xlat_tables.mk AML_PLAT := plat/amlogic AML_PLAT_SOC := ${AML_PLAT}/${PLAT} +AML_PLAT_COMMON := ${AML_PLAT}/common PLAT_INCLUDES := -I${AML_PLAT_SOC}/include @@ -23,7 +24,7 @@ PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ - ${AML_PLAT_SOC}/aarch64/gxbb_helpers.S \ + ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ ${AML_PLAT_SOC}/gxbb_bl31_setup.c \ ${AML_PLAT_SOC}/gxbb_efuse.c \ ${AML_PLAT_SOC}/gxbb_mhu.c \ diff --git a/plat/amlogic/gxl/aarch64/gxl_helpers.S b/plat/amlogic/gxl/aarch64/gxl_helpers.S deleted file mode 100644 index 760d6c46d..000000000 --- a/plat/amlogic/gxl/aarch64/gxl_helpers.S +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - - .globl plat_crash_console_flush - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl platform_mem_init - .globl plat_is_my_cpu_primary - .globl plat_my_core_pos - .globl plat_reset_handler - .globl plat_gxbb_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_my_core_pos(void); - * ----------------------------------------------------- - */ -func plat_my_core_pos - mrs x0, mpidr_el1 - b plat_gxbb_calc_core_pos -endfunc plat_my_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); - * ----------------------------------------------------- - */ -func plat_gxbb_calc_core_pos - and x0, x0, #MPIDR_CPU_MASK - ret -endfunc plat_gxbb_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_is_my_cpu_primary(void); - * ----------------------------------------------------- - */ -func plat_is_my_cpu_primary - mrs x0, mpidr_el1 - and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #GXBB_PRIMARY_CPU - cset w0, eq - ret -endfunc plat_is_my_cpu_primary - - /* --------------------------------------------- - * void platform_mem_init(void); - * --------------------------------------------- - */ -func platform_mem_init - ret -endfunc platform_mem_init - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, GXBB_UART0_AO_BASE - mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ - mov_imm x2, GXBB_UART_BAUDRATE - b console_meson_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(int c) - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, GXBB_UART0_AO_BASE - b console_meson_core_putc -endfunc plat_crash_console_putc - - /* --------------------------------------------- - * int plat_crash_console_flush() - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func plat_crash_console_flush - mov_imm x0, GXBB_UART0_AO_BASE - b console_meson_core_flush -endfunc plat_crash_console_flush - - /* --------------------------------------------- - * void plat_reset_handler(void); - * --------------------------------------------- - */ -func plat_reset_handler - ret -endfunc plat_reset_handler diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index 41a62618b..f699381d5 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -8,6 +8,7 @@ include lib/xlat_tables_v2/xlat_tables.mk AML_PLAT := plat/amlogic AML_PLAT_SOC := ${AML_PLAT}/${PLAT} +AML_PLAT_COMMON := ${AML_PLAT}/common DOIMAGEPATH ?= tools/amlogic DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage @@ -28,7 +29,7 @@ PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ - ${AML_PLAT_SOC}/aarch64/gxl_helpers.S \ + ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ ${AML_PLAT_SOC}/gxl_bl31_setup.c \ ${AML_PLAT_SOC}/gxl_efuse.c \ ${AML_PLAT_SOC}/gxl_mhu.c \ -- cgit v1.2.3 From 01b2a7fc3256dcec74e2f147ed28a37ad4df05fe Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 17:17:30 +0100 Subject: amlogic: Move the SHA256 DMA driver to common directory The SHA256 DMA driver can be used by multiple SoCs. Move it to the common directory. Signed-off-by: Carlo Caione Change-Id: I96319eeeeeebd503ef0dcb07c0e4ff6a67afeaa5 --- drivers/amlogic/crypto/sha_dma.c | 185 +++++++++++++++++++++++++++ drivers/amlogic/gxl/crypto/sha_dma.c | 185 --------------------------- include/drivers/amlogic/crypto/sha_dma.h | 36 ++++++ include/drivers/amlogic/gxl/crypto/sha_dma.h | 36 ------ plat/amlogic/gxl/platform.mk | 3 +- 5 files changed, 222 insertions(+), 223 deletions(-) create mode 100644 drivers/amlogic/crypto/sha_dma.c delete mode 100644 drivers/amlogic/gxl/crypto/sha_dma.c create mode 100644 include/drivers/amlogic/crypto/sha_dma.h delete mode 100644 include/drivers/amlogic/gxl/crypto/sha_dma.h diff --git a/drivers/amlogic/crypto/sha_dma.c b/drivers/amlogic/crypto/sha_dma.c new file mode 100644 index 000000000..d48ded987 --- /dev/null +++ b/drivers/amlogic/crypto/sha_dma.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2019, Remi Pommarel + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#define AML_SHA_DMA_BASE 0xc883e000 + +#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08) +#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18) + +#define ASD_MODE_SHA224 0x7 +#define ASD_MODE_SHA256 0x6 + +/* SHA DMA descriptor */ +struct asd_desc { + uint32_t cfg; + uint32_t src; + uint32_t dst; +}; +#define ASD_DESC_GET(x, msk, off) (((x) >> (off)) & (msk)) +#define ASD_DESC_SET(x, v, msk, off) \ + ((x) = ((x) & ~((msk) << (off))) | (((v) & (msk)) << (off))) + +#define ASD_DESC_LEN_OFF 0 +#define ASD_DESC_LEN_MASK 0x1ffff +#define ASD_DESC_LEN(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF)) +#define ASD_DESC_LEN_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF)) + +#define ASD_DESC_IRQ_OFF 17 +#define ASD_DESC_IRQ_MASK 0x1 +#define ASD_DESC_IRQ(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF)) +#define ASD_DESC_IRQ_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF)) + +#define ASD_DESC_EOD_OFF 18 +#define ASD_DESC_EOD_MASK 0x1 +#define ASD_DESC_EOD(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF)) +#define ASD_DESC_EOD_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF)) + +#define ASD_DESC_LOOP_OFF 19 +#define ASD_DESC_LOOP_MASK 0x1 +#define ASD_DESC_LOOP(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF)) +#define ASD_DESC_LOOP_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF)) + +#define ASD_DESC_MODE_OFF 20 +#define ASD_DESC_MODE_MASK 0xf +#define ASD_DESC_MODE(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF)) +#define ASD_DESC_MODE_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF)) + +#define ASD_DESC_BEGIN_OFF 24 +#define ASD_DESC_BEGIN_MASK 0x1 +#define ASD_DESC_BEGIN(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_BEGIN_MASK, ASD_DESC_BEGIN_OFF)) +#define ASD_DESC_BEGIN_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_BEGIN_MASK, ASD_DESC_BEGIN_OFF)) + +#define ASD_DESC_END_OFF 25 +#define ASD_DESC_END_MASK 0x1 +#define ASD_DESC_END(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_END_MASK, ASD_DESC_END_OFF)) +#define ASD_DESC_END_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_END_MASK, ASD_DESC_END_OFF)) + +#define ASD_DESC_OP_OFF 26 +#define ASD_DESC_OP_MASK 0x2 +#define ASD_DESC_OP(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_OP_MASK, ASD_DESC_OP_OFF)) +#define ASD_DESC_OP_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_OP_MASK, ASD_DESC_OP_OFF)) + +#define ASD_DESC_ENCONLY_OFF 28 +#define ASD_DESC_ENCONLY_MASK 0x1 +#define ASD_DESC_ENCONLY(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_ENCONLY_MASK, ASD_DESC_ENCONLY_OFF)) +#define ASD_DESC_ENCONLY_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_ENCONLY_MASK, ASD_DESC_ENCONLY_OFF)) + +#define ASD_DESC_BLOCK_OFF 29 +#define ASD_DESC_BLOCK_MASK 0x1 +#define ASD_DESC_BLOCK(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_BLOCK_MASK, ASD_DESC_BLOCK_OFF)) +#define ASD_DESC_BLOCK_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_BLOCK_MASK, ASD_DESC_BLOCK_OFF)) + +#define ASD_DESC_ERR_OFF 30 +#define ASD_DESC_ERR_MASK 0x1 +#define ASD_DESC_ERR(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF)) +#define ASD_DESC_ERR_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF)) + +#define ASD_DESC_OWNER_OFF 31u +#define ASD_DESC_OWNER_MASK 0x1u +#define ASD_DESC_OWNER(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF)) +#define ASD_DESC_OWNER_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF)) + +static void asd_compute_sha(struct asd_ctx *ctx, void *data, size_t len, + int finalize) +{ + /* Make it cache line size aligned ? */ + struct asd_desc desc = { + .src = (uint32_t)(uintptr_t)data, + .dst = (uint32_t)(uintptr_t)ctx->digest, + }; + + /* Check data address is 32bit compatible */ + assert((uintptr_t)data == (uintptr_t)desc.src); + assert((uintptr_t)ctx->digest == (uintptr_t)desc.dst); + assert((uintptr_t)&desc == (uintptr_t)&desc); + + ASD_DESC_LEN_SET(&desc, len); + ASD_DESC_OWNER_SET(&desc, 1u); + ASD_DESC_ENCONLY_SET(&desc, 1); + ASD_DESC_EOD_SET(&desc, 1); + if (ctx->started == 0) { + ASD_DESC_BEGIN_SET(&desc, 1); + ctx->started = 1; + } + if (finalize) { + ASD_DESC_END_SET(&desc, 1); + ctx->started = 0; + } + if (ctx->mode == ASM_SHA224) + ASD_DESC_MODE_SET(&desc, ASD_MODE_SHA224); + else + ASD_DESC_MODE_SET(&desc, ASD_MODE_SHA256); + + flush_dcache_range((uintptr_t)&desc, sizeof(desc)); + flush_dcache_range((uintptr_t)data, len); + + mmio_write_32(AML_SHA_DMA_STATUS, 0xf); + mmio_write_32(AML_SHA_DMA_DESC, ((uintptr_t)&desc) | 2); + while (mmio_read_32(AML_SHA_DMA_STATUS) == 0) + continue; + flush_dcache_range((uintptr_t)ctx->digest, SHA256_HASHSZ); +} + +void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len) +{ + size_t nr; + + if (ctx->blocksz) { + nr = MIN(len, SHA256_BLOCKSZ - ctx->blocksz); + memcpy(ctx->block + ctx->blocksz, data, nr); + ctx->blocksz += nr; + len -= nr; + data += nr; + } + + if (ctx->blocksz == SHA256_BLOCKSZ) { + asd_compute_sha(ctx, ctx->block, SHA256_BLOCKSZ, 0); + ctx->blocksz = 0; + } + + asd_compute_sha(ctx, data, len & ~(SHA256_BLOCKSZ - 1), 0); + data += len & ~(SHA256_BLOCKSZ - 1); + + if (len & (SHA256_BLOCKSZ - 1)) { + nr = len & (SHA256_BLOCKSZ - 1); + memcpy(ctx->block + ctx->blocksz, data, nr); + ctx->blocksz += nr; + } +} + +void asd_sha_finalize(struct asd_ctx *ctx) +{ + asd_compute_sha(ctx, ctx->block, ctx->blocksz, 1); +} diff --git a/drivers/amlogic/gxl/crypto/sha_dma.c b/drivers/amlogic/gxl/crypto/sha_dma.c deleted file mode 100644 index a969dea74..000000000 --- a/drivers/amlogic/gxl/crypto/sha_dma.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2019, Remi Pommarel - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -#define AML_SHA_DMA_BASE 0xc883e000 - -#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08) -#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18) - -#define ASD_MODE_SHA224 0x7 -#define ASD_MODE_SHA256 0x6 - -/* SHA DMA descriptor */ -struct asd_desc { - uint32_t cfg; - uint32_t src; - uint32_t dst; -}; -#define ASD_DESC_GET(x, msk, off) (((x) >> (off)) & (msk)) -#define ASD_DESC_SET(x, v, msk, off) \ - ((x) = ((x) & ~((msk) << (off))) | (((v) & (msk)) << (off))) - -#define ASD_DESC_LEN_OFF 0 -#define ASD_DESC_LEN_MASK 0x1ffff -#define ASD_DESC_LEN(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF)) -#define ASD_DESC_LEN_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF)) - -#define ASD_DESC_IRQ_OFF 17 -#define ASD_DESC_IRQ_MASK 0x1 -#define ASD_DESC_IRQ(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF)) -#define ASD_DESC_IRQ_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF)) - -#define ASD_DESC_EOD_OFF 18 -#define ASD_DESC_EOD_MASK 0x1 -#define ASD_DESC_EOD(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF)) -#define ASD_DESC_EOD_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF)) - -#define ASD_DESC_LOOP_OFF 19 -#define ASD_DESC_LOOP_MASK 0x1 -#define ASD_DESC_LOOP(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF)) -#define ASD_DESC_LOOP_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF)) - -#define ASD_DESC_MODE_OFF 20 -#define ASD_DESC_MODE_MASK 0xf -#define ASD_DESC_MODE(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF)) -#define ASD_DESC_MODE_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF)) - -#define ASD_DESC_BEGIN_OFF 24 -#define ASD_DESC_BEGIN_MASK 0x1 -#define ASD_DESC_BEGIN(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_BEGIN_MASK, ASD_DESC_BEGIN_OFF)) -#define ASD_DESC_BEGIN_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_BEGIN_MASK, ASD_DESC_BEGIN_OFF)) - -#define ASD_DESC_END_OFF 25 -#define ASD_DESC_END_MASK 0x1 -#define ASD_DESC_END(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_END_MASK, ASD_DESC_END_OFF)) -#define ASD_DESC_END_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_END_MASK, ASD_DESC_END_OFF)) - -#define ASD_DESC_OP_OFF 26 -#define ASD_DESC_OP_MASK 0x2 -#define ASD_DESC_OP(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_OP_MASK, ASD_DESC_OP_OFF)) -#define ASD_DESC_OP_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_OP_MASK, ASD_DESC_OP_OFF)) - -#define ASD_DESC_ENCONLY_OFF 28 -#define ASD_DESC_ENCONLY_MASK 0x1 -#define ASD_DESC_ENCONLY(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_ENCONLY_MASK, ASD_DESC_ENCONLY_OFF)) -#define ASD_DESC_ENCONLY_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_ENCONLY_MASK, ASD_DESC_ENCONLY_OFF)) - -#define ASD_DESC_BLOCK_OFF 29 -#define ASD_DESC_BLOCK_MASK 0x1 -#define ASD_DESC_BLOCK(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_BLOCK_MASK, ASD_DESC_BLOCK_OFF)) -#define ASD_DESC_BLOCK_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_BLOCK_MASK, ASD_DESC_BLOCK_OFF)) - -#define ASD_DESC_ERR_OFF 30 -#define ASD_DESC_ERR_MASK 0x1 -#define ASD_DESC_ERR(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF)) -#define ASD_DESC_ERR_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF)) - -#define ASD_DESC_OWNER_OFF 31u -#define ASD_DESC_OWNER_MASK 0x1u -#define ASD_DESC_OWNER(d) \ - (ASD_DESC_GET((d)->cfg, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF)) -#define ASD_DESC_OWNER_SET(d, v) \ - (ASD_DESC_SET((d)->cfg, v, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF)) - -static void asd_compute_sha(struct asd_ctx *ctx, void *data, size_t len, - int finalize) -{ - /* Make it cache line size aligned ? */ - struct asd_desc desc = { - .src = (uint32_t)(uintptr_t)data, - .dst = (uint32_t)(uintptr_t)ctx->digest, - }; - - /* Check data address is 32bit compatible */ - assert((uintptr_t)data == (uintptr_t)desc.src); - assert((uintptr_t)ctx->digest == (uintptr_t)desc.dst); - assert((uintptr_t)&desc == (uintptr_t)&desc); - - ASD_DESC_LEN_SET(&desc, len); - ASD_DESC_OWNER_SET(&desc, 1u); - ASD_DESC_ENCONLY_SET(&desc, 1); - ASD_DESC_EOD_SET(&desc, 1); - if (ctx->started == 0) { - ASD_DESC_BEGIN_SET(&desc, 1); - ctx->started = 1; - } - if (finalize) { - ASD_DESC_END_SET(&desc, 1); - ctx->started = 0; - } - if (ctx->mode == ASM_SHA224) - ASD_DESC_MODE_SET(&desc, ASD_MODE_SHA224); - else - ASD_DESC_MODE_SET(&desc, ASD_MODE_SHA256); - - flush_dcache_range((uintptr_t)&desc, sizeof(desc)); - flush_dcache_range((uintptr_t)data, len); - - mmio_write_32(AML_SHA_DMA_STATUS, 0xf); - mmio_write_32(AML_SHA_DMA_DESC, ((uintptr_t)&desc) | 2); - while (mmio_read_32(AML_SHA_DMA_STATUS) == 0) - continue; - flush_dcache_range((uintptr_t)ctx->digest, SHA256_HASHSZ); -} - -void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len) -{ - size_t nr; - - if (ctx->blocksz) { - nr = MIN(len, SHA256_BLOCKSZ - ctx->blocksz); - memcpy(ctx->block + ctx->blocksz, data, nr); - ctx->blocksz += nr; - len -= nr; - data += nr; - } - - if (ctx->blocksz == SHA256_BLOCKSZ) { - asd_compute_sha(ctx, ctx->block, SHA256_BLOCKSZ, 0); - ctx->blocksz = 0; - } - - asd_compute_sha(ctx, data, len & ~(SHA256_BLOCKSZ - 1), 0); - data += len & ~(SHA256_BLOCKSZ - 1); - - if (len & (SHA256_BLOCKSZ - 1)) { - nr = len & (SHA256_BLOCKSZ - 1); - memcpy(ctx->block + ctx->blocksz, data, nr); - ctx->blocksz += nr; - } -} - -void asd_sha_finalize(struct asd_ctx *ctx) -{ - asd_compute_sha(ctx, ctx->block, ctx->blocksz, 1); -} diff --git a/include/drivers/amlogic/crypto/sha_dma.h b/include/drivers/amlogic/crypto/sha_dma.h new file mode 100644 index 000000000..52129a61f --- /dev/null +++ b/include/drivers/amlogic/crypto/sha_dma.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2019, Remi Pommarel + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef SHA_DMA_H +#define SHA_DMA_H + +#define SHA256_HASHSZ 32 +#define SHA256_BLOCKSZ 0x40 + +enum ASD_MODE { + ASM_INVAL, + ASM_SHA256, + ASM_SHA224, +}; + +struct asd_ctx { + uint8_t digest[SHA256_HASHSZ]; + uint8_t block[SHA256_BLOCKSZ]; + size_t blocksz; + enum ASD_MODE mode; + uint8_t started; +}; + +static inline void asd_sha_init(struct asd_ctx *ctx, enum ASD_MODE mode) +{ + ctx->started = 0; + ctx->mode = mode; + ctx->blocksz = 0; +} + +void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len); +void asd_sha_finalize(struct asd_ctx *ctx); + +#endif diff --git a/include/drivers/amlogic/gxl/crypto/sha_dma.h b/include/drivers/amlogic/gxl/crypto/sha_dma.h deleted file mode 100644 index 52129a61f..000000000 --- a/include/drivers/amlogic/gxl/crypto/sha_dma.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2019, Remi Pommarel - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef SHA_DMA_H -#define SHA_DMA_H - -#define SHA256_HASHSZ 32 -#define SHA256_BLOCKSZ 0x40 - -enum ASD_MODE { - ASM_INVAL, - ASM_SHA256, - ASM_SHA224, -}; - -struct asd_ctx { - uint8_t digest[SHA256_HASHSZ]; - uint8_t block[SHA256_BLOCKSZ]; - size_t blocksz; - enum ASD_MODE mode; - uint8_t started; -}; - -static inline void asd_sha_init(struct asd_ctx *ctx, enum ASD_MODE mode) -{ - ctx->started = 0; - ctx->mode = mode; - ctx->blocksz = 0; -} - -void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len); -void asd_sha_finalize(struct asd_ctx *ctx); - -#endif diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index f699381d5..a7cda7708 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -14,7 +14,6 @@ DOIMAGEPATH ?= tools/amlogic DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ - -Iinclude/drivers/amlogic/${PLAT} \ -I${AML_PLAT_SOC}/include GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ @@ -37,7 +36,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${AML_PLAT_SOC}/gxl_scpi.c \ ${AML_PLAT_SOC}/gxl_sip_svc.c \ ${AML_PLAT_SOC}/gxl_thermal.c \ - drivers/amlogic/${PLAT}/crypto/sha_dma.c \ + drivers/amlogic/crypto/sha_dma.c \ ${GIC_SOURCES} # Tune compiler for Cortex-A53 -- cgit v1.2.3 From 69b315aabf74f9492f9323b9e6c7e5cc4322bada Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 17:28:23 +0100 Subject: amlogic: Move SCPI code to common directory The SCPI code is the same between GXBB and GXL. No need to have it replicated for each SoCs. Move it to the common directory. Signed-off-by: Carlo Caione Change-Id: I7e416caf1e9538b3ce7702c0363ee00a054e2451 --- plat/amlogic/common/aml_scpi.c | 211 ++++++++++++++++++++++++++++++ plat/amlogic/common/include/aml_private.h | 40 ++++++ plat/amlogic/gxbb/gxbb_scpi.c | 139 -------------------- plat/amlogic/gxbb/platform.mk | 6 +- plat/amlogic/gxl/gxl_scpi.c | 211 ------------------------------ plat/amlogic/gxl/platform.mk | 5 +- 6 files changed, 258 insertions(+), 354 deletions(-) create mode 100644 plat/amlogic/common/aml_scpi.c create mode 100644 plat/amlogic/common/include/aml_private.h delete mode 100644 plat/amlogic/gxbb/gxbb_scpi.c delete mode 100644 plat/amlogic/gxl/gxl_scpi.c diff --git a/plat/amlogic/common/aml_scpi.c b/plat/amlogic/common/aml_scpi.c new file mode 100644 index 000000000..672702967 --- /dev/null +++ b/plat/amlogic/common/aml_scpi.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +#include "aml_private.h" + +#define SIZE_SHIFT 20 +#define SIZE_MASK 0x1FF +#define SIZE_FWBLK 0x200UL + +/* + * Note: The Amlogic SCP firmware uses the legacy SCPI protocol. + */ +#define SCPI_CMD_SET_CSS_POWER_STATE 0x04 +#define SCPI_CMD_SET_SYS_POWER_STATE 0x08 + +#define SCPI_CMD_JTAG_SET_STATE 0xC0 +#define SCPI_CMD_EFUSE_READ 0xC2 + +#define SCPI_CMD_COPY_FW 0xd4 +#define SCPI_CMD_SET_FW_ADDR 0xd3 +#define SCPI_CMD_FW_SIZE 0xd2 + +static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) +{ + return command | (size << SIZE_SHIFT); +} + +static void scpi_secure_message_send(uint32_t command, uint32_t size) +{ + mhu_secure_message_send(scpi_cmd(command, size)); +} + +uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) +{ + uint32_t response = mhu_secure_message_wait(); + + size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; + + response &= ~(SIZE_MASK << SIZE_SHIFT); + + if (size_out != NULL) + *size_out = size; + + if (message_out != NULL) + *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD; + + return response; +} + +void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state) +{ + uint32_t state = (mpidr & 0x0F) | /* CPU ID */ + ((mpidr & 0xF00) >> 4) | /* Cluster ID */ + (cpu_state << 8) | + (cluster_state << 12) | + (css_state << 16); + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} + +uint32_t scpi_sys_power_state(uint64_t system_state) +{ + uint32_t *response; + size_t size; + + mhu_secure_message_start(); + mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); + scpi_secure_message_receive((void *)&response, &size); + mhu_secure_message_end(); + + return *response; +} + +void scpi_jtag_set_state(uint32_t state, uint8_t select) +{ + assert(state <= GXBB_JTAG_STATE_OFF); + + if (select > GXBB_JTAG_A53_EE) { + WARN("BL31: Invalid JTAG select (0x%x).\n", select); + return; + } + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, + (state << 8) | (uint32_t)select); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} + +uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) +{ + uint32_t *response; + size_t resp_size; + + if (size > 0x1FC) + return 0; + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); + scpi_secure_message_receive((void *)&response, &resp_size); + mhu_secure_message_end(); + + /* + * response[0] is the size of the response message. + * response[1 ... N] are the contents. + */ + if (*response != 0) + memcpy(dst, response + 1, *response); + + return *response; +} + +void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3) +{ + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); + mhu_secure_message_send(scpi_cmd(0xC3, 16)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} + +static inline void scpi_copy_scp_data(uint8_t *data, size_t len) +{ + void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + size_t sz; + + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); + scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); + mhu_secure_message_wait(); + + for (sz = 0; sz < len; sz += SIZE_FWBLK) { + memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz)); + mhu_secure_message_send(SCPI_CMD_COPY_FW); + } +} + +static inline void scpi_set_scp_addr(uint64_t addr, size_t len) +{ + volatile uint64_t *dst = (uint64_t *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + + /* + * It is ok as GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as + * non cachable + */ + *dst = addr; + scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr)); + mhu_secure_message_wait(); + + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); + scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); + mhu_secure_message_wait(); +} + +static inline void scpi_send_fw_hash(uint8_t hash[], size_t len) +{ + void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + + memcpy(dst, hash, len); + mhu_secure_message_send(0xd0); + mhu_secure_message_send(0xd1); + mhu_secure_message_send(0xd5); + mhu_secure_message_end(); +} + +/** + * Upload a FW to SCP. + * + * @param addr: firmware data address + * @param size: size of firmware + * @param send: If set, actually copy the firmware in SCP memory otherwise only + * send the firmware address. + */ +void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send) +{ + struct asd_ctx ctx; + + asd_sha_init(&ctx, ASM_SHA256); + asd_sha_update(&ctx, (void *)addr, size); + asd_sha_finalize(&ctx); + + mhu_secure_message_start(); + if (send == 0) + scpi_set_scp_addr(addr, size); + else + scpi_copy_scp_data((void *)addr, size); + + scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest)); +} diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h new file mode 100644 index 000000000..6f1855f63 --- /dev/null +++ b/plat/amlogic/common/include/aml_private.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GXBB_PRIVATE_H +#define GXBB_PRIVATE_H + +#include +#include + +/* Utility functions */ +unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); +void gxbb_console_init(void); +void gxbb_setup_page_tables(void); + +/* MHU functions */ +void mhu_secure_message_start(void); +void mhu_secure_message_send(uint32_t msg); +uint32_t mhu_secure_message_wait(void); +void mhu_secure_message_end(void); +void mhu_secure_init(void); + +/* SCPI functions */ +void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state); +uint32_t scpi_sys_power_state(uint64_t system_state); +void scpi_jtag_set_state(uint32_t state, uint8_t select); +uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size); +void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3); +void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); + +/* Peripherals */ +void gxbb_thermal_unknown(void); +uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size); +uint64_t gxbb_efuse_user_max(void); + +#endif /* GXBB_PRIVATE_H */ diff --git a/plat/amlogic/gxbb/gxbb_scpi.c b/plat/amlogic/gxbb/gxbb_scpi.c deleted file mode 100644 index 83eeda29d..000000000 --- a/plat/amlogic/gxbb/gxbb_scpi.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include -#include - -#include "gxbb_private.h" - -#define SIZE_SHIFT 20 -#define SIZE_MASK 0x1FF - -/* - * Note: The Amlogic SCP firmware uses the legacy SCPI protocol. - */ -#define SCPI_CMD_SET_CSS_POWER_STATE 0x04 -#define SCPI_CMD_SET_SYS_POWER_STATE 0x08 - -#define SCPI_CMD_JTAG_SET_STATE 0xC0 -#define SCPI_CMD_EFUSE_READ 0xC2 - -static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) -{ - return command | (size << SIZE_SHIFT); -} - -void scpi_secure_message_send(uint32_t command, uint32_t size) -{ - mhu_secure_message_send(scpi_cmd(command, size)); -} - -uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) -{ - uint32_t response = mhu_secure_message_wait(); - - size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; - - response &= ~(SIZE_MASK << SIZE_SHIFT); - - if (size_out != NULL) - *size_out = size; - - if (message_out != NULL) - *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD; - - return response; -} - -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state) -{ - uint32_t state = (mpidr & 0x0F) | /* CPU ID */ - ((mpidr & 0xF00) >> 4) | /* Cluster ID */ - (cpu_state << 8) | - (cluster_state << 12) | - (css_state << 16); - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_sys_power_state(uint64_t system_state) -{ - uint32_t *response; - size_t size; - - mhu_secure_message_start(); - mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); - scpi_secure_message_receive((void *)&response, &size); - mhu_secure_message_end(); - - return *response; -} - -void scpi_jtag_set_state(uint32_t state, uint8_t select) -{ - assert(state <= GXBB_JTAG_STATE_OFF); - - if (select > GXBB_JTAG_A53_EE) { - WARN("BL31: Invalid JTAG select (0x%x).\n", select); - return; - } - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, - (state << 8) | (uint32_t)select); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) -{ - uint32_t *response; - size_t resp_size; - - if (size > 0x1FC) - return 0; - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); - scpi_secure_message_receive((void *)&response, &resp_size); - mhu_secure_message_end(); - - /* - * response[0] is the size of the response message. - * response[1 ... N] are the contents. - */ - if (*response != 0) - memcpy(dst, response + 1, *response); - - return *response; -} - -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3) -{ - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); - mhu_secure_message_send(scpi_cmd(0xC3, 16)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk index e69f3f631..2430f2340 100644 --- a/plat/amlogic/gxbb/platform.mk +++ b/plat/amlogic/gxbb/platform.mk @@ -10,7 +10,9 @@ AML_PLAT := plat/amlogic AML_PLAT_SOC := ${AML_PLAT}/${PLAT} AML_PLAT_COMMON := ${AML_PLAT}/common -PLAT_INCLUDES := -I${AML_PLAT_SOC}/include +PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ + -I${AML_PLAT_SOC}/include \ + -I${AML_PLAT_COMMON}/include GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ @@ -29,7 +31,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${AML_PLAT_SOC}/gxbb_efuse.c \ ${AML_PLAT_SOC}/gxbb_mhu.c \ ${AML_PLAT_SOC}/gxbb_pm.c \ - ${AML_PLAT_SOC}/gxbb_scpi.c \ + ${AML_PLAT_COMMON}/aml_scpi.c \ ${AML_PLAT_SOC}/gxbb_sip_svc.c \ ${AML_PLAT_SOC}/gxbb_thermal.c \ ${GIC_SOURCES} diff --git a/plat/amlogic/gxl/gxl_scpi.c b/plat/amlogic/gxl/gxl_scpi.c deleted file mode 100644 index 13d652436..000000000 --- a/plat/amlogic/gxl/gxl_scpi.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -#include "gxl_private.h" - -#define SIZE_SHIFT 20 -#define SIZE_MASK 0x1FF -#define SIZE_FWBLK 0x200UL - -/* - * Note: The Amlogic SCP firmware uses the legacy SCPI protocol. - */ -#define SCPI_CMD_SET_CSS_POWER_STATE 0x04 -#define SCPI_CMD_SET_SYS_POWER_STATE 0x08 - -#define SCPI_CMD_JTAG_SET_STATE 0xC0 -#define SCPI_CMD_EFUSE_READ 0xC2 - -#define SCPI_CMD_COPY_FW 0xd4 -#define SCPI_CMD_SET_FW_ADDR 0xd3 -#define SCPI_CMD_FW_SIZE 0xd2 - -static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) -{ - return command | (size << SIZE_SHIFT); -} - -static void scpi_secure_message_send(uint32_t command, uint32_t size) -{ - mhu_secure_message_send(scpi_cmd(command, size)); -} - -uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) -{ - uint32_t response = mhu_secure_message_wait(); - - size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; - - response &= ~(SIZE_MASK << SIZE_SHIFT); - - if (size_out != NULL) - *size_out = size; - - if (message_out != NULL) - *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD; - - return response; -} - -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state) -{ - uint32_t state = (mpidr & 0x0F) | /* CPU ID */ - ((mpidr & 0xF00) >> 4) | /* Cluster ID */ - (cpu_state << 8) | - (cluster_state << 12) | - (css_state << 16); - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_sys_power_state(uint64_t system_state) -{ - uint32_t *response; - size_t size; - - mhu_secure_message_start(); - mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); - scpi_secure_message_receive((void *)&response, &size); - mhu_secure_message_end(); - - return *response; -} - -void scpi_jtag_set_state(uint32_t state, uint8_t select) -{ - assert(state <= GXBB_JTAG_STATE_OFF); - - if (select > GXBB_JTAG_A53_EE) { - WARN("BL31: Invalid JTAG select (0x%x).\n", select); - return; - } - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, - (state << 8) | (uint32_t)select); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) -{ - uint32_t *response; - size_t resp_size; - - if (size > 0x1FC) - return 0; - - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); - scpi_secure_message_receive((void *)&response, &resp_size); - mhu_secure_message_end(); - - /* - * response[0] is the size of the response message. - * response[1 ... N] are the contents. - */ - if (*response != 0) - memcpy(dst, response + 1, *response); - - return *response; -} - -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3) -{ - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); - mhu_secure_message_send(scpi_cmd(0xC3, 16)); - mhu_secure_message_wait(); - mhu_secure_message_end(); -} - -static inline void scpi_copy_scp_data(uint8_t *data, size_t len) -{ - void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; - size_t sz; - - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); - scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); - mhu_secure_message_wait(); - - for (sz = 0; sz < len; sz += SIZE_FWBLK) { - memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz)); - mhu_secure_message_send(SCPI_CMD_COPY_FW); - } -} - -static inline void scpi_set_scp_addr(uint64_t addr, size_t len) -{ - volatile uint64_t *dst = (uint64_t *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; - - /* - * It is ok as GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as - * non cachable - */ - *dst = addr; - scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr)); - mhu_secure_message_wait(); - - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); - scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); - mhu_secure_message_wait(); -} - -static inline void scpi_send_fw_hash(uint8_t hash[], size_t len) -{ - void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; - - memcpy(dst, hash, len); - mhu_secure_message_send(0xd0); - mhu_secure_message_send(0xd1); - mhu_secure_message_send(0xd5); - mhu_secure_message_end(); -} - -/** - * Upload a FW to SCP. - * - * @param addr: firmware data address - * @param size: size of firmware - * @param send: If set, actually copy the firmware in SCP memory otherwise only - * send the firmware address. - */ -void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send) -{ - struct asd_ctx ctx; - - asd_sha_init(&ctx, ASM_SHA256); - asd_sha_update(&ctx, (void *)addr, size); - asd_sha_finalize(&ctx); - - mhu_secure_message_start(); - if (send == 0) - scpi_set_scp_addr(addr, size); - else - scpi_copy_scp_data((void *)addr, size); - - scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest)); -} diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index a7cda7708..f2394829a 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -14,7 +14,8 @@ DOIMAGEPATH ?= tools/amlogic DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ - -I${AML_PLAT_SOC}/include + -I${AML_PLAT_SOC}/include \ + -I${AML_PLAT_COMMON}/include GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ @@ -33,7 +34,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${AML_PLAT_SOC}/gxl_efuse.c \ ${AML_PLAT_SOC}/gxl_mhu.c \ ${AML_PLAT_SOC}/gxl_pm.c \ - ${AML_PLAT_SOC}/gxl_scpi.c \ + ${AML_PLAT_COMMON}/aml_scpi.c \ ${AML_PLAT_SOC}/gxl_sip_svc.c \ ${AML_PLAT_SOC}/gxl_thermal.c \ drivers/amlogic/crypto/sha_dma.c \ -- cgit v1.2.3 From e26864af8b3d69fb1eb5618500fe2c589ca65dcf Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 17:31:51 +0100 Subject: amlogic: Introduce unified private header file Now that also the SHA256 DMA driver is shared between all the SoCs, we can have one single private platform header file. Signed-off-by: Carlo Caione Change-Id: I77d51915f9d8233aeceeed66ed1f491573402cfc --- plat/amlogic/gxbb/gxbb_bl31_setup.c | 4 ++-- plat/amlogic/gxbb/gxbb_efuse.c | 4 ++-- plat/amlogic/gxbb/gxbb_pm.c | 4 ++-- plat/amlogic/gxbb/gxbb_private.h | 38 ----------------------------------- plat/amlogic/gxbb/gxbb_sip_svc.c | 4 ++-- plat/amlogic/gxbb/gxbb_thermal.c | 4 ++-- plat/amlogic/gxbb/gxbb_topology.c | 4 ++-- plat/amlogic/gxl/gxl_bl31_setup.c | 2 +- plat/amlogic/gxl/gxl_efuse.c | 4 ++-- plat/amlogic/gxl/gxl_pm.c | 2 +- plat/amlogic/gxl/gxl_private.h | 40 ------------------------------------- plat/amlogic/gxl/gxl_sip_svc.c | 4 ++-- plat/amlogic/gxl/gxl_thermal.c | 4 ++-- plat/amlogic/gxl/gxl_topology.c | 4 ++-- 14 files changed, 22 insertions(+), 100 deletions(-) delete mode 100644 plat/amlogic/gxbb/gxbb_private.h delete mode 100644 plat/amlogic/gxl/gxl_private.h diff --git a/plat/amlogic/gxbb/gxbb_bl31_setup.c b/plat/amlogic/gxbb/gxbb_bl31_setup.c index b867a5846..be23ce3b0 100644 --- a/plat/amlogic/gxbb/gxbb_bl31_setup.c +++ b/plat/amlogic/gxbb/gxbb_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,7 @@ #include #include -#include "gxbb_private.h" +#include "aml_private.h" /* * Placeholder variables for copying the arguments that have been passed to diff --git a/plat/amlogic/gxbb/gxbb_efuse.c b/plat/amlogic/gxbb/gxbb_efuse.c index edea5426c..412480213 100644 --- a/plat/amlogic/gxbb/gxbb_efuse.c +++ b/plat/amlogic/gxbb/gxbb_efuse.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include -#include "gxbb_private.h" +#include "aml_private.h" #define EFUSE_BASE 0x140 #define EFUSE_SIZE 0xC0 diff --git a/plat/amlogic/gxbb/gxbb_pm.c b/plat/amlogic/gxbb/gxbb_pm.c index 59b9436fe..4b0d755b4 100644 --- a/plat/amlogic/gxbb/gxbb_pm.c +++ b/plat/amlogic/gxbb/gxbb_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ #include #include -#include "gxbb_private.h" +#include "aml_private.h" #define SCPI_POWER_ON 0 #define SCPI_POWER_RETENTION 1 diff --git a/plat/amlogic/gxbb/gxbb_private.h b/plat/amlogic/gxbb/gxbb_private.h deleted file mode 100644 index 910a42c1c..000000000 --- a/plat/amlogic/gxbb/gxbb_private.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef GXBB_PRIVATE_H -#define GXBB_PRIVATE_H - -#include - -/* Utility functions */ -unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); -void gxbb_console_init(void); -void gxbb_setup_page_tables(void); - -/* MHU functions */ -void mhu_secure_message_start(void); -void mhu_secure_message_send(uint32_t msg); -uint32_t mhu_secure_message_wait(void); -void mhu_secure_message_end(void); -void mhu_secure_init(void); - -/* SCPI functions */ -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state); -uint32_t scpi_sys_power_state(uint64_t system_state); -void scpi_jtag_set_state(uint32_t state, uint8_t select); -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size); -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3); - -/* Peripherals */ -void gxbb_thermal_unknown(void); -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size); -uint64_t gxbb_efuse_user_max(void); - -#endif /* GXBB_PRIVATE_H */ diff --git a/plat/amlogic/gxbb/gxbb_sip_svc.c b/plat/amlogic/gxbb/gxbb_sip_svc.c index 63c7dba15..f8f471915 100644 --- a/plat/amlogic/gxbb/gxbb_sip_svc.c +++ b/plat/amlogic/gxbb/gxbb_sip_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,7 @@ #include #include -#include "gxbb_private.h" +#include "aml_private.h" /******************************************************************************* * This function is responsible for handling all SiP calls diff --git a/plat/amlogic/gxbb/gxbb_thermal.c b/plat/amlogic/gxbb/gxbb_thermal.c index b6048eee4..268606cd9 100644 --- a/plat/amlogic/gxbb/gxbb_thermal.c +++ b/plat/amlogic/gxbb/gxbb_thermal.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include -#include "gxbb_private.h" +#include "aml_private.h" static int32_t modules_initialized = -1; diff --git a/plat/amlogic/gxbb/gxbb_topology.c b/plat/amlogic/gxbb/gxbb_topology.c index eec2d34d4..23c39be47 100644 --- a/plat/amlogic/gxbb/gxbb_topology.c +++ b/plat/amlogic/gxbb/gxbb_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,7 @@ #include -#include "gxbb_private.h" +#include "aml_private.h" /* The power domain tree descriptor */ static unsigned char power_domain_tree_desc[] = { diff --git a/plat/amlogic/gxl/gxl_bl31_setup.c b/plat/amlogic/gxl/gxl_bl31_setup.c index b1da7942b..ddf43c9e2 100644 --- a/plat/amlogic/gxl/gxl_bl31_setup.c +++ b/plat/amlogic/gxl/gxl_bl31_setup.c @@ -13,7 +13,7 @@ #include #include -#include "gxl_private.h" +#include "aml_private.h" /* * Placeholder variables for copying the arguments that have been passed to diff --git a/plat/amlogic/gxl/gxl_efuse.c b/plat/amlogic/gxl/gxl_efuse.c index b17d1b8e3..412480213 100644 --- a/plat/amlogic/gxl/gxl_efuse.c +++ b/plat/amlogic/gxl/gxl_efuse.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include -#include "gxl_private.h" +#include "aml_private.h" #define EFUSE_BASE 0x140 #define EFUSE_SIZE 0xC0 diff --git a/plat/amlogic/gxl/gxl_pm.c b/plat/amlogic/gxl/gxl_pm.c index 4a5d26e90..544ae2039 100644 --- a/plat/amlogic/gxl/gxl_pm.c +++ b/plat/amlogic/gxl/gxl_pm.c @@ -15,7 +15,7 @@ #include #include -#include "gxl_private.h" +#include "aml_private.h" #define SCPI_POWER_ON 0 #define SCPI_POWER_RETENTION 1 diff --git a/plat/amlogic/gxl/gxl_private.h b/plat/amlogic/gxl/gxl_private.h deleted file mode 100644 index 913cbf653..000000000 --- a/plat/amlogic/gxl/gxl_private.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef GXBB_PRIVATE_H -#define GXBB_PRIVATE_H - -#include -#include - -/* Utility functions */ -unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); -void gxbb_console_init(void); -void gxbb_setup_page_tables(void); - -/* MHU functions */ -void mhu_secure_message_start(void); -void mhu_secure_message_send(uint32_t msg); -uint32_t mhu_secure_message_wait(void); -void mhu_secure_message_end(void); -void mhu_secure_init(void); - -/* SCPI functions */ -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state); -uint32_t scpi_sys_power_state(uint64_t system_state); -void scpi_jtag_set_state(uint32_t state, uint8_t select); -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size); -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3); -void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); - -/* Peripherals */ -void gxbb_thermal_unknown(void); -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size); -uint64_t gxbb_efuse_user_max(void); - -#endif /* GXBB_PRIVATE_H */ diff --git a/plat/amlogic/gxl/gxl_sip_svc.c b/plat/amlogic/gxl/gxl_sip_svc.c index 74fbc80e4..eb832eea1 100644 --- a/plat/amlogic/gxl/gxl_sip_svc.c +++ b/plat/amlogic/gxl/gxl_sip_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,7 @@ #include #include -#include "gxl_private.h" +#include "aml_private.h" /******************************************************************************* * This function is responsible for handling all SiP calls diff --git a/plat/amlogic/gxl/gxl_thermal.c b/plat/amlogic/gxl/gxl_thermal.c index 3af1c6dc6..268606cd9 100644 --- a/plat/amlogic/gxl/gxl_thermal.c +++ b/plat/amlogic/gxl/gxl_thermal.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include -#include "gxl_private.h" +#include "aml_private.h" static int32_t modules_initialized = -1; diff --git a/plat/amlogic/gxl/gxl_topology.c b/plat/amlogic/gxl/gxl_topology.c index cca3ead50..5fbad7352 100644 --- a/plat/amlogic/gxl/gxl_topology.c +++ b/plat/amlogic/gxl/gxl_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,7 +8,7 @@ #include #include -#include "gxl_private.h" +#include "aml_private.h" /* The power domain tree descriptor */ static unsigned char power_domain_tree_desc[] = { -- cgit v1.2.3 From 5b7436987177fd35ab8c8fc9f69d743f0a577813 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 17:36:32 +0100 Subject: amlogic: Move platform macros assembly file to common directory The platform macros are shared between all the SoCs. Move it to common directory. Signed-off-by: Carlo Caione Change-Id: Ia04c3ffe4d7b068aa701268ed99f69995d8db92b --- plat/amlogic/common/include/plat_macros.S | 71 +++++++++++++++++++++++++++++++ plat/amlogic/gxbb/include/plat_macros.S | 71 ------------------------------- plat/amlogic/gxl/include/plat_macros.S | 71 ------------------------------- 3 files changed, 71 insertions(+), 142 deletions(-) create mode 100644 plat/amlogic/common/include/plat_macros.S delete mode 100644 plat/amlogic/gxbb/include/plat_macros.S delete mode 100644 plat/amlogic/gxl/include/plat_macros.S diff --git a/plat/amlogic/common/include/plat_macros.S b/plat/amlogic/common/include/plat_macros.S new file mode 100644 index 000000000..c721c21b6 --- /dev/null +++ b/plat/amlogic/common/include/plat_macros.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include +#include + +.section .rodata.gic_reg_name, "aS" + +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + + /* GICC registers */ + + mov_imm x17, GXBB_GICC_BASE + + adr x6, gicc_regs + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + bl str_in_crash_buf_print + + /* GICD registers */ + + mov_imm x16, GXBB_GICD_BASE + + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str + +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/amlogic/gxbb/include/plat_macros.S b/plat/amlogic/gxbb/include/plat_macros.S deleted file mode 100644 index c721c21b6..000000000 --- a/plat/amlogic/gxbb/include/plat_macros.S +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLAT_MACROS_S -#define PLAT_MACROS_S - -#include -#include - -.section .rodata.gic_reg_name, "aS" - -gicc_regs: - .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" -gicd_pend_reg: - .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" -newline: - .asciz "\n" -spacer: - .asciz ":\t\t0x" - - /* --------------------------------------------- - * The below required platform porting macro - * prints out relevant GIC and CCI registers - * whenever an unhandled exception is taken in - * BL31. - * Clobbers: x0 - x10, x16, x17, sp - * --------------------------------------------- - */ - .macro plat_crash_print_regs - - /* GICC registers */ - - mov_imm x17, GXBB_GICC_BASE - - adr x6, gicc_regs - ldr w8, [x17, #GICC_HPPIR] - ldr w9, [x17, #GICC_AHPPIR] - ldr w10, [x17, #GICC_CTLR] - bl str_in_crash_buf_print - - /* GICD registers */ - - mov_imm x16, GXBB_GICD_BASE - - add x7, x16, #GICD_ISPENDR - adr x4, gicd_pend_reg - bl asm_print_str - -gicd_ispendr_loop: - sub x4, x7, x16 - cmp x4, #0x280 - b.eq exit_print_gic_regs - bl asm_print_hex - - adr x4, spacer - bl asm_print_str - - ldr x4, [x7], #8 - bl asm_print_hex - - adr x4, newline - bl asm_print_str - b gicd_ispendr_loop -exit_print_gic_regs: - - .endm - -#endif /* PLAT_MACROS_S */ diff --git a/plat/amlogic/gxl/include/plat_macros.S b/plat/amlogic/gxl/include/plat_macros.S deleted file mode 100644 index c721c21b6..000000000 --- a/plat/amlogic/gxl/include/plat_macros.S +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLAT_MACROS_S -#define PLAT_MACROS_S - -#include -#include - -.section .rodata.gic_reg_name, "aS" - -gicc_regs: - .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" -gicd_pend_reg: - .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" -newline: - .asciz "\n" -spacer: - .asciz ":\t\t0x" - - /* --------------------------------------------- - * The below required platform porting macro - * prints out relevant GIC and CCI registers - * whenever an unhandled exception is taken in - * BL31. - * Clobbers: x0 - x10, x16, x17, sp - * --------------------------------------------- - */ - .macro plat_crash_print_regs - - /* GICC registers */ - - mov_imm x17, GXBB_GICC_BASE - - adr x6, gicc_regs - ldr w8, [x17, #GICC_HPPIR] - ldr w9, [x17, #GICC_AHPPIR] - ldr w10, [x17, #GICC_CTLR] - bl str_in_crash_buf_print - - /* GICD registers */ - - mov_imm x16, GXBB_GICD_BASE - - add x7, x16, #GICD_ISPENDR - adr x4, gicd_pend_reg - bl asm_print_str - -gicd_ispendr_loop: - sub x4, x7, x16 - cmp x4, #0x280 - b.eq exit_print_gic_regs - bl asm_print_hex - - adr x4, spacer - bl asm_print_str - - ldr x4, [x7], #8 - bl asm_print_hex - - adr x4, newline - bl asm_print_str - b gicd_ispendr_loop -exit_print_gic_regs: - - .endm - -#endif /* PLAT_MACROS_S */ -- cgit v1.2.3 From d498d2497096807f6fed026dda206fe2c5ae11b1 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 17:43:33 +0100 Subject: amlogic: Move efuse code to common directory The efuse code is the same between GXL and GXBB. Move the code to common directory. Signed-off-by: Carlo Caione Change-Id: Ie37f21d1907a36292724f1fb645a78041fe4a6b3 --- plat/amlogic/common/aml_efuse.c | 25 +++++++++++++++++++++++++ plat/amlogic/gxbb/gxbb_efuse.c | 25 ------------------------- plat/amlogic/gxbb/platform.mk | 2 +- plat/amlogic/gxl/gxl_efuse.c | 25 ------------------------- plat/amlogic/gxl/platform.mk | 2 +- 5 files changed, 27 insertions(+), 52 deletions(-) create mode 100644 plat/amlogic/common/aml_efuse.c delete mode 100644 plat/amlogic/gxbb/gxbb_efuse.c delete mode 100644 plat/amlogic/gxl/gxl_efuse.c diff --git a/plat/amlogic/common/aml_efuse.c b/plat/amlogic/common/aml_efuse.c new file mode 100644 index 000000000..412480213 --- /dev/null +++ b/plat/amlogic/common/aml_efuse.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "aml_private.h" + +#define EFUSE_BASE 0x140 +#define EFUSE_SIZE 0xC0 + +uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) +{ + if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) + return 0; + + return scpi_efuse_read(dst, offset + EFUSE_BASE, size); +} + +uint64_t gxbb_efuse_user_max(void) +{ + return EFUSE_SIZE; +} diff --git a/plat/amlogic/gxbb/gxbb_efuse.c b/plat/amlogic/gxbb/gxbb_efuse.c deleted file mode 100644 index 412480213..000000000 --- a/plat/amlogic/gxbb/gxbb_efuse.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include "aml_private.h" - -#define EFUSE_BASE 0x140 -#define EFUSE_SIZE 0xC0 - -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) -{ - if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) - return 0; - - return scpi_efuse_read(dst, offset + EFUSE_BASE, size); -} - -uint64_t gxbb_efuse_user_max(void) -{ - return EFUSE_SIZE; -} diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk index 2430f2340..d2d337caf 100644 --- a/plat/amlogic/gxbb/platform.mk +++ b/plat/amlogic/gxbb/platform.mk @@ -28,7 +28,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ ${AML_PLAT_SOC}/gxbb_bl31_setup.c \ - ${AML_PLAT_SOC}/gxbb_efuse.c \ + ${AML_PLAT_COMMON}/aml_efuse.c \ ${AML_PLAT_SOC}/gxbb_mhu.c \ ${AML_PLAT_SOC}/gxbb_pm.c \ ${AML_PLAT_COMMON}/aml_scpi.c \ diff --git a/plat/amlogic/gxl/gxl_efuse.c b/plat/amlogic/gxl/gxl_efuse.c deleted file mode 100644 index 412480213..000000000 --- a/plat/amlogic/gxl/gxl_efuse.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include "aml_private.h" - -#define EFUSE_BASE 0x140 -#define EFUSE_SIZE 0xC0 - -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) -{ - if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) - return 0; - - return scpi_efuse_read(dst, offset + EFUSE_BASE, size); -} - -uint64_t gxbb_efuse_user_max(void) -{ - return EFUSE_SIZE; -} diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index f2394829a..5c8206cf1 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -31,7 +31,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ ${AML_PLAT_SOC}/gxl_bl31_setup.c \ - ${AML_PLAT_SOC}/gxl_efuse.c \ + ${AML_PLAT_COMMON}/aml_efuse.c \ ${AML_PLAT_SOC}/gxl_mhu.c \ ${AML_PLAT_SOC}/gxl_pm.c \ ${AML_PLAT_COMMON}/aml_scpi.c \ -- cgit v1.2.3 From 6f3b0dc465437c67ed9f44b918ac189e635ce716 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 17:46:04 +0100 Subject: amlogic: Move MHU code to common directory The MHU code is shared between all the supported platforms. Move it to the common directory instead. Signed-off-by: Carlo Caione Change-Id: Iaf53122866eae85c13f772927d16836dcfa877a3 --- plat/amlogic/common/aml_mhu.c | 52 ++++++++++++++++++++++++++++++++++++++++++ plat/amlogic/gxbb/gxbb_mhu.c | 53 ------------------------------------------- plat/amlogic/gxbb/platform.mk | 2 +- plat/amlogic/gxl/gxl_mhu.c | 52 ------------------------------------------ plat/amlogic/gxl/platform.mk | 2 +- 5 files changed, 54 insertions(+), 107 deletions(-) create mode 100644 plat/amlogic/common/aml_mhu.c delete mode 100644 plat/amlogic/gxbb/gxbb_mhu.c delete mode 100644 plat/amlogic/gxl/gxl_mhu.c diff --git a/plat/amlogic/common/aml_mhu.c b/plat/amlogic/common/aml_mhu.c new file mode 100644 index 000000000..4c1d5b600 --- /dev/null +++ b/plat/amlogic/common/aml_mhu.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +static DEFINE_BAKERY_LOCK(mhu_lock); + +void mhu_secure_message_start(void) +{ + bakery_lock_get(&mhu_lock); + + while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) + ; +} + +void mhu_secure_message_send(uint32_t msg) +{ + mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg); + + while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) + ; +} + +uint32_t mhu_secure_message_wait(void) +{ + uint32_t val; + + do { + val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0); + } while (val == 0); + + return val; +} + +void mhu_secure_message_end(void) +{ + mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); + + bakery_lock_release(&mhu_lock); +} + +void mhu_secure_init(void) +{ + bakery_lock_init(&mhu_lock); + + mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); +} diff --git a/plat/amlogic/gxbb/gxbb_mhu.c b/plat/amlogic/gxbb/gxbb_mhu.c deleted file mode 100644 index 903ef411c..000000000 --- a/plat/amlogic/gxbb/gxbb_mhu.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -static DEFINE_BAKERY_LOCK(mhu_lock); - -void mhu_secure_message_start(void) -{ - bakery_lock_get(&mhu_lock); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -void mhu_secure_message_send(uint32_t msg) -{ - mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -uint32_t mhu_secure_message_wait(void) -{ - uint32_t val; - - do { - val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0); - } while (val == 0); - - return val; -} - -void mhu_secure_message_end(void) -{ - mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); - - bakery_lock_release(&mhu_lock); -} - -void mhu_secure_init(void) -{ - bakery_lock_init(&mhu_lock); - - mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); -} diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk index d2d337caf..7da6468df 100644 --- a/plat/amlogic/gxbb/platform.mk +++ b/plat/amlogic/gxbb/platform.mk @@ -29,7 +29,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ ${AML_PLAT_SOC}/gxbb_bl31_setup.c \ ${AML_PLAT_COMMON}/aml_efuse.c \ - ${AML_PLAT_SOC}/gxbb_mhu.c \ + ${AML_PLAT_COMMON}/aml_mhu.c \ ${AML_PLAT_SOC}/gxbb_pm.c \ ${AML_PLAT_COMMON}/aml_scpi.c \ ${AML_PLAT_SOC}/gxbb_sip_svc.c \ diff --git a/plat/amlogic/gxl/gxl_mhu.c b/plat/amlogic/gxl/gxl_mhu.c deleted file mode 100644 index 4c1d5b600..000000000 --- a/plat/amlogic/gxl/gxl_mhu.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -static DEFINE_BAKERY_LOCK(mhu_lock); - -void mhu_secure_message_start(void) -{ - bakery_lock_get(&mhu_lock); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -void mhu_secure_message_send(uint32_t msg) -{ - mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg); - - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) - ; -} - -uint32_t mhu_secure_message_wait(void) -{ - uint32_t val; - - do { - val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0); - } while (val == 0); - - return val; -} - -void mhu_secure_message_end(void) -{ - mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); - - bakery_lock_release(&mhu_lock); -} - -void mhu_secure_init(void) -{ - bakery_lock_init(&mhu_lock); - - mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); -} diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index 5c8206cf1..b4f2a90f7 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -32,7 +32,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ ${AML_PLAT_SOC}/gxl_bl31_setup.c \ ${AML_PLAT_COMMON}/aml_efuse.c \ - ${AML_PLAT_SOC}/gxl_mhu.c \ + ${AML_PLAT_COMMON}/aml_mhu.c \ ${AML_PLAT_SOC}/gxl_pm.c \ ${AML_PLAT_COMMON}/aml_scpi.c \ ${AML_PLAT_SOC}/gxl_sip_svc.c \ -- cgit v1.2.3 From cd94cc4013f1da68d03bb40d61ecfcbc9305bbd9 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 17:48:11 +0100 Subject: amlogic: Move thermal code to common directory As for most of the Amlogic code, this is common between the Amlogic SoCs. Move the code to the common directory. Signed-off-by: Carlo Caione Change-Id: Id3f0073ff1f0b9ddbe964f80303323ee4a2f27b0 --- plat/amlogic/common/aml_thermal.c | 27 +++++++++++++++++++++++++++ plat/amlogic/gxbb/gxbb_thermal.c | 27 --------------------------- plat/amlogic/gxbb/platform.mk | 2 +- plat/amlogic/gxl/gxl_thermal.c | 27 --------------------------- plat/amlogic/gxl/platform.mk | 2 +- 5 files changed, 29 insertions(+), 56 deletions(-) create mode 100644 plat/amlogic/common/aml_thermal.c delete mode 100644 plat/amlogic/gxbb/gxbb_thermal.c delete mode 100644 plat/amlogic/gxl/gxl_thermal.c diff --git a/plat/amlogic/common/aml_thermal.c b/plat/amlogic/common/aml_thermal.c new file mode 100644 index 000000000..268606cd9 --- /dev/null +++ b/plat/amlogic/common/aml_thermal.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "aml_private.h" + +static int32_t modules_initialized = -1; + +/******************************************************************************* + * Unknown commands related to something thermal-related + ******************************************************************************/ +void gxbb_thermal_unknown(void) +{ + uint16_t ret; + + if (modules_initialized == -1) { + scpi_efuse_read(&ret, 0, 2); + modules_initialized = ret; + } + + scpi_unknown_thermal(10, 2, /* thermal */ + 13, 1); /* thermalver */ +} diff --git a/plat/amlogic/gxbb/gxbb_thermal.c b/plat/amlogic/gxbb/gxbb_thermal.c deleted file mode 100644 index 268606cd9..000000000 --- a/plat/amlogic/gxbb/gxbb_thermal.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include "aml_private.h" - -static int32_t modules_initialized = -1; - -/******************************************************************************* - * Unknown commands related to something thermal-related - ******************************************************************************/ -void gxbb_thermal_unknown(void) -{ - uint16_t ret; - - if (modules_initialized == -1) { - scpi_efuse_read(&ret, 0, 2); - modules_initialized = ret; - } - - scpi_unknown_thermal(10, 2, /* thermal */ - 13, 1); /* thermalver */ -} diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk index 7da6468df..4c3df1b71 100644 --- a/plat/amlogic/gxbb/platform.mk +++ b/plat/amlogic/gxbb/platform.mk @@ -33,7 +33,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${AML_PLAT_SOC}/gxbb_pm.c \ ${AML_PLAT_COMMON}/aml_scpi.c \ ${AML_PLAT_SOC}/gxbb_sip_svc.c \ - ${AML_PLAT_SOC}/gxbb_thermal.c \ + ${AML_PLAT_COMMON}/aml_thermal.c \ ${GIC_SOURCES} # Tune compiler for Cortex-A53 diff --git a/plat/amlogic/gxl/gxl_thermal.c b/plat/amlogic/gxl/gxl_thermal.c deleted file mode 100644 index 268606cd9..000000000 --- a/plat/amlogic/gxl/gxl_thermal.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include "aml_private.h" - -static int32_t modules_initialized = -1; - -/******************************************************************************* - * Unknown commands related to something thermal-related - ******************************************************************************/ -void gxbb_thermal_unknown(void) -{ - uint16_t ret; - - if (modules_initialized == -1) { - scpi_efuse_read(&ret, 0, 2); - modules_initialized = ret; - } - - scpi_unknown_thermal(10, 2, /* thermal */ - 13, 1); /* thermalver */ -} diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index b4f2a90f7..11687b5bf 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -36,7 +36,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${AML_PLAT_SOC}/gxl_pm.c \ ${AML_PLAT_COMMON}/aml_scpi.c \ ${AML_PLAT_SOC}/gxl_sip_svc.c \ - ${AML_PLAT_SOC}/gxl_thermal.c \ + ${AML_PLAT_COMMON}/aml_thermal.c \ drivers/amlogic/crypto/sha_dma.c \ ${GIC_SOURCES} -- cgit v1.2.3 From 261e7fd7b6017f3ca0f9e9527c74053eb5552f9e Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 17:50:16 +0100 Subject: amlogic: Move topology file to common directory As done already for multiple files, move the topology file to the common directory. Signed-off-by: Carlo Caione Change-Id: Iaca357a089593ad58c35c05c929239132249dcda --- plat/amlogic/common/aml_topology.c | 53 ++++++++++++++++++++++++++++++++++++ plat/amlogic/gxbb/gxbb_topology.c | 55 -------------------------------------- plat/amlogic/gxbb/platform.mk | 2 +- plat/amlogic/gxl/gxl_topology.c | 53 ------------------------------------ plat/amlogic/gxl/platform.mk | 2 +- 5 files changed, 55 insertions(+), 110 deletions(-) create mode 100644 plat/amlogic/common/aml_topology.c delete mode 100644 plat/amlogic/gxbb/gxbb_topology.c delete mode 100644 plat/amlogic/gxl/gxl_topology.c diff --git a/plat/amlogic/common/aml_topology.c b/plat/amlogic/common/aml_topology.c new file mode 100644 index 000000000..5fbad7352 --- /dev/null +++ b/plat/amlogic/common/aml_topology.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include "aml_private.h" + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first node */ + PLATFORM_CLUSTER0_CORE_COUNT +}; + +/******************************************************************************* + * This function returns the ARM default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) + return -1; + + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) + return -1; + + return plat_gxbb_calc_core_pos(mpidr); +} diff --git a/plat/amlogic/gxbb/gxbb_topology.c b/plat/amlogic/gxbb/gxbb_topology.c deleted file mode 100644 index 23c39be47..000000000 --- a/plat/amlogic/gxbb/gxbb_topology.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include - -#include "aml_private.h" - -/* The power domain tree descriptor */ -static unsigned char power_domain_tree_desc[] = { - /* Number of root nodes */ - PLATFORM_CLUSTER_COUNT, - /* Number of children for the first node */ - PLATFORM_CLUSTER0_CORE_COUNT -}; - -/******************************************************************************* - * This function returns the ARM default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) - return -1; - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) - return -1; - - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) - return -1; - - return plat_gxbb_calc_core_pos(mpidr); -} diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk index 4c3df1b71..e27519050 100644 --- a/plat/amlogic/gxbb/platform.mk +++ b/plat/amlogic/gxbb/platform.mk @@ -21,7 +21,7 @@ GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ ${AML_PLAT_SOC}/gxbb_common.c \ - ${AML_PLAT_SOC}/gxbb_topology.c \ + ${AML_PLAT_COMMON}/aml_topology.c \ ${XLAT_TABLES_LIB_SRCS} BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ diff --git a/plat/amlogic/gxl/gxl_topology.c b/plat/amlogic/gxl/gxl_topology.c deleted file mode 100644 index 5fbad7352..000000000 --- a/plat/amlogic/gxl/gxl_topology.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include "aml_private.h" - -/* The power domain tree descriptor */ -static unsigned char power_domain_tree_desc[] = { - /* Number of root nodes */ - PLATFORM_CLUSTER_COUNT, - /* Number of children for the first node */ - PLATFORM_CLUSTER0_CORE_COUNT -}; - -/******************************************************************************* - * This function returns the ARM default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) - return -1; - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) - return -1; - - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) - return -1; - - return plat_gxbb_calc_core_pos(mpidr); -} diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index 11687b5bf..1c41cd5ad 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -24,7 +24,7 @@ GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ ${AML_PLAT_SOC}/gxl_common.c \ - ${AML_PLAT_SOC}/gxl_topology.c \ + ${AML_PLAT_COMMON}/aml_topology.c \ ${XLAT_TABLES_LIB_SRCS} BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ -- cgit v1.2.3 From 35aee24ef56f6aed4e0703c1986eba3bb80e393f Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 17:52:40 +0100 Subject: amlogic: Move the SIP SVC code to common directory The code is the same between GXBB and GXL. Move it to the common source directory. Signed-off-by: Carlo Caione Change-Id: I875689a6fd029971aa755fc2725217e90ed06b6c --- plat/amlogic/common/aml_sip_svc.c | 66 +++++++++++++++++++++++++++++++++++++ plat/amlogic/gxbb/gxbb_sip_svc.c | 68 --------------------------------------- plat/amlogic/gxbb/platform.mk | 2 +- plat/amlogic/gxl/gxl_sip_svc.c | 66 ------------------------------------- plat/amlogic/gxl/platform.mk | 2 +- 5 files changed, 68 insertions(+), 136 deletions(-) create mode 100644 plat/amlogic/common/aml_sip_svc.c delete mode 100644 plat/amlogic/gxbb/gxbb_sip_svc.c delete mode 100644 plat/amlogic/gxl/gxl_sip_svc.c diff --git a/plat/amlogic/common/aml_sip_svc.c b/plat/amlogic/common/aml_sip_svc.c new file mode 100644 index 000000000..a212e6324 --- /dev/null +++ b/plat/amlogic/common/aml_sip_svc.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#include "aml_private.h" + +/******************************************************************************* + * This function is responsible for handling all SiP calls + ******************************************************************************/ +static uintptr_t gxbb_sip_handler(uint32_t smc_fid, + u_register_t x1, u_register_t x2, + u_register_t x3, u_register_t x4, + void *cookie, void *handle, + u_register_t flags) +{ + switch (smc_fid) { + + case GXBB_SM_GET_SHARE_MEM_INPUT_BASE: + SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE); + + case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE: + SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE); + + case GXBB_SM_EFUSE_READ: + { + void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; + uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2); + + SMC_RET1(handle, ret); + } + case GXBB_SM_EFUSE_USER_MAX: + SMC_RET1(handle, gxbb_efuse_user_max()); + + case GXBB_SM_JTAG_ON: + scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); + SMC_RET1(handle, 0); + + case GXBB_SM_JTAG_OFF: + scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1); + SMC_RET1(handle, 0); + + default: + ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid); + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +DECLARE_RT_SVC( + gxbb_sip_handler, + + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + gxbb_sip_handler +); diff --git a/plat/amlogic/gxbb/gxbb_sip_svc.c b/plat/amlogic/gxbb/gxbb_sip_svc.c deleted file mode 100644 index f8f471915..000000000 --- a/plat/amlogic/gxbb/gxbb_sip_svc.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include - -#include "aml_private.h" - -/******************************************************************************* - * This function is responsible for handling all SiP calls - ******************************************************************************/ -static uintptr_t gxbb_sip_handler(uint32_t smc_fid, - u_register_t x1, u_register_t x2, - u_register_t x3, u_register_t x4, - void *cookie, void *handle, - u_register_t flags) -{ - switch (smc_fid) { - - case GXBB_SM_GET_SHARE_MEM_INPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE); - - case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE); - - case GXBB_SM_EFUSE_READ: - { - void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; - uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2); - - SMC_RET1(handle, ret); - } - case GXBB_SM_EFUSE_USER_MAX: - SMC_RET1(handle, gxbb_efuse_user_max()); - - case GXBB_SM_JTAG_ON: - scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); - SMC_RET1(handle, 0); - - case GXBB_SM_JTAG_OFF: - scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1); - SMC_RET1(handle, 0); - - default: - ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid); - break; - } - - SMC_RET1(handle, SMC_UNK); -} - -DECLARE_RT_SVC( - gxbb_sip_handler, - - OEN_SIP_START, - OEN_SIP_END, - SMC_TYPE_FAST, - NULL, - gxbb_sip_handler -); diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk index e27519050..27f3c4239 100644 --- a/plat/amlogic/gxbb/platform.mk +++ b/plat/amlogic/gxbb/platform.mk @@ -32,7 +32,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${AML_PLAT_COMMON}/aml_mhu.c \ ${AML_PLAT_SOC}/gxbb_pm.c \ ${AML_PLAT_COMMON}/aml_scpi.c \ - ${AML_PLAT_SOC}/gxbb_sip_svc.c \ + ${AML_PLAT_COMMON}/aml_sip_svc.c \ ${AML_PLAT_COMMON}/aml_thermal.c \ ${GIC_SOURCES} diff --git a/plat/amlogic/gxl/gxl_sip_svc.c b/plat/amlogic/gxl/gxl_sip_svc.c deleted file mode 100644 index eb832eea1..000000000 --- a/plat/amlogic/gxl/gxl_sip_svc.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include - -#include "aml_private.h" - -/******************************************************************************* - * This function is responsible for handling all SiP calls - ******************************************************************************/ -static uintptr_t gxbb_sip_handler(uint32_t smc_fid, - u_register_t x1, u_register_t x2, - u_register_t x3, u_register_t x4, - void *cookie, void *handle, - u_register_t flags) -{ - switch (smc_fid) { - - case GXBB_SM_GET_SHARE_MEM_INPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE); - - case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE); - - case GXBB_SM_EFUSE_READ: - { - void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; - uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2); - - SMC_RET1(handle, ret); - } - case GXBB_SM_EFUSE_USER_MAX: - SMC_RET1(handle, gxbb_efuse_user_max()); - - case GXBB_SM_JTAG_ON: - scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); - SMC_RET1(handle, 0); - - case GXBB_SM_JTAG_OFF: - scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1); - SMC_RET1(handle, 0); - - default: - ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid); - break; - } - - SMC_RET1(handle, SMC_UNK); -} - -DECLARE_RT_SVC( - gxbb_sip_handler, - - OEN_SIP_START, - OEN_SIP_END, - SMC_TYPE_FAST, - NULL, - gxbb_sip_handler -); diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index 1c41cd5ad..f4d323550 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -35,7 +35,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${AML_PLAT_COMMON}/aml_mhu.c \ ${AML_PLAT_SOC}/gxl_pm.c \ ${AML_PLAT_COMMON}/aml_scpi.c \ - ${AML_PLAT_SOC}/gxl_sip_svc.c \ + ${AML_PLAT_COMMON}/aml_sip_svc.c \ ${AML_PLAT_COMMON}/aml_thermal.c \ drivers/amlogic/crypto/sha_dma.c \ ${GIC_SOURCES} -- cgit v1.2.3 From fab695122779a268025ece9a6ef38ffc03fd99df Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 18:37:46 +0100 Subject: amlogic: Rework Makefiles Now that every piece is in place, the makefiles can be refactored and slightly beautified removing useless and redundant parts. Signed-off-by: Carlo Caione Change-Id: If74e1909df52d475cf4b0dfed819d07d3a4c85b9 --- plat/amlogic/gxbb/platform.mk | 37 ++++++++++++++++++------------------- plat/amlogic/gxl/platform.mk | 39 +++++++++++++++++++-------------------- 2 files changed, 37 insertions(+), 39 deletions(-) diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk index 27f3c4239..59c4f3d63 100644 --- a/plat/amlogic/gxbb/platform.mk +++ b/plat/amlogic/gxbb/platform.mk @@ -10,30 +10,29 @@ AML_PLAT := plat/amlogic AML_PLAT_SOC := ${AML_PLAT}/${PLAT} AML_PLAT_COMMON := ${AML_PLAT}/common -PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ - -I${AML_PLAT_SOC}/include \ +PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ + -I${AML_PLAT_SOC}/include \ -I${AML_PLAT_COMMON}/include -GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/v2/gicv2_helpers.c \ +GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ plat/common/plat_gicv2.c -PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ - ${AML_PLAT_SOC}/gxbb_common.c \ - ${AML_PLAT_COMMON}/aml_topology.c \ - ${XLAT_TABLES_LIB_SRCS} - -BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ - plat/common/plat_psci_common.c \ +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + plat/common/plat_psci_common.c \ + drivers/amlogic/console/aarch64/meson_console.S \ + ${AML_PLAT_SOC}/gxbb_bl31_setup.c \ + ${AML_PLAT_SOC}/gxbb_pm.c \ + ${AML_PLAT_SOC}/gxbb_common.c \ ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ - ${AML_PLAT_SOC}/gxbb_bl31_setup.c \ - ${AML_PLAT_COMMON}/aml_efuse.c \ - ${AML_PLAT_COMMON}/aml_mhu.c \ - ${AML_PLAT_SOC}/gxbb_pm.c \ - ${AML_PLAT_COMMON}/aml_scpi.c \ - ${AML_PLAT_COMMON}/aml_sip_svc.c \ - ${AML_PLAT_COMMON}/aml_thermal.c \ + ${AML_PLAT_COMMON}/aml_efuse.c \ + ${AML_PLAT_COMMON}/aml_mhu.c \ + ${AML_PLAT_COMMON}/aml_scpi.c \ + ${AML_PLAT_COMMON}/aml_sip_svc.c \ + ${AML_PLAT_COMMON}/aml_thermal.c \ + ${AML_PLAT_COMMON}/aml_topology.c \ + ${XLAT_TABLES_LIB_SRCS} \ ${GIC_SOURCES} # Tune compiler for Cortex-A53 diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index f4d323550..80c991ced 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -13,31 +13,30 @@ AML_PLAT_COMMON := ${AML_PLAT}/common DOIMAGEPATH ?= tools/amlogic DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage -PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ - -I${AML_PLAT_SOC}/include \ +PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ + -I${AML_PLAT_SOC}/include \ -I${AML_PLAT_COMMON}/include -GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/v2/gicv2_helpers.c \ +GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ plat/common/plat_gicv2.c -PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ - ${AML_PLAT_SOC}/gxl_common.c \ - ${AML_PLAT_COMMON}/aml_topology.c \ - ${XLAT_TABLES_LIB_SRCS} - -BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ - plat/common/plat_psci_common.c \ +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + plat/common/plat_psci_common.c \ + drivers/amlogic/console/aarch64/meson_console.S \ + ${AML_PLAT_SOC}/gxl_bl31_setup.c \ + ${AML_PLAT_SOC}/gxl_pm.c \ + ${AML_PLAT_SOC}/gxl_common.c \ ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ - ${AML_PLAT_SOC}/gxl_bl31_setup.c \ - ${AML_PLAT_COMMON}/aml_efuse.c \ - ${AML_PLAT_COMMON}/aml_mhu.c \ - ${AML_PLAT_SOC}/gxl_pm.c \ - ${AML_PLAT_COMMON}/aml_scpi.c \ - ${AML_PLAT_COMMON}/aml_sip_svc.c \ - ${AML_PLAT_COMMON}/aml_thermal.c \ - drivers/amlogic/crypto/sha_dma.c \ + ${AML_PLAT_COMMON}/aml_efuse.c \ + ${AML_PLAT_COMMON}/aml_mhu.c \ + ${AML_PLAT_COMMON}/aml_scpi.c \ + ${AML_PLAT_COMMON}/aml_sip_svc.c \ + ${AML_PLAT_COMMON}/aml_thermal.c \ + ${AML_PLAT_COMMON}/aml_topology.c \ + drivers/amlogic/crypto/sha_dma.c \ + ${XLAT_TABLES_LIB_SRCS} \ ${GIC_SOURCES} # Tune compiler for Cortex-A53 -- cgit v1.2.3 From f681c676df66ffc1afd30948d9d789492e043e99 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 18:47:06 +0100 Subject: amlogic: Fix prefixes in the helpers file The code is the common directory is now generic, no need to have the SoC prefix hardcoded in the function names. Signed-off-by: Carlo Caione Change-Id: Ied3a5e506b9abd4c2d6f893bafef50019bff24f1 --- plat/amlogic/common/aarch64/aml_helpers.S | 24 ++++++++++++------------ plat/amlogic/common/aml_topology.c | 2 +- plat/amlogic/common/include/aml_private.h | 2 +- plat/amlogic/gxbb/gxbb_common.c | 6 +++--- plat/amlogic/gxbb/gxbb_def.h | 8 ++++---- plat/amlogic/gxbb/gxbb_pm.c | 18 +++++++++--------- plat/amlogic/gxbb/include/platform_def.h | 4 ++-- plat/amlogic/gxl/gxl_common.c | 8 ++++---- plat/amlogic/gxl/gxl_def.h | 6 +++--- plat/amlogic/gxl/gxl_pm.c | 20 ++++++++++---------- plat/amlogic/gxl/include/platform_def.h | 4 ++-- 11 files changed, 51 insertions(+), 51 deletions(-) diff --git a/plat/amlogic/common/aarch64/aml_helpers.S b/plat/amlogic/common/aarch64/aml_helpers.S index 760d6c46d..39bff0833 100644 --- a/plat/amlogic/common/aarch64/aml_helpers.S +++ b/plat/amlogic/common/aarch64/aml_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +16,7 @@ .globl plat_is_my_cpu_primary .globl plat_my_core_pos .globl plat_reset_handler - .globl plat_gxbb_calc_core_pos + .globl plat_calc_core_pos /* ----------------------------------------------------- * unsigned int plat_my_core_pos(void); @@ -24,17 +24,17 @@ */ func plat_my_core_pos mrs x0, mpidr_el1 - b plat_gxbb_calc_core_pos + b plat_calc_core_pos endfunc plat_my_core_pos /* ----------------------------------------------------- - * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); + * unsigned int plat_calc_core_pos(u_register_t mpidr); * ----------------------------------------------------- */ -func plat_gxbb_calc_core_pos +func plat_calc_core_pos and x0, x0, #MPIDR_CPU_MASK ret -endfunc plat_gxbb_calc_core_pos +endfunc plat_calc_core_pos /* ----------------------------------------------------- * unsigned int plat_is_my_cpu_primary(void); @@ -43,7 +43,7 @@ endfunc plat_gxbb_calc_core_pos func plat_is_my_cpu_primary mrs x0, mpidr_el1 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #GXBB_PRIMARY_CPU + cmp x0, #AML_PRIMARY_CPU cset w0, eq ret endfunc plat_is_my_cpu_primary @@ -61,9 +61,9 @@ endfunc platform_mem_init * --------------------------------------------- */ func plat_crash_console_init - mov_imm x0, GXBB_UART0_AO_BASE - mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ - mov_imm x2, GXBB_UART_BAUDRATE + mov_imm x0, AML_UART0_AO_BASE + mov_imm x1, AML_UART0_AO_CLK_IN_HZ + mov_imm x2, AML_UART_BAUDRATE b console_meson_init endfunc plat_crash_console_init @@ -73,7 +73,7 @@ endfunc plat_crash_console_init * --------------------------------------------- */ func plat_crash_console_putc - mov_imm x1, GXBB_UART0_AO_BASE + mov_imm x1, AML_UART0_AO_BASE b console_meson_core_putc endfunc plat_crash_console_putc @@ -84,7 +84,7 @@ endfunc plat_crash_console_putc * --------------------------------------------- */ func plat_crash_console_flush - mov_imm x0, GXBB_UART0_AO_BASE + mov_imm x0, AML_UART0_AO_BASE b console_meson_core_flush endfunc plat_crash_console_flush diff --git a/plat/amlogic/common/aml_topology.c b/plat/amlogic/common/aml_topology.c index 5fbad7352..0a04c1105 100644 --- a/plat/amlogic/common/aml_topology.c +++ b/plat/amlogic/common/aml_topology.c @@ -49,5 +49,5 @@ int plat_core_pos_by_mpidr(u_register_t mpidr) if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) return -1; - return plat_gxbb_calc_core_pos(mpidr); + return plat_calc_core_pos(mpidr); } diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h index 6f1855f63..c06004f8d 100644 --- a/plat/amlogic/common/include/aml_private.h +++ b/plat/amlogic/common/include/aml_private.h @@ -11,7 +11,7 @@ #include /* Utility functions */ -unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); +unsigned int plat_calc_core_pos(u_register_t mpidr); void gxbb_console_init(void); void gxbb_setup_page_tables(void); diff --git a/plat/amlogic/gxbb/gxbb_common.c b/plat/amlogic/gxbb/gxbb_common.c index eb688f772..06ff0082a 100644 --- a/plat/amlogic/gxbb/gxbb_common.c +++ b/plat/amlogic/gxbb/gxbb_common.c @@ -109,9 +109,9 @@ static console_meson_t gxbb_console; void gxbb_console_init(void) { - int rc = console_meson_register(GXBB_UART0_AO_BASE, - GXBB_UART0_AO_CLK_IN_HZ, - GXBB_UART_BAUDRATE, + int rc = console_meson_register(AML_UART0_AO_BASE, + AML_UART0_AO_CLK_IN_HZ, + AML_UART_BAUDRATE, &gxbb_console); if (rc == 0) { /* diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h index 3e27097c3..e43bb1d26 100644 --- a/plat/amlogic/gxbb/gxbb_def.h +++ b/plat/amlogic/gxbb/gxbb_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -75,9 +75,9 @@ /******************************************************************************* * UART definitions ******************************************************************************/ -#define GXBB_UART0_AO_BASE UL(0xC81004C0) -#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ -#define GXBB_UART_BAUDRATE U(115200) +#define AML_UART0_AO_BASE UL(0xC81004C0) +#define AML_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ +#define AML_UART_BAUDRATE U(115200) /******************************************************************************* * Memory-mapped I/O Registers diff --git a/plat/amlogic/gxbb/gxbb_pm.c b/plat/amlogic/gxbb/gxbb_pm.c index 4b0d755b4..0d542a56c 100644 --- a/plat/amlogic/gxbb/gxbb_pm.c +++ b/plat/amlogic/gxbb/gxbb_pm.c @@ -31,7 +31,7 @@ static volatile uint32_t gxbb_cpu0_go; static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value) { - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); mmio_write_64(cpu_mailbox_addr, value); @@ -86,10 +86,10 @@ static void __dead2 gxbb_system_off(void) static int32_t gxbb_pwr_domain_on(u_register_t mpidr) { - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { + if (core == AML_PRIMARY_CPU) { VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); gxbb_cpu0_go = 1; @@ -113,12 +113,12 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr) static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) { - unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + unsigned int core = plat_calc_core_pos(read_mpidr_el1()); assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == PLAT_LOCAL_STATE_OFF); - if (core == GXBB_PRIMARY_CPU) { + if (core == AML_PRIMARY_CPU) { gxbb_cpu0_go = 0; flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go)); dsb(); @@ -132,7 +132,7 @@ static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr_el1(); - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4); mmio_write_32(addr, 0xFFFFFFFF); @@ -141,7 +141,7 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) gicv2_cpuif_disable(); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) + if (core == AML_PRIMARY_CPU) return; scpi_set_css_power_state(mpidr, @@ -151,10 +151,10 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) { - unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + unsigned int core = plat_calc_core_pos(read_mpidr_el1()); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { + if (core == AML_PRIMARY_CPU) { VERBOSE("BL31: CPU0 entering wait loop...\n"); while (gxbb_cpu0_go == 0) diff --git a/plat/amlogic/gxbb/include/platform_def.h b/plat/amlogic/gxbb/include/platform_def.h index da4aedde8..bd6ce32d9 100644 --- a/plat/amlogic/gxbb/include/platform_def.h +++ b/plat/amlogic/gxbb/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,7 +25,7 @@ #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT -#define GXBB_PRIMARY_CPU U(0) +#define AML_PRIMARY_CPU U(0) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ diff --git a/plat/amlogic/gxl/gxl_common.c b/plat/amlogic/gxl/gxl_common.c index e3bd6048a..cede8d8c8 100644 --- a/plat/amlogic/gxl/gxl_common.c +++ b/plat/amlogic/gxl/gxl_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -107,9 +107,9 @@ static console_meson_t gxbb_console; void gxbb_console_init(void) { - int rc = console_meson_register(GXBB_UART0_AO_BASE, - GXBB_UART0_AO_CLK_IN_HZ, - GXBB_UART_BAUDRATE, + int rc = console_meson_register(AML_UART0_AO_BASE, + AML_UART0_AO_CLK_IN_HZ, + AML_UART_BAUDRATE, &gxbb_console); if (rc == 0) { /* diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h index 089fa8db9..ced811d94 100644 --- a/plat/amlogic/gxl/gxl_def.h +++ b/plat/amlogic/gxl/gxl_def.h @@ -79,9 +79,9 @@ /******************************************************************************* * UART definitions ******************************************************************************/ -#define GXBB_UART0_AO_BASE UL(0xC81004C0) -#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ -#define GXBB_UART_BAUDRATE U(115200) +#define AML_UART0_AO_BASE UL(0xC81004C0) +#define AML_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ +#define AML_UART_BAUDRATE U(115200) /******************************************************************************* * Memory-mapped I/O Registers diff --git a/plat/amlogic/gxl/gxl_pm.c b/plat/amlogic/gxl/gxl_pm.c index 544ae2039..d6071bfc6 100644 --- a/plat/amlogic/gxl/gxl_pm.c +++ b/plat/amlogic/gxl/gxl_pm.c @@ -29,7 +29,7 @@ static volatile uint32_t gxbb_cpu0_go; static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value) { - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); mmio_write_64(cpu_mailbox_addr, value); @@ -37,7 +37,7 @@ static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value) static void gxl_pm_reset(u_register_t mpidr) { - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8; mmio_write_32(cpu_mailbox_addr, 0); @@ -99,10 +99,10 @@ static void __dead2 gxbb_system_off(void) static int32_t gxbb_pwr_domain_on(u_register_t mpidr) { - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { + if (core == AML_PRIMARY_CPU) { VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); gxbb_cpu0_go = 1; @@ -127,12 +127,12 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr) static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) { - unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + unsigned int core = plat_calc_core_pos(read_mpidr_el1()); assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == PLAT_LOCAL_STATE_OFF); - if (core == GXBB_PRIMARY_CPU) { + if (core == AML_PRIMARY_CPU) { gxbb_cpu0_go = 0; flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go)); @@ -147,12 +147,12 @@ static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr_el1(); - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); gicv2_cpuif_disable(); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) + if (core == AML_PRIMARY_CPU) return; scpi_set_css_power_state(mpidr, @@ -163,10 +163,10 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr_el1(); - unsigned int core = plat_gxbb_calc_core_pos(mpidr); + unsigned int core = plat_calc_core_pos(mpidr); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ - if (core == GXBB_PRIMARY_CPU) { + if (core == AML_PRIMARY_CPU) { VERBOSE("BL31: CPU0 entering wait loop...\n"); while (gxbb_cpu0_go == 0) diff --git a/plat/amlogic/gxl/include/platform_def.h b/plat/amlogic/gxl/include/platform_def.h index b32ec56da..80b0d6463 100644 --- a/plat/amlogic/gxl/include/platform_def.h +++ b/plat/amlogic/gxl/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,7 +25,7 @@ #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT -#define GXBB_PRIMARY_CPU U(0) +#define AML_PRIMARY_CPU U(0) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ -- cgit v1.2.3 From 821781f30e8428c34666603a32351d100862a8d1 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 24 Aug 2019 18:51:48 +0100 Subject: amlogic: Fix prefixes in the platform macros file Fixing at the same time the related register names. Signed-off-by: Carlo Caione Change-Id: Ib1130d50abe6088f1c0826878d1ae454a0f23008 --- plat/amlogic/common/include/plat_macros.S | 6 +++--- plat/amlogic/gxbb/gxbb_bl31_setup.c | 4 ++-- plat/amlogic/gxbb/gxbb_def.h | 4 ++-- plat/amlogic/gxl/gxl_bl31_setup.c | 4 ++-- plat/amlogic/gxl/gxl_def.h | 4 ++-- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/plat/amlogic/common/include/plat_macros.S b/plat/amlogic/common/include/plat_macros.S index c721c21b6..d620fcfba 100644 --- a/plat/amlogic/common/include/plat_macros.S +++ b/plat/amlogic/common/include/plat_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,7 +33,7 @@ spacer: /* GICC registers */ - mov_imm x17, GXBB_GICC_BASE + mov_imm x17, AML_GICC_BASE adr x6, gicc_regs ldr w8, [x17, #GICC_HPPIR] @@ -43,7 +43,7 @@ spacer: /* GICD registers */ - mov_imm x16, GXBB_GICD_BASE + mov_imm x16, AML_GICD_BASE add x7, x16, #GICD_ISPENDR adr x4, gicd_pend_reg diff --git a/plat/amlogic/gxbb/gxbb_bl31_setup.c b/plat/amlogic/gxbb/gxbb_bl31_setup.c index be23ce3b0..e5402c339 100644 --- a/plat/amlogic/gxbb/gxbb_bl31_setup.c +++ b/plat/amlogic/gxbb/gxbb_bl31_setup.c @@ -127,8 +127,8 @@ static const interrupt_prop_t gxbb_interrupt_props[] = { }; static const gicv2_driver_data_t gxbb_gic_data = { - .gicd_base = GXBB_GICD_BASE, - .gicc_base = GXBB_GICC_BASE, + .gicd_base = AML_GICD_BASE, + .gicc_base = AML_GICC_BASE, .interrupt_props = gxbb_interrupt_props, .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), }; diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h index e43bb1d26..e888aa606 100644 --- a/plat/amlogic/gxbb/gxbb_def.h +++ b/plat/amlogic/gxbb/gxbb_def.h @@ -58,8 +58,8 @@ /******************************************************************************* * GIC-400 and interrupt handling related constants ******************************************************************************/ -#define GXBB_GICD_BASE UL(0xC4301000) -#define GXBB_GICC_BASE UL(0xC4302000) +#define AML_GICD_BASE UL(0xC4301000) +#define AML_GICC_BASE UL(0xC4302000) #define IRQ_SEC_PHY_TIMER 29 diff --git a/plat/amlogic/gxl/gxl_bl31_setup.c b/plat/amlogic/gxl/gxl_bl31_setup.c index ddf43c9e2..796f1a0a8 100644 --- a/plat/amlogic/gxl/gxl_bl31_setup.c +++ b/plat/amlogic/gxl/gxl_bl31_setup.c @@ -141,8 +141,8 @@ static const interrupt_prop_t gxbb_interrupt_props[] = { }; static const gicv2_driver_data_t gxbb_gic_data = { - .gicd_base = GXBB_GICD_BASE, - .gicc_base = GXBB_GICC_BASE, + .gicd_base = AML_GICD_BASE, + .gicc_base = AML_GICC_BASE, .interrupt_props = gxbb_interrupt_props, .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), }; diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h index ced811d94..3cc7a1c03 100644 --- a/plat/amlogic/gxl/gxl_def.h +++ b/plat/amlogic/gxl/gxl_def.h @@ -62,8 +62,8 @@ /******************************************************************************* * GIC-400 and interrupt handling related constants ******************************************************************************/ -#define GXBB_GICD_BASE UL(0xC4301000) -#define GXBB_GICC_BASE UL(0xC4302000) +#define AML_GICD_BASE UL(0xC4301000) +#define AML_GICC_BASE UL(0xC4302000) #define IRQ_SEC_PHY_TIMER 29 -- cgit v1.2.3 From 93c795ae9ca57ae5c92031f6beb1286cf64cc865 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sun, 25 Aug 2019 17:26:27 +0100 Subject: amlogic: Fix prefixes in the efuse driver The efuse driver is hardcoding the GXBB prefix. No need to do that since the driver is shared between multiple SoCs. Signed-off-by: Carlo Caione Change-Id: I97691b0bbd55170d8216d301a3fc04feb8c2af2e --- plat/amlogic/common/aml_efuse.c | 4 ++-- plat/amlogic/common/aml_sip_svc.c | 4 ++-- plat/amlogic/common/include/aml_private.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/plat/amlogic/common/aml_efuse.c b/plat/amlogic/common/aml_efuse.c index 412480213..9ab4ba297 100644 --- a/plat/amlogic/common/aml_efuse.c +++ b/plat/amlogic/common/aml_efuse.c @@ -11,7 +11,7 @@ #define EFUSE_BASE 0x140 #define EFUSE_SIZE 0xC0 -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) +uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size) { if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) return 0; @@ -19,7 +19,7 @@ uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) return scpi_efuse_read(dst, offset + EFUSE_BASE, size); } -uint64_t gxbb_efuse_user_max(void) +uint64_t aml_efuse_user_max(void) { return EFUSE_SIZE; } diff --git a/plat/amlogic/common/aml_sip_svc.c b/plat/amlogic/common/aml_sip_svc.c index a212e6324..b35899784 100644 --- a/plat/amlogic/common/aml_sip_svc.c +++ b/plat/amlogic/common/aml_sip_svc.c @@ -32,12 +32,12 @@ static uintptr_t gxbb_sip_handler(uint32_t smc_fid, case GXBB_SM_EFUSE_READ: { void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; - uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2); + uint64_t ret = aml_efuse_read(dst, (uint32_t)x1, x2); SMC_RET1(handle, ret); } case GXBB_SM_EFUSE_USER_MAX: - SMC_RET1(handle, gxbb_efuse_user_max()); + SMC_RET1(handle, aml_efuse_user_max()); case GXBB_SM_JTAG_ON: scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h index c06004f8d..952b5c43c 100644 --- a/plat/amlogic/common/include/aml_private.h +++ b/plat/amlogic/common/include/aml_private.h @@ -34,7 +34,7 @@ void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); /* Peripherals */ void gxbb_thermal_unknown(void); -uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size); -uint64_t gxbb_efuse_user_max(void); +uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size); +uint64_t aml_efuse_user_max(void); #endif /* GXBB_PRIVATE_H */ -- cgit v1.2.3 From 010fdc1ba02638296e4effbdddb1044bed822ee2 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sun, 25 Aug 2019 18:09:03 +0100 Subject: amlogic: Fix prefixes in the private header file The header file is shared between all the SoCs. Better avoiding hardcoding the SoC name in the function names. Signed-off-by: Carlo Caione Change-Id: I9074871bd1ed8a702c1a656e0f50f2d3c6cb0425 --- plat/amlogic/common/include/aml_private.h | 4 ++-- plat/amlogic/gxbb/gxbb_bl31_setup.c | 4 ++-- plat/amlogic/gxbb/gxbb_common.c | 4 ++-- plat/amlogic/gxl/gxl_bl31_setup.c | 4 ++-- plat/amlogic/gxl/gxl_common.c | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h index 952b5c43c..3d7e6ebda 100644 --- a/plat/amlogic/common/include/aml_private.h +++ b/plat/amlogic/common/include/aml_private.h @@ -12,8 +12,8 @@ /* Utility functions */ unsigned int plat_calc_core_pos(u_register_t mpidr); -void gxbb_console_init(void); -void gxbb_setup_page_tables(void); +void aml_console_init(void); +void aml_setup_page_tables(void); /* MHU functions */ void mhu_secure_message_start(void); diff --git a/plat/amlogic/gxbb/gxbb_bl31_setup.c b/plat/amlogic/gxbb/gxbb_bl31_setup.c index e5402c339..c474d6967 100644 --- a/plat/amlogic/gxbb/gxbb_bl31_setup.c +++ b/plat/amlogic/gxbb/gxbb_bl31_setup.c @@ -67,7 +67,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, struct gxbb_bl31_param *from_bl2; /* Initialize the console to provide early debug support */ - gxbb_console_init(); + aml_console_init(); /* * In debug builds, we pass a special value in 'arg1' to verify platform @@ -97,7 +97,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void bl31_plat_arch_setup(void) { - gxbb_setup_page_tables(); + aml_setup_page_tables(); enable_mmu_el3(0); } diff --git a/plat/amlogic/gxbb/gxbb_common.c b/plat/amlogic/gxbb/gxbb_common.c index 06ff0082a..756093256 100644 --- a/plat/amlogic/gxbb/gxbb_common.c +++ b/plat/amlogic/gxbb/gxbb_common.c @@ -81,7 +81,7 @@ static const mmap_region_t gxbb_mmap[] = { /******************************************************************************* * Function that sets up the translation tables. ******************************************************************************/ -void gxbb_setup_page_tables(void) +void aml_setup_page_tables(void) { #if IMAGE_BL31 const mmap_region_t gxbb_bl_mmap[] = { @@ -107,7 +107,7 @@ void gxbb_setup_page_tables(void) ******************************************************************************/ static console_meson_t gxbb_console; -void gxbb_console_init(void) +void aml_console_init(void) { int rc = console_meson_register(AML_UART0_AO_BASE, AML_UART0_AO_CLK_IN_HZ, diff --git a/plat/amlogic/gxl/gxl_bl31_setup.c b/plat/amlogic/gxl/gxl_bl31_setup.c index 796f1a0a8..d44b9aaa3 100644 --- a/plat/amlogic/gxl/gxl_bl31_setup.c +++ b/plat/amlogic/gxl/gxl_bl31_setup.c @@ -69,7 +69,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, struct gxl_bl31_param *from_bl2; /* Initialize the console to provide early debug support */ - gxbb_console_init(); + aml_console_init(); /* Check that params passed from BL2 are not NULL. */ from_bl2 = (struct gxl_bl31_param *) arg0; @@ -96,7 +96,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void bl31_plat_arch_setup(void) { - gxbb_setup_page_tables(); + aml_setup_page_tables(); enable_mmu_el3(0); } diff --git a/plat/amlogic/gxl/gxl_common.c b/plat/amlogic/gxl/gxl_common.c index cede8d8c8..f975cadda 100644 --- a/plat/amlogic/gxl/gxl_common.c +++ b/plat/amlogic/gxl/gxl_common.c @@ -79,7 +79,7 @@ static const mmap_region_t gxbb_mmap[] = { /******************************************************************************* * Function that sets up the translation tables. ******************************************************************************/ -void gxbb_setup_page_tables(void) +void aml_setup_page_tables(void) { #if IMAGE_BL31 const mmap_region_t gxbb_bl_mmap[] = { @@ -105,7 +105,7 @@ void gxbb_setup_page_tables(void) ******************************************************************************/ static console_meson_t gxbb_console; -void gxbb_console_init(void) +void aml_console_init(void) { int rc = console_meson_register(AML_UART0_AO_BASE, AML_UART0_AO_CLK_IN_HZ, -- cgit v1.2.3 From 73f6d057666f55799f48e16f13faf47851fd393c Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sun, 25 Aug 2019 18:09:59 +0100 Subject: amlogic: Fix prefixes in the thermal driver No need to have a special SoC-specific prefix. Signed-off-by: Carlo Caione Change-Id: I0da543e7d92d56604e79440a98027ffd9a2eaa59 --- plat/amlogic/common/aml_thermal.c | 2 +- plat/amlogic/common/include/aml_private.h | 2 +- plat/amlogic/gxbb/gxbb_bl31_setup.c | 2 +- plat/amlogic/gxl/gxl_bl31_setup.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/amlogic/common/aml_thermal.c b/plat/amlogic/common/aml_thermal.c index 268606cd9..0a57f10f4 100644 --- a/plat/amlogic/common/aml_thermal.c +++ b/plat/amlogic/common/aml_thermal.c @@ -13,7 +13,7 @@ static int32_t modules_initialized = -1; /******************************************************************************* * Unknown commands related to something thermal-related ******************************************************************************/ -void gxbb_thermal_unknown(void) +void aml_thermal_unknown(void) { uint16_t ret; diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h index 3d7e6ebda..9670c8783 100644 --- a/plat/amlogic/common/include/aml_private.h +++ b/plat/amlogic/common/include/aml_private.h @@ -33,7 +33,7 @@ void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); /* Peripherals */ -void gxbb_thermal_unknown(void); +void aml_thermal_unknown(void); uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size); uint64_t aml_efuse_user_max(void); diff --git a/plat/amlogic/gxbb/gxbb_bl31_setup.c b/plat/amlogic/gxbb/gxbb_bl31_setup.c index c474d6967..cff29b392 100644 --- a/plat/amlogic/gxbb/gxbb_bl31_setup.c +++ b/plat/amlogic/gxbb/gxbb_bl31_setup.c @@ -142,5 +142,5 @@ void bl31_platform_setup(void) gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); - gxbb_thermal_unknown(); + aml_thermal_unknown(); } diff --git a/plat/amlogic/gxl/gxl_bl31_setup.c b/plat/amlogic/gxl/gxl_bl31_setup.c index d44b9aaa3..fbfb76a0a 100644 --- a/plat/amlogic/gxl/gxl_bl31_setup.c +++ b/plat/amlogic/gxl/gxl_bl31_setup.c @@ -158,5 +158,5 @@ void bl31_platform_setup(void) gxl_scp_boot(); - gxbb_thermal_unknown(); + aml_thermal_unknown(); } -- cgit v1.2.3 From 381b901f22a3d78ac15bb6d9ea5f88ed365d1fbf Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 26 Aug 2019 13:04:12 +0100 Subject: amlogic: Fix prefixes in the SIP/SVC code All the SIP/SVC related code is currently the same between GXL and GXBB. Rename function names and register names to avoid hardcoding the GXBB prefix. Signed-off-by: Carlo Caione Change-Id: I7e58ab68489df8d4762663fc01fb64e6899cc8bf --- plat/amlogic/common/aml_scpi.c | 4 ++-- plat/amlogic/common/aml_sip_svc.c | 28 ++++++++++++++-------------- plat/amlogic/gxbb/gxbb_def.h | 28 ++++++++++++++-------------- plat/amlogic/gxl/gxl_def.h | 28 ++++++++++++++-------------- 4 files changed, 44 insertions(+), 44 deletions(-) diff --git a/plat/amlogic/common/aml_scpi.c b/plat/amlogic/common/aml_scpi.c index 672702967..28837a2c5 100644 --- a/plat/amlogic/common/aml_scpi.c +++ b/plat/amlogic/common/aml_scpi.c @@ -89,9 +89,9 @@ uint32_t scpi_sys_power_state(uint64_t system_state) void scpi_jtag_set_state(uint32_t state, uint8_t select) { - assert(state <= GXBB_JTAG_STATE_OFF); + assert(state <= AML_JTAG_STATE_OFF); - if (select > GXBB_JTAG_A53_EE) { + if (select > AML_JTAG_A53_EE) { WARN("BL31: Invalid JTAG select (0x%x).\n", select); return; } diff --git a/plat/amlogic/common/aml_sip_svc.c b/plat/amlogic/common/aml_sip_svc.c index b35899784..6736a816a 100644 --- a/plat/amlogic/common/aml_sip_svc.c +++ b/plat/amlogic/common/aml_sip_svc.c @@ -15,7 +15,7 @@ /******************************************************************************* * This function is responsible for handling all SiP calls ******************************************************************************/ -static uintptr_t gxbb_sip_handler(uint32_t smc_fid, +static uintptr_t aml_sip_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3, u_register_t x4, void *cookie, void *handle, @@ -23,28 +23,28 @@ static uintptr_t gxbb_sip_handler(uint32_t smc_fid, { switch (smc_fid) { - case GXBB_SM_GET_SHARE_MEM_INPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE); + case AML_SM_GET_SHARE_MEM_INPUT_BASE: + SMC_RET1(handle, AML_SHARE_MEM_INPUT_BASE); - case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE: - SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE); + case AML_SM_GET_SHARE_MEM_OUTPUT_BASE: + SMC_RET1(handle, AML_SHARE_MEM_OUTPUT_BASE); - case GXBB_SM_EFUSE_READ: + case AML_SM_EFUSE_READ: { - void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; + void *dst = (void *)AML_SHARE_MEM_OUTPUT_BASE; uint64_t ret = aml_efuse_read(dst, (uint32_t)x1, x2); SMC_RET1(handle, ret); } - case GXBB_SM_EFUSE_USER_MAX: + case AML_SM_EFUSE_USER_MAX: SMC_RET1(handle, aml_efuse_user_max()); - case GXBB_SM_JTAG_ON: - scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); + case AML_SM_JTAG_ON: + scpi_jtag_set_state(AML_JTAG_STATE_ON, x1); SMC_RET1(handle, 0); - case GXBB_SM_JTAG_OFF: - scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1); + case AML_SM_JTAG_OFF: + scpi_jtag_set_state(AML_JTAG_STATE_OFF, x1); SMC_RET1(handle, 0); default: @@ -56,11 +56,11 @@ static uintptr_t gxbb_sip_handler(uint32_t smc_fid, } DECLARE_RT_SVC( - gxbb_sip_handler, + aml_sip_handler, OEN_SIP_START, OEN_SIP_END, SMC_TYPE_FAST, NULL, - gxbb_sip_handler + aml_sip_handler ); diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h index e888aa606..1b781d957 100644 --- a/plat/amlogic/gxbb/gxbb_def.h +++ b/plat/amlogic/gxbb/gxbb_def.h @@ -28,8 +28,8 @@ #define BL31_LIMIT (BL31_BASE + BL31_SIZE) /* Shared memory used for SMC services */ -#define GXBB_SHARE_MEM_INPUT_BASE UL(0x100FE000) -#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x100FF000) +#define AML_SHARE_MEM_INPUT_BASE UL(0x100FE000) +#define AML_SHARE_MEM_OUTPUT_BASE UL(0x100FF000) #define GXBB_SEC_DEVICE0_BASE UL(0xC0000000) #define GXBB_SEC_DEVICE0_SIZE UL(0x09000000) @@ -98,21 +98,21 @@ /******************************************************************************* * System Monitor Call IDs and arguments ******************************************************************************/ -#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) -#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) +#define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) +#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) -#define GXBB_SM_EFUSE_READ U(0x82000030) -#define GXBB_SM_EFUSE_USER_MAX U(0x82000033) +#define AML_SM_EFUSE_READ U(0x82000030) +#define AML_SM_EFUSE_USER_MAX U(0x82000033) -#define GXBB_SM_JTAG_ON U(0x82000040) -#define GXBB_SM_JTAG_OFF U(0x82000041) +#define AML_SM_JTAG_ON U(0x82000040) +#define AML_SM_JTAG_OFF U(0x82000041) -#define GXBB_JTAG_STATE_ON U(0) -#define GXBB_JTAG_STATE_OFF U(1) +#define AML_JTAG_STATE_ON U(0) +#define AML_JTAG_STATE_OFF U(1) -#define GXBB_JTAG_M3_AO U(0) -#define GXBB_JTAG_M3_EE U(1) -#define GXBB_JTAG_A53_AO U(2) -#define GXBB_JTAG_A53_EE U(3) +#define AML_JTAG_M3_AO U(0) +#define AML_JTAG_M3_EE U(1) +#define AML_JTAG_A53_AO U(2) +#define AML_JTAG_A53_EE U(3) #endif /* GXBB_DEF_H */ diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h index 3cc7a1c03..1149d072f 100644 --- a/plat/amlogic/gxl/gxl_def.h +++ b/plat/amlogic/gxl/gxl_def.h @@ -28,8 +28,8 @@ #define BL31_LIMIT (BL31_BASE + BL31_SIZE) /* Shared memory used for SMC services */ -#define GXBB_SHARE_MEM_INPUT_BASE UL(0x050FE000) -#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x050FF000) +#define AML_SHARE_MEM_INPUT_BASE UL(0x050FE000) +#define AML_SHARE_MEM_OUTPUT_BASE UL(0x050FF000) #define GXBB_SEC_DEVICE0_BASE UL(0xC0000000) #define GXBB_SEC_DEVICE0_SIZE UL(0x09000000) @@ -108,21 +108,21 @@ /******************************************************************************* * System Monitor Call IDs and arguments ******************************************************************************/ -#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) -#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) +#define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) +#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) -#define GXBB_SM_EFUSE_READ U(0x82000030) -#define GXBB_SM_EFUSE_USER_MAX U(0x82000033) +#define AML_SM_EFUSE_READ U(0x82000030) +#define AML_SM_EFUSE_USER_MAX U(0x82000033) -#define GXBB_SM_JTAG_ON U(0x82000040) -#define GXBB_SM_JTAG_OFF U(0x82000041) +#define AML_SM_JTAG_ON U(0x82000040) +#define AML_SM_JTAG_OFF U(0x82000041) -#define GXBB_JTAG_STATE_ON U(0) -#define GXBB_JTAG_STATE_OFF U(1) +#define AML_JTAG_STATE_ON U(0) +#define AML_JTAG_STATE_OFF U(1) -#define GXBB_JTAG_M3_AO U(0) -#define GXBB_JTAG_M3_EE U(1) -#define GXBB_JTAG_A53_AO U(2) -#define GXBB_JTAG_A53_EE U(3) +#define AML_JTAG_M3_AO U(0) +#define AML_JTAG_M3_EE U(1) +#define AML_JTAG_A53_AO U(2) +#define AML_JTAG_A53_EE U(3) #endif /* GXBB_DEF_H */ -- cgit v1.2.3 From cbaad533d1fa1ce8e81e095591281af5b60a6be9 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 28 Aug 2019 09:46:18 +0100 Subject: amlogic: Fix prefixes in the MHU code Make the MHU code AML specific adding a new aml_* prefix and remove the GXBB prefix from the register names. Signed-off-by: Carlo Caione Change-Id: I8f20918e29f08542bd71bd679f88e65b4efaa7d2 --- plat/amlogic/common/aml_mhu.c | 24 ++++----- plat/amlogic/common/aml_scpi.c | 90 +++++++++++++++---------------- plat/amlogic/common/include/aml_private.h | 10 ++-- plat/amlogic/gxbb/gxbb_bl31_setup.c | 2 +- plat/amlogic/gxbb/gxbb_def.h | 16 +++--- plat/amlogic/gxl/gxl_bl31_setup.c | 2 +- plat/amlogic/gxl/gxl_def.h | 16 +++--- 7 files changed, 80 insertions(+), 80 deletions(-) diff --git a/plat/amlogic/common/aml_mhu.c b/plat/amlogic/common/aml_mhu.c index 4c1d5b600..001686af0 100644 --- a/plat/amlogic/common/aml_mhu.c +++ b/plat/amlogic/common/aml_mhu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,43 +10,43 @@ static DEFINE_BAKERY_LOCK(mhu_lock); -void mhu_secure_message_start(void) +void aml_mhu_secure_message_start(void) { bakery_lock_get(&mhu_lock); - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) + while (mmio_read_32(AML_HIU_MAILBOX_STAT_3) != 0) ; } -void mhu_secure_message_send(uint32_t msg) +void aml_mhu_secure_message_send(uint32_t msg) { - mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg); + mmio_write_32(AML_HIU_MAILBOX_SET_3, msg); - while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) + while (mmio_read_32(AML_HIU_MAILBOX_STAT_3) != 0) ; } -uint32_t mhu_secure_message_wait(void) +uint32_t aml_mhu_secure_message_wait(void) { uint32_t val; do { - val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0); + val = mmio_read_32(AML_HIU_MAILBOX_STAT_0); } while (val == 0); return val; } -void mhu_secure_message_end(void) +void aml_mhu_secure_message_end(void) { - mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); + mmio_write_32(AML_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); bakery_lock_release(&mhu_lock); } -void mhu_secure_init(void) +void aml_mhu_secure_init(void) { bakery_lock_init(&mhu_lock); - mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); + mmio_write_32(AML_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); } diff --git a/plat/amlogic/common/aml_scpi.c b/plat/amlogic/common/aml_scpi.c index 28837a2c5..0a8c97a31 100644 --- a/plat/amlogic/common/aml_scpi.c +++ b/plat/amlogic/common/aml_scpi.c @@ -37,12 +37,12 @@ static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) static void scpi_secure_message_send(uint32_t command, uint32_t size) { - mhu_secure_message_send(scpi_cmd(command, size)); + aml_mhu_secure_message_send(scpi_cmd(command, size)); } uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) { - uint32_t response = mhu_secure_message_wait(); + uint32_t response = aml_mhu_secure_message_wait(); size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; @@ -52,7 +52,7 @@ uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) *size_out = size; if (message_out != NULL) - *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD; + *message_out = (void *)AML_MHU_SECURE_SCP_TO_AP_PAYLOAD; return response; } @@ -66,11 +66,11 @@ void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, (cluster_state << 12) | (css_state << 16); - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); + aml_mhu_secure_message_start(); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); + aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); + aml_mhu_secure_message_wait(); + aml_mhu_secure_message_end(); } uint32_t scpi_sys_power_state(uint64_t system_state) @@ -78,11 +78,11 @@ uint32_t scpi_sys_power_state(uint64_t system_state) uint32_t *response; size_t size; - mhu_secure_message_start(); - mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); + aml_mhu_secure_message_start(); + mmio_write_8(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); + aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); scpi_secure_message_receive((void *)&response, &size); - mhu_secure_message_end(); + aml_mhu_secure_message_end(); return *response; } @@ -96,12 +96,12 @@ void scpi_jtag_set_state(uint32_t state, uint8_t select) return; } - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, + aml_mhu_secure_message_start(); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, (state << 8) | (uint32_t)select); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); - mhu_secure_message_wait(); - mhu_secure_message_end(); + aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); + aml_mhu_secure_message_wait(); + aml_mhu_secure_message_end(); } uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) @@ -112,12 +112,12 @@ uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) if (size > 0x1FC) return 0; - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); - mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); + aml_mhu_secure_message_start(); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); + aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); scpi_secure_message_receive((void *)&response, &resp_size); - mhu_secure_message_end(); + aml_mhu_secure_message_end(); /* * response[0] is the size of the response message. @@ -132,57 +132,57 @@ uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3) { - mhu_secure_message_start(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); - mhu_secure_message_send(scpi_cmd(0xC3, 16)); - mhu_secure_message_wait(); - mhu_secure_message_end(); + aml_mhu_secure_message_start(); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); + aml_mhu_secure_message_send(scpi_cmd(0xC3, 16)); + aml_mhu_secure_message_wait(); + aml_mhu_secure_message_end(); } static inline void scpi_copy_scp_data(uint8_t *data, size_t len) { - void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD; size_t sz; - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); - mhu_secure_message_wait(); + aml_mhu_secure_message_wait(); for (sz = 0; sz < len; sz += SIZE_FWBLK) { memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz)); - mhu_secure_message_send(SCPI_CMD_COPY_FW); + aml_mhu_secure_message_send(SCPI_CMD_COPY_FW); } } static inline void scpi_set_scp_addr(uint64_t addr, size_t len) { - volatile uint64_t *dst = (uint64_t *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + volatile uint64_t *dst = (uint64_t *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD; /* - * It is ok as GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as + * It is ok as AML_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as * non cachable */ *dst = addr; scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr)); - mhu_secure_message_wait(); + aml_mhu_secure_message_wait(); - mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); + mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); - mhu_secure_message_wait(); + aml_mhu_secure_message_wait(); } static inline void scpi_send_fw_hash(uint8_t hash[], size_t len) { - void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD; memcpy(dst, hash, len); - mhu_secure_message_send(0xd0); - mhu_secure_message_send(0xd1); - mhu_secure_message_send(0xd5); - mhu_secure_message_end(); + aml_mhu_secure_message_send(0xd0); + aml_mhu_secure_message_send(0xd1); + aml_mhu_secure_message_send(0xd5); + aml_mhu_secure_message_end(); } /** @@ -201,7 +201,7 @@ void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send) asd_sha_update(&ctx, (void *)addr, size); asd_sha_finalize(&ctx); - mhu_secure_message_start(); + aml_mhu_secure_message_start(); if (send == 0) scpi_set_scp_addr(addr, size); else diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h index 9670c8783..0d5a26c9b 100644 --- a/plat/amlogic/common/include/aml_private.h +++ b/plat/amlogic/common/include/aml_private.h @@ -16,11 +16,11 @@ void aml_console_init(void); void aml_setup_page_tables(void); /* MHU functions */ -void mhu_secure_message_start(void); -void mhu_secure_message_send(uint32_t msg); -uint32_t mhu_secure_message_wait(void); -void mhu_secure_message_end(void); -void mhu_secure_init(void); +void aml_mhu_secure_message_start(void); +void aml_mhu_secure_message_send(uint32_t msg); +uint32_t aml_mhu_secure_message_wait(void); +void aml_mhu_secure_message_end(void); +void aml_mhu_secure_init(void); /* SCPI functions */ void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, diff --git a/plat/amlogic/gxbb/gxbb_bl31_setup.c b/plat/amlogic/gxbb/gxbb_bl31_setup.c index cff29b392..26419d40c 100644 --- a/plat/amlogic/gxbb/gxbb_bl31_setup.c +++ b/plat/amlogic/gxbb/gxbb_bl31_setup.c @@ -135,7 +135,7 @@ static const gicv2_driver_data_t gxbb_gic_data = { void bl31_platform_setup(void) { - mhu_secure_init(); + aml_mhu_secure_init(); gicv2_driver_init(&gxbb_gic_data); gicv2_distif_init(); diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h index 1b781d957..b9183a451 100644 --- a/plat/amlogic/gxbb/gxbb_def.h +++ b/plat/amlogic/gxbb/gxbb_def.h @@ -42,8 +42,8 @@ /* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ /* Mailboxes */ -#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) -#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) +#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) +#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) #define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00) #define GXBB_TZROM_BASE UL(0xD9040000) @@ -88,12 +88,12 @@ #define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C) -#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404) -#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408) -#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) -#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428) -#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) -#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430) +#define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404) +#define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408) +#define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) +#define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428) +#define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) +#define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430) /******************************************************************************* * System Monitor Call IDs and arguments diff --git a/plat/amlogic/gxl/gxl_bl31_setup.c b/plat/amlogic/gxl/gxl_bl31_setup.c index fbfb76a0a..409222091 100644 --- a/plat/amlogic/gxl/gxl_bl31_setup.c +++ b/plat/amlogic/gxl/gxl_bl31_setup.c @@ -149,7 +149,7 @@ static const gicv2_driver_data_t gxbb_gic_data = { void bl31_platform_setup(void) { - mhu_secure_init(); + aml_mhu_secure_init(); gicv2_driver_init(&gxbb_gic_data); gicv2_distif_init(); diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h index 1149d072f..2a1c8d346 100644 --- a/plat/amlogic/gxl/gxl_def.h +++ b/plat/amlogic/gxl/gxl_def.h @@ -42,8 +42,8 @@ /* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ /* Mailboxes */ -#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) -#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) +#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) +#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) #define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00) // * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) @@ -98,12 +98,12 @@ ((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \ GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK) -#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404) -#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408) -#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) -#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428) -#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) -#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430) +#define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404) +#define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408) +#define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) +#define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428) +#define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) +#define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430) /******************************************************************************* * System Monitor Call IDs and arguments -- cgit v1.2.3 From 9a5616fa185824a4c4e330fd345ce6ae3fd69ef3 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 28 Aug 2019 10:08:24 +0100 Subject: amlogic: Fix prefixes in the SCPI related code Add a new aml_* prefix to the SCPI related function calls. Signed-off-by: Carlo Caione Change-Id: I697812ac1c0df28cbb639a1dc3e838f1107fb739 --- plat/amlogic/common/aml_efuse.c | 2 +- plat/amlogic/common/aml_scpi.c | 54 +++++++++++++++---------------- plat/amlogic/common/aml_sip_svc.c | 4 +-- plat/amlogic/common/aml_thermal.c | 6 ++-- plat/amlogic/common/include/aml_private.h | 16 ++++----- plat/amlogic/gxbb/gxbb_pm.c | 12 +++---- plat/amlogic/gxl/gxl_bl31_setup.c | 8 ++--- plat/amlogic/gxl/gxl_pm.c | 12 +++---- 8 files changed, 57 insertions(+), 57 deletions(-) diff --git a/plat/amlogic/common/aml_efuse.c b/plat/amlogic/common/aml_efuse.c index 9ab4ba297..00884ebd5 100644 --- a/plat/amlogic/common/aml_efuse.c +++ b/plat/amlogic/common/aml_efuse.c @@ -16,7 +16,7 @@ uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size) if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) return 0; - return scpi_efuse_read(dst, offset + EFUSE_BASE, size); + return aml_scpi_efuse_read(dst, offset + EFUSE_BASE, size); } uint64_t aml_efuse_user_max(void) diff --git a/plat/amlogic/common/aml_scpi.c b/plat/amlogic/common/aml_scpi.c index 0a8c97a31..728bcd061 100644 --- a/plat/amlogic/common/aml_scpi.c +++ b/plat/amlogic/common/aml_scpi.c @@ -30,17 +30,17 @@ #define SCPI_CMD_SET_FW_ADDR 0xd3 #define SCPI_CMD_FW_SIZE 0xd2 -static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) +static inline uint32_t aml_scpi_cmd(uint32_t command, uint32_t size) { return command | (size << SIZE_SHIFT); } -static void scpi_secure_message_send(uint32_t command, uint32_t size) +static void aml_scpi_secure_message_send(uint32_t command, uint32_t size) { - aml_mhu_secure_message_send(scpi_cmd(command, size)); + aml_mhu_secure_message_send(aml_scpi_cmd(command, size)); } -uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) +static uint32_t aml_scpi_secure_message_receive(void **message_out, size_t *size_out) { uint32_t response = aml_mhu_secure_message_wait(); @@ -57,7 +57,7 @@ uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) return response; } -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, +void aml_scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, uint32_t cluster_state, uint32_t css_state) { uint32_t state = (mpidr & 0x0F) | /* CPU ID */ @@ -68,26 +68,26 @@ void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, aml_mhu_secure_message_start(); mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); - aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); + aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); aml_mhu_secure_message_wait(); aml_mhu_secure_message_end(); } -uint32_t scpi_sys_power_state(uint64_t system_state) +uint32_t aml_scpi_sys_power_state(uint64_t system_state) { uint32_t *response; size_t size; aml_mhu_secure_message_start(); mmio_write_8(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); - aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); - scpi_secure_message_receive((void *)&response, &size); + aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); + aml_scpi_secure_message_receive((void *)&response, &size); aml_mhu_secure_message_end(); return *response; } -void scpi_jtag_set_state(uint32_t state, uint8_t select) +void aml_scpi_jtag_set_state(uint32_t state, uint8_t select) { assert(state <= AML_JTAG_STATE_OFF); @@ -99,12 +99,12 @@ void scpi_jtag_set_state(uint32_t state, uint8_t select) aml_mhu_secure_message_start(); mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, (state << 8) | (uint32_t)select); - aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); + aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); aml_mhu_secure_message_wait(); aml_mhu_secure_message_end(); } -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) +uint32_t aml_scpi_efuse_read(void *dst, uint32_t base, uint32_t size) { uint32_t *response; size_t resp_size; @@ -115,8 +115,8 @@ uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) aml_mhu_secure_message_start(); mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); - aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); - scpi_secure_message_receive((void *)&response, &resp_size); + aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); + aml_scpi_secure_message_receive((void *)&response, &resp_size); aml_mhu_secure_message_end(); /* @@ -129,26 +129,26 @@ uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) return *response; } -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3) +void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3) { aml_mhu_secure_message_start(); mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); - aml_mhu_secure_message_send(scpi_cmd(0xC3, 16)); + aml_mhu_secure_message_send(aml_scpi_cmd(0xC3, 16)); aml_mhu_secure_message_wait(); aml_mhu_secure_message_end(); } -static inline void scpi_copy_scp_data(uint8_t *data, size_t len) +static inline void aml_scpi_copy_scp_data(uint8_t *data, size_t len) { void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD; size_t sz; mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); - scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); + aml_scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); aml_mhu_secure_message_wait(); for (sz = 0; sz < len; sz += SIZE_FWBLK) { @@ -157,7 +157,7 @@ static inline void scpi_copy_scp_data(uint8_t *data, size_t len) } } -static inline void scpi_set_scp_addr(uint64_t addr, size_t len) +static inline void aml_scpi_set_scp_addr(uint64_t addr, size_t len) { volatile uint64_t *dst = (uint64_t *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD; @@ -166,15 +166,15 @@ static inline void scpi_set_scp_addr(uint64_t addr, size_t len) * non cachable */ *dst = addr; - scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr)); + aml_scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr)); aml_mhu_secure_message_wait(); mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); - scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); + aml_scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); aml_mhu_secure_message_wait(); } -static inline void scpi_send_fw_hash(uint8_t hash[], size_t len) +static inline void aml_scpi_send_fw_hash(uint8_t hash[], size_t len) { void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD; @@ -193,7 +193,7 @@ static inline void scpi_send_fw_hash(uint8_t hash[], size_t len) * @param send: If set, actually copy the firmware in SCP memory otherwise only * send the firmware address. */ -void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send) +void aml_scpi_upload_scp_fw(uintptr_t addr, size_t size, int send) { struct asd_ctx ctx; @@ -203,9 +203,9 @@ void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send) aml_mhu_secure_message_start(); if (send == 0) - scpi_set_scp_addr(addr, size); + aml_scpi_set_scp_addr(addr, size); else - scpi_copy_scp_data((void *)addr, size); + aml_scpi_copy_scp_data((void *)addr, size); - scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest)); + aml_scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest)); } diff --git a/plat/amlogic/common/aml_sip_svc.c b/plat/amlogic/common/aml_sip_svc.c index 6736a816a..8a9b070d8 100644 --- a/plat/amlogic/common/aml_sip_svc.c +++ b/plat/amlogic/common/aml_sip_svc.c @@ -40,11 +40,11 @@ static uintptr_t aml_sip_handler(uint32_t smc_fid, SMC_RET1(handle, aml_efuse_user_max()); case AML_SM_JTAG_ON: - scpi_jtag_set_state(AML_JTAG_STATE_ON, x1); + aml_scpi_jtag_set_state(AML_JTAG_STATE_ON, x1); SMC_RET1(handle, 0); case AML_SM_JTAG_OFF: - scpi_jtag_set_state(AML_JTAG_STATE_OFF, x1); + aml_scpi_jtag_set_state(AML_JTAG_STATE_OFF, x1); SMC_RET1(handle, 0); default: diff --git a/plat/amlogic/common/aml_thermal.c b/plat/amlogic/common/aml_thermal.c index 0a57f10f4..53ed10323 100644 --- a/plat/amlogic/common/aml_thermal.c +++ b/plat/amlogic/common/aml_thermal.c @@ -18,10 +18,10 @@ void aml_thermal_unknown(void) uint16_t ret; if (modules_initialized == -1) { - scpi_efuse_read(&ret, 0, 2); + aml_scpi_efuse_read(&ret, 0, 2); modules_initialized = ret; } - scpi_unknown_thermal(10, 2, /* thermal */ - 13, 1); /* thermalver */ + aml_scpi_unknown_thermal(10, 2, /* thermal */ + 13, 1); /* thermalver */ } diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h index 0d5a26c9b..d6629fc3a 100644 --- a/plat/amlogic/common/include/aml_private.h +++ b/plat/amlogic/common/include/aml_private.h @@ -23,14 +23,14 @@ void aml_mhu_secure_message_end(void); void aml_mhu_secure_init(void); /* SCPI functions */ -void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, - uint32_t cluster_state, uint32_t css_state); -uint32_t scpi_sys_power_state(uint64_t system_state); -void scpi_jtag_set_state(uint32_t state, uint8_t select); -uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size); -void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, - uint32_t arg2, uint32_t arg3); -void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); +void aml_scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state); +uint32_t aml_scpi_sys_power_state(uint64_t system_state); +void aml_scpi_jtag_set_state(uint32_t state, uint8_t select); +uint32_t aml_scpi_efuse_read(void *dst, uint32_t base, uint32_t size); +void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3); +void aml_scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); /* Peripherals */ void aml_thermal_unknown(void); diff --git a/plat/amlogic/gxbb/gxbb_pm.c b/plat/amlogic/gxbb/gxbb_pm.c index 0d542a56c..20f655a67 100644 --- a/plat/amlogic/gxbb/gxbb_pm.c +++ b/plat/amlogic/gxbb/gxbb_pm.c @@ -52,7 +52,7 @@ static void __dead2 gxbb_system_reset(void) mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); - int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); + int ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT); if (ret != 0) { ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret); @@ -69,7 +69,7 @@ static void __dead2 gxbb_system_off(void) { INFO("BL31: PSCI_SYSTEM_OFF\n"); - unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); + unsigned int ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); if (ret != 0) { ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret); @@ -103,8 +103,8 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr) } gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint); - scpi_set_css_power_state(mpidr, - SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); + aml_scpi_set_css_power_state(mpidr, + SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); dmbsy(); sev(); @@ -144,8 +144,8 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) if (core == AML_PRIMARY_CPU) return; - scpi_set_css_power_state(mpidr, - SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); + aml_scpi_set_css_power_state(mpidr, + SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); } static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t diff --git a/plat/amlogic/gxl/gxl_bl31_setup.c b/plat/amlogic/gxl/gxl_bl31_setup.c index 409222091..e7c42184d 100644 --- a/plat/amlogic/gxl/gxl_bl31_setup.c +++ b/plat/amlogic/gxl/gxl_bl31_setup.c @@ -108,10 +108,10 @@ static inline bool gxl_scp_ready(void) static inline void gxl_scp_boot(void) { - scpi_upload_scp_fw(bl30_image_info.image_base, - bl30_image_info.image_size, 0); - scpi_upload_scp_fw(bl301_image_info.image_base, - bl301_image_info.image_size, 1); + aml_scpi_upload_scp_fw(bl30_image_info.image_base, + bl30_image_info.image_size, 0); + aml_scpi_upload_scp_fw(bl301_image_info.image_base, + bl301_image_info.image_size, 1); while (!gxl_scp_ready()) ; } diff --git a/plat/amlogic/gxl/gxl_pm.c b/plat/amlogic/gxl/gxl_pm.c index d6071bfc6..2e9f4b8b0 100644 --- a/plat/amlogic/gxl/gxl_pm.c +++ b/plat/amlogic/gxl/gxl_pm.c @@ -59,7 +59,7 @@ static void __dead2 gxbb_system_reset(void) mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); - ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); + ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT); if (ret != 0) { ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret); @@ -81,7 +81,7 @@ static void __dead2 gxbb_system_off(void) u_register_t mpidr = read_mpidr_el1(); int ret; - ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); + ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); if (ret != 0) { ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret); @@ -117,8 +117,8 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr) } gxl_pm_set_reset_addr(mpidr, gxbb_sec_entrypoint); - scpi_set_css_power_state(mpidr, - SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); + aml_scpi_set_css_power_state(mpidr, + SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); dmbsy(); sev(); @@ -155,8 +155,8 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) if (core == AML_PRIMARY_CPU) return; - scpi_set_css_power_state(mpidr, - SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); + aml_scpi_set_css_power_state(mpidr, + SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); } static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t -- cgit v1.2.3 From 0e1d78969bbc7e562711511b9c8596a5ff5f5144 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 28 Aug 2019 15:19:56 +0100 Subject: amlogic: Fix prefixes in the PM code Remove the GXBB prefix from the code in the common directory and add SoC-specific prefixes in the SoC specific code. Signed-off-by: Carlo Caione Change-Id: Ic983ef70b0ef23f95088dd8df488d8c42c3bc030 --- plat/amlogic/gxbb/gxbb_def.h | 4 +-- plat/amlogic/gxbb/gxbb_pm.c | 8 +++--- plat/amlogic/gxl/gxl_def.h | 4 +-- plat/amlogic/gxl/gxl_pm.c | 62 ++++++++++++++++++++++---------------------- 4 files changed, 39 insertions(+), 39 deletions(-) diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h index b9183a451..27bc0addd 100644 --- a/plat/amlogic/gxbb/gxbb_def.h +++ b/plat/amlogic/gxbb/gxbb_def.h @@ -44,7 +44,7 @@ /* Mailboxes */ #define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) #define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) -#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00) +#define AML_PSCI_MAILBOX_BASE UL(0xD9013F00) #define GXBB_TZROM_BASE UL(0xD9040000) #define GXBB_TZROM_SIZE UL(0x00010000) @@ -86,7 +86,7 @@ #define GXBB_SYS_CPU_CFG7 UL(0xC8834664) -#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C) +#define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C) #define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404) #define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408) diff --git a/plat/amlogic/gxbb/gxbb_pm.c b/plat/amlogic/gxbb/gxbb_pm.c index 20f655a67..ed57fee47 100644 --- a/plat/amlogic/gxbb/gxbb_pm.c +++ b/plat/amlogic/gxbb/gxbb_pm.c @@ -32,7 +32,7 @@ static volatile uint32_t gxbb_cpu0_go; static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value) { unsigned int core = plat_calc_core_pos(mpidr); - uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); + uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); mmio_write_64(cpu_mailbox_addr, value); flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t)); @@ -42,7 +42,7 @@ static void __dead2 gxbb_system_reset(void) { INFO("BL31: PSCI_SYSTEM_RESET\n"); - uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3); + uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3); NOTICE("BL31: Reboot reason: 0x%x\n", status); @@ -50,7 +50,7 @@ static void __dead2 gxbb_system_reset(void) console_flush(); - mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); + mmio_write_32(AML_AO_RTI_STATUS_REG3, status); int ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT); @@ -133,7 +133,7 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr_el1(); unsigned int core = plat_calc_core_pos(mpidr); - uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4); + uintptr_t addr = AML_PSCI_MAILBOX_BASE + 8 + (core << 4); mmio_write_32(addr, 0xFFFFFFFF); flush_dcache_range(addr, sizeof(uint32_t)); diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h index 2a1c8d346..3b604a619 100644 --- a/plat/amlogic/gxl/gxl_def.h +++ b/plat/amlogic/gxl/gxl_def.h @@ -44,7 +44,7 @@ /* Mailboxes */ #define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) #define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) -#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00) +#define AML_PSCI_MAILBOX_BASE UL(0xD9013F00) // * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) // * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * @@ -90,7 +90,7 @@ #define GXBB_SYS_CPU_CFG7 UL(0xC8834664) -#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C) +#define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C) #define GXBB_AO_RTI_SCP_STAT UL(0xDA10023C) #define GXBB_AO_RTI_SCP_READY_OFF U(0x14) #define GXBB_A0_RTI_SCP_READY_MASK U(3) diff --git a/plat/amlogic/gxl/gxl_pm.c b/plat/amlogic/gxl/gxl_pm.c index 2e9f4b8b0..a3ec7d9bd 100644 --- a/plat/amlogic/gxl/gxl_pm.c +++ b/plat/amlogic/gxl/gxl_pm.c @@ -24,13 +24,13 @@ #define SCPI_SYSTEM_SHUTDOWN 0 #define SCPI_SYSTEM_REBOOT 1 -static uintptr_t gxbb_sec_entrypoint; -static volatile uint32_t gxbb_cpu0_go; +static uintptr_t gxl_sec_entrypoint; +static volatile uint32_t gxl_cpu0_go; static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value) { unsigned int core = plat_calc_core_pos(mpidr); - uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); + uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); mmio_write_64(cpu_mailbox_addr, value); } @@ -38,17 +38,17 @@ static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value) static void gxl_pm_reset(u_register_t mpidr) { unsigned int core = plat_calc_core_pos(mpidr); - uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8; + uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8; mmio_write_32(cpu_mailbox_addr, 0); } -static void __dead2 gxbb_system_reset(void) +static void __dead2 gxl_system_reset(void) { INFO("BL31: PSCI_SYSTEM_RESET\n"); u_register_t mpidr = read_mpidr_el1(); - uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3); + uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3); int ret; NOTICE("BL31: Reboot reason: 0x%x\n", status); @@ -57,7 +57,7 @@ static void __dead2 gxbb_system_reset(void) console_flush(); - mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); + mmio_write_32(AML_AO_RTI_STATUS_REG3, status); ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT); @@ -74,7 +74,7 @@ static void __dead2 gxbb_system_reset(void) panic(); } -static void __dead2 gxbb_system_off(void) +static void __dead2 gxl_system_off(void) { INFO("BL31: PSCI_SYSTEM_OFF\n"); @@ -97,7 +97,7 @@ static void __dead2 gxbb_system_off(void) panic(); } -static int32_t gxbb_pwr_domain_on(u_register_t mpidr) +static int32_t gxl_pwr_domain_on(u_register_t mpidr) { unsigned int core = plat_calc_core_pos(mpidr); @@ -105,9 +105,9 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr) if (core == AML_PRIMARY_CPU) { VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); - gxbb_cpu0_go = 1; - flush_dcache_range((uintptr_t)&gxbb_cpu0_go, - sizeof(gxbb_cpu0_go)); + gxl_cpu0_go = 1; + flush_dcache_range((uintptr_t)&gxl_cpu0_go, + sizeof(gxl_cpu0_go)); dsb(); isb(); @@ -116,7 +116,7 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr) return PSCI_E_SUCCESS; } - gxl_pm_set_reset_addr(mpidr, gxbb_sec_entrypoint); + gxl_pm_set_reset_addr(mpidr, gxl_sec_entrypoint); aml_scpi_set_css_power_state(mpidr, SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); dmbsy(); @@ -125,7 +125,7 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr) return PSCI_E_SUCCESS; } -static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) +static void gxl_pwr_domain_on_finish(const psci_power_state_t *target_state) { unsigned int core = plat_calc_core_pos(read_mpidr_el1()); @@ -133,9 +133,9 @@ static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) PLAT_LOCAL_STATE_OFF); if (core == AML_PRIMARY_CPU) { - gxbb_cpu0_go = 0; - flush_dcache_range((uintptr_t)&gxbb_cpu0_go, - sizeof(gxbb_cpu0_go)); + gxl_cpu0_go = 0; + flush_dcache_range((uintptr_t)&gxl_cpu0_go, + sizeof(gxl_cpu0_go)); dsb(); isb(); } @@ -144,7 +144,7 @@ static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) gicv2_cpuif_enable(); } -static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) +static void gxl_pwr_domain_off(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr_el1(); unsigned int core = plat_calc_core_pos(mpidr); @@ -159,7 +159,7 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); } -static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t +static void __dead2 gxl_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr_el1(); @@ -169,7 +169,7 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t if (core == AML_PRIMARY_CPU) { VERBOSE("BL31: CPU0 entering wait loop...\n"); - while (gxbb_cpu0_go == 0) + while (gxl_cpu0_go == 0) wfe(); VERBOSE("BL31: CPU0 resumed.\n"); @@ -181,7 +181,7 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t * In order to avoid an assert, mmu has to be disabled. */ disable_mmu_el3(); - ((void(*)(void))gxbb_sec_entrypoint)(); + ((void(*)(void))gxl_sec_entrypoint)(); } dsbsy(); @@ -195,20 +195,20 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t /******************************************************************************* * Platform handlers and setup function. ******************************************************************************/ -static const plat_psci_ops_t gxbb_ops = { - .pwr_domain_on = gxbb_pwr_domain_on, - .pwr_domain_on_finish = gxbb_pwr_domain_on_finish, - .pwr_domain_off = gxbb_pwr_domain_off, - .pwr_domain_pwr_down_wfi = gxbb_pwr_domain_pwr_down_wfi, - .system_off = gxbb_system_off, - .system_reset = gxbb_system_reset, +static const plat_psci_ops_t gxl_ops = { + .pwr_domain_on = gxl_pwr_domain_on, + .pwr_domain_on_finish = gxl_pwr_domain_on_finish, + .pwr_domain_off = gxl_pwr_domain_off, + .pwr_domain_pwr_down_wfi = gxl_pwr_domain_pwr_down_wfi, + .system_off = gxl_system_off, + .system_reset = gxl_system_reset, }; int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { - gxbb_sec_entrypoint = sec_entrypoint; - *psci_ops = &gxbb_ops; - gxbb_cpu0_go = 0; + gxl_sec_entrypoint = sec_entrypoint; + *psci_ops = &gxl_ops; + gxl_cpu0_go = 0; return 0; } -- cgit v1.2.3 From 9158854a58bbff71dbf926814e7addfdae94f4b1 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 28 Aug 2019 15:32:22 +0100 Subject: amlogic: Fix prefixes in the SoC specific files Remove the GXBB prefix where needed and add SoC specific prefixes for GXBB/GXL. Signed-off-by: Carlo Caione Change-Id: Ic3eb3a77ca2d9c779a9dee5cee786e9c16ecdb27 --- plat/amlogic/gxbb/gxbb_bl31_setup.c | 2 +- plat/amlogic/gxbb/gxbb_common.c | 38 +++++++++++------------ plat/amlogic/gxbb/gxbb_def.h | 40 ++++++++++++------------ plat/amlogic/gxbb/include/platform_def.h | 2 +- plat/amlogic/gxl/gxl_bl31_setup.c | 12 ++++---- plat/amlogic/gxl/gxl_common.c | 52 ++++++++++++++++---------------- plat/amlogic/gxl/gxl_def.h | 52 ++++++++++++++++---------------- 7 files changed, 99 insertions(+), 99 deletions(-) diff --git a/plat/amlogic/gxbb/gxbb_bl31_setup.c b/plat/amlogic/gxbb/gxbb_bl31_setup.c index 26419d40c..6d6b2ad70 100644 --- a/plat/amlogic/gxbb/gxbb_bl31_setup.c +++ b/plat/amlogic/gxbb/gxbb_bl31_setup.c @@ -73,7 +73,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, * In debug builds, we pass a special value in 'arg1' to verify platform * parameters from BL2 to BL31. In release builds it's not used. */ - assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL); + assert(arg1 == AML_BL31_PLAT_PARAM_VAL); /* Check that params passed from BL2 are not NULL. */ from_bl2 = (struct gxbb_bl31_param *) arg0; diff --git a/plat/amlogic/gxbb/gxbb_common.c b/plat/amlogic/gxbb/gxbb_common.c index 756093256..831bc66e5 100644 --- a/plat/amlogic/gxbb/gxbb_common.c +++ b/plat/amlogic/gxbb/gxbb_common.c @@ -20,32 +20,32 @@ /******************************************************************************* * Platform memory map regions ******************************************************************************/ -#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \ - GXBB_NSDRAM0_SIZE, \ +#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \ + AML_NSDRAM0_SIZE, \ MT_MEMORY | MT_RW | MT_NS) -#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \ - GXBB_NSDRAM1_SIZE, \ +#define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \ + AML_NSDRAM1_SIZE, \ MT_MEMORY | MT_RW | MT_NS) -#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \ - GXBB_SEC_DEVICE0_SIZE, \ +#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \ + AML_SEC_DEVICE0_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \ - GXBB_SEC_DEVICE1_SIZE, \ +#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \ + AML_SEC_DEVICE1_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \ - GXBB_TZRAM_SIZE, \ +#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \ + AML_TZRAM_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \ - GXBB_SEC_DEVICE2_SIZE, \ +#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \ + AML_SEC_DEVICE2_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \ - GXBB_SEC_DEVICE3_SIZE, \ +#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \ + AML_SEC_DEVICE3_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) static const mmap_region_t gxbb_mmap[] = { @@ -133,13 +133,13 @@ unsigned int plat_get_syscnt_freq2(void) { uint32_t val; - val = mmio_read_32(GXBB_SYS_CPU_CFG7); + val = mmio_read_32(AML_SYS_CPU_CFG7); val &= 0xFDFFFFFF; - mmio_write_32(GXBB_SYS_CPU_CFG7, val); + mmio_write_32(AML_SYS_CPU_CFG7, val); - val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL); + val = mmio_read_32(AML_AO_TIMESTAMP_CNTL); val &= 0xFFFFFE00; - mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val); + mmio_write_32(AML_AO_TIMESTAMP_CNTL, val); - return GXBB_OSC24M_CLK_IN_HZ; + return AML_OSC24M_CLK_IN_HZ; } diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h index 27bc0addd..2f6d1d2ae 100644 --- a/plat/amlogic/gxbb/gxbb_def.h +++ b/plat/amlogic/gxbb/gxbb_def.h @@ -12,16 +12,16 @@ /******************************************************************************* * System oscillator ******************************************************************************/ -#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ +#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ /******************************************************************************* * Memory regions ******************************************************************************/ -#define GXBB_NSDRAM0_BASE UL(0x01000000) -#define GXBB_NSDRAM0_SIZE UL(0x0F000000) +#define AML_NSDRAM0_BASE UL(0x01000000) +#define AML_NSDRAM0_SIZE UL(0x0F000000) -#define GXBB_NSDRAM1_BASE UL(0x10000000) -#define GXBB_NSDRAM1_SIZE UL(0x00100000) +#define AML_NSDRAM1_BASE UL(0x10000000) +#define AML_NSDRAM1_SIZE UL(0x00100000) #define BL31_BASE UL(0x10100000) #define BL31_SIZE UL(0x000C0000) @@ -31,14 +31,14 @@ #define AML_SHARE_MEM_INPUT_BASE UL(0x100FE000) #define AML_SHARE_MEM_OUTPUT_BASE UL(0x100FF000) -#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000) -#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000) +#define AML_SEC_DEVICE0_BASE UL(0xC0000000) +#define AML_SEC_DEVICE0_SIZE UL(0x09000000) -#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000) -#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000) +#define AML_SEC_DEVICE1_BASE UL(0xD0040000) +#define AML_SEC_DEVICE1_SIZE UL(0x00008000) -#define GXBB_TZRAM_BASE UL(0xD9000000) -#define GXBB_TZRAM_SIZE UL(0x00014000) +#define AML_TZRAM_BASE UL(0xD9000000) +#define AML_TZRAM_SIZE UL(0x00014000) /* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ /* Mailboxes */ @@ -46,14 +46,14 @@ #define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) #define AML_PSCI_MAILBOX_BASE UL(0xD9013F00) -#define GXBB_TZROM_BASE UL(0xD9040000) -#define GXBB_TZROM_SIZE UL(0x00010000) +#define AML_TZROM_BASE UL(0xD9040000) +#define AML_TZROM_SIZE UL(0x00010000) -#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000) -#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000) +#define AML_SEC_DEVICE2_BASE UL(0xDA000000) +#define AML_SEC_DEVICE2_SIZE UL(0x00200000) -#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000) -#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000) +#define AML_SEC_DEVICE3_BASE UL(0xDA800000) +#define AML_SEC_DEVICE3_SIZE UL(0x00200000) /******************************************************************************* * GIC-400 and interrupt handling related constants @@ -76,15 +76,15 @@ * UART definitions ******************************************************************************/ #define AML_UART0_AO_BASE UL(0xC81004C0) -#define AML_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ +#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ #define AML_UART_BAUDRATE U(115200) /******************************************************************************* * Memory-mapped I/O Registers ******************************************************************************/ -#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4) +#define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4) -#define GXBB_SYS_CPU_CFG7 UL(0xC8834664) +#define AML_SYS_CPU_CFG7 UL(0xC8834664) #define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C) diff --git a/plat/amlogic/gxbb/include/platform_def.h b/plat/amlogic/gxbb/include/platform_def.h index bd6ce32d9..a5cbe78e1 100644 --- a/plat/amlogic/gxbb/include/platform_def.h +++ b/plat/amlogic/gxbb/include/platform_def.h @@ -16,7 +16,7 @@ #define PLATFORM_LINKER_ARCH aarch64 /* Special value used to verify platform parameters from BL2 to BL31 */ -#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) +#define AML_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) #define PLATFORM_STACK_SIZE UL(0x1000) diff --git a/plat/amlogic/gxl/gxl_bl31_setup.c b/plat/amlogic/gxl/gxl_bl31_setup.c index e7c42184d..9c49646a9 100644 --- a/plat/amlogic/gxl/gxl_bl31_setup.c +++ b/plat/amlogic/gxl/gxl_bl31_setup.c @@ -103,7 +103,7 @@ void bl31_plat_arch_setup(void) static inline bool gxl_scp_ready(void) { - return GXBB_AO_RTI_SCP_IS_READY(mmio_read_32(GXBB_AO_RTI_SCP_STAT)); + return AML_AO_RTI_SCP_IS_READY(mmio_read_32(AML_AO_RTI_SCP_STAT)); } static inline void gxl_scp_boot(void) @@ -119,7 +119,7 @@ static inline void gxl_scp_boot(void) /******************************************************************************* * GICv2 driver setup information ******************************************************************************/ -static const interrupt_prop_t gxbb_interrupt_props[] = { +static const interrupt_prop_t gxl_interrupt_props[] = { INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, @@ -140,18 +140,18 @@ static const interrupt_prop_t gxbb_interrupt_props[] = { GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), }; -static const gicv2_driver_data_t gxbb_gic_data = { +static const gicv2_driver_data_t gxl_gic_data = { .gicd_base = AML_GICD_BASE, .gicc_base = AML_GICC_BASE, - .interrupt_props = gxbb_interrupt_props, - .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), + .interrupt_props = gxl_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(gxl_interrupt_props), }; void bl31_platform_setup(void) { aml_mhu_secure_init(); - gicv2_driver_init(&gxbb_gic_data); + gicv2_driver_init(&gxl_gic_data); gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); diff --git a/plat/amlogic/gxl/gxl_common.c b/plat/amlogic/gxl/gxl_common.c index f975cadda..631488846 100644 --- a/plat/amlogic/gxl/gxl_common.c +++ b/plat/amlogic/gxl/gxl_common.c @@ -18,35 +18,35 @@ /******************************************************************************* * Platform memory map regions ******************************************************************************/ -#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \ - GXBB_NSDRAM0_SIZE, \ +#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \ + AML_NSDRAM0_SIZE, \ MT_MEMORY | MT_RW | MT_NS) -#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \ - GXBB_NSDRAM1_SIZE, \ +#define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \ + AML_NSDRAM1_SIZE, \ MT_MEMORY | MT_RW | MT_NS) -#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \ - GXBB_SEC_DEVICE0_SIZE, \ +#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \ + AML_SEC_DEVICE0_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \ - GXBB_SEC_DEVICE1_SIZE, \ +#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \ + AML_SEC_DEVICE1_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \ - GXBB_TZRAM_SIZE, \ +#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \ + AML_TZRAM_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \ - GXBB_SEC_DEVICE2_SIZE, \ +#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \ + AML_SEC_DEVICE2_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \ - GXBB_SEC_DEVICE3_SIZE, \ +#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \ + AML_SEC_DEVICE3_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -static const mmap_region_t gxbb_mmap[] = { +static const mmap_region_t gxl_mmap[] = { MAP_NSDRAM0, MAP_NSDRAM1, MAP_SEC_DEVICE0, @@ -82,7 +82,7 @@ static const mmap_region_t gxbb_mmap[] = { void aml_setup_page_tables(void) { #if IMAGE_BL31 - const mmap_region_t gxbb_bl_mmap[] = { + const mmap_region_t gxl_bl_mmap[] = { MAP_BL31, MAP_BL_CODE, MAP_BL_RO_DATA, @@ -93,9 +93,9 @@ void aml_setup_page_tables(void) }; #endif - mmap_add(gxbb_bl_mmap); + mmap_add(gxl_bl_mmap); - mmap_add(gxbb_mmap); + mmap_add(gxl_mmap); init_xlat_tables(); } @@ -103,14 +103,14 @@ void aml_setup_page_tables(void) /******************************************************************************* * Function that sets up the console ******************************************************************************/ -static console_meson_t gxbb_console; +static console_meson_t gxl_console; void aml_console_init(void) { int rc = console_meson_register(AML_UART0_AO_BASE, AML_UART0_AO_CLK_IN_HZ, AML_UART_BAUDRATE, - &gxbb_console); + &gxl_console); if (rc == 0) { /* * The crash console doesn't use the multi console API, it uses @@ -120,7 +120,7 @@ void aml_console_init(void) panic(); } - console_set_scope(&gxbb_console.console, + console_set_scope(&gxl_console.console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); } @@ -131,13 +131,13 @@ unsigned int plat_get_syscnt_freq2(void) { uint32_t val; - val = mmio_read_32(GXBB_SYS_CPU_CFG7); + val = mmio_read_32(AML_SYS_CPU_CFG7); val &= 0xFDFFFFFF; - mmio_write_32(GXBB_SYS_CPU_CFG7, val); + mmio_write_32(AML_SYS_CPU_CFG7, val); - val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL); + val = mmio_read_32(AML_AO_TIMESTAMP_CNTL); val &= 0xFFFFFE00; - mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val); + mmio_write_32(AML_AO_TIMESTAMP_CNTL, val); - return GXBB_OSC24M_CLK_IN_HZ; + return AML_OSC24M_CLK_IN_HZ; } diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h index 3b604a619..1af101ef2 100644 --- a/plat/amlogic/gxl/gxl_def.h +++ b/plat/amlogic/gxl/gxl_def.h @@ -12,16 +12,16 @@ /******************************************************************************* * System oscillator ******************************************************************************/ -#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ +#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ /******************************************************************************* * Memory regions ******************************************************************************/ -#define GXBB_NSDRAM0_BASE UL(0x01000000) -#define GXBB_NSDRAM0_SIZE UL(0x0F000000) +#define AML_NSDRAM0_BASE UL(0x01000000) +#define AML_NSDRAM0_SIZE UL(0x0F000000) -#define GXBB_NSDRAM1_BASE UL(0x10000000) -#define GXBB_NSDRAM1_SIZE UL(0x00100000) +#define AML_NSDRAM1_BASE UL(0x10000000) +#define AML_NSDRAM1_SIZE UL(0x00100000) #define BL31_BASE UL(0x05100000) #define BL31_SIZE UL(0x000C0000) @@ -31,14 +31,14 @@ #define AML_SHARE_MEM_INPUT_BASE UL(0x050FE000) #define AML_SHARE_MEM_OUTPUT_BASE UL(0x050FF000) -#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000) -#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000) +#define AML_SEC_DEVICE0_BASE UL(0xC0000000) +#define AML_SEC_DEVICE0_SIZE UL(0x09000000) -#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000) -#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000) +#define AML_SEC_DEVICE1_BASE UL(0xD0040000) +#define AML_SEC_DEVICE1_SIZE UL(0x00008000) -#define GXBB_TZRAM_BASE UL(0xD9000000) -#define GXBB_TZRAM_SIZE UL(0x00014000) +#define AML_TZRAM_BASE UL(0xD9000000) +#define AML_TZRAM_SIZE UL(0x00014000) /* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ /* Mailboxes */ @@ -50,14 +50,14 @@ // * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * // * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) * -#define GXBB_TZROM_BASE UL(0xD9040000) -#define GXBB_TZROM_SIZE UL(0x00010000) +#define AML_TZROM_BASE UL(0xD9040000) +#define AML_TZROM_SIZE UL(0x00010000) -#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000) -#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000) +#define AML_SEC_DEVICE2_BASE UL(0xDA000000) +#define AML_SEC_DEVICE2_SIZE UL(0x00200000) -#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000) -#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000) +#define AML_SEC_DEVICE3_BASE UL(0xDA800000) +#define AML_SEC_DEVICE3_SIZE UL(0x00200000) /******************************************************************************* * GIC-400 and interrupt handling related constants @@ -80,23 +80,23 @@ * UART definitions ******************************************************************************/ #define AML_UART0_AO_BASE UL(0xC81004C0) -#define AML_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ +#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ #define AML_UART_BAUDRATE U(115200) /******************************************************************************* * Memory-mapped I/O Registers ******************************************************************************/ -#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4) +#define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4) -#define GXBB_SYS_CPU_CFG7 UL(0xC8834664) +#define AML_SYS_CPU_CFG7 UL(0xC8834664) #define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C) -#define GXBB_AO_RTI_SCP_STAT UL(0xDA10023C) -#define GXBB_AO_RTI_SCP_READY_OFF U(0x14) -#define GXBB_A0_RTI_SCP_READY_MASK U(3) -#define GXBB_AO_RTI_SCP_IS_READY(v) \ - ((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \ - GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK) +#define AML_AO_RTI_SCP_STAT UL(0xDA10023C) +#define AML_AO_RTI_SCP_READY_OFF U(0x14) +#define AML_A0_RTI_SCP_READY_MASK U(3) +#define AML_AO_RTI_SCP_IS_READY(v) \ + ((((v) >> AML_AO_RTI_SCP_READY_OFF) & \ + AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK) #define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404) #define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408) -- cgit v1.2.3 From 36bf55d66c3b01970f8aff0d3c2b70c9271717b7 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 5 Sep 2019 08:17:02 -0700 Subject: Tegra: memctrl_v2: fix "overflow before widen" coverity issue This patch fixes a coding error, where the size of the protected memory area was truncated due to an incorrect typecast. This defect was found by coverity and reported as CID 336781. Change-Id: I41878b0a9a5e5cd78ef3393fdc7b9ea7f7403ed3 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index a3ef5e131..2f31906d8 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -360,17 +361,15 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) if ((phys_base > vmem_end_old) || (video_mem_base > vmem_end_new)) { tegra_clear_videomem(video_mem_base, - (uint32_t)video_mem_size_mb << 20U); + video_mem_size_mb << 20U); } else { if (video_mem_base < phys_base) { non_overlap_area_size = phys_base - video_mem_base; - tegra_clear_videomem(video_mem_base, - (uint32_t)non_overlap_area_size); + tegra_clear_videomem(video_mem_base, non_overlap_area_size); } if (vmem_end_old > vmem_end_new) { non_overlap_area_size = vmem_end_old - vmem_end_new; - tegra_clear_videomem(vmem_end_new, - (uint32_t)non_overlap_area_size); + tegra_clear_videomem(vmem_end_new, non_overlap_area_size); } } -- cgit v1.2.3 From 1946b86843c99b8ab7070869fc7f12d441e1d967 Mon Sep 17 00:00:00 2001 From: Imre Kis Date: Thu, 8 Aug 2019 19:06:12 +0200 Subject: Add Linux DTS files for 32 bit threaded FVPs RevC models have the MT bit set and the affinities shifted in the MPIDR register. To make the Linux able to boot all CPUs it needs a modified DTS file containing the shifted affinity values. Beside these values the DTS files should be the same so the common part was moved into a new file which is included in the DTS files with shifted and non-shifted affinities. The same setup already exists for 64 bit systems. Signed-off-by: Imre Kis Change-Id: I90f7b9c8d8a24c9b3f97232441dbe0a29aa8976d --- fdts/fvp-base-gicv3-psci-aarch32-1t.dts | 41 ++++ fdts/fvp-base-gicv3-psci-aarch32-common.dtsi | 314 +++++++++++++++++++++++++++ fdts/fvp-base-gicv3-psci-aarch32.dts | 311 +------------------------- 3 files changed, 357 insertions(+), 309 deletions(-) create mode 100644 fdts/fvp-base-gicv3-psci-aarch32-1t.dts create mode 100644 fdts/fvp-base-gicv3-psci-aarch32-common.dtsi diff --git a/fdts/fvp-base-gicv3-psci-aarch32-1t.dts b/fdts/fvp-base-gicv3-psci-aarch32-1t.dts new file mode 100644 index 000000000..f7c936210 --- /dev/null +++ b/fdts/fvp-base-gicv3-psci-aarch32-1t.dts @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +/include/ "fvp-base-gicv3-psci-aarch32-common.dtsi" + +&CPU0 { + reg = <0x0>; +}; + +&CPU1 { + reg = <0x100>; +}; + +&CPU2 { + reg = <0x200>; +}; + +&CPU3 { + reg = <0x300>; +}; + +&CPU4 { + reg = <0x10000>; +}; + +&CPU5 { + reg = <0x10100>; +}; + +&CPU6 { + reg = <0x10200>; +}; + +&CPU7 { + reg = <0x10300>; +}; diff --git a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi new file mode 100644 index 000000000..6179c66e7 --- /dev/null +++ b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Base"; + compatible = "arm,vfp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, // GICD + <0x0 0x2f100000 0 0x200000>, // GICR + <0x0 0x2c000000 0 0x2000>, // GICC + <0x0 0x2c010000 0 0x2000>, // GICH + <0x0 0x2c02f000 0 0x2000>; // GICV + interrupts = <1 9 4>; + + its: its@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x2f020000 0x0 0x20000>; // GITS + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 0 0 4>, + <0 0 1 &gic 0 0 0 1 4>, + <0 0 2 &gic 0 0 0 2 4>, + <0 0 3 &gic 0 0 0 3 4>, + <0 0 4 &gic 0 0 0 4 4>, + <0 0 5 &gic 0 0 0 5 4>, + <0 0 6 &gic 0 0 0 6 4>, + <0 0 7 &gic 0 0 0 7 4>, + <0 0 8 &gic 0 0 0 8 4>, + <0 0 9 &gic 0 0 0 9 4>, + <0 0 10 &gic 0 0 0 10 4>, + <0 0 11 &gic 0 0 0 11 4>, + <0 0 12 &gic 0 0 0 12 4>, + <0 0 13 &gic 0 0 0 13 4>, + <0 0 14 &gic 0 0 0 14 4>, + <0 0 15 &gic 0 0 0 15 4>, + <0 0 16 &gic 0 0 0 16 4>, + <0 0 17 &gic 0 0 0 17 4>, + <0 0 18 &gic 0 0 0 18 4>, + <0 0 19 &gic 0 0 0 19 4>, + <0 0 20 &gic 0 0 0 20 4>, + <0 0 21 &gic 0 0 0 21 4>, + <0 0 22 &gic 0 0 0 22 4>, + <0 0 23 &gic 0 0 0 23 4>, + <0 0 24 &gic 0 0 0 24 4>, + <0 0 25 &gic 0 0 0 25 4>, + <0 0 26 &gic 0 0 0 26 4>, + <0 0 27 &gic 0 0 0 27 4>, + <0 0 28 &gic 0 0 0 28 4>, + <0 0 29 &gic 0 0 0 29 4>, + <0 0 30 &gic 0 0 0 30 4>, + <0 0 31 &gic 0 0 0 31 4>, + <0 0 32 &gic 0 0 0 32 4>, + <0 0 33 &gic 0 0 0 33 4>, + <0 0 34 &gic 0 0 0 34 4>, + <0 0 35 &gic 0 0 0 35 4>, + <0 0 36 &gic 0 0 0 36 4>, + <0 0 37 &gic 0 0 0 37 4>, + <0 0 38 &gic 0 0 0 38 4>, + <0 0 39 &gic 0 0 0 39 4>, + <0 0 40 &gic 0 0 0 40 4>, + <0 0 41 &gic 0 0 0 41 4>, + <0 0 42 &gic 0 0 0 42 4>; + + /include/ "rtsm_ve-motherboard-aarch32.dtsi" + }; + + panels { + panel@0 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff --git a/fdts/fvp-base-gicv3-psci-aarch32.dts b/fdts/fvp-base-gicv3-psci-aarch32.dts index b914ca0c1..2833cdfac 100644 --- a/fdts/fvp-base-gicv3-psci-aarch32.dts +++ b/fdts/fvp-base-gicv3-psci-aarch32.dts @@ -1,316 +1,9 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /dts-v1/; -/memreserve/ 0x80000000 0x00010000; - -/ { -}; - -/ { - model = "FVP Base"; - compatible = "arm,vfp-base", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - sys_poweroff = <0x84000008>; - sys_reset = <0x84000009>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "arm,psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <40>; - exit-latency-us = <100>; - min-residency-us = <150>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1000>; - min-residency-us = <2500>; - }; - }; - - CPU0:cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU1:cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU2:cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x2>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU3:cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x3>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU4:cpu@100 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU5:cpu@101 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU6:cpu@102 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x102>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU7:cpu@103 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x103>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x7F000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - - gic: interrupt-controller@2f000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x0 0x2f000000 0 0x10000>, // GICD - <0x0 0x2f100000 0 0x200000>, // GICR - <0x0 0x2c000000 0 0x2000>, // GICC - <0x0 0x2c010000 0 0x2000>, // GICH - <0x0 0x2c02f000 0 0x2000>; // GICV - interrupts = <1 9 4>; - - its: its@2f020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x2f020000 0x0 0x20000>; // GITS - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff01>, - <1 14 0xff01>, - <1 11 0xff01>, - <1 10 0xff01>; - clock-frequency = <100000000>; - }; - - timer@2a810000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x2a810000 0x0 0x10000>; - clock-frequency = <100000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - frame@2a830000 { - frame-number = <1>; - interrupts = <0 26 4>; - reg = <0x0 0x2a830000 0x0 0x10000>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - }; - - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 0 0 4>, - <0 0 1 &gic 0 0 0 1 4>, - <0 0 2 &gic 0 0 0 2 4>, - <0 0 3 &gic 0 0 0 3 4>, - <0 0 4 &gic 0 0 0 4 4>, - <0 0 5 &gic 0 0 0 5 4>, - <0 0 6 &gic 0 0 0 6 4>, - <0 0 7 &gic 0 0 0 7 4>, - <0 0 8 &gic 0 0 0 8 4>, - <0 0 9 &gic 0 0 0 9 4>, - <0 0 10 &gic 0 0 0 10 4>, - <0 0 11 &gic 0 0 0 11 4>, - <0 0 12 &gic 0 0 0 12 4>, - <0 0 13 &gic 0 0 0 13 4>, - <0 0 14 &gic 0 0 0 14 4>, - <0 0 15 &gic 0 0 0 15 4>, - <0 0 16 &gic 0 0 0 16 4>, - <0 0 17 &gic 0 0 0 17 4>, - <0 0 18 &gic 0 0 0 18 4>, - <0 0 19 &gic 0 0 0 19 4>, - <0 0 20 &gic 0 0 0 20 4>, - <0 0 21 &gic 0 0 0 21 4>, - <0 0 22 &gic 0 0 0 22 4>, - <0 0 23 &gic 0 0 0 23 4>, - <0 0 24 &gic 0 0 0 24 4>, - <0 0 25 &gic 0 0 0 25 4>, - <0 0 26 &gic 0 0 0 26 4>, - <0 0 27 &gic 0 0 0 27 4>, - <0 0 28 &gic 0 0 0 28 4>, - <0 0 29 &gic 0 0 0 29 4>, - <0 0 30 &gic 0 0 0 30 4>, - <0 0 31 &gic 0 0 0 31 4>, - <0 0 32 &gic 0 0 0 32 4>, - <0 0 33 &gic 0 0 0 33 4>, - <0 0 34 &gic 0 0 0 34 4>, - <0 0 35 &gic 0 0 0 35 4>, - <0 0 36 &gic 0 0 0 36 4>, - <0 0 37 &gic 0 0 0 37 4>, - <0 0 38 &gic 0 0 0 38 4>, - <0 0 39 &gic 0 0 0 39 4>, - <0 0 40 &gic 0 0 0 40 4>, - <0 0 41 &gic 0 0 0 41 4>, - <0 0 42 &gic 0 0 0 42 4>; - - /include/ "rtsm_ve-motherboard-aarch32.dtsi" - }; - - panels { - panel@0 { - compatible = "panel"; - mode = "XVGA"; - refresh = <60>; - xres = <1024>; - yres = <768>; - pixclock = <15748>; - left_margin = <152>; - right_margin = <48>; - upper_margin = <23>; - lower_margin = <3>; - hsync_len = <104>; - vsync_len = <4>; - sync = <0>; - vmode = "FB_VMODE_NONINTERLACED"; - tim2 = "TIM2_BCD", "TIM2_IPC"; - cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; - caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; - bpp = <16>; - }; - }; -}; +/include/ "fvp-base-gicv3-psci-aarch32-common.dtsi" -- cgit v1.2.3 From 9dd94382bd23db0fa201b254dc3f1bebdfd627c2 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Thu, 18 Jul 2019 14:25:33 +0100 Subject: Enable MTE support in both secure and non-secure worlds This patch adds support for the new Memory Tagging Extension arriving in ARMv8.5. MTE support is now enabled by default on systems that support at EL0. To enable it at ELx for both the non-secure and the secure world, the compiler flag CTX_INCLUDE_MTE_REGS includes register saving and restoring when necessary in order to prevent register leakage between the worlds. Change-Id: I2d4ea993d6b11654ea0d4757d00ca20d23acf36c Signed-off-by: Justin Chadwell --- Makefile | 10 ++++++++++ bl32/tsp/tsp_main.c | 8 ++++++++ include/arch/aarch64/arch.h | 8 ++++++++ include/arch/aarch64/arch_helpers.h | 6 ++++++ include/lib/el3_runtime/aarch64/context.h | 14 +++++++++++++- lib/el3_runtime/aarch64/context.S | 21 +++++++++++++++++++++ lib/el3_runtime/aarch64/context_mgmt.c | 29 +++++++++++++++++++++-------- make_helpers/defaults.mk | 5 +++++ 8 files changed, 92 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index 43ff8d2ff..71a52b56a 100644 --- a/Makefile +++ b/Makefile @@ -510,6 +510,14 @@ ifeq ($(ENABLE_BTI),1) $(info Branch Protection is an experimental feature) endif +ifeq ($(CTX_INCLUDE_MTE_REGS),1) + ifneq (${ARCH},aarch64) + $(error CTX_INCLUDE_MTE_REGS requires AArch64) + else + $(info CTX_INCLUDE_MTE_REGS is an experimental feature) + endif +endif + ################################################################################ # Process platform overrideable behaviour ################################################################################ @@ -631,6 +639,7 @@ $(eval $(call assert_boolean,CREATE_KEYS)) $(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS)) $(eval $(call assert_boolean,CTX_INCLUDE_FPREGS)) $(eval $(call assert_boolean,CTX_INCLUDE_PAUTH_REGS)) +$(eval $(call assert_boolean,CTX_INCLUDE_MTE_REGS)) $(eval $(call assert_boolean,DEBUG)) $(eval $(call assert_boolean,DYN_DISABLE_AUTH)) $(eval $(call assert_boolean,EL3_EXCEPTION_HANDLING)) @@ -686,6 +695,7 @@ $(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS)) $(eval $(call add_define,CTX_INCLUDE_FPREGS)) $(eval $(call add_define,CTX_INCLUDE_PAUTH_REGS)) $(eval $(call add_define,EL3_EXCEPTION_HANDLING)) +$(eval $(call add_define,CTX_INCLUDE_MTE_REGS)) $(eval $(call add_define,ENABLE_AMU)) $(eval $(call add_define,ENABLE_ASSERTIONS)) $(eval $(call add_define,ENABLE_BTI)) diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c index 30bf6ffc8..0a817351c 100644 --- a/bl32/tsp/tsp_main.c +++ b/bl32/tsp/tsp_main.c @@ -386,6 +386,14 @@ tsp_args_t *tsp_smc_handler(uint64_t func, */ tsp_get_magic(service_args); +#if CTX_INCLUDE_MTE_REGS + /* + * Write a dummy value to an MTE register, to simulate usage in the + * secure world + */ + write_gcr_el1(0x99); +#endif + /* Determine the function to perform based on the function ID */ switch (TSP_BARE_FID(func)) { case TSP_ADD: diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 5f84ecede..dc6a80340 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -898,4 +898,12 @@ ******************************************************************************/ #define SSBS S3_3_C4_C2_6 +/******************************************************************************* + * Armv8.5 - Memory Tagging Extension Registers + ******************************************************************************/ +#define TFSRE0_EL1 S3_0_C5_C6_1 +#define TFSR_EL1 S3_0_C5_C6_0 +#define RGSR_EL1 S3_0_C1_C0_5 +#define GCR_EL1 S3_0_C1_C0_6 + #endif /* ARCH_H */ diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index c17370647..c60f2e8f7 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -501,6 +501,12 @@ DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) +/* Armv8.5 MTE Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) + #define IS_IN_EL(x) \ (GET_EL(read_CurrentEl()) == MODE_EL##x) diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index 64fa8a9ea..e90a6e7d2 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -123,10 +123,22 @@ #define CTX_TIMER_SYSREGS_END CTX_AARCH32_END #endif /* NS_TIMER_SWITCH */ +#if CTX_INCLUDE_MTE_REGS +#define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0)) +#define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) +#define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) +#define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18)) + +/* Align to the next 16 byte boundary */ +#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) +#else +#define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END +#endif /* CTX_INCLUDE_MTE_REGS */ + /* * End of system registers. */ -#define CTX_SYSREGS_END CTX_TIMER_SYSREGS_END +#define CTX_SYSREGS_END CTX_MTE_REGS_END /******************************************************************************* * Constants that allow assembler code to access members of and the 'fp_regs' diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 53dc02e64..37bb12c80 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -145,6 +145,17 @@ func el1_sysregs_context_save str x14, [x0, #CTX_CNTKCTL_EL1] #endif + /* Save MTE system registers if the build has instructed so */ +#if CTX_INCLUDE_MTE_REGS + mrs x15, TFSRE0_EL1 + mrs x16, TFSR_EL1 + stp x15, x16, [x0, #CTX_TFSRE0_EL1] + + mrs x9, RGSR_EL1 + mrs x10, GCR_EL1 + stp x9, x10, [x0, #CTX_RGSR_EL1] +#endif + ret endfunc el1_sysregs_context_save @@ -229,6 +240,16 @@ func el1_sysregs_context_restore ldr x14, [x0, #CTX_CNTKCTL_EL1] msr cntkctl_el1, x14 #endif + /* Restore MTE system registers if the build has instructed so */ +#if CTX_INCLUDE_MTE_REGS + ldp x11, x12, [x0, #CTX_TFSRE0_EL1] + msr TFSRE0_EL1, x11 + msr TFSR_EL1, x12 + + ldp x13, x14, [x0, #CTX_RGSR_EL1] + msr RGSR_EL1, x13 + msr GCR_EL1, x14 +#endif /* No explict ISB required here as ERET covers it */ ret diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index bd5b3aa6c..446d9da92 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -137,17 +137,30 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) scr_el3 |= SCR_API_BIT | SCR_APK_BIT; #endif /* !CTX_INCLUDE_PAUTH_REGS */ - unsigned int mte = get_armv8_5_mte_support(); - /* - * Enable MTE support unilaterally for normal world if the CPU supports - * it. + * Enable MTE support. Support is enabled unilaterally for the normal + * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is + * set. */ - if (mte != MTE_UNIMPLEMENTED) { - if (security_state == NON_SECURE) { - scr_el3 |= SCR_ATA_BIT; - } + unsigned int mte = get_armv8_5_mte_support(); +#if CTX_INCLUDE_MTE_REGS + assert(mte == MTE_IMPLEMENTED_ELX); + scr_el3 |= SCR_ATA_BIT; +#else + if (mte == MTE_IMPLEMENTED_EL0) { + /* + * Can enable MTE across both worlds as no MTE registers are + * used + */ + scr_el3 |= SCR_ATA_BIT; + } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) { + /* + * Can only enable MTE in Non-Secure world without register + * saving + */ + scr_el3 |= SCR_ATA_BIT; } +#endif #ifdef IMAGE_BL31 /* diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index f63e46f39..66c2af4c3 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -214,6 +214,11 @@ ifeq (${ARCH},aarch32) override ENABLE_SPE_FOR_LOWER_ELS := 0 endif +# Include Memory Tagging Extension registers in cpu context. This must be set +# to 1 if the platform wants to use this feature in the Secure world and MTE is +# enabled at ELX. +CTX_INCLUDE_MTE_REGS := 0 + ENABLE_AMU := 0 # By default, enable Scalable Vector Extension if implemented for Non-secure -- cgit v1.2.3 From 88d493fb1b0a780809aea491fc30a145af92930b Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Thu, 18 Jul 2019 16:16:32 +0100 Subject: Add documentation for CTX_INCLUDE_MTE_REGS A new build flag, CTX_INCLUDE_MTE_REGS, has been added; this patch adds documentation for it in the User Guide along with instructions of what different values mean. Change-Id: I430a9c6ced06b1b6be317edbeff4f5530e30f63a Signed-off-by: Justin Chadwell --- docs/design/firmware-design.rst | 11 ++++++++++- docs/getting_started/user-guide.rst | 8 ++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index 00e199a20..dc0820826 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -2581,7 +2581,16 @@ Armv8.5-A ~~~~~~~~~ - Branch Target Identification feature is selected by ``BRANCH_PROTECTION`` - option set to 1. This option defaults to 0 and this is an experimental feature. + option set to 1. This option defaults to 0 and this is an experimental + feature. + +- Memory Tagging Extension feature is unconditionally enabled for both worlds + (at EL0 and S-EL0) if it is only supported at EL0. If instead it is + implemented at all ELs, it is unconditionally enabled for only the normal + world. To enable it for the secure world as well, the build option + ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement + MTE support at all, it is always disabled, no matter what build options + are used. Armv7-A ~~~~~~~ diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index b447f1493..855a79716 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -383,6 +383,13 @@ Common build options registers to be included when saving and restoring the CPU context. Default is 0. +- ``CTX_INCLUDE_MTE_REGS``: Enables register saving/reloading support for + ARMv8.5 Memory Tagging Extension. A value of 0 will disable + saving/reloading and restrict the use of MTE to the normal world if the + CPU has support, while a value of 1 enables the saving/reloading, allowing + the use of MTE in both the secure and non-secure worlds. Default is 0 + (disabled) and this feature is experimental. + - ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth registers to be included when saving and restoring the CPU context as @@ -798,6 +805,7 @@ Common build options cluster platforms). If this option is enabled, then warm boot path enables D-caches immediately after enabling MMU. This option defaults to 0. + Arm development platform specific build options ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -- cgit v1.2.3 From 0c411c78842929da7de9005bd1d988950920ac99 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Sat, 17 Aug 2019 01:10:02 +0300 Subject: Assert if power level value greater then PSCI_INVALID_PWR_LVL Signed-off-by: Deepika Bhavnani Change-Id: I4a496d5a8e7a9a127cd6224c968539eb74932fca --- lib/psci/psci_common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 022c87751..55a0d8722 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -192,6 +192,7 @@ static unsigned int get_power_on_target_pwrlvl(void) pwrlvl = psci_get_suspend_pwrlvl(); if (pwrlvl == PSCI_INVALID_PWR_LVL) pwrlvl = PLAT_MAX_PWR_LVL; + assert(pwrlvl < PSCI_INVALID_PWR_LVL); return pwrlvl; } -- cgit v1.2.3 From f992b960f9ac4206ecbd413a0310f11814b7242d Mon Sep 17 00:00:00 2001 From: kenny liang Date: Tue, 25 Jun 2019 15:33:48 +0800 Subject: mediatek: mt8183: refine GIC driver Refine MTK GIC driver. Remove unused codes. Signed-off-by: kenny liang Change-Id: I39e05ce7aa3c257e237fbc8e661cdde65cbcec7c --- plat/mediatek/mt8183/include/mt_gic_v3.h | 5 ---- plat/mediatek/mt8183/plat_mt_gic.c | 44 ++++---------------------------- 2 files changed, 5 insertions(+), 44 deletions(-) diff --git a/plat/mediatek/mt8183/include/mt_gic_v3.h b/plat/mediatek/mt8183/include/mt_gic_v3.h index e2706f46a..9d78ddb10 100644 --- a/plat/mediatek/mt8183/include/mt_gic_v3.h +++ b/plat/mediatek/mt8183/include/mt_gic_v3.h @@ -9,11 +9,6 @@ #include -enum irq_schedule_mode { - SW_MODE, - HW_MODE -}; - #define GIC_INT_MASK (MCUCFG_BASE + 0x5e8) #define GIC500_ACTIVE_SEL_SHIFT 3 #define GIC500_ACTIVE_SEL_MASK (0x7 << GIC500_ACTIVE_SEL_SHIFT) diff --git a/plat/mediatek/mt8183/plat_mt_gic.c b/plat/mediatek/mt8183/plat_mt_gic.c index 21443799f..ccb72be42 100644 --- a/plat/mediatek/mt8183/plat_mt_gic.c +++ b/plat/mediatek/mt8183/plat_mt_gic.c @@ -1,14 +1,14 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include #include #include -#include <../drivers/arm/gic/v3/gicv3_private.h> #include #include #include "plat_private.h" @@ -21,13 +21,9 @@ uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; -/* - * We save and restore the GICv3 context on system suspend. Allocate the - * data in the designated EL3 Secure carve-out memory - */ -gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram"); -gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram"); - +/* we save and restore the GICv3 context on system suspend */ +gicv3_redist_ctx_t rdist_ctx; +gicv3_dist_ctx_t dist_ctx; static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr) { @@ -42,27 +38,6 @@ gicv3_driver_data_t mt_gicv3_data = { .mpidr_to_core_pos = mt_mpidr_to_core_pos, }; -void setup_int_schedule_mode(enum irq_schedule_mode mode, - unsigned int active_cpu) -{ - assert(mode <= HW_MODE); - assert(active_cpu <= 0xFF); - - if (mode == HW_MODE) { - mmio_write_32(GIC_INT_MASK, - (mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_SEL_MASK)) - | (0x1 << GIC500_ACTIVE_SEL_SHIFT)); - } else if (mode == SW_MODE) { - mmio_write_32(GIC_INT_MASK, - (mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_SEL_MASK))); - } - - mmio_write_32(GIC_INT_MASK, - (mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_CPU_MASK)) - | (active_cpu << GIC500_ACTIVE_CPU_SHIFT)); - return; -} - void clear_sec_pol_ctl_en(void) { unsigned int i; @@ -85,7 +60,6 @@ void mt_gic_init(void) gicv3_rdistif_init(plat_my_core_pos()); gicv3_cpuif_enable(plat_my_core_pos()); - setup_int_schedule_mode(SW_MODE, 0xf); clear_sec_pol_ctl_en(); } @@ -94,14 +68,6 @@ void mt_gic_set_pending(uint32_t irq) gicv3_set_interrupt_pending(irq, plat_my_core_pos()); } -uint32_t mt_gic_get_pending(uint32_t irq) -{ - uint32_t bit = 1 << (irq % 32); - - return (mmio_read_32(gicv3_driver_data->gicd_base + - GICD_ISPENDR + irq / 32 * 4) & bit) ? 1 : 0; -} - void mt_gic_cpuif_enable(void) { gicv3_cpuif_enable(plat_my_core_pos()); -- cgit v1.2.3 From 7352f329e8db1ee655ef1a062ef6fc6dabb3bec2 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Thu, 2 May 2019 19:29:25 +0800 Subject: mediatek: mt8183: support CPU hotplug - Add DCM driver - Add SPMC driver - Implement core and cluster power on/off handlers Change-Id: I902002f8ea6f98fd73bf259188162b10d3939c72 Signed-off-by: kenny liang --- include/lib/cpus/aarch64/cortex_a53.h | 7 + include/lib/cpus/aarch64/cortex_a73.h | 7 + plat/mediatek/mt8183/bl31_plat_setup.c | 7 +- plat/mediatek/mt8183/drivers/spmc/mtspmc.c | 366 +++++ plat/mediatek/mt8183/drivers/spmc/mtspmc.h | 42 + plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h | 239 +++ plat/mediatek/mt8183/include/plat_dcm.h | 53 + plat/mediatek/mt8183/include/spm.h | 1715 ++++++++++++++++++++ plat/mediatek/mt8183/plat_dcm.c | 112 ++ plat/mediatek/mt8183/plat_pm.c | 105 +- plat/mediatek/mt8183/platform.mk | 5 +- 11 files changed, 2650 insertions(+), 8 deletions(-) create mode 100644 plat/mediatek/mt8183/drivers/spmc/mtspmc.c create mode 100644 plat/mediatek/mt8183/drivers/spmc/mtspmc.h create mode 100644 plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h create mode 100644 plat/mediatek/mt8183/include/plat_dcm.h create mode 100644 plat/mediatek/mt8183/include/spm.h create mode 100644 plat/mediatek/mt8183/plat_dcm.c diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 09db12b6e..ea7181ed4 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -73,4 +73,11 @@ ******************************************************************************/ #define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3 +/******************************************************************************* + * Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs + ******************************************************************************/ +#ifndef __ASSEMBLY__ +DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1) +#endif + #endif /* CORTEX_A53_H */ diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index 1238c0ef4..fb4f1ec0c 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -35,4 +35,11 @@ #define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2 +/******************************************************************************* + * Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs + ******************************************************************************/ +#ifndef __ASSEMBLY__ +DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1) +#endif + #endif /* CORTEX_A73_H */ diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c index e623e96ab..f20e8acdd 100644 --- a/plat/mediatek/mt8183/bl31_plat_setup.c +++ b/plat/mediatek/mt8183/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -95,6 +96,10 @@ void bl31_platform_setup(void) /* Init mcsi SF */ plat_mtk_cci_init_sf(); + +#if SPMC_MODE == 1 + spmc_init(); +#endif } /******************************************************************************* diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc.c b/plat/mediatek/mt8183/drivers/spmc/mtspmc.c new file mode 100644 index 000000000..ac8e1b47d --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc.c @@ -0,0 +1,366 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtspmc_private.h" + + +static void set_retention(int cluster, int tick) +{ + uint64_t cpuectlr; + + if (cluster) + cpuectlr = read_a73_cpuectlr_el1(); + else + cpuectlr = read_a53_cpuectlr_el1(); + + cpuectlr &= ~0x7ULL; + cpuectlr |= tick & 0x7; + + if (cluster) + write_a73_cpuectlr_el1(cpuectlr); + else + write_a53_cpuectlr_el1(cpuectlr); +} + +void spm_enable_cpu_auto_off(int cluster, int cpu) +{ + uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK); + + set_retention(cluster, 1); + mmio_clrbits_32(reg, SW_NO_WAIT_Q); +} + +void spm_disable_cpu_auto_off(int cluster, int cpu) +{ + uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK); + + mmio_setbits_32(reg, SW_NO_WAIT_Q); + set_retention(cluster, 0); +} + +void spm_set_cpu_power_off(int cluster, int cpu) +{ + mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON); +} + +void spm_enable_cluster_auto_off(int cluster) +{ + assert(cluster); + + mmio_clrbits_32(MCUCFG_MP2_SPMC, SW_NO_WAIT_Q); + mmio_clrbits_32(MCUCFG_MP2_COQ, BIT(0)); + + mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, MP1_SPMC_SRAM_DORMANT_EN); + + mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON); +} + +void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr) +{ + uintptr_t reg; + const uintptr_t mp2_bootreg[] = { + MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1, + MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 }; + + if (cluster) { + assert(cpu >= 0 && cpu < 4); + reg = mp2_bootreg[cpu]; + } else { + reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR); + } + + mmio_write_32(reg, bootaddr); +} + +uintptr_t mcucfg_get_bootaddr(int cluster, int cpu) +{ + uintptr_t reg; + const uintptr_t mp2_bootreg[] = { + MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1, + MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 }; + + if (cluster) { + assert(cpu >= 0 && cpu < 4); + reg = mp2_bootreg[cpu]; + } else { + reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR); + } + + return mmio_read_32(reg); +} + +void mcucfg_init_archstate(int cluster, int cpu, int arm64) +{ + uintptr_t reg; + int i; + + reg = per_cluster(cluster, MCUCFG_INITARCH); + i = cluster ? 16 : 12; + + mmio_setbits_32(reg, (arm64 & 1) << (i + cpu)); +} + +/** + * Return power state of specified subsystem + * + * @mask: mask to SPM_PWR_STATUS to query the power state + * of one subsystem. + * RETURNS: + * 0 (the subsys was powered off) + * 1 (the subsys was powered on) + */ +int spm_get_powerstate(uint32_t mask) +{ + return mmio_read_32(SPM_PWR_STATUS) & mask; +} + +int spm_get_cluster_powerstate(int cluster) +{ + uint32_t mask; + + mask = cluster ? PWR_STATUS_MP1_CPUTOP : PWR_STATUS_MP0_CPUTOP; + + return spm_get_powerstate(mask); +} + +int spm_get_cpu_powerstate(int cluster, int cpu) +{ + uint32_t i; + + /* + * a quick way to specify the mask of cpu[0-3]/cpu[4-7] in PWR_STATUS + * register which are the BITS[9:12](MP0_CPU0~3) and + * BITS[16:19](MP1_CPU0~3) + */ + i = (cluster) ? 16 : 9; + i = 1 << (i + cpu); + + return spm_get_powerstate(i); +} + +int spmc_init(void) +{ + /* enable SPM register control */ + mmio_write_32(SPM_POWERON_CONFIG_EN, + PROJECT_CODE | MD_BCLK_CG_EN | BCLK_CG_EN); + +#if SPMC_MODE == 1 + INFO("SPM: enable SPMC mode\n"); + + /* 0: SPMC mode 1: Legacy mode */ + mmio_write_32(SPM_BYPASS_SPMC, 0); + + mmio_clrbits_32(per_cluster(0, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND); + + mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); + mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); + mmio_clrbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); + mmio_clrbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); + + mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); + mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); + mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); +#endif + + mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND); + mmio_setbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_RST_B); + mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_CLK_DIS); + + mmio_clrbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); + mmio_clrbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); + mmio_clrbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); + mmio_clrbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); + + mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); + mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); + mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); + mmio_setbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); + + return 0; +} + +/** + * Power on a core with specified cluster and core index + * + * @cluster: the cluster ID of the CPU which to be powered on + * @cpu: the CPU ID of the CPU which to be powered on + */ +void spm_poweron_cpu(int cluster, int cpu) +{ + INFO("spmc: power on core %d.%d\n", cluster, cpu); + + /* STA_POWER_ON */ + /* Start to turn on MP0_CPU0 */ + + /* Set PWR_RST_B = 1 */ + mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); + + /* Set PWR_ON = 1 */ + mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON); + + /* Wait until MP0_CPU0_PWR_STA_MASK = 1 */ + while (!spm_get_cpu_powerstate(cluster, cpu)) + ; + + /* Finish to turn on MP0_CPU0 */ + INFO("spmc: power on core %d.%d successfully\n", cluster, cpu); +} + +/** + * Power off a core with specified cluster and core index + * + * @cluster: the cluster ID of the CPU which to be powered off + * @cpu: the CPU ID of the CPU which to be powered off + */ +void spm_poweroff_cpu(int cluster, int cpu) +{ + INFO("spmc: power off core %d.%d\n", cluster, cpu); + + /* Start to turn off MP0_CPU0 */ + /* Set PWR_ON_2ND = 0 */ + mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); + + /* Set PWR_ON = 0 */ + mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON); + + /* Wait until MP0_CPU0_PWR_STA_MASK = 0 */ + while (spm_get_cpu_powerstate(cluster, cpu)) + ; + + /* Set PWR_RST_B = 0 */ + mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); + + /* Finish to turn off MP0_CPU0 */ + INFO("spmc: power off core %d.%d successfully\n", cluster, cpu); +} + +/** + * Power off a cluster with specified index + * + * @cluster: the cluster index which to be powered off + */ +void spm_poweroff_cluster(int cluster) +{ + uint32_t mask; + uint32_t pwr_rst_ctl; + + INFO("spmc: power off cluster %d\n", cluster); + + /* Start to turn off MP0_CPUTOP */ + /* Set bus protect - step1 : 0 */ + mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK : + MP0_CPUTOP_PROT_STEP1_0_MASK; + mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_SET, mask); + + while ((mmio_read_32(INFRA_TOPAXI_PROTECTEN_STA1_1) & mask) != mask) + ; + + /* Set PWR_ON_2ND = 0 */ + mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), + PWRCTRL_PWR_ON_2ND); + + /* SPMC_DORMANT_ENABLE[0]=0 */ + mask = (cluster) ? MP1_SPMC_SRAM_DORMANT_EN : MP0_SPMC_SRAM_DORMANT_EN; + mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, mask); + + /* Set PWR_ON = 0" */ + mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON); + + /* Wait until MP0_CPUTOP_PWR_STA_MASK = 0 */ + while (spm_get_cluster_powerstate(cluster)) + ; + + /* NOTE + * Following flow only for BIG core cluster. It was from + * application note but not covered in mtcmos_ctrl.c + */ + if (cluster) { + pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL); + mmio_write_32(MCUCFG_MP2_PWR_RST_CTL, + (pwr_rst_ctl & ~SW_RST_B) | TOPAON_APB_MASK); + } + + /* CPU_EXT_BUCK_ISO[0]=1 */ + if (cluster) + mmio_setbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO); + + /* Finish to turn off MP0_CPUTOP */ + INFO("spmc: power off cluster %d successfully\n", cluster); +} + +/** + * Power on a cluster with specified index + * + * @cluster: the cluster index which to be powered on + */ +void spm_poweron_cluster(int cluster) +{ + uint32_t mask; + uint32_t pwr_rst_ctl; + + INFO("spmc: power on cluster %d\n", cluster); + + /* Start to turn on MP1_CPUTOP */ + + /* NOTE + * Following flow only for BIG core cluster. It was from + * application note but not covered in mtcmos_ctrl.c + */ + if (cluster) { + mmio_clrbits_32(MCUCFG_MP2_PWR_RST_CTL, SW_RST_B); + + /* CPU_EXT_BUCK_ISO[1]=0 */ + /* Set mp_vproc_ext_off to 0 to release vproc isolation control */ + mmio_clrbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO); + + /* NOTE + * Following flow only for BIG core cluster. It was from + * application note but not covered in mtcmos_ctrl.c + */ + pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL); + mmio_write_32(MCUCFG_MP2_PWR_RST_CTL, + (pwr_rst_ctl | SW_RST_B) & ~TOPAON_APB_MASK); + } + + /* Set PWR_ON_2ND = 0 */ + mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), + PWRCTRL_PWR_ON_2ND); + + /* Set PWR_RST_B = 1 */ + mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), + PWRCTRL_PWR_RST_B); + + /* Set PWR_CLK_DIS = 0 */ + mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), + PWRCTRL_PWR_CLK_DIS); + + /* Set PWR_ON = 1 */ + mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON); + + /* Wait until MP1_CPUTOP_PWR_STA_MASK = 1 */ + while (!spm_get_cluster_powerstate(cluster)) + ; + + /* Release bus protect - step1 : 0 */ + mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK : + MP0_CPUTOP_PROT_STEP1_0_MASK; + mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_CLR, mask); + + /* Finish to turn on MP1_CPUTOP */ + INFO("spmc: power on cluster %d successfully\n", cluster); +} diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc.h b/plat/mediatek/mt8183/drivers/spmc/mtspmc.h new file mode 100644 index 000000000..4cf3bcfb3 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTSPMC_H +#define MTSPMC_H + +/* + * CONFIG_SPMC_MODE: Select CPU power control mode. + * + * 0: Legacy + * Control power flow from SW through SPM register (MP*_PWR_CON). + * 1: HW + * Control power flow from SPMC. Most control flow and timing are handled + * by SPMC. + */ +#define SPMC_MODE 1 + +int spmc_init(void); + +void spm_poweron_cpu(int cluster, int cpu); +void spm_poweroff_cpu(int cluster, int cpu); + +void spm_poweroff_cluster(int cluster); +void spm_poweron_cluster(int cluster); + +int spm_get_cpu_powerstate(int cluster, int cpu); +int spm_get_cluster_powerstate(int cluster); +int spm_get_powerstate(uint32_t mask); + +void spm_enable_cpu_auto_off(int cluster, int cpu); +void spm_disable_cpu_auto_off(int cluster, int cpu); +void spm_set_cpu_power_off(int cluster, int cpu); +void spm_enable_cluster_auto_off(int cluster); + +void mcucfg_init_archstate(int cluster, int cpu, int arm64); +void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr); +uintptr_t mcucfg_get_bootaddr(int cluster, int cpu); + +#endif /* MTSPMC_H */ diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h new file mode 100644 index 000000000..613d4714f --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTSPMC_PRIVATE_H +#define MTSPMC_PRIVATE_H + +/* + * per_cpu/cluster helper + */ +struct per_cpu_reg { + int cluster_addr; + int cpu_stride; +}; + +#define per_cpu(cluster, cpu, reg) (reg[cluster].cluster_addr + \ + (cpu << reg[cluster].cpu_stride)) +#define per_cluster(cluster, reg) (reg[cluster].cluster_addr) + +/* SPMC related registers */ +#define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000) +/* bit-fields of SPM_POWERON_CONFIG_EN */ +#define BCLK_CG_EN (1 << 0) +#define MD_BCLK_CG_EN (1 << 1) +#define PROJECT_CODE (0xb16 << 16) + +#define SPM_PWR_STATUS (SPM_BASE + 0x180) +#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184) + +#define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4) +#define SPM_SPMC_DORMANT_ENABLE (SPM_BASE + 0x2b8) + +#define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204) +#define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208) +#define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C) +#define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210) +#define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214) +#define SPM_MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218) +#define SPM_MP1_CPU0_PWR_CON (SPM_BASE + 0x21C) +#define SPM_MP1_CPU1_PWR_CON (SPM_BASE + 0x220) +#define SPM_MP1_CPU2_PWR_CON (SPM_BASE + 0x224) +#define SPM_MP1_CPU3_PWR_CON (SPM_BASE + 0x228) +#define SPM_MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240) +#define SPM_MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244) +#define SPM_MP0_CPU0_L1_PDN (SPM_BASE + 0x248) +#define SPM_MP0_CPU1_L1_PDN (SPM_BASE + 0x24C) +#define SPM_MP0_CPU2_L1_PDN (SPM_BASE + 0x250) +#define SPM_MP0_CPU3_L1_PDN (SPM_BASE + 0x254) +#define SPM_MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258) +#define SPM_MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C) +#define SPM_MP1_CPU0_L1_PDN (SPM_BASE + 0x260) +#define SPM_MP1_CPU1_L1_PDN (SPM_BASE + 0x264) +#define SPM_MP1_CPU2_L1_PDN (SPM_BASE + 0x268) +#define SPM_MP1_CPU3_L1_PDN (SPM_BASE + 0x26C) + +#define SPM_CPU_EXT_BUCK_ISO (SPM_BASE + 0x290) +/* bit-fields of SPM_CPU_EXT_BUCK_ISO */ +#define MP0_EXT_BUCK_ISO (1 << 0) +#define MP1_EXT_BUCK_ISO (1 << 1) +#define MP_EXT_BUCK_ISO (1 << 2) + +/* bit-fields of SPM_PWR_STATUS */ +#define PWR_STATUS_MD (1 << 0) +#define PWR_STATUS_CONN (1 << 1) +#define PWR_STATUS_DDRPHY (1 << 2) +#define PWR_STATUS_DISP (1 << 3) +#define PWR_STATUS_MFG (1 << 4) +#define PWR_STATUS_ISP (1 << 5) +#define PWR_STATUS_INFRA (1 << 6) +#define PWR_STATUS_VDEC (1 << 7) +#define PWR_STATUS_MP0_CPUTOP (1 << 8) +#define PWR_STATUS_MP0_CPU0 (1 << 9) +#define PWR_STATUS_MP0_CPU1 (1 << 10) +#define PWR_STATUS_MP0_CPU2 (1 << 11) +#define PWR_STATUS_MP0_CPU3 (1 << 12) +#define PWR_STATUS_MCUSYS (1 << 14) +#define PWR_STATUS_MP1_CPUTOP (1 << 15) +#define PWR_STATUS_MP1_CPU0 (1 << 16) +#define PWR_STATUS_MP1_CPU1 (1 << 17) +#define PWR_STATUS_MP1_CPU2 (1 << 18) +#define PWR_STATUS_MP1_CPU3 (1 << 19) +#define PWR_STATUS_VEN (1 << 21) +#define PWR_STATUS_MFG_ASYNC (1 << 23) +#define PWR_STATUS_AUDIO (1 << 24) +#define PWR_STATUS_C2K (1 << 28) +#define PWR_STATUS_MD_INFRA (1 << 29) + + +/* bit-fields of SPM_*_PWR_CON */ +#define PWRCTRL_PWR_RST_B (1 << 0) +#define PWRCTRL_PWR_ISO (1 << 1) +#define PWRCTRL_PWR_ON (1 << 2) +#define PWRCTRL_PWR_ON_2ND (1 << 3) +#define PWRCTRL_PWR_CLK_DIS (1 << 4) +#define PWRCTRL_PWR_SRAM_CKISO (1 << 5) +#define PWRCTRL_PWR_SRAM_ISOINT_B (1 << 6) +#define PWRCTRL_PWR_SRAM_PD_SLPB_CLAMP (1 << 7) +#define PWRCTRL_PWR_SRAM_PDN (1 << 8) +#define PWRCTRL_PWR_SRAM_SLEEP_B (1 << 12) +#define PWRCTRL_PWR_SRAM_PDN_ACK (1 << 24) +#define PWRCTRL_PWR_SRAM_SLEEP_B_ACK (1 << 28) + +/* per_cpu registers for SPM_MP?_CPU?_PWR_CON */ +static const struct per_cpu_reg SPM_CPU_PWR[] = { + [0] = { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2 }, + [1] = { .cluster_addr = SPM_MP1_CPU0_PWR_CON, .cpu_stride = 2 }, +}; + +/* per_cluster registers for SPM_MP?_CPUTOP_PWR_CON */ +static const struct per_cpu_reg SPM_CLUSTER_PWR[] = { + [0] = { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON }, + [1] = { .cluster_addr = SPM_MP1_CPUTOP_PWR_CON }, +}; + +/* APB Module infracfg_ao */ +#define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_AO_BASE + 0x250) +#define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_AO_BASE + 0x258) +#define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_AO_BASE + 0x2A8) +#define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_AO_BASE + 0x2AC) + +/* bit-fields of INFRA_TOPAXI_PROTECTEN_1_SET */ +#define MP0_CPUTOP_PROT_STEP1_0_MASK ((1 << 10)|(1 << 12)| \ + (1 << 13)|(1 << 26)) +#define MP1_CPUTOP_PROT_STEP1_0_MASK ((1 << 11)|(1 << 14)| \ + (1 << 15)|(1 << 27)) + +/* bit-fields of INFRA_TOPAXI_PROTECTEN_STA1_1 */ +#define MP0_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 10)|(1 << 12)| \ + (1 << 13)|(1 << 26)) +#define MP1_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 11)|(1 << 14)| \ + (1 << 15)|(1 << 27)) + + +/* + * MCU configuration registers + */ +#define MCUCFG_MP0_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp0_axi_config) +#define MCUCFG_MP1_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp1_axi_config) +/* bit-fields of MCUCFG_MP?_AXI_CONFIG */ +#define MCUCFG_AXI_CONFIG_BROADCASTINNER (1 << 0) +#define MCUCFG_AXI_CONFIG_BROADCASTOUTER (1 << 1) +#define MCUCFG_AXI_CONFIG_BROADCASTCACHEMAINT (1 << 2) +#define MCUCFG_AXI_CONFIG_SYSBARDISABLE (1 << 3) +#define MCUCFG_AXI_CONFIG_ACINACTM (1 << 4) +#define MCUCFG_AXI_CONFIG_AINACTS (1 << 5) + +/* per_cpu registers for MCUCFG_MP?_AXI_CONFIG */ +static const struct per_cpu_reg MCUCFG_SCUCTRL[] = { + [0] = { .cluster_addr = MCUCFG_MP0_AXI_CONFIG }, + [1] = { .cluster_addr = MCUCFG_MP1_AXI_CONFIG }, +}; + +#define MCUCFG_MP0_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[2]) +#define MCUCFG_MP0_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[3]) +#define MCUCFG_MP1_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[2]) +#define MCUCFG_MP1_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[3]) + +#define MCUCFG_CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00) +/* bit-fields of MCUCFG_CPUSYS0_SPARKVRETCNTRL */ +#define CPU0_SPARK_VRET_CTRL (0x3f << 0) +#define CPU1_SPARK_VRET_CTRL (0x3f << 8) +#define CPU2_SPARK_VRET_CTRL (0x3f << 16) +#define CPU3_SPARK_VRET_CTRL (0x3f << 24) + +/* SPARK control in little cores */ +#define MCUCFG_CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1c30) +#define MCUCFG_CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1c34) +#define MCUCFG_CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1c38) +#define MCUCFG_CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1c3c) +/* bit-fields of MCUCFG_CPUSYS0_CPU?_SPMC_CTL */ +#define SW_SPARK_EN (1 << 0) +#define SW_NO_WAIT_Q (1 << 1) + +/* the MCUCFG which BIG cores used is at (MCUCFG_BASE + 0x2000) */ +#define MCUCFG_MP2_BASE (MCUCFG_BASE + 0x2000) +#define MCUCFG_MP2_PWR_RST_CTL (MCUCFG_MP2_BASE + 0x8) +/* bit-fields of MCUCFG_MP2_PWR_RST_CTL */ +#define SW_RST_B (1 << 0) +#define TOPAON_APB_MASK (1 << 1) + +#define MCUCFG_MP2_CPUCFG (MCUCFG_MP2_BASE + 0x208) + +#define MCUCFG_MP2_RVADDR0 (MCUCFG_MP2_BASE + 0x290) +#define MCUCFG_MP2_RVADDR1 (MCUCFG_MP2_BASE + 0x298) +#define MCUCFG_MP2_RVADDR2 (MCUCFG_MP2_BASE + 0x2c0) +#define MCUCFG_MP2_RVADDR3 (MCUCFG_MP2_BASE + 0x2c8) + +/* SPMC control */ +#define MCUCFG_MP0_SPMC (MCUCFG_BASE + 0x788) +#define MCUCFG_MP2_SPMC (MCUCFG_MP2_BASE + 0x2a0) +#define MCUCFG_MP2_COQ (MCUCFG_MP2_BASE + 0x2bC) + +/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG2 */ +static const struct per_cpu_reg MCUCFG_BOOTADDR[] = { + [0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG2, .cpu_stride = 3 }, +}; + +/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG3 */ +static const struct per_cpu_reg MCUCFG_INITARCH[] = { + [0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG3 }, + [1] = { .cluster_addr = MCUCFG_MP2_CPUCFG }, +}; + +/* SPARK control in BIG cores */ +#define MCUCFG_MP2_PTP3_CPU0_SPMC0 (MCUCFG_MP2_BASE + 0x430) +#define MCUCFG_MP2_PTP3_CPU0_SPMC1 (MCUCFG_MP2_BASE + 0x434) +#define MCUCFG_MP2_PTP3_CPU1_SPMC0 (MCUCFG_MP2_BASE + 0x438) +#define MCUCFG_MP2_PTP3_CPU1_SPMC1 (MCUCFG_MP2_BASE + 0x43c) +#define MCUCFG_MP2_PTP3_CPU2_SPMC0 (MCUCFG_MP2_BASE + 0x440) +#define MCUCFG_MP2_PTP3_CPU2_SPMC1 (MCUCFG_MP2_BASE + 0x444) +#define MCUCFG_MP2_PTP3_CPU3_SPMC0 (MCUCFG_MP2_BASE + 0x448) +#define MCUCFG_MP2_PTP3_CPU3_SPMC1 (MCUCFG_MP2_BASE + 0x44c) +/* bit-fields of MCUCFG_MP2_PTP3_CPU?_SPMC? */ +#define SW_SPARK_EN (1 << 0) +#define SW_NO_WAIT_Q (1 << 1) + +#define MCUCFG_MP2_SPARK2LDO (MCUCFG_MP2_BASE + 0x700) +/* bit-fields of MCUCFG_MP2_SPARK2LDO */ +#define SPARK_VRET_CTRL (0x3f << 0) +#define CPU0_SPARK_LDO_AMUXSEL (0xf << 6) +#define CPU1_SPARK_LDO_AMUXSEL (0xf << 10) +#define CPU2_SPARK_LDO_AMUXSEL (0xf << 14) +#define CPU3_SPARK_LDO_AMUXSEL (0xf << 18) + +/* per_cpu registers for SPARK */ +static const struct per_cpu_reg MCUCFG_SPARK[] = { + [0] = { .cluster_addr = MCUCFG_CPUSYS0_CPU0_SPMC_CTL, .cpu_stride = 2 }, + [1] = { .cluster_addr = MCUCFG_MP2_PTP3_CPU0_SPMC0, .cpu_stride = 3 }, +}; + +/* per_cpu registers for SPARK2LDO */ +static const struct per_cpu_reg MCUCFG_SPARK2LDO[] = { + [0] = { .cluster_addr = MCUCFG_CPUSYS0_SPARKVRETCNTRL }, + [1] = { .cluster_addr = MCUCFG_MP2_SPARK2LDO }, +}; + +#endif /* MTSPMC_PRIVATE_H */ diff --git a/plat/mediatek/mt8183/include/plat_dcm.h b/plat/mediatek/mt8183/include/plat_dcm.h new file mode 100644 index 000000000..afa9b63e8 --- /dev/null +++ b/plat/mediatek/mt8183/include/plat_dcm.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DCM_H +#define PLAT_DCM_H + +#define MP2_SYNC_DCM (MCUCFG_BASE + 0x2274) +#define MP2_SYNC_DCM_MASK (0x1 << 0) +#define MP2_SYNC_DCM_ON (0x1 << 0) +#define MP2_SYNC_DCM_OFF (0x0 << 0) + +extern uint64_t plat_dcm_mcsi_a_addr; +extern uint32_t plat_dcm_mcsi_a_val; +extern int plat_dcm_initiated; + +extern void plat_dcm_mcsi_a_backup(void); +extern void plat_dcm_mcsi_a_restore(void); +extern void plat_dcm_rgu_enable(void); +extern void plat_dcm_restore_cluster_on(unsigned long mpidr); +extern void plat_dcm_msg_handler(uint64_t x1); +extern unsigned long plat_dcm_get_enabled_cnt(uint64_t type); +extern void plat_dcm_init(void); + +#define ALL_DCM_TYPE (ARMCORE_DCM_TYPE | MCUSYS_DCM_TYPE \ + | STALL_DCM_TYPE | BIG_CORE_DCM_TYPE \ + | GIC_SYNC_DCM_TYPE | RGU_DCM_TYPE \ + | INFRA_DCM_TYPE \ + | DDRPHY_DCM_TYPE | EMI_DCM_TYPE | DRAMC_DCM_TYPE \ + | MCSI_DCM_TYPE) + +enum { + ARMCORE_DCM_TYPE = (1U << 0), + MCUSYS_DCM_TYPE = (1U << 1), + INFRA_DCM_TYPE = (1U << 2), + PERI_DCM_TYPE = (1U << 3), + EMI_DCM_TYPE = (1U << 4), + DRAMC_DCM_TYPE = (1U << 5), + DDRPHY_DCM_TYPE = (1U << 6), + STALL_DCM_TYPE = (1U << 7), + BIG_CORE_DCM_TYPE = (1U << 8), + GIC_SYNC_DCM_TYPE = (1U << 9), + LAST_CORE_DCM_TYPE = (1U << 10), + RGU_DCM_TYPE = (1U << 11), + TOPCKG_DCM_TYPE = (1U << 12), + LPDMA_DCM_TYPE = (1U << 13), + MCSI_DCM_TYPE = (1U << 14), + NR_DCM_TYPE = 15, +}; + +#endif /* PLAT_DCM_H */ \ No newline at end of file diff --git a/plat/mediatek/mt8183/include/spm.h b/plat/mediatek/mt8183/include/spm.h new file mode 100644 index 000000000..208d760d6 --- /dev/null +++ b/plat/mediatek/mt8183/include/spm.h @@ -0,0 +1,1715 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPM_H +#define SPM_H + +#define POWERON_CONFIG_EN (SPM_BASE + 0x000) +#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) +#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) +#define SPM_CLK_CON (SPM_BASE + 0x00C) +#define SPM_CLK_SETTLE (SPM_BASE + 0x010) +#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) +#define PCM_CON0 (SPM_BASE + 0x018) +#define PCM_CON1 (SPM_BASE + 0x01C) +#define PCM_IM_PTR (SPM_BASE + 0x020) +#define PCM_IM_LEN (SPM_BASE + 0x024) +#define PCM_REG_DATA_INI (SPM_BASE + 0x028) +#define PCM_PWR_IO_EN (SPM_BASE + 0x02C) +#define PCM_TIMER_VAL (SPM_BASE + 0x030) +#define PCM_WDT_VAL (SPM_BASE + 0x034) +#define PCM_IM_HOST_RW_PTR (SPM_BASE + 0x038) +#define PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03C) +#define PCM_EVENT_VECTOR0 (SPM_BASE + 0x040) +#define PCM_EVENT_VECTOR1 (SPM_BASE + 0x044) +#define PCM_EVENT_VECTOR2 (SPM_BASE + 0x048) +#define PCM_EVENT_VECTOR3 (SPM_BASE + 0x04C) +#define PCM_EVENT_VECTOR4 (SPM_BASE + 0x050) +#define PCM_EVENT_VECTOR5 (SPM_BASE + 0x054) +#define PCM_EVENT_VECTOR6 (SPM_BASE + 0x058) +#define PCM_EVENT_VECTOR7 (SPM_BASE + 0x05C) +#define PCM_EVENT_VECTOR8 (SPM_BASE + 0x060) +#define PCM_EVENT_VECTOR9 (SPM_BASE + 0x064) +#define PCM_EVENT_VECTOR10 (SPM_BASE + 0x068) +#define PCM_EVENT_VECTOR11 (SPM_BASE + 0x06C) +#define PCM_EVENT_VECTOR12 (SPM_BASE + 0x070) +#define PCM_EVENT_VECTOR13 (SPM_BASE + 0x074) +#define PCM_EVENT_VECTOR14 (SPM_BASE + 0x078) +#define PCM_EVENT_VECTOR15 (SPM_BASE + 0x07C) +#define PCM_EVENT_VECTOR_EN (SPM_BASE + 0x080) +#define SPM_SWINT (SPM_BASE + 0x08C) +#define SPM_SWINT_SET (SPM_BASE + 0x090) +#define SPM_SWINT_CLR (SPM_BASE + 0x094) +#define SPM_SCP_MAILBOX (SPM_BASE + 0x098) +#define SPM_SCP_IRQ (SPM_BASE + 0x09C) +#define SPM_TWAM_CON (SPM_BASE + 0x0A0) +#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4) +#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8) +#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) +#define SPM_IRQ_MASK (SPM_BASE + 0x0B4) +#define SPM_SRC_REQ (SPM_BASE + 0x0B8) +#define SPM_SRC_MASK (SPM_BASE + 0x0BC) +#define SPM_SRC2_MASK (SPM_BASE + 0x0C0) +#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0C4) +#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0C8) +#define SCP_CLK_CON (SPM_BASE + 0x0D0) +#define PCM_DEBUG_CON (SPM_BASE + 0x0D4) +#define PCM_REG0_DATA (SPM_BASE + 0x100) +#define PCM_REG1_DATA (SPM_BASE + 0x104) +#define PCM_REG2_DATA (SPM_BASE + 0x108) +#define PCM_REG3_DATA (SPM_BASE + 0x10C) +#define PCM_REG4_DATA (SPM_BASE + 0x110) +#define PCM_REG5_DATA (SPM_BASE + 0x114) +#define PCM_REG6_DATA (SPM_BASE + 0x118) +#define PCM_REG7_DATA (SPM_BASE + 0x11C) +#define PCM_REG8_DATA (SPM_BASE + 0x120) +#define PCM_REG9_DATA (SPM_BASE + 0x124) +#define PCM_REG10_DATA (SPM_BASE + 0x128) +#define PCM_REG11_DATA (SPM_BASE + 0x12C) +#define PCM_REG12_DATA (SPM_BASE + 0x130) +#define PCM_REG13_DATA (SPM_BASE + 0x134) +#define PCM_REG14_DATA (SPM_BASE + 0x138) +#define PCM_REG15_DATA (SPM_BASE + 0x13C) +#define PCM_REG12_MASK_B_STA (SPM_BASE + 0x140) +#define PCM_REG12_EXT_DATA (SPM_BASE + 0x144) +#define PCM_REG12_EXT_MASK_B_STA (SPM_BASE + 0x148) +#define PCM_EVENT_REG_STA (SPM_BASE + 0x14C) +#define PCM_TIMER_OUT (SPM_BASE + 0x150) +#define PCM_WDT_OUT (SPM_BASE + 0x154) +#define SPM_IRQ_STA (SPM_BASE + 0x158) +#define SPM_WAKEUP_STA (SPM_BASE + 0x15C) +#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x160) +#define SPM_WAKEUP_MISC (SPM_BASE + 0x164) +#define BUS_PROTECT_RDY (SPM_BASE + 0x168) +#define BUS_PROTECT2_RDY (SPM_BASE + 0x16C) +#define SUBSYS_IDLE_STA (SPM_BASE + 0x170) +#define CPU_IDLE_STA (SPM_BASE + 0x174) +#define PCM_FSM_STA (SPM_BASE + 0x178) +#define PWR_STATUS (SPM_BASE + 0x180) +#define PWR_STATUS_2ND (SPM_BASE + 0x184) +#define CPU_PWR_STATUS (SPM_BASE + 0x188) +#define CPU_PWR_STATUS_2ND (SPM_BASE + 0x18C) +#define PCM_WDT_LATCH_0 (SPM_BASE + 0x190) +#define PCM_WDT_LATCH_1 (SPM_BASE + 0x194) +#define PCM_WDT_LATCH_2 (SPM_BASE + 0x198) +#define DRAMC_DBG_LATCH (SPM_BASE + 0x19C) +#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1A0) +#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1A4) +#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1A8) +#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1AC) +#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1B0) +#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1B4) +#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1B8) +#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1BC) +#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1C0) +#define PCM_WDT_LATCH_3 (SPM_BASE + 0x1C4) +#define SPM_SRC_RDY_STA (SPM_BASE + 0x1D0) +#define MISC_STA (SPM_BASE + 0x1D4) +#define MCU_PWR_CON (SPM_BASE + 0x200) +#define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204) +#define MP0_CPU0_PWR_CON (SPM_BASE + 0x208) +#define MP0_CPU1_PWR_CON (SPM_BASE + 0x20C) +#define MP0_CPU2_PWR_CON (SPM_BASE + 0x210) +#define MP0_CPU3_PWR_CON (SPM_BASE + 0x214) +#define MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218) +#define MP1_CPU0_PWR_CON (SPM_BASE + 0x21C) +#define MP1_CPU1_PWR_CON (SPM_BASE + 0x220) +#define MP1_CPU2_PWR_CON (SPM_BASE + 0x224) +#define MP1_CPU3_PWR_CON (SPM_BASE + 0x228) +#define MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240) +#define MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244) +#define MP0_CPU0_L1_PDN (SPM_BASE + 0x248) +#define MP0_CPU1_L1_PDN (SPM_BASE + 0x24C) +#define MP0_CPU2_L1_PDN (SPM_BASE + 0x250) +#define MP0_CPU3_L1_PDN (SPM_BASE + 0x254) +#define MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258) +#define MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C) +#define MP1_CPU0_L1_PDN (SPM_BASE + 0x260) +#define MP1_CPU1_L1_PDN (SPM_BASE + 0x264) +#define MP1_CPU2_L1_PDN (SPM_BASE + 0x268) +#define MP1_CPU3_L1_PDN (SPM_BASE + 0x26C) +#define CPU_EXT_BUCK_ISO (SPM_BASE + 0x290) +#define DUMMY1_PWR_CON (SPM_BASE + 0x2B0) +#define BYPASS_SPMC (SPM_BASE + 0x2B4) +#define SPMC_DORMANT_ENABLE (SPM_BASE + 0x2B8) +#define ARMPLL_CLK_CON (SPM_BASE + 0x2BC) +#define SPMC_IN_RET (SPM_BASE + 0x2C0) +#define VDE_PWR_CON (SPM_BASE + 0x300) +#define VEN_PWR_CON (SPM_BASE + 0x304) +#define ISP_PWR_CON (SPM_BASE + 0x308) +#define DIS_PWR_CON (SPM_BASE + 0x30C) +#define MJC_PWR_CON (SPM_BASE + 0x310) +#define AUDIO_PWR_CON (SPM_BASE + 0x314) +#define IFR_PWR_CON (SPM_BASE + 0x318) +#define DPY_PWR_CON (SPM_BASE + 0x31C) +#define MD1_PWR_CON (SPM_BASE + 0x320) +#define MD2_PWR_CON (SPM_BASE + 0x324) +#define C2K_PWR_CON (SPM_BASE + 0x328) +#define CONN_PWR_CON (SPM_BASE + 0x32C) +#define VCOREPDN_PWR_CON (SPM_BASE + 0x330) +#define MFG_ASYNC_PWR_CON (SPM_BASE + 0x334) +#define MFG_PWR_CON (SPM_BASE + 0x338) +#define MFG_CORE0_PWR_CON (SPM_BASE + 0x33C) +#define MFG_CORE1_PWR_CON (SPM_BASE + 0x340) +#define CAM_PWR_CON (SPM_BASE + 0x344) +#define SYSRAM_CON (SPM_BASE + 0x350) +#define SYSROM_CON (SPM_BASE + 0x354) +#define SCP_SRAM_CON (SPM_BASE + 0x358) +#define GCPU_SRAM_CON (SPM_BASE + 0x35C) +#define MDSYS_INTF_INFRA_PWR_CON (SPM_BASE + 0x360) +#define MDSYS_INTF_MD1_PWR_CON (SPM_BASE + 0x364) +#define MDSYS_INTF_C2K_PWR_CON (SPM_BASE + 0x368) +#define BSI_TOP_SRAM_CON (SPM_BASE + 0x370) +#define DVFSP_SRAM_CON (SPM_BASE + 0x374) +#define MD_EXT_BUCK_ISO (SPM_BASE + 0x390) +#define DUMMY2_PWR_CON (SPM_BASE + 0x3B0) +#define MD1_OUTPUT_PISO_S_EN_IZ (SPM_BASE + 0x3B4) +#define SPM_DVFS_CON (SPM_BASE + 0x400) +#define SPM_MDBSI_CON (SPM_BASE + 0x404) +#define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x408) +#define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x40C) +#define SPM_BSI_GEN (SPM_BASE + 0x410) +#define SPM_BSI_EN_SR (SPM_BASE + 0x414) +#define SPM_BSI_CLK_SR (SPM_BASE + 0x418) +#define SPM_BSI_D0_SR (SPM_BASE + 0x41C) +#define SPM_BSI_D1_SR (SPM_BASE + 0x420) +#define SPM_BSI_D2_SR (SPM_BASE + 0x424) +#define SPM_AP_SEMA (SPM_BASE + 0x428) +#define SPM_SPM_SEMA (SPM_BASE + 0x42C) +#define AP2MD_CROSS_TRIGGER (SPM_BASE + 0x430) +#define AP_MDSRC_REQ (SPM_BASE + 0x434) +#define SPM2MD_DVFS_CON (SPM_BASE + 0x438) +#define MD2SPM_DVFS_CON (SPM_BASE + 0x43C) +#define DRAMC_DPY_CLK_SW_CON_RSV (SPM_BASE + 0x440) +#define DPY_LP_CON (SPM_BASE + 0x444) +#define CPU_DVFS_REQ (SPM_BASE + 0x448) +#define SPM_PLL_CON (SPM_BASE + 0x44C) +#define SPM_EMI_BW_MODE (SPM_BASE + 0x450) +#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x454) +#define ULPOSC_CON (SPM_BASE + 0x458) +#define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x460) +#define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x464) +#define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x470) +#define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x474) +#define SPM_SEMA_M0 (SPM_BASE + 0x480) +#define SPM_SEMA_M1 (SPM_BASE + 0x484) +#define SPM_SEMA_M2 (SPM_BASE + 0x488) +#define SPM_SEMA_M3 (SPM_BASE + 0x48C) +#define SPM_SEMA_M4 (SPM_BASE + 0x490) +#define SPM_SEMA_M5 (SPM_BASE + 0x494) +#define SPM_SEMA_M6 (SPM_BASE + 0x498) +#define SPM_SEMA_M7 (SPM_BASE + 0x49C) +#define SPM_SEMA_M8 (SPM_BASE + 0x4A0) +#define SPM_SEMA_M9 (SPM_BASE + 0x4A4) +#define SRAM_DREQ_ACK (SPM_BASE + 0x4AC) +#define SRAM_DREQ_CON (SPM_BASE + 0x4B0) +#define SRAM_DREQ_CON_SET (SPM_BASE + 0x4B4) +#define SRAM_DREQ_CON_CLR (SPM_BASE + 0x4B8) +#define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x500) +#define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x504) +#define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x508) +#define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x50C) +#define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x510) +#define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x514) +#define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x518) +#define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x51C) +#define MP0_CPU0_WFI_EN (SPM_BASE + 0x530) +#define MP0_CPU1_WFI_EN (SPM_BASE + 0x534) +#define MP0_CPU2_WFI_EN (SPM_BASE + 0x538) +#define MP0_CPU3_WFI_EN (SPM_BASE + 0x53C) +#define MP1_CPU0_WFI_EN (SPM_BASE + 0x540) +#define MP1_CPU1_WFI_EN (SPM_BASE + 0x544) +#define MP1_CPU2_WFI_EN (SPM_BASE + 0x548) +#define MP1_CPU3_WFI_EN (SPM_BASE + 0x54C) +#define CPU_PTPOD2_CON (SPM_BASE + 0x560) +#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570) +#define ROOT_CORE_ADDR (SPM_BASE + 0x574) +#define CPU_SPARE_CON (SPM_BASE + 0x580) +#define CPU_SPARE_CON_SET (SPM_BASE + 0x584) +#define CPU_SPARE_CON_CLR (SPM_BASE + 0x588) +#define SPM_SW_FLAG (SPM_BASE + 0x600) +#define SPM_SW_DEBUG (SPM_BASE + 0x604) +#define SPM_SW_RSV_0 (SPM_BASE + 0x608) +#define SPM_SW_RSV_1 (SPM_BASE + 0x60C) +#define SPM_SW_RSV_2 (SPM_BASE + 0x610) +#define SPM_SW_RSV_3 (SPM_BASE + 0x614) +#define SPM_SW_RSV_4 (SPM_BASE + 0x618) +#define SPM_SW_RSV_5 (SPM_BASE + 0x61C) +#define SPM_RSV_CON (SPM_BASE + 0x620) +#define SPM_RSV_STA (SPM_BASE + 0x624) +#define SPM_PASR_DPD_0 (SPM_BASE + 0x630) +#define SPM_PASR_DPD_1 (SPM_BASE + 0x634) +#define SPM_PASR_DPD_2 (SPM_BASE + 0x638) +#define SPM_PASR_DPD_3 (SPM_BASE + 0x63C) +#define SPM_SPARE_CON (SPM_BASE + 0x640) +#define SPM_SPARE_CON_SET (SPM_BASE + 0x644) +#define SPM_SPARE_CON_CLR (SPM_BASE + 0x648) +#define SPM_SW_RSV_6 (SPM_BASE + 0x64C) +#define SPM_SW_RSV_7 (SPM_BASE + 0x650) +#define SPM_SW_RSV_8 (SPM_BASE + 0x654) +#define SPM_SW_RSV_9 (SPM_BASE + 0x658) +#define SPM_SW_RSV_10 (SPM_BASE + 0x65C) +#define SPM_SW_RSV_11 (SPM_BASE + 0x660) +#define SPM_SW_RSV_12 (SPM_BASE + 0x664) +#define SPM_SW_RSV_13 (SPM_BASE + 0x668) +#define SPM_SW_RSV_14 (SPM_BASE + 0x66C) +#define SPM_SW_RSV_15 (SPM_BASE + 0x670) +#define SPM_SW_RSV_16 (SPM_BASE + 0x674) +#define SPM_SW_RSV_17 (SPM_BASE + 0x678) +#define SPM_SW_RSV_18 (SPM_BASE + 0x67C) +#define SPM_SW_RSV_19 (SPM_BASE + 0x680) +#define SW_CRTL_EVENT (SPM_BASE + 0x690) + + +#define MP1_CPU3_PWR_STA_MASK (1U << 19) +#define MP1_CPU2_PWR_STA_MASK (1U << 18) +#define MP1_CPU1_PWR_STA_MASK (1U << 17) +#define MP1_CPU0_PWR_STA_MASK (1U << 16) +#define MP1_CPUTOP_PWR_STA_MASK (1U << 15) +#define MCU_PWR_STA_MASK (1U << 14) +#define MP0_CPU3_PWR_STA_MASK (1U << 12) +#define MP0_CPU2_PWR_STA_MASK (1U << 11) +#define MP0_CPU1_PWR_STA_MASK (1U << 10) +#define MP0_CPU0_PWR_STA_MASK (1U << 9) +#define MP0_CPUTOP_PWR_STA_MASK (1U << 8) + + +#define MP1_CPU3_STANDBYWFI (1U << 17) +#define MP1_CPU2_STANDBYWFI (1U << 16) +#define MP1_CPU1_STANDBYWFI (1U << 15) +#define MP1_CPU0_STANDBYWFI (1U << 14) +#define MP0_CPU3_STANDBYWFI (1U << 13) +#define MP0_CPU2_STANDBYWFI (1U << 12) +#define MP0_CPU1_STANDBYWFI (1U << 11) +#define MP0_CPU0_STANDBYWFI (1U << 10) + +#define MP0_SPMC_SRAM_DORMANT_EN (1<<0) +#define MP1_SPMC_SRAM_DORMANT_EN (1<<1) +#define MP2_SPMC_SRAM_DORMANT_EN (1<<2) + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ + +/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ +#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ + +/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ +#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ + +/* SPM_CLK_CON (0x10006000+0x00C) */ +#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ +#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ +#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ +#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ +#define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ +#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ +#define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */ +#define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ +#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ +#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ +#define SRCLKEN1_EN_LSB (1U << 14) /* 1b */ +#define SCP_DCM_EN_LSB (1U << 15) /* 1b */ +#define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */ +#define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */ + +/* SPM_CLK_SETTLE (0x10006000+0x010) */ +#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ + +/* SPM_AP_STANDBY_CON (0x10006000+0x014) */ +#define WFI_OP_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */ +#define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ +#define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ +#define MM_MASK_B_LSB (1U << 16) /* 2b */ +#define MD_DDR_EN_DBC_EN_LSB (1U << 18) /* 1b */ +#define MD_MASK_B_LSB (1U << 19) /* 2b */ +#define SCP_MASK_B_LSB (1U << 21) /* 1b */ +#define LTE_MASK_B_LSB (1U << 22) /* 1b */ +#define SRCCLKENI_MASK_B_LSB (1U << 23) /* 1b */ +#define MD_APSRC_1_SEL_LSB (1U << 24) /* 1b */ +#define MD_APSRC_0_SEL_LSB (1U << 25) /* 1b */ +#define CONN_MASK_B_LSB (1U << 26) /* 1b */ +#define CONN_APSRC_SEL_LSB (1U << 27) /* 1b */ + +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_KICK_L_LSB (1U << 0) /* 1b */ +#define IM_KICK_L_LSB (1U << 1) /* 1b */ +#define PCM_CK_EN_LSB (1U << 2) /* 1b */ +#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ +#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ +#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ + +/* PCM_CON1 (0x10006000+0x01C) */ +#define IM_SLAVE_LSB (1U << 0) /* 1b */ +#define IM_SLEEP_LSB (1U << 1) /* 1b */ +#define MIF_APBEN_LSB (1U << 3) /* 1b */ +#define IM_PDN_LSB (1U << 4) /* 1b */ +#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ +#define IM_NONRP_EN_LSB (1U << 6) /* 1b */ +#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ +#define PCM_WDT_EN_LSB (1U << 8) /* 1b */ +#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ +#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ +#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ +#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ +#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ +#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ + +/* PCM_IM_PTR (0x10006000+0x020) */ +#define PCM_IM_PTR_LSB (1U << 0) /* 32b */ + +/* PCM_IM_LEN (0x10006000+0x024) */ +#define PCM_IM_LEN_LSB (1U << 0) /* 13b */ + +/* PCM_REG_DATA_INI (0x10006000+0x028) */ +#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ + +/* PCM_PWR_IO_EN (0x10006000+0x02C) */ +#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ +#define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */ + +/* PCM_TIMER_VAL (0x10006000+0x030) */ +#define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ + +/* PCM_WDT_VAL (0x10006000+0x034) */ +#define PCM_WDT_VAL_LSB (1U << 0) /* 32b */ + +/* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */ +#define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */ +#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ +#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ + +/* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */ +#define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */ + +/* PCM_EVENT_VECTOR0 (0x10006000+0x040) */ +#define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR1 (0x10006000+0x044) */ +#define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR2 (0x10006000+0x048) */ +#define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */ +#define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR4 (0x10006000+0x050) */ +#define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR5 (0x10006000+0x054) */ +#define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR6 (0x10006000+0x058) */ +#define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */ +#define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR8 (0x10006000+0x060) */ +#define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR9 (0x10006000+0x064) */ +#define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR10 (0x10006000+0x068) */ +#define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */ +#define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR12 (0x10006000+0x070) */ +#define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR13 (0x10006000+0x074) */ +#define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR14 (0x10006000+0x078) */ +#define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */ +#define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */ + +/* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */ +#define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */ + +/* SPM_SWINT (0x10006000+0x08C) */ +#define SPM_SWINT_LSB (1U << 0) /* 10b */ + +/* SPM_SWINT_SET (0x10006000+0x090) */ +#define SPM_SWINT_SET_LSB (1U << 0) /* 10b */ + +/* SPM_SWINT_CLR (0x10006000+0x094) */ +#define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */ + +/* SPM_SCP_MAILBOX (0x10006000+0x098) */ +#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ + +/* SPM_SCP_IRQ (0x10006000+0x09C) */ +#define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */ +#define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */ + +/* SPM_TWAM_CON (0x10006000+0x0A0) */ +#define TWAM_ENABLE_LSB (1U << 0) /* 1b */ +#define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */ +#define TWAM_SW_RST_LSB (1U << 2) /* 1b */ +#define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */ +#define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */ +#define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */ +#define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */ +#define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */ +#define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */ +#define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */ +#define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */ + +/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ +#define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ + +/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ +#define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */ + +/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ +#define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */ + +/* SPM_IRQ_MASK (0x10006000+0x0B4) */ +#define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */ +#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ +#define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */ + +/* SPM_SRC_REQ (0x10006000+0x0B8) */ +#define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ +#define SPM_F26M_REQ_LSB (1U << 1) /* 1b */ +#define SPM_LTE_REQ_LSB (1U << 2) /* 1b */ +#define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ +#define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ +#define SPM_DVFS_REQ_LSB (1U << 5) /* 1b */ +#define SPM_DVFS_FORCE_DOWN_LSB (1U << 6) /* 1b */ +#define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */ +#define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */ +#define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */ + +/* SPM_SRC_MASK (0x10006000+0x0BC) */ +#define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */ +#define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */ +#define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */ +#define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */ +#define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */ +#define CCIFMD_MD1_EVENT_MASK_B_LSB (1U << 5) /* 1b */ +#define CCIFMD_MD2_EVENT_MASK_B_LSB (1U << 6) /* 1b */ +#define DSI0_VSYNC_MASK_B_LSB (1U << 7) /* 1b */ +#define DSI1_VSYNC_MASK_B_LSB (1U << 8) /* 1b */ +#define DPI_VSYNC_MASK_B_LSB (1U << 9) /* 1b */ +#define ISP0_VSYNC_MASK_B_LSB (1U << 10) /* 1b */ +#define ISP1_VSYNC_MASK_B_LSB (1U << 11) /* 1b */ +#define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 12) /* 1b */ +#define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 13) /* 1b */ +#define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 14) /* 1b */ +#define MD32_SRCCLKENA_INFRA_MASK_B_LSB (1U << 15) /* 1b */ +#define SRCCLKENI_INFRA_MASK_B_LSB (1U << 16) /* 1b */ +#define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 17) /* 1b */ +#define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 18) /* 1b */ +#define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 19) /* 1b */ +#define MD32_APSRCREQ_INFRA_MASK_B_LSB (1U << 20) /* 1b */ +#define MD_DDR_EN_0_MASK_B_LSB (1U << 21) /* 1b */ +#define MD_DDR_EN_1_MASK_B_LSB (1U << 22) /* 1b */ +#define MD_VRF18_REQ_0_MASK_B_LSB (1U << 23) /* 1b */ +#define MD_VRF18_REQ_1_MASK_B_LSB (1U << 24) /* 1b */ +#define MD1_DVFS_REQ_MASK_LSB (1U << 25) /* 2b */ +#define CPU_DVFS_REQ_MASK_LSB (1U << 27) /* 1b */ +#define EMI_BW_DVFS_REQ_MASK_LSB (1U << 28) /* 1b */ +#define MD_SRCCLKENA_0_DVFS_REQ_MASK_B_LSB (1U << 29) /* 1b */ +#define MD_SRCCLKENA_1_DVFS_REQ_MASK_B_LSB (1U << 30) /* 1b */ +#define CONN_SRCCLKENA_DVFS_REQ_MASK_B_LSB (1U << 31) /* 1b */ + +/* SPM_SRC2_MASK (0x10006000+0x0C0) */ +#define DVFS_HALT_MASK_B_LSB (1U << 0) /* 5b */ +#define VDEC_REQ_MASK_B_LSB (1U << 6) /* 1b */ +#define GCE_REQ_MASK_B_LSB (1U << 7) /* 1b */ +#define CPU_MD_DVFS_REQ_MERGE_MASK_B_LSB (1U << 8) /* 1b */ +#define MD_DDR_EN_DVFS_HALT_MASK_B_LSB (1U << 9) /* 2b */ +#define DSI0_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 11) /* 1b */ +#define DSI1_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 12) /* 1b */ +#define DPI_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 13) /* 1b */ +#define ISP0_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 14) /* 1b */ +#define ISP1_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 15) /* 1b */ +#define CONN_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */ +#define DISP_REQ_MASK_B_LSB (1U << 17) /* 1b */ +#define DISP1_REQ_MASK_B_LSB (1U << 18) /* 1b */ +#define MFG_REQ_MASK_B_LSB (1U << 19) /* 1b */ +#define C2K_PS_RCCIF_WAKE_MASK_B_LSB (1U << 20) /* 1b */ +#define C2K_L1_RCCIF_WAKE_MASK_B_LSB (1U << 21) /* 1b */ +#define PS_C2K_RCCIF_WAKE_MASK_B_LSB (1U << 22) /* 1b */ +#define L1_C2K_RCCIF_WAKE_MASK_B_LSB (1U << 23) /* 1b */ +#define SDIO_ON_DVFS_REQ_MASK_B_LSB (1U << 24) /* 1b */ +#define EMI_BOOST_DVFS_REQ_MASK_B_LSB (1U << 25) /* 1b */ +#define CPU_MD_EMI_DVFS_REQ_PROT_DIS_LSB (1U << 26) /* 1b */ +#define DRAMC_SPCMD_APSRC_REQ_MASK_B_LSB (1U << 27) /* 1b */ + +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ +#define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ + +/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */ +#define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */ + +/* SCP_CLK_CON (0x10006000+0x0D0) */ +#define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ + +/* PCM_DEBUG_CON (0x10006000+0x0D4) */ +#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ + +/* PCM_REG0_DATA (0x10006000+0x100) */ +#define PCM_REG0_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG1_DATA (0x10006000+0x104) */ +#define PCM_REG1_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG2_DATA (0x10006000+0x108) */ +#define PCM_REG2_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG3_DATA (0x10006000+0x10C) */ +#define PCM_REG3_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG4_DATA (0x10006000+0x110) */ +#define PCM_REG4_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG5_DATA (0x10006000+0x114) */ +#define PCM_REG5_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG6_DATA (0x10006000+0x118) */ +#define PCM_REG6_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG7_DATA (0x10006000+0x11C) */ +#define PCM_REG7_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG8_DATA (0x10006000+0x120) */ +#define PCM_REG8_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG9_DATA (0x10006000+0x124) */ +#define PCM_REG9_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG10_DATA (0x10006000+0x128) */ +#define PCM_REG10_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG11_DATA (0x10006000+0x12C) */ +#define PCM_REG11_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG12_DATA (0x10006000+0x130) */ +#define PCM_REG12_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG13_DATA (0x10006000+0x134) */ +#define PCM_REG13_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG14_DATA (0x10006000+0x138) */ +#define PCM_REG14_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG15_DATA (0x10006000+0x13C) */ +#define PCM_REG15_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG12_MASK_B_STA (0x10006000+0x140) */ +#define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */ + +/* PCM_REG12_EXT_DATA (0x10006000+0x144) */ +#define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */ + +/* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */ +#define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */ + +/* PCM_EVENT_REG_STA (0x10006000+0x14C) */ +#define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */ + +/* PCM_TIMER_OUT (0x10006000+0x150) */ +#define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */ + +/* PCM_WDT_OUT (0x10006000+0x154) */ +#define PCM_WDT_OUT_LSB (1U << 0) /* 32b */ + +/* SPM_IRQ_STA (0x10006000+0x158) */ +#define TWAM_IRQ_LSB (1U << 2) /* 1b */ +#define PCM_IRQ_LSB (1U << 3) /* 1b */ +#define SPM_IRQ_SWINT_LSB (1U << 4) /* 10b */ + +/* SPM_WAKEUP_STA (0x10006000+0x15C) */ +#define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */ + +/* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */ +#define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */ + +/* SPM_WAKEUP_MISC (0x10006000+0x164) */ +#define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */ +#define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */ +#define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */ + +/* BUS_PROTECT_RDY (0x10006000+0x168) */ +#define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */ + +/* BUS_PROTECT2_RDY (0x10006000+0x16C) */ +#define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */ + +/* SUBSYS_IDLE_STA (0x10006000+0x170) */ +#define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */ + +/* CPU_IDLE_STA (0x10006000+0x174) */ +#define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */ +#define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */ +#define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */ +#define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */ +#define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */ +#define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */ +#define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */ +#define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */ +#define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */ +#define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */ +#define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */ +#define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */ +#define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */ +#define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */ +#define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */ +#define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */ +#define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */ +#define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */ +#define MCUSYS_IDLE_LSB (1U << 23) /* 1b */ + +/* PCM_FSM_STA (0x10006000+0x178) */ +#define EXEC_INST_OP_LSB (1U << 0) /* 4b */ +#define PC_STATE_LSB (1U << 4) /* 3b */ +#define IM_STATE_LSB (1U << 7) /* 3b */ +#define MASTER_STATE_LSB (1U << 10) /* 5b */ +#define EVENT_FSM_LSB (1U << 15) /* 3b */ +#define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */ +#define PCM_KICK_LSB (1U << 21) /* 1b */ +#define IM_KICK_LSB (1U << 22) /* 1b */ +#define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */ +#define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */ + +/* PWR_STATUS (0x10006000+0x180) */ +#define PWR_STATUS_LSB (1U << 0) /* 32b */ + +/* PWR_STATUS_2ND (0x10006000+0x184) */ +#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ + +/* CPU_PWR_STATUS (0x10006000+0x188) */ +#define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */ + +/* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */ +#define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ + +/* PCM_WDT_LATCH_0 (0x10006000+0x190) */ +#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ + +/* PCM_WDT_LATCH_1 (0x10006000+0x194) */ +#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ + +/* PCM_WDT_LATCH_2 (0x10006000+0x198) */ +#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ + +/* DRAMC_DBG_LATCH (0x10006000+0x19C) */ +#define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */ + +/* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */ +#define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */ + +/* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */ +#define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */ + +/* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */ +#define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */ + +/* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */ +#define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */ + +/* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */ +#define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */ + +/* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */ +#define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */ + +/* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */ +#define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */ + +/* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */ +#define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */ + +/* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */ +#define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */ + +/* PCM_WDT_LATCH_3 (0x10006000+0x1C4) */ +#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ + +/* SPM_SRC_RDY_STA (0x10006000+0x1D0) */ +#define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */ +#define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */ + +/* MISC_STA (0x10006000+0x1D4) */ +#define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */ + +/* MCU_PWR_CON (0x10006000+0x200) */ +#define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MCU_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MCU_PWR_ON_LSB (1U << 2) /* 1b */ +#define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ + +/* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */ +#define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ + +/* MP0_CPU0_PWR_CON (0x10006000+0x208) */ +#define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ + +/* MP0_CPU1_PWR_CON (0x10006000+0x20C) */ +#define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ + +/* MP0_CPU2_PWR_CON (0x10006000+0x210) */ +#define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ + +/* MP0_CPU3_PWR_CON (0x10006000+0x214) */ +#define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ + +/* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */ +#define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ + +/* MP1_CPU0_PWR_CON (0x10006000+0x21C) */ +#define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ + +/* MP1_CPU1_PWR_CON (0x10006000+0x220) */ +#define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ + +/* MP1_CPU2_PWR_CON (0x10006000+0x224) */ +#define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ + +/* MP1_CPU3_PWR_CON (0x10006000+0x228) */ +#define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ + +/* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */ +#define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ + +/* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */ +#define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ + +/* MP0_CPU0_L1_PDN (0x10006000+0x248) */ +#define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ + +/* MP0_CPU1_L1_PDN (0x10006000+0x24C) */ +#define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ + +/* MP0_CPU2_L1_PDN (0x10006000+0x250) */ +#define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ + +/* MP0_CPU3_L1_PDN (0x10006000+0x254) */ +#define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ + +/* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */ +#define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ + +/* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */ +#define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ + +/* MP1_CPU0_L1_PDN (0x10006000+0x260) */ +#define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ + +/* MP1_CPU1_L1_PDN (0x10006000+0x264) */ +#define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ + +/* MP1_CPU2_L1_PDN (0x10006000+0x268) */ +#define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ + +/* MP1_CPU3_L1_PDN (0x10006000+0x26C) */ +#define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ + +/* CPU_EXT_BUCK_ISO (0x10006000+0x290) */ +#define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ +#define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ + +/* DUMMY1_PWR_CON (0x10006000+0x2B0) */ +#define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */ +#define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ + +/* BYPASS_SPMC (0x10006000+0x2B4) */ +#define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */ + +/* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */ +#define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */ +#define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */ + +/* ARMPLL_CLK_CON (0x10006000+0x2BC) */ +#define MUXSEL_SC_CCIPLL_LSB (1U << 0) /* 1b */ +#define MUXSEL_SC_ARMPLL1_LSB (1U << 1) /* 1b */ +#define MUXSEL_SC_ARMPLL2_LSB (1U << 2) /* 1b */ +#define REG_SC_ARM_CLK_OFF_LSB (1U << 8) /* 4b */ +#define REG_SC_ARMPLL_OFF_LSB (1U << 12) /* 4b */ +#define REG_SC_ARMPLLOUT_OFF_LSB (1U << 16) /* 4b */ +#define REG_SC_FHC_PAUSE_LSB (1U << 20) /* 4b */ +#define REG_SC_ARMPLL_S_OFF_LSB (1U << 24) /* 4b */ + +/* SPMC_IN_RET (0x10006000+0x2C0) */ +#define SPMC_STATUS_LSB (1U << 0) /* 8b */ + +/* VDE_PWR_CON (0x10006000+0x300) */ +#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VDE_PWR_ON_LSB (1U << 2) /* 1b */ +#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ + +/* VEN_PWR_CON (0x10006000+0x304) */ +#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VEN_PWR_ON_LSB (1U << 2) /* 1b */ +#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ + +/* ISP_PWR_CON (0x10006000+0x308) */ +#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define ISP_PWR_ON_LSB (1U << 2) /* 1b */ +#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ + +/* DIS_PWR_CON (0x10006000+0x30C) */ +#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DIS_PWR_ON_LSB (1U << 2) /* 1b */ +#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ + +/* MJC_PWR_CON (0x10006000+0x310) */ +#define MJC_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MJC_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MJC_PWR_ON_LSB (1U << 2) /* 1b */ +#define MJC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MJC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MJC_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MJC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ + +/* AUDIO_PWR_CON (0x10006000+0x314) */ +#define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define AUD_PWR_ISO_LSB (1U << 1) /* 1b */ +#define AUD_PWR_ON_LSB (1U << 2) /* 1b */ +#define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ + +/* IFR_PWR_CON (0x10006000+0x318) */ +#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ +#define IFR_PWR_ON_LSB (1U << 2) /* 1b */ +#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ + +/* DPY_PWR_CON (0x10006000+0x31C) */ +#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DPY_PWR_ON_LSB (1U << 2) /* 1b */ +#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ + +/* MD1_PWR_CON (0x10006000+0x320) */ +#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MD1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ + +/* MD2_PWR_CON (0x10006000+0x324) */ +#define MD2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MD2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MD2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MD2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MD2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MD2_SRAM_PDN_LSB (1U << 8) /* 1b */ + +/* C2K_PWR_CON (0x10006000+0x328) */ +#define C2K_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define C2K_PWR_ISO_LSB (1U << 1) /* 1b */ +#define C2K_PWR_ON_LSB (1U << 2) /* 1b */ +#define C2K_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define C2K_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ + +/* CONN_PWR_CON (0x10006000+0x32C) */ +#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CONN_PWR_ON_LSB (1U << 2) /* 1b */ +#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ + +/* VCOREPDN_PWR_CON (0x10006000+0x330) */ +#define VCOREPDN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VCOREPDN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VCOREPDN_PWR_ON_LSB (1U << 2) /* 1b */ +#define VCOREPDN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VCOREPDN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ + +/* MFG_ASYNC_PWR_CON (0x10006000+0x334) */ +#define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ + +/* MFG_PWR_CON (0x10006000+0x338) */ +#define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_SRAM_PDN_LSB (1U << 8) /* 6b */ +#define MFG_SRAM_PDN_ACK_LSB (1U << 16) /* 6b */ + +/* MFG_CORE0_PWR_CON (0x10006000+0x33C) */ +#define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_CORE0_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_CORE0_SRAM_PDN_LSB (1U << 5) /* 1b */ +#define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 6) /* 1b */ + +/* MFG_CORE1_PWR_CON (0x10006000+0x340) */ +#define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_CORE1_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_CORE1_SRAM_PDN_LSB (1U << 5) /* 1b */ +#define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 6) /* 1b */ + +/* CAM_PWR_CON (0x10006000+0x344) */ +#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CAM_PWR_ON_LSB (1U << 2) /* 1b */ +#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ + +/* SYSRAM_CON (0x10006000+0x350) */ +#define IFR_SRAMROM_SRAM_PDN_LSB (1U << 0) /* 8b */ +#define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 8) /* 8b */ +#define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 16) /* 8b */ +#define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 24) /* 8b */ + +/* SYSROM_CON (0x10006000+0x354) */ +#define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */ + +/* SCP_SRAM_CON (0x10006000+0x358) */ +#define SCP_SRAM_PDN_LSB (1U << 0) /* 1b */ +#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define SCP_SRAM_ISOINT_B_LSB (1U << 8) /* 1b */ + +/* GCPU_SRAM_CON (0x10006000+0x35C) */ +#define GCPU_SRAM_PDN_LSB (1U << 0) /* 4b */ +#define GCPU_SRAM_CKISO_LSB (1U << 4) /* 4b */ +#define GCPU_SRAM_SLEEP_B_LSB (1U << 8) /* 4b */ +#define GCPU_SRAM_ISOINT_B_LSB (1U << 12) /* 4b */ + +/* MDSYS_INTF_INFRA_PWR_CON (0x10006000+0x360) */ +#define MDSYS_INTF_INFRA_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MDSYS_INTF_INFRA_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MDSYS_INTF_INFRA_PWR_ON_LSB (1U << 2) /* 1b */ +#define MDSYS_INTF_INFRA_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MDSYS_INTF_INFRA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ + +/* MDSYS_INTF_MD1_PWR_CON (0x10006000+0x364) */ +#define MDSYS_INTF_MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MDSYS_INTF_MD1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MDSYS_INTF_MD1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MDSYS_INTF_MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MDSYS_INTF_MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ + +/* MDSYS_INTF_C2K_PWR_CON (0x10006000+0x368) */ +#define MDSYS_INTF_C2K_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MDSYS_INTF_C2K_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MDSYS_INTF_C2K_PWR_ON_LSB (1U << 2) /* 1b */ +#define MDSYS_INTF_C2K_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MDSYS_INTF_C2K_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ + +/* BSI_TOP_SRAM_CON (0x10006000+0x370) */ +#define BSI_TOP_SRAM_PDN_LSB (1U << 0) /* 7b */ +#define BSI_TOP_SRAM_DSLP_LSB (1U << 7) /* 7b */ +#define BSI_TOP_SRAM_SLEEP_B_LSB (1U << 14) /* 7b */ +#define BSI_TOP_SRAM_ISOINT_B_LSB (1U << 21) /* 7b */ +#define BSI_TOP_SRAM_ISO_EN_LSB (1U << 28) /* 2b */ + +/* DVFSP_SRAM_CON (0x10006000+0x374) */ +#define DVFSP_SRAM_PDN_LSB (1U << 0) /* 2b */ +#define DVFSP_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ +#define DVFSP_SRAM_ISOINT_B_LSB (1U << 8) /* 2b */ + +/* MD_EXT_BUCK_ISO (0x10006000+0x390) */ +#define MD_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ + +/* DUMMY2_PWR_CON (0x10006000+0x3B0) */ +#define DUMMY2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DUMMY2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DUMMY2_PWR_ON_LSB (1U << 2) /* 1b */ +#define DUMMY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DUMMY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DUMMY2_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define DUMMY2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ + +/* MD1_OUTPUT_PISO_S_EN_IZ (0x10006000+0x3B4) */ +#define MD1_OUTPUT_PISO_S_EN_IZ_LSB (1U << 0) /* 1b */ + +/* SPM_DVFS_CON (0x10006000+0x400) */ +#define SPM_DVFS_CON_LSB (1U << 0) /* 4b */ +#define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */ + +/* SPM_MDBSI_CON (0x10006000+0x404) */ +#define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */ + +/* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */ +#define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */ + +/* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */ +#define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */ + +/* SPM_BSI_GEN (0x10006000+0x410) */ +#define SPM_BSI_START_LSB (1U << 0) /* 1b */ + +/* SPM_BSI_EN_SR (0x10006000+0x414) */ +#define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */ + +/* SPM_BSI_CLK_SR (0x10006000+0x418) */ +#define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */ + +/* SPM_BSI_D0_SR (0x10006000+0x41C) */ +#define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */ + +/* SPM_BSI_D1_SR (0x10006000+0x420) */ +#define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */ + +/* SPM_BSI_D2_SR (0x10006000+0x424) */ +#define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */ + +/* SPM_AP_SEMA (0x10006000+0x428) */ +#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ + +/* SPM_SPM_SEMA (0x10006000+0x42C) */ +#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ + +/* AP2MD_CROSS_TRIGGER (0x10006000+0x430) */ +#define AP2MD_CROSS_TRIGGER_REQ_LSB (1U << 0) /* 1b */ +#define AP2MD_CROSS_TRIGGER_ACK_LSB (1U << 1) /* 1b */ + +/* AP_MDSRC_REQ (0x10006000+0x434) */ +#define AP_MD1SRC_REQ_LSB (1U << 0) /* 1b */ +#define AP_MD2SRC_REQ_LSB (1U << 1) /* 1b */ +#define AP_MD1SRC_ACK_LSB (1U << 4) /* 1b */ +#define AP_MD2SRC_ACK_LSB (1U << 5) /* 1b */ + +/* SPM2MD_DVFS_CON (0x10006000+0x438) */ +#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 16b */ + +/* MD2SPM_DVFS_CON (0x10006000+0x43C) */ +#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 16b */ + +/* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */ +#define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */ +#define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */ +#define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */ +#define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */ +#define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */ +#define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */ +#define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */ + +/* DPY_LP_CON (0x10006000+0x444) */ +#define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */ + +/* CPU_DVFS_REQ (0x10006000+0x448) */ +#define CPU_DVFS_REQ_LSB (1U << 0) /* 16b */ +#define DVFS_HALT_LSB (1U << 16) /* 1b */ +#define MD_DVFS_ERROR_STATUS_LSB (1U << 17) /* 1b */ + +/* SPM_PLL_CON (0x10006000+0x44C) */ +#define SC_MPLLOUT_OFF_LSB (1U << 0) /* 1b */ +#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ +#define SC_MPLL_OFF_LSB (1U << 4) /* 1b */ +#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ +#define SC_MPLL_S_OFF_LSB (1U << 8) /* 1b */ +#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ +#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ +#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */ + +/* SPM_EMI_BW_MODE (0x10006000+0x450) */ +#define EMI_BW_MODE_LSB (1U << 0) /* 1b */ +#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ + +/* AP2MD_PEER_WAKEUP (0x10006000+0x454) */ +#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ + +/* ULPOSC_CON (0x10006000+0x458) */ +#define ULPOSC_EN_LSB (1U << 0) /* 1b */ +#define ULPOSC_RST_LSB (1U << 1) /* 1b */ +#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ + +/* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */ +#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */ +#define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */ +#define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */ +#define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */ +#define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */ +#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */ +#define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */ +#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */ +#define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */ +#define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */ +#define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */ +#define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */ +#define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */ +#define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */ +#define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */ + +/* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */ +#define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */ +#define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */ +#define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */ +#define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */ +#define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */ +#define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */ +#define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */ +#define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */ +#define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */ +#define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */ +#define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */ +#define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */ +#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */ +#define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */ + +/* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */ +#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */ +#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */ +#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */ +#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */ +#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */ +#define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */ +#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */ + +/* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */ +#define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */ +#define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */ +#define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */ +#define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */ +#define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */ +#define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */ +#define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */ +#define SPM2MM_ULTRAREQ_LSB (1U << 8) /* 1b */ +#define SPM2MD_ULTRAREQ_LSB (1U << 9) /* 1b */ +#define SPM2MM_ULTRAACK_D2T_LSB (1U << 30) /* 1b */ +#define SPM2MD_ULTRAACK_D2T_LSB (1U << 31) /* 1b */ + +/* SPM_SEMA_M0 (0x10006000+0x480) */ +#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ + +/* SPM_SEMA_M1 (0x10006000+0x484) */ +#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ + +/* SPM_SEMA_M2 (0x10006000+0x488) */ +#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ + +/* SPM_SEMA_M3 (0x10006000+0x48C) */ +#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ + +/* SPM_SEMA_M4 (0x10006000+0x490) */ +#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ + +/* SPM_SEMA_M5 (0x10006000+0x494) */ +#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ + +/* SPM_SEMA_M6 (0x10006000+0x498) */ +#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ + +/* SPM_SEMA_M7 (0x10006000+0x49C) */ +#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ + +/* SPM_SEMA_M8 (0x10006000+0x4A0) */ +#define SPM_SEMA_M8_LSB (1U << 0) /* 8b */ + +/* SPM_SEMA_M9 (0x10006000+0x4A4) */ +#define SPM_SEMA_M9_LSB (1U << 0) /* 8b */ + +/* SRAM_DREQ_ACK (0x10006000+0x4AC) */ +#define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */ + +/* SRAM_DREQ_CON (0x10006000+0x4B0) */ +#define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */ + +/* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */ +#define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */ + +/* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */ +#define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */ + +/* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */ +#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ + +/* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */ +#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ + +/* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */ +#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ + +/* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */ +#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ + +/* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */ +#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ + +/* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */ +#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ + +/* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */ +#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ + +/* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */ +#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ + +/* MP0_CPU0_WFI_EN (0x10006000+0x530) */ +#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ + +/* MP0_CPU1_WFI_EN (0x10006000+0x534) */ +#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ + +/* MP0_CPU2_WFI_EN (0x10006000+0x538) */ +#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ + +/* MP0_CPU3_WFI_EN (0x10006000+0x53C) */ +#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ + +/* MP1_CPU0_WFI_EN (0x10006000+0x540) */ +#define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ + +/* MP1_CPU1_WFI_EN (0x10006000+0x544) */ +#define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ + +/* MP1_CPU2_WFI_EN (0x10006000+0x548) */ +#define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ + +/* MP1_CPU3_WFI_EN (0x10006000+0x54C) */ +#define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ + +/* CPU_PTPOD2_CON (0x10006000+0x560) */ +#define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */ +#define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */ +#define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */ +#define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */ +#define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */ +#define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */ + +/* ROOT_CPUTOP_ADDR (0x10006000+0x570) */ +#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ + +/* ROOT_CORE_ADDR (0x10006000+0x574) */ +#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ + +/* CPU_SPARE_CON (0x10006000+0x580) */ +#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ + +/* CPU_SPARE_CON_SET (0x10006000+0x584) */ +#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ + +/* CPU_SPARE_CON_CLR (0x10006000+0x588) */ +#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ + +/* SPM_SW_FLAG (0x10006000+0x600) */ +#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ + +/* SPM_SW_DEBUG (0x10006000+0x604) */ +#define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_0 (0x10006000+0x608) */ +#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_1 (0x10006000+0x60C) */ +#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_2 (0x10006000+0x610) */ +#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_3 (0x10006000+0x614) */ +#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_4 (0x10006000+0x618) */ +#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_5 (0x10006000+0x61C) */ +#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ + +/* SPM_RSV_CON (0x10006000+0x620) */ +#define SPM_RSV_CON_LSB (1U << 0) /* 16b */ + +/* SPM_RSV_STA (0x10006000+0x624) */ +#define SPM_RSV_STA_LSB (1U << 0) /* 16b */ + +/* SPM_PASR_DPD_0 (0x10006000+0x630) */ +#define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */ + +/* SPM_PASR_DPD_1 (0x10006000+0x634) */ +#define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */ + +/* SPM_PASR_DPD_2 (0x10006000+0x638) */ +#define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */ + +/* SPM_PASR_DPD_3 (0x10006000+0x63C) */ +#define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */ + +/* SPM_SPARE_CON (0x10006000+0x640) */ +#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ + +/* SPM_SPARE_CON_SET (0x10006000+0x644) */ +#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ + +/* SPM_SPARE_CON_CLR (0x10006000+0x648) */ +#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_6 (0x10006000+0x64C) */ +#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_7 (0x10006000+0x650) */ +#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_8 (0x10006000+0x654) */ +#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_9 (0x10006000+0x658) */ +#define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_10 (0x10006000+0x65C) */ +#define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_11 (0x10006000+0x660) */ +#define SPM_SW_RSV_11_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_12 (0x10006000+0x664) */ +#define SPM_SW_RSV_12_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_13 (0x10006000+0x668) */ +#define SPM_SW_RSV_13_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_14 (0x10006000+0x66C) */ +#define SPM_SW_RSV_14_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_15 (0x10006000+0x670) */ +#define SPM_SW_RSV_15_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_16 (0x10006000+0x674) */ +#define SPM_SW_RSV_16_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_17 (0x10006000+0x678) */ +#define SPM_SW_RSV_17_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_18 (0x10006000+0x67C) */ +#define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */ + +/* SPM_SW_RSV_19 (0x10006000+0x680) */ +#define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */ + +/* SW_CRTL_EVENT (0x10006000+0x690) */ +#define SW_CRTL_EVENT_ON_LSB (1U << 0) /* 1b */ + +#define SPM_PROJECT_CODE 0xb16 + +#define SPM_REGWR_EN (1U << 0) +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define SPM_CPU_PDN_DIS (1U << 0) +#define SPM_INFRA_PDN_DIS (1U << 1) +#define SPM_DDRPHY_PDN_DIS (1U << 2) +#define SPM_DUALVCORE_PDN_DIS (1U << 3) +#define SPM_PASR_DIS (1U << 4) +#define SPM_DPD_DIS (1U << 5) +#define SPM_SODI_DIS (1U << 6) +#define SPM_MEMPLL_RESET (1U << 7) +#define SPM_MAINPLL_PDN_DIS (1U << 8) +#define SPM_CPU_DVS_DIS (1U << 9) +#define SPM_CPU_DORMANT (1U << 10) +#define SPM_EXT_VSEL_GPIO103 (1U << 11) +#define SPM_DDR_HIGH_SPEED (1U << 12) +#define SPM_OPT (1U << 13) + +#define POWER_ON_VAL1_DEF 0x15820 +#define PCM_FSM_STA_DEF 0x48490 +#define PCM_END_FSM_STA_DEF 0x08490 +#define PCM_END_FSM_STA_MASK 0x3fff0 +#define PCM_HANDSHAKE_SEND1 0xbeefbeef + +#define PCM_WDT_TIMEOUT (30 * 32768) +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +#define CON0_PCM_KICK (1U << 0) +#define CON0_IM_KICK (1U << 1) +#define CON0_IM_SLEEP_DVS (1U << 3) +#define CON0_PCM_SW_RESET (1U << 15) +#define CON0_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define CON1_IM_SLAVE (1U << 0) +#define CON1_MIF_APBEN (1U << 3) +#define CON1_PCM_TIMER_EN (1U << 5) +#define CON1_IM_NONRP_EN (1U << 6) +#define CON1_PCM_WDT_EN (1U << 8) +#define CON1_PCM_WDT_WAKE_MODE (1U << 9) +#define CON1_SPM_SRAM_SLP_B (1U << 10) +#define CON1_SPM_SRAM_ISO_B (1U << 11) +#define CON1_EVENT_LOCK_EN (1U << 12) +#define CON1_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R2 (1U << 18) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +#define CC_SYSCLK0_EN_0 (1U << 0) +#define CC_SYSCLK0_EN_1 (1U << 1) +#define CC_SYSCLK1_EN_0 (1U << 2) +#define CC_SYSCLK1_EN_1 (1U << 3) +#define CC_SYSSETTLE_SEL (1U << 4) +#define CC_LOCK_INFRA_DCM (1U << 5) +#define CC_SRCLKENA_MASK_0 (1U << 6) +#define CC_CXO32K_RM_EN_MD1 (1U << 9) +#define CC_CXO32K_RM_EN_MD2 (1U << 10) +#define CC_CLKSQ1_SEL (1U << 12) +#define CC_DISABLE_DORM_PWR (1U << 14) +#define CC_MD32_DCM_EN (1U << 18) + +#define WFI_OP_AND 1 +#define WFI_OP_OR 0 + +#define WAKE_MISC_PCM_TIMER (1U << 19) +#define WAKE_MISC_CPU_WAKE (1U << 20) + +/* define WAKE_SRC_XXX */ +#define WAKE_SRC_SPM_MERGE (1 << 0) +#define WAKE_SRC_KP (1 << 2) +#define WAKE_SRC_WDT (1 << 3) +#define WAKE_SRC_GPT (1 << 4) +#define WAKE_SRC_EINT (1 << 6) +#define WAKE_SRC_LOW_BAT (1 << 9) +#define WAKE_SRC_MD32 (1 << 10) +#define WAKE_SRC_USB_CD (1 << 14) +#define WAKE_SRC_USB_PDN (1 << 15) +#define WAKE_SRC_AFE (1 << 20) +#define WAKE_SRC_THERM (1 << 21) +#define WAKE_SRC_SYSPWREQ (1 << 24) +#define WAKE_SRC_SEJ (1 << 27) +#define WAKE_SRC_ALL_MD32 (1 << 28) +#define WAKE_SRC_CPU_IRQ (1 << 29) + +#define spm_read(addr) mmio_read_32(addr) +#define spm_write(addr, val) mmio_write_32(addr, val) + +#endif /* SPM_H */ diff --git a/plat/mediatek/mt8183/plat_dcm.c b/plat/mediatek/mt8183/plat_dcm.c new file mode 100644 index 000000000..8ee77f108 --- /dev/null +++ b/plat/mediatek/mt8183/plat_dcm.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PWR_STATUS (SPM_BASE + 0x180) + +uint64_t plat_dcm_mcsi_a_addr; +uint32_t plat_dcm_mcsi_a_val; +static int plat_dcm_init_type; +static unsigned int dcm_big_core_cnt; +int plat_dcm_initiated; + +#define PWR_STA_BIG_MP_MASK (0x1 << 15) + +DEFINE_BAKERY_LOCK(dcm_lock); + +void dcm_lock_init(void) +{ + bakery_lock_init(&dcm_lock); +} + +void dcm_lock_get(void) +{ + bakery_lock_get(&dcm_lock); +} + +void dcm_lock_release(void) +{ + bakery_lock_release(&dcm_lock); +} + +void plat_dcm_mcsi_a_backup(void) +{ +} + +void plat_dcm_mcsi_a_restore(void) +{ +} + +void plat_dcm_rgu_enable(void) +{ +} + +void plat_dcm_big_core_sync(short on) +{ + /* Check if Big cluster power is existed */ + if (!(mmio_read_32(PWR_STATUS) & PWR_STA_BIG_MP_MASK)) + return; + + if (on) { + mmio_write_32(MP2_SYNC_DCM, + (mmio_read_32(MP2_SYNC_DCM) & ~MP2_SYNC_DCM_MASK) + | MP2_SYNC_DCM_ON); + dcm_big_core_cnt++; + } else + mmio_write_32(MP2_SYNC_DCM, + (mmio_read_32(MP2_SYNC_DCM) & ~MP2_SYNC_DCM_MASK) + | MP2_SYNC_DCM_OFF); +} + +void plat_dcm_restore_cluster_on(unsigned long mpidr) +{ + unsigned long cluster_id = + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; + + switch (cluster_id) { + case 0x1: + dcm_lock_get(); + if (plat_dcm_init_type & BIG_CORE_DCM_TYPE) + plat_dcm_big_core_sync(1); + else + plat_dcm_big_core_sync(0); + dcm_lock_release(); + break; + default: + break; + } +} + +void plat_dcm_msg_handler(uint64_t x1) +{ + plat_dcm_init_type = x1 & ALL_DCM_TYPE; +} + +unsigned long plat_dcm_get_enabled_cnt(uint64_t type) +{ + switch (type) { + case BIG_CORE_DCM_TYPE: + return dcm_big_core_cnt; + default: + return 0; + } +} + +void plat_dcm_init(void) +{ + dcm_lock_init(); +} diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c index dd54d7040..fa24e2e00 100644 --- a/plat/mediatek/mt8183/plat_pm.c +++ b/plat/mediatek/mt8183/plat_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,21 +15,114 @@ /* mediatek platform specific headers */ #include #include +#include #include +#include #include +#include +#include #include +#define MTK_LOCAL_STATE_OFF 2 + +static uintptr_t secure_entrypoint; + +static void mp1_L2_desel_config(void) +{ + mmio_write_64(MCUCFG_BASE + 0x2200, 0x2092c820); + + dsb(); +} + +static int plat_mtk_power_domain_on(unsigned long mpidr) +{ + int cpu = MPIDR_AFFLVL0_VAL(mpidr); + int cluster = MPIDR_AFFLVL1_VAL(mpidr); + + INFO("%s():%d: mpidr: %lx, c.c: %d.%d\n", + __func__, __LINE__, mpidr, cluster, cpu); + + /* power on cluster */ + if (!spm_get_cluster_powerstate(cluster)) { + spm_poweron_cluster(cluster); + if (cluster == 1) { + l2c_parity_check_setup(); + circular_buffer_setup(); + mp1_L2_desel_config(); + mt_gic_sync_dcm_disable(); + } + } + + /* init cpu reset arch as AARCH64 */ + mcucfg_init_archstate(cluster, cpu, 1); + mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); + + spm_poweron_cpu(cluster, cpu); + + return PSCI_E_SUCCESS; +} + +static void plat_mtk_power_domain_off(const psci_power_state_t *state) +{ + uint64_t mpidr = read_mpidr(); + int cpu = MPIDR_AFFLVL0_VAL(mpidr); + int cluster = MPIDR_AFFLVL1_VAL(mpidr); + + INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu); + + /* Prevent interrupts from spuriously waking up this cpu */ + mt_gic_cpuif_disable(); + + spm_enable_cpu_auto_off(cluster, cpu); + + if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) { + if (cluster == 1) + mt_gic_sync_dcm_enable(); + + plat_mtk_cci_disable(); + spm_enable_cluster_auto_off(cluster); + } + + spm_set_cpu_power_off(cluster, cpu); +} + +static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state) +{ + uint64_t mpidr = read_mpidr(); + int cpu = MPIDR_AFFLVL0_VAL(mpidr); + int cluster = MPIDR_AFFLVL1_VAL(mpidr); + + INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu); + + assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF); + + if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) { + enable_scu(mpidr); + + /* Enable coherency if this cluster was off */ + plat_mtk_cci_enable(); + /* Enable big core dcm if this cluster was on */ + plat_dcm_restore_cluster_on(mpidr); + /* Enable rgu dcm if this cluster was off */ + plat_dcm_rgu_enable(); + } + + spm_disable_cpu_auto_off(cluster, cpu); + + /* Enable the gic cpu interface */ + mt_gic_pcpu_init(); + mt_gic_cpuif_enable(); +} + /******************************************************************************* * MTK_platform handler called when an affinity instance is about to be turned * on. The level and mpidr determine the affinity instance. ******************************************************************************/ -static uintptr_t secure_entrypoint; - static const plat_psci_ops_t plat_plat_pm_ops = { .cpu_standby = NULL, - .pwr_domain_on = NULL, - .pwr_domain_on_finish = NULL, - .pwr_domain_off = NULL, + .pwr_domain_on = plat_mtk_power_domain_on, + .pwr_domain_on_finish = plat_mtk_power_domain_on_finish, + .pwr_domain_off = plat_mtk_power_domain_off, .pwr_domain_suspend = NULL, .pwr_domain_suspend_finish = NULL, .system_off = NULL, diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index f0a598a38..ae466b0f0 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2019, MediaTek Inc. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -9,6 +9,7 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/drivers/ \ + -I${MTK_PLAT_SOC}/drivers/spmc/ \ -I${MTK_PLAT_SOC}/include/ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \ @@ -35,9 +36,11 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ ${MTK_PLAT_SOC}/aarch64/platform_common.c \ ${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c \ + ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \ ${MTK_PLAT_SOC}/plat_pm.c \ ${MTK_PLAT_SOC}/plat_topology.c \ ${MTK_PLAT_SOC}/plat_mt_gic.c \ + ${MTK_PLAT_SOC}/plat_dcm.c \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ ${MTK_PLAT_SOC}/plat_debug.c \ ${MTK_PLAT_SOC}/scu.c -- cgit v1.2.3 From e977b4db2a96f3587f1eb1b82efa90d80def4605 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Thu, 2 May 2019 20:02:05 +0800 Subject: mediatek: mt8183: support system off - Add PMIC driver - Add RTC drvier - Refactor PMIC and RTC to mediatek/common - Implement system off handler Change-Id: If76497646ace1b78bc9a5fa0110b652fe512281a Signed-off-by: kenny liang --- .../common/drivers/pmic_wrap/pmic_wrap_init.c | 165 +++++++++++++++++++++ plat/mediatek/common/drivers/rtc/rtc_common.c | 64 ++++++++ plat/mediatek/mt8183/drivers/pmic/pmic.c | 24 +++ plat/mediatek/mt8183/drivers/pmic/pmic.h | 24 +++ plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h | 94 ++++++++++++ plat/mediatek/mt8183/drivers/rtc/rtc.c | 133 +++++++++++++++++ plat/mediatek/mt8183/drivers/rtc/rtc.h | 147 ++++++++++++++++++ plat/mediatek/mt8183/plat_pm.c | 20 ++- plat/mediatek/mt8183/platform.mk | 6 + 9 files changed, 676 insertions(+), 1 deletion(-) create mode 100644 plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c create mode 100644 plat/mediatek/common/drivers/rtc/rtc_common.c create mode 100644 plat/mediatek/mt8183/drivers/pmic/pmic.c create mode 100644 plat/mediatek/mt8183/drivers/pmic/pmic.h create mode 100644 plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h create mode 100644 plat/mediatek/mt8183/drivers/rtc/rtc.c create mode 100644 plat/mediatek/mt8183/drivers/rtc/rtc.h diff --git a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c new file mode 100644 index 000000000..e3cfd46a0 --- /dev/null +++ b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +/* pmic wrap module wait_idle and read polling interval (in microseconds) */ +enum { + WAIT_IDLE_POLLING_DELAY_US = 1, + READ_POLLING_DELAY_US = 2 +}; + +static inline uint32_t wait_for_state_idle(uint32_t timeout_us, + void *wacs_register, + void *wacs_vldclr_register, + uint32_t *read_reg) +{ + uint32_t reg_rdata; + uint32_t retry; + + retry = (timeout_us + WAIT_IDLE_POLLING_DELAY_US) / + WAIT_IDLE_POLLING_DELAY_US; + + do { + udelay(WAIT_IDLE_POLLING_DELAY_US); + reg_rdata = mmio_read_32((uintptr_t)wacs_register); + /* if last read command timeout,clear vldclr bit + * read command state machine:FSM_REQ-->wfdle-->WFVLDCLR; + * write:FSM_REQ-->idle + */ + switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & + RDATA_WACS_FSM_MASK)) { + case WACS_FSM_WFVLDCLR: + mmio_write_32((uintptr_t)wacs_vldclr_register, 1); + ERROR("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n"); + break; + case WACS_FSM_WFDLE: + ERROR("WACS_FSM = WACS_FSM_WFDLE\n"); + break; + case WACS_FSM_REQ: + ERROR("WACS_FSM = WACS_FSM_REQ\n"); + break; + case WACS_FSM_IDLE: + goto done; + default: + break; + } + + retry--; + } while (retry); + +done: + if (!retry) /* timeout */ + return E_PWR_WAIT_IDLE_TIMEOUT; + + if (read_reg) + *read_reg = reg_rdata; + return 0; +} + +static inline uint32_t wait_for_state_ready(uint32_t timeout_us, + void *wacs_register, + uint32_t *read_reg) +{ + uint32_t reg_rdata; + uint32_t retry; + + retry = (timeout_us + READ_POLLING_DELAY_US) / READ_POLLING_DELAY_US; + + do { + udelay(READ_POLLING_DELAY_US); + reg_rdata = mmio_read_32((uintptr_t)wacs_register); + + if (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) + == WACS_FSM_WFVLDCLR) + break; + + retry--; + } while (retry); + + if (!retry) { /* timeout */ + ERROR("timeout when waiting for idle\n"); + return E_PWR_WAIT_IDLE_TIMEOUT_READ; + } + + if (read_reg) + *read_reg = reg_rdata; + return 0; +} + +static int32_t pwrap_wacs2(uint32_t write, + uint32_t adr, + uint32_t wdata, + uint32_t *rdata, + uint32_t init_check) +{ + uint32_t reg_rdata = 0; + uint32_t wacs_write = 0; + uint32_t wacs_adr = 0; + uint32_t wacs_cmd = 0; + uint32_t return_value = 0; + + if (init_check) { + reg_rdata = mmio_read_32((uintptr_t)&mtk_pwrap->wacs2_rdata); + /* Prevent someone to used pwrap before pwrap init */ + if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & + RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { + ERROR("initialization isn't finished\n"); + return E_PWR_NOT_INIT_DONE; + } + } + reg_rdata = 0; + /* Check IDLE in advance */ + return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE, + &mtk_pwrap->wacs2_rdata, + &mtk_pwrap->wacs2_vldclr, + 0); + if (return_value != 0) { + ERROR("wait_for_fsm_idle fail,return_value=%d\n", return_value); + goto FAIL; + } + wacs_write = write << 31; + wacs_adr = (adr >> 1) << 16; + wacs_cmd = wacs_write | wacs_adr | wdata; + + mmio_write_32((uintptr_t)&mtk_pwrap->wacs2_cmd, wacs_cmd); + if (write == 0) { + if (rdata == NULL) { + ERROR("rdata is a NULL pointer\n"); + return_value = E_PWR_INVALID_ARG; + goto FAIL; + } + return_value = wait_for_state_ready(TIMEOUT_READ, + &mtk_pwrap->wacs2_rdata, + ®_rdata); + if (return_value != 0) { + ERROR("wait_for_fsm_vldclr fail,return_value=%d\n", + return_value); + goto FAIL; + } + *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT) + & RDATA_WACS_RDATA_MASK); + mmio_write_32((uintptr_t)&mtk_pwrap->wacs2_vldclr, 1); + } +FAIL: + return return_value; +} + +/* external API for pmic_wrap user */ + +int32_t pwrap_read(uint32_t adr, uint32_t *rdata) +{ + return pwrap_wacs2(0, adr, 0, rdata, 1); +} + +int32_t pwrap_write(uint32_t adr, uint32_t wdata) +{ + return pwrap_wacs2(1, adr, wdata, 0, 1); +} diff --git a/plat/mediatek/common/drivers/rtc/rtc_common.c b/plat/mediatek/common/drivers/rtc/rtc_common.c new file mode 100644 index 000000000..cad12a03b --- /dev/null +++ b/plat/mediatek/common/drivers/rtc/rtc_common.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include + +/* RTC busy status polling interval and retry count */ +enum { + RTC_WRTGR_POLLING_DELAY_MS = 10, + RTC_WRTGR_POLLING_CNT = 100 +}; + +uint16_t RTC_Read(uint32_t addr) +{ + uint32_t rdata = 0; + + pwrap_read((uint32_t)addr, &rdata); + return (uint16_t)rdata; +} + +void RTC_Write(uint32_t addr, uint16_t data) +{ + pwrap_write((uint32_t)addr, (uint32_t)data); +} + +int32_t rtc_busy_wait(void) +{ + uint64_t retry = RTC_WRTGR_POLLING_CNT; + + do { + mdelay(RTC_WRTGR_POLLING_DELAY_MS); + if (!(RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY)) + return 1; + retry--; + } while (retry); + + ERROR("[RTC] rtc cbusy time out!\n"); + return 0; +} + +int32_t RTC_Write_Trigger(void) +{ + RTC_Write(RTC_WRTGR, 1); + return rtc_busy_wait(); +} + +int32_t Writeif_unlock(void) +{ + RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1); + if (!RTC_Write_Trigger()) + return 0; + RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2); + if (!RTC_Write_Trigger()) + return 0; + + return 1; +} + diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic.c b/plat/mediatek/mt8183/drivers/pmic/pmic.c new file mode 100644 index 000000000..818c1493a --- /dev/null +++ b/plat/mediatek/mt8183/drivers/pmic/pmic.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +void wk_pmic_enable_sdn_delay(void) +{ + uint32_t con; + + pwrap_write(PMIC_TMA_KEY, 0x9CA7); + pwrap_read(PMIC_PSEQ_ELR11, &con); + con &= ~PMIC_RG_SDN_DLY_ENB; + pwrap_write(PMIC_PSEQ_ELR11, con); + pwrap_write(PMIC_TMA_KEY, 0); +} + +void pmic_power_off(void) +{ + pwrap_write(PMIC_PWRHOLD, 0x0); +} diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic.h b/plat/mediatek/mt8183/drivers/pmic/pmic.h new file mode 100644 index 000000000..d62c6daf1 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/pmic/pmic.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMIC_H +#define PMIC_H + +enum { + PMIC_TMA_KEY = 0x03a8, + PMIC_PWRHOLD = 0x0a08, + PMIC_PSEQ_ELR11 = 0x0a62 +}; + +enum { + PMIC_RG_SDN_DLY_ENB = 1U << 10 +}; + +/* external API */ +void wk_pmic_enable_sdn_delay(void); +void pmic_power_off(void); + +#endif /* PMIC_H */ diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h new file mode 100644 index 000000000..679c5e4c3 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMIC_WRAP_INIT_H +#define PMIC_WRAP_INIT_H + +#include +#include + +/* external API */ +int32_t pwrap_read(uint32_t adr, uint32_t *rdata); +int32_t pwrap_write(uint32_t adr, uint32_t wdata); + +static struct mt8183_pmic_wrap_regs *const mtk_pwrap = + (void *)PMIC_WRAP_BASE; + +/* timeout setting */ +enum { + TIMEOUT_READ = 255, /* us */ + TIMEOUT_WAIT_IDLE = 255 /* us */ +}; + +/* PMIC_WRAP registers */ +struct mt8183_pmic_wrap_regs { + uint32_t reserved[776]; + uint32_t wacs2_cmd; + uint32_t wacs2_rdata; + uint32_t wacs2_vldclr; + uint32_t reserved1[4]; +}; + +enum { + RDATA_WACS_RDATA_SHIFT = 0, + RDATA_WACS_FSM_SHIFT = 16, + RDATA_WACS_REQ_SHIFT = 19, + RDATA_SYNC_IDLE_SHIFT, + RDATA_INIT_DONE_SHIFT, + RDATA_SYS_IDLE_SHIFT, +}; + +enum { + RDATA_WACS_RDATA_MASK = 0xffff, + RDATA_WACS_FSM_MASK = 0x7, + RDATA_WACS_REQ_MASK = 0x1, + RDATA_SYNC_IDLE_MASK = 0x1, + RDATA_INIT_DONE_MASK = 0x1, + RDATA_SYS_IDLE_MASK = 0x1, +}; + +/* WACS_FSM */ +enum { + WACS_FSM_IDLE = 0x00, + WACS_FSM_REQ = 0x02, + WACS_FSM_WFDLE = 0x04, + WACS_FSM_WFVLDCLR = 0x06, + WACS_INIT_DONE = 0x01, + WACS_SYNC_IDLE = 0x01, + WACS_SYNC_BUSY = 0x00 +}; + +/* error information flag */ +enum { + E_PWR_INVALID_ARG = 1, + E_PWR_INVALID_RW = 2, + E_PWR_INVALID_ADDR = 3, + E_PWR_INVALID_WDAT = 4, + E_PWR_INVALID_OP_MANUAL = 5, + E_PWR_NOT_IDLE_STATE = 6, + E_PWR_NOT_INIT_DONE = 7, + E_PWR_NOT_INIT_DONE_READ = 8, + E_PWR_WAIT_IDLE_TIMEOUT = 9, + E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, + E_PWR_INIT_SIDLY_FAIL = 11, + E_PWR_RESET_TIMEOUT = 12, + E_PWR_TIMEOUT = 13, + E_PWR_INIT_RESET_SPI = 20, + E_PWR_INIT_SIDLY = 21, + E_PWR_INIT_REG_CLOCK = 22, + E_PWR_INIT_ENABLE_PMIC = 23, + E_PWR_INIT_DIO = 24, + E_PWR_INIT_CIPHER = 25, + E_PWR_INIT_WRITE_TEST = 26, + E_PWR_INIT_ENABLE_CRC = 27, + E_PWR_INIT_ENABLE_DEWRAP = 28, + E_PWR_INIT_ENABLE_EVENT = 29, + E_PWR_READ_TEST_FAIL = 30, + E_PWR_WRITE_TEST_FAIL = 31, + E_PWR_SWITCH_DIO = 32 +}; + +#endif /* PMIC_WRAP_INIT_H */ diff --git a/plat/mediatek/mt8183/drivers/rtc/rtc.c b/plat/mediatek/mt8183/drivers/rtc/rtc.c new file mode 100644 index 000000000..a821c1bc8 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/rtc/rtc.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +static void RTC_Config_Interface(uint32_t addr, uint16_t data, + uint16_t MASK, uint16_t SHIFT) +{ + uint16_t pmic_reg = 0; + + pmic_reg = RTC_Read(addr); + + pmic_reg &= ~(MASK << SHIFT); + pmic_reg |= (data << SHIFT); + + RTC_Write(addr, pmic_reg); +} + +static void rtc_disable_2sec_reboot(void) +{ + uint16_t reboot; + + reboot = (RTC_Read(RTC_AL_SEC) & ~RTC_BBPU_2SEC_EN) & + ~RTC_BBPU_AUTO_PDN_SEL; + RTC_Write(RTC_AL_SEC, reboot); + RTC_Write_Trigger(); +} + +static void rtc_xosc_write(uint16_t val, bool reload) +{ + uint16_t bbpu; + + RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1); + rtc_busy_wait(); + RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2); + rtc_busy_wait(); + + RTC_Write(RTC_OSC32CON, val); + rtc_busy_wait(); + + if (reload) { + bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD; + RTC_Write(RTC_BBPU, bbpu); + RTC_Write_Trigger(); + } +} + +static void rtc_enable_k_eosc(void) +{ + uint16_t osc32; + uint16_t rtc_eosc_cali_td = 8; /* eosc cali period time */ + + /* Truning on eosc cali mode clock */ + RTC_Config_Interface(PMIC_RG_TOP_CON, 1, + PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, + PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT); + RTC_Config_Interface(PMIC_RG_TOP_CON, 1, + PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, + PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT); + RTC_Config_Interface(PMIC_RG_SCK_TOP_CKPDN_CON0, 0, + PMIC_RG_RTC_EOSC32_CK_PDN_MASK, + PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT); + + switch (rtc_eosc_cali_td) { + case 1: + RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x3, + PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT); + break; + case 2: + RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x4, + PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT); + break; + case 4: + RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x5, + PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT); + break; + case 16: + RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x7, + PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT); + break; + default: + RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x6, + PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT); + break; + } + /* Switch the DCXO from 32k-less mode to RTC mode, + * otherwise, EOSC cali will fail + */ + /* RTC mode will have only OFF mode and FPM */ + RTC_Config_Interface(PMIC_RG_DCXO_CW02, 0, PMIC_RG_XO_EN32K_MAN_MASK, + PMIC_RG_XO_EN32K_MAN_SHIFT); + RTC_Write(RTC_BBPU, + RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + RTC_Write_Trigger(); + /* Enable K EOSC mode for normal power off and then plug out battery */ + RTC_Write(RTC_AL_YEA, ((RTC_Read(RTC_AL_YEA) | RTC_K_EOSC_RSV_0) + & (~RTC_K_EOSC_RSV_1)) | RTC_K_EOSC_RSV_2); + RTC_Write_Trigger(); + + osc32 = RTC_Read(RTC_OSC32CON); + rtc_xosc_write(osc32 | RTC_EMBCK_SRC_SEL, true); + INFO("[RTC] RTC_enable_k_eosc\n"); +} + +void rtc_power_off_sequence(void) +{ + uint16_t bbpu; + + rtc_disable_2sec_reboot(); + rtc_enable_k_eosc(); + + /* clear alarm */ + bbpu = RTC_BBPU_KEY | RTC_BBPU_CLR | RTC_BBPU_PWREN; + if (Writeif_unlock()) { + RTC_Write(RTC_BBPU, bbpu); + + RTC_Write(RTC_AL_MASK, RTC_AL_MASK_DOW); + RTC_Write_Trigger(); + mdelay(1); + + bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD; + RTC_Write(RTC_BBPU, bbpu); + RTC_Write_Trigger(); + INFO("[RTC] BBPU=0x%x, IRQ_EN=0x%x, AL_MSK=0x%x, AL_SEC=0x%x\n", + RTC_Read(RTC_BBPU), RTC_Read(RTC_IRQ_EN), + RTC_Read(RTC_AL_MASK), RTC_Read(RTC_AL_SEC)); + } +} diff --git a/plat/mediatek/mt8183/drivers/rtc/rtc.h b/plat/mediatek/mt8183/drivers/rtc/rtc.h new file mode 100644 index 000000000..66686b400 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/rtc/rtc.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RTC_H +#define RTC_H + +/* RTC registers */ +enum { + RTC_BBPU = 0x0588, + RTC_IRQ_STA = 0x058A, + RTC_IRQ_EN = 0x058C, + RTC_CII_EN = 0x058E +}; + +enum { + RTC_AL_SEC = 0x05A0, + RTC_AL_MIN = 0x05A2, + RTC_AL_HOU = 0x05A4, + RTC_AL_DOM = 0x05A6, + RTC_AL_DOW = 0x05A8, + RTC_AL_MTH = 0x05AA, + RTC_AL_YEA = 0x05AC, + RTC_AL_MASK = 0x0590 +}; + +enum { + RTC_OSC32CON = 0x05AE, + RTC_CON = 0x05C4, + RTC_WRTGR = 0x05C2 +}; + +enum { + RTC_PDN1 = 0x05B4, + RTC_PDN2 = 0x05B6, + RTC_SPAR0 = 0x05B8, + RTC_SPAR1 = 0x05BA, + RTC_PROT = 0x05BC, + RTC_DIFF = 0x05BE, + RTC_CALI = 0x05C0 +}; + +enum { + RTC_OSC32CON_UNLOCK1 = 0x1A57, + RTC_OSC32CON_UNLOCK2 = 0x2B68 +}; + +enum { + RTC_PROT_UNLOCK1 = 0x586A, + RTC_PROT_UNLOCK2 = 0x9136 +}; + +enum { + RTC_BBPU_PWREN = 1U << 0, + RTC_BBPU_CLR = 1U << 1, + RTC_BBPU_INIT = 1U << 2, + RTC_BBPU_AUTO = 1U << 3, + RTC_BBPU_CLRPKY = 1U << 4, + RTC_BBPU_RELOAD = 1U << 5, + RTC_BBPU_CBUSY = 1U << 6 +}; + +enum { + RTC_AL_MASK_SEC = 1U << 0, + RTC_AL_MASK_MIN = 1U << 1, + RTC_AL_MASK_HOU = 1U << 2, + RTC_AL_MASK_DOM = 1U << 3, + RTC_AL_MASK_DOW = 1U << 4, + RTC_AL_MASK_MTH = 1U << 5, + RTC_AL_MASK_YEA = 1U << 6 +}; + +enum { + RTC_BBPU_AUTO_PDN_SEL = 1U << 6, + RTC_BBPU_2SEC_CK_SEL = 1U << 7, + RTC_BBPU_2SEC_EN = 1U << 8, + RTC_BBPU_2SEC_MODE = 0x3 << 9, + RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11, + RTC_BBPU_2SEC_STAT_STA = 1U << 12 +}; + +enum { + RTC_BBPU_KEY = 0x43 << 8 +}; + +enum { + RTC_EMBCK_SRC_SEL = 1 << 8, + RTC_EMBCK_SEL_MODE = 3 << 6, + RTC_XOSC32_ENB = 1 << 5, + RTC_REG_XOSC32_ENB = 1 << 15 +}; + +enum { + RTC_K_EOSC_RSV_0 = 1 << 8, + RTC_K_EOSC_RSV_1 = 1 << 9, + RTC_K_EOSC_RSV_2 = 1 << 10 +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_TOP_CON = 0x001E, + PMIC_RG_TOP_CKPDN_CON1 = 0x0112, + PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, + PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, + PMIC_RG_TOP_CKSEL_CON0 = 0x0118, + PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A, + PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C +}; + +/* PMIC SCK Register Definition */ +enum { + PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x051A, + PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x051C, + PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x051E, + PMIC_RG_EOSC_CALI_CON0 = 0x540 +}; + +/* PMIC DCXO Register Definition */ +enum { + PMIC_RG_DCXO_CW00 = 0x0788, + PMIC_RG_DCXO_CW02 = 0x0790 +}; + +enum { + PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK = 0x1, + PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT = 1, + PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK = 0x1, + PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT = 3, + PMIC_RG_RTC_EOSC32_CK_PDN_MASK = 0x1, + PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT = 2, + PMIC_RG_EOSC_CALI_TD_MASK = 0x7, + PMIC_RG_EOSC_CALI_TD_SHIFT = 5, + PMIC_RG_XO_EN32K_MAN_MASK = 0x1, + PMIC_RG_XO_EN32K_MAN_SHIFT = 0 +}; + +/* external API */ +uint16_t RTC_Read(uint32_t addr); +void RTC_Write(uint32_t addr, uint16_t data); +int32_t rtc_busy_wait(void); +int32_t RTC_Write_Trigger(void); +int32_t Writeif_unlock(void); +void rtc_power_off_sequence(void); + +#endif /* RTC_H */ diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c index fa24e2e00..e2aa2b9ec 100644 --- a/plat/mediatek/mt8183/plat_pm.c +++ b/plat/mediatek/mt8183/plat_pm.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #define MTK_LOCAL_STATE_OFF 2 @@ -114,6 +116,22 @@ static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state) mt_gic_cpuif_enable(); } +/******************************************************************************* + * MTK handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 plat_mtk_system_off(void) +{ + INFO("MTK System Off\n"); + + rtc_power_off_sequence(); + wk_pmic_enable_sdn_delay(); + pmic_power_off(); + + wfi(); + ERROR("MTK System Off: operation not handled.\n"); + panic(); +} + /******************************************************************************* * MTK_platform handler called when an affinity instance is about to be turned * on. The level and mpidr determine the affinity instance. @@ -125,7 +143,7 @@ static const plat_psci_ops_t plat_plat_pm_ops = { .pwr_domain_off = plat_mtk_power_domain_off, .pwr_domain_suspend = NULL, .pwr_domain_suspend_finish = NULL, - .system_off = NULL, + .system_off = plat_mtk_system_off, .system_reset = NULL, .validate_power_state = NULL, .get_sys_suspend_power_state = NULL, diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index ae466b0f0..f2e15e386 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -10,6 +10,8 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/drivers/ \ -I${MTK_PLAT_SOC}/drivers/spmc/ \ + -I${MTK_PLAT_SOC}/drivers/pmic/ \ + -I${MTK_PLAT_SOC}/drivers/rtc/ \ -I${MTK_PLAT_SOC}/include/ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \ @@ -33,9 +35,13 @@ BL31_SOURCES += common/desc_image_load.c \ lib/cpus/aarch64/cortex_a73.S \ plat/common/plat_gicv3.c \ ${MTK_PLAT}/common/mtk_plat_common.c \ + ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \ + ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ ${MTK_PLAT_SOC}/aarch64/platform_common.c \ ${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c \ + ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ + ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \ ${MTK_PLAT_SOC}/plat_pm.c \ ${MTK_PLAT_SOC}/plat_topology.c \ -- cgit v1.2.3 From 50cd952249fc40461e91b5b388b7f7c79326a49a Mon Sep 17 00:00:00 2001 From: kenny liang Date: Thu, 2 May 2019 20:24:50 +0800 Subject: mediatek: mt8183: add GPIO driver Add GPIO driver. Change-Id: I8c35ce4ea247f3726081b0bbb95f0930c2b82517 Signed-off-by: kenny liang --- plat/mediatek/mt8183/drivers/gpio/mtgpio.c | 439 +++++++++++++++++++++++++ plat/mediatek/mt8183/drivers/gpio/mtgpio.h | 154 +++++++++ plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h | 208 ++++++++++++ plat/mediatek/mt8183/platform.mk | 2 + 4 files changed, 803 insertions(+) create mode 100644 plat/mediatek/mt8183/drivers/gpio/mtgpio.c create mode 100644 plat/mediatek/mt8183/drivers/gpio/mtgpio.h create mode 100644 plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h diff --git a/plat/mediatek/mt8183/drivers/gpio/mtgpio.c b/plat/mediatek/mt8183/drivers/gpio/mtgpio.c new file mode 100644 index 000000000..61aaeefbc --- /dev/null +++ b/plat/mediatek/mt8183/drivers/gpio/mtgpio.c @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/****************************************************************************** + *Macro Definition + ******************************************************************************/ +#define GPIO_MODE_BITS 4 +#define MAX_GPIO_MODE_PER_REG 8 +#define MAX_GPIO_REG_BITS 32 +#define DIR_BASE (GPIO_BASE + 0x000) +#define DOUT_BASE (GPIO_BASE + 0x100) +#define DIN_BASE (GPIO_BASE + 0x200) +#define MODE_BASE (GPIO_BASE + 0x300) +#define SET 0x4 +#define CLR 0x8 +#define PULLEN_ADDR_OFFSET 0x060 +#define PULLSEL_ADDR_OFFSET 0x080 + +void mt_set_gpio_dir_chip(uint32_t pin, int dir) +{ + uint32_t pos, bit; + + assert(pin < MAX_GPIO_PIN); + assert(dir < GPIO_DIR_MAX); + + pos = pin / MAX_GPIO_REG_BITS; + bit = pin % MAX_GPIO_REG_BITS; + + if (dir == GPIO_DIR_IN) + mmio_write_32(DIR_BASE + 0x10 * pos + CLR, 1U << bit); + else + mmio_write_32(DIR_BASE + 0x10 * pos + SET, 1U << bit); +} + +int mt_get_gpio_dir_chip(uint32_t pin) +{ + uint32_t pos, bit; + uint32_t reg; + + assert(pin < MAX_GPIO_PIN); + + pos = pin / MAX_GPIO_REG_BITS; + bit = pin % MAX_GPIO_REG_BITS; + + reg = mmio_read_32(DIR_BASE + 0x10 * pos); + return (((reg & (1U << bit)) != 0) ? GPIO_DIR_OUT : GPIO_DIR_IN); +} + +void mt_set_gpio_out_chip(uint32_t pin, int output) +{ + uint32_t pos, bit; + + assert(pin < MAX_GPIO_PIN); + assert(output < GPIO_OUT_MAX); + + pos = pin / MAX_GPIO_REG_BITS; + bit = pin % MAX_GPIO_REG_BITS; + + if (output == GPIO_OUT_ZERO) + mmio_write_32(DOUT_BASE + 0x10 * pos + CLR, 1U << bit); + else + mmio_write_32(DOUT_BASE + 0x10 * pos + SET, 1U << bit); +} + +int mt_get_gpio_out_chip(uint32_t pin) +{ + uint32_t pos, bit; + uint32_t reg; + + assert(pin < MAX_GPIO_PIN); + + pos = pin / MAX_GPIO_REG_BITS; + bit = pin % MAX_GPIO_REG_BITS; + + reg = mmio_read_32(DOUT_BASE + 0x10 * pos); + return (((reg & (1U << bit)) != 0) ? 1 : 0); +} + +int mt_get_gpio_in_chip(uint32_t pin) +{ + uint32_t pos, bit; + uint32_t reg; + + assert(pin < MAX_GPIO_PIN); + + pos = pin / MAX_GPIO_REG_BITS; + bit = pin % MAX_GPIO_REG_BITS; + + reg = mmio_read_32(DIN_BASE + 0x10 * pos); + return (((reg & (1U << bit)) != 0) ? 1 : 0); +} + +void mt_set_gpio_mode_chip(uint32_t pin, int mode) +{ + uint32_t pos, bit; + uint32_t data; + uint32_t mask; + + assert(pin < MAX_GPIO_PIN); + assert(mode < GPIO_MODE_MAX); + + mask = (1U << GPIO_MODE_BITS) - 1; + + mode = mode & mask; + pos = pin / MAX_GPIO_MODE_PER_REG; + bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS; + + data = mmio_read_32(MODE_BASE + 0x10 * pos); + data &= (~(mask << bit)); + data |= (mode << bit); + mmio_write_32(MODE_BASE + 0x10 * pos, data); +} + +int mt_get_gpio_mode_chip(uint32_t pin) +{ + uint32_t pos, bit; + uint32_t data; + uint32_t mask; + + assert(pin < MAX_GPIO_PIN); + + mask = (1U << GPIO_MODE_BITS) - 1; + + pos = pin / MAX_GPIO_MODE_PER_REG; + bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS; + + data = mmio_read_32(MODE_BASE + 0x10 * pos); + return (data >> bit) & mask; +} + +int32_t gpio_get_pull_iocfg(uint32_t pin) +{ + switch (pin) { + case 0 ... 10: + return IOCFG_5_BASE; + case 11 ... 12: + return IOCFG_0_BASE; + case 13 ... 28: + return IOCFG_1_BASE; + case 43 ... 49: + return IOCFG_2_BASE; + case 50 ... 60: + return IOCFG_3_BASE; + case 61 ... 88: + return IOCFG_4_BASE; + case 89 ... 90: + return IOCFG_5_BASE; + case 95 ... 106: + return IOCFG_5_BASE; + case 107 ... 121: + return IOCFG_6_BASE; + case 134 ... 160: + return IOCFG_0_BASE; + case 161 ... 166: + return IOCFG_1_BASE; + case 167 ... 176: + return IOCFG_3_BASE; + case 177 ... 179: + return IOCFG_5_BASE; + default: + return -1; + } +} + +int32_t gpio_get_pupd_iocfg(uint32_t pin) +{ + const int32_t offset = 0x0c0; + + switch (pin) { + case 29 ... 34: + return IOCFG_1_BASE + offset; + case 35 ... 42: + return IOCFG_2_BASE + offset; + case 91 ... 94: + return IOCFG_5_BASE + offset; + case 122 ... 133: + return IOCFG_7_BASE + offset; + default: + return -1; + } +} + +int gpio_get_pupd_offset(uint32_t pin) +{ + switch (pin) { + case 29 ... 34: + return (pin - 29) * 4 % 32; + case 35 ... 42: + return (pin - 35) * 4 % 32; + case 91 ... 94: + return (pin - 91) * 4 % 32; + case 122 ... 129: + return (pin - 122) * 4 % 32; + case 130 ... 133: + return (pin - 130) * 4 % 32; + default: + return -1; + } +} + +void mt_set_gpio_pull_enable_chip(uint32_t pin, int en) +{ + int pullen_addr = gpio_get_pull_iocfg(pin) + PULLEN_ADDR_OFFSET; + int pupd_addr = gpio_get_pupd_iocfg(pin); + int pupd_offset = gpio_get_pupd_offset(pin); + + assert(pin < MAX_GPIO_PIN); + + assert(!((PULL_offset[pin].offset == (int8_t)-1) && + (pupd_offset == (int8_t)-1))); + + if (en == GPIO_PULL_DISABLE) { + if (PULL_offset[pin].offset == (int8_t)-1) + mmio_clrbits_32(pupd_addr, 3U << pupd_offset); + else + mmio_clrbits_32(pullen_addr, + 1U << PULL_offset[pin].offset); + } else if (en == GPIO_PULL_ENABLE) { + if (PULL_offset[pin].offset == (int8_t)-1) { + /* For PUPD+R0+R1 Type, mt_set_gpio_pull_enable + * does not know + * which one between PU and PD shall be enabled. + * Use R0 to guarantee at one resistor is set when lk + * apply default setting + */ + mmio_setbits_32(pupd_addr, 1U << pupd_offset); + mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 1)); + } else { + /* For PULLEN + PULLSEL Type */ + mmio_setbits_32(pullen_addr, + 1U << PULL_offset[pin].offset); + } + } else if (en == GPIO_PULL_ENABLE_R0) { + assert(!(pupd_offset == (int8_t)-1)); + mmio_setbits_32(pupd_addr, 1U << pupd_offset); + mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 1)); + } else if (en == GPIO_PULL_ENABLE_R1) { + assert(!(pupd_offset == (int8_t)-1)); + + mmio_clrbits_32(pupd_addr, 1U << pupd_offset); + mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 1)); + } else if (en == GPIO_PULL_ENABLE_R0R1) { + assert(!(pupd_offset == (int8_t)-1)); + mmio_setbits_32(pupd_addr, 3U << pupd_offset); + } +} + +int mt_get_gpio_pull_enable_chip(uint32_t pin) +{ + uint32_t reg; + + int pullen_addr = gpio_get_pull_iocfg(pin) + PULLEN_ADDR_OFFSET; + int pupd_addr = gpio_get_pupd_iocfg(pin); + int pupd_offset = gpio_get_pupd_offset(pin); + + assert(pin < MAX_GPIO_PIN); + + assert(!((PULL_offset[pin].offset == (int8_t)-1) && + (pupd_offset == (int8_t)-1))); + + if (PULL_offset[pin].offset == (int8_t)-1) { + reg = mmio_read_32(pupd_addr); + return ((reg & (3U << pupd_offset)) ? 1 : 0); + } else if (pupd_offset == (int8_t)-1) { + reg = mmio_read_32(pullen_addr); + return ((reg & (1U << PULL_offset[pin].offset)) ? 1 : 0); + } + + return -ERINVAL; +} + +void mt_set_gpio_pull_select_chip(uint32_t pin, int sel) +{ + int pullsel_addr = gpio_get_pull_iocfg(pin) + PULLSEL_ADDR_OFFSET; + int pupd_addr = gpio_get_pupd_iocfg(pin); + int pupd_offset = gpio_get_pupd_offset(pin); + + assert(pin < MAX_GPIO_PIN); + + assert(!((PULL_offset[pin].offset == (int8_t) -1) && + (pupd_offset == (int8_t)-1))); + + if (sel == GPIO_PULL_NONE) { + /* Regard No PULL as PULL disable + pull down */ + mt_set_gpio_pull_enable_chip(pin, GPIO_PULL_DISABLE); + if (PULL_offset[pin].offset == (int8_t)-1) + mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 2)); + else + mmio_clrbits_32(pullsel_addr, + 1U << PULL_offset[pin].offset); + } else if (sel == GPIO_PULL_UP) { + mt_set_gpio_pull_enable_chip(pin, GPIO_PULL_ENABLE); + if (PULL_offset[pin].offset == (int8_t)-1) + mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 2)); + else + mmio_setbits_32(pullsel_addr, + 1U << PULL_offset[pin].offset); + } else if (sel == GPIO_PULL_DOWN) { + mt_set_gpio_pull_enable_chip(pin, GPIO_PULL_ENABLE); + if (PULL_offset[pin].offset == -1) + mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 2)); + else + mmio_clrbits_32(pullsel_addr, + 1U << PULL_offset[pin].offset); + } +} + +/* get pull-up or pull-down, regardless of resistor value */ +int mt_get_gpio_pull_select_chip(uint32_t pin) +{ + uint32_t reg; + + int pullen_addr = gpio_get_pull_iocfg(pin) + PULLEN_ADDR_OFFSET; + int pullsel_addr = gpio_get_pull_iocfg(pin) + PULLSEL_ADDR_OFFSET; + int pupd_addr = gpio_get_pupd_iocfg(pin); + int pupd_offset = gpio_get_pupd_offset(pin); + + assert(pin < MAX_GPIO_PIN); + + assert(!((PULL_offset[pin].offset == (int8_t)-1) && + (pupd_offset == (int8_t)-1))); + + if (PULL_offset[pin].offset == (int8_t)-1) { + reg = mmio_read_32(pupd_addr); + if (reg & (3U << pupd_offset)) { + reg = mmio_read_32(pupd_addr); + /* Reg value: 0 for PU, 1 for PD --> + * reverse return value */ + return ((reg & (1U << (pupd_offset + 2))) ? + GPIO_PULL_DOWN : GPIO_PULL_UP); + } else { + return GPIO_PULL_NONE; + } + } else if (pupd_offset == (int8_t)-1) { + reg = mmio_read_32(pullen_addr); + if ((reg & (1U << PULL_offset[pin].offset))) { + reg = mmio_read_32(pullsel_addr); + return ((reg & (1U << PULL_offset[pin].offset)) ? + GPIO_PULL_UP : GPIO_PULL_DOWN); + } else { + return GPIO_PULL_NONE; + } + } + + return -ERINVAL; +} + +void mt_set_gpio_dir(int gpio, int direction) +{ + mt_set_gpio_dir_chip((uint32_t)gpio, direction); +} + +int mt_get_gpio_dir(int gpio) +{ + uint32_t pin; + + pin = (uint32_t)gpio; + return mt_get_gpio_dir_chip(pin); +} + +void mt_set_gpio_pull(int gpio, int pull) +{ + uint32_t pin; + + pin = (uint32_t)gpio; + mt_set_gpio_pull_select_chip(pin, pull); +} + +int mt_get_gpio_pull(int gpio) +{ + uint32_t pin; + + pin = (uint32_t)gpio; + return mt_get_gpio_pull_select_chip(pin); +} + +void mt_set_gpio_out(int gpio, int value) +{ + uint32_t pin; + + pin = (uint32_t)gpio; + mt_set_gpio_out_chip(pin, value); +} + +int mt_get_gpio_out(int gpio) +{ + uint32_t pin; + + pin = (uint32_t)gpio; + return mt_get_gpio_out_chip(pin); +} + +int mt_get_gpio_in(int gpio) +{ + uint32_t pin; + + pin = (uint32_t)gpio; + return mt_get_gpio_in_chip(pin); +} + +void mt_set_gpio_mode(int gpio, int mode) +{ + uint32_t pin; + + pin = (uint32_t)gpio; + mt_set_gpio_mode_chip(pin, mode); +} + +int mt_get_gpio_mode(int gpio) +{ + uint32_t pin; + + pin = (uint32_t)gpio; + return mt_get_gpio_mode_chip(pin); +} + +const gpio_ops_t mtgpio_ops = { + .get_direction = mt_get_gpio_dir, + .set_direction = mt_set_gpio_dir, + .get_value = mt_get_gpio_in, + .set_value = mt_set_gpio_out, + .set_pull = mt_set_gpio_pull, + .get_pull = mt_get_gpio_pull, +}; diff --git a/plat/mediatek/mt8183/drivers/gpio/mtgpio.h b/plat/mediatek/mt8183/drivers/gpio/mtgpio.h new file mode 100644 index 000000000..9461c54bc --- /dev/null +++ b/plat/mediatek/mt8183/drivers/gpio/mtgpio.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_GPIO_H +#define MT_GPIO_H + +#include +#include + +/* Error Code No. */ +#define RSUCCESS 0 +#define ERACCESS 1 +#define ERINVAL 2 +#define ERWRAPPER 3 +#define MAX_GPIO_PIN MT_GPIO_BASE_MAX + +/* Enumeration for GPIO pin */ +typedef enum GPIO_PIN { + GPIO_UNSUPPORTED = -1, + + GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, + GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15, + GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23, + GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31, + GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39, + GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47, + GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55, + GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63, + GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71, + GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79, + GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87, + GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95, + GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103, + GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111, + GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119, + GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127, + GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, GPIO135, + GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142, GPIO143, + GPIO144, GPIO145, GPIO146, GPIO147, GPIO148, GPIO149, GPIO150, GPIO151, + GPIO152, GPIO153, GPIO154, GPIO155, GPIO156, GPIO157, GPIO158, GPIO159, + GPIO160, GPIO161, GPIO162, GPIO163, GPIO164, GPIO165, GPIO166, GPIO167, + GPIO168, GPIO169, GPIO170, GPIO171, GPIO172, GPIO173, GPIO174, GPIO175, + GPIO176, GPIO177, GPIO178, GPIO179, + MT_GPIO_BASE_MAX +} GPIO_PIN; + +/* GPIO MODE CONTROL VALUE*/ +typedef enum { + GPIO_MODE_UNSUPPORTED = -1, + GPIO_MODE_GPIO = 0, + GPIO_MODE_00 = 0, + GPIO_MODE_01, + GPIO_MODE_02, + GPIO_MODE_03, + GPIO_MODE_04, + GPIO_MODE_05, + GPIO_MODE_06, + GPIO_MODE_07, + + GPIO_MODE_MAX, + GPIO_MODE_DEFAULT = GPIO_MODE_00, +} GPIO_MODE; + +/* GPIO DIRECTION */ +typedef enum { + GPIO_DIR_UNSUPPORTED = -1, + GPIO_DIR_OUT = 0, + GPIO_DIR_IN = 1, + GPIO_DIR_MAX, + GPIO_DIR_DEFAULT = GPIO_DIR_IN, +} GPIO_DIR; + +/* GPIO PULL ENABLE*/ +typedef enum { + GPIO_PULL_EN_UNSUPPORTED = -1, + GPIO_PULL_DISABLE = 0, + GPIO_PULL_ENABLE = 1, + GPIO_PULL_ENABLE_R0 = 2, + GPIO_PULL_ENABLE_R1 = 3, + GPIO_PULL_ENABLE_R0R1 = 4, + + GPIO_PULL_EN_MAX, + GPIO_PULL_EN_DEFAULT = GPIO_PULL_ENABLE, +} GPIO_PULL_EN; + +/* GPIO PULL-UP/PULL-DOWN*/ +typedef enum { + GPIO_PULL_UNSUPPORTED = -1, + GPIO_PULL_NONE = 0, + GPIO_PULL_UP = 1, + GPIO_PULL_DOWN = 2, + GPIO_PULL_MAX, + GPIO_PULL_DEFAULT = GPIO_PULL_DOWN +} GPIO_PULL; + +/* GPIO OUTPUT */ +typedef enum { + GPIO_OUT_UNSUPPORTED = -1, + GPIO_OUT_ZERO = 0, + GPIO_OUT_ONE = 1, + + GPIO_OUT_MAX, + GPIO_OUT_DEFAULT = GPIO_OUT_ZERO, + GPIO_DATA_OUT_DEFAULT = GPIO_OUT_ZERO, /*compatible with DCT*/ +} GPIO_OUT; + +/* GPIO INPUT */ +typedef enum { + GPIO_IN_UNSUPPORTED = -1, + GPIO_IN_ZERO = 0, + GPIO_IN_ONE = 1, + + GPIO_IN_MAX, +} GPIO_IN; + +typedef struct { + uint32_t val; + uint32_t set; + uint32_t rst; + uint32_t _align1; +} VAL_REGS; + +typedef struct { + VAL_REGS dir[6]; /*0x0000 ~ 0x005F: 96 bytes */ + uint8_t rsv00[160]; /*0x0060 ~ 0x00FF: 160 bytes */ + VAL_REGS dout[6]; /*0x0100 ~ 0x015F: 96 bytes */ + uint8_t rsv01[160]; /*0x0160 ~ 0x01FF: 160 bytes */ + VAL_REGS din[6]; /*0x0200 ~ 0x025F: 96 bytes */ + uint8_t rsv02[160]; /*0x0260 ~ 0x02FF: 160 bytes */ + VAL_REGS mode[23]; /*0x0300 ~ 0x046F: 368 bytes */ +} GPIO_REGS; + +/* GPIO Driver interface */ +/*direction*/ +void mt_set_gpio_dir(int gpio, int direction); +int mt_get_gpio_dir(int gpio); + +/*pull select*/ +void mt_set_gpio_pull(int gpio, int pull); +int mt_get_gpio_pull(int gpio); + +/*input/output*/ +void mt_set_gpio_out(int gpio, int value); +int mt_get_gpio_out(int gpio); +int mt_get_gpio_in(int gpio); + +/*mode control*/ +void mt_set_gpio_mode(int gpio, int mode); +int mt_get_gpio_mode(int gpio); + +#endif /* MT_GPIO_H */ diff --git a/plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h b/plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h new file mode 100644 index 000000000..4e1fd2b2b --- /dev/null +++ b/plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_GPIO_CFG_H +#define MT_GPIO_CFG_H + +#include +#include + +#define IOCFG_0_BASE 0x11F20000 +#define IOCFG_1_BASE 0x11E80000 +#define IOCFG_2_BASE 0x11E70000 +#define IOCFG_3_BASE 0x11E90000 +#define IOCFG_4_BASE 0x11D30000 +#define IOCFG_5_BASE 0x11D20000 +#define IOCFG_6_BASE 0x11C50000 +#define IOCFG_7_BASE 0x11F30000 + +typedef struct { + int8_t offset; +} PIN_offset; + +PIN_offset PULL_offset[] = { + /* 0 */ {6}, + /* 1 */ {7}, + /* 2 */ {8}, + /* 3 */ {9}, + /* 4 */ {11}, + /* 5 */ {12}, + /* 6 */ {13}, + /* 7 */ {14}, + /* 8 */ {0}, + /* 9 */ {26}, + /* 10 */ {27}, + /* 11 */ {10}, + /* 12 */ {17}, + /* 13 */ {6}, + /* 14 */ {7}, + /* 15 */ {8}, + /* 16 */ {9}, + /* 17 */ {10}, + /* 18 */ {11}, + /* 19 */ {12}, + /* 20 */ {13}, + /* 21 */ {14}, + /* 22 */ {15}, + /* 23 */ {16}, + /* 24 */ {17}, + /* 25 */ {18}, + /* 26 */ {19}, + /* 27 */ {20}, + /* 28 */ {21}, + /* 29 */ {-1}, + /* 30 */ {-1}, + /* 31 */ {-1}, + /* 32 */ {-1}, + /* 33 */ {-1}, + /* 34 */ {-1}, + /* 35 */ {-1}, + /* 36 */ {-1}, + /* 37 */ {-1}, + /* 38 */ {-1}, + /* 39 */ {-1}, + /* 40 */ {-1}, + /* 41 */ {-1}, + /* 42 */ {-1}, + /* 43 */ {8}, + /* 44 */ {9}, + /* 45 */ {10}, + /* 46 */ {11}, + /* 47 */ {12}, + /* 48 */ {13}, + /* 49 */ {14}, + /* 50 */ {0}, + /* 51 */ {1}, + /* 52 */ {2}, + /* 53 */ {3}, + /* 54 */ {4}, + /* 55 */ {5}, + /* 56 */ {6}, + /* 57 */ {7}, + /* 58 */ {8}, + /* 59 */ {9}, + /* 60 */ {10}, + /* 61 */ {0}, + /* 62 */ {1}, + /* 63 */ {2}, + /* 64 */ {3}, + /* 65 */ {4}, + /* 66 */ {5}, + /* 67 */ {6}, + /* 68 */ {7}, + /* 69 */ {8}, + /* 70 */ {9}, + /* 71 */ {10}, + /* 72 */ {11}, + /* 73 */ {12}, + /* 74 */ {13}, + /* 75 */ {14}, + /* 76 */ {15}, + /* 77 */ {16}, + /* 78 */ {17}, + /* 79 */ {18}, + /* 80 */ {19}, + /* 81 */ {20}, + /* 82 */ {21}, + /* 83 */ {22}, + /* 84 */ {23}, + /* 85 */ {24}, + /* 86 */ {25}, + /* 87 */ {26}, + /* 88 */ {27}, + /* 89 */ {24}, + /* 90 */ {1}, + /* 91 */ {-1}, + /* 92 */ {-1}, + /* 93 */ {-1}, + /* 94 */ {-1}, + /* 95 */ {15}, + /* 96 */ {17}, + /* 97 */ {18}, + /* 98 */ {19}, + /* 99 */ {20}, + /* 100 */ {21}, + /* 101 */ {22}, + /* 102 */ {23}, + /* 103 */ {28}, + /* 104 */ {29}, + /* 105 */ {30}, + /* 106 */ {31}, + /* 107 */ {0}, + /* 108 */ {1}, + /* 109 */ {2}, + /* 110 */ {3}, + /* 111 */ {4}, + /* 112 */ {5}, + /* 113 */ {6}, + /* 114 */ {7}, + /* 115 */ {8}, + /* 116 */ {9}, + /* 117 */ {10}, + /* 118 */ {11}, + /* 119 */ {12}, + /* 120 */ {13}, + /* 121 */ {14}, + /* 122 */ {-1}, + /* 123 */ {-1}, + /* 124 */ {-1}, + /* 125 */ {-1}, + /* 126 */ {-1}, + /* 127 */ {-1}, + /* 128 */ {-1}, + /* 129 */ {-1}, + /* 130 */ {-1}, + /* 131 */ {-1}, + /* 132 */ {-1}, + /* 133 */ {-1}, + /* 134 */ {0}, + /* 135 */ {1}, + /* 136 */ {2}, + /* 137 */ {3}, + /* 138 */ {4}, + /* 139 */ {5}, + /* 140 */ {6}, + /* 141 */ {7}, + /* 142 */ {8}, + /* 143 */ {9}, + /* 144 */ {11}, + /* 145 */ {12}, + /* 146 */ {13}, + /* 147 */ {14}, + /* 148 */ {15}, + /* 149 */ {16}, + /* 150 */ {18}, + /* 151 */ {19}, + /* 152 */ {20}, + /* 153 */ {21}, + /* 154 */ {22}, + /* 155 */ {23}, + /* 156 */ {24}, + /* 157 */ {25}, + /* 158 */ {26}, + /* 159 */ {27}, + /* 160 */ {28}, + /* 161 */ {0}, + /* 162 */ {1}, + /* 163 */ {2}, + /* 164 */ {3}, + /* 165 */ {4}, + /* 166 */ {5}, + /* 167 */ {11}, + /* 168 */ {12}, + /* 169 */ {13}, + /* 170 */ {14}, + /* 171 */ {15}, + /* 172 */ {16}, + /* 173 */ {17}, + /* 174 */ {18}, + /* 175 */ {19}, + /* 176 */ {20}, + /* 177 */ {10}, + /* 178 */ {16}, + /* 179 */ {25} +}; +#endif /* MT_GPIO_CFG_H */ diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index f2e15e386..9c2b9645c 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -10,6 +10,7 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/drivers/ \ -I${MTK_PLAT_SOC}/drivers/spmc/ \ + -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \ -I${MTK_PLAT_SOC}/drivers/rtc/ \ -I${MTK_PLAT_SOC}/include/ @@ -43,6 +44,7 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \ + ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ ${MTK_PLAT_SOC}/plat_pm.c \ ${MTK_PLAT_SOC}/plat_topology.c \ ${MTK_PLAT_SOC}/plat_mt_gic.c \ -- cgit v1.2.3 From a561205724cb188624b5ac6543faa9e44cc1a882 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Fri, 3 May 2019 16:59:07 +0800 Subject: mediatek: mt8183: pass platform parameters Add plat parameter structs to support BL2 to pass variable-length, variable-type parameters to BL31. The parameters are structured as a link list. During BL31 setup time, we traverse the list to process each parameter. Signed-off-by: kenny liang Change-Id: Ie84cfc9606656fb1d2780a68cadf27e09afa6628 --- .../export/plat/mediatek/common/plat_params_exp.h | 19 ++++++++++++ plat/mediatek/common/params_setup.c | 35 ++++++++++++++++++++++ plat/mediatek/common/plat_params.h | 17 +++++++++++ plat/mediatek/mt8183/bl31_plat_setup.c | 3 ++ plat/mediatek/mt8183/platform.mk | 2 ++ 5 files changed, 76 insertions(+) create mode 100644 include/export/plat/mediatek/common/plat_params_exp.h create mode 100644 plat/mediatek/common/params_setup.c create mode 100644 plat/mediatek/common/plat_params.h diff --git a/include/export/plat/mediatek/common/plat_params_exp.h b/include/export/plat/mediatek/common/plat_params_exp.h new file mode 100644 index 000000000..d65003086 --- /dev/null +++ b/include/export/plat/mediatek/common/plat_params_exp.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_MEDIATEK_COMMON_PLAT_PARAMS_EXP_H +#define ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_MEDIATEK_COMMON_PLAT_PARAMS_EXP_H + +/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */ + +#include "../../../lib/bl_aux_params/bl_aux_params_exp.h" + +/* param type */ +enum bl_aux_mtk_param_type { + BL_AUX_PARAM_MTK_RESET_GPIO = BL_AUX_PARAM_VENDOR_SPECIFIC_FIRST, +}; + +#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_MEDIATEK_COMMON_PLAT_PARAMS_EXP_H */ diff --git a/plat/mediatek/common/params_setup.c b/plat/mediatek/common/params_setup.c new file mode 100644 index 000000000..a9df13e23 --- /dev/null +++ b/plat/mediatek/common/params_setup.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +static struct bl_aux_gpio_info rst_gpio; + +struct bl_aux_gpio_info *plat_get_mtk_gpio_reset(void) +{ + return &rst_gpio; +} + +static bool mtk_aux_param_handler(struct bl_aux_param_header *param) +{ + /* Store platform parameters for later processing if needed. */ + switch (param->type) { + case BL_AUX_PARAM_MTK_RESET_GPIO: + rst_gpio = ((struct bl_aux_param_gpio *)param)->gpio; + return true; + } + + return false; +} + +void params_early_setup(u_register_t plat_param_from_bl2) +{ + bl_aux_params_parse(plat_param_from_bl2, mtk_aux_param_handler); +} + diff --git a/plat/mediatek/common/plat_params.h b/plat/mediatek/common/plat_params.h new file mode 100644 index 000000000..828c3dccf --- /dev/null +++ b/plat/mediatek/common/plat_params.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PARAMS_H +#define PLAT_PARAMS_H + +#include + +#include + +struct bl_aux_gpio_info *plat_get_mtk_gpio_reset(void); +void params_early_setup(u_register_t plat_param_from_bl2); + +#endif diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c index f20e8acdd..ea39ff6f6 100644 --- a/plat/mediatek/mt8183/bl31_plat_setup.c +++ b/plat/mediatek/mt8183/bl31_plat_setup.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -74,6 +75,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, { static console_16550_t console; + params_early_setup(arg1); + console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); NOTICE("MT8183 bl31_setup\n"); diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index 9c2b9645c..8fb015105 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -31,6 +31,7 @@ BL31_SOURCES += common/desc_image_load.c \ drivers/delay_timer/generic_delay_timer.c \ drivers/gpio/gpio.c \ drivers/ti/uart/aarch64/16550_console.S \ + lib/bl_aux_params/bl_aux_params.c \ lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a73.S \ @@ -38,6 +39,7 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT}/common/mtk_plat_common.c \ ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \ ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ + ${MTK_PLAT}/common/params_setup.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ ${MTK_PLAT_SOC}/aarch64/platform_common.c \ ${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c \ -- cgit v1.2.3 From 3d91c9c382cf392b7012a2849388426f7b5003e0 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Fri, 3 May 2019 17:02:46 +0800 Subject: mediatek: mt8183: support system reset Implement system reset handler. Change-Id: I535ee414616dde8d2b59dec5a723a540a3a1341d Signed-off-by: kenny liang --- plat/mediatek/mt8183/plat_pm.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c index e2aa2b9ec..83c8d4cdc 100644 --- a/plat/mediatek/mt8183/plat_pm.c +++ b/plat/mediatek/mt8183/plat_pm.c @@ -17,11 +17,13 @@ #include #include #include +#include #include -#include #include #include +#include #include +#include #include #include @@ -132,6 +134,19 @@ static void __dead2 plat_mtk_system_off(void) panic(); } +static void __dead2 plat_mtk_system_reset(void) +{ + struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset(); + + INFO("MTK System Reset\n"); + + mt_set_gpio_out(gpio_reset->index, gpio_reset->polarity); + + wfi(); + ERROR("MTK System Reset: operation not handled.\n"); + panic(); +} + /******************************************************************************* * MTK_platform handler called when an affinity instance is about to be turned * on. The level and mpidr determine the affinity instance. @@ -144,7 +159,7 @@ static const plat_psci_ops_t plat_plat_pm_ops = { .pwr_domain_suspend = NULL, .pwr_domain_suspend_finish = NULL, .system_off = plat_mtk_system_off, - .system_reset = NULL, + .system_reset = plat_mtk_system_reset, .validate_power_state = NULL, .get_sys_suspend_power_state = NULL, }; -- cgit v1.2.3 From 0d8cb4937e7872c6fc49d26cc83bb72be907a073 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Thu, 2 May 2019 21:42:41 +0800 Subject: mediatek: mt8183: Support coreboot configuration When built for coreboot, we want to enable coreboot library to have better integration. For example, serial console should be initialized by coreboot_serial instead of hard-coded values. Most coreboot configuration will enable memory console, which needs larger XLAT_TABLES so MAX_XLAT_TABLES is increased; and to support that, TZRAM_SIZE also need to be enlarged. Change-Id: I08cf22df2fa26e48284e323d22ad8ce73a6ea803 Signed-off-by: Hung-Te Lin --- plat/mediatek/mt8183/bl31_plat_setup.c | 9 +++++++++ plat/mediatek/mt8183/include/platform_def.h | 4 ++-- plat/mediatek/mt8183/platform.mk | 2 ++ 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c index ea39ff6f6..337470abb 100644 --- a/plat/mediatek/mt8183/bl31_plat_setup.c +++ b/plat/mediatek/mt8183/bl31_plat_setup.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -77,7 +78,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, params_early_setup(arg1); +#if COREBOOT + if (coreboot_serial.type) + console_16550_register(coreboot_serial.baseaddr, + coreboot_serial.input_hertz, + coreboot_serial.baud, + &console); +#else console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); +#endif NOTICE("MT8183 bl31_setup\n"); diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h index bc9022bb4..f802ac2f5 100644 --- a/plat/mediatek/mt8183/include/platform_def.h +++ b/plat/mediatek/mt8183/include/platform_def.h @@ -273,7 +273,7 @@ INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ ******************************************************************************/ #define TZRAM_BASE 0x54600000 -#define TZRAM_SIZE 0x00020000 +#define TZRAM_SIZE 0x00030000 /******************************************************************************* * BL31 specific defines. @@ -291,7 +291,7 @@ INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ ******************************************************************************/ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) -#define MAX_XLAT_TABLES 4 +#define MAX_XLAT_TABLES 16 #define MAX_MMAP_REGIONS 16 /******************************************************************************* diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index 8fb015105..09fd13319 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -70,3 +70,5 @@ MULTI_CONSOLE_API := 1 MACH_MT8183 := 1 $(eval $(call add_define,MACH_MT8183)) +include lib/coreboot/coreboot.mk + -- cgit v1.2.3 From 40b06510f29058215b7774806c6cc3921cd55e5b Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Tue, 27 Aug 2019 09:43:47 +0100 Subject: Add python configuration for editorconfig As it currently is, python files are formatted using the general rules in .editorconfig - this means that 8-character hard tabs are used, which is not the recommended behaviour according to the PEP-8 standard. This patch correct this, and additionally limits the line length to 79 characters as required by the standard. Change-Id: I3b5c0aff12034c4184d4555aab36490cdb3885da Signed-off-by: Justin Chadwell --- .editorconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/.editorconfig b/.editorconfig index 928c30705..b14e0253b 100644 --- a/.editorconfig +++ b/.editorconfig @@ -11,6 +11,8 @@ # [CONT] contributing.rst # [LCS] Linux Coding Style # (https://www.kernel.org/doc/html/v4.10/process/coding-style.html) +# [PEP8] Style Guide for Python Code +# (https://www.python.org/dev/peps/pep-0008) root = true @@ -60,3 +62,14 @@ max_line_length = 180 # 180 only selected to prevent changes to existing text. tab_width = 4 + +# Adjustment for python which prefers a different style +[*.py] +# [PEP8] Indentation +# "Use 4 spaces per indentation level." +indent_size = 4 +indent_style = space + +# [PEP8] Maximum Line Length +# "Limit all lines to a maximum of 79 characters." +max_line_length = 79 -- cgit v1.2.3 From ebf851ed34eda0a4fcd87a155a13b02f3db8573c Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 4 Sep 2019 11:55:10 +0200 Subject: stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver The STM32 console driver was pre-pending '\r' before '\n'. It is now managed by the framework with the flag: CONSOLE_FLAG_TRANSLATE_CRLF. Remove the code in driver, and add the flag for STM32MP1. Change-Id: I5d0d5d5c4abee0b7dc11c2f8707b1b5cf10149ab Signed-off-by: Yann Gautier --- drivers/st/uart/aarch32/stm32_console.S | 28 ++++++---------------------- plat/st/stm32mp1/bl2_plat_setup.c | 3 +++ plat/st/stm32mp1/sp_min/sp_min_setup.c | 8 ++++++-- 3 files changed, 15 insertions(+), 24 deletions(-) diff --git a/drivers/st/uart/aarch32/stm32_console.S b/drivers/st/uart/aarch32/stm32_console.S index 39e449b29..ca3c1f618 100644 --- a/drivers/st/uart/aarch32/stm32_console.S +++ b/drivers/st/uart/aarch32/stm32_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -138,34 +138,18 @@ func console_stm32_core_putc /* Check the input parameter */ cmp r1, #0 beq putc_error - /* Prepend '\r' to '\n' */ - cmp r0, #0xA - bne 2f -1: - /* Check Transmit Data Register Empty */ -txe_loop_1: - ldr r2, [r1, #USART_ISR] - tst r2, #USART_ISR_TXE - beq txe_loop_1 - mov r2, #0xD - str r2, [r1, #USART_TDR] - /* Check transmit complete flag */ -tc_loop_1: - ldr r2, [r1, #USART_ISR] - tst r2, #USART_ISR_TC - beq tc_loop_1 -2: + /* Check Transmit Data Register Empty */ -txe_loop_2: +txe_loop: ldr r2, [r1, #USART_ISR] tst r2, #USART_ISR_TXE - beq txe_loop_2 + beq txe_loop str r0, [r1, #USART_TDR] /* Check transmit complete flag */ -tc_loop_2: +tc_loop: ldr r2, [r1, #USART_ISR] tst r2, #USART_ISR_TC - beq tc_loop_2 + beq tc_loop bx lr putc_error: mov r0, #-1 diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index 75ae372ae..c6aefe324 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -272,6 +272,9 @@ void bl2_el3_plat_arch_setup(void) panic(); } + console_set_scope(&console.console, CONSOLE_FLAG_BOOT | + CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF); + stm32mp_print_cpuinfo(); board_model = dt_get_board_model(); diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c index 417115b65..e10dfbfc0 100644 --- a/plat/st/stm32mp1/sp_min/sp_min_setup.c +++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c @@ -129,16 +129,20 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, result = dt_get_stdout_uart_info(&dt_uart_info); if ((result > 0) && (dt_uart_info.status != 0U)) { + unsigned int console_flags; + if (console_stm32_register(dt_uart_info.base, 0, STM32MP_UART_BAUDRATE, &console) == 0) { panic(); } + console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH | + CONSOLE_FLAG_TRANSLATE_CRLF; #ifdef DEBUG - console_set_scope(&console.console, - CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); + console_flags |= CONSOLE_FLAG_RUNTIME; #endif + console_set_scope(&console.console, console_flags); } } -- cgit v1.2.3 From 705bed5db104e6aee9b3cc9d25776299581be49e Mon Sep 17 00:00:00 2001 From: Jolly Shah Date: Tue, 27 Aug 2019 11:23:08 -0700 Subject: plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup() Common ipi_table needs to be initialized before using any IPI command (i.e send/receive). Move zynqmp ipi config table initialization from sip_svc_setup() to zynqmp_config_setup(). Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah --- plat/xilinx/zynqmp/aarch64/zynqmp_common.c | 6 +++++- plat/xilinx/zynqmp/platform.mk | 2 +- plat/xilinx/zynqmp/sip_svc_setup.c | 4 ---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c index 8ff6c4360..ab5d95d1e 100644 --- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c +++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -325,6 +326,9 @@ unsigned int zynqmp_get_bootmode(void) void zynqmp_config_setup(void) { + /* Configure IPI data for ZynqMP */ + zynqmp_ipi_config_table_init(); + zynqmp_print_platform_name(); generic_delay_timer_init(); } diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index bd7bc08da..c34a51674 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -64,6 +64,7 @@ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ plat/arm/common/arm_gicv2.c \ plat/common/plat_gicv2.c \ plat/xilinx/common/ipi.c \ + plat/xilinx/zynqmp/zynqmp_ipi.c \ plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \ plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -78,7 +79,6 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ plat/xilinx/zynqmp/plat_startup.c \ plat/xilinx/zynqmp/plat_topology.c \ plat/xilinx/zynqmp/sip_svc_setup.c \ - plat/xilinx/zynqmp/zynqmp_ipi.c \ plat/xilinx/zynqmp/pm_service/pm_svc_main.c \ plat/xilinx/zynqmp/pm_service/pm_api_sys.c \ plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c \ diff --git a/plat/xilinx/zynqmp/sip_svc_setup.c b/plat/xilinx/zynqmp/sip_svc_setup.c index edb81f5c3..9b182749c 100644 --- a/plat/xilinx/zynqmp/sip_svc_setup.c +++ b/plat/xilinx/zynqmp/sip_svc_setup.c @@ -9,7 +9,6 @@ #include #include -#include #include "ipi_mailbox_svc.h" #include "pm_svc_main.h" @@ -41,9 +40,6 @@ DEFINE_SVC_UUID2(zynqmp_sip_uuid, */ static int32_t sip_svc_setup(void) { - /* Configure IPI data for ZynqMP */ - zynqmp_ipi_config_table_init(); - /* PM implementation as SiP Service */ pm_setup(); -- cgit v1.2.3 From f906a44e9ea9ccefaab2a9d40bb2cb3f354609c8 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 26 Jul 2019 20:21:39 +0900 Subject: libc: fix sparse warning for __assert() Sparse warns this: lib/libc/assert.c:29:6: error: symbol '__assert' redeclared with different type (originally declared at include/lib/libc/assert.h:36) - different modifiers Add __dead2 to match the header declaration and C definition. I also changed '__dead2 void' to 'void __dead2' for the consistency with other parts. Change-Id: Iefa4f0e787c24fa7e7e499d2e7baf54d4deb49ef Signed-off-by: Masahiro Yamada --- include/lib/libc/assert.h | 8 ++++---- lib/libc/assert.c | 9 +++++---- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/lib/libc/assert.h b/include/lib/libc/assert.h index d04f9dc04..486bbc290 100644 --- a/include/lib/libc/assert.h +++ b/include/lib/libc/assert.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,12 +30,12 @@ #endif /* ENABLE_ASSERTIONS */ #if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE -__dead2 void __assert(const char *file, unsigned int line, +void __dead2 __assert(const char *file, unsigned int line, const char *assertion); #elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO -__dead2 void __assert(const char *file, unsigned int line); +void __dead2 __assert(const char *file, unsigned int line); #else -__dead2 void __assert(void); +void __dead2 __assert(void); #endif #endif /* ASSERT_H */ diff --git a/lib/libc/assert.c b/lib/libc/assert.c index 60f1a8660..49f59db16 100644 --- a/lib/libc/assert.c +++ b/lib/libc/assert.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,7 +18,8 @@ */ #if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE -void __assert(const char *file, unsigned int line, const char *assertion) +void __dead2 __assert(const char *file, unsigned int line, + const char *assertion) { printf("ASSERT: %s:%d:%s\n", file, line, assertion); backtrace("assert"); @@ -26,7 +27,7 @@ void __assert(const char *file, unsigned int line, const char *assertion) plat_panic_handler(); } #elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO -void __assert(const char *file, unsigned int line) +void __dead2 __assert(const char *file, unsigned int line) { printf("ASSERT: %s:%d\n", file, line); backtrace("assert"); @@ -34,7 +35,7 @@ void __assert(const char *file, unsigned int line) plat_panic_handler(); } #else -void __assert(void) +void __dead2 __assert(void) { backtrace("assert"); (void)console_flush(); -- cgit v1.2.3 From 1f4619796af5baf4b41b5723bbf708355f8597fa Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Tue, 20 Aug 2019 11:01:52 +0100 Subject: Add UBSAN support and handlers This patch adds support for the Undefined Behaviour sanitizer. There are two types of support offered - minimalistic trapping support which essentially immediately crashes on undefined behaviour and full support with full debug messages. The full support relies on ubsan.c which has been adapted from code used by OPTEE. Change-Id: I417c810f4fc43dcb56db6a6a555bfd0b38440727 Signed-off-by: Justin Chadwell --- Makefile | 20 ++++ bl31/aarch64/runtime_exceptions.S | 57 ++++++++++ docs/getting_started/user-guide.rst | 15 +++ include/arch/aarch64/arch.h | 3 + make_helpers/defaults.mk | 2 + plat/common/ubsan.c | 220 ++++++++++++++++++++++++++++++++++++ 6 files changed, 317 insertions(+) create mode 100644 plat/common/ubsan.c diff --git a/Makefile b/Makefile index 43ff8d2ff..043e751a7 100644 --- a/Makefile +++ b/Makefile @@ -278,6 +278,14 @@ TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ -ffreestanding -fno-builtin -Wall -std=gnu99 \ -Os -ffunction-sections -fdata-sections +ifeq (${SANITIZE_UB},on) +TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover +endif +ifeq (${SANITIZE_UB},trap) +TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover \ + -fsanitize-undefined-trap-on-error +endif + GCC_V_OUTPUT := $(shell $(CC) -v 2>&1) ifneq ($(findstring armlink,$(notdir $(LD))),) @@ -313,6 +321,10 @@ ifeq ($(notdir $(CC)),armclang) BL_COMMON_SOURCES += lib/${ARCH}/armclang_printf.S endif +ifeq (${SANITIZE_UB},on) +BL_COMMON_SOURCES += plat/common/ubsan.c +endif + INCLUDES += -Iinclude \ -Iinclude/arch/${ARCH} \ -Iinclude/lib/cpus/${ARCH} \ @@ -673,6 +685,10 @@ $(eval $(call assert_numeric,ARM_ARCH_MAJOR)) $(eval $(call assert_numeric,ARM_ARCH_MINOR)) $(eval $(call assert_numeric,BRANCH_PROTECTION)) +ifeq ($(filter $(SANITIZE_UB), on off trap),) + $(error "Invalid value for SANITIZE_UB: can be one of on, off, trap") +endif + ################################################################################ # Add definitions to the cpp preprocessor based on the current build options. # This is done after including the platform specific makefile to allow the @@ -724,6 +740,10 @@ $(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY)) $(eval $(call add_define,BL2_AT_EL3)) $(eval $(call add_define,BL2_IN_XIP_MEM)) +ifeq (${SANITIZE_UB},trap) + $(eval $(call add_define,MONITOR_TRAPS)) +endif + # Define the EL3_PAYLOAD_BASE flag only if it is provided. ifdef EL3_PAYLOAD_BASE $(eval $(call add_define,EL3_PAYLOAD_BASE)) diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index fd7656e2c..1cbec8fd9 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -220,6 +220,19 @@ vector_base runtime_exceptions * --------------------------------------------------------------------- */ vector_entry sync_exception_sp_el0 +#ifdef MONITOR_TRAPS + stp x29, x30, [sp, #-16]! + + mrs x30, esr_el3 + ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + + /* Check for BRK */ + cmp x30, #EC_BRK + b.eq brk_handler + + ldp x29, x30, [sp], #16 +#endif /* MONITOR_TRAPS */ + /* We don't expect any synchronous exceptions from EL3 */ b report_unhandled_exception end_vector_entry sync_exception_sp_el0 @@ -328,6 +341,14 @@ vector_entry serror_aarch32 b enter_lower_el_async_ea end_vector_entry serror_aarch32 +#ifdef MONITOR_TRAPS + .section .rodata.brk_string, "aS" +brk_location: + .asciz "Error at instruction 0x" +brk_message: + .asciz "Unexpected BRK instruction with value 0x" +#endif /* MONITOR_TRAPS */ + /* --------------------------------------------------------------------- * The following code handles secure monitor calls. * Depending upon the execution state from where the SMC has been @@ -455,3 +476,39 @@ rt_svc_fw_critical_error: msr spsel, #1 no_ret report_unhandled_exception endfunc smc_handler + + /* --------------------------------------------------------------------- + * The following code handles exceptions caused by BRK instructions. + * Following a BRK instruction, the only real valid cause of action is + * to print some information and panic, as the code that caused it is + * likely in an inconsistent internal state. + * + * This is initially intended to be used in conjunction with + * __builtin_trap. + * --------------------------------------------------------------------- + */ +#ifdef MONITOR_TRAPS +func brk_handler + /* Extract the ISS */ + mrs x10, esr_el3 + ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH + + /* Ensure the console is initialized */ + bl plat_crash_console_init + + adr x4, brk_location + bl asm_print_str + mrs x4, elr_el3 + bl asm_print_hex + bl asm_print_newline + + adr x4, brk_message + bl asm_print_str + mov x4, x10 + mov x5, #28 + bl asm_print_hex_bits + bl asm_print_newline + + no_ret plat_panic_handler +endfunc brk_handler +#endif /* MONITOR_TRAPS */ diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index b447f1493..1cfd4c739 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -684,6 +684,21 @@ Common build options file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key. +- ``SANITIZE_UB``: This option enables the Undefined Behaviour sanitizer. It + can take 3 values: 'off' (default), 'on' and 'trap'. When using 'trap', + gcc and clang will insert calls to ``__builtin_trap`` on detected + undefined behaviour, which defaults to a ``brk`` instruction. When using + 'on', undefined behaviour is translated to a call to special handlers which + prints the exact location of the problem and its cause and then panics. + + .. note:: + Because of the space penalty of the Undefined Behaviour sanitizer, + this option will increase the size of the binary. Depending on the + memory constraints of the target platform, it may not be possible to + enable the sanitizer for all images (BL1 and BL2 are especially + likely to be memory constrained). We recommend that the + sanitizer is enabled only in debug builds. + - ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the certificate generation tool to save the keys used to establish the Chain of Trust. Allowed options are '0' or '1'. Default is '0' (do not save). diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 5f84ecede..0a26fab1e 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -598,6 +598,8 @@ #define ESR_EC_SHIFT U(26) #define ESR_EC_MASK U(0x3f) #define ESR_EC_LENGTH U(6) +#define ESR_ISS_SHIFT U(0) +#define ESR_ISS_LENGTH U(25) #define EC_UNKNOWN U(0x0) #define EC_WFE_WFI U(0x1) #define EC_AARCH32_CP15_MRC_MCR U(0x3) @@ -624,6 +626,7 @@ #define EC_AARCH32_FP U(0x28) #define EC_AARCH64_FP U(0x2c) #define EC_SERROR U(0x2f) +#define EC_BRK U(0x3c) /* * External Abort bit in Instruction and Data Aborts synchronous exception diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index f63e46f39..fa2133551 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -224,3 +224,5 @@ ifneq (${ARCH},aarch32) else override ENABLE_SVE_FOR_NS := 0 endif + +SANITIZE_UB := off diff --git a/plat/common/ubsan.c b/plat/common/ubsan.c new file mode 100644 index 000000000..45b0f7cce --- /dev/null +++ b/plat/common/ubsan.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2016, Linaro Limited + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause + */ + +#include +#include +#include +#include + +struct source_location { + const char *file_name; + uint32_t line; + uint32_t column; +}; + +struct type_descriptor { + uint16_t type_kind; + uint16_t type_info; + char type_name[1]; +}; + +struct type_mismatch_data { + struct source_location loc; + struct type_descriptor *type; + unsigned long alignment; + unsigned char type_check_kind; +}; + +struct overflow_data { + struct source_location loc; + struct type_descriptor *type; +}; + +struct shift_out_of_bounds_data { + struct source_location loc; + struct type_descriptor *lhs_type; + struct type_descriptor *rhs_type; +}; + +struct out_of_bounds_data { + struct source_location loc; + struct type_descriptor *array_type; + struct type_descriptor *index_type; +}; + +struct unreachable_data { + struct source_location loc; +}; + +struct vla_bound_data { + struct source_location loc; + struct type_descriptor *type; +}; + +struct invalid_value_data { + struct source_location loc; + struct type_descriptor *type; +}; + +struct nonnull_arg_data { + struct source_location loc; +}; + +/* + * When compiling with -fsanitize=undefined the compiler expects functions + * with the following signatures. The functions are never called directly, + * only when undefined behavior is detected in instrumented code. + */ +void __ubsan_handle_type_mismatch_abort(struct type_mismatch_data *data, + unsigned long ptr); +void __ubsan_handle_type_mismatch_v1_abort(struct type_mismatch_data *data, + unsigned long ptr); +void __ubsan_handle_add_overflow_abort(struct overflow_data *data, + unsigned long lhs, unsigned long rhs); +void __ubsan_handle_sub_overflow_abort(struct overflow_data *data, + unsigned long lhs, unsigned long rhs); +void __ubsan_handle_mul_overflow_abort(struct overflow_data *data, + unsigned long lhs, unsigned long rhs); +void __ubsan_handle_negate_overflow_abort(struct overflow_data *data, + unsigned long old_val); +void __ubsan_handle_pointer_overflow_abort(struct overflow_data *data, + unsigned long old_val); +void __ubsan_handle_divrem_overflow_abort(struct overflow_data *data, + unsigned long lhs, unsigned long rhs); +void __ubsan_handle_shift_out_of_bounds_abort(struct shift_out_of_bounds_data *data, + unsigned long lhs, unsigned long rhs); +void __ubsan_handle_out_of_bounds_abort(struct out_of_bounds_data *data, + unsigned long idx); +void __ubsan_handle_unreachable_abort(struct unreachable_data *data); +void __ubsan_handle_missing_return_abort(struct unreachable_data *data); +void __ubsan_handle_vla_bound_not_positive_abort(struct vla_bound_data *data, + unsigned long bound); +void __ubsan_handle_load_invalid_value_abort(struct invalid_value_data *data, + unsigned long val); +void __ubsan_handle_nonnull_arg_abort(struct nonnull_arg_data *data +#if __GCC_VERSION < 60000 + , size_t arg_no +#endif + ); + +static void print_loc(const char *func, struct source_location *loc) +{ + ERROR("Undefined behavior at %s:%d col %d (%s)", + loc->file_name, loc->line, loc->column, func); +} + + +void __ubsan_handle_type_mismatch_abort(struct type_mismatch_data *data, + unsigned long ptr __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_type_mismatch_v1_abort(struct type_mismatch_data *data, + unsigned long ptr __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_add_overflow_abort(struct overflow_data *data, + unsigned long lhs __unused, + unsigned long rhs __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_sub_overflow_abort(struct overflow_data *data, + unsigned long lhs __unused, + unsigned long rhs __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_mul_overflow_abort(struct overflow_data *data, + unsigned long lhs __unused, + unsigned long rhs __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_negate_overflow_abort(struct overflow_data *data, + unsigned long old_val __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_pointer_overflow_abort(struct overflow_data *data, + unsigned long old_val __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_divrem_overflow_abort(struct overflow_data *data, + unsigned long lhs __unused, + unsigned long rhs __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_shift_out_of_bounds_abort(struct shift_out_of_bounds_data *data, + unsigned long lhs __unused, + unsigned long rhs __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_out_of_bounds_abort(struct out_of_bounds_data *data, + unsigned long idx __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_unreachable_abort(struct unreachable_data *data) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_missing_return_abort(struct unreachable_data *data) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_vla_bound_not_positive_abort(struct vla_bound_data *data, + unsigned long bound __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_load_invalid_value_abort(struct invalid_value_data *data, + unsigned long val __unused) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} + +void __ubsan_handle_nonnull_arg_abort(struct nonnull_arg_data *data +#if __GCC_VERSION < 60000 + , size_t arg_no __unused +#endif + ) +{ + print_loc(__func__, &data->loc); + plat_panic_handler(); +} -- cgit v1.2.3 From 07f979bcc70521dbc020d7ac87a09510fe86c7d0 Mon Sep 17 00:00:00 2001 From: John Tsichritzis Date: Tue, 13 Aug 2019 10:28:25 +0100 Subject: Zeus: apply the MSR SSBS instruction Zeus supports the SSBS mechanism and also the new MSR instruction to immediately apply the mitigation. Hence, the new instruction is utilised in the Zeus-specific reset function. Change-Id: I962747c28afe85a15207a0eba4146f9a115b27e7 Signed-off-by: John Tsichritzis --- lib/cpus/aarch64/neoverse_zeus.S | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/lib/cpus/aarch64/neoverse_zeus.S b/lib/cpus/aarch64/neoverse_zeus.S index 3d850137c..44882b459 100644 --- a/lib/cpus/aarch64/neoverse_zeus.S +++ b/lib/cpus/aarch64/neoverse_zeus.S @@ -46,6 +46,16 @@ func neoverse_zeus_errata_report endfunc neoverse_zeus_errata_report #endif +func neoverse_zeus_reset_func + mov x19, x30 + + /* Disable speculative loads */ + msr SSBS, xzr + + isb + ret x19 +endfunc neoverse_zeus_reset_func + /* --------------------------------------------- * This function provides Neoverse-Zeus specific * register information for crash reporting. @@ -66,5 +76,5 @@ func neoverse_zeus_cpu_reg_dump endfunc neoverse_zeus_cpu_reg_dump declare_cpu_ops neoverse_zeus, NEOVERSE_ZEUS_MIDR, \ - CPU_NO_RESET_FUNC, \ + neoverse_zeus_reset_func, \ neoverse_zeus_core_pwr_dwn -- cgit v1.2.3 From cd3c5b4cd765d6a56924fc80e98721441fe99b27 Mon Sep 17 00:00:00 2001 From: John Tsichritzis Date: Tue, 13 Aug 2019 10:11:41 +0100 Subject: Modify FVP makefile for cores that support both AArch64/32 Some cores support only AArch64 from EL1 and above, e.g. A76, N1 etc. If TF-A is compiled with CTX_INCLUDE_AARCH32_REGS=0 so as to properly handle those cores, only the AArch64 cores' assembly is included in the TF-A binary. In other words, for FVP, TF-A assumes that AArch64 only cores will never exist in the same cluster with cores that also support AArch32. However, A55 and A75 can be used as AArch64 only cores, despite supporting AArch32, too. This patch enables A55 and A75 to exist in clusters together with AArch64 cores. Change-Id: I58750ad6c3d76ce77eb354784c2a42f2c179031d Signed-off-by: John Tsichritzis --- plat/arm/board/fvp/platform.mk | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 617da2d69..1e7cfce5e 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -99,14 +99,16 @@ ifeq (${ARCH}, aarch64) # select a different set of CPU files, depending on whether we compile for # hardware assisted coherency cores or not ifeq (${HW_ASSISTED_COHERENCY}, 0) +# Cores used without DSU FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a72.S \ lib/cpus/aarch64/cortex_a73.S else - # AArch64-only cores +# Cores used with DSU only ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) + # AArch64-only cores FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ lib/cpus/aarch64/cortex_a76ae.S \ lib/cpus/aarch64/cortex_a77.S \ @@ -114,11 +116,10 @@ else lib/cpus/aarch64/neoverse_e1.S \ lib/cpus/aarch64/neoverse_zeus.S \ lib/cpus/aarch64/cortex_hercules.S - # AArch64/AArch32 - else - FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ - lib/cpus/aarch64/cortex_a75.S endif + # AArch64/AArch32 cores + FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ + lib/cpus/aarch64/cortex_a75.S endif else -- cgit v1.2.3 From 421b67b66697374f504ec2eb3d9f954437e02f2e Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 28 Aug 2019 10:14:46 +0100 Subject: amlogic: Fix header guards Make the header guards more generic and contextually remove the GXBB_BL31_PLAT_PARAM_VAL value that is unused on the GXL platform. Signed-off-by: Carlo Caione Change-Id: I842fa2e084e71280ae17b39c67877e844821a171 --- plat/amlogic/common/include/aml_private.h | 6 +++--- plat/amlogic/gxl/gxl_def.h | 6 +++--- plat/amlogic/gxl/include/platform_def.h | 3 --- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h index d6629fc3a..492374568 100644 --- a/plat/amlogic/common/include/aml_private.h +++ b/plat/amlogic/common/include/aml_private.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef GXBB_PRIVATE_H -#define GXBB_PRIVATE_H +#ifndef AML_PRIVATE_H +#define AML_PRIVATE_H #include #include @@ -37,4 +37,4 @@ void aml_thermal_unknown(void); uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size); uint64_t aml_efuse_user_max(void); -#endif /* GXBB_PRIVATE_H */ +#endif /* AML_PRIVATE_H */ diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h index 1af101ef2..6f49ed2b0 100644 --- a/plat/amlogic/gxl/gxl_def.h +++ b/plat/amlogic/gxl/gxl_def.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef GXBB_DEF_H -#define GXBB_DEF_H +#ifndef GXL_DEF_H +#define GXL_DEF_H #include @@ -125,4 +125,4 @@ #define AML_JTAG_A53_AO U(2) #define AML_JTAG_A53_EE U(3) -#endif /* GXBB_DEF_H */ +#endif /* GXL_DEF_H */ diff --git a/plat/amlogic/gxl/include/platform_def.h b/plat/amlogic/gxl/include/platform_def.h index 80b0d6463..ec64d6853 100644 --- a/plat/amlogic/gxl/include/platform_def.h +++ b/plat/amlogic/gxl/include/platform_def.h @@ -15,9 +15,6 @@ #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 -/* Special value used to verify platform parameters from BL2 to BL31 */ -#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) - #define PLATFORM_STACK_SIZE UL(0x1000) #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) -- cgit v1.2.3 From b56218744e318097b2d850510505d0bcac6d5132 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Tue, 3 Sep 2019 12:38:58 +0100 Subject: amlogic: Fix includes order As part of the code refactoring fix the order of the include files across all the source files. Signed-off-by: Carlo Caione Change-Id: Ice72f687cc26ee881a9051168149467688100cfb --- plat/amlogic/gxbb/gxbb_bl31_setup.c | 4 +--- plat/amlogic/gxbb/gxbb_common.c | 10 ++++------ plat/amlogic/gxbb/gxbb_pm.c | 8 +++----- plat/amlogic/gxl/gxl_bl31_setup.c | 6 +++--- plat/amlogic/gxl/gxl_common.c | 10 +++++----- plat/amlogic/gxl/gxl_pm.c | 6 +++--- 6 files changed, 19 insertions(+), 25 deletions(-) diff --git a/plat/amlogic/gxbb/gxbb_bl31_setup.c b/plat/amlogic/gxbb/gxbb_bl31_setup.c index 6d6b2ad70..cc7a1c49b 100644 --- a/plat/amlogic/gxbb/gxbb_bl31_setup.c +++ b/plat/amlogic/gxbb/gxbb_bl31_setup.c @@ -5,14 +5,12 @@ */ #include - -#include - #include #include #include #include #include +#include #include "aml_private.h" diff --git a/plat/amlogic/gxbb/gxbb_common.c b/plat/amlogic/gxbb/gxbb_common.c index 831bc66e5..e98748e77 100644 --- a/plat/amlogic/gxbb/gxbb_common.c +++ b/plat/amlogic/gxbb/gxbb_common.c @@ -5,10 +5,6 @@ */ #include -#include - -#include - #include #include #include @@ -16,6 +12,8 @@ #include #include #include +#include +#include /******************************************************************************* * Platform memory map regions @@ -36,8 +34,8 @@ AML_SEC_DEVICE1_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \ - AML_TZRAM_SIZE, \ +#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \ + AML_TZRAM_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \ diff --git a/plat/amlogic/gxbb/gxbb_pm.c b/plat/amlogic/gxbb/gxbb_pm.c index ed57fee47..48bff7ba5 100644 --- a/plat/amlogic/gxbb/gxbb_pm.c +++ b/plat/amlogic/gxbb/gxbb_pm.c @@ -4,18 +4,16 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include -#include - -#include - #include +#include #include #include #include +#include #include #include #include +#include #include "aml_private.h" diff --git a/plat/amlogic/gxl/gxl_bl31_setup.c b/plat/amlogic/gxl/gxl_bl31_setup.c index 9c49646a9..f581dd134 100644 --- a/plat/amlogic/gxl/gxl_bl31_setup.c +++ b/plat/amlogic/gxl/gxl_bl31_setup.c @@ -6,12 +6,12 @@ #include #include -#include #include -#include -#include +#include #include #include +#include +#include #include "aml_private.h" diff --git a/plat/amlogic/gxl/gxl_common.c b/plat/amlogic/gxl/gxl_common.c index 631488846..468688538 100644 --- a/plat/amlogic/gxl/gxl_common.c +++ b/plat/amlogic/gxl/gxl_common.c @@ -5,15 +5,15 @@ */ #include +#include #include #include #include -#include -#include #include +#include +#include #include #include -#include /******************************************************************************* * Platform memory map regions @@ -34,8 +34,8 @@ AML_SEC_DEVICE1_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \ - AML_TZRAM_SIZE, \ +#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \ + AML_TZRAM_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \ diff --git a/plat/amlogic/gxl/gxl_pm.c b/plat/amlogic/gxl/gxl_pm.c index a3ec7d9bd..433140b77 100644 --- a/plat/amlogic/gxl/gxl_pm.c +++ b/plat/amlogic/gxl/gxl_pm.c @@ -6,14 +6,14 @@ #include #include -#include #include -#include #include +#include +#include #include +#include #include #include -#include #include "aml_private.h" -- cgit v1.2.3 From afac9681ff28d9a402b6622af94935300b42fbdf Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Thu, 12 Sep 2019 15:14:01 +0800 Subject: intel: agilex: Fix psci power domain off Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by: Hadi Asyrafi Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673 --- plat/intel/soc/agilex/socfpga_psci.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/plat/intel/soc/agilex/socfpga_psci.c b/plat/intel/soc/agilex/socfpga_psci.c index 04d8a0e91..12060ef08 100644 --- a/plat/intel/soc/agilex/socfpga_psci.c +++ b/plat/intel/soc/agilex/socfpga_psci.c @@ -61,18 +61,12 @@ int socfpga_pwr_domain_on(u_register_t mpidr) ******************************************************************************/ void socfpga_pwr_domain_off(const psci_power_state_t *target_state) { - unsigned int cpu_id = plat_my_core_pos(); - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); - /* TODO: Prevent interrupts from spuriously waking up this cpu */ - /* gicv2_cpuif_disable(); */ - - /* assert core reset */ - mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); + /* Prevent interrupts from spuriously waking up this cpu */ + gicv2_cpuif_disable(); } /******************************************************************************* -- cgit v1.2.3 From b90f207a1d386ec391bd3ea9eb403c4ad7b7551b Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 20 Aug 2019 15:33:27 +0800 Subject: Invalidate dcache build option for bl2 entry at EL3 Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: Hadi Asyrafi Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06 --- Makefile | 2 ++ docs/getting_started/user-guide.rst | 6 ++++++ include/arch/aarch64/el3_common_macros.S | 2 +- make_helpers/defaults.mk | 3 +++ plat/intel/soc/agilex/platform.mk | 1 + 5 files changed, 13 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index bcfbd65ed..ecff944f7 100644 --- a/Makefile +++ b/Makefile @@ -689,6 +689,7 @@ $(eval $(call assert_boolean,USE_TBBR_DEFS)) $(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY)) $(eval $(call assert_boolean,BL2_AT_EL3)) $(eval $(call assert_boolean,BL2_IN_XIP_MEM)) +$(eval $(call assert_boolean,BL2_INV_DCACHE)) $(eval $(call assert_numeric,ARM_ARCH_MAJOR)) $(eval $(call assert_numeric,ARM_ARCH_MINOR)) @@ -749,6 +750,7 @@ $(eval $(call add_define,USE_TBBR_DEFS)) $(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY)) $(eval $(call add_define,BL2_AT_EL3)) $(eval $(call add_define,BL2_IN_XIP_MEM)) +$(eval $(call add_define,BL2_INV_DCACHE)) ifeq (${SANITIZE_UB},trap) $(eval $(call add_define,MONITOR_TRAPS)) diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 48cbdb9f4..3828d0b4e 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -287,6 +287,12 @@ Common build options enable this use-case. For now, this option is only supported when BL2_AT_EL3 is set to '1'. +- ``BL2_INV_DCACHE``: This is an optional build option which control dcache + invalidation upon BL2 entry. Some platform cannot handle cache operations + during entry as the coherency unit is not yet initialized. This may cause + crashing. Leaving this option to '1' (default) will allow the operation. + This option is only relevant when BL2_AT_EL3 is set to '1'. + - ``BL31``: This is an optional build option which specifies the path to BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not be built. diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index a36b7da79..53396d44b 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -333,7 +333,7 @@ * --------------------------------------------------------------------- */ .if \_init_c_runtime -#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3) +#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE) /* ------------------------------------------------------------- * Invalidate the RW memory used by the BL31 image. This * includes the data and NOBITS sections. This is done to diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index e462505a2..b6f76559c 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -33,6 +33,9 @@ BL2_AT_EL3 := 0 # when BL2_AT_EL3 is 1. BL2_IN_XIP_MEM := 0 +# Do dcache invalidate upon BL2 entry at EL3 +BL2_INV_DCACHE := 1 + # Select the branch protection features to use. BRANCH_PROTECTION := 0 diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 5d20462b7..d1ea62915 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -70,5 +70,6 @@ BL31_SOURCES += \ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 +BL2_INV_DCACHE := 0 MULTI_CONSOLE_API := 1 USE_COHERENT_MEM := 1 -- cgit v1.2.3 From aacff7498c7241696f55a9b80473e59b72d4d095 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Mon, 29 Jul 2019 17:13:10 +0100 Subject: Support larger RSA key sizes when using MBEDTLS Previously, TF-A could not support large RSA key sizes as the configuration options passed to MBEDTLS prevented storing and performing calculations with the larger, higher-precision numbers required. With these changes to the arguments passed to MBEDTLS, TF-A now supports using 3072 (3K) and 4096 (4K) keys in certificates. Change-Id: Ib73a6773145d2faa25c28d04f9a42e86f2fd555f Signed-off-by: Justin Chadwell --- Makefile | 4 +++ drivers/auth/mbedtls/mbedtls_common.mk | 13 +++++++- drivers/auth/tbbr/tbbr_cot.c | 16 ++++++++++ include/drivers/auth/mbedtls/mbedtls_config.h | 45 +++++++++++++++++---------- 4 files changed, 61 insertions(+), 17 deletions(-) diff --git a/Makefile b/Makefile index bcfbd65ed..d1376e864 100644 --- a/Makefile +++ b/Makefile @@ -694,6 +694,10 @@ $(eval $(call assert_numeric,ARM_ARCH_MAJOR)) $(eval $(call assert_numeric,ARM_ARCH_MINOR)) $(eval $(call assert_numeric,BRANCH_PROTECTION)) +ifdef KEY_SIZE + $(eval $(call assert_numeric,KEY_SIZE)) +endif + ifeq ($(filter $(SANITIZE_UB), on off trap),) $(error "Invalid value for SANITIZE_UB: can be one of on, off, trap") endif diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk index 63e65bd47..f34d3d000 100644 --- a/drivers/auth/mbedtls/mbedtls_common.mk +++ b/drivers/auth/mbedtls/mbedtls_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -59,6 +59,16 @@ ifeq (${TF_MBEDTLS_KEY_ALG},) endif endif +ifeq (${TF_MBEDTLS_KEY_SIZE},) + ifneq ($(findstring rsa,${TF_MBEDTLS_KEY_ALG}),) + ifeq (${KEY_SIZE},) + TF_MBEDTLS_KEY_SIZE := 2048 + else + TF_MBEDTLS_KEY_SIZE := ${KEY_SIZE} + endif + endif +endif + ifeq (${HASH_ALG}, sha384) TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA384 else ifeq (${HASH_ALG}, sha512) @@ -79,6 +89,7 @@ endif # Needs to be set to drive mbed TLS configuration correctly $(eval $(call add_define,TF_MBEDTLS_KEY_ALG_ID)) +$(eval $(call add_define,TF_MBEDTLS_KEY_SIZE)) $(eval $(call add_define,TF_MBEDTLS_HASH_ALG_ID)) diff --git a/drivers/auth/tbbr/tbbr_cot.c b/drivers/auth/tbbr/tbbr_cot.c index da3631bbf..6dd4ae252 100644 --- a/drivers/auth/tbbr/tbbr_cot.c +++ b/drivers/auth/tbbr/tbbr_cot.c @@ -7,6 +7,7 @@ #include #include +#include #include #if USE_TBBR_DEFS @@ -19,7 +20,22 @@ /* * Maximum key and hash sizes (in DER format) */ +#if TF_MBEDTLS_USE_RSA +#if TF_MBEDTLS_KEY_SIZE == 1024 +#define PK_DER_LEN 162 +#elif TF_MBEDTLS_KEY_SIZE == 2048 #define PK_DER_LEN 294 +#elif TF_MBEDTLS_KEY_SIZE == 3072 +#define PK_DER_LEN 422 +#elif TF_MBEDTLS_KEY_SIZE == 4096 +#define PK_DER_LEN 550 +#else +#error "Invalid value for TF_MBEDTLS_KEY_SIZE" +#endif +#else +#define PK_DER_LEN 294 +#endif + #define HASH_DER_LEN 83 /* diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config.h index f7248f984..6e179bbd1 100644 --- a/include/drivers/auth/mbedtls/mbedtls_config.h +++ b/include/drivers/auth/mbedtls/mbedtls_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,11 @@ #define TF_MBEDTLS_ECDSA 2 #define TF_MBEDTLS_RSA_AND_ECDSA 3 +#define TF_MBEDTLS_USE_RSA (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA \ + || TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) +#define TF_MBEDTLS_USE_ECDSA (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA \ + || TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) + /* * Hash algorithms currently supported on mbed TLS libraries */ @@ -54,19 +59,14 @@ #define MBEDTLS_PLATFORM_C -#if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA) +#if TF_MBEDTLS_USE_ECDSA #define MBEDTLS_ECDSA_C #define MBEDTLS_ECP_C #define MBEDTLS_ECP_DP_SECP256R1_ENABLED -#elif (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA) -#define MBEDTLS_RSA_C -#define MBEDTLS_X509_RSASSA_PSS_SUPPORT -#elif (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) +#endif +#if TF_MBEDTLS_USE_RSA #define MBEDTLS_RSA_C #define MBEDTLS_X509_RSASSA_PSS_SUPPORT -#define MBEDTLS_ECDSA_C -#define MBEDTLS_ECP_C -#define MBEDTLS_ECP_DP_SECP256R1_ENABLED #endif #define MBEDTLS_SHA256_C @@ -80,11 +80,20 @@ #define MBEDTLS_X509_CRT_PARSE_C /* MPI / BIGNUM options */ -#define MBEDTLS_MPI_WINDOW_SIZE 2 -#define MBEDTLS_MPI_MAX_SIZE 256 +#define MBEDTLS_MPI_WINDOW_SIZE 2 + +#if TF_MBEDTLS_USE_RSA +#if TF_MBEDTLS_KEY_SIZE <= 2048 +#define MBEDTLS_MPI_MAX_SIZE 256 +#else +#define MBEDTLS_MPI_MAX_SIZE 512 +#endif +#else +#define MBEDTLS_MPI_MAX_SIZE 256 +#endif /* Memory buffer allocator options */ -#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8 +#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8 #ifndef __ASSEMBLER__ /* System headers required to build mbed TLS with the current configuration */ @@ -95,13 +104,17 @@ /* * Determine Mbed TLS heap size * 13312 = 13*1024 - * 7168 = 7*1024 + * 11264 = 11*1024 + * 7168 = 7*1024 */ -#if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA) \ - || (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) +#if TF_MBEDTLS_USE_ECDSA #define TF_MBEDTLS_HEAP_SIZE U(13312) -#elif (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA) +#elif TF_MBEDTLS_USE_RSA +#if TF_MBEDTLS_KEY_SIZE <= 2048 #define TF_MBEDTLS_HEAP_SIZE U(7168) +#else +#define TF_MBEDTLS_HEAP_SIZE U(11264) +#endif #endif #endif /* MBEDTLS_CONFIG_H */ -- cgit v1.2.3 From dfe0f4c2999cef10f9c8fb6115e53891f6b2c190 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Mon, 29 Jul 2019 17:13:45 +0100 Subject: Add cert_create tool support for RSA key sizes cert_tool is now able to accept a command line option for specifying the key size. It now supports the following options: 1024, 2048 (default), 3072 and 4096. This is also modifiable by TFA using the build flag KEY_SIZE. Change-Id: Ifadecf84ade3763249ee8cc7123a8178f606f0e5 Signed-off-by: Justin Chadwell --- make_helpers/tbbr/tbbr_tools.mk | 4 ++- tools/cert_create/include/key.h | 19 +++++++++++--- tools/cert_create/src/key.c | 12 ++++----- tools/cert_create/src/main.c | 56 +++++++++++++++++++++++++++++++++++++++-- 4 files changed, 78 insertions(+), 13 deletions(-) diff --git a/make_helpers/tbbr/tbbr_tools.mk b/make_helpers/tbbr/tbbr_tools.mk index afc007a4b..9c47cc7c4 100644 --- a/make_helpers/tbbr/tbbr_tools.mk +++ b/make_helpers/tbbr/tbbr_tools.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,6 +21,7 @@ # Build options added by this file: # # KEY_ALG +# KEY_SIZE # ROT_KEY # TRUSTED_WORLD_KEY # NON_TRUSTED_WORLD_KEY @@ -52,6 +53,7 @@ $(eval $(call TOOL_ADD_PAYLOAD,${FWU_CERT},--fwu-cert,,FWU_)) # packed in the FIP). Developers can use their own keys by specifying the proper # build option in the command line when building the Trusted Firmware $(if ${KEY_ALG},$(eval $(call CERT_ADD_CMD_OPT,${KEY_ALG},--key-alg))) +$(if ${KEY_SIZE},$(eval $(call CERT_ADD_CMD_OPT,${KEY_SIZE},--key-size))) $(if ${HASH_ALG},$(eval $(call CERT_ADD_CMD_OPT,${HASH_ALG},--hash-alg))) $(if ${ROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${ROT_KEY},--rot-key))) $(if ${ROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${ROT_KEY},--rot-key,FWU_))) diff --git a/tools/cert_create/include/key.h b/tools/cert_create/include/key.h index 310a77f3e..c08beb8b2 100644 --- a/tools/cert_create/include/key.h +++ b/tools/cert_create/include/key.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +9,6 @@ #include -#define RSA_KEY_BITS 2048 - /* Error codes */ enum { KEY_ERR_NONE, @@ -30,6 +28,9 @@ enum { KEY_ALG_MAX_NUM }; +/* Maximum number of valid key sizes per algorithm */ +#define KEY_SIZE_MAX_NUM 4 + /* Supported hash algorithms */ enum{ HASH_ALG_SHA256, @@ -37,6 +38,16 @@ enum{ HASH_ALG_SHA512, }; +/* Supported key sizes */ +/* NOTE: the first item in each array is the default key size */ +static const unsigned int KEY_SIZES[KEY_ALG_MAX_NUM][KEY_SIZE_MAX_NUM] = { + { 2048, 1024, 3072, 4096 }, /* KEY_ALG_RSA */ + { 2048, 1024, 3072, 4096 }, /* KEY_ALG_RSA_1_5 */ +#ifndef OPENSSL_NO_EC + {} /* KEY_ALG_ECDSA */ +#endif /* OPENSSL_NO_EC */ +}; + /* * This structure contains the relevant information to create the keys * required to sign the certificates. @@ -58,7 +69,7 @@ typedef struct key_s { int key_init(void); key_t *key_get_by_opt(const char *opt); int key_new(key_t *key); -int key_create(key_t *key, int type); +int key_create(key_t *key, int type, int key_bits); int key_load(key_t *key, unsigned int *err_code); int key_store(key_t *key); diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c index fece77085..93d31f7c3 100644 --- a/tools/cert_create/src/key.c +++ b/tools/cert_create/src/key.c @@ -41,7 +41,7 @@ int key_new(key_t *key) return 1; } -static int key_create_rsa(key_t *key) +static int key_create_rsa(key_t *key, int key_bits) { BIGNUM *e; RSA *rsa = NULL; @@ -63,7 +63,7 @@ static int key_create_rsa(key_t *key) goto err; } - if (!RSA_generate_key_ex(rsa, RSA_KEY_BITS, e, NULL)) { + if (!RSA_generate_key_ex(rsa, key_bits, e, NULL)) { printf("Cannot generate RSA key\n"); goto err; } @@ -82,7 +82,7 @@ err: } #ifndef OPENSSL_NO_EC -static int key_create_ecdsa(key_t *key) +static int key_create_ecdsa(key_t *key, int key_bits) { EC_KEY *ec; @@ -109,7 +109,7 @@ err: } #endif /* OPENSSL_NO_EC */ -typedef int (*key_create_fn_t)(key_t *key); +typedef int (*key_create_fn_t)(key_t *key, int key_bits); static const key_create_fn_t key_create_fn[KEY_ALG_MAX_NUM] = { key_create_rsa, /* KEY_ALG_RSA */ key_create_rsa, /* KEY_ALG_RSA_1_5 */ @@ -118,7 +118,7 @@ static const key_create_fn_t key_create_fn[KEY_ALG_MAX_NUM] = { #endif /* OPENSSL_NO_EC */ }; -int key_create(key_t *key, int type) +int key_create(key_t *key, int type, int key_bits) { if (type >= KEY_ALG_MAX_NUM) { printf("Invalid key type\n"); @@ -126,7 +126,7 @@ int key_create(key_t *key, int type) } if (key_create_fn[type]) { - return key_create_fn[type](key); + return key_create_fn[type](key, key_bits); } return 0; diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c index 0f588cc8c..44a65eb98 100644 --- a/tools/cert_create/src/main.c +++ b/tools/cert_create/src/main.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -69,6 +70,7 @@ /* Global options */ static int key_alg; static int hash_alg; +static int key_size; static int new_keys; static int save_keys; static int print_cert; @@ -155,6 +157,18 @@ static int get_key_alg(const char *key_alg_str) return -1; } +static int get_key_size(const char *key_size_str) +{ + char *end; + long key_size; + + key_size = strtol(key_size_str, &end, 10); + if (*end != '\0') + return -1; + + return key_size; +} + static int get_hash_alg(const char *hash_alg_str) { int i; @@ -174,6 +188,7 @@ static void check_cmd_params(void) ext_t *ext; key_t *key; int i, j; + bool valid_size; /* Only save new keys */ if (save_keys && !new_keys) { @@ -181,6 +196,26 @@ static void check_cmd_params(void) exit(1); } + /* Validate key-size */ + valid_size = false; + for (i = 0; i < KEY_SIZE_MAX_NUM; i++) { + if (key_size == KEY_SIZES[key_alg][i]) { + valid_size = true; + break; + } + } + if (!valid_size) { + ERROR("'%d' is not a valid key size for '%s'\n", + key_size, key_algs_str[key_alg]); + NOTICE("Valid sizes are: "); + for (i = 0; i < KEY_SIZE_MAX_NUM && + KEY_SIZES[key_alg][i] != 0; i++) { + printf("%d ", KEY_SIZES[key_alg][i]); + } + printf("\n"); + exit(1); + } + /* Check that all required options have been specified in the * command line */ for (i = 0; i < num_certs; i++) { @@ -245,6 +280,10 @@ static const cmd_opt_t common_cmd_opt[] = { "Key algorithm: 'rsa' (default) - RSAPSS scheme as per \ PKCS#1 v2.1, 'rsa_1_5' - RSA PKCS#1 v1.5, 'ecdsa'" }, + { + { "key-size", required_argument, NULL, 'b' }, + "Key size (for supported algorithms)." + }, { { "hash-alg", required_argument, NULL, 's' }, "Hash algorithm : 'sha256' (default), 'sha384', 'sha512'" @@ -286,6 +325,7 @@ int main(int argc, char *argv[]) /* Set default options */ key_alg = KEY_ALG_RSA; hash_alg = HASH_ALG_SHA256; + key_size = -1; /* Add common command line options */ for (i = 0; i < NUM_ELEM(common_cmd_opt); i++) { @@ -315,7 +355,7 @@ int main(int argc, char *argv[]) while (1) { /* getopt_long stores the option index here. */ - c = getopt_long(argc, argv, "a:hknps:", cmd_opt, &opt_idx); + c = getopt_long(argc, argv, "a:b:hknps:", cmd_opt, &opt_idx); /* Detect the end of the options. */ if (c == -1) { @@ -330,6 +370,13 @@ int main(int argc, char *argv[]) exit(1); } break; + case 'b': + key_size = get_key_size(optarg); + if (key_size <= 0) { + ERROR("Invalid key size '%s'\n", optarg); + exit(1); + } + break; case 'h': print_help(argv[0], cmd_opt); exit(0); @@ -371,6 +418,11 @@ int main(int argc, char *argv[]) } } + /* Select a reasonable default key-size */ + if (key_size == -1) { + key_size = KEY_SIZES[key_alg][0]; + } + /* Check command line arguments */ check_cmd_params(); @@ -413,7 +465,7 @@ int main(int argc, char *argv[]) if (new_keys) { /* Try to create a new key */ NOTICE("Creating new key for '%s'\n", keys[i].desc); - if (!key_create(&keys[i], key_alg)) { + if (!key_create(&keys[i], key_alg, key_size)) { ERROR("Error creating key '%s'\n", keys[i].desc); exit(1); } -- cgit v1.2.3 From f29213d9e3c82f8b43e42023d5b39e097d86ff18 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Mon, 29 Jul 2019 17:18:21 +0100 Subject: Add documentation for new KEY_SIZE option This patch adds documentation for the new KEY_SIZE build option that is exposed by cert_create, and instructions on how to use it. Change-Id: I09b9b052bfdeeaca837e0f0026e2b01144f2472c Signed-off-by: Justin Chadwell --- docs/design/auth-framework.rst | 18 +++++++++++------- docs/getting_started/user-guide.rst | 12 ++++++++++++ 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/docs/design/auth-framework.rst b/docs/design/auth-framework.rst index da958b7c2..7de8ee1e2 100644 --- a/docs/design/auth-framework.rst +++ b/docs/design/auth-framework.rst @@ -704,7 +704,7 @@ Each image descriptor must specify: In the ``tbbr_cot.c`` file, a set of buffers are allocated to store the parameters extracted from the certificates. In the case of the TBBR CoT, these parameters -are hashes and public keys. In DER format, an RSA-2048 public key requires 294 +are hashes and public keys. In DER format, an RSA-4096 public key requires 550 bytes, and a hash requires 51 bytes. Depending on the CoT and the authentication process, some of the buffers may be reused at different stages during the boot. @@ -946,12 +946,16 @@ three functions: int verify_hash(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); -The mbedTLS library algorithm support is configured by the -``TF_MBEDTLS_KEY_ALG`` variable which can take in 3 values: `rsa`, `ecdsa` or -`rsa+ecdsa`. This variable allows the Makefile to include the corresponding -sources in the build for the various algorithms. Setting the variable to -`rsa+ecdsa` enables support for both rsa and ecdsa algorithms in the mbedTLS -library. +The mbedTLS library algorithm support is configured by both the +``TF_MBEDTLS_KEY_ALG`` and ``TF_MBEDTLS_KEY_SIZE`` variables. + +- ``TF_MBEDTLS_KEY_ALG`` can take in 3 values: `rsa`, `ecdsa` or `rsa+ecdsa`. + This variable allows the Makefile to include the corresponding sources in + the build for the various algorithms. Setting the variable to `rsa+ecdsa` + enables support for both rsa and ecdsa algorithms in the mbedTLS library. + +- ``TF_MBEDTLS_KEY_SIZE`` sets the supported RSA key size for TFA. Valid values + include 1024, 2048, 3072 and 4096. .. note:: If code size is a concern, the build option ``MBEDTLS_SHA256_SMALLER`` can diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 48cbdb9f4..89157386e 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -593,6 +593,18 @@ Common build options compliant and is retained only for compatibility. The default value of this flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. +- ``KEY_SIZE``: This build flag enables the user to select the key size for + the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` + depend on the chosen algorithm. + + +-----------+------------------------------------+ + | KEY_ALG | Possible key sizes | + +===========+====================================+ + | rsa | 1024, 2048 (default), 3072, 4096 | + +-----------+------------------------------------+ + | ecdsa | unavailable | + +-----------+------------------------------------+ + - ``HASH_ALG``: This build flag enables the user to select the secure hash algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. The default value of this flag is ``sha256``. -- cgit v1.2.3 From 6a415a508ea6acec321e4609d3f8e5c03ba67664 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Mon, 9 Sep 2019 15:24:31 +0100 Subject: Remove RSA PKCS#1 v1.5 support from cert_tool Support for PKCS#1 v1.5 was deprecated in SHA 1001202 and fully removed in SHA fe199e3, however, cert_tool is still able to generate certificates in that form. This patch fully removes the ability for cert_tool to generate these certificates. Additionally, this patch also fixes a bug where the issuing certificate was a RSA and the issued certificate was EcDSA. In this case, the issued certificate would be signed using PKCS#1 v1.5 instead of RSAPSS per PKCS#1 v2.1, preventing TF-A from verifying the image signatures. Now that PKCS#1 v1.5 support is removed, all certificates that are signed with RSA now use the more modern padding scheme. Change-Id: Id87d7d915be594a1876a73080528d968e65c4e9a Signed-off-by: Justin Chadwell --- docs/getting_started/user-guide.rst | 6 ++---- drivers/auth/mbedtls/mbedtls_common.mk | 6 +++--- tools/cert_create/include/cert.h | 3 +-- tools/cert_create/include/key.h | 2 -- tools/cert_create/src/cert.c | 9 ++++----- tools/cert_create/src/key.c | 1 - tools/cert_create/src/main.c | 6 ++---- 7 files changed, 12 insertions(+), 21 deletions(-) diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 89157386e..1229e663a 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -588,10 +588,8 @@ Common build options - ``KEY_ALG``: This build flag enables the user to select the algorithm to be used for generating the PKCS keys and subsequent signing of the certificate. - It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option - ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR - compliant and is retained only for compatibility. The default value of this - flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. + It accepts 2 values: ``rsa`` and ``ecdsa``. The default value of this flag + is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. - ``KEY_SIZE``: This build flag enables the user to select the key size for the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk index f34d3d000..4b8301541 100644 --- a/drivers/auth/mbedtls/mbedtls_common.mk +++ b/drivers/auth/mbedtls/mbedtls_common.mk @@ -48,9 +48,9 @@ LIBMBEDTLS_SRCS := $(addprefix ${MBEDTLS_DIR}/library/, \ ) # The platform may define the variable 'TF_MBEDTLS_KEY_ALG' to select the key -# algorithm to use. If the variable is not defined, select it based on algorithm -# used for key generation `KEY_ALG`. If `KEY_ALG` is not defined or is -# defined to `rsa`/`rsa_1_5`, then set the variable to `rsa`. +# algorithm to use. If the variable is not defined, select it based on +# algorithm used for key generation `KEY_ALG`. If `KEY_ALG` is not defined, +# then it is set to `rsa`. ifeq (${TF_MBEDTLS_KEY_ALG},) ifeq (${KEY_ALG}, ecdsa) TF_MBEDTLS_KEY_ALG := ecdsa diff --git a/tools/cert_create/include/cert.h b/tools/cert_create/include/cert.h index 39b45b58e..6db9b579d 100644 --- a/tools/cert_create/include/cert.h +++ b/tools/cert_create/include/cert.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -49,7 +49,6 @@ int cert_init(void); cert_t *cert_get_by_opt(const char *opt); int cert_add_ext(X509 *issuer, X509 *subject, int nid, char *value); int cert_new( - int key_alg, int md_alg, cert_t *cert, int days, diff --git a/tools/cert_create/include/key.h b/tools/cert_create/include/key.h index c08beb8b2..d96d9839a 100644 --- a/tools/cert_create/include/key.h +++ b/tools/cert_create/include/key.h @@ -21,7 +21,6 @@ enum { /* Supported key algorithms */ enum { KEY_ALG_RSA, /* RSA PSS as defined by PKCS#1 v2.1 (default) */ - KEY_ALG_RSA_1_5, /* RSA as defined by PKCS#1 v1.5 */ #ifndef OPENSSL_NO_EC KEY_ALG_ECDSA, #endif /* OPENSSL_NO_EC */ @@ -42,7 +41,6 @@ enum{ /* NOTE: the first item in each array is the default key size */ static const unsigned int KEY_SIZES[KEY_ALG_MAX_NUM][KEY_SIZE_MAX_NUM] = { { 2048, 1024, 3072, 4096 }, /* KEY_ALG_RSA */ - { 2048, 1024, 3072, 4096 }, /* KEY_ALG_RSA_1_5 */ #ifndef OPENSSL_NO_EC {} /* KEY_ALG_ECDSA */ #endif /* OPENSSL_NO_EC */ diff --git a/tools/cert_create/src/cert.c b/tools/cert_create/src/cert.c index 8e8aee699..c68a265b4 100644 --- a/tools/cert_create/src/cert.c +++ b/tools/cert_create/src/cert.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -93,7 +93,6 @@ int cert_add_ext(X509 *issuer, X509 *subject, int nid, char *value) } int cert_new( - int key_alg, int md_alg, cert_t *cert, int days, @@ -143,10 +142,10 @@ int cert_new( } /* - * Set additional parameters if algorithm is RSA PSS. This is not - * required for RSA 1.5 or ECDSA. + * Set additional parameters if issuing public key algorithm is RSA. + * This is not required for ECDSA. */ - if (key_alg == KEY_ALG_RSA) { + if (EVP_PKEY_base_id(ikey) == EVP_PKEY_RSA) { if (!EVP_PKEY_CTX_set_rsa_padding(pKeyCtx, RSA_PKCS1_PSS_PADDING)) { ERR_print_errors_fp(stdout); goto END; diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c index 93d31f7c3..0f80cce9b 100644 --- a/tools/cert_create/src/key.c +++ b/tools/cert_create/src/key.c @@ -112,7 +112,6 @@ err: typedef int (*key_create_fn_t)(key_t *key, int key_bits); static const key_create_fn_t key_create_fn[KEY_ALG_MAX_NUM] = { key_create_rsa, /* KEY_ALG_RSA */ - key_create_rsa, /* KEY_ALG_RSA_1_5 */ #ifndef OPENSSL_NO_EC key_create_ecdsa, /* KEY_ALG_ECDSA */ #endif /* OPENSSL_NO_EC */ diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c index 44a65eb98..0cbd2196b 100644 --- a/tools/cert_create/src/main.c +++ b/tools/cert_create/src/main.c @@ -92,7 +92,6 @@ static char *strdup(const char *str) static const char *key_algs_str[] = { [KEY_ALG_RSA] = "rsa", - [KEY_ALG_RSA_1_5] = "rsa_1_5", #ifndef OPENSSL_NO_EC [KEY_ALG_ECDSA] = "ecdsa" #endif /* OPENSSL_NO_EC */ @@ -277,8 +276,7 @@ static const cmd_opt_t common_cmd_opt[] = { }, { { "key-alg", required_argument, NULL, 'a' }, - "Key algorithm: 'rsa' (default) - RSAPSS scheme as per \ -PKCS#1 v2.1, 'rsa_1_5' - RSA PKCS#1 v1.5, 'ecdsa'" + "Key algorithm: 'rsa' (default)- RSAPSS scheme as per PKCS#1 v2.1, 'ecdsa'" }, { { "key-size", required_argument, NULL, 'b' }, @@ -545,7 +543,7 @@ int main(int argc, char *argv[]) } /* Create certificate. Signed with corresponding key */ - if (cert->fn && !cert_new(key_alg, hash_alg, cert, VAL_DAYS, 0, sk)) { + if (cert->fn && !cert_new(hash_alg, cert, VAL_DAYS, 0, sk)) { ERROR("Cannot create %s\n", cert->cn); exit(1); } -- cgit v1.2.3 From d1d06275e91ec4c48eade30eb09bc0d9f1d21299 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Thu, 2 May 2019 20:33:58 +0800 Subject: mediatek: mt8173: apply MULTI_CONSOLE framework - Switch uart driver from Mediatek 8250 to TI 16550 - Enable MULTI_CONSOLE Signed-off-by: kenny liang Change-Id: Ie3948d9e64d05d29a1f69592792e277b680c4ed4 --- plat/mediatek/mt8173/aarch64/plat_helpers.S | 42 ----------------------------- plat/mediatek/mt8173/bl31_plat_setup.c | 6 +++-- plat/mediatek/mt8173/plat_pm.c | 6 +++-- plat/mediatek/mt8173/platform.mk | 9 ++++--- 4 files changed, 13 insertions(+), 50 deletions(-) diff --git a/plat/mediatek/mt8173/aarch64/plat_helpers.S b/plat/mediatek/mt8173/aarch64/plat_helpers.S index 983ebe3da..095dfc505 100644 --- a/plat/mediatek/mt8173/aarch64/plat_helpers.S +++ b/plat/mediatek/mt8173/aarch64/plat_helpers.S @@ -11,9 +11,6 @@ .globl plat_report_exception .globl platform_is_primary_cpu .globl plat_my_core_pos - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl plat_crash_console_flush /* ----------------------------------------------------- * void plat_secondary_cold_boot_setup (void); @@ -50,42 +47,3 @@ func plat_my_core_pos add x0, x1, x0, LSR #6 ret endfunc plat_my_core_pos - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * Function to initialize the crash console - * without a C Runtime to print crash report. - * Clobber list : x0 - x4 - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, MT8173_UART0_BASE - mov_imm x1, MT8173_UART_CLOCK - mov_imm x2, MT8173_BAUDRATE - b console_core_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(void) - * Function to print a character on the crash - * console without a C Runtime. - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, MT8173_UART0_BASE - b console_core_putc -endfunc plat_crash_console_putc - - /* --------------------------------------------- - * int plat_crash_console_flush(int c) - * Function to force a write of all buffered - * data that hasn't been output. - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func plat_crash_console_flush - mov_imm x0, MT8173_UART0_BASE - b console_core_flush -endfunc plat_crash_console_flush diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index ad81b1695..73a479b50 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -9,8 +9,8 @@ #include #include #include -#include #include +#include #include #include #include @@ -100,7 +100,9 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); + static console_16550_t console; + + console_16550_register(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE, &console); VERBOSE("bl31_setup\n"); diff --git a/plat/mediatek/mt8173/plat_pm.c b/plat/mediatek/mt8173/plat_pm.c index 1b52470d5..c8d45993f 100644 --- a/plat/mediatek/mt8173/plat_pm.c +++ b/plat/mediatek/mt8173/plat_pm.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include @@ -543,12 +543,14 @@ int plat_validate_power_state(unsigned int power_state, void mtk_system_pwr_domain_resume(void) { - console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); + console_switch_state(CONSOLE_FLAG_BOOT); /* Assert system power domain is available on the platform */ assert(PLAT_MAX_PWR_LVL >= MTK_PWR_LVL2); plat_arm_gic_init(); + + console_switch_state(CONSOLE_FLAG_RUNTIME); } static const plat_psci_ops_t plat_plat_pm_ops = { diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk index 24e4ec650..e5eca9fcc 100644 --- a/plat/mediatek/mt8173/platform.mk +++ b/plat/mediatek/mt8173/platform.mk @@ -8,7 +8,6 @@ MTK_PLAT := plat/mediatek MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ - -I${MTK_PLAT}/common/drivers/uart/ \ -Iinclude/plat/arm/common/aarch64 \ -I${MTK_PLAT_SOC}/drivers/crypt/ \ -I${MTK_PLAT_SOC}/drivers/mtcmos/ \ @@ -21,21 +20,21 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ lib/xlat_tables/aarch64/xlat_tables.c \ plat/arm/common/arm_gicv2.c \ - plat/common/plat_gicv2.c + plat/common/plat_gicv2.c \ + plat/common/aarch64/crash_console_helpers.S BL31_SOURCES += common/desc_image_load.c \ drivers/arm/cci/cci.c \ drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/v2/gicv2_helpers.c \ - drivers/console/aarch64/console.S \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ + drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a72.S \ - ${MTK_PLAT}/common/drivers/uart/8250_console.S \ ${MTK_PLAT}/common/mtk_plat_common.c \ ${MTK_PLAT}/common/mtk_sip_svc.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ @@ -68,3 +67,5 @@ $(eval $(call add_define,MTK_SIP_SET_AUTHORIZED_SECURE_REG_ENABLE)) # Do not enable SVE ENABLE_SVE_FOR_NS := 0 + +MULTI_CONSOLE_API := 1 -- cgit v1.2.3 From a759d34519d4206dfe0a86389317c4b371850aa7 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Thu, 5 Sep 2019 12:27:39 +0100 Subject: amlogic: console: Move console driver to common directory The code managing the console is the same for all the platforms currently supported. Since it is unlikely to change in the future move the code to an external file in the common directory. Signed-off-by: Carlo Caione Change-Id: I6df555ea82d483b4f08a4a1e2cb0a7488fbaa015 --- plat/amlogic/common/aml_console.c | 33 +++++++++++++++++++++++++++++++++ plat/amlogic/gxbb/gxbb_common.c | 26 -------------------------- plat/amlogic/gxbb/platform.mk | 1 + plat/amlogic/gxl/gxl_common.c | 26 -------------------------- plat/amlogic/gxl/platform.mk | 1 + 5 files changed, 35 insertions(+), 52 deletions(-) create mode 100644 plat/amlogic/common/aml_console.c diff --git a/plat/amlogic/common/aml_console.c b/plat/amlogic/common/aml_console.c new file mode 100644 index 000000000..352279b6c --- /dev/null +++ b/plat/amlogic/common/aml_console.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2019, Carlo Caione + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +/******************************************************************************* + * Function that sets up the console + ******************************************************************************/ +static console_meson_t aml_console; + +void aml_console_init(void) +{ + int rc = console_meson_register(AML_UART0_AO_BASE, + AML_UART0_AO_CLK_IN_HZ, + AML_UART_BAUDRATE, + &aml_console); + if (rc == 0) { + /* + * The crash console doesn't use the multi console API, it uses + * the core console functions directly. It is safe to call panic + * and let it print debug information. + */ + panic(); + } + + console_set_scope(&aml_console.console, + CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); +} diff --git a/plat/amlogic/gxbb/gxbb_common.c b/plat/amlogic/gxbb/gxbb_common.c index e98748e77..260a347ab 100644 --- a/plat/amlogic/gxbb/gxbb_common.c +++ b/plat/amlogic/gxbb/gxbb_common.c @@ -7,9 +7,7 @@ #include #include #include -#include #include -#include #include #include #include @@ -100,30 +98,6 @@ void aml_setup_page_tables(void) init_xlat_tables(); } -/******************************************************************************* - * Function that sets up the console - ******************************************************************************/ -static console_meson_t gxbb_console; - -void aml_console_init(void) -{ - int rc = console_meson_register(AML_UART0_AO_BASE, - AML_UART0_AO_CLK_IN_HZ, - AML_UART_BAUDRATE, - &gxbb_console); - if (rc == 0) { - /* - * The crash console doesn't use the multi console API, it uses - * the core console functions directly. It is safe to call panic - * and let it print debug information. - */ - panic(); - } - - console_set_scope(&gxbb_console.console, - CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); -} - /******************************************************************************* * Function that returns the system counter frequency ******************************************************************************/ diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk index 59c4f3d63..57167b077 100644 --- a/plat/amlogic/gxbb/platform.mk +++ b/plat/amlogic/gxbb/platform.mk @@ -32,6 +32,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${AML_PLAT_COMMON}/aml_sip_svc.c \ ${AML_PLAT_COMMON}/aml_thermal.c \ ${AML_PLAT_COMMON}/aml_topology.c \ + ${AML_PLAT_COMMON}/aml_console.c \ ${XLAT_TABLES_LIB_SRCS} \ ${GIC_SOURCES} diff --git a/plat/amlogic/gxl/gxl_common.c b/plat/amlogic/gxl/gxl_common.c index 468688538..e1d7bfb92 100644 --- a/plat/amlogic/gxl/gxl_common.c +++ b/plat/amlogic/gxl/gxl_common.c @@ -7,11 +7,9 @@ #include #include #include -#include #include #include #include -#include #include #include @@ -100,30 +98,6 @@ void aml_setup_page_tables(void) init_xlat_tables(); } -/******************************************************************************* - * Function that sets up the console - ******************************************************************************/ -static console_meson_t gxl_console; - -void aml_console_init(void) -{ - int rc = console_meson_register(AML_UART0_AO_BASE, - AML_UART0_AO_CLK_IN_HZ, - AML_UART_BAUDRATE, - &gxl_console); - if (rc == 0) { - /* - * The crash console doesn't use the multi console API, it uses - * the core console functions directly. It is safe to call panic - * and let it print debug information. - */ - panic(); - } - - console_set_scope(&gxl_console.console, - CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); -} - /******************************************************************************* * Function that returns the system counter frequency ******************************************************************************/ diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index 80c991ced..2e47670f0 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -35,6 +35,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${AML_PLAT_COMMON}/aml_sip_svc.c \ ${AML_PLAT_COMMON}/aml_thermal.c \ ${AML_PLAT_COMMON}/aml_topology.c \ + ${AML_PLAT_COMMON}/aml_console.c \ drivers/amlogic/crypto/sha_dma.c \ ${XLAT_TABLES_LIB_SRCS} \ ${GIC_SOURCES} -- cgit v1.2.3 From fc81021aedf01a922686bc9fa22de411ec80592b Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Tue, 27 Aug 2019 00:32:24 +0300 Subject: Unify type of "cpu_idx" across PSCI module. cpu_idx is used as mix of `unsigned int` and `signed int` in code with typecasting at some places. This change is to unify the cpu_idx as `unsigned int` as underlying API;s `plat_my_core_pos` returns `unsigned int` It was discovered via coverity issue CID 354715 Signed-off-by: Deepika Bhavnani Change-Id: I4f0adb0c596ff1177210c5fe803bff853f2e54ce --- lib/psci/psci_common.c | 17 +++++++++-------- lib/psci/psci_private.h | 19 ++++++++++--------- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 022c87751..3bfa06852 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -159,9 +159,10 @@ void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info) ******************************************************************************/ unsigned int psci_is_last_on_cpu(void) { - int cpu_idx, my_idx = (int) plat_my_core_pos(); + unsigned int cpu_idx, my_idx = plat_my_core_pos(); - for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { + for (cpu_idx = 0; cpu_idx < (unsigned int)PLATFORM_CORE_COUNT; + cpu_idx++) { if (cpu_idx == my_idx) { assert(psci_get_aff_info_state() == AFF_STATE_ON); continue; @@ -206,7 +207,7 @@ static void psci_set_req_local_pwr_state(unsigned int pwrlvl, { assert(pwrlvl > PSCI_CPU_PWR_LVL); if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && - (cpu_idx < PLATFORM_CORE_COUNT)) { + (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) { psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state; } } @@ -237,12 +238,12 @@ void __init psci_init_req_local_pwr_states(void) * assertion is added to prevent us from accessing the CPU power level. *****************************************************************************/ static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, - int cpu_idx) + unsigned int cpu_idx) { assert(pwrlvl > PSCI_CPU_PWR_LVL); if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && - (cpu_idx < PLATFORM_CORE_COUNT)) { + (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) { return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx]; } else return NULL; @@ -351,7 +352,7 @@ static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl, /******************************************************************************* * PSCI helper function to get the parent nodes corresponding to a cpu_index. ******************************************************************************/ -void psci_get_parent_pwr_domain_nodes(int cpu_idx, +void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, unsigned int end_lvl, unsigned int *node_index) { @@ -417,7 +418,7 @@ void psci_do_state_coordination(unsigned int end_pwrlvl, psci_power_state_t *state_info) { unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); - int start_idx; + unsigned int start_idx; unsigned int ncpus; plat_local_state_t target_state, *req_states; @@ -763,7 +764,7 @@ int psci_validate_entry_point(entry_point_info_t *ep, void psci_warmboot_entrypoint(void) { unsigned int end_pwrlvl; - int cpu_idx = (int) plat_my_core_pos(); + unsigned int cpu_idx = plat_my_core_pos(); unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h index bbcc5cfe7..b49847c95 100644 --- a/lib/psci/psci_private.h +++ b/lib/psci/psci_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -55,16 +55,16 @@ static inline aff_info_state_t psci_get_aff_info_state(void) return get_cpu_data(psci_svc_cpu_data.aff_info_state); } -static inline aff_info_state_t psci_get_aff_info_state_by_idx(int idx) +static inline aff_info_state_t psci_get_aff_info_state_by_idx(unsigned int idx) { - return get_cpu_data_by_index((unsigned int)idx, + return get_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state); } -static inline void psci_set_aff_info_state_by_idx(int idx, +static inline void psci_set_aff_info_state_by_idx(unsigned int idx, aff_info_state_t aff_state) { - set_cpu_data_by_index((unsigned int)idx, + set_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state, aff_state); } @@ -88,9 +88,10 @@ static inline plat_local_state_t psci_get_cpu_local_state(void) return get_cpu_data(psci_svc_cpu_data.local_state); } -static inline plat_local_state_t psci_get_cpu_local_state_by_idx(int idx) +static inline plat_local_state_t psci_get_cpu_local_state_by_idx( + unsigned int idx) { - return get_cpu_data_by_index((unsigned int)idx, + return get_cpu_data_by_index(idx, psci_svc_cpu_data.local_state); } @@ -113,7 +114,7 @@ typedef struct non_cpu_pwr_domain_node { * Index of the first CPU power domain node level 0 which has this node * as its parent. */ - int cpu_start_idx; + unsigned int cpu_start_idx; /* * Number of CPU power domains which are siblings of the domain indexed @@ -269,7 +270,7 @@ void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, psci_power_state_t *target_state); int psci_validate_entry_point(entry_point_info_t *ep, uintptr_t entrypoint, u_register_t context_id); -void psci_get_parent_pwr_domain_nodes(int cpu_idx, +void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, unsigned int end_lvl, unsigned int *node_index); void psci_do_state_coordination(unsigned int end_pwrlvl, -- cgit v1.2.3 From ed108b56051de5da8024568a06781ce287e86c78 Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Fri, 13 Sep 2019 14:11:59 +0100 Subject: Refactor ARMv8.3 Pointer Authentication support code This patch provides the following features and makes modifications listed below: - Individual APIAKey key generation for each CPU. - New key generation on every BL31 warm boot and TSP CPU On event. - Per-CPU storage of APIAKey added in percpu_data[] of cpu_data structure. - `plat_init_apiakey()` function replaced with `plat_init_apkey()` which returns 128-bit value and uses Generic timer physical counter value to increase the randomness of the generated key. The new function can be used for generation of all ARMv8.3-PAuth keys - ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`. - New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively; pauth_disable_el1()` and `pauth_disable_el3()` functions disable PAuth for EL1 and EL3 respectively; `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from cpu-data structure. - Combined `save_gp_pauth_registers()` function replaces calls to `save_gp_registers()` and `pauth_context_save()`; `restore_gp_pauth_registers()` replaces `pauth_context_restore()` and `restore_gp_registers()` calls. - `restore_gp_registers_eret()` function removed with corresponding code placed in `el3_exit()`. - Fixed the issue when `pauth_t pauth_ctx` structure allocated space for 12 uint64_t PAuth registers instead of 10 by removal of macro CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h` and assigning its value to CTX_PAUTH_REGS_END. - Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions in `msr spsel` instruction instead of hard-coded values. - Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI. Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211 Signed-off-by: Alexei Fedorov --- bl1/aarch64/bl1_entrypoint.S | 19 +- bl1/aarch64/bl1_exceptions.S | 17 +- bl1/bl1_main.c | 19 +- bl2/aarch64/bl2_el3_entrypoint.S | 25 +- bl2/aarch64/bl2_entrypoint.S | 15 +- bl2/bl2_main.c | 54 ++-- bl31/aarch64/bl31_entrypoint.S | 32 +-- bl31/aarch64/ea_delegate.S | 40 +-- bl31/aarch64/runtime_exceptions.S | 57 ++-- bl31/bl31_main.c | 17 +- bl32/tsp/aarch64/tsp_entrypoint.S | 24 +- bl32/tsp/tsp_main.c | 20 +- common/bl_common.c | 50 ---- docs/getting_started/porting-guide.rst | 12 +- docs/getting_started/user-guide.rst | 6 +- include/arch/aarch64/arch_features.h | 8 - include/lib/el3_runtime/aarch64/context.h | 3 +- include/lib/el3_runtime/cpu_data.h | 39 ++- include/lib/extensions/pauth.h | 18 ++ include/plat/common/platform.h | 1 - lib/el3_runtime/aarch64/context.S | 445 +++++++++++++----------------- lib/extensions/pauth/pauth_helpers.S | 117 ++++++++ lib/psci/psci_setup.c | 8 +- lib/psci/psci_suspend.c | 8 +- plat/arm/common/aarch64/arm_pauth.c | 28 +- plat/arm/common/arm_common.mk | 3 +- readme.rst | 4 +- 27 files changed, 535 insertions(+), 554 deletions(-) create mode 100644 include/lib/extensions/pauth.h create mode 100644 lib/extensions/pauth/pauth_helpers.S diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index 0f8d5aaca..855add347 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -38,15 +38,12 @@ func bl1_entrypoint */ bl bl1_setup +#if ENABLE_PAUTH /* -------------------------------------------------------------------- - * Enable pointer authentication + * Program APIAKey_EL1 and enable pointer authentication. * -------------------------------------------------------------------- */ -#if ENABLE_PAUTH - mrs x0, sctlr_el3 - orr x0, x0, #SCTLR_EnIA_BIT - msr sctlr_el3, x0 - isb + bl pauth_init_enable_el3 #endif /* ENABLE_PAUTH */ /* -------------------------------------------------------------------- @@ -56,16 +53,12 @@ func bl1_entrypoint */ bl bl1_main +#if ENABLE_PAUTH /* -------------------------------------------------------------------- - * Disable pointer authentication before jumping to BL31 or that will - * cause an authentication failure during the early platform init. + * Disable pointer authentication before jumping to next boot image. * -------------------------------------------------------------------- */ -#if ENABLE_PAUTH - mrs x0, sctlr_el3 - bic x0, x0, #SCTLR_EnIA_BIT - msr sctlr_el3, x0 - isb + bl pauth_disable_el3 #endif /* ENABLE_PAUTH */ /* -------------------------------------------------- diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index ed7c27a18..3e72e39f2 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -164,7 +164,7 @@ func smc_handler64 * ---------------------------------------------- */ ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] - msr spsel, #0 + msr spsel, #MODE_SP_EL0 mov sp, x30 /* --------------------------------------------------------------------- @@ -217,19 +217,14 @@ unexpected_sync_exception: */ smc_handler: /* ----------------------------------------------------- - * Save the GP registers x0-x29. - * TODO: Revisit to store only SMCCC specified registers. - * ----------------------------------------------------- - */ - bl save_gp_registers - - /* ----------------------------------------------------- + * Save x0-x29 and ARMv8.3-PAuth (if enabled) registers. * If Secure Cycle Counter is not disabled in MDCR_EL3 * when ARMv8.5-PMU is implemented, save PMCR_EL0 and - * disable all event counters and cycle counter. + * disable Cycle Counter. + * TODO: Revisit to store only SMCCC specified registers. * ----------------------------------------------------- */ - bl save_pmcr_disable_pmu + bl save_gp_pmcr_pauth_regs /* ----------------------------------------------------- * Populate the parameters for the SMC handler. We @@ -255,7 +250,7 @@ smc_handler: * Switch back to SP_EL0 for the C runtime stack. * --------------------------------------------- */ - msr spsel, #0 + msr spsel, #MODE_SP_EL0 mov sp, x12 /* ----------------------------------------------------- diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index d44b46dc9..df01dbae0 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -59,18 +60,16 @@ void bl1_setup(void) /* Perform early platform-specific setup */ bl1_early_platform_setup(); -#ifdef __aarch64__ - /* - * Update pointer authentication key before the MMU is enabled. It is - * saved in the rodata section, that can be writen before enabling the - * MMU. This function must be called after the console is initialized - * in the early platform setup. - */ - bl_handle_pauth(); -#endif /* __aarch64__ */ - /* Perform late platform-specific setup */ bl1_plat_arch_setup(); + +#if CTX_INCLUDE_PAUTH_REGS + /* + * Assert that the ARMv8.3-PAuth registers are present or an access + * fault will be triggered when they are being saved or restored. + */ + assert(is_armv8_3_pauth_present()); +#endif /* CTX_INCLUDE_PAUTH_REGS */ } /******************************************************************************* diff --git a/bl2/aarch64/bl2_el3_entrypoint.S b/bl2/aarch64/bl2_el3_entrypoint.S index 261d29573..6fe2dd923 100644 --- a/bl2/aarch64/bl2_el3_entrypoint.S +++ b/bl2/aarch64/bl2_el3_entrypoint.S @@ -43,22 +43,12 @@ func bl2_entrypoint */ bl bl2_el3_setup - /* --------------------------------------------- - * Enable pointer authentication - * --------------------------------------------- - */ #if ENABLE_PAUTH - mrs x0, sctlr_el3 - orr x0, x0, #SCTLR_EnIA_BIT -#if ENABLE_BTI /* --------------------------------------------- - * Enable PAC branch type compatibility + * Program APIAKey_EL1 and enable pointer authentication. * --------------------------------------------- */ - bic x0, x0, #SCTLR_BT_BIT -#endif /* ENABLE_BTI */ - msr sctlr_el3, x0 - isb + bl pauth_init_enable_el3 #endif /* ENABLE_PAUTH */ /* --------------------------------------------- @@ -87,16 +77,13 @@ func bl2_run_next_image tlbi alle3 bl bl2_el3_plat_prepare_exit +#if ENABLE_PAUTH /* --------------------------------------------- - * Disable pointer authentication before jumping to BL31 or that will - * cause an authentication failure during the early platform init. + * Disable pointer authentication before jumping + * to next boot image. * --------------------------------------------- */ -#if ENABLE_PAUTH - mrs x0, sctlr_el3 - bic x0, x0, #SCTLR_EnIA_BIT - msr sctlr_el3, x0 - isb + bl pauth_disable_el3 #endif /* ENABLE_PAUTH */ ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S index 5e5b83b1d..a021e424a 100644 --- a/bl2/aarch64/bl2_entrypoint.S +++ b/bl2/aarch64/bl2_entrypoint.S @@ -117,22 +117,13 @@ func bl2_entrypoint mov x3, x23 bl bl2_setup - /* --------------------------------------------- - * Enable pointer authentication - * --------------------------------------------- - */ #if ENABLE_PAUTH - mrs x0, sctlr_el1 - orr x0, x0, #SCTLR_EnIA_BIT -#if ENABLE_BTI /* --------------------------------------------- - * Enable PAC branch type compatibility + * Program APIAKey_EL1 + * and enable pointer authentication. * --------------------------------------------- */ - bic x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT) -#endif /* ENABLE_BTI */ - msr sctlr_el1, x0 - isb + bl pauth_init_enable_el1 #endif /* ENABLE_PAUTH */ /* --------------------------------------------- diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c index 79b0e717b..802c17464 100644 --- a/bl2/bl2_main.c +++ b/bl2/bl2_main.c @@ -4,13 +4,17 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include + #include +#include #include #include #include #include #include #include +#include #include #include "bl2_private.h" @@ -31,18 +35,16 @@ void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, /* Perform early platform-specific setup */ bl2_early_platform_setup2(arg0, arg1, arg2, arg3); -#ifdef __aarch64__ - /* - * Update pointer authentication key before the MMU is enabled. It is - * saved in the rodata section, that can be writen before enabling the - * MMU. This function must be called after the console is initialized - * in the early platform setup. - */ - bl_handle_pauth(); -#endif /* __aarch64__ */ - /* Perform late platform-specific setup */ bl2_plat_arch_setup(); + +#if CTX_INCLUDE_PAUTH_REGS + /* + * Assert that the ARMv8.3-PAuth registers are present or an access + * fault will be triggered when they are being saved or restored. + */ + assert(is_armv8_3_pauth_present()); +#endif /* CTX_INCLUDE_PAUTH_REGS */ } #else /* if BL2_AT_EL3 */ @@ -55,18 +57,16 @@ void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, /* Perform early platform-specific setup */ bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3); -#ifdef __aarch64__ - /* - * Update pointer authentication key before the MMU is enabled. It is - * saved in the rodata section, that can be writen before enabling the - * MMU. This function must be called after the console is initialized - * in the early platform setup. - */ - bl_handle_pauth(); -#endif /* __aarch64__ */ - /* Perform late platform-specific setup */ bl2_el3_plat_arch_setup(); + +#if CTX_INCLUDE_PAUTH_REGS + /* + * Assert that the ARMv8.3-PAuth registers are present or an access + * fault will be triggered when they are being saved or restored. + */ + assert(is_armv8_3_pauth_present()); +#endif /* CTX_INCLUDE_PAUTH_REGS */ } #endif /* BL2_AT_EL3 */ @@ -108,6 +108,13 @@ void bl2_main(void) console_flush(); +#if ENABLE_PAUTH + /* + * Disable pointer authentication before running next boot image + */ + pauth_disable_el1(); +#endif /* ENABLE_PAUTH */ + /* * Run next BL image via an SMC to BL1. Information on how to pass * control to the BL32 (if present) and BL33 software images will @@ -119,6 +126,13 @@ void bl2_main(void) print_entry_point_info(next_bl_ep_info); console_flush(); +#if ENABLE_PAUTH + /* + * Disable pointer authentication before running next boot image + */ + pauth_disable_el3(); +#endif /* ENABLE_PAUTH */ + bl2_run_next_image(next_bl_ep_info); #endif /* BL2_AT_EL3 */ } diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index e7ad5a897..1ad26e4fe 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -98,26 +98,16 @@ func bl31_entrypoint mov x3, x23 bl bl31_setup - /* -------------------------------------------------------------------- - * Enable pointer authentication - * -------------------------------------------------------------------- - */ #if ENABLE_PAUTH - mrs x0, sctlr_el3 - orr x0, x0, #SCTLR_EnIA_BIT -#if ENABLE_BTI /* -------------------------------------------------------------------- - * Enable PAC branch type compatibility + * Program APIAKey_EL1 and enable pointer authentication * -------------------------------------------------------------------- */ - bic x0, x0, #SCTLR_BT_BIT -#endif /* ENABLE_BTI */ - msr sctlr_el3, x0 - isb + bl pauth_init_enable_el3 #endif /* ENABLE_PAUTH */ /* -------------------------------------------------------------------- - * Jump to main function. + * Jump to main function * -------------------------------------------------------------------- */ bl bl31_main @@ -209,24 +199,12 @@ func bl31_warm_entrypoint #endif bl bl31_plat_enable_mmu - /* -------------------------------------------------------------------- - * Enable pointer authentication - * -------------------------------------------------------------------- - */ #if ENABLE_PAUTH - bl pauth_load_bl_apiakey - - mrs x0, sctlr_el3 - orr x0, x0, #SCTLR_EnIA_BIT -#if ENABLE_BTI /* -------------------------------------------------------------------- - * Enable PAC branch type compatibility + * Program APIAKey_EL1 and enable pointer authentication * -------------------------------------------------------------------- */ - bic x0, x0, #SCTLR_BT_BIT -#endif /* ENABLE_BTI */ - msr sctlr_el3, x0 - isb + bl pauth_init_enable_el3 #endif /* ENABLE_PAUTH */ bl psci_warmboot_entrypoint diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S index 8dca10cf9..6e71a063a 100644 --- a/bl31/aarch64/ea_delegate.S +++ b/bl31/aarch64/ea_delegate.S @@ -65,22 +65,16 @@ func enter_lower_el_sync_ea mrs x30, esr_el3 tbz x30, #ESR_ISS_EABORT_EA_BIT, 2f - /* Save GP registers */ - bl save_gp_registers - /* - * If Secure Cycle Counter is not disabled in MDCR_EL3 - * when ARMv8.5-PMU is implemented, save PMCR_EL0 and - * disable all event counters and cycle counter. + * Save general purpose and ARMv8.3-PAuth registers (if enabled). + * If Secure Cycle Counter is not disabled in MDCR_EL3 when + * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. */ - bl save_pmcr_disable_pmu + bl save_gp_pmcr_pauth_regs - /* Save ARMv8.3-PAuth registers and load firmware key */ -#if CTX_INCLUDE_PAUTH_REGS - bl pauth_context_save -#endif #if ENABLE_PAUTH - bl pauth_load_bl_apiakey + /* Load and program APIAKey firmware key */ + bl pauth_load_bl31_apiakey #endif /* Setup exception class and syndrome arguments for platform handler */ @@ -110,22 +104,16 @@ func enter_lower_el_async_ea */ str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] - /* Save GP registers */ - bl save_gp_registers - /* - * If Secure Cycle Counter is not disabled in MDCR_EL3 - * when ARMv8.5-PMU is implemented, save PMCR_EL0 and - * disable all event counters and cycle counter. + * Save general purpose and ARMv8.3-PAuth registers (if enabled). + * If Secure Cycle Counter is not disabled in MDCR_EL3 when + * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. */ - bl save_pmcr_disable_pmu + bl save_gp_pmcr_pauth_regs - /* Save ARMv8.3-PAuth registers and load firmware key */ -#if CTX_INCLUDE_PAUTH_REGS - bl pauth_context_save -#endif #if ENABLE_PAUTH - bl pauth_load_bl_apiakey + /* Load and program APIAKey firmware key */ + bl pauth_load_bl31_apiakey #endif /* Setup exception class and syndrome arguments for platform handler */ @@ -247,7 +235,7 @@ func ea_proceed /* Switch to runtime stack */ ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] - msr spsel, #0 + msr spsel, #MODE_SP_EL0 mov sp, x5 mov x29, x30 @@ -269,7 +257,7 @@ func ea_proceed #endif /* Make SP point to context */ - msr spsel, #1 + msr spsel, #MODE_SP_ELX /* Restore EL3 state and ESR */ ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 1cbec8fd9..51f5b7b34 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -65,19 +65,17 @@ mrs x30, DISR_EL1 tbz x30, #DISR_A_BIT, 1f - /* Save GP registers and restore them afterwards */ - bl save_gp_registers - /* - * If Secure Cycle Counter is not disabled in MDCR_EL3 - * when ARMv8.5-PMU is implemented, save PMCR_EL0 and - * disable all event counters and cycle counter. + * Save general purpose and ARMv8.3-PAuth registers (if enabled). + * If Secure Cycle Counter is not disabled in MDCR_EL3 when + * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. */ - bl save_pmcr_disable_pmu + bl save_gp_pmcr_pauth_regs bl handle_lower_el_ea_esb - bl restore_gp_registers + /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */ + bl restore_gp_pmcr_pauth_regs 1: #else /* Unmask the SError interrupt */ @@ -129,21 +127,16 @@ */ .macro handle_interrupt_exception label - bl save_gp_registers - /* - * If Secure Cycle Counter is not disabled in MDCR_EL3 - * when ARMv8.5-PMU is implemented, save PMCR_EL0 and - * disable all event counters and cycle counter. + * Save general purpose and ARMv8.3-PAuth registers (if enabled). + * If Secure Cycle Counter is not disabled in MDCR_EL3 when + * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. */ - bl save_pmcr_disable_pmu + bl save_gp_pmcr_pauth_regs - /* Save ARMv8.3-PAuth registers and load firmware key */ -#if CTX_INCLUDE_PAUTH_REGS - bl pauth_context_save -#endif #if ENABLE_PAUTH - bl pauth_load_bl_apiakey + /* Load and program APIAKey firmware key */ + bl pauth_load_bl31_apiakey #endif /* Save the EL3 system registers needed to return from this exception */ @@ -154,7 +147,7 @@ /* Switch to the runtime stack i.e. SP_EL0 */ ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] mov x20, sp - msr spsel, #0 + msr spsel, #MODE_SP_EL0 mov sp, x2 /* @@ -368,22 +361,16 @@ smc_handler32: smc_handler64: /* NOTE: The code below must preserve x0-x4 */ - /* Save general purpose registers */ - bl save_gp_registers - /* - * If Secure Cycle Counter is not disabled in MDCR_EL3 - * when ARMv8.5-PMU is implemented, save PMCR_EL0 and - * disable all event counters and cycle counter. + * Save general purpose and ARMv8.3-PAuth registers (if enabled). + * If Secure Cycle Counter is not disabled in MDCR_EL3 when + * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. */ - bl save_pmcr_disable_pmu + bl save_gp_pmcr_pauth_regs - /* Save ARMv8.3-PAuth registers and load firmware key */ -#if CTX_INCLUDE_PAUTH_REGS - bl pauth_context_save -#endif #if ENABLE_PAUTH - bl pauth_load_bl_apiakey + /* Load and program APIAKey firmware key */ + bl pauth_load_bl31_apiakey #endif /* @@ -403,7 +390,7 @@ smc_handler64: ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] /* Switch to SP_EL0 */ - msr spsel, #0 + msr spsel, #MODE_SP_EL0 /* * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world @@ -471,10 +458,12 @@ smc_prohibited: mov x0, #SMC_UNK eret +#if DEBUG rt_svc_fw_critical_error: /* Switch to SP_ELx */ - msr spsel, #1 + msr spsel, #MODE_SP_ELX no_ret report_unhandled_exception +#endif endfunc smc_handler /* --------------------------------------------------------------------- diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c index 856ea9f62..92a2027dd 100644 --- a/bl31/bl31_main.c +++ b/bl31/bl31_main.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -72,16 +73,16 @@ void bl31_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, /* Perform early platform-specific setup */ bl31_early_platform_setup2(arg0, arg1, arg2, arg3); - /* - * Update pointer authentication key before the MMU is enabled. It is - * saved in the rodata section, that can be writen before enabling the - * MMU. This function must be called after the console is initialized - * in the early platform setup. - */ - bl_handle_pauth(); - /* Perform late platform-specific setup */ bl31_plat_arch_setup(); + +#if CTX_INCLUDE_PAUTH_REGS + /* + * Assert that the ARMv8.3-PAuth registers are present or an access + * fault will be triggered when they are being saved or restored. + */ + assert(is_armv8_3_pauth_present()); +#endif /* CTX_INCLUDE_PAUTH_REGS */ } /******************************************************************************* diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index fd6b0fbcb..1d3ec21a7 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -129,22 +129,13 @@ func tsp_entrypoint _align=3 */ bl tsp_setup - /* --------------------------------------------- - * Enable pointer authentication - * --------------------------------------------- - */ #if ENABLE_PAUTH - mrs x0, sctlr_el1 - orr x0, x0, #SCTLR_EnIA_BIT -#if ENABLE_BTI /* --------------------------------------------- - * Enable PAC branch type compatibility + * Program APIAKey_EL1 + * and enable pointer authentication * --------------------------------------------- */ - bic x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT) -#endif /* ENABLE_BTI */ - msr sctlr_el1, x0 - isb + bl pauth_init_enable_el1 #endif /* ENABLE_PAUTH */ /* --------------------------------------------- @@ -271,6 +262,15 @@ func tsp_cpu_on_entry mov x0, #0 bl bl32_plat_enable_mmu +#if ENABLE_PAUTH + /* --------------------------------------------- + * Program APIAKey_EL1 + * and enable pointer authentication + * --------------------------------------------- + */ + bl pauth_init_enable_el1 +#endif /* ENABLE_PAUTH */ + /* --------------------------------------------- * Enter C runtime to perform any remaining * book keeping diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c index 0a817351c..e1d961cc6 100644 --- a/bl32/tsp/tsp_main.c +++ b/bl32/tsp/tsp_main.c @@ -4,14 +4,16 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include +#include +#include #include #include #include #include #include #include +#include #include #include "tsp_private.h" @@ -79,16 +81,16 @@ void tsp_setup(void) /* Perform early platform-specific setup */ tsp_early_platform_setup(); - /* - * Update pointer authentication key before the MMU is enabled. It is - * saved in the rodata section, that can be writen before enabling the - * MMU. This function must be called after the console is initialized - * in the early platform setup. - */ - bl_handle_pauth(); - /* Perform late platform-specific setup */ tsp_plat_arch_setup(); + +#if ENABLE_PAUTH + /* + * Assert that the ARMv8.3-PAuth registers are present or an access + * fault will be triggered when they are being saved or restored. + */ + assert(is_armv8_3_pauth_present()); +#endif /* ENABLE_PAUTH */ } /******************************************************************************* diff --git a/common/bl_common.c b/common/bl_common.c index a09cd7171..e6f98029e 100644 --- a/common/bl_common.c +++ b/common/bl_common.c @@ -244,53 +244,3 @@ void print_entry_point_info(const entry_point_info_t *ep_info) #endif #undef PRINT_IMAGE_ARG } - -#ifdef __aarch64__ -/******************************************************************************* - * Handle all possible cases regarding ARMv8.3-PAuth. - ******************************************************************************/ -void bl_handle_pauth(void) -{ -#if ENABLE_PAUTH - /* - * ENABLE_PAUTH = 1 && CTX_INCLUDE_PAUTH_REGS = 1 - * - * Check that the system supports address authentication to avoid - * getting an access fault when accessing the registers. This is all - * that is needed to check. If any of the authentication mechanisms is - * supported, the system knows about ARMv8.3-PAuth, so all the registers - * are available and accessing them won't generate a fault. - * - * Obtain 128-bit instruction key A from the platform and save it to the - * system registers. Pointer authentication can't be enabled here or the - * authentication will fail when returning from this function. - */ - assert(is_armv8_3_pauth_apa_api_present()); - - uint64_t *apiakey = plat_init_apiakey(); - - write_apiakeylo_el1(apiakey[0]); - write_apiakeyhi_el1(apiakey[1]); -#else /* if !ENABLE_PAUTH */ - -# if CTX_INCLUDE_PAUTH_REGS - /* - * ENABLE_PAUTH = 0 && CTX_INCLUDE_PAUTH_REGS = 1 - * - * Assert that the ARMv8.3-PAuth registers are present or an access - * fault will be triggered when they are being saved or restored. - */ - assert(is_armv8_3_pauth_present()); -# else - /* - * ENABLE_PAUTH = 0 && CTX_INCLUDE_PAUTH_REGS = 0 - * - * Pointer authentication is allowed in the Non-secure world, but - * prohibited in the Secure world. The Trusted Firmware doesn't save the - * registers during a world switch. No check needed. - */ -# endif /* CTX_INCLUDE_PAUTH_REGS */ - -#endif /* ENABLE_PAUTH */ -} -#endif /* __aarch64__ */ diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index b327f6ee3..5786dd384 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -1796,21 +1796,21 @@ defined by the translation library, and can be found in the file On DynamIQ systems, this function must not use stack while enabling MMU, which is how the function in xlat table library version 2 is implemented. -Function : plat_init_apiakey [optional] -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Function : plat_init_apkey [optional] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: Argument : void - Return : uint64_t * + Return : uint128_t -This function populates the ``plat_apiakey`` array that contains the values used -to set the ``APIAKey{Hi,Lo}_EL1`` registers. It returns a pointer to this array. +This function returns the 128-bit value which can be used to program ARMv8.3 +pointer authentication keys. The value should be obtained from a reliable source of randomness. This function is only needed if ARMv8.3 pointer authentication is used in the -Trusted Firmware by building with ``ENABLE_PAUTH=1``. +Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero. Function : plat_get_syscnt_freq2() [mandatory] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 48cbdb9f4..facd5b6cc 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -318,8 +318,9 @@ Common build options - ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. - If enabled, it is needed to use a compiler that supports the option - ``-mbranch-protection``. Selects the branch protection features to use: + If enabled, it is needed to use a compiler (e.g GCC 9.1 and later versions) that + supports the option ``-mbranch-protection``. + Selects the branch protection features to use: - 0: Default value turns off all types of branch protection - 1: Enables all types of branch protection features - 2: Return address signing to its standard level @@ -820,7 +821,6 @@ Common build options cluster platforms). If this option is enabled, then warm boot path enables D-caches immediately after enabling MMU. This option defaults to 0. - Arm development platform specific build options ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 2f29f4873..0491f48c6 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -34,14 +34,6 @@ static inline bool is_armv8_3_pauth_present(void) return (read_id_aa64isar1_el1() & mask) != 0U; } -static inline bool is_armv8_3_pauth_apa_api_present(void) -{ - uint64_t mask = (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | - (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); - - return (read_id_aa64isar1_el1() & mask) != 0U; -} - static inline bool is_armv8_4_ttst_present(void) { return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) & diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index e90a6e7d2..7a1f3a3a8 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -212,8 +212,7 @@ #define CTX_PACDBKEY_HI U(0x38) #define CTX_PACGAKEY_LO U(0x40) #define CTX_PACGAKEY_HI U(0x48) -#define CTX_PACGAKEY_END U(0x50) -#define CTX_PAUTH_REGS_END U(0x60) /* Align to the next 16 byte boundary */ +#define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ #else #define CTX_PAUTH_REGS_END U(0) #endif /* CTX_INCLUDE_PAUTH_REGS */ diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h index 55db4cff6..54261358e 100644 --- a/include/lib/el3_runtime/cpu_data.h +++ b/include/lib/el3_runtime/cpu_data.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,23 +11,37 @@ #include +/* Size of psci_cpu_data structure */ +#define PSCI_CPU_DATA_SIZE 12 + #ifdef __aarch64__ -/* Offsets for the cpu_data structure */ -#define CPU_DATA_CRASH_BUF_OFFSET 0x18 +/* 8-bytes aligned size of psci_cpu_data structure */ +#define PSCI_CPU_DATA_SIZE_ALIGNED ((PSCI_CPU_DATA_SIZE + 7) & ~7) + +/* Offset of cpu_ops_ptr, size 8 bytes */ +#define CPU_DATA_CPU_OPS_PTR 0x10 + +#if ENABLE_PAUTH +/* 8-bytes aligned offset of apiakey[2], size 16 bytes */ +#define CPU_DATA_APIAKEY_OFFSET (0x18 + PSCI_CPU_DATA_SIZE_ALIGNED) +#define CPU_DATA_CRASH_BUF_OFFSET (CPU_DATA_APIAKEY_OFFSET + 0x10) +#else +#define CPU_DATA_CRASH_BUF_OFFSET (0x18 + PSCI_CPU_DATA_SIZE_ALIGNED) +#endif /* ENABLE_PAUTH */ + /* need enough space in crash buffer to save 8 registers */ #define CPU_DATA_CRASH_BUF_SIZE 64 -#define CPU_DATA_CPU_OPS_PTR 0x10 -#else /* __aarch64__ */ +#else /* !__aarch64__ */ #if CRASH_REPORTING #error "Crash reporting is not supported in AArch32" #endif #define CPU_DATA_CPU_OPS_PTR 0x0 -#define CPU_DATA_CRASH_BUF_OFFSET 0x4 +#define CPU_DATA_CRASH_BUF_OFFSET (0x4 + PSCI_CPU_DATA_SIZE) -#endif /* __aarch64__ */ +#endif /* __aarch64__ */ #if CRASH_REPORTING #define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \ @@ -88,13 +102,16 @@ typedef struct cpu_data { void *cpu_context[2]; #endif uintptr_t cpu_ops_ptr; + struct psci_cpu_data psci_svc_cpu_data; +#if ENABLE_PAUTH + uint64_t apiakey[2]; +#endif #if CRASH_REPORTING u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3]; #endif #if ENABLE_RUNTIME_INSTRUMENTATION uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT]; #endif - struct psci_cpu_data psci_svc_cpu_data; #if PLAT_PCPU_DATA_SIZE uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE]; #endif @@ -105,6 +122,12 @@ typedef struct cpu_data { extern cpu_data_t percpu_data[PLATFORM_CORE_COUNT]; +#if ENABLE_PAUTH +CASSERT(CPU_DATA_APIAKEY_OFFSET == __builtin_offsetof + (cpu_data_t, apiakey), + assert_cpu_data_crash_stack_offset_mismatch); +#endif + #if CRASH_REPORTING /* verify assembler offsets match data structures */ CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof diff --git a/include/lib/extensions/pauth.h b/include/lib/extensions/pauth.h new file mode 100644 index 000000000..2e780dec2 --- /dev/null +++ b/include/lib/extensions/pauth.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PAUTH_H +#define PAUTH_H + +/******************************************************************************* + * ARMv8.3-PAuth support functions + ******************************************************************************/ + +/* Disable ARMv8.3 pointer authentication in EL1/EL3 */ +void pauth_disable_el1(void); +void pauth_disable_el3(void); + +#endif /* PAUTH_H */ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index 3f9ab1b66..eeae62141 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -104,7 +104,6 @@ void plat_panic_handler(void) __dead2; const char *plat_log_get_prefix(unsigned int log_level); void bl2_plat_preload_setup(void); int plat_try_next_boot_source(void); -uint64_t *plat_init_apiakey(void); /******************************************************************************* * Mandatory BL1 functions diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 37bb12c80..110142520 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -14,61 +14,16 @@ .global fpregs_context_save .global fpregs_context_restore #endif -#if CTX_INCLUDE_PAUTH_REGS - .global pauth_context_restore - .global pauth_context_save -#endif -#if ENABLE_PAUTH - .global pauth_load_bl_apiakey -#endif - .global save_gp_registers - .global restore_gp_registers - .global restore_gp_registers_eret - .global save_pmcr_disable_pmu + .global save_gp_pmcr_pauth_regs + .global restore_gp_pmcr_pauth_regs .global el3_exit -/* ----------------------------------------------------- - * If ARMv8.5-PMU is implemented, cycle counting is - * disabled by seting MDCR_EL3.SCCD to 1. - * ----------------------------------------------------- - */ -func save_pmcr_disable_pmu - /* ----------------------------------------------------- - * Check if earlier initialization MDCR_EL3.SCCD to 1 - * failed, meaning that ARMv8-PMU is not implemented and - * PMCR_EL0 should be saved in non-secure context. - * ----------------------------------------------------- - */ - mrs x9, mdcr_el3 - tst x9, #MDCR_SCCD_BIT - bne 1f - - /* Secure Cycle Counter is not disabled */ - mrs x9, pmcr_el0 - - /* Check caller's security state */ - mrs x10, scr_el3 - tst x10, #SCR_NS_BIT - beq 2f - - /* Save PMCR_EL0 if called from Non-secure state */ - str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] - - /* Disable cycle counter when event counting is prohibited */ -2: orr x9, x9, #PMCR_EL0_DP_BIT - msr pmcr_el0, x9 - - isb -1: ret -endfunc save_pmcr_disable_pmu - -/* ----------------------------------------------------- - * The following function strictly follows the AArch64 - * PCS to use x9-x17 (temporary caller-saved registers) - * to save EL1 system register context. It assumes that - * 'x0' is pointing to a 'el1_sys_regs' structure where - * the register context will be saved. - * ----------------------------------------------------- +/* ------------------------------------------------------------------ + * The following function strictly follows the AArch64 PCS to use + * x9-x17 (temporary caller-saved registers) to save EL1 system + * register context. It assumes that 'x0' is pointing to a + * 'el1_sys_regs' structure where the register context will be saved. + * ------------------------------------------------------------------ */ func el1_sysregs_context_save @@ -159,13 +114,13 @@ func el1_sysregs_context_save ret endfunc el1_sysregs_context_save -/* ----------------------------------------------------- - * The following function strictly follows the AArch64 - * PCS to use x9-x17 (temporary caller-saved registers) - * to restore EL1 system register context. It assumes - * that 'x0' is pointing to a 'el1_sys_regs' structure - * from where the register context will be restored - * ----------------------------------------------------- +/* ------------------------------------------------------------------ + * The following function strictly follows the AArch64 PCS to use + * x9-x17 (temporary caller-saved registers) to restore EL1 system + * register context. It assumes that 'x0' is pointing to a + * 'el1_sys_regs' structure from where the register context will be + * restored + * ------------------------------------------------------------------ */ func el1_sysregs_context_restore @@ -255,21 +210,19 @@ func el1_sysregs_context_restore ret endfunc el1_sysregs_context_restore -/* ----------------------------------------------------- - * The following function follows the aapcs_64 strictly - * to use x9-x17 (temporary caller-saved registers - * according to AArch64 PCS) to save floating point - * register context. It assumes that 'x0' is pointing to - * a 'fp_regs' structure where the register context will +/* ------------------------------------------------------------------ + * The following function follows the aapcs_64 strictly to use + * x9-x17 (temporary caller-saved registers according to AArch64 PCS) + * to save floating point register context. It assumes that 'x0' is + * pointing to a 'fp_regs' structure where the register context will * be saved. * - * Access to VFP registers will trap if CPTR_EL3.TFP is - * set. However currently we don't use VFP registers - * nor set traps in Trusted Firmware, and assume it's - * cleared + * Access to VFP registers will trap if CPTR_EL3.TFP is set. + * However currently we don't use VFP registers nor set traps in + * Trusted Firmware, and assume it's cleared. * * TODO: Revisit when VFP is used in secure world - * ----------------------------------------------------- + * ------------------------------------------------------------------ */ #if CTX_INCLUDE_FPREGS func fpregs_context_save @@ -303,21 +256,19 @@ func fpregs_context_save ret endfunc fpregs_context_save -/* ----------------------------------------------------- - * The following function follows the aapcs_64 strictly - * to use x9-x17 (temporary caller-saved registers - * according to AArch64 PCS) to restore floating point - * register context. It assumes that 'x0' is pointing to - * a 'fp_regs' structure from where the register context +/* ------------------------------------------------------------------ + * The following function follows the aapcs_64 strictly to use x9-x17 + * (temporary caller-saved registers according to AArch64 PCS) to + * restore floating point register context. It assumes that 'x0' is + * pointing to a 'fp_regs' structure from where the register context * will be restored. * - * Access to VFP registers will trap if CPTR_EL3.TFP is - * set. However currently we don't use VFP registers - * nor set traps in Trusted Firmware, and assume it's - * cleared + * Access to VFP registers will trap if CPTR_EL3.TFP is set. + * However currently we don't use VFP registers nor set traps in + * Trusted Firmware, and assume it's cleared. * * TODO: Revisit when VFP is used in secure world - * ----------------------------------------------------- + * ------------------------------------------------------------------ */ func fpregs_context_restore ldp q0, q1, [x0, #CTX_FP_Q0] @@ -357,109 +308,23 @@ func fpregs_context_restore endfunc fpregs_context_restore #endif /* CTX_INCLUDE_FPREGS */ -#if CTX_INCLUDE_PAUTH_REGS -/* ----------------------------------------------------- - * The following function strictly follows the AArch64 - * PCS to use x9-x17 (temporary caller-saved registers) - * to save the ARMv8.3-PAuth register context. It assumes - * that 'sp' is pointing to a 'cpu_context_t' structure - * to where the register context will be saved. - * ----------------------------------------------------- - */ -func pauth_context_save - add x11, sp, #CTX_PAUTH_REGS_OFFSET - - mrs x9, APIAKeyLo_EL1 - mrs x10, APIAKeyHi_EL1 - stp x9, x10, [x11, #CTX_PACIAKEY_LO] - - mrs x9, APIBKeyLo_EL1 - mrs x10, APIBKeyHi_EL1 - stp x9, x10, [x11, #CTX_PACIBKEY_LO] - - mrs x9, APDAKeyLo_EL1 - mrs x10, APDAKeyHi_EL1 - stp x9, x10, [x11, #CTX_PACDAKEY_LO] - - mrs x9, APDBKeyLo_EL1 - mrs x10, APDBKeyHi_EL1 - stp x9, x10, [x11, #CTX_PACDBKEY_LO] - - mrs x9, APGAKeyLo_EL1 - mrs x10, APGAKeyHi_EL1 - stp x9, x10, [x11, #CTX_PACGAKEY_LO] - - ret -endfunc pauth_context_save - -/* ----------------------------------------------------- - * The following function strictly follows the AArch64 - * PCS to use x9-x17 (temporary caller-saved registers) - * to restore the ARMv8.3-PAuth register context. It assumes - * that 'sp' is pointing to a 'cpu_context_t' structure - * from where the register context will be restored. - * ----------------------------------------------------- - */ -func pauth_context_restore - add x11, sp, #CTX_PAUTH_REGS_OFFSET - - ldp x9, x10, [x11, #CTX_PACIAKEY_LO] - msr APIAKeyLo_EL1, x9 - msr APIAKeyHi_EL1, x10 - - ldp x9, x10, [x11, #CTX_PACIBKEY_LO] - msr APIBKeyLo_EL1, x9 - msr APIBKeyHi_EL1, x10 - - ldp x9, x10, [x11, #CTX_PACDAKEY_LO] - msr APDAKeyLo_EL1, x9 - msr APDAKeyHi_EL1, x10 - - ldp x9, x10, [x11, #CTX_PACDBKEY_LO] - msr APDBKeyLo_EL1, x9 - msr APDBKeyHi_EL1, x10 - - ldp x9, x10, [x11, #CTX_PACGAKEY_LO] - msr APGAKeyLo_EL1, x9 - msr APGAKeyHi_EL1, x10 - - ret -endfunc pauth_context_restore -#endif /* CTX_INCLUDE_PAUTH_REGS */ - -/* ----------------------------------------------------- - * The following function strictly follows the AArch64 - * PCS to use x9-x17 (temporary caller-saved registers) - * to load the APIA key used by the firmware. - * ----------------------------------------------------- - */ -#if ENABLE_PAUTH -func pauth_load_bl_apiakey - /* Load instruction key A used by the Trusted Firmware. */ - adrp x11, plat_apiakey - add x11, x11, :lo12:plat_apiakey - ldp x9, x10, [x11, #0] - - msr APIAKeyLo_EL1, x9 - msr APIAKeyHi_EL1, x10 - - ret -endfunc pauth_load_bl_apiakey -#endif /* ENABLE_PAUTH */ - -/* ----------------------------------------------------- - * The following functions are used to save and restore - * all the general purpose registers. Ideally we would - * only save and restore the callee saved registers when - * a world switch occurs but that type of implementation - * is more complex. So currently we will always save and - * restore these registers on entry and exit of EL3. - * These are not macros to ensure their invocation fits - * within the 32 instructions per exception vector. +/* ------------------------------------------------------------------ + * The following function is used to save and restore all the general + * purpose and ARMv8.3-PAuth (if enabled) registers. + * It also checks if Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, and if called from Non-secure + * state saves PMCR_EL0 and disables Cycle Counter. + * + * Ideally we would only save and restore the callee saved registers + * when a world switch occurs but that type of implementation is more + * complex. So currently we will always save and restore these + * registers on entry and exit of EL3. + * These are not macros to ensure their invocation fits within the 32 + * instructions per exception vector. * clobbers: x18 - * ----------------------------------------------------- + * ------------------------------------------------------------------ */ -func save_gp_registers +func save_gp_pmcr_pauth_regs stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] @@ -477,15 +342,114 @@ func save_gp_registers stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] mrs x18, sp_el0 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] + + /* ---------------------------------------------------------- + * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, + * meaning that ARMv8-PMU is not implemented and PMCR_EL0 + * should be saved in non-secure context. + * ---------------------------------------------------------- + */ + mrs x9, mdcr_el3 + tst x9, #MDCR_SCCD_BIT + bne 1f + + /* Secure Cycle Counter is not disabled */ + mrs x9, pmcr_el0 + + /* Check caller's security state */ + mrs x10, scr_el3 + tst x10, #SCR_NS_BIT + beq 2f + + /* Save PMCR_EL0 if called from Non-secure state */ + str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] + + /* Disable cycle counter when event counting is prohibited */ +2: orr x9, x9, #PMCR_EL0_DP_BIT + msr pmcr_el0, x9 + isb +1: +#if CTX_INCLUDE_PAUTH_REGS + /* ---------------------------------------------------------- + * Save the ARMv8.3-PAuth keys as they are not banked + * by exception level + * ---------------------------------------------------------- + */ + add x19, sp, #CTX_PAUTH_REGS_OFFSET + + mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */ + mrs x21, APIAKeyHi_EL1 + mrs x22, APIBKeyLo_EL1 /* x23:x22 = APIBKey */ + mrs x23, APIBKeyHi_EL1 + mrs x24, APDAKeyLo_EL1 /* x25:x24 = APDAKey */ + mrs x25, APDAKeyHi_EL1 + mrs x26, APDBKeyLo_EL1 /* x27:x26 = APDBKey */ + mrs x27, APDBKeyHi_EL1 + mrs x28, APGAKeyLo_EL1 /* x29:x28 = APGAKey */ + mrs x29, APGAKeyHi_EL1 + + stp x20, x21, [x19, #CTX_PACIAKEY_LO] + stp x22, x23, [x19, #CTX_PACIBKEY_LO] + stp x24, x25, [x19, #CTX_PACDAKEY_LO] + stp x26, x27, [x19, #CTX_PACDBKEY_LO] + stp x28, x29, [x19, #CTX_PACGAKEY_LO] +#endif /* CTX_INCLUDE_PAUTH_REGS */ + ret -endfunc save_gp_registers +endfunc save_gp_pmcr_pauth_regs -/* ----------------------------------------------------- - * This function restores all general purpose registers except x30 from the - * CPU context. x30 register must be explicitly restored by the caller. - * ----------------------------------------------------- +/* ------------------------------------------------------------------ + * This function restores ARMv8.3-PAuth (if enabled) and all general + * purpose registers except x30 from the CPU context. + * x30 register must be explicitly restored by the caller. + * ------------------------------------------------------------------ */ -func restore_gp_registers +func restore_gp_pmcr_pauth_regs +#if CTX_INCLUDE_PAUTH_REGS + /* Restore the ARMv8.3 PAuth keys */ + add x10, sp, #CTX_PAUTH_REGS_OFFSET + + ldp x0, x1, [x10, #CTX_PACIAKEY_LO] /* x1:x0 = APIAKey */ + ldp x2, x3, [x10, #CTX_PACIBKEY_LO] /* x3:x2 = APIBKey */ + ldp x4, x5, [x10, #CTX_PACDAKEY_LO] /* x5:x4 = APDAKey */ + ldp x6, x7, [x10, #CTX_PACDBKEY_LO] /* x7:x6 = APDBKey */ + ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */ + + msr APIAKeyLo_EL1, x0 + msr APIAKeyHi_EL1, x1 + msr APIBKeyLo_EL1, x2 + msr APIBKeyHi_EL1, x3 + msr APDAKeyLo_EL1, x4 + msr APDAKeyHi_EL1, x5 + msr APDBKeyLo_EL1, x6 + msr APDBKeyHi_EL1, x7 + msr APGAKeyLo_EL1, x8 + msr APGAKeyHi_EL1, x9 +#endif /* CTX_INCLUDE_PAUTH_REGS */ + + /* ---------------------------------------------------------- + * Restore PMCR_EL0 when returning to Non-secure state if + * Secure Cycle Counter is not disabled in MDCR_EL3 when + * ARMv8.5-PMU is implemented. + * ---------------------------------------------------------- + */ + mrs x0, scr_el3 + tst x0, #SCR_NS_BIT + beq 2f + + /* ---------------------------------------------------------- + * Back to Non-secure state. + * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, + * meaning that ARMv8-PMU is not implemented and PMCR_EL0 + * should be restored from non-secure context. + * ---------------------------------------------------------- + */ + mrs x0, mdcr_el3 + tst x0, #MDCR_SCCD_BIT + bne 2f + ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] + msr pmcr_el0, x0 +2: ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] @@ -504,49 +468,28 @@ func restore_gp_registers msr sp_el0, x28 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] ret -endfunc restore_gp_registers - -/* ----------------------------------------------------- - * Restore general purpose registers (including x30), and exit EL3 via ERET to - * a lower exception level. - * ----------------------------------------------------- - */ -func restore_gp_registers_eret - bl restore_gp_registers - ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] - -#if IMAGE_BL31 && RAS_EXTENSION - /* - * Issue Error Synchronization Barrier to synchronize SErrors before - * exiting EL3. We're running with EAs unmasked, so any synchronized - * errors would be taken immediately; therefore no need to inspect - * DISR_EL1 register. - */ - esb -#endif - eret -endfunc restore_gp_registers_eret +endfunc restore_gp_pmcr_pauth_regs -/* ----------------------------------------------------- - * This routine assumes that the SP_EL3 is pointing to - * a valid context structure from where the gp regs and - * other special registers can be retrieved. - * ----------------------------------------------------- +/* ------------------------------------------------------------------ + * This routine assumes that the SP_EL3 is pointing to a valid + * context structure from where the gp regs and other special + * registers can be retrieved. + * ------------------------------------------------------------------ */ func el3_exit - /* ----------------------------------------------------- - * Save the current SP_EL0 i.e. the EL3 runtime stack - * which will be used for handling the next SMC. Then - * switch to SP_EL3 - * ----------------------------------------------------- + /* ---------------------------------------------------------- + * Save the current SP_EL0 i.e. the EL3 runtime stack which + * will be used for handling the next SMC. + * Then switch to SP_EL3. + * ---------------------------------------------------------- */ mov x17, sp - msr spsel, #1 + msr spsel, #MODE_SP_ELX str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] - /* ----------------------------------------------------- + /* ---------------------------------------------------------- * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET - * ----------------------------------------------------- + * ---------------------------------------------------------- */ ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] @@ -554,43 +497,35 @@ func el3_exit msr spsr_el3, x16 msr elr_el3, x17 - /* ----------------------------------------------------- - * Restore PMCR_EL0 when returning to Non-secure state - * if Secure Cycle Counter is not disabled in MDCR_EL3 - * when ARMv8.5-PMU is implemented - * ----------------------------------------------------- - */ - tst x18, #SCR_NS_BIT - beq 2f - - /* ----------------------------------------------------- - * Back to Non-secure state. - * Check if earlier initialization MDCR_EL3.SCCD to 1 - * failed, meaning that ARMv8-PMU is not implemented and - * PMCR_EL0 should be restored from non-secure context. - * ----------------------------------------------------- - */ - mrs x17, mdcr_el3 - tst x17, #MDCR_SCCD_BIT - bne 2f - ldr x17, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] - msr pmcr_el0, x17 -2: - #if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 - /* Restore mitigation state as it was on entry to EL3 */ + /* ---------------------------------------------------------- + * Restore mitigation state as it was on entry to EL3 + * ---------------------------------------------------------- + */ ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE] - cmp x17, xzr - beq 1f + cbz x17, 1f blr x17 1: #endif + /* ---------------------------------------------------------- + * Restore general purpose (including x30), PMCR_EL0 and + * ARMv8.3-PAuth registers. + * Exit EL3 via ERET to a lower exception level. + * ---------------------------------------------------------- + */ + bl restore_gp_pmcr_pauth_regs + ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] -#if CTX_INCLUDE_PAUTH_REGS - /* Restore ARMv8.3-PAuth registers */ - bl pauth_context_restore +#if IMAGE_BL31 && RAS_EXTENSION + /* ---------------------------------------------------------- + * Issue Error Synchronization Barrier to synchronize SErrors + * before exiting EL3. We're running with EAs unmasked, so + * any synchronized errors would be taken immediately; + * therefore no need to inspect DISR_EL1 register. + * ---------------------------------------------------------- + */ + esb #endif + eret - /* Restore saved general purpose registers and return */ - b restore_gp_registers_eret endfunc el3_exit diff --git a/lib/extensions/pauth/pauth_helpers.S b/lib/extensions/pauth/pauth_helpers.S new file mode 100644 index 000000000..c6808de5b --- /dev/null +++ b/lib/extensions/pauth/pauth_helpers.S @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + + .global pauth_init_enable_el1 + .global pauth_disable_el1 + .global pauth_init_enable_el3 + .global pauth_disable_el3 + .globl pauth_load_bl31_apiakey + +/* ------------------------------------------------------------- + * Program APIAKey_EL1 and enable pointer authentication in EL1 + * ------------------------------------------------------------- + */ +func pauth_init_enable_el1 + stp x29, x30, [sp, #-16]! + + /* Initialize platform key */ + bl plat_init_apkey + + /* Program instruction key A used by the Trusted Firmware */ + msr APIAKeyLo_EL1, x0 + msr APIAKeyHi_EL1, x1 + + /* Enable pointer authentication */ + mrs x0, sctlr_el1 + orr x0, x0, #SCTLR_EnIA_BIT + +#if ENABLE_BTI + /* Enable PAC branch type compatibility */ + bic x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT) +#endif + msr sctlr_el1, x0 + isb + + ldp x29, x30, [sp], #16 + ret +endfunc pauth_init_enable_el1 + +/* ------------------------------------------------------------- + * Disable pointer authentication in EL3 + * ------------------------------------------------------------- + */ +func pauth_disable_el1 + mrs x0, sctlr_el1 + bic x0, x0, #SCTLR_EnIA_BIT + msr sctlr_el1, x0 + isb + ret +endfunc pauth_disable_el1 + +/* ------------------------------------------------------------- + * Program APIAKey_EL1 and enable pointer authentication in EL3 + * ------------------------------------------------------------- + */ +func pauth_init_enable_el3 + stp x29, x30, [sp, #-16]! + + /* Initialize platform key */ + bl plat_init_apkey + + /* Program instruction key A used by the Trusted Firmware */ + msr APIAKeyLo_EL1, x0 + msr APIAKeyHi_EL1, x1 + + /* Enable pointer authentication */ + mrs x0, sctlr_el3 + orr x0, x0, #SCTLR_EnIA_BIT + +#if ENABLE_BTI + /* Enable PAC branch type compatibility */ + bic x0, x0, #SCTLR_BT_BIT +#endif + msr sctlr_el3, x0 + isb + + ldp x29, x30, [sp], #16 + ret +endfunc pauth_init_enable_el3 + +/* ------------------------------------------------------------- + * Disable pointer authentication in EL3 + * ------------------------------------------------------------- + */ +func pauth_disable_el3 + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EnIA_BIT + msr sctlr_el3, x0 + isb + ret +endfunc pauth_disable_el3 + +/* ------------------------------------------------------------- + * The following function strictly follows the AArch64 PCS + * to use x9-x17 (temporary caller-saved registers) to load + * the APIAKey_EL1 used by the firmware. + * ------------------------------------------------------------- + */ +func pauth_load_bl31_apiakey + /* tpidr_el3 contains the address of cpu_data structure */ + mrs x9, tpidr_el3 + + /* Load apiakey from cpu_data */ + ldp x10, x11, [x9, #CPU_DATA_APIAKEY_OFFSET] + + /* Program instruction key A */ + msr APIAKeyLo_EL1, x10 + msr APIAKeyHi_EL1, x11 + isb + ret +endfunc pauth_load_bl31_apiakey diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c index b9467d3e0..853f9157c 100644 --- a/lib/psci/psci_setup.c +++ b/lib/psci/psci_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -280,6 +280,12 @@ void psci_arch_setup(void) /* Having initialized cpu_ops, we can now print errata status */ print_errata_status(); + +#if ENABLE_PAUTH + /* Store APIAKey_EL1 key */ + set_cpu_data(apiakey[0], read_apiakeylo_el1()); + set_cpu_data(apiakey[1], read_apiakeyhi_el1()); +#endif /* ENABLE_PAUTH */ } /****************************************************************************** diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c index 6d5c099fb..98dd2d62c 100644 --- a/lib/psci/psci_suspend.c +++ b/lib/psci/psci_suspend.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -304,6 +304,12 @@ void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info) counter_freq = plat_get_syscnt_freq2(); write_cntfrq_el0(counter_freq); +#if ENABLE_PAUTH + /* Store APIAKey_EL1 key */ + set_cpu_data(apiakey[0], read_apiakeylo_el1()); + set_cpu_data(apiakey[1], read_apiakeyhi_el1()); +#endif /* ENABLE_PAUTH */ + /* * Call the cpu suspend finish handler registered by the Secure Payload * Dispatcher to let it do any bookeeping. If the handler encounters an diff --git a/plat/arm/common/aarch64/arm_pauth.c b/plat/arm/common/aarch64/arm_pauth.c index a685c319d..7cea8a0c9 100644 --- a/plat/arm/common/aarch64/arm_pauth.c +++ b/plat/arm/common/aarch64/arm_pauth.c @@ -4,27 +4,25 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include /* - * Instruction pointer authentication key A. The low 64-bit are at [0], and the - * high bits at [1]. + * This is only a toy implementation to generate a seemingly random + * 128-bit key from sp, x30 and cntpct_el0 values. + * A production system must re-implement this function to generate + * keys from a reliable randomness source. */ -uint64_t plat_apiakey[2]; - -/* - * This is only a toy implementation to generate a seemingly random 128-bit key - * from sp and x30 values. A production system must re-implement this function - * to generate keys from a reliable randomness source. - */ -uint64_t *plat_init_apiakey(void) +uint128_t plat_init_apkey(void) { - uintptr_t return_addr = (uintptr_t)__builtin_return_address(0U); - uintptr_t frame_addr = (uintptr_t)__builtin_frame_address(0U); + uint64_t return_addr = (uint64_t)__builtin_return_address(0U); + uint64_t frame_addr = (uint64_t)__builtin_frame_address(0U); + uint64_t cntpct = read_cntpct_el0(); - plat_apiakey[0] = (return_addr << 13) ^ frame_addr; - plat_apiakey[1] = (frame_addr << 15) ^ return_addr; + /* Generate 128-bit key */ + uint64_t key_lo = (return_addr << 13) ^ frame_addr ^ cntpct; + uint64_t key_hi = (frame_addr << 15) ^ return_addr ^ cntpct; - return plat_apiakey; + return ((uint128_t)(key_hi) << 64) | key_lo; } diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 10b6e5122..a4a29bf74 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -234,7 +234,8 @@ endif # Pointer Authentication sources ifeq (${ENABLE_PAUTH}, 1) -PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c +PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c \ + lib/extensions/pauth/pauth_helpers.S endif # SPM uses libfdt in Arm platforms diff --git a/readme.rst b/readme.rst index 6c93a4ca2..b5038084d 100644 --- a/readme.rst +++ b/readme.rst @@ -156,8 +156,8 @@ Functionality The use of pointer authentication in the normal world is enabled whenever architectural support is available, without the need for additional build flags. Use of pointer authentication in the secure world remains an - experimental configuration at this time and requires the ``ENABLE_PAUTH`` - build flag to be set. + experimental configuration at this time and requires the + ``BRANCH_PROTECTION`` option to be set to non-zero. - Position-Independent Executable (PIE) support. Initially for BL31 only, with further support to be added in a future release. -- cgit v1.2.3 From eb5f0ba41eaead241efad2bc1e0502211fdca93b Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Fri, 13 Sep 2019 15:47:13 +0100 Subject: GICv3 driver: Fix support for full SPI range This patch fixes GICv3 driver bug which causes assertion when full range of SPI INTIDs 32-1019 is supported in GICv3 implementation. Change-Id: Ib6da4b6eea868cff271cb32c7c7570bf5547ab47 Signed-off-by: Alexei Fedorov --- drivers/arm/gic/v3/gicv3_main.c | 44 ++++++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 94a20ba07..44f5cd809 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -629,7 +629,9 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) num_ints &= TYPER_IT_LINES_NO_MASK; num_ints = (num_ints + 1U) << 5; - assert(num_ints <= (MAX_SPI_ID + 1U)); + /* Filter out special INTIDs 1020-1023 */ + if (num_ints > (MAX_SPI_ID + 1U)) + num_ints = MAX_SPI_ID + 1U; /* Wait for pending write to complete */ gicd_wait_for_pending_write(gicd_base); @@ -637,31 +639,31 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) /* Save the GICD_CTLR */ dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); - /* Save GICD_IGROUPR for INTIDs 32 - 1020 */ + /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); - /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */ + /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); - /* Save GICD_ISPENDR for INTIDs 32 - 1020 */ + /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); - /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */ + /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); - /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */ + /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); - /* Save GICD_ICFGR for INTIDs 32 - 1020 */ + /* Save GICD_ICFGR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); - /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */ + /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); - /* Save GICD_NSACR for INTIDs 32 - 1020 */ + /* Save GICD_NSACR for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); - /* Save GICD_IROUTER for INTIDs 32 - 1024 */ + /* Save GICD_IROUTER for INTIDs 32 - 1019 */ SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); /* @@ -707,24 +709,26 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) num_ints &= TYPER_IT_LINES_NO_MASK; num_ints = (num_ints + 1U) << 5; - assert(num_ints <= (MAX_SPI_ID + 1U)); + /* Filter out special INTIDs 1020-1023 */ + if (num_ints > (MAX_SPI_ID + 1U)) + num_ints = MAX_SPI_ID + 1U; - /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */ + /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); - /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */ + /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); - /* Restore GICD_ICFGR for INTIDs 32 - 1020 */ + /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); - /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */ + /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); - /* Restore GICD_NSACR for INTIDs 32 - 1020 */ + /* Restore GICD_NSACR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); - /* Restore GICD_IROUTER for INTIDs 32 - 1020 */ + /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); /* @@ -732,13 +736,13 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) * configured. */ - /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */ + /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); - /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */ + /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); - /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */ + /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); /* Restore the GICD_CTLR */ -- cgit v1.2.3 From 4f2b984852556afc3543d90150c46be4aaadbc75 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 9 Jul 2019 14:32:11 +0100 Subject: rpi3: Move shared rpi3 files into common directory To be able to share code more easily between the existing Raspberry Pi 3 and the upcoming Raspberry Pi 4 platform, move some code which is not board specific into a "common" directory. Change-Id: I9211ab2d754b040128fac13c2f0a30a5cc8c7f2c Signed-off-by: Andre Przywara --- plat/rpi/common/include/rpi_shared.h | 39 +++++ plat/rpi/common/rpi3_common.c | 232 ++++++++++++++++++++++++++++ plat/rpi/common/rpi3_image_load.c | 36 +++++ plat/rpi/common/rpi3_io_storage.c | 271 +++++++++++++++++++++++++++++++++ plat/rpi/common/rpi3_pm.c | 226 +++++++++++++++++++++++++++ plat/rpi/common/rpi3_rotpk.S | 15 ++ plat/rpi/common/rpi3_stack_protector.c | 29 ++++ plat/rpi/common/rpi3_topology.c | 58 +++++++ plat/rpi/common/rpi3_trusted_boot.c | 36 +++++ plat/rpi/rpi3/platform.mk | 25 +-- plat/rpi/rpi3/rpi3_bl1_setup.c | 4 +- plat/rpi/rpi3/rpi3_bl2_setup.c | 4 +- plat/rpi/rpi3/rpi3_bl31_setup.c | 4 +- plat/rpi/rpi3/rpi3_common.c | 232 ---------------------------- plat/rpi/rpi3/rpi3_image_load.c | 36 ----- plat/rpi/rpi3/rpi3_io_storage.c | 271 --------------------------------- plat/rpi/rpi3/rpi3_pm.c | 226 --------------------------- plat/rpi/rpi3/rpi3_private.h | 39 ----- plat/rpi/rpi3/rpi3_rotpk.S | 15 -- plat/rpi/rpi3/rpi3_stack_protector.c | 29 ---- plat/rpi/rpi3/rpi3_topology.c | 58 ------- plat/rpi/rpi3/rpi3_trusted_boot.c | 36 ----- 22 files changed, 961 insertions(+), 960 deletions(-) create mode 100644 plat/rpi/common/include/rpi_shared.h create mode 100644 plat/rpi/common/rpi3_common.c create mode 100644 plat/rpi/common/rpi3_image_load.c create mode 100644 plat/rpi/common/rpi3_io_storage.c create mode 100644 plat/rpi/common/rpi3_pm.c create mode 100644 plat/rpi/common/rpi3_rotpk.S create mode 100644 plat/rpi/common/rpi3_stack_protector.c create mode 100644 plat/rpi/common/rpi3_topology.c create mode 100644 plat/rpi/common/rpi3_trusted_boot.c delete mode 100644 plat/rpi/rpi3/rpi3_common.c delete mode 100644 plat/rpi/rpi3/rpi3_image_load.c delete mode 100644 plat/rpi/rpi3/rpi3_io_storage.c delete mode 100644 plat/rpi/rpi3/rpi3_pm.c delete mode 100644 plat/rpi/rpi3/rpi3_private.h delete mode 100644 plat/rpi/rpi3/rpi3_rotpk.S delete mode 100644 plat/rpi/rpi3/rpi3_stack_protector.c delete mode 100644 plat/rpi/rpi3/rpi3_topology.c delete mode 100644 plat/rpi/rpi3/rpi3_trusted_boot.c diff --git a/plat/rpi/common/include/rpi_shared.h b/plat/rpi/common/include/rpi_shared.h new file mode 100644 index 000000000..686343892 --- /dev/null +++ b/plat/rpi/common/include/rpi_shared.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI_SHARED_H +#define RPI_SHARED_H + +#include + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ + +/* Utility functions */ +void rpi3_console_init(void); +void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, + uintptr_t code_start, uintptr_t code_limit, + uintptr_t rodata_start, uintptr_t rodata_limit +#if USE_COHERENT_MEM + , uintptr_t coh_start, uintptr_t coh_limit +#endif + ); + +/* Optional functions required in the Raspberry Pi 3 port */ +unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr); + +/* BL2 utility functions */ +uint32_t rpi3_get_spsr_for_bl32_entry(void); +uint32_t rpi3_get_spsr_for_bl33_entry(void); + +/* IO storage utility functions */ +void plat_rpi3_io_setup(void); + +/* VideoCore firmware commands */ +int rpi3_vc_hardware_get_board_revision(uint32_t *revision); + +#endif /* RPI3_PRIVATE_H */ diff --git a/plat/rpi/common/rpi3_common.c b/plat/rpi/common/rpi3_common.c new file mode 100644 index 000000000..ac0330899 --- /dev/null +++ b/plat/rpi/common/rpi3_common.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ + DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ + SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#ifdef RPI3_PRELOADED_DTB_BASE +#define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \ + MT_MEMORY | MT_RW | MT_NS) +#endif + +#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \ + PLAT_RPI3_FIP_MAX_SIZE, \ + MT_MEMORY | MT_RO | MT_NS) + +#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#ifdef SPD_opteed +#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \ + RPI3_OPTEE_PAGEABLE_LOAD_BASE, \ + RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif + +/* + * Table of regions for various BL stages to map using the MMU. + */ +#ifdef IMAGE_BL1 +static const mmap_region_t plat_rpi3_mmap[] = { + MAP_SHARED_RAM, + MAP_DEVICE0, + MAP_FIP, +#ifdef SPD_opteed + MAP_OPTEE_PAGEABLE, +#endif + {0} +}; +#endif + +#ifdef IMAGE_BL2 +static const mmap_region_t plat_rpi3_mmap[] = { + MAP_SHARED_RAM, + MAP_DEVICE0, + MAP_FIP, + MAP_NS_DRAM0, +#ifdef BL32_BASE + MAP_BL32_MEM, +#endif + {0} +}; +#endif + +#ifdef IMAGE_BL31 +static const mmap_region_t plat_rpi3_mmap[] = { + MAP_SHARED_RAM, + MAP_DEVICE0, +#ifdef RPI3_PRELOADED_DTB_BASE + MAP_NS_DTB, +#endif +#ifdef BL32_BASE + MAP_BL32_MEM, +#endif + {0} +}; +#endif + +/******************************************************************************* + * Function that sets up the console + ******************************************************************************/ +static console_16550_t rpi3_console; + +void rpi3_console_init(void) +{ + int console_scope = CONSOLE_FLAG_BOOT; +#if RPI3_RUNTIME_UART != -1 + console_scope |= CONSOLE_FLAG_RUNTIME; +#endif + int rc = console_16550_register(PLAT_RPI3_UART_BASE, + PLAT_RPI3_UART_CLK_IN_HZ, + PLAT_RPI3_UART_BAUDRATE, + &rpi3_console); + if (rc == 0) { + /* + * The crash console doesn't use the multi console API, it uses + * the core console functions directly. It is safe to call panic + * and let it print debug information. + */ + panic(); + } + + console_set_scope(&rpi3_console.console, console_scope); +} + +/******************************************************************************* + * Function that sets up the translation tables. + ******************************************************************************/ +void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, + uintptr_t code_start, uintptr_t code_limit, + uintptr_t rodata_start, uintptr_t rodata_limit +#if USE_COHERENT_MEM + , uintptr_t coh_start, uintptr_t coh_limit +#endif + ) +{ + /* + * Map the Trusted SRAM with appropriate memory attributes. + * Subsequent mappings will adjust the attributes for specific regions. + */ + VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", + (void *) total_base, (void *) (total_base + total_size)); + mmap_add_region(total_base, total_base, + total_size, + MT_MEMORY | MT_RW | MT_SECURE); + + /* Re-map the code section */ + VERBOSE("Code region: %p - %p\n", + (void *) code_start, (void *) code_limit); + mmap_add_region(code_start, code_start, + code_limit - code_start, + MT_CODE | MT_SECURE); + + /* Re-map the read-only data section */ + VERBOSE("Read-only data region: %p - %p\n", + (void *) rodata_start, (void *) rodata_limit); + mmap_add_region(rodata_start, rodata_start, + rodata_limit - rodata_start, + MT_RO_DATA | MT_SECURE); + +#if USE_COHERENT_MEM + /* Re-map the coherent memory region */ + VERBOSE("Coherent region: %p - %p\n", + (void *) coh_start, (void *) coh_limit); + mmap_add_region(coh_start, coh_start, + coh_limit - coh_start, + MT_DEVICE | MT_RW | MT_SECURE); +#endif + + mmap_add(plat_rpi3_mmap); + + init_xlat_tables(); +} + +/******************************************************************************* + * Return entrypoint of BL33. + ******************************************************************************/ +uintptr_t plat_get_ns_image_entrypoint(void) +{ +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else + return PLAT_RPI3_NS_IMAGE_OFFSET; +#endif +} + +/******************************************************************************* + * Gets SPSR for BL32 entry + ******************************************************************************/ +uint32_t rpi3_get_spsr_for_bl32_entry(void) +{ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL32 image. + */ + return 0; +} + +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +uint32_t rpi3_get_spsr_for_bl33_entry(void) +{ +#if RPI3_BL33_IN_AARCH32 + INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n"); + return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE, + DISABLE_ALL_EXCEPTIONS); +#else + return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); +#endif +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} + +uint32_t plat_ic_get_pending_interrupt_type(void) +{ + ERROR("rpi3: Interrupt routed to EL3.\n"); + return INTR_TYPE_INVAL; +} + +uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) +{ + assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) || + (type == INTR_TYPE_NS)); + + assert(sec_state_is_valid(security_state)); + + /* Non-secure interrupts are signalled on the IRQ line always. */ + if (type == INTR_TYPE_NS) + return __builtin_ctz(SCR_IRQ_BIT); + + /* Secure interrupts are signalled on the FIQ line always. */ + return __builtin_ctz(SCR_FIQ_BIT); +} diff --git a/plat/rpi/common/rpi3_image_load.c b/plat/rpi/common/rpi3_image_load.c new file mode 100644 index 000000000..5394c6f7c --- /dev/null +++ b/plat/rpi/common/rpi3_image_load.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +/******************************************************************************* + * This function flushes the data structures so that they are visible + * in memory for the next BL image. + ******************************************************************************/ +void plat_flush_next_bl_params(void) +{ + flush_bl_params_desc(); +} + +/******************************************************************************* + * This function returns the list of loadable images. + ******************************************************************************/ +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +/******************************************************************************* + * This function returns the list of executable images. + ******************************************************************************/ +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +} diff --git a/plat/rpi/common/rpi3_io_storage.c b/plat/rpi/common/rpi3_io_storage.c new file mode 100644 index 000000000..49c6a760c --- /dev/null +++ b/plat/rpi/common/rpi3_io_storage.c @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +/* Semihosting filenames */ +#define BL2_IMAGE_NAME "bl2.bin" +#define BL31_IMAGE_NAME "bl31.bin" +#define BL32_IMAGE_NAME "bl32.bin" +#define BL33_IMAGE_NAME "bl33.bin" + +#if TRUSTED_BOARD_BOOT +#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt" +#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" +#define SOC_FW_KEY_CERT_NAME "soc_fw_key.crt" +#define TOS_FW_KEY_CERT_NAME "tos_fw_key.crt" +#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt" +#define SOC_FW_CONTENT_CERT_NAME "soc_fw_content.crt" +#define TOS_FW_CONTENT_CERT_NAME "tos_fw_content.crt" +#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt" +#endif /* TRUSTED_BOARD_BOOT */ + +/* IO devices */ +static const io_dev_connector_t *fip_dev_con; +static uintptr_t fip_dev_handle; +static const io_dev_connector_t *memmap_dev_con; +static uintptr_t memmap_dev_handle; + +static const io_block_spec_t fip_block_spec = { + .offset = PLAT_RPI3_FIP_BASE, + .length = PLAT_RPI3_FIP_MAX_SIZE +}; + +static const io_uuid_spec_t bl2_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, +}; + +static const io_uuid_spec_t bl31_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, +}; + +static const io_uuid_spec_t bl32_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + +static const io_uuid_spec_t bl32_extra1_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, +}; + +static const io_uuid_spec_t bl32_extra2_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, +}; + +static const io_uuid_spec_t bl33_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +#if TRUSTED_BOARD_BOOT +static const io_uuid_spec_t tb_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FW_CERT, +}; + +static const io_uuid_spec_t trusted_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_KEY_CERT, +}; + +static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = { + .uuid = UUID_SOC_FW_KEY_CERT, +}; + +static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, +}; + +static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, +}; + +static const io_uuid_spec_t soc_fw_cert_uuid_spec = { + .uuid = UUID_SOC_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t tos_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t nt_fw_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, +}; +#endif /* TRUSTED_BOARD_BOOT */ + +static int open_fip(const uintptr_t spec); +static int open_memmap(const uintptr_t spec); + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +/* By default, load images from the FIP */ +static const struct plat_io_policy policies[] = { + [FIP_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&fip_block_spec, + open_memmap + }, + [BL2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl2_uuid_spec, + open_fip + }, + [BL31_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_uuid_spec, + open_fip + }, + [BL32_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_uuid_spec, + open_fip + }, + [BL32_EXTRA1_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra1_uuid_spec, + open_fip + }, + [BL32_EXTRA2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra2_uuid_spec, + open_fip + }, + [BL33_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_uuid_spec, + open_fip + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_BOOT_FW_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tb_fw_cert_uuid_spec, + open_fip + }, + [TRUSTED_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&trusted_key_cert_uuid_spec, + open_fip + }, + [SOC_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_key_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_key_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_key_cert_uuid_spec, + open_fip + }, + [SOC_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_cert_uuid_spec, + open_fip + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + +static int open_fip(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if a Firmware Image Package is available */ + result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); + if (result == 0) { + result = io_open(fip_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using FIP\n"); + io_close(local_image_handle); + } + } + return result; +} + +static int open_memmap(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(memmap_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Memmap\n"); + io_close(local_image_handle); + } + } + return result; +} + +void plat_rpi3_io_setup(void) +{ + int io_result; + + io_result = register_io_dev_fip(&fip_dev_con); + assert(io_result == 0); + + io_result = register_io_dev_memmap(&memmap_dev_con); + assert(io_result == 0); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, + &fip_dev_handle); + assert(io_result == 0); + + io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, + &memmap_dev_handle); + assert(io_result == 0); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} + +/* + * Return an IO device handle and specification which can be used to access + * an image. Use this to enforce platform load policy + */ +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + if (result == 0) { + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + } + + return result; +} diff --git a/plat/rpi/common/rpi3_pm.c b/plat/rpi/common/rpi3_pm.c new file mode 100644 index 000000000..b79e2736e --- /dev/null +++ b/plat/rpi/common/rpi3_pm.c @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include + +/* Make composite power state parameter till power level 0 */ +#if PSCI_EXTENDED_STATE_ID + +#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) + +#else + +#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) + +#endif /* PSCI_EXTENDED_STATE_ID */ + +#define rpi3_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ + rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) + +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +static const unsigned int rpi3_pm_idle_states[] = { + /* State-id - 0x01 */ + rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, + MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x02 */ + rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, + MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x22 */ + rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, + MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), + 0, +}; + +/******************************************************************************* + * Platform handler called to check the validity of the power state + * parameter. The power state parameter has to be a composite power state. + ******************************************************************************/ +static int rpi3_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int state_id; + int i; + + assert(req_state != 0); + + /* + * Currently we are using a linear search for finding the matching + * entry in the idle power state array. This can be made a binary + * search if the number of entries justify the additional complexity. + */ + for (i = 0; rpi3_pm_idle_states[i] != 0; i++) { + if (power_state == rpi3_pm_idle_states[i]) { + break; + } + } + + /* Return error if entry not found in the idle state array */ + if (!rpi3_pm_idle_states[i]) { + return PSCI_E_INVALID_PARAMS; + } + + i = 0; + state_id = psci_get_pstate_id(power_state); + + /* Parse the State ID and populate the state info parameter */ + while (state_id) { + req_state->pwr_domain_state[i++] = state_id & + PLAT_LOCAL_PSTATE_MASK; + state_id >>= PLAT_LOCAL_PSTATE_WIDTH; + } + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Platform handler called when a CPU is about to enter standby. + ******************************************************************************/ +static void rpi3_cpu_standby(plat_local_state_t cpu_state) +{ + assert(cpu_state == PLAT_LOCAL_STATE_RET); + + /* + * Enter standby state. + * dsb is good practice before using wfi to enter low power states + */ + dsb(); + wfi(); +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +static int rpi3_pwr_domain_on(u_register_t mpidr) +{ + int rc = PSCI_E_SUCCESS; + unsigned int pos = plat_core_pos_by_mpidr(mpidr); + uint64_t *hold_base = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; + + assert(pos < PLATFORM_CORE_COUNT); + + hold_base[pos] = PLAT_RPI3_TM_HOLD_STATE_GO; + + /* Make sure that the write has completed */ + dsb(); + isb(); + + sev(); + + return rc; +} + +/******************************************************************************* + * Platform handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == + PLAT_LOCAL_STATE_OFF); +} + +/******************************************************************************* + * Platform handlers for system reset and system off. + ******************************************************************************/ + +/* 10 ticks (Watchdog timer = Timer clock / 16) */ +#define RESET_TIMEOUT U(10) + +static void __dead2 rpi3_watchdog_reset(void) +{ + uint32_t rstc; + + console_flush(); + + dsbsy(); + isb(); + + mmio_write_32(RPI3_PM_BASE + RPI3_PM_WDOG_OFFSET, + RPI3_PM_PASSWORD | RESET_TIMEOUT); + + rstc = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET); + rstc &= ~RPI3_PM_RSTC_WRCFG_MASK; + rstc |= RPI3_PM_PASSWORD | RPI3_PM_RSTC_WRCFG_FULL_RESET; + mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET, rstc); + + for (;;) { + wfi(); + } +} + +static void __dead2 rpi3_system_reset(void) +{ + INFO("rpi3: PSCI_SYSTEM_RESET: Invoking watchdog reset\n"); + + rpi3_watchdog_reset(); +} + +static void __dead2 rpi3_system_off(void) +{ + uint32_t rsts; + + INFO("rpi3: PSCI_SYSTEM_OFF: Invoking watchdog reset\n"); + + /* + * This function doesn't actually make the Raspberry Pi turn itself off, + * the hardware doesn't allow it. It simply reboots it and the RSTS + * value tells the bootcode.bin firmware not to continue the regular + * bootflow and to stay in a low power mode. + */ + + rsts = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET); + rsts |= RPI3_PM_PASSWORD | RPI3_PM_RSTS_WRCFG_HALT; + mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET, rsts); + + rpi3_watchdog_reset(); +} + +/******************************************************************************* + * Platform handlers and setup function. + ******************************************************************************/ +static const plat_psci_ops_t plat_rpi3_psci_pm_ops = { + .cpu_standby = rpi3_cpu_standby, + .pwr_domain_on = rpi3_pwr_domain_on, + .pwr_domain_on_finish = rpi3_pwr_domain_on_finish, + .system_off = rpi3_system_off, + .system_reset = rpi3_system_reset, + .validate_power_state = rpi3_validate_power_state, +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + uintptr_t *entrypoint = (void *) PLAT_RPI3_TM_ENTRYPOINT; + + *entrypoint = sec_entrypoint; + *psci_ops = &plat_rpi3_psci_pm_ops; + + return 0; +} diff --git a/plat/rpi/common/rpi3_rotpk.S b/plat/rpi/common/rpi3_rotpk.S new file mode 100644 index 000000000..1c17b2141 --- /dev/null +++ b/plat/rpi/common/rpi3_rotpk.S @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .global rpi3_rotpk_hash + .global rpi3_rotpk_hash_end +rpi3_rotpk_hash: + /* DER header */ + .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 + .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 + /* SHA256 */ + .incbin ROTPK_HASH +rpi3_rotpk_hash_end: diff --git a/plat/rpi/common/rpi3_stack_protector.c b/plat/rpi/common/rpi3_stack_protector.c new file mode 100644 index 000000000..aae5fac72 --- /dev/null +++ b/plat/rpi/common/rpi3_stack_protector.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +#include + +/* Get 128 bits of entropy and fuse the values together to form the canary. */ +#define TRNG_NBYTES 16U + +u_register_t plat_get_stack_protector_canary(void) +{ + size_t i; + u_register_t buf[TRNG_NBYTES / sizeof(u_register_t)]; + u_register_t ret = 0U; + + rpi3_rng_read(buf, sizeof(buf)); + + for (i = 0U; i < ARRAY_SIZE(buf); i++) + ret ^= buf[i]; + + return ret; +} diff --git a/plat/rpi/common/rpi3_topology.c b/plat/rpi/common/rpi3_topology.c new file mode 100644 index 000000000..3747287c2 --- /dev/null +++ b/plat/rpi/common/rpi3_topology.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first node */ + PLATFORM_CLUSTER0_CORE_COUNT, +}; + +/******************************************************************************* + * This function returns the ARM default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { + return -1; + } + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) { + return -1; + } + + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { + return -1; + } + + return plat_rpi3_calc_core_pos(mpidr); +} diff --git a/plat/rpi/common/rpi3_trusted_boot.c b/plat/rpi/common/rpi3_trusted_boot.c new file mode 100644 index 000000000..f6c669fad --- /dev/null +++ b/plat/rpi/common/rpi3_trusted_boot.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +extern char rpi3_rotpk_hash[], rpi3_rotpk_hash_end[]; + +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + *key_ptr = rpi3_rotpk_hash; + *key_len = rpi3_rotpk_hash_end - rpi3_rotpk_hash; + *flags = ROTPK_IS_HASH; + + return 0; +} + +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + *nv_ctr = 0; + + return 0; +} + +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + return 1; +} + +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + return get_mbedtls_heap_helper(heap_addr, heap_size); +} diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk index 21a880c0d..a21a7709a 100644 --- a/plat/rpi/rpi3/platform.mk +++ b/plat/rpi/rpi3/platform.mk @@ -7,10 +7,11 @@ include lib/libfdt/libfdt.mk include lib/xlat_tables_v2/xlat_tables.mk -PLAT_INCLUDES := -Iplat/rpi/rpi3/include +PLAT_INCLUDES := -Iplat/rpi/common/include \ + -Iplat/rpi/rpi3/include PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \ - plat/rpi/rpi3/rpi3_common.c \ + plat/rpi/common/rpi3_common.c \ ${XLAT_TABLES_LIB_SRCS} BL1_SOURCES += drivers/io/io_fip.c \ @@ -20,7 +21,7 @@ BL1_SOURCES += drivers/io/io_fip.c \ plat/common/aarch64/platform_mp_stack.S \ plat/rpi/rpi3/aarch64/plat_helpers.S \ plat/rpi/rpi3/rpi3_bl1_setup.c \ - plat/rpi/rpi3/rpi3_io_storage.c \ + plat/rpi/common/rpi3_io_storage.c \ drivers/rpi3/mailbox/rpi3_mbox.c \ plat/rpi/rpi3/rpi_mbox_board.c @@ -39,15 +40,15 @@ BL2_SOURCES += common/desc_image_load.c \ plat/rpi/rpi3/aarch64/plat_helpers.S \ plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c \ plat/rpi/rpi3/rpi3_bl2_setup.c \ - plat/rpi/rpi3/rpi3_image_load.c \ - plat/rpi/rpi3/rpi3_io_storage.c + plat/rpi/common/rpi3_image_load.c \ + plat/rpi/common/rpi3_io_storage.c BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ plat/rpi/rpi3/aarch64/plat_helpers.S \ plat/rpi/rpi3/rpi3_bl31_setup.c \ - plat/rpi/rpi3/rpi3_pm.c \ - plat/rpi/rpi3/rpi3_topology.c \ + plat/rpi/common/rpi3_pm.c \ + plat/rpi/common/rpi3_topology.c \ ${LIBFDT_SRCS} # Tune compiler for Cortex-A53 @@ -160,7 +161,7 @@ endif ifneq ($(ENABLE_STACK_PROTECTOR), 0) PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \ - plat/rpi/rpi3/rpi3_stack_protector.c + plat/rpi/common/rpi3_stack_protector.c endif ifeq (${SPD},opteed) @@ -190,13 +191,13 @@ ifneq (${TRUSTED_BOARD_BOOT},0) BL1_SOURCES += ${AUTH_SOURCES} \ bl1/tbbr/tbbr_img_desc.c \ plat/common/tbbr/plat_tbbr.c \ - plat/rpi/rpi3/rpi3_trusted_boot.c \ - plat/rpi/rpi3/rpi3_rotpk.S + plat/rpi/common/rpi3_trusted_boot.c \ + plat/rpi/common/rpi3_rotpk.S BL2_SOURCES += ${AUTH_SOURCES} \ plat/common/tbbr/plat_tbbr.c \ - plat/rpi/rpi3/rpi3_trusted_boot.c \ - plat/rpi/rpi3/rpi3_rotpk.S + plat/rpi/common/rpi3_trusted_boot.c \ + plat/rpi/common/rpi3_rotpk.S ROT_KEY = $(BUILD_PLAT)/rot_key.pem ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c index b869e9da8..31ad31c19 100644 --- a/plat/rpi/rpi3/rpi3_bl1_setup.c +++ b/plat/rpi/rpi3/rpi3_bl1_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,7 @@ #include #include -#include "rpi3_private.h" +#include /* Data structure which holds the extents of the trusted SRAM for BL1 */ static meminfo_t bl1_tzram_layout; diff --git a/plat/rpi/rpi3/rpi3_bl2_setup.c b/plat/rpi/rpi3/rpi3_bl2_setup.c index b5e58352a..991c0fcb2 100644 --- a/plat/rpi/rpi3/rpi3_bl2_setup.c +++ b/plat/rpi/rpi3/rpi3_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,7 +19,7 @@ #include #include -#include "rpi3_private.h" +#include /* Data structure which holds the extents of the trusted SRAM for BL2 */ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); diff --git a/plat/rpi/rpi3/rpi3_bl31_setup.c b/plat/rpi/rpi3/rpi3_bl31_setup.c index 2f1bc6493..a9efc52b8 100644 --- a/plat/rpi/rpi3/rpi3_bl31_setup.c +++ b/plat/rpi/rpi3/rpi3_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,7 +15,7 @@ #include #include -#include "rpi3_private.h" +#include /* * Placeholder variables for copying the arguments that have been passed to diff --git a/plat/rpi/rpi3/rpi3_common.c b/plat/rpi/rpi3/rpi3_common.c deleted file mode 100644 index 85a26c222..000000000 --- a/plat/rpi/rpi3/rpi3_common.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include "rpi3_private.h" - -#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ - DEVICE0_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ - SHARED_RAM_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#ifdef RPI3_PRELOADED_DTB_BASE -#define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \ - MT_MEMORY | MT_RW | MT_NS) -#endif - -#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \ - PLAT_RPI3_FIP_MAX_SIZE, \ - MT_MEMORY | MT_RO | MT_NS) - -#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) - -#ifdef SPD_opteed -#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \ - RPI3_OPTEE_PAGEABLE_LOAD_BASE, \ - RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) -#endif - -/* - * Table of regions for various BL stages to map using the MMU. - */ -#ifdef IMAGE_BL1 -static const mmap_region_t plat_rpi3_mmap[] = { - MAP_SHARED_RAM, - MAP_DEVICE0, - MAP_FIP, -#ifdef SPD_opteed - MAP_OPTEE_PAGEABLE, -#endif - {0} -}; -#endif - -#ifdef IMAGE_BL2 -static const mmap_region_t plat_rpi3_mmap[] = { - MAP_SHARED_RAM, - MAP_DEVICE0, - MAP_FIP, - MAP_NS_DRAM0, -#ifdef BL32_BASE - MAP_BL32_MEM, -#endif - {0} -}; -#endif - -#ifdef IMAGE_BL31 -static const mmap_region_t plat_rpi3_mmap[] = { - MAP_SHARED_RAM, - MAP_DEVICE0, -#ifdef RPI3_PRELOADED_DTB_BASE - MAP_NS_DTB, -#endif -#ifdef BL32_BASE - MAP_BL32_MEM, -#endif - {0} -}; -#endif - -/******************************************************************************* - * Function that sets up the console - ******************************************************************************/ -static console_16550_t rpi3_console; - -void rpi3_console_init(void) -{ - int console_scope = CONSOLE_FLAG_BOOT; -#if RPI3_RUNTIME_UART != -1 - console_scope |= CONSOLE_FLAG_RUNTIME; -#endif - int rc = console_16550_register(PLAT_RPI3_UART_BASE, - PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE, - &rpi3_console); - if (rc == 0) { - /* - * The crash console doesn't use the multi console API, it uses - * the core console functions directly. It is safe to call panic - * and let it print debug information. - */ - panic(); - } - - console_set_scope(&rpi3_console.console, console_scope); -} - -/******************************************************************************* - * Function that sets up the translation tables. - ******************************************************************************/ -void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, - uintptr_t code_start, uintptr_t code_limit, - uintptr_t rodata_start, uintptr_t rodata_limit -#if USE_COHERENT_MEM - , uintptr_t coh_start, uintptr_t coh_limit -#endif - ) -{ - /* - * Map the Trusted SRAM with appropriate memory attributes. - * Subsequent mappings will adjust the attributes for specific regions. - */ - VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", - (void *) total_base, (void *) (total_base + total_size)); - mmap_add_region(total_base, total_base, - total_size, - MT_MEMORY | MT_RW | MT_SECURE); - - /* Re-map the code section */ - VERBOSE("Code region: %p - %p\n", - (void *) code_start, (void *) code_limit); - mmap_add_region(code_start, code_start, - code_limit - code_start, - MT_CODE | MT_SECURE); - - /* Re-map the read-only data section */ - VERBOSE("Read-only data region: %p - %p\n", - (void *) rodata_start, (void *) rodata_limit); - mmap_add_region(rodata_start, rodata_start, - rodata_limit - rodata_start, - MT_RO_DATA | MT_SECURE); - -#if USE_COHERENT_MEM - /* Re-map the coherent memory region */ - VERBOSE("Coherent region: %p - %p\n", - (void *) coh_start, (void *) coh_limit); - mmap_add_region(coh_start, coh_start, - coh_limit - coh_start, - MT_DEVICE | MT_RW | MT_SECURE); -#endif - - mmap_add(plat_rpi3_mmap); - - init_xlat_tables(); -} - -/******************************************************************************* - * Return entrypoint of BL33. - ******************************************************************************/ -uintptr_t plat_get_ns_image_entrypoint(void) -{ -#ifdef PRELOADED_BL33_BASE - return PRELOADED_BL33_BASE; -#else - return PLAT_RPI3_NS_IMAGE_OFFSET; -#endif -} - -/******************************************************************************* - * Gets SPSR for BL32 entry - ******************************************************************************/ -uint32_t rpi3_get_spsr_for_bl32_entry(void) -{ - /* - * The Secure Payload Dispatcher service is responsible for - * setting the SPSR prior to entry into the BL32 image. - */ - return 0; -} - -/******************************************************************************* - * Gets SPSR for BL33 entry - ******************************************************************************/ -uint32_t rpi3_get_spsr_for_bl33_entry(void) -{ -#if RPI3_BL33_IN_AARCH32 - INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n"); - return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE, - DISABLE_ALL_EXCEPTIONS); -#else - return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); -#endif -} - -unsigned int plat_get_syscnt_freq2(void) -{ - return SYS_COUNTER_FREQ_IN_TICKS; -} - -uint32_t plat_ic_get_pending_interrupt_type(void) -{ - ERROR("rpi3: Interrupt routed to EL3.\n"); - return INTR_TYPE_INVAL; -} - -uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) -{ - assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) || - (type == INTR_TYPE_NS)); - - assert(sec_state_is_valid(security_state)); - - /* Non-secure interrupts are signalled on the IRQ line always. */ - if (type == INTR_TYPE_NS) - return __builtin_ctz(SCR_IRQ_BIT); - - /* Secure interrupts are signalled on the FIQ line always. */ - return __builtin_ctz(SCR_FIQ_BIT); -} diff --git a/plat/rpi/rpi3/rpi3_image_load.c b/plat/rpi/rpi3/rpi3_image_load.c deleted file mode 100644 index 5394c6f7c..000000000 --- a/plat/rpi/rpi3/rpi3_image_load.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include - -/******************************************************************************* - * This function flushes the data structures so that they are visible - * in memory for the next BL image. - ******************************************************************************/ -void plat_flush_next_bl_params(void) -{ - flush_bl_params_desc(); -} - -/******************************************************************************* - * This function returns the list of loadable images. - ******************************************************************************/ -bl_load_info_t *plat_get_bl_image_load_info(void) -{ - return get_bl_load_info_from_mem_params_desc(); -} - -/******************************************************************************* - * This function returns the list of executable images. - ******************************************************************************/ -bl_params_t *plat_get_next_bl_params(void) -{ - return get_next_bl_params_from_mem_params_desc(); -} diff --git a/plat/rpi/rpi3/rpi3_io_storage.c b/plat/rpi/rpi3/rpi3_io_storage.c deleted file mode 100644 index 49c6a760c..000000000 --- a/plat/rpi/rpi3/rpi3_io_storage.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -/* Semihosting filenames */ -#define BL2_IMAGE_NAME "bl2.bin" -#define BL31_IMAGE_NAME "bl31.bin" -#define BL32_IMAGE_NAME "bl32.bin" -#define BL33_IMAGE_NAME "bl33.bin" - -#if TRUSTED_BOARD_BOOT -#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt" -#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" -#define SOC_FW_KEY_CERT_NAME "soc_fw_key.crt" -#define TOS_FW_KEY_CERT_NAME "tos_fw_key.crt" -#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt" -#define SOC_FW_CONTENT_CERT_NAME "soc_fw_content.crt" -#define TOS_FW_CONTENT_CERT_NAME "tos_fw_content.crt" -#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt" -#endif /* TRUSTED_BOARD_BOOT */ - -/* IO devices */ -static const io_dev_connector_t *fip_dev_con; -static uintptr_t fip_dev_handle; -static const io_dev_connector_t *memmap_dev_con; -static uintptr_t memmap_dev_handle; - -static const io_block_spec_t fip_block_spec = { - .offset = PLAT_RPI3_FIP_BASE, - .length = PLAT_RPI3_FIP_MAX_SIZE -}; - -static const io_uuid_spec_t bl2_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, -}; - -static const io_uuid_spec_t bl31_uuid_spec = { - .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, -}; - -static const io_uuid_spec_t bl32_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32, -}; - -static const io_uuid_spec_t bl32_extra1_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, -}; - -static const io_uuid_spec_t bl32_extra2_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, -}; - -static const io_uuid_spec_t bl33_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, -}; - -#if TRUSTED_BOARD_BOOT -static const io_uuid_spec_t tb_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FW_CERT, -}; - -static const io_uuid_spec_t trusted_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_KEY_CERT, -}; - -static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = { - .uuid = UUID_SOC_FW_KEY_CERT, -}; - -static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, -}; - -static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, -}; - -static const io_uuid_spec_t soc_fw_cert_uuid_spec = { - .uuid = UUID_SOC_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t tos_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t nt_fw_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, -}; -#endif /* TRUSTED_BOARD_BOOT */ - -static int open_fip(const uintptr_t spec); -static int open_memmap(const uintptr_t spec); - -struct plat_io_policy { - uintptr_t *dev_handle; - uintptr_t image_spec; - int (*check)(const uintptr_t spec); -}; - -/* By default, load images from the FIP */ -static const struct plat_io_policy policies[] = { - [FIP_IMAGE_ID] = { - &memmap_dev_handle, - (uintptr_t)&fip_block_spec, - open_memmap - }, - [BL2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl2_uuid_spec, - open_fip - }, - [BL31_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl31_uuid_spec, - open_fip - }, - [BL32_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_uuid_spec, - open_fip - }, - [BL32_EXTRA1_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra1_uuid_spec, - open_fip - }, - [BL32_EXTRA2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra2_uuid_spec, - open_fip - }, - [BL33_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl33_uuid_spec, - open_fip - }, -#if TRUSTED_BOARD_BOOT - [TRUSTED_BOOT_FW_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tb_fw_cert_uuid_spec, - open_fip - }, - [TRUSTED_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&trusted_key_cert_uuid_spec, - open_fip - }, - [SOC_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&soc_fw_key_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_key_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_key_cert_uuid_spec, - open_fip - }, - [SOC_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&soc_fw_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_cert_uuid_spec, - open_fip - }, -#endif /* TRUSTED_BOARD_BOOT */ -}; - -static int open_fip(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - /* See if a Firmware Image Package is available */ - result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); - if (result == 0) { - result = io_open(fip_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using FIP\n"); - io_close(local_image_handle); - } - } - return result; -} - -static int open_memmap(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); - if (result == 0) { - result = io_open(memmap_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using Memmap\n"); - io_close(local_image_handle); - } - } - return result; -} - -void plat_rpi3_io_setup(void) -{ - int io_result; - - io_result = register_io_dev_fip(&fip_dev_con); - assert(io_result == 0); - - io_result = register_io_dev_memmap(&memmap_dev_con); - assert(io_result == 0); - - /* Open connections to devices and cache the handles */ - io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, - &fip_dev_handle); - assert(io_result == 0); - - io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, - &memmap_dev_handle); - assert(io_result == 0); - - /* Ignore improbable errors in release builds */ - (void)io_result; -} - -/* - * Return an IO device handle and specification which can be used to access - * an image. Use this to enforce platform load policy - */ -int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int result; - const struct plat_io_policy *policy; - - assert(image_id < ARRAY_SIZE(policies)); - - policy = &policies[image_id]; - result = policy->check(policy->image_spec); - if (result == 0) { - *image_spec = policy->image_spec; - *dev_handle = *(policy->dev_handle); - } - - return result; -} diff --git a/plat/rpi/rpi3/rpi3_pm.c b/plat/rpi/rpi3/rpi3_pm.c deleted file mode 100644 index b79e2736e..000000000 --- a/plat/rpi/rpi3/rpi3_pm.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include -#include -#include -#include - -#include - -/* Make composite power state parameter till power level 0 */ -#if PSCI_EXTENDED_STATE_ID - -#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ - (((lvl0_state) << PSTATE_ID_SHIFT) | \ - ((type) << PSTATE_TYPE_SHIFT)) - -#else - -#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ - (((lvl0_state) << PSTATE_ID_SHIFT) | \ - ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ - ((type) << PSTATE_TYPE_SHIFT)) - -#endif /* PSCI_EXTENDED_STATE_ID */ - -#define rpi3_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ - (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ - rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) - -/* - * The table storing the valid idle power states. Ensure that the - * array entries are populated in ascending order of state-id to - * enable us to use binary search during power state validation. - * The table must be terminated by a NULL entry. - */ -static const unsigned int rpi3_pm_idle_states[] = { - /* State-id - 0x01 */ - rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, - MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), - /* State-id - 0x02 */ - rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, - MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), - /* State-id - 0x22 */ - rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, - MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), - 0, -}; - -/******************************************************************************* - * Platform handler called to check the validity of the power state - * parameter. The power state parameter has to be a composite power state. - ******************************************************************************/ -static int rpi3_validate_power_state(unsigned int power_state, - psci_power_state_t *req_state) -{ - unsigned int state_id; - int i; - - assert(req_state != 0); - - /* - * Currently we are using a linear search for finding the matching - * entry in the idle power state array. This can be made a binary - * search if the number of entries justify the additional complexity. - */ - for (i = 0; rpi3_pm_idle_states[i] != 0; i++) { - if (power_state == rpi3_pm_idle_states[i]) { - break; - } - } - - /* Return error if entry not found in the idle state array */ - if (!rpi3_pm_idle_states[i]) { - return PSCI_E_INVALID_PARAMS; - } - - i = 0; - state_id = psci_get_pstate_id(power_state); - - /* Parse the State ID and populate the state info parameter */ - while (state_id) { - req_state->pwr_domain_state[i++] = state_id & - PLAT_LOCAL_PSTATE_MASK; - state_id >>= PLAT_LOCAL_PSTATE_WIDTH; - } - - return PSCI_E_SUCCESS; -} - -/******************************************************************************* - * Platform handler called when a CPU is about to enter standby. - ******************************************************************************/ -static void rpi3_cpu_standby(plat_local_state_t cpu_state) -{ - assert(cpu_state == PLAT_LOCAL_STATE_RET); - - /* - * Enter standby state. - * dsb is good practice before using wfi to enter low power states - */ - dsb(); - wfi(); -} - -/******************************************************************************* - * Platform handler called when a power domain is about to be turned on. The - * mpidr determines the CPU to be turned on. - ******************************************************************************/ -static int rpi3_pwr_domain_on(u_register_t mpidr) -{ - int rc = PSCI_E_SUCCESS; - unsigned int pos = plat_core_pos_by_mpidr(mpidr); - uint64_t *hold_base = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; - - assert(pos < PLATFORM_CORE_COUNT); - - hold_base[pos] = PLAT_RPI3_TM_HOLD_STATE_GO; - - /* Make sure that the write has completed */ - dsb(); - isb(); - - sev(); - - return rc; -} - -/******************************************************************************* - * Platform handler called when a power domain has just been powered on after - * being turned off earlier. The target_state encodes the low power state that - * each level has woken up from. - ******************************************************************************/ -static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state) -{ - assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == - PLAT_LOCAL_STATE_OFF); -} - -/******************************************************************************* - * Platform handlers for system reset and system off. - ******************************************************************************/ - -/* 10 ticks (Watchdog timer = Timer clock / 16) */ -#define RESET_TIMEOUT U(10) - -static void __dead2 rpi3_watchdog_reset(void) -{ - uint32_t rstc; - - console_flush(); - - dsbsy(); - isb(); - - mmio_write_32(RPI3_PM_BASE + RPI3_PM_WDOG_OFFSET, - RPI3_PM_PASSWORD | RESET_TIMEOUT); - - rstc = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET); - rstc &= ~RPI3_PM_RSTC_WRCFG_MASK; - rstc |= RPI3_PM_PASSWORD | RPI3_PM_RSTC_WRCFG_FULL_RESET; - mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET, rstc); - - for (;;) { - wfi(); - } -} - -static void __dead2 rpi3_system_reset(void) -{ - INFO("rpi3: PSCI_SYSTEM_RESET: Invoking watchdog reset\n"); - - rpi3_watchdog_reset(); -} - -static void __dead2 rpi3_system_off(void) -{ - uint32_t rsts; - - INFO("rpi3: PSCI_SYSTEM_OFF: Invoking watchdog reset\n"); - - /* - * This function doesn't actually make the Raspberry Pi turn itself off, - * the hardware doesn't allow it. It simply reboots it and the RSTS - * value tells the bootcode.bin firmware not to continue the regular - * bootflow and to stay in a low power mode. - */ - - rsts = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET); - rsts |= RPI3_PM_PASSWORD | RPI3_PM_RSTS_WRCFG_HALT; - mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET, rsts); - - rpi3_watchdog_reset(); -} - -/******************************************************************************* - * Platform handlers and setup function. - ******************************************************************************/ -static const plat_psci_ops_t plat_rpi3_psci_pm_ops = { - .cpu_standby = rpi3_cpu_standby, - .pwr_domain_on = rpi3_pwr_domain_on, - .pwr_domain_on_finish = rpi3_pwr_domain_on_finish, - .system_off = rpi3_system_off, - .system_reset = rpi3_system_reset, - .validate_power_state = rpi3_validate_power_state, -}; - -int plat_setup_psci_ops(uintptr_t sec_entrypoint, - const plat_psci_ops_t **psci_ops) -{ - uintptr_t *entrypoint = (void *) PLAT_RPI3_TM_ENTRYPOINT; - - *entrypoint = sec_entrypoint; - *psci_ops = &plat_rpi3_psci_pm_ops; - - return 0; -} diff --git a/plat/rpi/rpi3/rpi3_private.h b/plat/rpi/rpi3/rpi3_private.h deleted file mode 100644 index b01c40c30..000000000 --- a/plat/rpi/rpi3/rpi3_private.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef RPI3_PRIVATE_H -#define RPI3_PRIVATE_H - -#include - -/******************************************************************************* - * Function and variable prototypes - ******************************************************************************/ - -/* Utility functions */ -void rpi3_console_init(void); -void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, - uintptr_t code_start, uintptr_t code_limit, - uintptr_t rodata_start, uintptr_t rodata_limit -#if USE_COHERENT_MEM - , uintptr_t coh_start, uintptr_t coh_limit -#endif - ); - -/* Optional functions required in the Raspberry Pi 3 port */ -unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr); - -/* BL2 utility functions */ -uint32_t rpi3_get_spsr_for_bl32_entry(void); -uint32_t rpi3_get_spsr_for_bl33_entry(void); - -/* IO storage utility functions */ -void plat_rpi3_io_setup(void); - -/* VideoCore firmware commands */ -int rpi3_vc_hardware_get_board_revision(uint32_t *revision); - -#endif /* RPI3_PRIVATE_H */ diff --git a/plat/rpi/rpi3/rpi3_rotpk.S b/plat/rpi/rpi3/rpi3_rotpk.S deleted file mode 100644 index 1c17b2141..000000000 --- a/plat/rpi/rpi3/rpi3_rotpk.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - - .global rpi3_rotpk_hash - .global rpi3_rotpk_hash_end -rpi3_rotpk_hash: - /* DER header */ - .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 - .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 - /* SHA256 */ - .incbin ROTPK_HASH -rpi3_rotpk_hash_end: diff --git a/plat/rpi/rpi3/rpi3_stack_protector.c b/plat/rpi/rpi3/rpi3_stack_protector.c deleted file mode 100644 index 6f49f617b..000000000 --- a/plat/rpi/rpi3/rpi3_stack_protector.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -#include "rpi3_private.h" - -/* Get 128 bits of entropy and fuse the values together to form the canary. */ -#define TRNG_NBYTES 16U - -u_register_t plat_get_stack_protector_canary(void) -{ - size_t i; - u_register_t buf[TRNG_NBYTES / sizeof(u_register_t)]; - u_register_t ret = 0U; - - rpi3_rng_read(buf, sizeof(buf)); - - for (i = 0U; i < ARRAY_SIZE(buf); i++) - ret ^= buf[i]; - - return ret; -} diff --git a/plat/rpi/rpi3/rpi3_topology.c b/plat/rpi/rpi3/rpi3_topology.c deleted file mode 100644 index 200d41dd1..000000000 --- a/plat/rpi/rpi3/rpi3_topology.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include - -#include "rpi3_private.h" - -/* The power domain tree descriptor */ -static unsigned char power_domain_tree_desc[] = { - /* Number of root nodes */ - PLATFORM_CLUSTER_COUNT, - /* Number of children for the first node */ - PLATFORM_CLUSTER0_CORE_COUNT, -}; - -/******************************************************************************* - * This function returns the ARM default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { - return -1; - } - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) { - return -1; - } - - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { - return -1; - } - - return plat_rpi3_calc_core_pos(mpidr); -} diff --git a/plat/rpi/rpi3/rpi3_trusted_boot.c b/plat/rpi/rpi3/rpi3_trusted_boot.c deleted file mode 100644 index f6c669fad..000000000 --- a/plat/rpi/rpi3/rpi3_trusted_boot.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -extern char rpi3_rotpk_hash[], rpi3_rotpk_hash_end[]; - -int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, - unsigned int *flags) -{ - *key_ptr = rpi3_rotpk_hash; - *key_len = rpi3_rotpk_hash_end - rpi3_rotpk_hash; - *flags = ROTPK_IS_HASH; - - return 0; -} - -int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) -{ - *nv_ctr = 0; - - return 0; -} - -int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) -{ - return 1; -} - -int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) -{ - return get_mbedtls_heap_helper(heap_addr, heap_size); -} -- cgit v1.2.3 From 110fd1fe4d3315a774199a8c58810a02ec3eb041 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 9 Jul 2019 15:59:26 +0100 Subject: rpi3: Rename RPI3_IO_BASE to RPI_IO_BASE The location of the MMIO window is different between a Raspberry Pi 3 and 4: the former has it just below 1GB, the latter below 4GB. The relative location of the peripherals is mostly compatible though. To allow sharing code between the two models, let's rename the symbol used for the MMIO base to the more generic RPI_IO_BASE name. Change-Id: I3c2762fb30fd56cca743348e79d72ef8c60ddb03 Signed-off-by: Andre Przywara --- plat/rpi/rpi3/include/platform_def.h | 4 ++-- plat/rpi/rpi3/include/rpi_hw.h | 16 ++++++++-------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/plat/rpi/rpi3/include/platform_def.h b/plat/rpi/rpi3/include/platform_def.h index 2a12fe726..e308f70a6 100644 --- a/plat/rpi/rpi3/include/platform_def.h +++ b/plat/rpi/rpi3/include/platform_def.h @@ -110,8 +110,8 @@ /* * I/O registers. */ -#define DEVICE0_BASE RPI3_IO_BASE -#define DEVICE0_SIZE RPI3_IO_SIZE +#define DEVICE0_BASE RPI_IO_BASE +#define DEVICE0_SIZE RPI_IO_SIZE /* * Arm TF lives in SRAM, partition it here diff --git a/plat/rpi/rpi3/include/rpi_hw.h b/plat/rpi/rpi3/include/rpi_hw.h index 7a3ea57bc..01d5b4a0f 100644 --- a/plat/rpi/rpi3/include/rpi_hw.h +++ b/plat/rpi/rpi3/include/rpi_hw.h @@ -13,14 +13,14 @@ * Peripherals */ -#define RPI3_IO_BASE ULL(0x3F000000) -#define RPI3_IO_SIZE ULL(0x01000000) +#define RPI_IO_BASE ULL(0x3F000000) +#define RPI_IO_SIZE ULL(0x01000000) /* * ARM <-> VideoCore mailboxes */ #define RPI3_MBOX_OFFSET ULL(0x0000B880) -#define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET) +#define RPI3_MBOX_BASE (RPI_IO_BASE + RPI3_MBOX_OFFSET) /* VideoCore -> ARM */ #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) @@ -41,7 +41,7 @@ * Power management, reset controller, watchdog. */ #define RPI3_IO_PM_OFFSET ULL(0x00100000) -#define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET) +#define RPI3_PM_BASE (RPI_IO_BASE + RPI3_IO_PM_OFFSET) /* Registers on top of RPI3_PM_BASE. */ #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) #define RPI3_PM_RSTS_OFFSET ULL(0x00000020) @@ -62,7 +62,7 @@ * Hardware random number generator. */ #define RPI3_IO_RNG_OFFSET ULL(0x00104000) -#define RPI3_RNG_BASE (RPI3_IO_BASE + RPI3_IO_RNG_OFFSET) +#define RPI3_RNG_BASE (RPI_IO_BASE + RPI3_IO_RNG_OFFSET) #define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) #define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) #define RPI3_RNG_DATA_OFFSET ULL(0x00000008) @@ -80,20 +80,20 @@ * Serial port (called 'Mini UART' in the BCM docucmentation). */ #define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) -#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET) +#define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET) #define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) /* * GPIO controller */ #define RPI3_IO_GPIO_OFFSET ULL(0x00200000) -#define RPI3_GPIO_BASE (RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET) +#define RPI3_GPIO_BASE (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET) /* * SDHost controller */ #define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) -#define RPI3_SDHOST_BASE (RPI3_IO_BASE + RPI3_IO_SDHOST_OFFSET) +#define RPI3_SDHOST_BASE (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET) /* * Local interrupt controller -- cgit v1.2.3 From 4666d046489a865f6434d7925903e0365da44575 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 9 Jul 2019 11:44:14 +0100 Subject: rpi3: Move rpi3_hw.h header file to include/rpi_hw.h With the advent of Raspberry Pi 4 support, we need to separate some board specific headers between the RPi3 and RPi4. Rename and move the "rpi3_hw.h" header, so that .c files just include rpi_hw.h, and automatically get the correct version. Change-Id: I03b39063028d2bee1429bffccde71dddfe2dcde8 Signed-off-by: Andre Przywara --- plat/rpi/rpi3/aarch64/plat_helpers.S | 2 +- plat/rpi/rpi3/include/platform_def.h | 2 +- plat/rpi/rpi3/include/rpi_hw.h | 110 +++++++++++++++++++++++++++++++++++ plat/rpi/rpi3/rpi3_common.c | 2 +- plat/rpi/rpi3/rpi3_hw.h | 110 ----------------------------------- plat/rpi/rpi3/rpi3_mbox.c | 2 +- plat/rpi/rpi3/rpi3_pm.c | 2 +- plat/rpi/rpi3/rpi3_rng.c | 2 +- 8 files changed, 116 insertions(+), 116 deletions(-) create mode 100644 plat/rpi/rpi3/include/rpi_hw.h delete mode 100644 plat/rpi/rpi3/rpi3_hw.h diff --git a/plat/rpi/rpi3/aarch64/plat_helpers.S b/plat/rpi/rpi3/aarch64/plat_helpers.S index 7974b602d..556d87212 100644 --- a/plat/rpi/rpi3/aarch64/plat_helpers.S +++ b/plat/rpi/rpi3/aarch64/plat_helpers.S @@ -9,7 +9,7 @@ #include #include -#include "../rpi3_hw.h" +#include "../include/rpi_hw.h" .globl plat_crash_console_flush .globl plat_crash_console_init diff --git a/plat/rpi/rpi3/include/platform_def.h b/plat/rpi/rpi3/include/platform_def.h index 4d902225f..2a12fe726 100644 --- a/plat/rpi/rpi3/include/platform_def.h +++ b/plat/rpi/rpi3/include/platform_def.h @@ -12,7 +12,7 @@ #include #include -#include "../rpi3_hw.h" +#include "rpi_hw.h" /* Special value used to verify platform parameters from BL2 to BL31 */ #define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) diff --git a/plat/rpi/rpi3/include/rpi_hw.h b/plat/rpi/rpi3/include/rpi_hw.h new file mode 100644 index 000000000..7a3ea57bc --- /dev/null +++ b/plat/rpi/rpi3/include/rpi_hw.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI_HW_H +#define RPI_HW_H + +#include + +/* + * Peripherals + */ + +#define RPI3_IO_BASE ULL(0x3F000000) +#define RPI3_IO_SIZE ULL(0x01000000) + +/* + * ARM <-> VideoCore mailboxes + */ +#define RPI3_MBOX_OFFSET ULL(0x0000B880) +#define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET) +/* VideoCore -> ARM */ +#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) +#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) +#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) +#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) +#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) +/* ARM -> VideoCore */ +#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) +#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) +#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) +#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) +#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) +/* Mailbox status constants */ +#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ +#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ + +/* + * Power management, reset controller, watchdog. + */ +#define RPI3_IO_PM_OFFSET ULL(0x00100000) +#define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET) +/* Registers on top of RPI3_PM_BASE. */ +#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) +#define RPI3_PM_RSTS_OFFSET ULL(0x00000020) +#define RPI3_PM_WDOG_OFFSET ULL(0x00000024) +/* Watchdog constants */ +#define RPI3_PM_PASSWORD U(0x5A000000) +#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) +#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) +/* + * The RSTS register is used by the VideoCore firmware when booting the + * Raspberry Pi to know which partition to boot from. The partition value is + * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware + * to indicate halt. + */ +#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) + +/* + * Hardware random number generator. + */ +#define RPI3_IO_RNG_OFFSET ULL(0x00104000) +#define RPI3_RNG_BASE (RPI3_IO_BASE + RPI3_IO_RNG_OFFSET) +#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) +#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) +#define RPI3_RNG_DATA_OFFSET ULL(0x00000008) +#define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010) +/* Enable/disable RNG */ +#define RPI3_RNG_CTRL_ENABLE U(0x1) +#define RPI3_RNG_CTRL_DISABLE U(0x0) +/* Number of currently available words */ +#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24) +#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF) +/* Value to mask interrupts caused by the RNG */ +#define RPI3_RNG_INT_MASK_DISABLE U(0x1) + +/* + * Serial port (called 'Mini UART' in the BCM docucmentation). + */ +#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) +#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET) +#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) + +/* + * GPIO controller + */ +#define RPI3_IO_GPIO_OFFSET ULL(0x00200000) +#define RPI3_GPIO_BASE (RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET) + +/* + * SDHost controller + */ +#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) +#define RPI3_SDHOST_BASE (RPI3_IO_BASE + RPI3_IO_SDHOST_OFFSET) + +/* + * Local interrupt controller + */ +#define RPI3_INTC_BASE_ADDRESS ULL(0x40000000) +/* Registers on top of RPI3_INTC_BASE_ADDRESS */ +#define RPI3_INTC_CONTROL_OFFSET ULL(0x00000000) +#define RPI3_INTC_PRESCALER_OFFSET ULL(0x00000008) +#define RPI3_INTC_MBOX_CONTROL_OFFSET ULL(0x00000050) +#define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ ULL(0x00000080) +#define RPI3_INTC_PENDING_FIQ_OFFSET ULL(0x00000070) +#define RPI3_INTC_PENDING_FIQ_MBOX3 ULL(0x00000080) + +#endif /* RPI_HW_H */ diff --git a/plat/rpi/rpi3/rpi3_common.c b/plat/rpi/rpi3/rpi3_common.c index 9b10974ad..85a26c222 100644 --- a/plat/rpi/rpi3/rpi3_common.c +++ b/plat/rpi/rpi3/rpi3_common.c @@ -16,7 +16,7 @@ #include #include -#include "rpi3_hw.h" +#include #include "rpi3_private.h" #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ diff --git a/plat/rpi/rpi3/rpi3_hw.h b/plat/rpi/rpi3/rpi3_hw.h deleted file mode 100644 index 1a86835b3..000000000 --- a/plat/rpi/rpi3/rpi3_hw.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef RPI3_HW_H -#define RPI3_HW_H - -#include - -/* - * Peripherals - */ - -#define RPI3_IO_BASE ULL(0x3F000000) -#define RPI3_IO_SIZE ULL(0x01000000) - -/* - * ARM <-> VideoCore mailboxes - */ -#define RPI3_MBOX_OFFSET ULL(0x0000B880) -#define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET) -/* VideoCore -> ARM */ -#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) -#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) -#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) -#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) -#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) -/* ARM -> VideoCore */ -#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) -#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) -#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) -#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) -#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) -/* Mailbox status constants */ -#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ -#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ - -/* - * Power management, reset controller, watchdog. - */ -#define RPI3_IO_PM_OFFSET ULL(0x00100000) -#define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET) -/* Registers on top of RPI3_PM_BASE. */ -#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) -#define RPI3_PM_RSTS_OFFSET ULL(0x00000020) -#define RPI3_PM_WDOG_OFFSET ULL(0x00000024) -/* Watchdog constants */ -#define RPI3_PM_PASSWORD U(0x5A000000) -#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) -#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) -/* - * The RSTS register is used by the VideoCore firmware when booting the - * Raspberry Pi to know which partition to boot from. The partition value is - * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware - * to indicate halt. - */ -#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) - -/* - * Hardware random number generator. - */ -#define RPI3_IO_RNG_OFFSET ULL(0x00104000) -#define RPI3_RNG_BASE (RPI3_IO_BASE + RPI3_IO_RNG_OFFSET) -#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) -#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) -#define RPI3_RNG_DATA_OFFSET ULL(0x00000008) -#define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010) -/* Enable/disable RNG */ -#define RPI3_RNG_CTRL_ENABLE U(0x1) -#define RPI3_RNG_CTRL_DISABLE U(0x0) -/* Number of currently available words */ -#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24) -#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF) -/* Value to mask interrupts caused by the RNG */ -#define RPI3_RNG_INT_MASK_DISABLE U(0x1) - -/* - * Serial port (called 'Mini UART' in the BCM docucmentation). - */ -#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) -#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET) -#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) - -/* - * GPIO controller - */ -#define RPI3_IO_GPIO_OFFSET ULL(0x00200000) -#define RPI3_GPIO_BASE (RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET) - -/* - * SDHost controller - */ -#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) -#define RPI3_SDHOST_BASE (RPI3_IO_BASE + RPI3_IO_SDHOST_OFFSET) - -/* - * Local interrupt controller - */ -#define RPI3_INTC_BASE_ADDRESS ULL(0x40000000) -/* Registers on top of RPI3_INTC_BASE_ADDRESS */ -#define RPI3_INTC_CONTROL_OFFSET ULL(0x00000000) -#define RPI3_INTC_PRESCALER_OFFSET ULL(0x00000008) -#define RPI3_INTC_MBOX_CONTROL_OFFSET ULL(0x00000050) -#define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ ULL(0x00000080) -#define RPI3_INTC_PENDING_FIQ_OFFSET ULL(0x00000070) -#define RPI3_INTC_PENDING_FIQ_MBOX3 ULL(0x00000080) - -#endif /* RPI3_HW_H */ diff --git a/plat/rpi/rpi3/rpi3_mbox.c b/plat/rpi/rpi3/rpi3_mbox.c index 2db605edf..03b395e78 100644 --- a/plat/rpi/rpi3/rpi3_mbox.c +++ b/plat/rpi/rpi3/rpi3_mbox.c @@ -12,7 +12,7 @@ #include #include -#include "rpi3_hw.h" +#include /* This struct must be aligned to 16 bytes */ typedef struct __packed __aligned(16) rpi3_mbox_request { diff --git a/plat/rpi/rpi3/rpi3_pm.c b/plat/rpi/rpi3/rpi3_pm.c index 4f586b514..b79e2736e 100644 --- a/plat/rpi/rpi3/rpi3_pm.c +++ b/plat/rpi/rpi3/rpi3_pm.c @@ -15,7 +15,7 @@ #include #include -#include "rpi3_hw.h" +#include /* Make composite power state parameter till power level 0 */ #if PSCI_EXTENDED_STATE_ID diff --git a/plat/rpi/rpi3/rpi3_rng.c b/plat/rpi/rpi3/rpi3_rng.c index fd69adbf3..b6bf0052a 100644 --- a/plat/rpi/rpi3/rpi3_rng.c +++ b/plat/rpi/rpi3/rpi3_rng.c @@ -9,7 +9,7 @@ #include -#include "rpi3_hw.h" +#include /* Initial amount of values to discard */ #define RNG_WARMUP_COUNT U(0x40000) -- cgit v1.2.3 From a95e6415ac3117eeaec522574bde753f1e4ffb9f Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 08:58:23 +0100 Subject: rpi3: Make SHARED_RAM optional The existing Raspberry Pi 3 port sports a number of memory regions, which are used for several purposes. The upcoming RPi4 port will not use all of those, so make the SHARED_RAM region optional, by only mapping it if it has actually been defined. This helps to get a cleaner RPi4 port. Change-Id: Id69677b7fb6ed48d9f238854b610896785db8cab Signed-off-by: Andre Przywara --- plat/rpi/common/rpi3_common.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/plat/rpi/common/rpi3_common.c b/plat/rpi/common/rpi3_common.c index ac0330899..ab63d98f1 100644 --- a/plat/rpi/common/rpi3_common.c +++ b/plat/rpi/common/rpi3_common.c @@ -23,9 +23,11 @@ DEVICE0_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) +#ifdef SHARED_RAM_BASE #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ SHARED_RAM_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) +#endif #ifdef RPI3_PRELOADED_DTB_BASE #define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \ @@ -54,7 +56,9 @@ */ #ifdef IMAGE_BL1 static const mmap_region_t plat_rpi3_mmap[] = { +#ifdef MAP_SHARED_RAM MAP_SHARED_RAM, +#endif MAP_DEVICE0, MAP_FIP, #ifdef SPD_opteed @@ -66,7 +70,9 @@ static const mmap_region_t plat_rpi3_mmap[] = { #ifdef IMAGE_BL2 static const mmap_region_t plat_rpi3_mmap[] = { +#ifdef MAP_SHARED_RAM MAP_SHARED_RAM, +#endif MAP_DEVICE0, MAP_FIP, MAP_NS_DRAM0, @@ -79,7 +85,9 @@ static const mmap_region_t plat_rpi3_mmap[] = { #ifdef IMAGE_BL31 static const mmap_region_t plat_rpi3_mmap[] = { +#ifdef MAP_SHARED_RAM MAP_SHARED_RAM, +#endif MAP_DEVICE0, #ifdef RPI3_PRELOADED_DTB_BASE MAP_NS_DTB, -- cgit v1.2.3 From c00311893d4bffb43b3f023259120d9dc5f78e36 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 9 Jul 2019 13:54:56 +0100 Subject: rpi3: Move VC mailbox driver into generic drivers directory To allow sharing the driver between the RPi3 and RPi4, move the mailbox driver into the generic driver directory. Change-Id: I463e49acf82b02bf004f3d56482b7791f3020bc0 Signed-off-by: Andre Przywara --- drivers/rpi3/mailbox/rpi3_mbox.c | 82 +++++++++++++++++ include/drivers/rpi3/mailbox/rpi3_mbox.h | 39 ++++++++ plat/rpi/rpi3/platform.mk | 3 +- plat/rpi/rpi3/rpi3_mbox.c | 148 ------------------------------- plat/rpi/rpi3/rpi_mbox_board.c | 56 ++++++++++++ 5 files changed, 179 insertions(+), 149 deletions(-) create mode 100644 drivers/rpi3/mailbox/rpi3_mbox.c create mode 100644 include/drivers/rpi3/mailbox/rpi3_mbox.h delete mode 100644 plat/rpi/rpi3/rpi3_mbox.c create mode 100644 plat/rpi/rpi3/rpi_mbox_board.c diff --git a/drivers/rpi3/mailbox/rpi3_mbox.c b/drivers/rpi3/mailbox/rpi3_mbox.c new file mode 100644 index 000000000..aef1f39a7 --- /dev/null +++ b/drivers/rpi3/mailbox/rpi3_mbox.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +#include + +#include + +#define RPI3_MAILBOX_MAX_RETRIES U(1000000) + +/******************************************************************************* + * Routine to send requests to the VideoCore using the mailboxes. + ******************************************************************************/ +void rpi3_vc_mailbox_request_send(rpi3_mbox_request_t *req, int req_size) +{ + uint32_t st, data; + uintptr_t resp_addr, addr; + unsigned int retries; + + /* This is the location of the request buffer */ + addr = (uintptr_t)req; + + /* Make sure that the changes are seen by the VideoCore */ + flush_dcache_range(addr, req_size); + + /* Wait until the outbound mailbox is empty */ + retries = 0U; + + do { + st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET); + + retries++; + if (retries == RPI3_MAILBOX_MAX_RETRIES) { + ERROR("rpi3: mbox: Send request timeout\n"); + return; + } + + } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U); + + /* Send base address of this message to start request */ + mmio_write_32(RPI3_MBOX_BASE + RPI3_MBOX1_WRITE_OFFSET, + RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr); + + /* Wait until the inbound mailbox isn't empty */ + retries = 0U; + + do { + st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET); + + retries++; + if (retries == RPI3_MAILBOX_MAX_RETRIES) { + ERROR("rpi3: mbox: Receive response timeout\n"); + return; + } + + } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U); + + /* Get location and channel */ + data = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_READ_OFFSET); + + if ((data & RPI3_CHANNEL_MASK) != RPI3_CHANNEL_ARM_TO_VC) { + ERROR("rpi3: mbox: Wrong channel: 0x%08x\n", data); + panic(); + } + + resp_addr = (uintptr_t)(data & ~RPI3_CHANNEL_MASK); + if (addr != resp_addr) { + ERROR("rpi3: mbox: Unexpected address: 0x%08x\n", data); + panic(); + } + + /* Make sure that the data seen by the CPU is up to date */ + inv_dcache_range(addr, req_size); +} diff --git a/include/drivers/rpi3/mailbox/rpi3_mbox.h b/include/drivers/rpi3/mailbox/rpi3_mbox.h new file mode 100644 index 000000000..c1074402b --- /dev/null +++ b/include/drivers/rpi3/mailbox/rpi3_mbox.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI3_MBOX_H +#define RPI3_MBOX_H + +#include + +/* This struct must be aligned to 16 bytes */ +typedef struct __packed __aligned(16) rpi3_mbox_request { + uint32_t size; /* Buffer size in bytes */ + uint32_t code; /* Request/response code */ + uint32_t tags[0]; +} rpi3_mbox_request_t; + +#define RPI3_MBOX_BUFFER_SIZE U(256) + +/* Constants to perform a request/check the status of a request. */ +#define RPI3_MBOX_PROCESS_REQUEST U(0x00000000) +#define RPI3_MBOX_REQUEST_SUCCESSFUL U(0x80000000) +#define RPI3_MBOX_REQUEST_ERROR U(0x80000001) + +/* Command constants */ +#define RPI3_TAG_HARDWARE_GET_BOARD_REVISION U(0x00010002) +#define RPI3_TAG_END U(0x00000000) + +#define RPI3_TAG_REQUEST U(0x00000000) +#define RPI3_TAG_IS_RESPONSE U(0x80000000) /* Set if response */ +#define RPI3_TAG_RESPONSE_LENGTH_MASK U(0x7FFFFFFF) + +#define RPI3_CHANNEL_ARM_TO_VC U(0x8) +#define RPI3_CHANNEL_MASK U(0xF) + +void rpi3_vc_mailbox_request_send(rpi3_mbox_request_t *req, int req_size); + +#endif diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk index c011c0a70..b0e7b7097 100644 --- a/plat/rpi/rpi3/platform.mk +++ b/plat/rpi/rpi3/platform.mk @@ -21,7 +21,8 @@ BL1_SOURCES += drivers/io/io_fip.c \ plat/rpi/rpi3/aarch64/plat_helpers.S \ plat/rpi/rpi3/rpi3_bl1_setup.c \ plat/rpi/rpi3/rpi3_io_storage.c \ - plat/rpi/rpi3/rpi3_mbox.c + drivers/rpi3/mailbox/rpi3_mbox.c \ + plat/rpi/rpi3/rpi_mbox_board.c BL2_SOURCES += common/desc_image_load.c \ drivers/io/io_fip.c \ diff --git a/plat/rpi/rpi3/rpi3_mbox.c b/plat/rpi/rpi3/rpi3_mbox.c deleted file mode 100644 index 03b395e78..000000000 --- a/plat/rpi/rpi3/rpi3_mbox.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include - -#include - -/* This struct must be aligned to 16 bytes */ -typedef struct __packed __aligned(16) rpi3_mbox_request { - uint32_t size; /* Buffer size in bytes */ - uint32_t code; /* Request/response code */ - uint32_t tags[0]; -} rpi3_mbox_request_t; - -#define RPI3_MBOX_BUFFER_SIZE U(256) -static uint8_t __aligned(16) rpi3_mbox_buffer[RPI3_MBOX_BUFFER_SIZE]; - -/* Constants to perform a request/check the status of a request. */ -#define RPI3_MBOX_PROCESS_REQUEST U(0x00000000) -#define RPI3_MBOX_REQUEST_SUCCESSFUL U(0x80000000) -#define RPI3_MBOX_REQUEST_ERROR U(0x80000001) - -/* Command constants */ -#define RPI3_TAG_HARDWARE_GET_BOARD_REVISION U(0x00010002) -#define RPI3_TAG_END U(0x00000000) - -#define RPI3_TAG_REQUEST U(0x00000000) -#define RPI3_TAG_IS_RESPONSE U(0x80000000) /* Set if response */ -#define RPI3_TAG_RESPONSE_LENGTH_MASK U(0x7FFFFFFF) - -#define RPI3_CHANNEL_ARM_TO_VC U(0x8) -#define RPI3_CHANNEL_MASK U(0xF) - -#define RPI3_MAILBOX_MAX_RETRIES U(1000000) - -/******************************************************************************* - * Helpers to send requests to the VideoCore using the mailboxes. - ******************************************************************************/ -static void rpi3_vc_mailbox_request_send(void) -{ - uint32_t st, data; - uintptr_t resp_addr, addr; - unsigned int retries; - - /* This is the location of the request buffer */ - addr = (uintptr_t) &rpi3_mbox_buffer; - - /* Make sure that the changes are seen by the VideoCore */ - flush_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE); - - /* Wait until the outbound mailbox is empty */ - retries = 0U; - - do { - st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET); - - retries++; - if (retries == RPI3_MAILBOX_MAX_RETRIES) { - ERROR("rpi3: mbox: Send request timeout\n"); - return; - } - - } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U); - - /* Send base address of this message to start request */ - mmio_write_32(RPI3_MBOX_BASE + RPI3_MBOX1_WRITE_OFFSET, - RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr); - - /* Wait until the inbound mailbox isn't empty */ - retries = 0U; - - do { - st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET); - - retries++; - if (retries == RPI3_MAILBOX_MAX_RETRIES) { - ERROR("rpi3: mbox: Receive response timeout\n"); - return; - } - - } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U); - - /* Get location and channel */ - data = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_READ_OFFSET); - - if ((data & RPI3_CHANNEL_MASK) != RPI3_CHANNEL_ARM_TO_VC) { - ERROR("rpi3: mbox: Wrong channel: 0x%08x\n", data); - panic(); - } - - resp_addr = (uintptr_t)(data & ~RPI3_CHANNEL_MASK); - if (addr != resp_addr) { - ERROR("rpi3: mbox: Unexpected address: 0x%08x\n", data); - panic(); - } - - /* Make sure that the data seen by the CPU is up to date */ - inv_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE); -} - -/******************************************************************************* - * Request board revision. Returns the revision and 0 on success, -1 on error. - ******************************************************************************/ -int rpi3_vc_hardware_get_board_revision(uint32_t *revision) -{ - uint32_t tag_request_size = sizeof(uint32_t); - rpi3_mbox_request_t *req = (rpi3_mbox_request_t *) rpi3_mbox_buffer; - - assert(revision != NULL); - - VERBOSE("rpi3: mbox: Sending request at %p\n", (void *)req); - - req->size = sizeof(rpi3_mbox_buffer); - req->code = RPI3_MBOX_PROCESS_REQUEST; - - req->tags[0] = RPI3_TAG_HARDWARE_GET_BOARD_REVISION; - req->tags[1] = tag_request_size; /* Space available for the response */ - req->tags[2] = RPI3_TAG_REQUEST; - req->tags[3] = 0; /* Placeholder for the response */ - - req->tags[4] = RPI3_TAG_END; - - rpi3_vc_mailbox_request_send(); - - if (req->code != RPI3_MBOX_REQUEST_SUCCESSFUL) { - ERROR("rpi3: mbox: Code = 0x%08x\n", req->code); - return -1; - } - - if (req->tags[2] != (RPI3_TAG_IS_RESPONSE | tag_request_size)) { - ERROR("rpi3: mbox: get board revision failed (0x%08x)\n", - req->tags[2]); - return -1; - } - - *revision = req->tags[3]; - - return 0; -} diff --git a/plat/rpi/rpi3/rpi_mbox_board.c b/plat/rpi/rpi3/rpi_mbox_board.c new file mode 100644 index 000000000..e7c1e2ba3 --- /dev/null +++ b/plat/rpi/rpi3/rpi_mbox_board.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include + +#define RPI3_MBOX_BUFFER_SIZE U(256) +static uint8_t __aligned(16) rpi3_mbox_buffer[RPI3_MBOX_BUFFER_SIZE]; + +/******************************************************************************* + * Request board revision. Returns the revision and 0 on success, -1 on error. + ******************************************************************************/ +int rpi3_vc_hardware_get_board_revision(uint32_t *revision) +{ + uint32_t tag_request_size = sizeof(uint32_t); + rpi3_mbox_request_t *req = (rpi3_mbox_request_t *) rpi3_mbox_buffer; + + assert(revision != NULL); + + VERBOSE("rpi3: mbox: Sending request at %p\n", (void *)req); + + req->size = sizeof(rpi3_mbox_buffer); + req->code = RPI3_MBOX_PROCESS_REQUEST; + + req->tags[0] = RPI3_TAG_HARDWARE_GET_BOARD_REVISION; + req->tags[1] = tag_request_size; /* Space available for the response */ + req->tags[2] = RPI3_TAG_REQUEST; + req->tags[3] = 0; /* Placeholder for the response */ + + req->tags[4] = RPI3_TAG_END; + + rpi3_vc_mailbox_request_send(req, RPI3_MBOX_BUFFER_SIZE); + + if (req->code != RPI3_MBOX_REQUEST_SUCCESSFUL) { + ERROR("rpi3: mbox: Code = 0x%08x\n", req->code); + return -1; + } + + if (req->tags[2] != (RPI3_TAG_IS_RESPONSE | tag_request_size)) { + ERROR("rpi3: mbox: get board revision failed (0x%08x)\n", + req->tags[2]); + return -1; + } + + *revision = req->tags[3]; + + return 0; +} -- cgit v1.2.3 From f240728b76c05ac507189a37375b120379eda650 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 10 Jul 2019 17:27:17 +0100 Subject: qemu: Move and generalise FDT PSCI fixup The QEMU platform port scans its device tree to advertise PSCI as the CPU enable method. It does this by scanning *every* node in the DT and check whether its compatible string starts with "arm,cortex-a". Then it sets the enable-method to PSCI, if it doesn't already have one. Other platforms might want to use this functionality as well, so let's move it out of the QEMU platform directory and make it more robust by fixing some shortcomings: - A compatible string starting with a certain prefix is not a good way to find the CPU nodes. For instance a "arm,cortex-a72-pmu" node will match as well and is in turn favoured with an enable-method. - If the DT already has an enable-method, we won't change this to PSCI. Those two issues will for instance fail on the Raspberry Pi 4 DT. To fix those problems, we adjust the scanning method: The DT spec says that all CPU nodes are subnodes of the mandatory /cpus node, which is a subnode of the root node. Also each CPU node has to have a device_type = "cpu" property. So we find the /cpus node, then scan for a subnode with the proper device_type, forcing the enable-method to "psci". We have to restart this search after a property has been patched, as the node offsets might have changed meanwhile. This allows this routine to be reused for the Raspberry Pi 4 later. Change-Id: I00cae16cc923d9f8bb96a9b2a2933b9a79b06139 Signed-off-by: Andre Przywara --- common/fdt_fixup.c | 126 +++++++++++++++++++++++++++++++++++++++++++++ include/common/fdt_fixup.h | 13 +++++ plat/qemu/dt.c | 99 ----------------------------------- plat/qemu/platform.mk | 2 +- plat/qemu/qemu_bl2_setup.c | 3 +- plat/qemu/qemu_private.h | 3 -- 6 files changed, 142 insertions(+), 104 deletions(-) create mode 100644 common/fdt_fixup.c create mode 100644 include/common/fdt_fixup.h delete mode 100644 plat/qemu/dt.c diff --git a/common/fdt_fixup.c b/common/fdt_fixup.c new file mode 100644 index 000000000..0ae0050c0 --- /dev/null +++ b/common/fdt_fixup.c @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Contains generic routines to fix up the device tree blob passed on to + * payloads like BL32 and BL33 (and further down the boot chain). + * This allows to easily add PSCI nodes, when the original DT does not have + * it or advertises another method. + */ + +#include + +#include + +#include +#include +#include + +#include + +static int append_psci_compatible(void *fdt, int offs, const char *str) +{ + return fdt_appendprop(fdt, offs, "compatible", str, strlen(str) + 1); +} + +int dt_add_psci_node(void *fdt) +{ + int offs; + + if (fdt_path_offset(fdt, "/psci") >= 0) { + WARN("PSCI Device Tree node already exists!\n"); + return 0; + } + + offs = fdt_path_offset(fdt, "/"); + if (offs < 0) + return -1; + offs = fdt_add_subnode(fdt, offs, "psci"); + if (offs < 0) + return -1; + if (append_psci_compatible(fdt, offs, "arm,psci-1.0")) + return -1; + if (append_psci_compatible(fdt, offs, "arm,psci-0.2")) + return -1; + if (append_psci_compatible(fdt, offs, "arm,psci")) + return -1; + if (fdt_setprop_string(fdt, offs, "method", "smc")) + return -1; + if (fdt_setprop_u32(fdt, offs, "cpu_suspend", PSCI_CPU_SUSPEND_AARCH64)) + return -1; + if (fdt_setprop_u32(fdt, offs, "cpu_off", PSCI_CPU_OFF)) + return -1; + if (fdt_setprop_u32(fdt, offs, "cpu_on", PSCI_CPU_ON_AARCH64)) + return -1; + if (fdt_setprop_u32(fdt, offs, "sys_poweroff", PSCI_SYSTEM_OFF)) + return -1; + if (fdt_setprop_u32(fdt, offs, "sys_reset", PSCI_SYSTEM_RESET)) + return -1; + return 0; +} + +/* + * Find the first subnode that has a "device_type" property with the value + * "cpu" and which's enable-method is not "psci" (yet). + * Returns 0 if no such subnode is found, so all have already been patched + * or none have to be patched in the first place. + * Returns 1 if *one* such subnode has been found and successfully changed + * to "psci". + * Returns -1 on error. + * + * Call in a loop until it returns 0. Recalculate the node offset after + * it has returned 1. + */ +static int dt_update_one_cpu_node(void *fdt, int offset) +{ + int offs; + + /* Iterate over all subnodes to find those with device_type = "cpu". */ + for (offs = fdt_first_subnode(fdt, offset); offs >= 0; + offs = fdt_next_subnode(fdt, offs)) { + const char *prop; + int len; + + prop = fdt_getprop(fdt, offs, "device_type", &len); + if (!prop) + continue; + if (memcmp(prop, "cpu", 4) != 0 || len != 4) + continue; + + /* Ignore any nodes which already use "psci". */ + prop = fdt_getprop(fdt, offs, "enable-method", &len); + if (prop && memcmp(prop, "psci", 5) == 0 && len == 5) + continue; + + if (fdt_setprop_string(fdt, offs, "enable-method", "psci")) + return -1; + /* + * Subnode found and patched. + * Restart to accommodate potentially changed offsets. + */ + return 1; + } + + if (offs == -FDT_ERR_NOTFOUND) + return 0; + + return offs; +} + +int dt_add_psci_cpu_enable_methods(void *fdt) +{ + int offs, ret; + + do { + offs = fdt_path_offset(fdt, "/cpus"); + if (offs < 0) + return offs; + + ret = dt_update_one_cpu_node(fdt, offs); + } while (ret > 0); + + return ret; +} diff --git a/include/common/fdt_fixup.h b/include/common/fdt_fixup.h new file mode 100644 index 000000000..bb05bf5d0 --- /dev/null +++ b/include/common/fdt_fixup.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FDT_FIXUP_H +#define FDT_FIXUP_H + +int dt_add_psci_node(void *fdt); +int dt_add_psci_cpu_enable_methods(void *fdt); + +#endif /* FDT_FIXUP_H */ diff --git a/plat/qemu/dt.c b/plat/qemu/dt.c deleted file mode 100644 index b1cd368cb..000000000 --- a/plat/qemu/dt.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include - -#include "qemu_private.h" - -static int append_psci_compatible(void *fdt, int offs, const char *str) -{ - return fdt_appendprop(fdt, offs, "compatible", str, strlen(str) + 1); -} - -int dt_add_psci_node(void *fdt) -{ - int offs; - - if (fdt_path_offset(fdt, "/psci") >= 0) { - WARN("PSCI Device Tree node already exists!\n"); - return 0; - } - - offs = fdt_path_offset(fdt, "/"); - if (offs < 0) - return -1; - offs = fdt_add_subnode(fdt, offs, "psci"); - if (offs < 0) - return -1; - if (append_psci_compatible(fdt, offs, "arm,psci-1.0")) - return -1; - if (append_psci_compatible(fdt, offs, "arm,psci-0.2")) - return -1; - if (append_psci_compatible(fdt, offs, "arm,psci")) - return -1; - if (fdt_setprop_string(fdt, offs, "method", "smc")) - return -1; - if (fdt_setprop_u32(fdt, offs, "cpu_suspend", PSCI_CPU_SUSPEND_AARCH64)) - return -1; - if (fdt_setprop_u32(fdt, offs, "cpu_off", PSCI_CPU_OFF)) - return -1; - if (fdt_setprop_u32(fdt, offs, "cpu_on", PSCI_CPU_ON_AARCH64)) - return -1; - if (fdt_setprop_u32(fdt, offs, "sys_poweroff", PSCI_SYSTEM_OFF)) - return -1; - if (fdt_setprop_u32(fdt, offs, "sys_reset", PSCI_SYSTEM_RESET)) - return -1; - return 0; -} - -static int check_node_compat_prefix(void *fdt, int offs, const char *prefix) -{ - const size_t prefix_len = strlen(prefix); - size_t l; - int plen; - const char *prop; - - prop = fdt_getprop(fdt, offs, "compatible", &plen); - if (!prop) - return -1; - - while (plen > 0) { - if (memcmp(prop, prefix, prefix_len) == 0) - return 0; /* match */ - - l = strlen(prop) + 1; - prop += l; - plen -= l; - } - - return -1; -} - -int dt_add_psci_cpu_enable_methods(void *fdt) -{ - int offs = 0; - - while (1) { - offs = fdt_next_node(fdt, offs, NULL); - if (offs < 0) - break; - if (fdt_getprop(fdt, offs, "enable-method", NULL)) - continue; /* already set */ - if (check_node_compat_prefix(fdt, offs, "arm,cortex-a")) - continue; /* no compatible */ - if (fdt_setprop_string(fdt, offs, "enable-method", "psci")) - return -1; - /* Need to restart scanning as offsets may have changed */ - offs = 0; - } - return 0; -} diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk index 6b9749c79..bc4a21bc0 100644 --- a/plat/qemu/platform.mk +++ b/plat/qemu/platform.mk @@ -114,7 +114,7 @@ BL2_SOURCES += drivers/io/io_semihosting.c \ plat/qemu/qemu_io_storage.c \ plat/qemu/${ARCH}/plat_helpers.S \ plat/qemu/qemu_bl2_setup.c \ - plat/qemu/dt.c \ + common/fdt_fixup.c \ plat/qemu/qemu_bl2_mem_params_desc.c \ plat/qemu/qemu_image_load.c \ common/desc_image_load.c diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c index 4c97c8dd6..166d2454e 100644 --- a/plat/qemu/qemu_bl2_setup.c +++ b/plat/qemu/qemu_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/plat/qemu/qemu_private.h b/plat/qemu/qemu_private.h index 46b1ca1e9..71ea4de10 100644 --- a/plat/qemu/qemu_private.h +++ b/plat/qemu/qemu_private.h @@ -28,9 +28,6 @@ void qemu_configure_mmu_el3(unsigned long total_base, unsigned long total_size, void plat_qemu_io_setup(void); unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); -int dt_add_psci_node(void *fdt); -int dt_add_psci_cpu_enable_methods(void *fdt); - void qemu_console_init(void); void plat_qemu_gic_init(void); -- cgit v1.2.3 From e6fd00ab0a52fcdb130c343e0748f440200d9ae2 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 23:04:26 +0100 Subject: rpi3: Prepare for supporting a GIC (in RPi4) As the PSCI "power" management functions for the Raspberry Pi 3 port will be shared with the upcoming RPi4 support, we need to prepare them for dealing with the GIC interrupt controller. Splitting this code just for those simple calls to the generic GIC routines does not seem worthwhile, so just use a #define the protect the GIC code from being included by the existing RPi3 code. Change-Id: Iaca6b0214563852b28ad4a088ec45348ae8be40d Signed-off-by: Andre Przywara --- plat/rpi/common/rpi3_pm.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/plat/rpi/common/rpi3_pm.c b/plat/rpi/common/rpi3_pm.c index b79e2736e..8c2d070c4 100644 --- a/plat/rpi/common/rpi3_pm.c +++ b/plat/rpi/common/rpi3_pm.c @@ -17,6 +17,10 @@ #include +#ifdef RPI_HAVE_GIC +#include +#endif + /* Make composite power state parameter till power level 0 */ #if PSCI_EXTENDED_STATE_ID @@ -112,6 +116,13 @@ static void rpi3_cpu_standby(plat_local_state_t cpu_state) wfi(); } +static void rpi3_pwr_domain_off(const psci_power_state_t *target_state) +{ +#ifdef RPI_HAVE_GIC + gicv2_cpuif_disable(); +#endif +} + /******************************************************************************* * Platform handler called when a power domain is about to be turned on. The * mpidr determines the CPU to be turned on. @@ -144,6 +155,11 @@ static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state) { assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == PLAT_LOCAL_STATE_OFF); + +#ifdef RPI_HAVE_GIC + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +#endif } /******************************************************************************* @@ -207,6 +223,7 @@ static void __dead2 rpi3_system_off(void) ******************************************************************************/ static const plat_psci_ops_t plat_rpi3_psci_pm_ops = { .cpu_standby = rpi3_cpu_standby, + .pwr_domain_off = rpi3_pwr_domain_off, .pwr_domain_on = rpi3_pwr_domain_on, .pwr_domain_on_finish = rpi3_pwr_domain_on_finish, .system_off = rpi3_system_off, -- cgit v1.2.3 From ab13addd845e596fb5fba51da8d0f672cdf35eff Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 9 Jul 2019 11:18:59 +0100 Subject: rpi3: Add "rpi" platform directory With the incoming support for the Raspberry Pi 4 boards, one directory to serve both versions will not end up well. Create an additional layer by inserting a "rpi" directory betweeen /plat and rpi3, so that we can more easily share or separate files between the two later. Change-Id: I75adbb054fe7902f34db0fd5e579a55612dd8a5f Signed-off-by: Andre Przywara --- plat/rpi/rpi3/aarch64/plat_helpers.S | 179 +++++++++++++++ plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c | 136 ++++++++++++ plat/rpi/rpi3/include/plat_macros.S | 20 ++ plat/rpi/rpi3/include/platform_def.h | 261 ++++++++++++++++++++++ plat/rpi/rpi3/platform.mk | 218 ++++++++++++++++++ plat/rpi/rpi3/rpi3_bl1_setup.c | 95 ++++++++ plat/rpi/rpi3/rpi3_bl2_setup.c | 155 +++++++++++++ plat/rpi/rpi3/rpi3_bl31_setup.c | 214 ++++++++++++++++++ plat/rpi/rpi3/rpi3_common.c | 232 +++++++++++++++++++ plat/rpi/rpi3/rpi3_hw.h | 110 +++++++++ plat/rpi/rpi3/rpi3_image_load.c | 36 +++ plat/rpi/rpi3/rpi3_io_storage.c | 271 +++++++++++++++++++++++ plat/rpi/rpi3/rpi3_mbox.c | 148 +++++++++++++ plat/rpi/rpi3/rpi3_pm.c | 226 +++++++++++++++++++ plat/rpi/rpi3/rpi3_private.h | 42 ++++ plat/rpi/rpi3/rpi3_rng.c | 75 +++++++ plat/rpi/rpi3/rpi3_rotpk.S | 15 ++ plat/rpi/rpi3/rpi3_stack_protector.c | 29 +++ plat/rpi/rpi3/rpi3_topology.c | 58 +++++ plat/rpi/rpi3/rpi3_trusted_boot.c | 36 +++ plat/rpi3/aarch64/plat_helpers.S | 179 --------------- plat/rpi3/aarch64/rpi3_bl2_mem_params_desc.c | 136 ------------ plat/rpi3/include/plat_macros.S | 20 -- plat/rpi3/include/platform_def.h | 261 ---------------------- plat/rpi3/platform.mk | 218 ------------------ plat/rpi3/rpi3_bl1_setup.c | 95 -------- plat/rpi3/rpi3_bl2_setup.c | 155 ------------- plat/rpi3/rpi3_bl31_setup.c | 214 ------------------ plat/rpi3/rpi3_common.c | 232 ------------------- plat/rpi3/rpi3_hw.h | 110 --------- plat/rpi3/rpi3_image_load.c | 36 --- plat/rpi3/rpi3_io_storage.c | 271 ----------------------- plat/rpi3/rpi3_mbox.c | 148 ------------- plat/rpi3/rpi3_pm.c | 226 ------------------- plat/rpi3/rpi3_private.h | 42 ---- plat/rpi3/rpi3_rng.c | 75 ------- plat/rpi3/rpi3_rotpk.S | 15 -- plat/rpi3/rpi3_stack_protector.c | 29 --- plat/rpi3/rpi3_topology.c | 58 ----- plat/rpi3/rpi3_trusted_boot.c | 36 --- 40 files changed, 2556 insertions(+), 2556 deletions(-) create mode 100644 plat/rpi/rpi3/aarch64/plat_helpers.S create mode 100644 plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c create mode 100644 plat/rpi/rpi3/include/plat_macros.S create mode 100644 plat/rpi/rpi3/include/platform_def.h create mode 100644 plat/rpi/rpi3/platform.mk create mode 100644 plat/rpi/rpi3/rpi3_bl1_setup.c create mode 100644 plat/rpi/rpi3/rpi3_bl2_setup.c create mode 100644 plat/rpi/rpi3/rpi3_bl31_setup.c create mode 100644 plat/rpi/rpi3/rpi3_common.c create mode 100644 plat/rpi/rpi3/rpi3_hw.h create mode 100644 plat/rpi/rpi3/rpi3_image_load.c create mode 100644 plat/rpi/rpi3/rpi3_io_storage.c create mode 100644 plat/rpi/rpi3/rpi3_mbox.c create mode 100644 plat/rpi/rpi3/rpi3_pm.c create mode 100644 plat/rpi/rpi3/rpi3_private.h create mode 100644 plat/rpi/rpi3/rpi3_rng.c create mode 100644 plat/rpi/rpi3/rpi3_rotpk.S create mode 100644 plat/rpi/rpi3/rpi3_stack_protector.c create mode 100644 plat/rpi/rpi3/rpi3_topology.c create mode 100644 plat/rpi/rpi3/rpi3_trusted_boot.c delete mode 100644 plat/rpi3/aarch64/plat_helpers.S delete mode 100644 plat/rpi3/aarch64/rpi3_bl2_mem_params_desc.c delete mode 100644 plat/rpi3/include/plat_macros.S delete mode 100644 plat/rpi3/include/platform_def.h delete mode 100644 plat/rpi3/platform.mk delete mode 100644 plat/rpi3/rpi3_bl1_setup.c delete mode 100644 plat/rpi3/rpi3_bl2_setup.c delete mode 100644 plat/rpi3/rpi3_bl31_setup.c delete mode 100644 plat/rpi3/rpi3_common.c delete mode 100644 plat/rpi3/rpi3_hw.h delete mode 100644 plat/rpi3/rpi3_image_load.c delete mode 100644 plat/rpi3/rpi3_io_storage.c delete mode 100644 plat/rpi3/rpi3_mbox.c delete mode 100644 plat/rpi3/rpi3_pm.c delete mode 100644 plat/rpi3/rpi3_private.h delete mode 100644 plat/rpi3/rpi3_rng.c delete mode 100644 plat/rpi3/rpi3_rotpk.S delete mode 100644 plat/rpi3/rpi3_stack_protector.c delete mode 100644 plat/rpi3/rpi3_topology.c delete mode 100644 plat/rpi3/rpi3_trusted_boot.c diff --git a/plat/rpi/rpi3/aarch64/plat_helpers.S b/plat/rpi/rpi3/aarch64/plat_helpers.S new file mode 100644 index 000000000..7974b602d --- /dev/null +++ b/plat/rpi/rpi3/aarch64/plat_helpers.S @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include "../rpi3_hw.h" + + .globl plat_crash_console_flush + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl platform_mem_init + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_reset_handler + .globl plat_rpi3_calc_core_pos + .globl plat_secondary_cold_boot_setup + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * + * This function uses the plat_rpi3_calc_core_pos() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_rpi3_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr); + * + * CorePos = (ClusterId * 4) + CoreId + * ----------------------------------------------------- + */ +func plat_rpi3_calc_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc plat_rpi3_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #RPI3_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* Calculate address of our hold entry */ + bl plat_my_core_pos + lsl x0, x0, #3 + mov_imm x2, PLAT_RPI3_TM_HOLD_BASE + add x0, x0, x2 + + /* + * This code runs way before requesting the warmboot of this core, + * so it is possible to clear the mailbox before getting a request + * to boot. + */ + mov x1, PLAT_RPI3_TM_HOLD_STATE_WAIT + str x1,[x0] + + /* Wait until we have a go */ +poll_mailbox: + wfe + ldr x1, [x0] + cmp x1, PLAT_RPI3_TM_HOLD_STATE_GO + bne poll_mailbox + + /* Jump to the provided entrypoint */ + mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT + ldr x1, [x0] + br x1 +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * uintptr_t plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and a warm + * boot. + * + * This functions returns: + * - 0 for a cold boot. + * - Any other value for a warm boot. + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* TODO: support warm boot */ + mov x0, #0 + ret +endfunc plat_get_my_entrypoint + + /* --------------------------------------------- + * void platform_mem_init (void); + * + * No need to carry out any memory initialization. + * --------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0 - x3 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, PLAT_RPI3_UART_BASE + mov_imm x1, PLAT_RPI3_UART_CLK_IN_HZ + mov_imm x2, PLAT_RPI3_UART_BAUDRATE + b console_16550_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_RPI3_UART_BASE + b console_16550_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush() + * Function to force a write of all buffered + * data that hasn't been output. + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x0, PLAT_RPI3_UART_BASE + b console_16550_core_flush +endfunc plat_crash_console_flush + + /* --------------------------------------------- + * void plat_reset_handler(void); + * --------------------------------------------- + */ +func plat_reset_handler + /* use the 19.2 MHz clock for the architected timer */ + mov x0, #RPI3_INTC_BASE_ADDRESS + mov w1, #0x80000000 + str wzr, [x0, #RPI3_INTC_CONTROL_OFFSET] + str w1, [x0, #RPI3_INTC_PRESCALER_OFFSET] + ret +endfunc plat_reset_handler diff --git a/plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c b/plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c new file mode 100644 index 000000000..715aec410 --- /dev/null +++ b/plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +/******************************************************************************* + * Following descriptor provides BL image/ep information that gets used + * by BL2 to load the images and also subset of this information is + * passed to next BL image. The image loading sequence is managed by + * populating the images in required loading order. The image execution + * sequence is managed by populating the `next_handoff_image_id` with + * the next executable image id. + ******************************************************************************/ +static bl_mem_params_node_t bl2_mem_params_descs[] = { + + /* Fill BL31 related information */ + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), +#if DEBUG + .ep_info.args.arg1 = RPI3_BL31_PLAT_PARAM_VAL, +#endif + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + +# ifdef BL32_BASE + .next_handoff_image_id = BL32_IMAGE_ID, +# else + .next_handoff_image_id = BL33_IMAGE_ID, +# endif + }, + +# ifdef BL32_BASE + /* Fill BL32 related information */ + { + .image_id = BL32_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + + .next_handoff_image_id = BL33_IMAGE_ID, + }, + + /* + * Fill BL32 external 1 related information. + * A typical use for extra1 image is with OP-TEE where it is the pager + * image. + */ + { + .image_id = BL32_EXTRA1_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + + /* + * Fill BL32 external 2 related information. + * A typical use for extra2 image is with OP-TEE where it is the paged + * image. + */ + { + .image_id = BL32_EXTRA2_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_SKIP_LOADING), +#ifdef SPD_opteed + .image_info.image_base = RPI3_OPTEE_PAGEABLE_LOAD_BASE, + .image_info.image_max_size = RPI3_OPTEE_PAGEABLE_LOAD_SIZE, +#endif + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +# endif /* BL32_BASE */ + + /* Fill BL33 related information */ + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + NON_SECURE | EXECUTABLE), +# ifdef PRELOADED_BL33_BASE + .ep_info.pc = PRELOADED_BL33_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_SKIP_LOADING), +# else + .ep_info.pc = PLAT_RPI3_NS_IMAGE_OFFSET, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_RPI3_NS_IMAGE_OFFSET, + .image_info.image_max_size = PLAT_RPI3_NS_IMAGE_MAX_SIZE, +# endif /* PRELOADED_BL33_BASE */ + + .next_handoff_image_id = INVALID_IMAGE_ID, + } +}; + +REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/rpi/rpi3/include/plat_macros.S b/plat/rpi/rpi3/include/plat_macros.S new file mode 100644 index 000000000..c0c396791 --- /dev/null +++ b/plat/rpi/rpi3/include/plat_macros.S @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/rpi/rpi3/include/platform_def.h b/plat/rpi/rpi3/include/platform_def.h new file mode 100644 index 000000000..4d902225f --- /dev/null +++ b/plat/rpi/rpi3/include/platform_def.h @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include +#include +#include + +#include "../rpi3_hw.h" + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) + +#define PLATFORM_STACK_SIZE ULL(0x1000) + +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT + +#define RPI3_PRIMARY_CPU U(0) + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET U(1) +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF U(2) + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH U(4) +#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +/* + * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and + * secure DRAM. Note that this is all actually DRAM with different names, + * there is no Secure RAM in the Raspberry Pi 3. + */ +#if RPI3_USE_UEFI_MAP +#define SEC_ROM_BASE ULL(0x00000000) +#define SEC_ROM_SIZE ULL(0x00010000) + +/* FIP placed after ROM to append it to BL1 with very little padding. */ +#define PLAT_RPI3_FIP_BASE ULL(0x00020000) +#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x00010000) + +/* Reserve 2M of secure SRAM and DRAM, starting at 2M */ +#define SEC_SRAM_BASE ULL(0x00200000) +#define SEC_SRAM_SIZE ULL(0x00100000) + +#define SEC_DRAM0_BASE ULL(0x00300000) +#define SEC_DRAM0_SIZE ULL(0x00100000) + +/* Windows on ARM requires some RAM at 4M */ +#define NS_DRAM0_BASE ULL(0x00400000) +#define NS_DRAM0_SIZE ULL(0x00C00000) +#else +#define SEC_ROM_BASE ULL(0x00000000) +#define SEC_ROM_SIZE ULL(0x00020000) + +/* FIP placed after ROM to append it to BL1 with very little padding. */ +#define PLAT_RPI3_FIP_BASE ULL(0x00020000) +#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x001E0000) + +/* We have 16M of memory reserved starting at 256M */ +#define SEC_SRAM_BASE ULL(0x10000000) +#define SEC_SRAM_SIZE ULL(0x00100000) + +#define SEC_DRAM0_BASE ULL(0x10100000) +#define SEC_DRAM0_SIZE ULL(0x00F00000) +/* End of reserved memory */ + +#define NS_DRAM0_BASE ULL(0x11000000) +#define NS_DRAM0_SIZE ULL(0x01000000) +#endif /* RPI3_USE_UEFI_MAP */ + +/* + * BL33 entrypoint. + */ +#define PLAT_RPI3_NS_IMAGE_OFFSET NS_DRAM0_BASE +#define PLAT_RPI3_NS_IMAGE_MAX_SIZE NS_DRAM0_SIZE + +/* + * I/O registers. + */ +#define DEVICE0_BASE RPI3_IO_BASE +#define DEVICE0_SIZE RPI3_IO_SIZE + +/* + * Arm TF lives in SRAM, partition it here + */ +#define SHARED_RAM_BASE SEC_SRAM_BASE +#define SHARED_RAM_SIZE ULL(0x00001000) + +#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) +#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) + +/* + * Mailbox to control the secondary cores.All secondary cores are held in a wait + * loop in cold boot. To release them perform the following steps (plus any + * additional barriers that may be needed): + * + * uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT; + * *entrypoint = ADDRESS_TO_JUMP_TO; + * + * uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; + * mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO; + * + * sev(); + */ +#define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE + +/* The secure entry point to be used on warm reset by all CPUs. */ +#define PLAT_RPI3_TM_ENTRYPOINT PLAT_RPI3_TRUSTED_MAILBOX_BASE +#define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8) + +/* Hold entries for each CPU. */ +#define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \ + PLAT_RPI3_TM_ENTRYPOINT_SIZE) +#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8) +#define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \ + PLATFORM_CORE_COUNT) + +#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \ + PLAT_RPI3_TM_HOLD_SIZE) + +#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0) +#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1) + +/* + * BL1 specific defines. + * + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + * + * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using + * the current BL1 RW debug size plus a little space for growth. + */ +#define PLAT_MAX_BL1_RW_SIZE ULL(0x12000) + +#define BL1_RO_BASE SEC_ROM_BASE +#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) +#define BL1_RW_BASE (BL1_RW_LIMIT - PLAT_MAX_BL1_RW_SIZE) +#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) + +/* + * BL2 specific defines. + * + * Put BL2 just below BL31. BL2_BASE is calculated using the current BL2 debug + * size plus a little space for growth. + */ +#define PLAT_MAX_BL2_SIZE ULL(0x2C000) + +#define BL2_BASE (BL2_LIMIT - PLAT_MAX_BL2_SIZE) +#define BL2_LIMIT BL31_BASE + +/* + * BL31 specific defines. + * + * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the + * current BL31 debug size plus a little space for growth. + */ +#define PLAT_MAX_BL31_SIZE ULL(0x20000) + +#define BL31_BASE (BL31_LIMIT - PLAT_MAX_BL31_SIZE) +#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) +#define BL31_PROGBITS_LIMIT BL1_RW_BASE + +/* + * BL32 specific defines. + * + * BL32 can execute from Secure SRAM or Secure DRAM. + */ +#define BL32_SRAM_BASE BL_RAM_BASE +#define BL32_SRAM_LIMIT BL31_BASE +#define BL32_DRAM_BASE SEC_DRAM0_BASE +#define BL32_DRAM_LIMIT (SEC_DRAM0_BASE + SEC_DRAM0_SIZE) + +#ifdef SPD_opteed +/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ +#define RPI3_OPTEE_PAGEABLE_LOAD_SIZE 0x080000 /* 512KB */ +#define RPI3_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - \ + RPI3_OPTEE_PAGEABLE_LOAD_SIZE) +#endif + +#define SEC_SRAM_ID 0 +#define SEC_DRAM_ID 1 + +#if RPI3_BL32_RAM_LOCATION_ID == SEC_SRAM_ID +# define BL32_MEM_BASE BL_RAM_BASE +# define BL32_MEM_SIZE BL_RAM_SIZE +# define BL32_BASE BL32_SRAM_BASE +# define BL32_LIMIT BL32_SRAM_LIMIT +#elif RPI3_BL32_RAM_LOCATION_ID == SEC_DRAM_ID +# define BL32_MEM_BASE SEC_DRAM0_BASE +# define BL32_MEM_SIZE SEC_DRAM0_SIZE +# define BL32_BASE BL32_DRAM_BASE +# define BL32_LIMIT BL32_DRAM_LIMIT +#else +# error "Unsupported RPI3_BL32_RAM_LOCATION_ID value" +#endif +#define BL32_SIZE (BL32_LIMIT - BL32_BASE) + +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ + +/* + * Other memory-related defines. + */ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) + +#define MAX_MMAP_REGIONS 8 +#define MAX_XLAT_TABLES 4 + +#define MAX_IO_DEVICES U(3) +#define MAX_IO_HANDLES U(4) + +#define MAX_IO_BLOCK_DEVICES U(1) + +/* + * Serial-related constants. + */ +#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE +#define PLAT_RPI3_UART_CLK_IN_HZ RPI3_MINI_UART_CLK_IN_HZ +#define PLAT_RPI3_UART_BAUDRATE ULL(115200) + +/* + * System counter + */ +#define SYS_COUNTER_FREQ_IN_TICKS ULL(19200000) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk new file mode 100644 index 000000000..c011c0a70 --- /dev/null +++ b/plat/rpi/rpi3/platform.mk @@ -0,0 +1,218 @@ +# +# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include lib/libfdt/libfdt.mk +include lib/xlat_tables_v2/xlat_tables.mk + +PLAT_INCLUDES := -Iplat/rpi/rpi3/include + +PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \ + plat/rpi/rpi3/rpi3_common.c \ + ${XLAT_TABLES_LIB_SRCS} + +BL1_SOURCES += drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + lib/cpus/aarch64/cortex_a53.S \ + plat/common/aarch64/platform_mp_stack.S \ + plat/rpi/rpi3/aarch64/plat_helpers.S \ + plat/rpi/rpi3/rpi3_bl1_setup.c \ + plat/rpi/rpi3/rpi3_io_storage.c \ + plat/rpi/rpi3/rpi3_mbox.c + +BL2_SOURCES += common/desc_image_load.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + drivers/gpio/gpio.c \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/rpi3/gpio/rpi3_gpio.c \ + drivers/io/io_block.c \ + drivers/mmc/mmc.c \ + drivers/rpi3/sdhost/rpi3_sdhost.c \ + plat/common/aarch64/platform_mp_stack.S \ + plat/rpi/rpi3/aarch64/plat_helpers.S \ + plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c \ + plat/rpi/rpi3/rpi3_bl2_setup.c \ + plat/rpi/rpi3/rpi3_image_load.c \ + plat/rpi/rpi3/rpi3_io_storage.c + +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + plat/common/plat_psci_common.c \ + plat/rpi/rpi3/aarch64/plat_helpers.S \ + plat/rpi/rpi3/rpi3_bl31_setup.c \ + plat/rpi/rpi3/rpi3_pm.c \ + plat/rpi/rpi3/rpi3_topology.c \ + ${LIBFDT_SRCS} + +# Tune compiler for Cortex-A53 +ifeq ($(notdir $(CC)),armclang) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else ifneq ($(findstring clang,$(notdir $(CC))),) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else + TF_CFLAGS_aarch64 += -mtune=cortex-a53 +endif + +# Platform Makefile target +# ------------------------ + +RPI3_BL1_PAD_BIN := ${BUILD_PLAT}/bl1_pad.bin +RPI3_ARMSTUB8_BIN := ${BUILD_PLAT}/armstub8.bin + +# Add new default target when compiling this platform +all: armstub + +# This target concatenates BL1 and the FIP so that the base addresses match the +# ones defined in the memory map +armstub: bl1 fip + @echo " CAT $@" + ${Q}cp ${BUILD_PLAT}/bl1.bin ${RPI3_BL1_PAD_BIN} + ${Q}truncate --size=131072 ${RPI3_BL1_PAD_BIN} + ${Q}cat ${RPI3_BL1_PAD_BIN} ${BUILD_PLAT}/fip.bin > ${RPI3_ARMSTUB8_BIN} + @${ECHO_BLANK_LINE} + @echo "Built $@ successfully" + @${ECHO_BLANK_LINE} + +# Build config flags +# ------------------ + +# Enable all errata workarounds for Cortex-A53 +ERRATA_A53_826319 := 1 +ERRATA_A53_835769 := 1 +ERRATA_A53_836870 := 1 +ERRATA_A53_843419 := 1 +ERRATA_A53_855873 := 1 + +WORKAROUND_CVE_2017_5715 := 0 + +# Disable stack protector by default +ENABLE_STACK_PROTECTOR := 0 + +# Reset to BL31 isn't supported +RESET_TO_BL31 := 0 + +# Have different sections for code and rodata +SEPARATE_CODE_AND_RODATA := 1 + +# Use Coherent memory +USE_COHERENT_MEM := 1 + +# Platform build flags +# -------------------- + +# BL33 images are in AArch64 by default +RPI3_BL33_IN_AARCH32 := 0 + +# Assume that BL33 isn't the Linux kernel by default +RPI3_DIRECT_LINUX_BOOT := 0 + +# UART to use at runtime. -1 means the runtime UART is disabled. +# Any other value means the default UART will be used. +RPI3_RUNTIME_UART := -1 + +# Use normal memory mapping for ROM, FIP, SRAM and DRAM +RPI3_USE_UEFI_MAP := 0 + +# BL32 location +RPI3_BL32_RAM_LOCATION := tdram +ifeq (${RPI3_BL32_RAM_LOCATION}, tsram) + RPI3_BL32_RAM_LOCATION_ID = SEC_SRAM_ID +else ifeq (${RPI3_BL32_RAM_LOCATION}, tdram) + RPI3_BL32_RAM_LOCATION_ID = SEC_DRAM_ID +else + $(error "Unsupported RPI3_BL32_RAM_LOCATION value") +endif + +# Process platform flags +# ---------------------- + +$(eval $(call add_define,RPI3_BL32_RAM_LOCATION_ID)) +$(eval $(call add_define,RPI3_BL33_IN_AARCH32)) +$(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT)) +ifdef RPI3_PRELOADED_DTB_BASE +$(eval $(call add_define,RPI3_PRELOADED_DTB_BASE)) +endif +$(eval $(call add_define,RPI3_RUNTIME_UART)) +$(eval $(call add_define,RPI3_USE_UEFI_MAP)) + +# Verify build config +# ------------------- +# +ifneq (${RPI3_DIRECT_LINUX_BOOT}, 0) + ifndef RPI3_PRELOADED_DTB_BASE + $(error Error: RPI3_PRELOADED_DTB_BASE needed if RPI3_DIRECT_LINUX_BOOT=1) + endif +endif + +ifneq (${RESET_TO_BL31}, 0) + $(error Error: rpi3 needs RESET_TO_BL31=0) +endif + +ifeq (${ARCH},aarch32) + $(error Error: AArch32 not supported on rpi3) +endif + +ifneq ($(ENABLE_STACK_PROTECTOR), 0) +PLAT_BL_COMMON_SOURCES += plat/rpi/rpi3/rpi3_rng.c \ + plat/rpi/rpi3/rpi3_stack_protector.c +endif + +ifeq (${SPD},opteed) +BL2_SOURCES += \ + lib/optee/optee_utils.c +endif + +# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images +# in the FIP if the platform requires. +ifneq ($(BL32_EXTRA1),) +$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1)) +endif +ifneq ($(BL32_EXTRA2),) +$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2)) +endif + +ifneq (${TRUSTED_BOARD_BOOT},0) + + include drivers/auth/mbedtls/mbedtls_crypto.mk + include drivers/auth/mbedtls/mbedtls_x509.mk + + AUTH_SOURCES := drivers/auth/auth_mod.c \ + drivers/auth/crypto_mod.c \ + drivers/auth/img_parser_mod.c \ + drivers/auth/tbbr/tbbr_cot.c + + BL1_SOURCES += ${AUTH_SOURCES} \ + bl1/tbbr/tbbr_img_desc.c \ + plat/common/tbbr/plat_tbbr.c \ + plat/rpi/rpi3/rpi3_trusted_boot.c \ + plat/rpi/rpi3/rpi3_rotpk.S + + BL2_SOURCES += ${AUTH_SOURCES} \ + plat/common/tbbr/plat_tbbr.c \ + plat/rpi/rpi3/rpi3_trusted_boot.c \ + plat/rpi/rpi3/rpi3_rotpk.S + + ROT_KEY = $(BUILD_PLAT)/rot_key.pem + ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin + + $(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) + + $(BUILD_PLAT)/bl1/rpi3_rotpk.o: $(ROTPK_HASH) + $(BUILD_PLAT)/bl2/rpi3_rotpk.o: $(ROTPK_HASH) + + certificates: $(ROT_KEY) + + $(ROT_KEY): + @echo " OPENSSL $@" + $(Q)openssl genrsa 2048 > $@ 2>/dev/null + + $(ROTPK_HASH): $(ROT_KEY) + @echo " OPENSSL $@" + $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + openssl dgst -sha256 -binary > $@ 2>/dev/null +endif diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c new file mode 100644 index 000000000..b869e9da8 --- /dev/null +++ b/plat/rpi/rpi3/rpi3_bl1_setup.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include "rpi3_private.h" + +/* Data structure which holds the extents of the trusted SRAM for BL1 */ +static meminfo_t bl1_tzram_layout; + +meminfo_t *bl1_plat_sec_mem_layout(void) +{ + return &bl1_tzram_layout; +} + +/******************************************************************************* + * Perform any BL1 specific platform actions. + ******************************************************************************/ +void bl1_early_platform_setup(void) +{ + /* Initialize the console to provide early debug support */ + rpi3_console_init(); + + /* Allow BL1 to see the whole Trusted RAM */ + bl1_tzram_layout.total_base = BL_RAM_BASE; + bl1_tzram_layout.total_size = BL_RAM_SIZE; +} + +/****************************************************************************** + * Perform the very early platform specific architecture setup. This only + * does basic initialization. Later architectural setup (bl1_arch_setup()) + * does not do anything platform specific. + *****************************************************************************/ +void bl1_plat_arch_setup(void) +{ + rpi3_setup_page_tables(bl1_tzram_layout.total_base, + bl1_tzram_layout.total_size, + BL_CODE_BASE, BL1_CODE_END, + BL1_RO_DATA_BASE, BL1_RO_DATA_END +#if USE_COHERENT_MEM + , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END +#endif + ); + + enable_mmu_el3(0); +} + +void bl1_platform_setup(void) +{ + uint32_t __unused rev; + int __unused rc; + + rc = rpi3_vc_hardware_get_board_revision(&rev); + + if (rc == 0) { + const char __unused *model, __unused *info; + + switch (rev) { + case 0xA02082: + model = "Raspberry Pi 3 Model B"; + info = "(1GB, Sony, UK)"; + break; + case 0xA22082: + model = "Raspberry Pi 3 Model B"; + info = "(1GB, Embest, China)"; + break; + case 0xA020D3: + model = "Raspberry Pi 3 Model B+"; + info = "(1GB, Sony, UK)"; + break; + default: + model = "Unknown"; + info = "(Unknown)"; + ERROR("rpi3: Unknown board revision 0x%08x\n", rev); + break; + } + + NOTICE("rpi3: Detected: %s %s [0x%08x]\n", model, info, rev); + } else { + ERROR("rpi3: Unable to detect board revision\n"); + } + + /* Initialise the IO layer and register platform IO devices */ + plat_rpi3_io_setup(); +} diff --git a/plat/rpi/rpi3/rpi3_bl2_setup.c b/plat/rpi/rpi3/rpi3_bl2_setup.c new file mode 100644 index 000000000..b5e58352a --- /dev/null +++ b/plat/rpi/rpi3/rpi3_bl2_setup.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rpi3_private.h" + +/* Data structure which holds the extents of the trusted SRAM for BL2 */ +static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); + +/* rpi3 GPIO setup function. */ +static void rpi3_gpio_setup(void) +{ + struct rpi3_gpio_params params; + + memset(¶ms, 0, sizeof(struct rpi3_gpio_params)); + params.reg_base = RPI3_GPIO_BASE; + + rpi3_gpio_init(¶ms); +} + +/* Data structure which holds the MMC info */ +static struct mmc_device_info mmc_info; + +static void rpi3_sdhost_setup(void) +{ + struct rpi3_sdhost_params params; + + memset(¶ms, 0, sizeof(struct rpi3_sdhost_params)); + params.reg_base = RPI3_SDHOST_BASE; + params.bus_width = MMC_BUS_WIDTH_1; + params.clk_rate = 50000000; + mmc_info.mmc_dev_type = MMC_IS_SD_HC; + rpi3_sdhost_init(¶ms, &mmc_info); +} + +/******************************************************************************* + * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 + * in x0. This memory layout is sitting at the base of the free trusted SRAM. + * Copy it to a safe location before its reclaimed by later BL2 functionality. + ******************************************************************************/ + +void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + meminfo_t *mem_layout = (meminfo_t *) arg1; + + /* Initialize the console to provide early debug support */ + rpi3_console_init(); + + /* Enable arch timer */ + generic_delay_timer_init(); + + /* Setup GPIO driver */ + rpi3_gpio_setup(); + + /* Setup the BL2 memory layout */ + bl2_tzram_layout = *mem_layout; + + /* Setup SDHost driver */ + rpi3_sdhost_setup(); + + plat_rpi3_io_setup(); +} + +void bl2_platform_setup(void) +{ + /* + * This is where a TrustZone address space controller and other + * security related peripherals would be configured. + */ +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. + ******************************************************************************/ +void bl2_plat_arch_setup(void) +{ + rpi3_setup_page_tables(bl2_tzram_layout.total_base, + bl2_tzram_layout.total_size, + BL_CODE_BASE, BL_CODE_END, + BL_RO_DATA_BASE, BL_RO_DATA_END +#if USE_COHERENT_MEM + , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END +#endif + ); + + enable_mmu_el1(0); +} + +/******************************************************************************* + * This function can be used by the platforms to update/use image + * information for given `image_id`. + ******************************************************************************/ +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + int err = 0; + bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); +#ifdef SPD_opteed + bl_mem_params_node_t *pager_mem_params = NULL; + bl_mem_params_node_t *paged_mem_params = NULL; +#endif + + assert(bl_mem_params != NULL); + + switch (image_id) { + case BL32_IMAGE_ID: +#ifdef SPD_opteed + pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); + assert(pager_mem_params); + + paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); + assert(paged_mem_params); + + err = parse_optee_header(&bl_mem_params->ep_info, + &pager_mem_params->image_info, + &paged_mem_params->image_info); + if (err != 0) + WARN("OPTEE header parse error.\n"); +#endif + bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl32_entry(); + break; + + case BL33_IMAGE_ID: + /* BL33 expects to receive the primary CPU MPID (through r0) */ + bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); + bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry(); + + /* Shutting down the SDHost driver to let BL33 drives SDHost.*/ + rpi3_sdhost_stop(); + break; + + default: + /* Do nothing in default case */ + break; + } + + return err; +} diff --git a/plat/rpi/rpi3/rpi3_bl31_setup.c b/plat/rpi/rpi3/rpi3_bl31_setup.c new file mode 100644 index 000000000..2f1bc6493 --- /dev/null +++ b/plat/rpi/rpi3/rpi3_bl31_setup.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include +#include +#include +#include + +#include "rpi3_private.h" + +/* + * Placeholder variables for copying the arguments that have been passed to + * BL31 from BL2. + */ +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(sec_state_is_valid(type) != 0); + + next_image_info = (type == NON_SECURE) + ? &bl33_image_ep_info : &bl32_image_ep_info; + + /* None of the images can have 0x0 as the entrypoint. */ + if (next_image_info->pc) { + return next_image_info; + } else { + return NULL; + } +} + +/******************************************************************************* + * Perform any BL31 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before + * they are lost (potentially). This needs to be done before the MMU is + * initialized so that the memory layout can be used while creating page + * tables. BL2 has flushed this information to memory, so we are guaranteed + * to pick up good data. + ******************************************************************************/ +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) + +{ + /* Initialize the console to provide early debug support */ + rpi3_console_init(); + + /* + * In debug builds, a special value is passed in 'arg1' to verify + * platform parameters from BL2 to BL31. Not used in release builds. + */ + assert(arg1 == RPI3_BL31_PLAT_PARAM_VAL); + + /* Check that params passed from BL2 are not NULL. */ + bl_params_t *params_from_bl2 = (bl_params_t *) arg0; + + assert(params_from_bl2 != NULL); + assert(params_from_bl2->h.type == PARAM_BL_PARAMS); + assert(params_from_bl2->h.version >= VERSION_2); + + bl_params_node_t *bl_params = params_from_bl2->head; + + /* + * Copy BL33 and BL32 (if present), entry point information. + * They are stored in Secure RAM, in BL2's address space. + */ + while (bl_params) { + if (bl_params->image_id == BL32_IMAGE_ID) { + bl32_image_ep_info = *bl_params->ep_info; + } + + if (bl_params->image_id == BL33_IMAGE_ID) { + bl33_image_ep_info = *bl_params->ep_info; + } + + bl_params = bl_params->next_params_info; + } + + if (bl33_image_ep_info.pc == 0) { + panic(); + } + +#if RPI3_DIRECT_LINUX_BOOT +# if RPI3_BL33_IN_AARCH32 + /* + * According to the file ``Documentation/arm/Booting`` of the Linux + * kernel tree, Linux expects: + * r0 = 0 + * r1 = machine type number, optional in DT-only platforms (~0 if so) + * r2 = Physical address of the device tree blob + */ + VERBOSE("rpi3: Preparing to boot 32-bit Linux kernel\n"); + bl33_image_ep_info.args.arg0 = 0U; + bl33_image_ep_info.args.arg1 = ~0U; + bl33_image_ep_info.args.arg2 = (u_register_t) RPI3_PRELOADED_DTB_BASE; +# else + /* + * According to the file ``Documentation/arm64/booting.txt`` of the + * Linux kernel tree, Linux expects the physical address of the device + * tree blob (DTB) in x0, while x1-x3 are reserved for future use and + * must be 0. + */ + VERBOSE("rpi3: Preparing to boot 64-bit Linux kernel\n"); + bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE; + bl33_image_ep_info.args.arg1 = 0ULL; + bl33_image_ep_info.args.arg2 = 0ULL; + bl33_image_ep_info.args.arg3 = 0ULL; +# endif /* RPI3_BL33_IN_AARCH32 */ +#endif /* RPI3_DIRECT_LINUX_BOOT */ +} + +void bl31_plat_arch_setup(void) +{ + rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE, + BL_CODE_BASE, BL_CODE_END, + BL_RO_DATA_BASE, BL_RO_DATA_END +#if USE_COHERENT_MEM + , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END +#endif + ); + + enable_mmu_el3(0); +} + +#ifdef RPI3_PRELOADED_DTB_BASE +/* + * Add information to the device tree (if any) about the reserved DRAM used by + * the Trusted Firmware. + */ +static void rpi3_dtb_add_mem_rsv(void) +{ + int i, regions, rc; + uint64_t addr, size; + void *dtb = (void *)RPI3_PRELOADED_DTB_BASE; + + INFO("rpi3: Checking DTB...\n"); + + /* Return if no device tree is detected */ + if (fdt_check_header(dtb) != 0) + return; + + regions = fdt_num_mem_rsv(dtb); + + VERBOSE("rpi3: Found %d mem reserve region(s)\n", regions); + + /* We expect to find one reserved region that we can modify */ + if (regions < 1) + return; + + /* + * Look for the region that corresponds to the default boot firmware. It + * starts at address 0, and it is not needed when the default firmware + * is replaced by this port of the Trusted Firmware. + */ + for (i = 0; i < regions; i++) { + if (fdt_get_mem_rsv(dtb, i, &addr, &size) != 0) + continue; + + if (addr != 0x0) + continue; + + VERBOSE("rpi3: Firmware mem reserve region found\n"); + + rc = fdt_del_mem_rsv(dtb, i); + if (rc != 0) { + INFO("rpi3: Can't remove mem reserve region (%d)\n", rc); + } + + break; + } + + if (i == regions) { + VERBOSE("rpi3: Firmware mem reserve region not found\n"); + } + + /* + * Reserve all SRAM. As said in the documentation, this isn't actually + * secure memory, so it is needed to tell BL33 that this is a reserved + * memory region. It doesn't guarantee it won't use it, though. + */ + rc = fdt_add_mem_rsv(dtb, SEC_SRAM_BASE, SEC_SRAM_SIZE); + if (rc != 0) { + WARN("rpi3: Can't add mem reserve region (%d)\n", rc); + } + + INFO("rpi3: Reserved 0x%llx - 0x%llx in DTB\n", SEC_SRAM_BASE, + SEC_SRAM_BASE + SEC_SRAM_SIZE); +} +#endif + +void bl31_platform_setup(void) +{ +#ifdef RPI3_PRELOADED_DTB_BASE + /* Only modify a DTB if we know where to look for it */ + rpi3_dtb_add_mem_rsv(); +#endif +} diff --git a/plat/rpi/rpi3/rpi3_common.c b/plat/rpi/rpi3/rpi3_common.c new file mode 100644 index 000000000..9b10974ad --- /dev/null +++ b/plat/rpi/rpi3/rpi3_common.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "rpi3_hw.h" +#include "rpi3_private.h" + +#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ + DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ + SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#ifdef RPI3_PRELOADED_DTB_BASE +#define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \ + MT_MEMORY | MT_RW | MT_NS) +#endif + +#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \ + PLAT_RPI3_FIP_MAX_SIZE, \ + MT_MEMORY | MT_RO | MT_NS) + +#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#ifdef SPD_opteed +#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \ + RPI3_OPTEE_PAGEABLE_LOAD_BASE, \ + RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif + +/* + * Table of regions for various BL stages to map using the MMU. + */ +#ifdef IMAGE_BL1 +static const mmap_region_t plat_rpi3_mmap[] = { + MAP_SHARED_RAM, + MAP_DEVICE0, + MAP_FIP, +#ifdef SPD_opteed + MAP_OPTEE_PAGEABLE, +#endif + {0} +}; +#endif + +#ifdef IMAGE_BL2 +static const mmap_region_t plat_rpi3_mmap[] = { + MAP_SHARED_RAM, + MAP_DEVICE0, + MAP_FIP, + MAP_NS_DRAM0, +#ifdef BL32_BASE + MAP_BL32_MEM, +#endif + {0} +}; +#endif + +#ifdef IMAGE_BL31 +static const mmap_region_t plat_rpi3_mmap[] = { + MAP_SHARED_RAM, + MAP_DEVICE0, +#ifdef RPI3_PRELOADED_DTB_BASE + MAP_NS_DTB, +#endif +#ifdef BL32_BASE + MAP_BL32_MEM, +#endif + {0} +}; +#endif + +/******************************************************************************* + * Function that sets up the console + ******************************************************************************/ +static console_16550_t rpi3_console; + +void rpi3_console_init(void) +{ + int console_scope = CONSOLE_FLAG_BOOT; +#if RPI3_RUNTIME_UART != -1 + console_scope |= CONSOLE_FLAG_RUNTIME; +#endif + int rc = console_16550_register(PLAT_RPI3_UART_BASE, + PLAT_RPI3_UART_CLK_IN_HZ, + PLAT_RPI3_UART_BAUDRATE, + &rpi3_console); + if (rc == 0) { + /* + * The crash console doesn't use the multi console API, it uses + * the core console functions directly. It is safe to call panic + * and let it print debug information. + */ + panic(); + } + + console_set_scope(&rpi3_console.console, console_scope); +} + +/******************************************************************************* + * Function that sets up the translation tables. + ******************************************************************************/ +void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, + uintptr_t code_start, uintptr_t code_limit, + uintptr_t rodata_start, uintptr_t rodata_limit +#if USE_COHERENT_MEM + , uintptr_t coh_start, uintptr_t coh_limit +#endif + ) +{ + /* + * Map the Trusted SRAM with appropriate memory attributes. + * Subsequent mappings will adjust the attributes for specific regions. + */ + VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", + (void *) total_base, (void *) (total_base + total_size)); + mmap_add_region(total_base, total_base, + total_size, + MT_MEMORY | MT_RW | MT_SECURE); + + /* Re-map the code section */ + VERBOSE("Code region: %p - %p\n", + (void *) code_start, (void *) code_limit); + mmap_add_region(code_start, code_start, + code_limit - code_start, + MT_CODE | MT_SECURE); + + /* Re-map the read-only data section */ + VERBOSE("Read-only data region: %p - %p\n", + (void *) rodata_start, (void *) rodata_limit); + mmap_add_region(rodata_start, rodata_start, + rodata_limit - rodata_start, + MT_RO_DATA | MT_SECURE); + +#if USE_COHERENT_MEM + /* Re-map the coherent memory region */ + VERBOSE("Coherent region: %p - %p\n", + (void *) coh_start, (void *) coh_limit); + mmap_add_region(coh_start, coh_start, + coh_limit - coh_start, + MT_DEVICE | MT_RW | MT_SECURE); +#endif + + mmap_add(plat_rpi3_mmap); + + init_xlat_tables(); +} + +/******************************************************************************* + * Return entrypoint of BL33. + ******************************************************************************/ +uintptr_t plat_get_ns_image_entrypoint(void) +{ +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else + return PLAT_RPI3_NS_IMAGE_OFFSET; +#endif +} + +/******************************************************************************* + * Gets SPSR for BL32 entry + ******************************************************************************/ +uint32_t rpi3_get_spsr_for_bl32_entry(void) +{ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL32 image. + */ + return 0; +} + +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +uint32_t rpi3_get_spsr_for_bl33_entry(void) +{ +#if RPI3_BL33_IN_AARCH32 + INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n"); + return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE, + DISABLE_ALL_EXCEPTIONS); +#else + return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); +#endif +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} + +uint32_t plat_ic_get_pending_interrupt_type(void) +{ + ERROR("rpi3: Interrupt routed to EL3.\n"); + return INTR_TYPE_INVAL; +} + +uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) +{ + assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) || + (type == INTR_TYPE_NS)); + + assert(sec_state_is_valid(security_state)); + + /* Non-secure interrupts are signalled on the IRQ line always. */ + if (type == INTR_TYPE_NS) + return __builtin_ctz(SCR_IRQ_BIT); + + /* Secure interrupts are signalled on the FIQ line always. */ + return __builtin_ctz(SCR_FIQ_BIT); +} diff --git a/plat/rpi/rpi3/rpi3_hw.h b/plat/rpi/rpi3/rpi3_hw.h new file mode 100644 index 000000000..1a86835b3 --- /dev/null +++ b/plat/rpi/rpi3/rpi3_hw.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI3_HW_H +#define RPI3_HW_H + +#include + +/* + * Peripherals + */ + +#define RPI3_IO_BASE ULL(0x3F000000) +#define RPI3_IO_SIZE ULL(0x01000000) + +/* + * ARM <-> VideoCore mailboxes + */ +#define RPI3_MBOX_OFFSET ULL(0x0000B880) +#define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET) +/* VideoCore -> ARM */ +#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) +#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) +#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) +#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) +#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) +/* ARM -> VideoCore */ +#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) +#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) +#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) +#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) +#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) +/* Mailbox status constants */ +#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ +#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ + +/* + * Power management, reset controller, watchdog. + */ +#define RPI3_IO_PM_OFFSET ULL(0x00100000) +#define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET) +/* Registers on top of RPI3_PM_BASE. */ +#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) +#define RPI3_PM_RSTS_OFFSET ULL(0x00000020) +#define RPI3_PM_WDOG_OFFSET ULL(0x00000024) +/* Watchdog constants */ +#define RPI3_PM_PASSWORD U(0x5A000000) +#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) +#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) +/* + * The RSTS register is used by the VideoCore firmware when booting the + * Raspberry Pi to know which partition to boot from. The partition value is + * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware + * to indicate halt. + */ +#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) + +/* + * Hardware random number generator. + */ +#define RPI3_IO_RNG_OFFSET ULL(0x00104000) +#define RPI3_RNG_BASE (RPI3_IO_BASE + RPI3_IO_RNG_OFFSET) +#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) +#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) +#define RPI3_RNG_DATA_OFFSET ULL(0x00000008) +#define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010) +/* Enable/disable RNG */ +#define RPI3_RNG_CTRL_ENABLE U(0x1) +#define RPI3_RNG_CTRL_DISABLE U(0x0) +/* Number of currently available words */ +#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24) +#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF) +/* Value to mask interrupts caused by the RNG */ +#define RPI3_RNG_INT_MASK_DISABLE U(0x1) + +/* + * Serial port (called 'Mini UART' in the BCM docucmentation). + */ +#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) +#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET) +#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) + +/* + * GPIO controller + */ +#define RPI3_IO_GPIO_OFFSET ULL(0x00200000) +#define RPI3_GPIO_BASE (RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET) + +/* + * SDHost controller + */ +#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) +#define RPI3_SDHOST_BASE (RPI3_IO_BASE + RPI3_IO_SDHOST_OFFSET) + +/* + * Local interrupt controller + */ +#define RPI3_INTC_BASE_ADDRESS ULL(0x40000000) +/* Registers on top of RPI3_INTC_BASE_ADDRESS */ +#define RPI3_INTC_CONTROL_OFFSET ULL(0x00000000) +#define RPI3_INTC_PRESCALER_OFFSET ULL(0x00000008) +#define RPI3_INTC_MBOX_CONTROL_OFFSET ULL(0x00000050) +#define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ ULL(0x00000080) +#define RPI3_INTC_PENDING_FIQ_OFFSET ULL(0x00000070) +#define RPI3_INTC_PENDING_FIQ_MBOX3 ULL(0x00000080) + +#endif /* RPI3_HW_H */ diff --git a/plat/rpi/rpi3/rpi3_image_load.c b/plat/rpi/rpi3/rpi3_image_load.c new file mode 100644 index 000000000..5394c6f7c --- /dev/null +++ b/plat/rpi/rpi3/rpi3_image_load.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +/******************************************************************************* + * This function flushes the data structures so that they are visible + * in memory for the next BL image. + ******************************************************************************/ +void plat_flush_next_bl_params(void) +{ + flush_bl_params_desc(); +} + +/******************************************************************************* + * This function returns the list of loadable images. + ******************************************************************************/ +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +/******************************************************************************* + * This function returns the list of executable images. + ******************************************************************************/ +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +} diff --git a/plat/rpi/rpi3/rpi3_io_storage.c b/plat/rpi/rpi3/rpi3_io_storage.c new file mode 100644 index 000000000..49c6a760c --- /dev/null +++ b/plat/rpi/rpi3/rpi3_io_storage.c @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +/* Semihosting filenames */ +#define BL2_IMAGE_NAME "bl2.bin" +#define BL31_IMAGE_NAME "bl31.bin" +#define BL32_IMAGE_NAME "bl32.bin" +#define BL33_IMAGE_NAME "bl33.bin" + +#if TRUSTED_BOARD_BOOT +#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt" +#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" +#define SOC_FW_KEY_CERT_NAME "soc_fw_key.crt" +#define TOS_FW_KEY_CERT_NAME "tos_fw_key.crt" +#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt" +#define SOC_FW_CONTENT_CERT_NAME "soc_fw_content.crt" +#define TOS_FW_CONTENT_CERT_NAME "tos_fw_content.crt" +#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt" +#endif /* TRUSTED_BOARD_BOOT */ + +/* IO devices */ +static const io_dev_connector_t *fip_dev_con; +static uintptr_t fip_dev_handle; +static const io_dev_connector_t *memmap_dev_con; +static uintptr_t memmap_dev_handle; + +static const io_block_spec_t fip_block_spec = { + .offset = PLAT_RPI3_FIP_BASE, + .length = PLAT_RPI3_FIP_MAX_SIZE +}; + +static const io_uuid_spec_t bl2_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, +}; + +static const io_uuid_spec_t bl31_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, +}; + +static const io_uuid_spec_t bl32_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + +static const io_uuid_spec_t bl32_extra1_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, +}; + +static const io_uuid_spec_t bl32_extra2_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, +}; + +static const io_uuid_spec_t bl33_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +#if TRUSTED_BOARD_BOOT +static const io_uuid_spec_t tb_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FW_CERT, +}; + +static const io_uuid_spec_t trusted_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_KEY_CERT, +}; + +static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = { + .uuid = UUID_SOC_FW_KEY_CERT, +}; + +static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, +}; + +static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, +}; + +static const io_uuid_spec_t soc_fw_cert_uuid_spec = { + .uuid = UUID_SOC_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t tos_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t nt_fw_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, +}; +#endif /* TRUSTED_BOARD_BOOT */ + +static int open_fip(const uintptr_t spec); +static int open_memmap(const uintptr_t spec); + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +/* By default, load images from the FIP */ +static const struct plat_io_policy policies[] = { + [FIP_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&fip_block_spec, + open_memmap + }, + [BL2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl2_uuid_spec, + open_fip + }, + [BL31_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_uuid_spec, + open_fip + }, + [BL32_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_uuid_spec, + open_fip + }, + [BL32_EXTRA1_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra1_uuid_spec, + open_fip + }, + [BL32_EXTRA2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra2_uuid_spec, + open_fip + }, + [BL33_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_uuid_spec, + open_fip + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_BOOT_FW_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tb_fw_cert_uuid_spec, + open_fip + }, + [TRUSTED_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&trusted_key_cert_uuid_spec, + open_fip + }, + [SOC_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_key_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_key_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_key_cert_uuid_spec, + open_fip + }, + [SOC_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_cert_uuid_spec, + open_fip + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + +static int open_fip(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if a Firmware Image Package is available */ + result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); + if (result == 0) { + result = io_open(fip_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using FIP\n"); + io_close(local_image_handle); + } + } + return result; +} + +static int open_memmap(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(memmap_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Memmap\n"); + io_close(local_image_handle); + } + } + return result; +} + +void plat_rpi3_io_setup(void) +{ + int io_result; + + io_result = register_io_dev_fip(&fip_dev_con); + assert(io_result == 0); + + io_result = register_io_dev_memmap(&memmap_dev_con); + assert(io_result == 0); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, + &fip_dev_handle); + assert(io_result == 0); + + io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, + &memmap_dev_handle); + assert(io_result == 0); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} + +/* + * Return an IO device handle and specification which can be used to access + * an image. Use this to enforce platform load policy + */ +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + if (result == 0) { + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + } + + return result; +} diff --git a/plat/rpi/rpi3/rpi3_mbox.c b/plat/rpi/rpi3/rpi3_mbox.c new file mode 100644 index 000000000..2db605edf --- /dev/null +++ b/plat/rpi/rpi3/rpi3_mbox.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include + +#include "rpi3_hw.h" + +/* This struct must be aligned to 16 bytes */ +typedef struct __packed __aligned(16) rpi3_mbox_request { + uint32_t size; /* Buffer size in bytes */ + uint32_t code; /* Request/response code */ + uint32_t tags[0]; +} rpi3_mbox_request_t; + +#define RPI3_MBOX_BUFFER_SIZE U(256) +static uint8_t __aligned(16) rpi3_mbox_buffer[RPI3_MBOX_BUFFER_SIZE]; + +/* Constants to perform a request/check the status of a request. */ +#define RPI3_MBOX_PROCESS_REQUEST U(0x00000000) +#define RPI3_MBOX_REQUEST_SUCCESSFUL U(0x80000000) +#define RPI3_MBOX_REQUEST_ERROR U(0x80000001) + +/* Command constants */ +#define RPI3_TAG_HARDWARE_GET_BOARD_REVISION U(0x00010002) +#define RPI3_TAG_END U(0x00000000) + +#define RPI3_TAG_REQUEST U(0x00000000) +#define RPI3_TAG_IS_RESPONSE U(0x80000000) /* Set if response */ +#define RPI3_TAG_RESPONSE_LENGTH_MASK U(0x7FFFFFFF) + +#define RPI3_CHANNEL_ARM_TO_VC U(0x8) +#define RPI3_CHANNEL_MASK U(0xF) + +#define RPI3_MAILBOX_MAX_RETRIES U(1000000) + +/******************************************************************************* + * Helpers to send requests to the VideoCore using the mailboxes. + ******************************************************************************/ +static void rpi3_vc_mailbox_request_send(void) +{ + uint32_t st, data; + uintptr_t resp_addr, addr; + unsigned int retries; + + /* This is the location of the request buffer */ + addr = (uintptr_t) &rpi3_mbox_buffer; + + /* Make sure that the changes are seen by the VideoCore */ + flush_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE); + + /* Wait until the outbound mailbox is empty */ + retries = 0U; + + do { + st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET); + + retries++; + if (retries == RPI3_MAILBOX_MAX_RETRIES) { + ERROR("rpi3: mbox: Send request timeout\n"); + return; + } + + } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U); + + /* Send base address of this message to start request */ + mmio_write_32(RPI3_MBOX_BASE + RPI3_MBOX1_WRITE_OFFSET, + RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr); + + /* Wait until the inbound mailbox isn't empty */ + retries = 0U; + + do { + st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET); + + retries++; + if (retries == RPI3_MAILBOX_MAX_RETRIES) { + ERROR("rpi3: mbox: Receive response timeout\n"); + return; + } + + } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U); + + /* Get location and channel */ + data = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_READ_OFFSET); + + if ((data & RPI3_CHANNEL_MASK) != RPI3_CHANNEL_ARM_TO_VC) { + ERROR("rpi3: mbox: Wrong channel: 0x%08x\n", data); + panic(); + } + + resp_addr = (uintptr_t)(data & ~RPI3_CHANNEL_MASK); + if (addr != resp_addr) { + ERROR("rpi3: mbox: Unexpected address: 0x%08x\n", data); + panic(); + } + + /* Make sure that the data seen by the CPU is up to date */ + inv_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE); +} + +/******************************************************************************* + * Request board revision. Returns the revision and 0 on success, -1 on error. + ******************************************************************************/ +int rpi3_vc_hardware_get_board_revision(uint32_t *revision) +{ + uint32_t tag_request_size = sizeof(uint32_t); + rpi3_mbox_request_t *req = (rpi3_mbox_request_t *) rpi3_mbox_buffer; + + assert(revision != NULL); + + VERBOSE("rpi3: mbox: Sending request at %p\n", (void *)req); + + req->size = sizeof(rpi3_mbox_buffer); + req->code = RPI3_MBOX_PROCESS_REQUEST; + + req->tags[0] = RPI3_TAG_HARDWARE_GET_BOARD_REVISION; + req->tags[1] = tag_request_size; /* Space available for the response */ + req->tags[2] = RPI3_TAG_REQUEST; + req->tags[3] = 0; /* Placeholder for the response */ + + req->tags[4] = RPI3_TAG_END; + + rpi3_vc_mailbox_request_send(); + + if (req->code != RPI3_MBOX_REQUEST_SUCCESSFUL) { + ERROR("rpi3: mbox: Code = 0x%08x\n", req->code); + return -1; + } + + if (req->tags[2] != (RPI3_TAG_IS_RESPONSE | tag_request_size)) { + ERROR("rpi3: mbox: get board revision failed (0x%08x)\n", + req->tags[2]); + return -1; + } + + *revision = req->tags[3]; + + return 0; +} diff --git a/plat/rpi/rpi3/rpi3_pm.c b/plat/rpi/rpi3/rpi3_pm.c new file mode 100644 index 000000000..4f586b514 --- /dev/null +++ b/plat/rpi/rpi3/rpi3_pm.c @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include "rpi3_hw.h" + +/* Make composite power state parameter till power level 0 */ +#if PSCI_EXTENDED_STATE_ID + +#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) + +#else + +#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) + +#endif /* PSCI_EXTENDED_STATE_ID */ + +#define rpi3_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ + rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) + +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +static const unsigned int rpi3_pm_idle_states[] = { + /* State-id - 0x01 */ + rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, + MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x02 */ + rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, + MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x22 */ + rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, + MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), + 0, +}; + +/******************************************************************************* + * Platform handler called to check the validity of the power state + * parameter. The power state parameter has to be a composite power state. + ******************************************************************************/ +static int rpi3_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int state_id; + int i; + + assert(req_state != 0); + + /* + * Currently we are using a linear search for finding the matching + * entry in the idle power state array. This can be made a binary + * search if the number of entries justify the additional complexity. + */ + for (i = 0; rpi3_pm_idle_states[i] != 0; i++) { + if (power_state == rpi3_pm_idle_states[i]) { + break; + } + } + + /* Return error if entry not found in the idle state array */ + if (!rpi3_pm_idle_states[i]) { + return PSCI_E_INVALID_PARAMS; + } + + i = 0; + state_id = psci_get_pstate_id(power_state); + + /* Parse the State ID and populate the state info parameter */ + while (state_id) { + req_state->pwr_domain_state[i++] = state_id & + PLAT_LOCAL_PSTATE_MASK; + state_id >>= PLAT_LOCAL_PSTATE_WIDTH; + } + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Platform handler called when a CPU is about to enter standby. + ******************************************************************************/ +static void rpi3_cpu_standby(plat_local_state_t cpu_state) +{ + assert(cpu_state == PLAT_LOCAL_STATE_RET); + + /* + * Enter standby state. + * dsb is good practice before using wfi to enter low power states + */ + dsb(); + wfi(); +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +static int rpi3_pwr_domain_on(u_register_t mpidr) +{ + int rc = PSCI_E_SUCCESS; + unsigned int pos = plat_core_pos_by_mpidr(mpidr); + uint64_t *hold_base = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; + + assert(pos < PLATFORM_CORE_COUNT); + + hold_base[pos] = PLAT_RPI3_TM_HOLD_STATE_GO; + + /* Make sure that the write has completed */ + dsb(); + isb(); + + sev(); + + return rc; +} + +/******************************************************************************* + * Platform handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == + PLAT_LOCAL_STATE_OFF); +} + +/******************************************************************************* + * Platform handlers for system reset and system off. + ******************************************************************************/ + +/* 10 ticks (Watchdog timer = Timer clock / 16) */ +#define RESET_TIMEOUT U(10) + +static void __dead2 rpi3_watchdog_reset(void) +{ + uint32_t rstc; + + console_flush(); + + dsbsy(); + isb(); + + mmio_write_32(RPI3_PM_BASE + RPI3_PM_WDOG_OFFSET, + RPI3_PM_PASSWORD | RESET_TIMEOUT); + + rstc = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET); + rstc &= ~RPI3_PM_RSTC_WRCFG_MASK; + rstc |= RPI3_PM_PASSWORD | RPI3_PM_RSTC_WRCFG_FULL_RESET; + mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET, rstc); + + for (;;) { + wfi(); + } +} + +static void __dead2 rpi3_system_reset(void) +{ + INFO("rpi3: PSCI_SYSTEM_RESET: Invoking watchdog reset\n"); + + rpi3_watchdog_reset(); +} + +static void __dead2 rpi3_system_off(void) +{ + uint32_t rsts; + + INFO("rpi3: PSCI_SYSTEM_OFF: Invoking watchdog reset\n"); + + /* + * This function doesn't actually make the Raspberry Pi turn itself off, + * the hardware doesn't allow it. It simply reboots it and the RSTS + * value tells the bootcode.bin firmware not to continue the regular + * bootflow and to stay in a low power mode. + */ + + rsts = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET); + rsts |= RPI3_PM_PASSWORD | RPI3_PM_RSTS_WRCFG_HALT; + mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET, rsts); + + rpi3_watchdog_reset(); +} + +/******************************************************************************* + * Platform handlers and setup function. + ******************************************************************************/ +static const plat_psci_ops_t plat_rpi3_psci_pm_ops = { + .cpu_standby = rpi3_cpu_standby, + .pwr_domain_on = rpi3_pwr_domain_on, + .pwr_domain_on_finish = rpi3_pwr_domain_on_finish, + .system_off = rpi3_system_off, + .system_reset = rpi3_system_reset, + .validate_power_state = rpi3_validate_power_state, +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + uintptr_t *entrypoint = (void *) PLAT_RPI3_TM_ENTRYPOINT; + + *entrypoint = sec_entrypoint; + *psci_ops = &plat_rpi3_psci_pm_ops; + + return 0; +} diff --git a/plat/rpi/rpi3/rpi3_private.h b/plat/rpi/rpi3/rpi3_private.h new file mode 100644 index 000000000..53078f8e9 --- /dev/null +++ b/plat/rpi/rpi3/rpi3_private.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI3_PRIVATE_H +#define RPI3_PRIVATE_H + +#include + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ + +/* Utility functions */ +void rpi3_console_init(void); +void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, + uintptr_t code_start, uintptr_t code_limit, + uintptr_t rodata_start, uintptr_t rodata_limit +#if USE_COHERENT_MEM + , uintptr_t coh_start, uintptr_t coh_limit +#endif + ); + +/* Optional functions required in the Raspberry Pi 3 port */ +unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr); + +/* BL2 utility functions */ +uint32_t rpi3_get_spsr_for_bl32_entry(void); +uint32_t rpi3_get_spsr_for_bl33_entry(void); + +/* IO storage utility functions */ +void plat_rpi3_io_setup(void); + +/* Hardware RNG functions */ +void rpi3_rng_read(void *buf, size_t len); + +/* VideoCore firmware commands */ +int rpi3_vc_hardware_get_board_revision(uint32_t *revision); + +#endif /* RPI3_PRIVATE_H */ diff --git a/plat/rpi/rpi3/rpi3_rng.c b/plat/rpi/rpi3/rpi3_rng.c new file mode 100644 index 000000000..fd69adbf3 --- /dev/null +++ b/plat/rpi/rpi3/rpi3_rng.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include "rpi3_hw.h" + +/* Initial amount of values to discard */ +#define RNG_WARMUP_COUNT U(0x40000) + +static void rpi3_rng_initialize(void) +{ + uint32_t int_mask, ctrl; + + /* Return if it is already enabled */ + ctrl = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET); + if ((ctrl & RPI3_RNG_CTRL_ENABLE) != 0U) { + return; + } + + /* Mask interrupts */ + int_mask = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET); + int_mask |= RPI3_RNG_INT_MASK_DISABLE; + mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET, int_mask); + + /* Discard several values when initializing to give it time to warmup */ + mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET, RNG_WARMUP_COUNT); + + mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET, + RPI3_RNG_CTRL_ENABLE); +} + +static uint32_t rpi3_rng_get_word(void) +{ + size_t nwords; + + do { + /* Get number of available words to read */ + nwords = (mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET) + >> RPI3_RNG_STATUS_NUM_WORDS_SHIFT) + & RPI3_RNG_STATUS_NUM_WORDS_MASK; + } while (nwords == 0U); + + return mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_DATA_OFFSET); +} + +void rpi3_rng_read(void *buf, size_t len) +{ + uint32_t data; + size_t left = len; + uint32_t *dst = buf; + + assert(buf != NULL); + assert(len != 0U); + assert(check_uptr_overflow((uintptr_t) buf, (uintptr_t) len) == 0); + + rpi3_rng_initialize(); + + while (left >= sizeof(uint32_t)) { + data = rpi3_rng_get_word(); + *dst++ = data; + left -= sizeof(uint32_t); + } + + if (left > 0U) { + data = rpi3_rng_get_word(); + memcpy(dst, &data, left); + } +} diff --git a/plat/rpi/rpi3/rpi3_rotpk.S b/plat/rpi/rpi3/rpi3_rotpk.S new file mode 100644 index 000000000..1c17b2141 --- /dev/null +++ b/plat/rpi/rpi3/rpi3_rotpk.S @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .global rpi3_rotpk_hash + .global rpi3_rotpk_hash_end +rpi3_rotpk_hash: + /* DER header */ + .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 + .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 + /* SHA256 */ + .incbin ROTPK_HASH +rpi3_rotpk_hash_end: diff --git a/plat/rpi/rpi3/rpi3_stack_protector.c b/plat/rpi/rpi3/rpi3_stack_protector.c new file mode 100644 index 000000000..6f49f617b --- /dev/null +++ b/plat/rpi/rpi3/rpi3_stack_protector.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +#include "rpi3_private.h" + +/* Get 128 bits of entropy and fuse the values together to form the canary. */ +#define TRNG_NBYTES 16U + +u_register_t plat_get_stack_protector_canary(void) +{ + size_t i; + u_register_t buf[TRNG_NBYTES / sizeof(u_register_t)]; + u_register_t ret = 0U; + + rpi3_rng_read(buf, sizeof(buf)); + + for (i = 0U; i < ARRAY_SIZE(buf); i++) + ret ^= buf[i]; + + return ret; +} diff --git a/plat/rpi/rpi3/rpi3_topology.c b/plat/rpi/rpi3/rpi3_topology.c new file mode 100644 index 000000000..200d41dd1 --- /dev/null +++ b/plat/rpi/rpi3/rpi3_topology.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include "rpi3_private.h" + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first node */ + PLATFORM_CLUSTER0_CORE_COUNT, +}; + +/******************************************************************************* + * This function returns the ARM default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { + return -1; + } + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) { + return -1; + } + + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { + return -1; + } + + return plat_rpi3_calc_core_pos(mpidr); +} diff --git a/plat/rpi/rpi3/rpi3_trusted_boot.c b/plat/rpi/rpi3/rpi3_trusted_boot.c new file mode 100644 index 000000000..f6c669fad --- /dev/null +++ b/plat/rpi/rpi3/rpi3_trusted_boot.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +extern char rpi3_rotpk_hash[], rpi3_rotpk_hash_end[]; + +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + *key_ptr = rpi3_rotpk_hash; + *key_len = rpi3_rotpk_hash_end - rpi3_rotpk_hash; + *flags = ROTPK_IS_HASH; + + return 0; +} + +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + *nv_ctr = 0; + + return 0; +} + +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + return 1; +} + +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + return get_mbedtls_heap_helper(heap_addr, heap_size); +} diff --git a/plat/rpi3/aarch64/plat_helpers.S b/plat/rpi3/aarch64/plat_helpers.S deleted file mode 100644 index 7974b602d..000000000 --- a/plat/rpi3/aarch64/plat_helpers.S +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -#include "../rpi3_hw.h" - - .globl plat_crash_console_flush - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl platform_mem_init - .globl plat_get_my_entrypoint - .globl plat_is_my_cpu_primary - .globl plat_my_core_pos - .globl plat_reset_handler - .globl plat_rpi3_calc_core_pos - .globl plat_secondary_cold_boot_setup - - /* ----------------------------------------------------- - * unsigned int plat_my_core_pos(void) - * - * This function uses the plat_rpi3_calc_core_pos() - * definition to get the index of the calling CPU. - * ----------------------------------------------------- - */ -func plat_my_core_pos - mrs x0, mpidr_el1 - b plat_rpi3_calc_core_pos -endfunc plat_my_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr); - * - * CorePos = (ClusterId * 4) + CoreId - * ----------------------------------------------------- - */ -func plat_rpi3_calc_core_pos - and x1, x0, #MPIDR_CPU_MASK - and x0, x0, #MPIDR_CLUSTER_MASK - add x0, x1, x0, LSR #6 - ret -endfunc plat_rpi3_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_is_my_cpu_primary (void); - * - * Find out whether the current cpu is the primary - * cpu. - * ----------------------------------------------------- - */ -func plat_is_my_cpu_primary - mrs x0, mpidr_el1 - and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #RPI3_PRIMARY_CPU - cset w0, eq - ret -endfunc plat_is_my_cpu_primary - - /* ----------------------------------------------------- - * void plat_secondary_cold_boot_setup (void); - * - * This function performs any platform specific actions - * needed for a secondary cpu after a cold reset e.g - * mark the cpu's presence, mechanism to place it in a - * holding pen etc. - * ----------------------------------------------------- - */ -func plat_secondary_cold_boot_setup - /* Calculate address of our hold entry */ - bl plat_my_core_pos - lsl x0, x0, #3 - mov_imm x2, PLAT_RPI3_TM_HOLD_BASE - add x0, x0, x2 - - /* - * This code runs way before requesting the warmboot of this core, - * so it is possible to clear the mailbox before getting a request - * to boot. - */ - mov x1, PLAT_RPI3_TM_HOLD_STATE_WAIT - str x1,[x0] - - /* Wait until we have a go */ -poll_mailbox: - wfe - ldr x1, [x0] - cmp x1, PLAT_RPI3_TM_HOLD_STATE_GO - bne poll_mailbox - - /* Jump to the provided entrypoint */ - mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT - ldr x1, [x0] - br x1 -endfunc plat_secondary_cold_boot_setup - - /* --------------------------------------------------------------------- - * uintptr_t plat_get_my_entrypoint (void); - * - * Main job of this routine is to distinguish between a cold and a warm - * boot. - * - * This functions returns: - * - 0 for a cold boot. - * - Any other value for a warm boot. - * --------------------------------------------------------------------- - */ -func plat_get_my_entrypoint - /* TODO: support warm boot */ - mov x0, #0 - ret -endfunc plat_get_my_entrypoint - - /* --------------------------------------------- - * void platform_mem_init (void); - * - * No need to carry out any memory initialization. - * --------------------------------------------- - */ -func platform_mem_init - ret -endfunc platform_mem_init - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * Function to initialize the crash console - * without a C Runtime to print crash report. - * Clobber list : x0 - x3 - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, PLAT_RPI3_UART_BASE - mov_imm x1, PLAT_RPI3_UART_CLK_IN_HZ - mov_imm x2, PLAT_RPI3_UART_BAUDRATE - b console_16550_core_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(int c) - * Function to print a character on the crash - * console without a C Runtime. - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, PLAT_RPI3_UART_BASE - b console_16550_core_putc -endfunc plat_crash_console_putc - - /* --------------------------------------------- - * int plat_crash_console_flush() - * Function to force a write of all buffered - * data that hasn't been output. - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func plat_crash_console_flush - mov_imm x0, PLAT_RPI3_UART_BASE - b console_16550_core_flush -endfunc plat_crash_console_flush - - /* --------------------------------------------- - * void plat_reset_handler(void); - * --------------------------------------------- - */ -func plat_reset_handler - /* use the 19.2 MHz clock for the architected timer */ - mov x0, #RPI3_INTC_BASE_ADDRESS - mov w1, #0x80000000 - str wzr, [x0, #RPI3_INTC_CONTROL_OFFSET] - str w1, [x0, #RPI3_INTC_PRESCALER_OFFSET] - ret -endfunc plat_reset_handler diff --git a/plat/rpi3/aarch64/rpi3_bl2_mem_params_desc.c b/plat/rpi3/aarch64/rpi3_bl2_mem_params_desc.c deleted file mode 100644 index 715aec410..000000000 --- a/plat/rpi3/aarch64/rpi3_bl2_mem_params_desc.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include - -/******************************************************************************* - * Following descriptor provides BL image/ep information that gets used - * by BL2 to load the images and also subset of this information is - * passed to next BL image. The image loading sequence is managed by - * populating the images in required loading order. The image execution - * sequence is managed by populating the `next_handoff_image_id` with - * the next executable image id. - ******************************************************************************/ -static bl_mem_params_node_t bl2_mem_params_descs[] = { - - /* Fill BL31 related information */ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), -#if DEBUG - .ep_info.args.arg1 = RPI3_BL31_PLAT_PARAM_VAL, -#endif - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, - -# ifdef BL32_BASE - .next_handoff_image_id = BL32_IMAGE_ID, -# else - .next_handoff_image_id = BL33_IMAGE_ID, -# endif - }, - -# ifdef BL32_BASE - /* Fill BL32 related information */ - { - .image_id = BL32_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE), - .ep_info.pc = BL32_BASE, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - - .next_handoff_image_id = BL33_IMAGE_ID, - }, - - /* - * Fill BL32 external 1 related information. - * A typical use for extra1 image is with OP-TEE where it is the pager - * image. - */ - { - .image_id = BL32_EXTRA1_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_SKIP_LOADING), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, - - /* - * Fill BL32 external 2 related information. - * A typical use for extra2 image is with OP-TEE where it is the paged - * image. - */ - { - .image_id = BL32_EXTRA2_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_SKIP_LOADING), -#ifdef SPD_opteed - .image_info.image_base = RPI3_OPTEE_PAGEABLE_LOAD_BASE, - .image_info.image_max_size = RPI3_OPTEE_PAGEABLE_LOAD_SIZE, -#endif - .next_handoff_image_id = INVALID_IMAGE_ID, - }, -# endif /* BL32_BASE */ - - /* Fill BL33 related information */ - { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - NON_SECURE | EXECUTABLE), -# ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_SKIP_LOADING), -# else - .ep_info.pc = PLAT_RPI3_NS_IMAGE_OFFSET, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_RPI3_NS_IMAGE_OFFSET, - .image_info.image_max_size = PLAT_RPI3_NS_IMAGE_MAX_SIZE, -# endif /* PRELOADED_BL33_BASE */ - - .next_handoff_image_id = INVALID_IMAGE_ID, - } -}; - -REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/rpi3/include/plat_macros.S b/plat/rpi3/include/plat_macros.S deleted file mode 100644 index c0c396791..000000000 --- a/plat/rpi3/include/plat_macros.S +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef PLAT_MACROS_S -#define PLAT_MACROS_S - - /* --------------------------------------------- - * The below required platform porting macro - * prints out relevant platform registers - * whenever an unhandled exception is taken in - * BL31. - * Clobbers: x0 - x10, x16, x17, sp - * --------------------------------------------- - */ - .macro plat_crash_print_regs - .endm - -#endif /* PLAT_MACROS_S */ diff --git a/plat/rpi3/include/platform_def.h b/plat/rpi3/include/platform_def.h deleted file mode 100644 index 4d902225f..000000000 --- a/plat/rpi3/include/platform_def.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLATFORM_DEF_H -#define PLATFORM_DEF_H - -#include -#include -#include -#include - -#include "../rpi3_hw.h" - -/* Special value used to verify platform parameters from BL2 to BL31 */ -#define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) - -#define PLATFORM_STACK_SIZE ULL(0x1000) - -#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) -#define PLATFORM_CLUSTER_COUNT U(1) -#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT - -#define RPI3_PRIMARY_CPU U(0) - -#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 -#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ - PLATFORM_CORE_COUNT) - -#define PLAT_MAX_RET_STATE U(1) -#define PLAT_MAX_OFF_STATE U(2) - -/* Local power state for power domains in Run state. */ -#define PLAT_LOCAL_STATE_RUN U(0) -/* Local power state for retention. Valid only for CPU power domains */ -#define PLAT_LOCAL_STATE_RET U(1) -/* - * Local power state for OFF/power-down. Valid for CPU and cluster power - * domains. - */ -#define PLAT_LOCAL_STATE_OFF U(2) - -/* - * Macros used to parse state information from State-ID if it is using the - * recommended encoding for State-ID. - */ -#define PLAT_LOCAL_PSTATE_WIDTH U(4) -#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) - -/* - * Some data must be aligned on the biggest cache line size in the platform. - * This is known only to the platform as it might have a combination of - * integrated and external caches. - */ -#define CACHE_WRITEBACK_SHIFT U(6) -#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) - -/* - * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and - * secure DRAM. Note that this is all actually DRAM with different names, - * there is no Secure RAM in the Raspberry Pi 3. - */ -#if RPI3_USE_UEFI_MAP -#define SEC_ROM_BASE ULL(0x00000000) -#define SEC_ROM_SIZE ULL(0x00010000) - -/* FIP placed after ROM to append it to BL1 with very little padding. */ -#define PLAT_RPI3_FIP_BASE ULL(0x00020000) -#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x00010000) - -/* Reserve 2M of secure SRAM and DRAM, starting at 2M */ -#define SEC_SRAM_BASE ULL(0x00200000) -#define SEC_SRAM_SIZE ULL(0x00100000) - -#define SEC_DRAM0_BASE ULL(0x00300000) -#define SEC_DRAM0_SIZE ULL(0x00100000) - -/* Windows on ARM requires some RAM at 4M */ -#define NS_DRAM0_BASE ULL(0x00400000) -#define NS_DRAM0_SIZE ULL(0x00C00000) -#else -#define SEC_ROM_BASE ULL(0x00000000) -#define SEC_ROM_SIZE ULL(0x00020000) - -/* FIP placed after ROM to append it to BL1 with very little padding. */ -#define PLAT_RPI3_FIP_BASE ULL(0x00020000) -#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x001E0000) - -/* We have 16M of memory reserved starting at 256M */ -#define SEC_SRAM_BASE ULL(0x10000000) -#define SEC_SRAM_SIZE ULL(0x00100000) - -#define SEC_DRAM0_BASE ULL(0x10100000) -#define SEC_DRAM0_SIZE ULL(0x00F00000) -/* End of reserved memory */ - -#define NS_DRAM0_BASE ULL(0x11000000) -#define NS_DRAM0_SIZE ULL(0x01000000) -#endif /* RPI3_USE_UEFI_MAP */ - -/* - * BL33 entrypoint. - */ -#define PLAT_RPI3_NS_IMAGE_OFFSET NS_DRAM0_BASE -#define PLAT_RPI3_NS_IMAGE_MAX_SIZE NS_DRAM0_SIZE - -/* - * I/O registers. - */ -#define DEVICE0_BASE RPI3_IO_BASE -#define DEVICE0_SIZE RPI3_IO_SIZE - -/* - * Arm TF lives in SRAM, partition it here - */ -#define SHARED_RAM_BASE SEC_SRAM_BASE -#define SHARED_RAM_SIZE ULL(0x00001000) - -#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) -#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) - -/* - * Mailbox to control the secondary cores.All secondary cores are held in a wait - * loop in cold boot. To release them perform the following steps (plus any - * additional barriers that may be needed): - * - * uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT; - * *entrypoint = ADDRESS_TO_JUMP_TO; - * - * uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; - * mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO; - * - * sev(); - */ -#define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE - -/* The secure entry point to be used on warm reset by all CPUs. */ -#define PLAT_RPI3_TM_ENTRYPOINT PLAT_RPI3_TRUSTED_MAILBOX_BASE -#define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8) - -/* Hold entries for each CPU. */ -#define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \ - PLAT_RPI3_TM_ENTRYPOINT_SIZE) -#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8) -#define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \ - PLATFORM_CORE_COUNT) - -#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \ - PLAT_RPI3_TM_HOLD_SIZE) - -#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0) -#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1) - -/* - * BL1 specific defines. - * - * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of - * addresses. - * - * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using - * the current BL1 RW debug size plus a little space for growth. - */ -#define PLAT_MAX_BL1_RW_SIZE ULL(0x12000) - -#define BL1_RO_BASE SEC_ROM_BASE -#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) -#define BL1_RW_BASE (BL1_RW_LIMIT - PLAT_MAX_BL1_RW_SIZE) -#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) - -/* - * BL2 specific defines. - * - * Put BL2 just below BL31. BL2_BASE is calculated using the current BL2 debug - * size plus a little space for growth. - */ -#define PLAT_MAX_BL2_SIZE ULL(0x2C000) - -#define BL2_BASE (BL2_LIMIT - PLAT_MAX_BL2_SIZE) -#define BL2_LIMIT BL31_BASE - -/* - * BL31 specific defines. - * - * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the - * current BL31 debug size plus a little space for growth. - */ -#define PLAT_MAX_BL31_SIZE ULL(0x20000) - -#define BL31_BASE (BL31_LIMIT - PLAT_MAX_BL31_SIZE) -#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) -#define BL31_PROGBITS_LIMIT BL1_RW_BASE - -/* - * BL32 specific defines. - * - * BL32 can execute from Secure SRAM or Secure DRAM. - */ -#define BL32_SRAM_BASE BL_RAM_BASE -#define BL32_SRAM_LIMIT BL31_BASE -#define BL32_DRAM_BASE SEC_DRAM0_BASE -#define BL32_DRAM_LIMIT (SEC_DRAM0_BASE + SEC_DRAM0_SIZE) - -#ifdef SPD_opteed -/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ -#define RPI3_OPTEE_PAGEABLE_LOAD_SIZE 0x080000 /* 512KB */ -#define RPI3_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - \ - RPI3_OPTEE_PAGEABLE_LOAD_SIZE) -#endif - -#define SEC_SRAM_ID 0 -#define SEC_DRAM_ID 1 - -#if RPI3_BL32_RAM_LOCATION_ID == SEC_SRAM_ID -# define BL32_MEM_BASE BL_RAM_BASE -# define BL32_MEM_SIZE BL_RAM_SIZE -# define BL32_BASE BL32_SRAM_BASE -# define BL32_LIMIT BL32_SRAM_LIMIT -#elif RPI3_BL32_RAM_LOCATION_ID == SEC_DRAM_ID -# define BL32_MEM_BASE SEC_DRAM0_BASE -# define BL32_MEM_SIZE SEC_DRAM0_SIZE -# define BL32_BASE BL32_DRAM_BASE -# define BL32_LIMIT BL32_DRAM_LIMIT -#else -# error "Unsupported RPI3_BL32_RAM_LOCATION_ID value" -#endif -#define BL32_SIZE (BL32_LIMIT - BL32_BASE) - -#ifdef SPD_none -#undef BL32_BASE -#endif /* SPD_none */ - -/* - * Other memory-related defines. - */ -#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) -#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) - -#define MAX_MMAP_REGIONS 8 -#define MAX_XLAT_TABLES 4 - -#define MAX_IO_DEVICES U(3) -#define MAX_IO_HANDLES U(4) - -#define MAX_IO_BLOCK_DEVICES U(1) - -/* - * Serial-related constants. - */ -#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE -#define PLAT_RPI3_UART_CLK_IN_HZ RPI3_MINI_UART_CLK_IN_HZ -#define PLAT_RPI3_UART_BAUDRATE ULL(115200) - -/* - * System counter - */ -#define SYS_COUNTER_FREQ_IN_TICKS ULL(19200000) - -#endif /* PLATFORM_DEF_H */ diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk deleted file mode 100644 index f238cd61d..000000000 --- a/plat/rpi3/platform.mk +++ /dev/null @@ -1,218 +0,0 @@ -# -# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -include lib/libfdt/libfdt.mk -include lib/xlat_tables_v2/xlat_tables.mk - -PLAT_INCLUDES := -Iplat/rpi3/include - -PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \ - plat/rpi3/rpi3_common.c \ - ${XLAT_TABLES_LIB_SRCS} - -BL1_SOURCES += drivers/io/io_fip.c \ - drivers/io/io_memmap.c \ - drivers/io/io_storage.c \ - lib/cpus/aarch64/cortex_a53.S \ - plat/common/aarch64/platform_mp_stack.S \ - plat/rpi3/aarch64/plat_helpers.S \ - plat/rpi3/rpi3_bl1_setup.c \ - plat/rpi3/rpi3_io_storage.c \ - plat/rpi3/rpi3_mbox.c - -BL2_SOURCES += common/desc_image_load.c \ - drivers/io/io_fip.c \ - drivers/io/io_memmap.c \ - drivers/io/io_storage.c \ - drivers/gpio/gpio.c \ - drivers/delay_timer/delay_timer.c \ - drivers/delay_timer/generic_delay_timer.c \ - drivers/rpi3/gpio/rpi3_gpio.c \ - drivers/io/io_block.c \ - drivers/mmc/mmc.c \ - drivers/rpi3/sdhost/rpi3_sdhost.c \ - plat/common/aarch64/platform_mp_stack.S \ - plat/rpi3/aarch64/plat_helpers.S \ - plat/rpi3/aarch64/rpi3_bl2_mem_params_desc.c \ - plat/rpi3/rpi3_bl2_setup.c \ - plat/rpi3/rpi3_image_load.c \ - plat/rpi3/rpi3_io_storage.c - -BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ - plat/common/plat_psci_common.c \ - plat/rpi3/aarch64/plat_helpers.S \ - plat/rpi3/rpi3_bl31_setup.c \ - plat/rpi3/rpi3_pm.c \ - plat/rpi3/rpi3_topology.c \ - ${LIBFDT_SRCS} - -# Tune compiler for Cortex-A53 -ifeq ($(notdir $(CC)),armclang) - TF_CFLAGS_aarch64 += -mcpu=cortex-a53 -else ifneq ($(findstring clang,$(notdir $(CC))),) - TF_CFLAGS_aarch64 += -mcpu=cortex-a53 -else - TF_CFLAGS_aarch64 += -mtune=cortex-a53 -endif - -# Platform Makefile target -# ------------------------ - -RPI3_BL1_PAD_BIN := ${BUILD_PLAT}/bl1_pad.bin -RPI3_ARMSTUB8_BIN := ${BUILD_PLAT}/armstub8.bin - -# Add new default target when compiling this platform -all: armstub - -# This target concatenates BL1 and the FIP so that the base addresses match the -# ones defined in the memory map -armstub: bl1 fip - @echo " CAT $@" - ${Q}cp ${BUILD_PLAT}/bl1.bin ${RPI3_BL1_PAD_BIN} - ${Q}truncate --size=131072 ${RPI3_BL1_PAD_BIN} - ${Q}cat ${RPI3_BL1_PAD_BIN} ${BUILD_PLAT}/fip.bin > ${RPI3_ARMSTUB8_BIN} - @${ECHO_BLANK_LINE} - @echo "Built $@ successfully" - @${ECHO_BLANK_LINE} - -# Build config flags -# ------------------ - -# Enable all errata workarounds for Cortex-A53 -ERRATA_A53_826319 := 1 -ERRATA_A53_835769 := 1 -ERRATA_A53_836870 := 1 -ERRATA_A53_843419 := 1 -ERRATA_A53_855873 := 1 - -WORKAROUND_CVE_2017_5715 := 0 - -# Disable stack protector by default -ENABLE_STACK_PROTECTOR := 0 - -# Reset to BL31 isn't supported -RESET_TO_BL31 := 0 - -# Have different sections for code and rodata -SEPARATE_CODE_AND_RODATA := 1 - -# Use Coherent memory -USE_COHERENT_MEM := 1 - -# Platform build flags -# -------------------- - -# BL33 images are in AArch64 by default -RPI3_BL33_IN_AARCH32 := 0 - -# Assume that BL33 isn't the Linux kernel by default -RPI3_DIRECT_LINUX_BOOT := 0 - -# UART to use at runtime. -1 means the runtime UART is disabled. -# Any other value means the default UART will be used. -RPI3_RUNTIME_UART := -1 - -# Use normal memory mapping for ROM, FIP, SRAM and DRAM -RPI3_USE_UEFI_MAP := 0 - -# BL32 location -RPI3_BL32_RAM_LOCATION := tdram -ifeq (${RPI3_BL32_RAM_LOCATION}, tsram) - RPI3_BL32_RAM_LOCATION_ID = SEC_SRAM_ID -else ifeq (${RPI3_BL32_RAM_LOCATION}, tdram) - RPI3_BL32_RAM_LOCATION_ID = SEC_DRAM_ID -else - $(error "Unsupported RPI3_BL32_RAM_LOCATION value") -endif - -# Process platform flags -# ---------------------- - -$(eval $(call add_define,RPI3_BL32_RAM_LOCATION_ID)) -$(eval $(call add_define,RPI3_BL33_IN_AARCH32)) -$(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT)) -ifdef RPI3_PRELOADED_DTB_BASE -$(eval $(call add_define,RPI3_PRELOADED_DTB_BASE)) -endif -$(eval $(call add_define,RPI3_RUNTIME_UART)) -$(eval $(call add_define,RPI3_USE_UEFI_MAP)) - -# Verify build config -# ------------------- -# -ifneq (${RPI3_DIRECT_LINUX_BOOT}, 0) - ifndef RPI3_PRELOADED_DTB_BASE - $(error Error: RPI3_PRELOADED_DTB_BASE needed if RPI3_DIRECT_LINUX_BOOT=1) - endif -endif - -ifneq (${RESET_TO_BL31}, 0) - $(error Error: rpi3 needs RESET_TO_BL31=0) -endif - -ifeq (${ARCH},aarch32) - $(error Error: AArch32 not supported on rpi3) -endif - -ifneq ($(ENABLE_STACK_PROTECTOR), 0) -PLAT_BL_COMMON_SOURCES += plat/rpi3/rpi3_rng.c \ - plat/rpi3/rpi3_stack_protector.c -endif - -ifeq (${SPD},opteed) -BL2_SOURCES += \ - lib/optee/optee_utils.c -endif - -# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images -# in the FIP if the platform requires. -ifneq ($(BL32_EXTRA1),) -$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1)) -endif -ifneq ($(BL32_EXTRA2),) -$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2)) -endif - -ifneq (${TRUSTED_BOARD_BOOT},0) - - include drivers/auth/mbedtls/mbedtls_crypto.mk - include drivers/auth/mbedtls/mbedtls_x509.mk - - AUTH_SOURCES := drivers/auth/auth_mod.c \ - drivers/auth/crypto_mod.c \ - drivers/auth/img_parser_mod.c \ - drivers/auth/tbbr/tbbr_cot.c - - BL1_SOURCES += ${AUTH_SOURCES} \ - bl1/tbbr/tbbr_img_desc.c \ - plat/common/tbbr/plat_tbbr.c \ - plat/rpi3/rpi3_trusted_boot.c \ - plat/rpi3/rpi3_rotpk.S - - BL2_SOURCES += ${AUTH_SOURCES} \ - plat/common/tbbr/plat_tbbr.c \ - plat/rpi3/rpi3_trusted_boot.c \ - plat/rpi3/rpi3_rotpk.S - - ROT_KEY = $(BUILD_PLAT)/rot_key.pem - ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin - - $(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) - - $(BUILD_PLAT)/bl1/rpi3_rotpk.o: $(ROTPK_HASH) - $(BUILD_PLAT)/bl2/rpi3_rotpk.o: $(ROTPK_HASH) - - certificates: $(ROT_KEY) - - $(ROT_KEY): - @echo " OPENSSL $@" - $(Q)openssl genrsa 2048 > $@ 2>/dev/null - - $(ROTPK_HASH): $(ROT_KEY) - @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null -endif diff --git a/plat/rpi3/rpi3_bl1_setup.c b/plat/rpi3/rpi3_bl1_setup.c deleted file mode 100644 index b869e9da8..000000000 --- a/plat/rpi3/rpi3_bl1_setup.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include -#include -#include -#include - -#include "rpi3_private.h" - -/* Data structure which holds the extents of the trusted SRAM for BL1 */ -static meminfo_t bl1_tzram_layout; - -meminfo_t *bl1_plat_sec_mem_layout(void) -{ - return &bl1_tzram_layout; -} - -/******************************************************************************* - * Perform any BL1 specific platform actions. - ******************************************************************************/ -void bl1_early_platform_setup(void) -{ - /* Initialize the console to provide early debug support */ - rpi3_console_init(); - - /* Allow BL1 to see the whole Trusted RAM */ - bl1_tzram_layout.total_base = BL_RAM_BASE; - bl1_tzram_layout.total_size = BL_RAM_SIZE; -} - -/****************************************************************************** - * Perform the very early platform specific architecture setup. This only - * does basic initialization. Later architectural setup (bl1_arch_setup()) - * does not do anything platform specific. - *****************************************************************************/ -void bl1_plat_arch_setup(void) -{ - rpi3_setup_page_tables(bl1_tzram_layout.total_base, - bl1_tzram_layout.total_size, - BL_CODE_BASE, BL1_CODE_END, - BL1_RO_DATA_BASE, BL1_RO_DATA_END -#if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END -#endif - ); - - enable_mmu_el3(0); -} - -void bl1_platform_setup(void) -{ - uint32_t __unused rev; - int __unused rc; - - rc = rpi3_vc_hardware_get_board_revision(&rev); - - if (rc == 0) { - const char __unused *model, __unused *info; - - switch (rev) { - case 0xA02082: - model = "Raspberry Pi 3 Model B"; - info = "(1GB, Sony, UK)"; - break; - case 0xA22082: - model = "Raspberry Pi 3 Model B"; - info = "(1GB, Embest, China)"; - break; - case 0xA020D3: - model = "Raspberry Pi 3 Model B+"; - info = "(1GB, Sony, UK)"; - break; - default: - model = "Unknown"; - info = "(Unknown)"; - ERROR("rpi3: Unknown board revision 0x%08x\n", rev); - break; - } - - NOTICE("rpi3: Detected: %s %s [0x%08x]\n", model, info, rev); - } else { - ERROR("rpi3: Unable to detect board revision\n"); - } - - /* Initialise the IO layer and register platform IO devices */ - plat_rpi3_io_setup(); -} diff --git a/plat/rpi3/rpi3_bl2_setup.c b/plat/rpi3/rpi3_bl2_setup.c deleted file mode 100644 index b5e58352a..000000000 --- a/plat/rpi3/rpi3_bl2_setup.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rpi3_private.h" - -/* Data structure which holds the extents of the trusted SRAM for BL2 */ -static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); - -/* rpi3 GPIO setup function. */ -static void rpi3_gpio_setup(void) -{ - struct rpi3_gpio_params params; - - memset(¶ms, 0, sizeof(struct rpi3_gpio_params)); - params.reg_base = RPI3_GPIO_BASE; - - rpi3_gpio_init(¶ms); -} - -/* Data structure which holds the MMC info */ -static struct mmc_device_info mmc_info; - -static void rpi3_sdhost_setup(void) -{ - struct rpi3_sdhost_params params; - - memset(¶ms, 0, sizeof(struct rpi3_sdhost_params)); - params.reg_base = RPI3_SDHOST_BASE; - params.bus_width = MMC_BUS_WIDTH_1; - params.clk_rate = 50000000; - mmc_info.mmc_dev_type = MMC_IS_SD_HC; - rpi3_sdhost_init(¶ms, &mmc_info); -} - -/******************************************************************************* - * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 - * in x0. This memory layout is sitting at the base of the free trusted SRAM. - * Copy it to a safe location before its reclaimed by later BL2 functionality. - ******************************************************************************/ - -void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, - u_register_t arg2, u_register_t arg3) -{ - meminfo_t *mem_layout = (meminfo_t *) arg1; - - /* Initialize the console to provide early debug support */ - rpi3_console_init(); - - /* Enable arch timer */ - generic_delay_timer_init(); - - /* Setup GPIO driver */ - rpi3_gpio_setup(); - - /* Setup the BL2 memory layout */ - bl2_tzram_layout = *mem_layout; - - /* Setup SDHost driver */ - rpi3_sdhost_setup(); - - plat_rpi3_io_setup(); -} - -void bl2_platform_setup(void) -{ - /* - * This is where a TrustZone address space controller and other - * security related peripherals would be configured. - */ -} - -/******************************************************************************* - * Perform the very early platform specific architectural setup here. - ******************************************************************************/ -void bl2_plat_arch_setup(void) -{ - rpi3_setup_page_tables(bl2_tzram_layout.total_base, - bl2_tzram_layout.total_size, - BL_CODE_BASE, BL_CODE_END, - BL_RO_DATA_BASE, BL_RO_DATA_END -#if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END -#endif - ); - - enable_mmu_el1(0); -} - -/******************************************************************************* - * This function can be used by the platforms to update/use image - * information for given `image_id`. - ******************************************************************************/ -int bl2_plat_handle_post_image_load(unsigned int image_id) -{ - int err = 0; - bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); -#ifdef SPD_opteed - bl_mem_params_node_t *pager_mem_params = NULL; - bl_mem_params_node_t *paged_mem_params = NULL; -#endif - - assert(bl_mem_params != NULL); - - switch (image_id) { - case BL32_IMAGE_ID: -#ifdef SPD_opteed - pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); - assert(pager_mem_params); - - paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); - assert(paged_mem_params); - - err = parse_optee_header(&bl_mem_params->ep_info, - &pager_mem_params->image_info, - &paged_mem_params->image_info); - if (err != 0) - WARN("OPTEE header parse error.\n"); -#endif - bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl32_entry(); - break; - - case BL33_IMAGE_ID: - /* BL33 expects to receive the primary CPU MPID (through r0) */ - bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); - bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry(); - - /* Shutting down the SDHost driver to let BL33 drives SDHost.*/ - rpi3_sdhost_stop(); - break; - - default: - /* Do nothing in default case */ - break; - } - - return err; -} diff --git a/plat/rpi3/rpi3_bl31_setup.c b/plat/rpi3/rpi3_bl31_setup.c deleted file mode 100644 index 2f1bc6493..000000000 --- a/plat/rpi3/rpi3_bl31_setup.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include - -#include -#include -#include -#include - -#include "rpi3_private.h" - -/* - * Placeholder variables for copying the arguments that have been passed to - * BL31 from BL2. - */ -static entry_point_info_t bl32_image_ep_info; -static entry_point_info_t bl33_image_ep_info; - -/******************************************************************************* - * Return a pointer to the 'entry_point_info' structure of the next image for - * the security state specified. BL33 corresponds to the non-secure image type - * while BL32 corresponds to the secure image type. A NULL pointer is returned - * if the image does not exist. - ******************************************************************************/ -entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) -{ - entry_point_info_t *next_image_info; - - assert(sec_state_is_valid(type) != 0); - - next_image_info = (type == NON_SECURE) - ? &bl33_image_ep_info : &bl32_image_ep_info; - - /* None of the images can have 0x0 as the entrypoint. */ - if (next_image_info->pc) { - return next_image_info; - } else { - return NULL; - } -} - -/******************************************************************************* - * Perform any BL31 early platform setup. Here is an opportunity to copy - * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before - * they are lost (potentially). This needs to be done before the MMU is - * initialized so that the memory layout can be used while creating page - * tables. BL2 has flushed this information to memory, so we are guaranteed - * to pick up good data. - ******************************************************************************/ -void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, - u_register_t arg2, u_register_t arg3) - -{ - /* Initialize the console to provide early debug support */ - rpi3_console_init(); - - /* - * In debug builds, a special value is passed in 'arg1' to verify - * platform parameters from BL2 to BL31. Not used in release builds. - */ - assert(arg1 == RPI3_BL31_PLAT_PARAM_VAL); - - /* Check that params passed from BL2 are not NULL. */ - bl_params_t *params_from_bl2 = (bl_params_t *) arg0; - - assert(params_from_bl2 != NULL); - assert(params_from_bl2->h.type == PARAM_BL_PARAMS); - assert(params_from_bl2->h.version >= VERSION_2); - - bl_params_node_t *bl_params = params_from_bl2->head; - - /* - * Copy BL33 and BL32 (if present), entry point information. - * They are stored in Secure RAM, in BL2's address space. - */ - while (bl_params) { - if (bl_params->image_id == BL32_IMAGE_ID) { - bl32_image_ep_info = *bl_params->ep_info; - } - - if (bl_params->image_id == BL33_IMAGE_ID) { - bl33_image_ep_info = *bl_params->ep_info; - } - - bl_params = bl_params->next_params_info; - } - - if (bl33_image_ep_info.pc == 0) { - panic(); - } - -#if RPI3_DIRECT_LINUX_BOOT -# if RPI3_BL33_IN_AARCH32 - /* - * According to the file ``Documentation/arm/Booting`` of the Linux - * kernel tree, Linux expects: - * r0 = 0 - * r1 = machine type number, optional in DT-only platforms (~0 if so) - * r2 = Physical address of the device tree blob - */ - VERBOSE("rpi3: Preparing to boot 32-bit Linux kernel\n"); - bl33_image_ep_info.args.arg0 = 0U; - bl33_image_ep_info.args.arg1 = ~0U; - bl33_image_ep_info.args.arg2 = (u_register_t) RPI3_PRELOADED_DTB_BASE; -# else - /* - * According to the file ``Documentation/arm64/booting.txt`` of the - * Linux kernel tree, Linux expects the physical address of the device - * tree blob (DTB) in x0, while x1-x3 are reserved for future use and - * must be 0. - */ - VERBOSE("rpi3: Preparing to boot 64-bit Linux kernel\n"); - bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE; - bl33_image_ep_info.args.arg1 = 0ULL; - bl33_image_ep_info.args.arg2 = 0ULL; - bl33_image_ep_info.args.arg3 = 0ULL; -# endif /* RPI3_BL33_IN_AARCH32 */ -#endif /* RPI3_DIRECT_LINUX_BOOT */ -} - -void bl31_plat_arch_setup(void) -{ - rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE, - BL_CODE_BASE, BL_CODE_END, - BL_RO_DATA_BASE, BL_RO_DATA_END -#if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END -#endif - ); - - enable_mmu_el3(0); -} - -#ifdef RPI3_PRELOADED_DTB_BASE -/* - * Add information to the device tree (if any) about the reserved DRAM used by - * the Trusted Firmware. - */ -static void rpi3_dtb_add_mem_rsv(void) -{ - int i, regions, rc; - uint64_t addr, size; - void *dtb = (void *)RPI3_PRELOADED_DTB_BASE; - - INFO("rpi3: Checking DTB...\n"); - - /* Return if no device tree is detected */ - if (fdt_check_header(dtb) != 0) - return; - - regions = fdt_num_mem_rsv(dtb); - - VERBOSE("rpi3: Found %d mem reserve region(s)\n", regions); - - /* We expect to find one reserved region that we can modify */ - if (regions < 1) - return; - - /* - * Look for the region that corresponds to the default boot firmware. It - * starts at address 0, and it is not needed when the default firmware - * is replaced by this port of the Trusted Firmware. - */ - for (i = 0; i < regions; i++) { - if (fdt_get_mem_rsv(dtb, i, &addr, &size) != 0) - continue; - - if (addr != 0x0) - continue; - - VERBOSE("rpi3: Firmware mem reserve region found\n"); - - rc = fdt_del_mem_rsv(dtb, i); - if (rc != 0) { - INFO("rpi3: Can't remove mem reserve region (%d)\n", rc); - } - - break; - } - - if (i == regions) { - VERBOSE("rpi3: Firmware mem reserve region not found\n"); - } - - /* - * Reserve all SRAM. As said in the documentation, this isn't actually - * secure memory, so it is needed to tell BL33 that this is a reserved - * memory region. It doesn't guarantee it won't use it, though. - */ - rc = fdt_add_mem_rsv(dtb, SEC_SRAM_BASE, SEC_SRAM_SIZE); - if (rc != 0) { - WARN("rpi3: Can't add mem reserve region (%d)\n", rc); - } - - INFO("rpi3: Reserved 0x%llx - 0x%llx in DTB\n", SEC_SRAM_BASE, - SEC_SRAM_BASE + SEC_SRAM_SIZE); -} -#endif - -void bl31_platform_setup(void) -{ -#ifdef RPI3_PRELOADED_DTB_BASE - /* Only modify a DTB if we know where to look for it */ - rpi3_dtb_add_mem_rsv(); -#endif -} diff --git a/plat/rpi3/rpi3_common.c b/plat/rpi3/rpi3_common.c deleted file mode 100644 index 9b10974ad..000000000 --- a/plat/rpi3/rpi3_common.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "rpi3_hw.h" -#include "rpi3_private.h" - -#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ - DEVICE0_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ - SHARED_RAM_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#ifdef RPI3_PRELOADED_DTB_BASE -#define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \ - MT_MEMORY | MT_RW | MT_NS) -#endif - -#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \ - PLAT_RPI3_FIP_MAX_SIZE, \ - MT_MEMORY | MT_RO | MT_NS) - -#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) - -#ifdef SPD_opteed -#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \ - RPI3_OPTEE_PAGEABLE_LOAD_BASE, \ - RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) -#endif - -/* - * Table of regions for various BL stages to map using the MMU. - */ -#ifdef IMAGE_BL1 -static const mmap_region_t plat_rpi3_mmap[] = { - MAP_SHARED_RAM, - MAP_DEVICE0, - MAP_FIP, -#ifdef SPD_opteed - MAP_OPTEE_PAGEABLE, -#endif - {0} -}; -#endif - -#ifdef IMAGE_BL2 -static const mmap_region_t plat_rpi3_mmap[] = { - MAP_SHARED_RAM, - MAP_DEVICE0, - MAP_FIP, - MAP_NS_DRAM0, -#ifdef BL32_BASE - MAP_BL32_MEM, -#endif - {0} -}; -#endif - -#ifdef IMAGE_BL31 -static const mmap_region_t plat_rpi3_mmap[] = { - MAP_SHARED_RAM, - MAP_DEVICE0, -#ifdef RPI3_PRELOADED_DTB_BASE - MAP_NS_DTB, -#endif -#ifdef BL32_BASE - MAP_BL32_MEM, -#endif - {0} -}; -#endif - -/******************************************************************************* - * Function that sets up the console - ******************************************************************************/ -static console_16550_t rpi3_console; - -void rpi3_console_init(void) -{ - int console_scope = CONSOLE_FLAG_BOOT; -#if RPI3_RUNTIME_UART != -1 - console_scope |= CONSOLE_FLAG_RUNTIME; -#endif - int rc = console_16550_register(PLAT_RPI3_UART_BASE, - PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE, - &rpi3_console); - if (rc == 0) { - /* - * The crash console doesn't use the multi console API, it uses - * the core console functions directly. It is safe to call panic - * and let it print debug information. - */ - panic(); - } - - console_set_scope(&rpi3_console.console, console_scope); -} - -/******************************************************************************* - * Function that sets up the translation tables. - ******************************************************************************/ -void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, - uintptr_t code_start, uintptr_t code_limit, - uintptr_t rodata_start, uintptr_t rodata_limit -#if USE_COHERENT_MEM - , uintptr_t coh_start, uintptr_t coh_limit -#endif - ) -{ - /* - * Map the Trusted SRAM with appropriate memory attributes. - * Subsequent mappings will adjust the attributes for specific regions. - */ - VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", - (void *) total_base, (void *) (total_base + total_size)); - mmap_add_region(total_base, total_base, - total_size, - MT_MEMORY | MT_RW | MT_SECURE); - - /* Re-map the code section */ - VERBOSE("Code region: %p - %p\n", - (void *) code_start, (void *) code_limit); - mmap_add_region(code_start, code_start, - code_limit - code_start, - MT_CODE | MT_SECURE); - - /* Re-map the read-only data section */ - VERBOSE("Read-only data region: %p - %p\n", - (void *) rodata_start, (void *) rodata_limit); - mmap_add_region(rodata_start, rodata_start, - rodata_limit - rodata_start, - MT_RO_DATA | MT_SECURE); - -#if USE_COHERENT_MEM - /* Re-map the coherent memory region */ - VERBOSE("Coherent region: %p - %p\n", - (void *) coh_start, (void *) coh_limit); - mmap_add_region(coh_start, coh_start, - coh_limit - coh_start, - MT_DEVICE | MT_RW | MT_SECURE); -#endif - - mmap_add(plat_rpi3_mmap); - - init_xlat_tables(); -} - -/******************************************************************************* - * Return entrypoint of BL33. - ******************************************************************************/ -uintptr_t plat_get_ns_image_entrypoint(void) -{ -#ifdef PRELOADED_BL33_BASE - return PRELOADED_BL33_BASE; -#else - return PLAT_RPI3_NS_IMAGE_OFFSET; -#endif -} - -/******************************************************************************* - * Gets SPSR for BL32 entry - ******************************************************************************/ -uint32_t rpi3_get_spsr_for_bl32_entry(void) -{ - /* - * The Secure Payload Dispatcher service is responsible for - * setting the SPSR prior to entry into the BL32 image. - */ - return 0; -} - -/******************************************************************************* - * Gets SPSR for BL33 entry - ******************************************************************************/ -uint32_t rpi3_get_spsr_for_bl33_entry(void) -{ -#if RPI3_BL33_IN_AARCH32 - INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n"); - return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE, - DISABLE_ALL_EXCEPTIONS); -#else - return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); -#endif -} - -unsigned int plat_get_syscnt_freq2(void) -{ - return SYS_COUNTER_FREQ_IN_TICKS; -} - -uint32_t plat_ic_get_pending_interrupt_type(void) -{ - ERROR("rpi3: Interrupt routed to EL3.\n"); - return INTR_TYPE_INVAL; -} - -uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) -{ - assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) || - (type == INTR_TYPE_NS)); - - assert(sec_state_is_valid(security_state)); - - /* Non-secure interrupts are signalled on the IRQ line always. */ - if (type == INTR_TYPE_NS) - return __builtin_ctz(SCR_IRQ_BIT); - - /* Secure interrupts are signalled on the FIQ line always. */ - return __builtin_ctz(SCR_FIQ_BIT); -} diff --git a/plat/rpi3/rpi3_hw.h b/plat/rpi3/rpi3_hw.h deleted file mode 100644 index 1a86835b3..000000000 --- a/plat/rpi3/rpi3_hw.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef RPI3_HW_H -#define RPI3_HW_H - -#include - -/* - * Peripherals - */ - -#define RPI3_IO_BASE ULL(0x3F000000) -#define RPI3_IO_SIZE ULL(0x01000000) - -/* - * ARM <-> VideoCore mailboxes - */ -#define RPI3_MBOX_OFFSET ULL(0x0000B880) -#define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET) -/* VideoCore -> ARM */ -#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) -#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) -#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) -#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) -#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) -/* ARM -> VideoCore */ -#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) -#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) -#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) -#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) -#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) -/* Mailbox status constants */ -#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ -#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ - -/* - * Power management, reset controller, watchdog. - */ -#define RPI3_IO_PM_OFFSET ULL(0x00100000) -#define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET) -/* Registers on top of RPI3_PM_BASE. */ -#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) -#define RPI3_PM_RSTS_OFFSET ULL(0x00000020) -#define RPI3_PM_WDOG_OFFSET ULL(0x00000024) -/* Watchdog constants */ -#define RPI3_PM_PASSWORD U(0x5A000000) -#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) -#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) -/* - * The RSTS register is used by the VideoCore firmware when booting the - * Raspberry Pi to know which partition to boot from. The partition value is - * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware - * to indicate halt. - */ -#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) - -/* - * Hardware random number generator. - */ -#define RPI3_IO_RNG_OFFSET ULL(0x00104000) -#define RPI3_RNG_BASE (RPI3_IO_BASE + RPI3_IO_RNG_OFFSET) -#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) -#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) -#define RPI3_RNG_DATA_OFFSET ULL(0x00000008) -#define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010) -/* Enable/disable RNG */ -#define RPI3_RNG_CTRL_ENABLE U(0x1) -#define RPI3_RNG_CTRL_DISABLE U(0x0) -/* Number of currently available words */ -#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24) -#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF) -/* Value to mask interrupts caused by the RNG */ -#define RPI3_RNG_INT_MASK_DISABLE U(0x1) - -/* - * Serial port (called 'Mini UART' in the BCM docucmentation). - */ -#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) -#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET) -#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) - -/* - * GPIO controller - */ -#define RPI3_IO_GPIO_OFFSET ULL(0x00200000) -#define RPI3_GPIO_BASE (RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET) - -/* - * SDHost controller - */ -#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) -#define RPI3_SDHOST_BASE (RPI3_IO_BASE + RPI3_IO_SDHOST_OFFSET) - -/* - * Local interrupt controller - */ -#define RPI3_INTC_BASE_ADDRESS ULL(0x40000000) -/* Registers on top of RPI3_INTC_BASE_ADDRESS */ -#define RPI3_INTC_CONTROL_OFFSET ULL(0x00000000) -#define RPI3_INTC_PRESCALER_OFFSET ULL(0x00000008) -#define RPI3_INTC_MBOX_CONTROL_OFFSET ULL(0x00000050) -#define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ ULL(0x00000080) -#define RPI3_INTC_PENDING_FIQ_OFFSET ULL(0x00000070) -#define RPI3_INTC_PENDING_FIQ_MBOX3 ULL(0x00000080) - -#endif /* RPI3_HW_H */ diff --git a/plat/rpi3/rpi3_image_load.c b/plat/rpi3/rpi3_image_load.c deleted file mode 100644 index 5394c6f7c..000000000 --- a/plat/rpi3/rpi3_image_load.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include - -/******************************************************************************* - * This function flushes the data structures so that they are visible - * in memory for the next BL image. - ******************************************************************************/ -void plat_flush_next_bl_params(void) -{ - flush_bl_params_desc(); -} - -/******************************************************************************* - * This function returns the list of loadable images. - ******************************************************************************/ -bl_load_info_t *plat_get_bl_image_load_info(void) -{ - return get_bl_load_info_from_mem_params_desc(); -} - -/******************************************************************************* - * This function returns the list of executable images. - ******************************************************************************/ -bl_params_t *plat_get_next_bl_params(void) -{ - return get_next_bl_params_from_mem_params_desc(); -} diff --git a/plat/rpi3/rpi3_io_storage.c b/plat/rpi3/rpi3_io_storage.c deleted file mode 100644 index 49c6a760c..000000000 --- a/plat/rpi3/rpi3_io_storage.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -/* Semihosting filenames */ -#define BL2_IMAGE_NAME "bl2.bin" -#define BL31_IMAGE_NAME "bl31.bin" -#define BL32_IMAGE_NAME "bl32.bin" -#define BL33_IMAGE_NAME "bl33.bin" - -#if TRUSTED_BOARD_BOOT -#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt" -#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" -#define SOC_FW_KEY_CERT_NAME "soc_fw_key.crt" -#define TOS_FW_KEY_CERT_NAME "tos_fw_key.crt" -#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt" -#define SOC_FW_CONTENT_CERT_NAME "soc_fw_content.crt" -#define TOS_FW_CONTENT_CERT_NAME "tos_fw_content.crt" -#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt" -#endif /* TRUSTED_BOARD_BOOT */ - -/* IO devices */ -static const io_dev_connector_t *fip_dev_con; -static uintptr_t fip_dev_handle; -static const io_dev_connector_t *memmap_dev_con; -static uintptr_t memmap_dev_handle; - -static const io_block_spec_t fip_block_spec = { - .offset = PLAT_RPI3_FIP_BASE, - .length = PLAT_RPI3_FIP_MAX_SIZE -}; - -static const io_uuid_spec_t bl2_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, -}; - -static const io_uuid_spec_t bl31_uuid_spec = { - .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, -}; - -static const io_uuid_spec_t bl32_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32, -}; - -static const io_uuid_spec_t bl32_extra1_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, -}; - -static const io_uuid_spec_t bl32_extra2_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, -}; - -static const io_uuid_spec_t bl33_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, -}; - -#if TRUSTED_BOARD_BOOT -static const io_uuid_spec_t tb_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FW_CERT, -}; - -static const io_uuid_spec_t trusted_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_KEY_CERT, -}; - -static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = { - .uuid = UUID_SOC_FW_KEY_CERT, -}; - -static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, -}; - -static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, -}; - -static const io_uuid_spec_t soc_fw_cert_uuid_spec = { - .uuid = UUID_SOC_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t tos_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t nt_fw_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, -}; -#endif /* TRUSTED_BOARD_BOOT */ - -static int open_fip(const uintptr_t spec); -static int open_memmap(const uintptr_t spec); - -struct plat_io_policy { - uintptr_t *dev_handle; - uintptr_t image_spec; - int (*check)(const uintptr_t spec); -}; - -/* By default, load images from the FIP */ -static const struct plat_io_policy policies[] = { - [FIP_IMAGE_ID] = { - &memmap_dev_handle, - (uintptr_t)&fip_block_spec, - open_memmap - }, - [BL2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl2_uuid_spec, - open_fip - }, - [BL31_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl31_uuid_spec, - open_fip - }, - [BL32_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_uuid_spec, - open_fip - }, - [BL32_EXTRA1_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra1_uuid_spec, - open_fip - }, - [BL32_EXTRA2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra2_uuid_spec, - open_fip - }, - [BL33_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl33_uuid_spec, - open_fip - }, -#if TRUSTED_BOARD_BOOT - [TRUSTED_BOOT_FW_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tb_fw_cert_uuid_spec, - open_fip - }, - [TRUSTED_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&trusted_key_cert_uuid_spec, - open_fip - }, - [SOC_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&soc_fw_key_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_key_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_key_cert_uuid_spec, - open_fip - }, - [SOC_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&soc_fw_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_cert_uuid_spec, - open_fip - }, -#endif /* TRUSTED_BOARD_BOOT */ -}; - -static int open_fip(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - /* See if a Firmware Image Package is available */ - result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); - if (result == 0) { - result = io_open(fip_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using FIP\n"); - io_close(local_image_handle); - } - } - return result; -} - -static int open_memmap(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); - if (result == 0) { - result = io_open(memmap_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using Memmap\n"); - io_close(local_image_handle); - } - } - return result; -} - -void plat_rpi3_io_setup(void) -{ - int io_result; - - io_result = register_io_dev_fip(&fip_dev_con); - assert(io_result == 0); - - io_result = register_io_dev_memmap(&memmap_dev_con); - assert(io_result == 0); - - /* Open connections to devices and cache the handles */ - io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, - &fip_dev_handle); - assert(io_result == 0); - - io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, - &memmap_dev_handle); - assert(io_result == 0); - - /* Ignore improbable errors in release builds */ - (void)io_result; -} - -/* - * Return an IO device handle and specification which can be used to access - * an image. Use this to enforce platform load policy - */ -int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int result; - const struct plat_io_policy *policy; - - assert(image_id < ARRAY_SIZE(policies)); - - policy = &policies[image_id]; - result = policy->check(policy->image_spec); - if (result == 0) { - *image_spec = policy->image_spec; - *dev_handle = *(policy->dev_handle); - } - - return result; -} diff --git a/plat/rpi3/rpi3_mbox.c b/plat/rpi3/rpi3_mbox.c deleted file mode 100644 index 2db605edf..000000000 --- a/plat/rpi3/rpi3_mbox.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include - -#include "rpi3_hw.h" - -/* This struct must be aligned to 16 bytes */ -typedef struct __packed __aligned(16) rpi3_mbox_request { - uint32_t size; /* Buffer size in bytes */ - uint32_t code; /* Request/response code */ - uint32_t tags[0]; -} rpi3_mbox_request_t; - -#define RPI3_MBOX_BUFFER_SIZE U(256) -static uint8_t __aligned(16) rpi3_mbox_buffer[RPI3_MBOX_BUFFER_SIZE]; - -/* Constants to perform a request/check the status of a request. */ -#define RPI3_MBOX_PROCESS_REQUEST U(0x00000000) -#define RPI3_MBOX_REQUEST_SUCCESSFUL U(0x80000000) -#define RPI3_MBOX_REQUEST_ERROR U(0x80000001) - -/* Command constants */ -#define RPI3_TAG_HARDWARE_GET_BOARD_REVISION U(0x00010002) -#define RPI3_TAG_END U(0x00000000) - -#define RPI3_TAG_REQUEST U(0x00000000) -#define RPI3_TAG_IS_RESPONSE U(0x80000000) /* Set if response */ -#define RPI3_TAG_RESPONSE_LENGTH_MASK U(0x7FFFFFFF) - -#define RPI3_CHANNEL_ARM_TO_VC U(0x8) -#define RPI3_CHANNEL_MASK U(0xF) - -#define RPI3_MAILBOX_MAX_RETRIES U(1000000) - -/******************************************************************************* - * Helpers to send requests to the VideoCore using the mailboxes. - ******************************************************************************/ -static void rpi3_vc_mailbox_request_send(void) -{ - uint32_t st, data; - uintptr_t resp_addr, addr; - unsigned int retries; - - /* This is the location of the request buffer */ - addr = (uintptr_t) &rpi3_mbox_buffer; - - /* Make sure that the changes are seen by the VideoCore */ - flush_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE); - - /* Wait until the outbound mailbox is empty */ - retries = 0U; - - do { - st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET); - - retries++; - if (retries == RPI3_MAILBOX_MAX_RETRIES) { - ERROR("rpi3: mbox: Send request timeout\n"); - return; - } - - } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U); - - /* Send base address of this message to start request */ - mmio_write_32(RPI3_MBOX_BASE + RPI3_MBOX1_WRITE_OFFSET, - RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr); - - /* Wait until the inbound mailbox isn't empty */ - retries = 0U; - - do { - st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET); - - retries++; - if (retries == RPI3_MAILBOX_MAX_RETRIES) { - ERROR("rpi3: mbox: Receive response timeout\n"); - return; - } - - } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U); - - /* Get location and channel */ - data = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_READ_OFFSET); - - if ((data & RPI3_CHANNEL_MASK) != RPI3_CHANNEL_ARM_TO_VC) { - ERROR("rpi3: mbox: Wrong channel: 0x%08x\n", data); - panic(); - } - - resp_addr = (uintptr_t)(data & ~RPI3_CHANNEL_MASK); - if (addr != resp_addr) { - ERROR("rpi3: mbox: Unexpected address: 0x%08x\n", data); - panic(); - } - - /* Make sure that the data seen by the CPU is up to date */ - inv_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE); -} - -/******************************************************************************* - * Request board revision. Returns the revision and 0 on success, -1 on error. - ******************************************************************************/ -int rpi3_vc_hardware_get_board_revision(uint32_t *revision) -{ - uint32_t tag_request_size = sizeof(uint32_t); - rpi3_mbox_request_t *req = (rpi3_mbox_request_t *) rpi3_mbox_buffer; - - assert(revision != NULL); - - VERBOSE("rpi3: mbox: Sending request at %p\n", (void *)req); - - req->size = sizeof(rpi3_mbox_buffer); - req->code = RPI3_MBOX_PROCESS_REQUEST; - - req->tags[0] = RPI3_TAG_HARDWARE_GET_BOARD_REVISION; - req->tags[1] = tag_request_size; /* Space available for the response */ - req->tags[2] = RPI3_TAG_REQUEST; - req->tags[3] = 0; /* Placeholder for the response */ - - req->tags[4] = RPI3_TAG_END; - - rpi3_vc_mailbox_request_send(); - - if (req->code != RPI3_MBOX_REQUEST_SUCCESSFUL) { - ERROR("rpi3: mbox: Code = 0x%08x\n", req->code); - return -1; - } - - if (req->tags[2] != (RPI3_TAG_IS_RESPONSE | tag_request_size)) { - ERROR("rpi3: mbox: get board revision failed (0x%08x)\n", - req->tags[2]); - return -1; - } - - *revision = req->tags[3]; - - return 0; -} diff --git a/plat/rpi3/rpi3_pm.c b/plat/rpi3/rpi3_pm.c deleted file mode 100644 index 4f586b514..000000000 --- a/plat/rpi3/rpi3_pm.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include -#include -#include -#include - -#include "rpi3_hw.h" - -/* Make composite power state parameter till power level 0 */ -#if PSCI_EXTENDED_STATE_ID - -#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ - (((lvl0_state) << PSTATE_ID_SHIFT) | \ - ((type) << PSTATE_TYPE_SHIFT)) - -#else - -#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ - (((lvl0_state) << PSTATE_ID_SHIFT) | \ - ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ - ((type) << PSTATE_TYPE_SHIFT)) - -#endif /* PSCI_EXTENDED_STATE_ID */ - -#define rpi3_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ - (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ - rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) - -/* - * The table storing the valid idle power states. Ensure that the - * array entries are populated in ascending order of state-id to - * enable us to use binary search during power state validation. - * The table must be terminated by a NULL entry. - */ -static const unsigned int rpi3_pm_idle_states[] = { - /* State-id - 0x01 */ - rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, - MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), - /* State-id - 0x02 */ - rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, - MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), - /* State-id - 0x22 */ - rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, - MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), - 0, -}; - -/******************************************************************************* - * Platform handler called to check the validity of the power state - * parameter. The power state parameter has to be a composite power state. - ******************************************************************************/ -static int rpi3_validate_power_state(unsigned int power_state, - psci_power_state_t *req_state) -{ - unsigned int state_id; - int i; - - assert(req_state != 0); - - /* - * Currently we are using a linear search for finding the matching - * entry in the idle power state array. This can be made a binary - * search if the number of entries justify the additional complexity. - */ - for (i = 0; rpi3_pm_idle_states[i] != 0; i++) { - if (power_state == rpi3_pm_idle_states[i]) { - break; - } - } - - /* Return error if entry not found in the idle state array */ - if (!rpi3_pm_idle_states[i]) { - return PSCI_E_INVALID_PARAMS; - } - - i = 0; - state_id = psci_get_pstate_id(power_state); - - /* Parse the State ID and populate the state info parameter */ - while (state_id) { - req_state->pwr_domain_state[i++] = state_id & - PLAT_LOCAL_PSTATE_MASK; - state_id >>= PLAT_LOCAL_PSTATE_WIDTH; - } - - return PSCI_E_SUCCESS; -} - -/******************************************************************************* - * Platform handler called when a CPU is about to enter standby. - ******************************************************************************/ -static void rpi3_cpu_standby(plat_local_state_t cpu_state) -{ - assert(cpu_state == PLAT_LOCAL_STATE_RET); - - /* - * Enter standby state. - * dsb is good practice before using wfi to enter low power states - */ - dsb(); - wfi(); -} - -/******************************************************************************* - * Platform handler called when a power domain is about to be turned on. The - * mpidr determines the CPU to be turned on. - ******************************************************************************/ -static int rpi3_pwr_domain_on(u_register_t mpidr) -{ - int rc = PSCI_E_SUCCESS; - unsigned int pos = plat_core_pos_by_mpidr(mpidr); - uint64_t *hold_base = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; - - assert(pos < PLATFORM_CORE_COUNT); - - hold_base[pos] = PLAT_RPI3_TM_HOLD_STATE_GO; - - /* Make sure that the write has completed */ - dsb(); - isb(); - - sev(); - - return rc; -} - -/******************************************************************************* - * Platform handler called when a power domain has just been powered on after - * being turned off earlier. The target_state encodes the low power state that - * each level has woken up from. - ******************************************************************************/ -static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state) -{ - assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == - PLAT_LOCAL_STATE_OFF); -} - -/******************************************************************************* - * Platform handlers for system reset and system off. - ******************************************************************************/ - -/* 10 ticks (Watchdog timer = Timer clock / 16) */ -#define RESET_TIMEOUT U(10) - -static void __dead2 rpi3_watchdog_reset(void) -{ - uint32_t rstc; - - console_flush(); - - dsbsy(); - isb(); - - mmio_write_32(RPI3_PM_BASE + RPI3_PM_WDOG_OFFSET, - RPI3_PM_PASSWORD | RESET_TIMEOUT); - - rstc = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET); - rstc &= ~RPI3_PM_RSTC_WRCFG_MASK; - rstc |= RPI3_PM_PASSWORD | RPI3_PM_RSTC_WRCFG_FULL_RESET; - mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET, rstc); - - for (;;) { - wfi(); - } -} - -static void __dead2 rpi3_system_reset(void) -{ - INFO("rpi3: PSCI_SYSTEM_RESET: Invoking watchdog reset\n"); - - rpi3_watchdog_reset(); -} - -static void __dead2 rpi3_system_off(void) -{ - uint32_t rsts; - - INFO("rpi3: PSCI_SYSTEM_OFF: Invoking watchdog reset\n"); - - /* - * This function doesn't actually make the Raspberry Pi turn itself off, - * the hardware doesn't allow it. It simply reboots it and the RSTS - * value tells the bootcode.bin firmware not to continue the regular - * bootflow and to stay in a low power mode. - */ - - rsts = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET); - rsts |= RPI3_PM_PASSWORD | RPI3_PM_RSTS_WRCFG_HALT; - mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET, rsts); - - rpi3_watchdog_reset(); -} - -/******************************************************************************* - * Platform handlers and setup function. - ******************************************************************************/ -static const plat_psci_ops_t plat_rpi3_psci_pm_ops = { - .cpu_standby = rpi3_cpu_standby, - .pwr_domain_on = rpi3_pwr_domain_on, - .pwr_domain_on_finish = rpi3_pwr_domain_on_finish, - .system_off = rpi3_system_off, - .system_reset = rpi3_system_reset, - .validate_power_state = rpi3_validate_power_state, -}; - -int plat_setup_psci_ops(uintptr_t sec_entrypoint, - const plat_psci_ops_t **psci_ops) -{ - uintptr_t *entrypoint = (void *) PLAT_RPI3_TM_ENTRYPOINT; - - *entrypoint = sec_entrypoint; - *psci_ops = &plat_rpi3_psci_pm_ops; - - return 0; -} diff --git a/plat/rpi3/rpi3_private.h b/plat/rpi3/rpi3_private.h deleted file mode 100644 index 53078f8e9..000000000 --- a/plat/rpi3/rpi3_private.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef RPI3_PRIVATE_H -#define RPI3_PRIVATE_H - -#include - -/******************************************************************************* - * Function and variable prototypes - ******************************************************************************/ - -/* Utility functions */ -void rpi3_console_init(void); -void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, - uintptr_t code_start, uintptr_t code_limit, - uintptr_t rodata_start, uintptr_t rodata_limit -#if USE_COHERENT_MEM - , uintptr_t coh_start, uintptr_t coh_limit -#endif - ); - -/* Optional functions required in the Raspberry Pi 3 port */ -unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr); - -/* BL2 utility functions */ -uint32_t rpi3_get_spsr_for_bl32_entry(void); -uint32_t rpi3_get_spsr_for_bl33_entry(void); - -/* IO storage utility functions */ -void plat_rpi3_io_setup(void); - -/* Hardware RNG functions */ -void rpi3_rng_read(void *buf, size_t len); - -/* VideoCore firmware commands */ -int rpi3_vc_hardware_get_board_revision(uint32_t *revision); - -#endif /* RPI3_PRIVATE_H */ diff --git a/plat/rpi3/rpi3_rng.c b/plat/rpi3/rpi3_rng.c deleted file mode 100644 index fd69adbf3..000000000 --- a/plat/rpi3/rpi3_rng.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include "rpi3_hw.h" - -/* Initial amount of values to discard */ -#define RNG_WARMUP_COUNT U(0x40000) - -static void rpi3_rng_initialize(void) -{ - uint32_t int_mask, ctrl; - - /* Return if it is already enabled */ - ctrl = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET); - if ((ctrl & RPI3_RNG_CTRL_ENABLE) != 0U) { - return; - } - - /* Mask interrupts */ - int_mask = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET); - int_mask |= RPI3_RNG_INT_MASK_DISABLE; - mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET, int_mask); - - /* Discard several values when initializing to give it time to warmup */ - mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET, RNG_WARMUP_COUNT); - - mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET, - RPI3_RNG_CTRL_ENABLE); -} - -static uint32_t rpi3_rng_get_word(void) -{ - size_t nwords; - - do { - /* Get number of available words to read */ - nwords = (mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET) - >> RPI3_RNG_STATUS_NUM_WORDS_SHIFT) - & RPI3_RNG_STATUS_NUM_WORDS_MASK; - } while (nwords == 0U); - - return mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_DATA_OFFSET); -} - -void rpi3_rng_read(void *buf, size_t len) -{ - uint32_t data; - size_t left = len; - uint32_t *dst = buf; - - assert(buf != NULL); - assert(len != 0U); - assert(check_uptr_overflow((uintptr_t) buf, (uintptr_t) len) == 0); - - rpi3_rng_initialize(); - - while (left >= sizeof(uint32_t)) { - data = rpi3_rng_get_word(); - *dst++ = data; - left -= sizeof(uint32_t); - } - - if (left > 0U) { - data = rpi3_rng_get_word(); - memcpy(dst, &data, left); - } -} diff --git a/plat/rpi3/rpi3_rotpk.S b/plat/rpi3/rpi3_rotpk.S deleted file mode 100644 index 1c17b2141..000000000 --- a/plat/rpi3/rpi3_rotpk.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - - .global rpi3_rotpk_hash - .global rpi3_rotpk_hash_end -rpi3_rotpk_hash: - /* DER header */ - .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 - .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 - /* SHA256 */ - .incbin ROTPK_HASH -rpi3_rotpk_hash_end: diff --git a/plat/rpi3/rpi3_stack_protector.c b/plat/rpi3/rpi3_stack_protector.c deleted file mode 100644 index 6f49f617b..000000000 --- a/plat/rpi3/rpi3_stack_protector.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -#include "rpi3_private.h" - -/* Get 128 bits of entropy and fuse the values together to form the canary. */ -#define TRNG_NBYTES 16U - -u_register_t plat_get_stack_protector_canary(void) -{ - size_t i; - u_register_t buf[TRNG_NBYTES / sizeof(u_register_t)]; - u_register_t ret = 0U; - - rpi3_rng_read(buf, sizeof(buf)); - - for (i = 0U; i < ARRAY_SIZE(buf); i++) - ret ^= buf[i]; - - return ret; -} diff --git a/plat/rpi3/rpi3_topology.c b/plat/rpi3/rpi3_topology.c deleted file mode 100644 index 200d41dd1..000000000 --- a/plat/rpi3/rpi3_topology.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include - -#include "rpi3_private.h" - -/* The power domain tree descriptor */ -static unsigned char power_domain_tree_desc[] = { - /* Number of root nodes */ - PLATFORM_CLUSTER_COUNT, - /* Number of children for the first node */ - PLATFORM_CLUSTER0_CORE_COUNT, -}; - -/******************************************************************************* - * This function returns the ARM default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { - return -1; - } - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) { - return -1; - } - - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { - return -1; - } - - return plat_rpi3_calc_core_pos(mpidr); -} diff --git a/plat/rpi3/rpi3_trusted_boot.c b/plat/rpi3/rpi3_trusted_boot.c deleted file mode 100644 index f6c669fad..000000000 --- a/plat/rpi3/rpi3_trusted_boot.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -extern char rpi3_rotpk_hash[], rpi3_rotpk_hash_end[]; - -int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, - unsigned int *flags) -{ - *key_ptr = rpi3_rotpk_hash; - *key_len = rpi3_rotpk_hash_end - rpi3_rotpk_hash; - *flags = ROTPK_IS_HASH; - - return 0; -} - -int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) -{ - *nv_ctr = 0; - - return 0; -} - -int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) -{ - return 1; -} - -int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) -{ - return get_mbedtls_heap_helper(heap_addr, heap_size); -} -- cgit v1.2.3 From 990ab78e788093d30b9416927fafb3bc13fa086f Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 9 Jul 2019 14:29:24 +0100 Subject: rpi3: Move rng driver to drivers To allow sharing the driver between the RPi3 and RPi4, move the random number generator driver into the generic driver directory. Change-Id: Iae94d7cb22c6bce3af9bff709d76d4caf87b14d1 Signed-off-by: Andre Przywara --- drivers/rpi3/rng/rpi3_rng.c | 75 +++++++++++++++++++++++++++++++++++++ include/drivers/rpi3/rng/rpi3_rng.h | 12 ++++++ plat/rpi/rpi3/platform.mk | 4 +- plat/rpi/rpi3/rpi3_private.h | 5 +-- plat/rpi/rpi3/rpi3_rng.c | 75 ------------------------------------- 5 files changed, 90 insertions(+), 81 deletions(-) create mode 100644 drivers/rpi3/rng/rpi3_rng.c create mode 100644 include/drivers/rpi3/rng/rpi3_rng.h delete mode 100644 plat/rpi/rpi3/rpi3_rng.c diff --git a/drivers/rpi3/rng/rpi3_rng.c b/drivers/rpi3/rng/rpi3_rng.c new file mode 100644 index 000000000..b6bf0052a --- /dev/null +++ b/drivers/rpi3/rng/rpi3_rng.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include + +/* Initial amount of values to discard */ +#define RNG_WARMUP_COUNT U(0x40000) + +static void rpi3_rng_initialize(void) +{ + uint32_t int_mask, ctrl; + + /* Return if it is already enabled */ + ctrl = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET); + if ((ctrl & RPI3_RNG_CTRL_ENABLE) != 0U) { + return; + } + + /* Mask interrupts */ + int_mask = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET); + int_mask |= RPI3_RNG_INT_MASK_DISABLE; + mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET, int_mask); + + /* Discard several values when initializing to give it time to warmup */ + mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET, RNG_WARMUP_COUNT); + + mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET, + RPI3_RNG_CTRL_ENABLE); +} + +static uint32_t rpi3_rng_get_word(void) +{ + size_t nwords; + + do { + /* Get number of available words to read */ + nwords = (mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET) + >> RPI3_RNG_STATUS_NUM_WORDS_SHIFT) + & RPI3_RNG_STATUS_NUM_WORDS_MASK; + } while (nwords == 0U); + + return mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_DATA_OFFSET); +} + +void rpi3_rng_read(void *buf, size_t len) +{ + uint32_t data; + size_t left = len; + uint32_t *dst = buf; + + assert(buf != NULL); + assert(len != 0U); + assert(check_uptr_overflow((uintptr_t) buf, (uintptr_t) len) == 0); + + rpi3_rng_initialize(); + + while (left >= sizeof(uint32_t)) { + data = rpi3_rng_get_word(); + *dst++ = data; + left -= sizeof(uint32_t); + } + + if (left > 0U) { + data = rpi3_rng_get_word(); + memcpy(dst, &data, left); + } +} diff --git a/include/drivers/rpi3/rng/rpi3_rng.h b/include/drivers/rpi3/rng/rpi3_rng.h new file mode 100644 index 000000000..ea5a67708 --- /dev/null +++ b/include/drivers/rpi3/rng/rpi3_rng.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI3_RNG_H +#define RPI3_RNG_H + +void rpi3_rng_read(void *buf, size_t len); + +#endif diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk index b0e7b7097..21a880c0d 100644 --- a/plat/rpi/rpi3/platform.mk +++ b/plat/rpi/rpi3/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -159,7 +159,7 @@ ifeq (${ARCH},aarch32) endif ifneq ($(ENABLE_STACK_PROTECTOR), 0) -PLAT_BL_COMMON_SOURCES += plat/rpi/rpi3/rpi3_rng.c \ +PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \ plat/rpi/rpi3/rpi3_stack_protector.c endif diff --git a/plat/rpi/rpi3/rpi3_private.h b/plat/rpi/rpi3/rpi3_private.h index 53078f8e9..b01c40c30 100644 --- a/plat/rpi/rpi3/rpi3_private.h +++ b/plat/rpi/rpi3/rpi3_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,9 +33,6 @@ uint32_t rpi3_get_spsr_for_bl33_entry(void); /* IO storage utility functions */ void plat_rpi3_io_setup(void); -/* Hardware RNG functions */ -void rpi3_rng_read(void *buf, size_t len); - /* VideoCore firmware commands */ int rpi3_vc_hardware_get_board_revision(uint32_t *revision); diff --git a/plat/rpi/rpi3/rpi3_rng.c b/plat/rpi/rpi3/rpi3_rng.c deleted file mode 100644 index b6bf0052a..000000000 --- a/plat/rpi/rpi3/rpi3_rng.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include - -/* Initial amount of values to discard */ -#define RNG_WARMUP_COUNT U(0x40000) - -static void rpi3_rng_initialize(void) -{ - uint32_t int_mask, ctrl; - - /* Return if it is already enabled */ - ctrl = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET); - if ((ctrl & RPI3_RNG_CTRL_ENABLE) != 0U) { - return; - } - - /* Mask interrupts */ - int_mask = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET); - int_mask |= RPI3_RNG_INT_MASK_DISABLE; - mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET, int_mask); - - /* Discard several values when initializing to give it time to warmup */ - mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET, RNG_WARMUP_COUNT); - - mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET, - RPI3_RNG_CTRL_ENABLE); -} - -static uint32_t rpi3_rng_get_word(void) -{ - size_t nwords; - - do { - /* Get number of available words to read */ - nwords = (mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET) - >> RPI3_RNG_STATUS_NUM_WORDS_SHIFT) - & RPI3_RNG_STATUS_NUM_WORDS_MASK; - } while (nwords == 0U); - - return mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_DATA_OFFSET); -} - -void rpi3_rng_read(void *buf, size_t len) -{ - uint32_t data; - size_t left = len; - uint32_t *dst = buf; - - assert(buf != NULL); - assert(len != 0U); - assert(check_uptr_overflow((uintptr_t) buf, (uintptr_t) len) == 0); - - rpi3_rng_initialize(); - - while (left >= sizeof(uint32_t)) { - data = rpi3_rng_get_word(); - *dst++ = data; - left -= sizeof(uint32_t); - } - - if (left > 0U) { - data = rpi3_rng_get_word(); - memcpy(dst, &data, left); - } -} -- cgit v1.2.3 From 3ef45dda88c83413c2c554212956d7966fab2807 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 09:00:23 +0100 Subject: Add fdt_add_reserved_memory() helper function If a firmware component like TF-A reserves special memory regions for its own or secure payload services, it should announce the location and size of those regions to the non-secure world. This will avoid disappointment when some rich OS tries to acccess this memory, which will likely end in a crash. The traditional way of advertising reserved memory using device tree is using the special memreserve feature of the device tree blob (DTB). However by definition those regions mentioned there do not prevent the rich OS to map this memory, which may lead to speculative accesses to this memory and hence spurious bus errors. A safer way of carving out memory is to use the /reserved-memory node as part of the normal DT structure. Besides being easier to setup, this also defines an explicit "no-map" property to signify the secure-only nature of certain memory regions, which avoids the rich OS to accidentally step on it. Add a helper function to allow platform ports to easily add a region. Change-Id: I2b92676cf48fd3bdacda05b5c6b1c7952ebed68c Signed-off-by: Andre Przywara --- common/fdt_fixup.c | 30 ++++++++++++++++++++++++++++++ include/common/fdt_fixup.h | 2 ++ 2 files changed, 32 insertions(+) diff --git a/common/fdt_fixup.c b/common/fdt_fixup.c index 0ae0050c0..8843404df 100644 --- a/common/fdt_fixup.c +++ b/common/fdt_fixup.c @@ -9,6 +9,9 @@ * payloads like BL32 and BL33 (and further down the boot chain). * This allows to easily add PSCI nodes, when the original DT does not have * it or advertises another method. + * Also it supports to add reserved memory nodes to describe memory that + * is used by the secure world, so that non-secure software avoids using + * that. */ #include @@ -124,3 +127,30 @@ int dt_add_psci_cpu_enable_methods(void *fdt) return ret; } + +#define HIGH_BITS(x) ((sizeof(x) > 4) ? ((x) >> 32) : (typeof(x))0) + +int fdt_add_reserved_memory(void *dtb, const char *node_name, + uintptr_t base, size_t size) +{ + int offs = fdt_path_offset(dtb, "/reserved-memory"); + uint32_t addresses[3]; + + if (offs < 0) { /* create if not existing yet */ + offs = fdt_add_subnode(dtb, 0, "reserved-memory"); + if (offs < 0) + return offs; + fdt_setprop_u32(dtb, offs, "#address-cells", 2); + fdt_setprop_u32(dtb, offs, "#size-cells", 1); + fdt_setprop(dtb, offs, "ranges", NULL, 0); + } + + addresses[0] = cpu_to_fdt32(HIGH_BITS(base)); + addresses[1] = cpu_to_fdt32(base & 0xffffffff); + addresses[2] = cpu_to_fdt32(size & 0xffffffff); + offs = fdt_add_subnode(dtb, offs, node_name); + fdt_setprop(dtb, offs, "no-map", NULL, 0); + fdt_setprop(dtb, offs, "reg", addresses, 12); + + return 0; +} diff --git a/include/common/fdt_fixup.h b/include/common/fdt_fixup.h index bb05bf5d0..0248de9cf 100644 --- a/include/common/fdt_fixup.h +++ b/include/common/fdt_fixup.h @@ -9,5 +9,7 @@ int dt_add_psci_node(void *fdt); int dt_add_psci_cpu_enable_methods(void *fdt); +int fdt_add_reserved_memory(void *dtb, const char *node_name, + uintptr_t base, size_t size); #endif /* FDT_FIXUP_H */ -- cgit v1.2.3 From dcf6d4f8edfe76b3a01cbb80549499444ff3c7bd Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 09:02:15 +0100 Subject: rpi3: Do prescaler and control setup in C To initialise the arch timer configuration and some clock prescaler, we need to do two MMIO access *once*, early during boot. As tempting as it may sound, plat_reset_handler() is not the right place to do this, as it will be called on every CPU coming up, both for secondary cores as well as during warmboots. So this access will be done multiple times, and even during a rich OS' runtime. Whether doing so anyway is actually harmful is hard to say, but we should definitely avoid this if possible. Move the initialisation of these registers to C code in bl1_early_platform_setup(), where it will still be executed early enough (before enabling the console), but only once during the whole boot process. Change-Id: I081c41a5476d424411411488ff8f633e87d3bcc5 Signed-off-by: Andre Przywara --- plat/rpi/rpi3/aarch64/plat_helpers.S | 14 -------------- plat/rpi/rpi3/rpi3_bl1_setup.c | 6 ++++++ 2 files changed, 6 insertions(+), 14 deletions(-) diff --git a/plat/rpi/rpi3/aarch64/plat_helpers.S b/plat/rpi/rpi3/aarch64/plat_helpers.S index 556d87212..24278bdf6 100644 --- a/plat/rpi/rpi3/aarch64/plat_helpers.S +++ b/plat/rpi/rpi3/aarch64/plat_helpers.S @@ -18,7 +18,6 @@ .globl plat_get_my_entrypoint .globl plat_is_my_cpu_primary .globl plat_my_core_pos - .globl plat_reset_handler .globl plat_rpi3_calc_core_pos .globl plat_secondary_cold_boot_setup @@ -164,16 +163,3 @@ func plat_crash_console_flush mov_imm x0, PLAT_RPI3_UART_BASE b console_16550_core_flush endfunc plat_crash_console_flush - - /* --------------------------------------------- - * void plat_reset_handler(void); - * --------------------------------------------- - */ -func plat_reset_handler - /* use the 19.2 MHz clock for the architected timer */ - mov x0, #RPI3_INTC_BASE_ADDRESS - mov w1, #0x80000000 - str wzr, [x0, #RPI3_INTC_CONTROL_OFFSET] - str w1, [x0, #RPI3_INTC_PRESCALER_OFFSET] - ret -endfunc plat_reset_handler diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c index 31ad31c19..3ac30e0f0 100644 --- a/plat/rpi/rpi3/rpi3_bl1_setup.c +++ b/plat/rpi/rpi3/rpi3_bl1_setup.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -28,6 +29,11 @@ meminfo_t *bl1_plat_sec_mem_layout(void) ******************************************************************************/ void bl1_early_platform_setup(void) { + /* use the 19.2 MHz clock for the architected timer */ + mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_CONTROL_OFFSET, 0); + mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_PRESCALER_OFFSET, + 0x80000000); + /* Initialize the console to provide early debug support */ rpi3_console_init(); -- cgit v1.2.3 From eeb5a7b595ebe938c3cf720507c5474a8ea3153b Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Tue, 3 Sep 2019 21:08:51 +0300 Subject: SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64 AArch64 System register SCTLR_EL1[31:0] is architecturally mapped to AArch32 System register SCTLR[31:0] AArch64 System register ACTLR_EL1[31:0] is architecturally mapped to AArch32 System register ACTLR[31:0]. `u_register_t` should be used when it's important to store the contents of a register in its native size Signed-off-by: Deepika Bhavnani Change-Id: I0055422f8cc0454405e011f53c1c4ddcaceb5779 --- lib/el3_runtime/aarch64/context_mgmt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 446d9da92..a05ee5a6e 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -69,7 +69,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) uint32_t scr_el3; el3_state_t *state; gp_regs_t *gp_regs; - unsigned long sctlr_elx, actlr_elx; + u_register_t sctlr_elx, actlr_elx; assert(ctx != NULL); -- cgit v1.2.3 From ee006a79f622b39a35beaaf95d7b42b7078823f8 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Tue, 3 Sep 2019 21:51:09 +0300 Subject: Unsigned long should not be used as per coding guidelines We should either change them to `unsigned int` or `unsigned long long` when the size of the variable is the same in AArch64 and AArch32 or to `u_register_t` if it is supposed to be 32 bit wide in AArch32 and 64 bit wide in AArch64. Signed-off-by: Deepika Bhavnani Change-Id: I80e2a6edb33248ee88be395829abbd4c36c89abe --- bl1/aarch64/bl1_arch_setup.c | 4 ++-- bl1/bl1_fwu.c | 2 +- bl1/bl1_main.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index 624bd80f2..0a1cb304a 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,7 +23,7 @@ void bl1_arch_setup(void) ******************************************************************************/ void bl1_arch_next_el_setup(void) { - unsigned long next_sctlr; + u_register_t next_sctlr; /* Use the same endianness than the current BL */ next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT); diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c index d222b9c52..48f08d2ca 100644 --- a/bl1/bl1_fwu.c +++ b/bl1/bl1_fwu.c @@ -483,7 +483,7 @@ static int bl1_fwu_image_auth(unsigned int image_id, * Flush image_info to memory so that other * secure world images can see changes. */ - flush_dcache_range((unsigned long)&image_desc->image_info, + flush_dcache_range((uintptr_t)&image_desc->image_info, sizeof(image_info_t)); INFO("BL1-FWU: Authentication was successful\n"); diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index d44b46dc9..b882a07e5 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -48,7 +48,7 @@ void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, bl2_mem_layout->total_base = bl1_mem_layout->total_base; bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; - flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); + flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); } /******************************************************************************* -- cgit v1.2.3 From f389d0e90011ac4816e12f62f4fe3a179ef15cef Mon Sep 17 00:00:00 2001 From: kenny liang Date: Thu, 2 May 2019 21:06:05 +0800 Subject: mediatek: mt8173: refactor RTC and PMIC drivers Refactor RTC and PMIC drivers. Signed-off-by: kenny liang Change-Id: I74fca536cd61e00c962f080f1ba3759287682ecf --- plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c | 165 --------------------- plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h | 4 +- plat/mediatek/mt8173/drivers/rtc/rtc.c | 57 +------ plat/mediatek/mt8173/drivers/rtc/rtc.h | 6 + plat/mediatek/mt8173/platform.mk | 3 +- 5 files changed, 12 insertions(+), 223 deletions(-) delete mode 100644 plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c diff --git a/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c b/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c deleted file mode 100644 index 8120d9962..000000000 --- a/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include -#include - -/* pmic wrap module wait_idle and read polling interval (in microseconds) */ -enum { - WAIT_IDLE_POLLING_DELAY_US = 1, - READ_POLLING_DELAY_US = 2 -}; - -static inline uint32_t wait_for_state_idle(uint32_t timeout_us, - void *wacs_register, - void *wacs_vldclr_register, - uint32_t *read_reg) -{ - uint32_t reg_rdata; - uint32_t retry; - - retry = (timeout_us + WAIT_IDLE_POLLING_DELAY_US) / - WAIT_IDLE_POLLING_DELAY_US; - - do { - udelay(WAIT_IDLE_POLLING_DELAY_US); - reg_rdata = mmio_read_32((uintptr_t)wacs_register); - /* if last read command timeout,clear vldclr bit - read command state machine:FSM_REQ-->wfdle-->WFVLDCLR; - write:FSM_REQ-->idle */ - switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & - RDATA_WACS_FSM_MASK)) { - case WACS_FSM_WFVLDCLR: - mmio_write_32((uintptr_t)wacs_vldclr_register, 1); - ERROR("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n"); - break; - case WACS_FSM_WFDLE: - ERROR("WACS_FSM = WACS_FSM_WFDLE\n"); - break; - case WACS_FSM_REQ: - ERROR("WACS_FSM = WACS_FSM_REQ\n"); - break; - case WACS_FSM_IDLE: - goto done; - default: - break; - } - - retry--; - } while (retry); - -done: - if (!retry) /* timeout */ - return E_PWR_WAIT_IDLE_TIMEOUT; - - if (read_reg) - *read_reg = reg_rdata; - return 0; -} - -static inline uint32_t wait_for_state_ready(uint32_t timeout_us, - void *wacs_register, - uint32_t *read_reg) -{ - uint32_t reg_rdata; - uint32_t retry; - - retry = (timeout_us + READ_POLLING_DELAY_US) / READ_POLLING_DELAY_US; - - do { - udelay(READ_POLLING_DELAY_US); - reg_rdata = mmio_read_32((uintptr_t)wacs_register); - - if (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) - == WACS_FSM_WFVLDCLR) - break; - - retry--; - } while (retry); - - if (!retry) { /* timeout */ - ERROR("timeout when waiting for idle\n"); - return E_PWR_WAIT_IDLE_TIMEOUT_READ; - } - - if (read_reg) - *read_reg = reg_rdata; - return 0; -} - -static int32_t pwrap_wacs2(uint32_t write, - uint32_t adr, - uint32_t wdata, - uint32_t *rdata, - uint32_t init_check) -{ - uint32_t reg_rdata = 0; - uint32_t wacs_write = 0; - uint32_t wacs_adr = 0; - uint32_t wacs_cmd = 0; - uint32_t return_value = 0; - - if (init_check) { - reg_rdata = mmio_read_32((uintptr_t)&mt8173_pwrap->wacs2_rdata); - /* Prevent someone to used pwrap before pwrap init */ - if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & - RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { - ERROR("initialization isn't finished\n"); - return E_PWR_NOT_INIT_DONE; - } - } - reg_rdata = 0; - /* Check IDLE in advance */ - return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE, - &mt8173_pwrap->wacs2_rdata, - &mt8173_pwrap->wacs2_vldclr, - 0); - if (return_value != 0) { - ERROR("wait_for_fsm_idle fail,return_value=%d\n", return_value); - goto FAIL; - } - wacs_write = write << 31; - wacs_adr = (adr >> 1) << 16; - wacs_cmd = wacs_write | wacs_adr | wdata; - - mmio_write_32((uintptr_t)&mt8173_pwrap->wacs2_cmd, wacs_cmd); - if (write == 0) { - if (NULL == rdata) { - ERROR("rdata is a NULL pointer\n"); - return_value = E_PWR_INVALID_ARG; - goto FAIL; - } - return_value = wait_for_state_ready(TIMEOUT_READ, - &mt8173_pwrap->wacs2_rdata, - ®_rdata); - if (return_value != 0) { - ERROR("wait_for_fsm_vldclr fail,return_value=%d\n", - return_value); - goto FAIL; - } - *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT) - & RDATA_WACS_RDATA_MASK); - mmio_write_32((uintptr_t)&mt8173_pwrap->wacs2_vldclr, 1); - } -FAIL: - return return_value; -} - -/* external API for pmic_wrap user */ - -int32_t pwrap_read(uint32_t adr, uint32_t *rdata) -{ - return pwrap_wacs2(0, adr, 0, rdata, 1); -} - -int32_t pwrap_write(uint32_t adr, uint32_t wdata) -{ - return pwrap_wacs2(1, adr, wdata, 0, 1); -} diff --git a/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h index 0f0977137..0dffc23ee 100644 --- a/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h +++ b/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h @@ -7,11 +7,13 @@ #ifndef PMIC_WRAP_INIT_H #define PMIC_WRAP_INIT_H +#include + /* external API */ int32_t pwrap_read(uint32_t adr, uint32_t *rdata); int32_t pwrap_write(uint32_t adr, uint32_t wdata); -static struct mt8173_pmic_wrap_regs *const mt8173_pwrap = +static struct mt8173_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; /* timeout setting */ diff --git a/plat/mediatek/mt8173/drivers/rtc/rtc.c b/plat/mediatek/mt8173/drivers/rtc/rtc.c index 2b9033ed9..587886c68 100644 --- a/plat/mediatek/mt8173/drivers/rtc/rtc.c +++ b/plat/mediatek/mt8173/drivers/rtc/rtc.c @@ -5,66 +5,11 @@ */ #include - #include -#include #include -#include #include -/* RTC busy status polling interval and retry count */ -enum { - RTC_WRTGR_POLLING_DELAY_MS = 10, - RTC_WRTGR_POLLING_CNT = 100 -}; - -static uint16_t RTC_Read(uint32_t addr) -{ - uint32_t rdata = 0; - - pwrap_read((uint32_t)addr, &rdata); - return (uint16_t)rdata; -} - -static void RTC_Write(uint32_t addr, uint16_t data) -{ - pwrap_write((uint32_t)addr, (uint32_t)data); -} - -static inline int32_t rtc_busy_wait(void) -{ - uint64_t retry = RTC_WRTGR_POLLING_CNT; - - do { - mdelay(RTC_WRTGR_POLLING_DELAY_MS); - if (!(RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY)) - return 1; - retry--; - } while (retry); - - ERROR("[RTC] rtc cbusy time out!\n"); - return 0; -} - -static int32_t Write_trigger(void) -{ - RTC_Write(RTC_WRTGR, 1); - return rtc_busy_wait(); -} - -static int32_t Writeif_unlock(void) -{ - RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1); - if (!Write_trigger()) - return 0; - RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2); - if (!Write_trigger()) - return 0; - - return 1; -} - void rtc_bbpu_power_down(void) { uint16_t bbpu; @@ -73,7 +18,7 @@ void rtc_bbpu_power_down(void) bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_PWREN; if (Writeif_unlock()) { RTC_Write(RTC_BBPU, bbpu); - if (!Write_trigger()) + if (!RTC_Write_Trigger()) assert(0); } else { assert(0); diff --git a/plat/mediatek/mt8173/drivers/rtc/rtc.h b/plat/mediatek/mt8173/drivers/rtc/rtc.h index 9c4ca49a9..f60a4c18f 100644 --- a/plat/mediatek/mt8173/drivers/rtc/rtc.h +++ b/plat/mediatek/mt8173/drivers/rtc/rtc.h @@ -49,6 +49,12 @@ enum { RTC_BBPU_KEY = 0x43 << 8 }; +/* external API */ +uint16_t RTC_Read(uint32_t addr); +void RTC_Write(uint32_t addr, uint16_t data); +int32_t rtc_busy_wait(void); +int32_t RTC_Write_Trigger(void); +int32_t Writeif_unlock(void); void rtc_bbpu_power_down(void); #endif /* RTC_H */ diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk index e5eca9fcc..a66c49bb4 100644 --- a/plat/mediatek/mt8173/platform.mk +++ b/plat/mediatek/mt8173/platform.mk @@ -35,6 +35,8 @@ BL31_SOURCES += common/desc_image_load.c \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a72.S \ + ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \ + ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ ${MTK_PLAT}/common/mtk_plat_common.c \ ${MTK_PLAT}/common/mtk_sip_svc.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ @@ -42,7 +44,6 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ ${MTK_PLAT_SOC}/drivers/crypt/crypt.c \ ${MTK_PLAT_SOC}/drivers/mtcmos/mtcmos.c \ - ${MTK_PLAT_SOC}/drivers/pmic/pmic_wrap_init.c \ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ ${MTK_PLAT_SOC}/drivers/spm/spm.c \ ${MTK_PLAT_SOC}/drivers/spm/spm_hotplug.c \ -- cgit v1.2.3 From e419574e85290d121ca5c0d62e469c0457290690 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Wed, 21 Aug 2019 21:16:29 +0800 Subject: mediatek: mt8183: configure MCUSYS DCM Configure MCUSYS DCM. Signed-off-by: kenny liang Change-Id: Ib810125b514cbcc43c770377bc71a29a05a19320 --- plat/mediatek/mt8183/bl31_plat_setup.c | 52 ++- plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h | 8 +- plat/mediatek/mt8183/include/mcucfg.h | 383 +++++++++++++++++++-- 3 files changed, 396 insertions(+), 47 deletions(-) diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c index 337470abb..fcf3093b9 100644 --- a/plat/mediatek/mt8183/bl31_plat_setup.c +++ b/plat/mediatek/mt8183/bl31_plat_setup.c @@ -32,15 +32,49 @@ static void platform_setup_cpu(void) { mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001); - VERBOSE("addr of cci_adb400_dcm_config: 0x%x\n", - mmio_read_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config)); - VERBOSE("addr of sync_dcm_config: 0x%x\n", - mmio_read_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config)); - - VERBOSE("mp0_spmc: 0x%x\n", - mmio_read_32((uintptr_t)&mt8183_mcucfg->mp0_cputop_spmc_ctl)); - VERBOSE("mp1_spmc: 0x%x\n", - mmio_read_32((uintptr_t)&mt8183_mcucfg->mp1_cputop_spmc_ctl)); + /* Mcusys dcm control */ + /* Enable pll plldiv dcm */ + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, + BUS_PLLDIV_DCM); + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, + MP0_PLLDIV_DCM); + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, + MP2_PLLDIV_DCM); + /* Enable mscib dcm */ + mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, + MCSIB_CACTIVE_SEL_MASK, MCSIB_CACTIVE_SEL); + mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, + MCSIB_DCM_MASK, MCSIB_DCM); + /* Enable adb400 dcm */ + mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config, + CCI_ADB400_DCM_MASK, CCI_ADB400_DCM); + /* Enable bus clock dcm */ + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, + MCU_BUS_DCM); + /* Enable bus fabric dcm */ + mmio_clrsetbits_32( + (uintptr_t)&mt8183_mcucfg->mcusys_bus_fabric_dcm_ctrl, + MCUSYS_BUS_FABRIC_DCM_MASK, + MCUSYS_BUS_FABRIC_DCM); + /* Enable l2c sram dcm */ + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, + L2C_SRAM_DCM); + /* Enable busmp0 sync dcm */ + mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config, + SYNC_DCM_MASK, SYNC_DCM); + /* Enable cntvalue dcm */ + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, + CNTVALUEB_DCM); + /* Enable dcm cluster stall */ + mmio_clrsetbits_32( + (uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, + MCUSYS_MAX_ACCESS_LATENCY_MASK, + MCUSYS_MAX_ACCESS_LATENCY); + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, + MCU0_SYNC_DCM_STALL_WR_EN); + /* Enable rgu dcm */ + mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, + CPUSYS_RGU_DCM_CINFIG); } /******************************************************************************* diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h index 613d4714f..2228e63f2 100644 --- a/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h +++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h @@ -136,8 +136,7 @@ static const struct per_cpu_reg SPM_CLUSTER_PWR[] = { /* * MCU configuration registers */ -#define MCUCFG_MP0_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp0_axi_config) -#define MCUCFG_MP1_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp1_axi_config) + /* bit-fields of MCUCFG_MP?_AXI_CONFIG */ #define MCUCFG_AXI_CONFIG_BROADCASTINNER (1 << 0) #define MCUCFG_AXI_CONFIG_BROADCASTOUTER (1 << 1) @@ -146,11 +145,6 @@ static const struct per_cpu_reg SPM_CLUSTER_PWR[] = { #define MCUCFG_AXI_CONFIG_ACINACTM (1 << 4) #define MCUCFG_AXI_CONFIG_AINACTS (1 << 5) -/* per_cpu registers for MCUCFG_MP?_AXI_CONFIG */ -static const struct per_cpu_reg MCUCFG_SCUCTRL[] = { - [0] = { .cluster_addr = MCUCFG_MP0_AXI_CONFIG }, - [1] = { .cluster_addr = MCUCFG_MP1_AXI_CONFIG }, -}; #define MCUCFG_MP0_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[2]) #define MCUCFG_MP0_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[3]) diff --git a/plat/mediatek/mt8183/include/mcucfg.h b/plat/mediatek/mt8183/include/mcucfg.h index 83ee88fac..6b03818d0 100644 --- a/plat/mediatek/mt8183/include/mcucfg.h +++ b/plat/mediatek/mt8183/include/mcucfg.h @@ -28,51 +28,141 @@ struct mt8183_mcucfg_regs { uint32_t mp0_rw_rsvd0; /* 0x6C */ uint32_t mp0_rw_rsvd1; /* 0x70 */ uint32_t mp0_ro_rsvd; /* 0x74 */ - uint32_t reserved0_0[98]; /* 0x78 */ - uint32_t mp1_ca7l_cache_config; /* 0x200 */ - uint32_t mp1_miscdbg; /* 0x204 */ - uint32_t reserved0_1[9]; /* 0x208 */ - uint32_t mp1_axi_config; /* 0x22C */ - uint32_t mp1_misc_config[10]; /* 0x230 */ - uint32_t reserved0_2[3]; /* 0x258 */ - uint32_t mp1_ca7l_misc_config; /* 0x264 */ - uint32_t reserved0_3[310]; /* 0x268 */ + uint32_t reserved0_0; /* 0x78 */ + uint32_t mp0_l2_cache_parity1_rdata; /* 0x7C */ + uint32_t mp0_l2_cache_parity2_rdata; /* 0x80 */ + uint32_t reserved0_1; /* 0x84 */ + uint32_t mp0_rgu_dcm_config; /* 0x88 */ + uint32_t mp0_ca53_specific_ctrl; /* 0x8C */ + uint32_t mp0_esr_case; /* 0x90 */ + uint32_t mp0_esr_mask; /* 0x94 */ + uint32_t mp0_esr_trig_en; /* 0x98 */ + uint32_t reserved_0_2; /* 0x9C */ + uint32_t mp0_ses_cg_en; /* 0xA0 */ + uint32_t reserved0_3[216]; /* 0xA4 */ + uint32_t mp_dbg_ctrl; /* 0x404 */ + uint32_t reserved0_4[34]; /* 0x408 */ + uint32_t mp_dfd_ctrl; /* 0x490 */ + uint32_t dfd_cnt_l; /* 0x494 */ + uint32_t dfd_cnt_h; /* 0x498 */ + uint32_t misccfg_ro_rsvd; /* 0x49C */ + uint32_t reserved0_5[24]; /* 0x4A0 */ + uint32_t mp1_rst_status; /* 0x500 */ + uint32_t mp1_dbg_ctrl; /* 0x504 */ + uint32_t mp1_dbg_flag; /* 0x508 */ + uint32_t mp1_ca7l_ir_mon; /* 0x50C */ + uint32_t reserved0_6[32]; /* 0x510 */ + uint32_t mcusys_dbg_mon_sel_a; /* 0x590 */ + uint32_t mcucys_dbg_mon; /* 0x594 */ + uint32_t misccfg_sec_voi_status0; /* 0x598 */ + uint32_t misccfg_sec_vio_status1; /* 0x59C */ + uint32_t reserved0_7[18]; /* 0x5A0 */ + uint32_t gic500_int_mask; /* 0x5E8 */ + uint32_t core_rst_en_latch; /* 0x5EC */ + uint32_t reserved0_8[3]; /* 0x5F0 */ + uint32_t dbg_core_ret; /* 0x5FC */ + uint32_t mcusys_config_a; /* 0x600 */ + uint32_t mcusys_config1_a; /* 0x604 */ + uint32_t mcusys_gic_prebase_a; /* 0x608 */ + uint32_t mcusys_pinmux; /* 0x60C */ + uint32_t sec_range0_start; /* 0x610 */ + uint32_t sec_range0_end; /* 0x614 */ + uint32_t sec_range_enable; /* 0x618 */ + uint32_t l2c_mm_base; /* 0x61C */ + uint32_t reserved0_9[8]; /* 0x620 */ + uint32_t aclken_div; /* 0x640 */ + uint32_t pclken_div; /* 0x644 */ + uint32_t l2c_sram_ctrl; /* 0x648 */ + uint32_t armpll_jit_ctrl; /* 0x64C */ + uint32_t cci_addrmap; /* 0x650 */ + uint32_t cci_config; /* 0x654 */ + uint32_t cci_periphbase; /* 0x658 */ + uint32_t cci_nevntcntovfl; /* 0x65C */ + uint32_t cci_clk_ctrl; /* 0x660 */ + uint32_t cci_acel_s1_ctrl; /* 0x664 */ + uint32_t mcusys_bus_fabric_dcm_ctrl; /* 0x668 */ + uint32_t mcu_misc_dcm_ctrl; /* 0x66C */ + uint32_t xgpt_ctl; /* 0x670 */ + uint32_t xgpt_idx; /* 0x674 */ + uint32_t reserved0_10[3]; /* 0x678 */ + uint32_t mcusys_rw_rsvd0; /* 0x684 */ + uint32_t mcusys_rw_rsvd1; /* 0x688 */ + uint32_t reserved0_11[13]; /* 0x68C */ + uint32_t gic_500_delsel_ctl; /* 0x6C0 */ + uint32_t etb_delsel_ctl; /* 0x6C4 */ + uint32_t etb_rst_ctl; /* 0x6C8 */ + uint32_t reserved0_12[29]; /* 0x6CC */ uint32_t cci_adb400_dcm_config; /* 0x740 */ uint32_t sync_dcm_config; /* 0x744 */ - uint32_t reserved0_4[16]; /* 0x748 */ - uint32_t mp0_cputop_spmc_ctl; /* 0x788 */ - uint32_t mp1_cputop_spmc_ctl; /* 0x78C */ - uint32_t mp1_cputop_spmc_sram_ctl; /* 0x790 */ - uint32_t reserved0_5[23]; /* 0x794 */ + uint32_t reserved0_13; /* 0x748 */ + uint32_t sync_dcm_cluster_config; /* 0x74C */ + uint32_t sw_udi; /* 0x750 */ + uint32_t reserved0_14; /* 0x754 */ + uint32_t gic_sync_dcm; /* 0x758 */ + uint32_t big_dbg_pwr_ctrl; /* 0x75C */ + uint32_t gic_cpu_periphbase; /* 0x760 */ + uint32_t axi_cpu_config; /* 0x764 */ + uint32_t reserved0_15[2]; /* 0x768 */ + uint32_t mcsib_sys_ctrl1; /* 0x770 */ + uint32_t mcsib_sys_ctrl2; /* 0x774 */ + uint32_t mcsib_sys_ctrl3; /* 0x778 */ + uint32_t mcsib_sys_ctrl4; /* 0x77C */ + uint32_t mcsib_dbg_ctrl1; /* 0x780 */ + uint32_t pwrmcu_apb2to1; /* 0x784 */ + uint32_t mp0_spmc; /* 0x788 */ + uint32_t reserved0_16; /* 0x78C */ + uint32_t mp0_spmc_sram_ctl; /* 0x790 */ + uint32_t reserved0_17; /* 0x794 */ + uint32_t mp0_sw_rst_wait_cycle; /* 0x798 */ + uint32_t reserved0_18; /* 0x79C */ + uint32_t mp0_pll_divider_cfg; /* 0x7A0 */ + uint32_t reserved0_19; /* 0x7A4 */ + uint32_t mp2_pll_divider_cfg; /* 0x7A8 */ + uint32_t reserved0_20[5]; /* 0x7AC */ + uint32_t bus_pll_divider_cfg; /* 0x7C0 */ + uint32_t reserved0_21[7]; /* 0x7C4 */ + uint32_t clusterid_aff1; /* 0x7E0 */ + uint32_t clusterid_aff2; /* 0x7E4 */ + uint32_t reserved0_22[2]; /* 0x7E8 */ uint32_t l2_cfg_mp0; /* 0x7F0 */ uint32_t l2_cfg_mp1; /* 0x7F4 */ - uint32_t reserved0_6[1282]; /* 0x7F8 */ + uint32_t reserved0_23[218]; /* 0x7F8 */ + uint32_t mscib_dcm_en; /* 0xB60 */ + uint32_t reserved0_24[1063]; /* 0xB64 */ uint32_t cpusys0_sparkvretcntrl; /* 0x1C00 */ uint32_t cpusys0_sparken; /* 0x1C04 */ uint32_t cpusys0_amuxsel; /* 0x1C08 */ - uint32_t reserved0_7[9]; /* 0x1C0C */ + uint32_t reserved0_25[9]; /* 0x1C0C */ uint32_t cpusys0_cpu0_spmc_ctl; /* 0x1C30 */ uint32_t cpusys0_cpu1_spmc_ctl; /* 0x1C34 */ uint32_t cpusys0_cpu2_spmc_ctl; /* 0x1C38 */ uint32_t cpusys0_cpu3_spmc_ctl; /* 0x1C3C */ - uint32_t reserved0_8[370]; /* 0x1C40 */ + uint32_t reserved0_26[8]; /* 0x1C40 */ + uint32_t mp0_sync_dcm_cgavg_ctrl; /* 0x1C60 */ + uint32_t mp0_sync_dcm_cgavg_fact; /* 0x1C64 */ + uint32_t mp0_sync_dcm_cgavg_rfact; /* 0x1C68 */ + uint32_t mp0_sync_dcm_cgavg; /* 0x1C6C */ + uint32_t mp0_l2_parity_clr; /* 0x1C70 */ + uint32_t reserved0_27[357]; /* 0x1C74 */ uint32_t mp2_cpucfg; /* 0x2208 */ uint32_t mp2_axi_config; /* 0x220C */ - uint32_t reserved0_9[36]; /* 0x2210 */ - uint32_t mp2_cputop_spm_ctl; /* 0x22A0 */ - uint32_t mp2_cputop_spm_sta; /* 0x22A4 */ - uint32_t reserved0_10[98]; /* 0x22A8 */ - uint32_t cpusys2_cpu0_spmc_ctl; /* 0x2430 */ - uint32_t cpusys2_cpu0_spmc_sta; /* 0x2434 */ - uint32_t cpusys2_cpu1_spmc_ctl; /* 0x2438 */ - uint32_t cpusys2_cpu1_spmc_sta; /* 0x243C */ - uint32_t reserved0_11[176]; /* 0x2440 */ + uint32_t reserved0_28[25]; /* 0x2210 */ + uint32_t mp2_sync_dcm; /* 0x2274 */ + uint32_t reserved0_29[10]; /* 0x2278 */ + uint32_t ptp3_cputop_spmc0; /* 0x22A0 */ + uint32_t ptp3_cputop_spmc1; /* 0x22A4 */ + uint32_t reserved0_30[98]; /* 0x22A8 */ + uint32_t ptp3_cpu0_spmc0; /* 0x2430 */ + uint32_t ptp3_cpu0_spmc1; /* 0x2434 */ + uint32_t ptp3_cpu1_spmc0; /* 0x2438 */ + uint32_t ptp3_cpu1_spmc1; /* 0x243C */ + uint32_t ptp3_cpu2_spmc0; /* 0x2440 */ + uint32_t ptp3_cpu2_spmc1; /* 0x2444 */ + uint32_t ptp3_cpu3_spmc0; /* 0x2448 */ + uint32_t ptp3_cpu3_spmc1; /* 0x244C */ + uint32_t ptp3_cpux_spmc; /* 0x2450 */ + uint32_t reserved0_31[171]; /* 0x2454 */ uint32_t spark2ld0; /* 0x2700 */ - uint32_t reserved0_12[1355]; /* 0x2704 */ - uint32_t cpusys1_cpu0_spmc_ctl; /* 0x3C30 */ - uint32_t cpusys1_cpu1_spmc_ctl; /* 0x3C34 */ - uint32_t cpusys1_cpu2_spmc_ctl; /* 0x3C38 */ - uint32_t cpusys1_cpu3_spmc_ctl; /* 0x3C3C */ }; static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE; @@ -244,4 +334,235 @@ enum { MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT }; +/* bus pll divider dcm related */ +enum { + BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT = 11, + BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24, + BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25, + + BUS_PLLDIV_DCM = (1 << BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT) | + (1 << BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT) | + (1 << BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT) +}; + +/* mp0 pll divider dcm related */ +enum { + MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11, + MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24, + MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25, + MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31, + MP0_PLLDIV_DCM = (1 << MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT) | + (1 << MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT) | + (1 << MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT) | + (1u << MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT) +}; + +/* mp2 pll divider dcm related */ +enum { + MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11, + MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24, + MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25, + MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31, + MP2_PLLDIV_DCM = (1 << MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT) | + (1 << MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT) | + (1 << MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT) | + (1u << MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT) +}; + +/* mcsib dcm related */ +enum { + MCSIB_CACTIVE_SEL_SHIFT = 0, + MCSIB_DCM_EN_SHIFT = 16, + + MCSIB_CACTIVE_SEL_MASK = 0xffff << MCSIB_CACTIVE_SEL_SHIFT, + MCSIB_CACTIVE_SEL = 0xffff << MCSIB_CACTIVE_SEL_SHIFT, + + MCSIB_DCM_MASK = 0xffffu << MCSIB_DCM_EN_SHIFT, + MCSIB_DCM = 0xffffu << MCSIB_DCM_EN_SHIFT, +}; + +/* cci adb400 dcm related */ +enum { + CCI_M0_ADB400_DCM_EN_SHIFT = 0, + CCI_M1_ADB400_DCM_EN_SHIFT = 1, + CCI_M2_ADB400_DCM_EN_SHIFT = 2, + CCI_S2_ADB400_DCM_EN_SHIFT = 3, + CCI_S3_ADB400_DCM_EN_SHIFT = 4, + CCI_S4_ADB400_DCM_EN_SHIFT = 5, + CCI_S5_ADB400_DCM_EN_SHIFT = 6, + ACP_S3_ADB400_DCM_EN_SHIFT = 11, + + CCI_ADB400_DCM_MASK = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M1_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M2_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S2_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S5_ADB400_DCM_EN_SHIFT) | + (1 << ACP_S3_ADB400_DCM_EN_SHIFT), + CCI_ADB400_DCM = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M1_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M2_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S2_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S5_ADB400_DCM_EN_SHIFT) | + (1 << ACP_S3_ADB400_DCM_EN_SHIFT) +}; + +/* sync dcm related */ +enum { + CCI_SYNC_DCM_DIV_EN_SHIFT = 0, + CCI_SYNC_DCM_UPDATE_TOG_SHIFT = 1, + CCI_SYNC_DCM_DIV_SEL_SHIFT = 2, + MP0_SYNC_DCM_DIV_EN_SHIFT = 10, + MP0_SYNC_DCM_UPDATE_TOG_SHIFT = 11, + MP0_SYNC_DCM_DIV_SEL_SHIFT = 12, + + SYNC_DCM_MASK = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) | + (1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0x7f << CCI_SYNC_DCM_DIV_SEL_SHIFT) | + (1 << MP0_SYNC_DCM_DIV_EN_SHIFT) | + (1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0x7f << MP0_SYNC_DCM_DIV_SEL_SHIFT), + SYNC_DCM = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) | + (1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0 << CCI_SYNC_DCM_DIV_SEL_SHIFT) | + (1 << MP0_SYNC_DCM_DIV_EN_SHIFT) | + (1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0 << MP0_SYNC_DCM_DIV_SEL_SHIFT) +}; + +/* mcu bus dcm related */ +enum { + MCU_BUS_DCM_EN_SHIFT = 8, + MCU_BUS_DCM = 1 << MCU_BUS_DCM_EN_SHIFT +}; + +/* mcusys bus fabric dcm related */ +enum { + ACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 0, + EMI2_ADB400_S_DCM_CTRL_SHIFT = 1, + ACLK_GPU_DYNAMIC_CG_EN_SHIFT = 2, + ACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 3, + MP0_ADB400_S_DCM_CTRL_SHIFT = 4, + MP0_ADB400_M_DCM_CTRL_SHIFT = 5, + MP1_ADB400_S_DCM_CTRL_SHIFT = 6, + MP1_ADB400_M_DCM_CTRL_SHIFT = 7, + EMICLK_EMI_DYNAMIC_CG_EN_SHIFT = 8, + INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 9, + EMICLK_GPU_DYNAMIC_CG_EN_SHIFT = 10, + INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 11, + EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT = 12, + EMI1_ADB400_S_DCM_CTRL_SHIFT = 16, + MP2_ADB400_M_DCM_CTRL_SHIFT = 17, + MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT = 18, + MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT = 19, + MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT = 20, + L2_SHARE_ADB400_DCM_CTRL_SHIFT = 21, + MP1_AGGRESS_DCM_CTRL_SHIFT = 22, + MP0_AGGRESS_DCM_CTRL_SHIFT = 23, + MP0_ADB400_ACP_S_DCM_CTRL_SHIFT = 24, + MP0_ADB400_ACP_M_DCM_CTRL_SHIFT = 25, + MP1_ADB400_ACP_S_DCM_CTRL_SHIFT = 26, + MP1_ADB400_ACP_M_DCM_CTRL_SHIFT = 27, + MP3_ADB400_M_DCM_CTRL_SHIFT = 28, + MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT = 29, + + MCUSYS_BUS_FABRIC_DCM_MASK = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) | + (1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (1 << MP0_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_M_DCM_CTRL_SHIFT) | + (1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP2_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) | + (1 << MP1_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP3_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT), + + MCUSYS_BUS_FABRIC_DCM = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) | + (1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (0 << MP0_ADB400_S_DCM_CTRL_SHIFT) | + (0 << MP0_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_M_DCM_CTRL_SHIFT) | + (1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) | + (0 << MP2_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) | + (1 << MP1_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP3_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT) +}; + +/* l2c_sram dcm related */ +enum { + L2C_SRAM_DCM_EN_SHIFT = 0, + L2C_SRAM_DCM = 1 << L2C_SRAM_DCM_EN_SHIFT +}; + +/* mcu misc dcm related */ +enum { + MP0_CNTVALUEB_DCM_EN_SHIFT = 0, + MP_CNTVALUEB_DCM_EN = 8, + + CNTVALUEB_DCM = (1 << MP0_CNTVALUEB_DCM_EN_SHIFT) | + (1 << MP_CNTVALUEB_DCM_EN) +}; + +/* sync dcm cluster config related */ +enum { + MP0_SYNC_DCM_STALL_WR_EN_SHIFT = 7, + MCUSYS_MAX_ACCESS_LATENCY_SHIFT = 24, + + MCU0_SYNC_DCM_STALL_WR_EN = 1 << MP0_SYNC_DCM_STALL_WR_EN_SHIFT, + + MCUSYS_MAX_ACCESS_LATENCY_MASK = 0xf << MCUSYS_MAX_ACCESS_LATENCY_SHIFT, + MCUSYS_MAX_ACCESS_LATENCY = 0x5 << MCUSYS_MAX_ACCESS_LATENCY_SHIFT +}; + +/* cpusys rgu dcm related */ +enum { + CPUSYS_RGU_DCM_CONFIG_SHIFT = 0, + + CPUSYS_RGU_DCM_CINFIG = 1 << CPUSYS_RGU_DCM_CONFIG_SHIFT +}; + +/* mp2 sync dcm related */ +enum { + MP2_DCM_EN_SHIFT = 0, + + MP2_DCM_EN = 1 << MP2_DCM_EN_SHIFT +}; #endif /* MT8183_MCUCFG_H */ -- cgit v1.2.3 From f9f84f44fba3155f6d0559a9d29fd9404f774398 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Tue, 20 Aug 2019 22:27:44 +0800 Subject: mediatek: mt8183: add MTK uart driver for controlling clock gate Add uart clock gate contol for suspend/resume scenario. Signed-off-by: kenny liang Change-Id: Id4197b0720630ec6c74aec206a9b206511bf515a --- plat/mediatek/mt8183/drivers/uart/uart.c | 111 ++++++++++++++++++++++++++++ plat/mediatek/mt8183/drivers/uart/uart.h | 100 +++++++++++++++++++++++++ plat/mediatek/mt8183/include/platform_def.h | 1 + plat/mediatek/mt8183/platform.mk | 2 + 4 files changed, 214 insertions(+) create mode 100644 plat/mediatek/mt8183/drivers/uart/uart.c create mode 100644 plat/mediatek/mt8183/drivers/uart/uart.h diff --git a/plat/mediatek/mt8183/drivers/uart/uart.c b/plat/mediatek/mt8183/drivers/uart/uart.c new file mode 100644 index 000000000..3c6a98036 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/uart/uart.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +static struct mt_uart uart_save_addr[DRV_SUPPORT_UART_PORTS]; + +static const unsigned int uart_base_addr[DRV_SUPPORT_UART_PORTS] = { + UART0_BASE, + UART1_BASE +}; + +void mt_uart_restore(void) +{ + int uart_idx = UART_PORT0; + struct mt_uart *uart; + unsigned long base; + + /* Must NOT print any debug log before UART restore */ + for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS; + uart_idx++) { + + uart = &uart_save_addr[uart_idx]; + base = uart->base; + + mmio_write_32(UART_LCR(base), UART_LCR_MODE_B); + mmio_write_32(UART_EFR(base), uart->registers.efr); + mmio_write_32(UART_LCR(base), uart->registers.lcr); + mmio_write_32(UART_FCR(base), uart->registers.fcr); + + /* baudrate */ + mmio_write_32(UART_HIGHSPEED(base), uart->registers.highspeed); + mmio_write_32(UART_FRACDIV_L(base), uart->registers.fracdiv_l); + mmio_write_32(UART_FRACDIV_M(base), uart->registers.fracdiv_m); + mmio_write_32(UART_LCR(base), + uart->registers.lcr | UART_LCR_DLAB); + mmio_write_32(UART_DLL(base), uart->registers.dll); + mmio_write_32(UART_DLH(base), uart->registers.dlh); + mmio_write_32(UART_LCR(base), uart->registers.lcr); + mmio_write_32(UART_SAMPLE_COUNT(base), + uart->registers.sample_count); + mmio_write_32(UART_SAMPLE_POINT(base), + uart->registers.sample_point); + mmio_write_32(UART_GUARD(base), uart->registers.guard); + + /* flow control */ + mmio_write_32(UART_ESCAPE_EN(base), uart->registers.escape_en); + mmio_write_32(UART_MCR(base), uart->registers.mcr); + mmio_write_32(UART_IER(base), uart->registers.ier); + mmio_write_32(UART_SCR(base), uart->registers.scr); + } +} + +void mt_uart_save(void) +{ + int uart_idx = UART_PORT0; + struct mt_uart *uart; + unsigned long base; + + for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS; + uart_idx++) { + + uart_save_addr[uart_idx].base = uart_base_addr[uart_idx]; + base = uart_base_addr[uart_idx]; + uart = &uart_save_addr[uart_idx]; + uart->registers.lcr = mmio_read_32(UART_LCR(base)); + + mmio_write_32(UART_LCR(base), UART_LCR_MODE_B); + uart->registers.efr = mmio_read_32(UART_EFR(base)); + mmio_write_32(UART_LCR(base), uart->registers.lcr); + uart->registers.fcr = mmio_read_32(UART_FCR_RD(base)); + + /* baudrate */ + uart->registers.highspeed = mmio_read_32(UART_HIGHSPEED(base)); + uart->registers.fracdiv_l = mmio_read_32(UART_FRACDIV_L(base)); + uart->registers.fracdiv_m = mmio_read_32(UART_FRACDIV_M(base)); + mmio_write_32(UART_LCR(base), + uart->registers.lcr | UART_LCR_DLAB); + uart->registers.dll = mmio_read_32(UART_DLL(base)); + uart->registers.dlh = mmio_read_32(UART_DLH(base)); + mmio_write_32(UART_LCR(base), uart->registers.lcr); + uart->registers.sample_count = mmio_read_32( + UART_SAMPLE_COUNT(base)); + uart->registers.sample_point = mmio_read_32( + UART_SAMPLE_POINT(base)); + uart->registers.guard = mmio_read_32(UART_GUARD(base)); + + /* flow control */ + uart->registers.escape_en = mmio_read_32(UART_ESCAPE_EN(base)); + uart->registers.mcr = mmio_read_32(UART_MCR(base)); + uart->registers.ier = mmio_read_32(UART_IER(base)); + uart->registers.scr = mmio_read_32(UART_SCR(base)); + } +} + +void mt_console_uart_cg(int on) +{ + if (on) + mmio_write_32(UART_CLOCK_GATE_CLR, UART0_CLOCK_GATE_BIT); + else + mmio_write_32(UART_CLOCK_GATE_SET, UART0_CLOCK_GATE_BIT); +} + +int mt_console_uart_cg_status(void) +{ + return mmio_read_32(UART_CLOCK_GATE_STA) & UART0_CLOCK_GATE_BIT; +} diff --git a/plat/mediatek/mt8183/drivers/uart/uart.h b/plat/mediatek/mt8183/drivers/uart/uart.h new file mode 100644 index 000000000..be04c3509 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/uart/uart.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __UART_H__ +#define __UART_H__ + +#include + +/* UART HW information */ +#define HW_SUPPORT_UART_PORTS 2 +#define DRV_SUPPORT_UART_PORTS 2 + +/* console UART clock cg */ +#define UART_CLOCK_GATE_SET (INFRACFG_AO_BASE + 0x80) +#define UART_CLOCK_GATE_CLR (INFRACFG_AO_BASE + 0x84) +#define UART_CLOCK_GATE_STA (INFRACFG_AO_BASE + 0x90) +#define UART0_CLOCK_GATE_BIT (1U<<22) +#define UART1_CLOCK_GATE_BIT (1U<<23) + +/* UART registers */ +#define UART_RBR(_baseaddr) (_baseaddr + 0x0) +#define UART_THR(_baseaddr) (_baseaddr + 0x0) +#define UART_IER(_baseaddr) (_baseaddr + 0x4) +#define UART_IIR(_baseaddr) (_baseaddr + 0x8) +#define UART_FCR(_baseaddr) (_baseaddr + 0x8) +#define UART_LCR(_baseaddr) (_baseaddr + 0xc) +#define UART_MCR(_baseaddr) (_baseaddr + 0x10) +#define UART_LSR(_baseaddr) (_baseaddr + 0x14) +#define UART_MSR(_baseaddr) (_baseaddr + 0x18) +#define UART_SCR(_baseaddr) (_baseaddr + 0x1c) +#define UART_DLL(_baseaddr) (_baseaddr + 0x0) +#define UART_DLH(_baseaddr) (_baseaddr + 0x4) +#define UART_EFR(_baseaddr) (_baseaddr + 0x8) +#define UART_XON1(_baseaddr) (_baseaddr + 0x10) +#define UART_XON2(_baseaddr) (_baseaddr + 0x14) +#define UART_XOFF1(_baseaddr) (_baseaddr + 0x18) +#define UART_XOFF2(_baseaddr) (_baseaddr + 0x1c) +#define UART_AUTOBAUD(_baseaddr) (_baseaddr + 0x20) +#define UART_HIGHSPEED(_baseaddr) (_baseaddr + 0x24) +#define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr + 0x28) +#define UART_SAMPLE_POINT(_baseaddr) (_baseaddr + 0x2c) +#define UART_AUTOBAUD_REG(_baseaddr) (_baseaddr + 0x30) +#define UART_RATE_FIX_REG(_baseaddr) (_baseaddr + 0x34) +#define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr + 0x38) +#define UART_GUARD(_baseaddr) (_baseaddr + 0x3c) +#define UART_ESCAPE_DAT(_baseaddr) (_baseaddr + 0x40) +#define UART_ESCAPE_EN(_baseaddr) (_baseaddr + 0x44) +#define UART_SLEEP_EN(_baseaddr) (_baseaddr + 0x48) +#define UART_DMA_EN(_baseaddr) (_baseaddr + 0x4c) +#define UART_RXTRI_AD(_baseaddr) (_baseaddr + 0x50) +#define UART_FRACDIV_L(_baseaddr) (_baseaddr + 0x54) +#define UART_FRACDIV_M(_baseaddr) (_baseaddr + 0x58) +#define UART_FCR_RD(_baseaddr) (_baseaddr + 0x5C) +#define UART_USB_RX_SEL(_baseaddr) (_baseaddr + 0xB0) +#define UART_SLEEP_REQ(_baseaddr) (_baseaddr + 0xB4) +#define UART_SLEEP_ACK(_baseaddr) (_baseaddr + 0xB8) +#define UART_SPM_SEL(_baseaddr) (_baseaddr + 0xBC) +#define UART_LCR_DLAB 0x0080 +#define UART_LCR_MODE_B 0x00bf + +enum uart_port_ID { + UART_PORT0 = 0, + UART_PORT1 +}; + +struct mt_uart_register { + unsigned int dll; + unsigned int dlh; + unsigned int ier; + unsigned int lcr; + unsigned int mcr; + unsigned int fcr; + unsigned int lsr; + unsigned int scr; + unsigned int efr; + unsigned int highspeed; + unsigned int sample_count; + unsigned int sample_point; + unsigned int fracdiv_l; + unsigned int fracdiv_m; + unsigned int escape_en; + unsigned int guard; + unsigned int rx_sel; +}; + +struct mt_uart { + unsigned long base; + struct mt_uart_register registers; +}; + +/* external API */ +void mt_uart_save(void); +void mt_uart_restore(void); +void mt_console_uart_cg(int on); +int mt_console_uart_cg_status(void); + +#endif /* __UART_H__ */ diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h index f802ac2f5..dab265b47 100644 --- a/plat/mediatek/mt8183/include/platform_def.h +++ b/plat/mediatek/mt8183/include/platform_def.h @@ -87,6 +87,7 @@ * UART related constants ******************************************************************************/ #define UART0_BASE (IO_PHYS + 0x01002000) +#define UART1_BASE (IO_PHYS + 0x01003000) #define UART_BAUDRATE 115200 #define UART_CLOCK 26000000 diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index 09fd13319..3053a87f5 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -13,6 +13,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \ -I${MTK_PLAT_SOC}/drivers/rtc/ \ + -I${MTK_PLAT_SOC}/drivers/uart/ \ -I${MTK_PLAT_SOC}/include/ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \ @@ -47,6 +48,7 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ + ${MTK_PLAT_SOC}/drivers/uart/uart.c \ ${MTK_PLAT_SOC}/plat_pm.c \ ${MTK_PLAT_SOC}/plat_topology.c \ ${MTK_PLAT_SOC}/plat_mt_gic.c \ -- cgit v1.2.3 From 3c25ba440750d4b58599aca907a479627ef62551 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Wed, 21 Aug 2019 20:50:20 +0800 Subject: mediatek: mt8183: add MTK SPM driver Add MTK SPM driver for suspend/resume scenario. Signed-off-by: kenny liang Change-Id: I8207eea95914da9e63c62f3afc8329f3ccd9a22c --- plat/mediatek/mt8183/bl31_plat_setup.c | 2 + plat/mediatek/mt8183/drivers/pmic/pmic.c | 18 + plat/mediatek/mt8183/drivers/pmic/pmic.h | 8 +- plat/mediatek/mt8183/drivers/spm/spm.c | 328 +++ plat/mediatek/mt8183/drivers/spm/spm.h | 2552 ++++++++++++++++++++++ plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c | 170 ++ plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h | 50 + plat/mediatek/mt8183/drivers/spm/spm_suspend.c | 255 +++ plat/mediatek/mt8183/drivers/spm/spm_suspend.h | 13 + plat/mediatek/mt8183/include/plat_debug.h | 2 - plat/mediatek/mt8183/include/platform_def.h | 2 + plat/mediatek/mt8183/include/spm.h | 1715 --------------- plat/mediatek/mt8183/plat_debug.c | 1 + plat/mediatek/mt8183/plat_pm.c | 56 +- plat/mediatek/mt8183/platform.mk | 4 + 15 files changed, 3455 insertions(+), 1721 deletions(-) create mode 100644 plat/mediatek/mt8183/drivers/spm/spm.c create mode 100644 plat/mediatek/mt8183/drivers/spm/spm.h create mode 100644 plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c create mode 100644 plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h create mode 100644 plat/mediatek/mt8183/drivers/spm/spm_suspend.c create mode 100644 plat/mediatek/mt8183/drivers/spm/spm_suspend.h delete mode 100644 plat/mediatek/mt8183/include/spm.h diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c index fcf3093b9..fd3a5b0b7 100644 --- a/plat/mediatek/mt8183/bl31_plat_setup.c +++ b/plat/mediatek/mt8183/bl31_plat_setup.c @@ -23,6 +23,7 @@ #include #include #include +#include #include static entry_point_info_t bl32_ep_info; @@ -146,6 +147,7 @@ void bl31_platform_setup(void) #if SPMC_MODE == 1 spmc_init(); #endif + spm_boot_init(); } /******************************************************************************* diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic.c b/plat/mediatek/mt8183/drivers/pmic/pmic.c index 818c1493a..b0f898e21 100644 --- a/plat/mediatek/mt8183/drivers/pmic/pmic.c +++ b/plat/mediatek/mt8183/drivers/pmic/pmic.c @@ -7,6 +7,24 @@ #include #include +void bcpu_enable(uint32_t en) +{ + pwrap_write(PMIC_VPROC11_OP_EN, 0x1); + if (en) + pwrap_write(PMIC_VPROC11_CON0, 1); + else + pwrap_write(PMIC_VPROC11_CON0, 0); +} + +void bcpu_sram_enable(uint32_t en) +{ + pwrap_write(PMIC_VSRAM_PROC11_OP_EN, 0x1); + if (en) + pwrap_write(PMIC_VSRAM_PROC11_CON0, 1); + else + pwrap_write(PMIC_VSRAM_PROC11_CON0, 0); +} + void wk_pmic_enable_sdn_delay(void) { uint32_t con; diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic.h b/plat/mediatek/mt8183/drivers/pmic/pmic.h index d62c6daf1..f19f9f6e4 100644 --- a/plat/mediatek/mt8183/drivers/pmic/pmic.h +++ b/plat/mediatek/mt8183/drivers/pmic/pmic.h @@ -10,7 +10,11 @@ enum { PMIC_TMA_KEY = 0x03a8, PMIC_PWRHOLD = 0x0a08, - PMIC_PSEQ_ELR11 = 0x0a62 + PMIC_PSEQ_ELR11 = 0x0a62, + PMIC_VPROC11_CON0 = 0x1388, + PMIC_VPROC11_OP_EN = 0x1390, + PMIC_VSRAM_PROC11_CON0 = 0x1b46, + PMIC_VSRAM_PROC11_OP_EN = 0x1b4e }; enum { @@ -18,6 +22,8 @@ enum { }; /* external API */ +void bcpu_enable(uint32_t en); +void bcpu_sram_enable(uint32_t en); void wk_pmic_enable_sdn_delay(void); void pmic_power_off(void); diff --git a/plat/mediatek/mt8183/drivers/spm/spm.c b/plat/mediatek/mt8183/drivers/spm/spm.c new file mode 100644 index 000000000..dcafd55fd --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm.c @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include +#include +#include +#include + +DEFINE_BAKERY_LOCK(spm_lock); + +const char *wakeup_src_str[32] = { + [0] = "R12_PCM_TIMER", + [1] = "R12_SSPM_WDT_EVENT_B", + [2] = "R12_KP_IRQ_B", + [3] = "R12_APWDT_EVENT_B", + [4] = "R12_APXGPT1_EVENT_B", + [5] = "R12_CONN2AP_SPM_WAKEUP_B", + [6] = "R12_EINT_EVENT_B", + [7] = "R12_CONN_WDT_IRQ_B", + [8] = "R12_CCIF0_EVENT_B", + [9] = "R12_LOWBATTERY_IRQ_B", + [10] = "R12_SSPM_SPM_IRQ_B", + [11] = "R12_SCP_SPM_IRQ_B", + [12] = "R12_SCP_WDT_EVENT_B", + [13] = "R12_PCM_WDT_WAKEUP_B", + [14] = "R12_USB_CDSC_B ", + [15] = "R12_USB_POWERDWN_B", + [16] = "R12_SYS_TIMER_EVENT_B", + [17] = "R12_EINT_EVENT_SECURE_B", + [18] = "R12_CCIF1_EVENT_B", + [19] = "R12_UART0_IRQ_B", + [20] = "R12_AFE_IRQ_MCU_B", + [21] = "R12_THERM_CTRL_EVENT_B", + [22] = "R12_SYS_CIRQ_IRQ_B", + [23] = "R12_MD2AP_PEER_EVENT_B", + [24] = "R12_CSYSPWREQ_B", + [25] = "R12_MD1_WDT_B ", + [26] = "R12_CLDMA_EVENT_B", + [27] = "R12_SEJ_WDT_GPT_B", + [28] = "R12_ALL_SSPM_WAKEUP_B", + [29] = "R12_CPU_IRQ_B", + [30] = "R12_CPU_WFI_AND_B" +}; + +const char *spm_get_firmware_version(void) +{ + return "DYNAMIC_SPM_FW_VERSION"; +} + +void spm_lock_init(void) +{ + bakery_lock_init(&spm_lock); +} + +void spm_lock_get(void) +{ + bakery_lock_get(&spm_lock); +} + +void spm_lock_release(void) +{ + bakery_lock_release(&spm_lock); +} + +void spm_set_bootaddr(unsigned long bootaddr) +{ + /* initialize core4~7 boot entry address */ + mmio_write_32(SW2SPM_MAILBOX_3, bootaddr); +} + +void spm_set_cpu_status(int cpu) +{ + if (cpu >= 0 && cpu < 4) { + mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006204); + mmio_write_32(ROOT_CORE_ADDR, 0x10006208 + (cpu * 0x4)); + } else if (cpu >= 4 && cpu < 8) { + mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006218); + mmio_write_32(ROOT_CORE_ADDR, 0x1000621c + ((cpu - 4) * 0x4)); + } else { + ERROR("%s: error cpu number %d\n", __func__, cpu); + } +} + +void spm_set_power_control(const struct pwr_ctrl *pwrctrl) +{ + mmio_write_32(SPM_AP_STANDBY_CON, + ((pwrctrl->wfi_op & 0x1) << 0) | + ((pwrctrl->mp0_cputop_idle_mask & 0x1) << 1) | + ((pwrctrl->mp1_cputop_idle_mask & 0x1) << 2) | + ((pwrctrl->mcusys_idle_mask & 0x1) << 4) | + ((pwrctrl->mm_mask_b & 0x3) << 16) | + ((pwrctrl->md_ddr_en_0_dbc_en & 0x1) << 18) | + ((pwrctrl->md_ddr_en_1_dbc_en & 0x1) << 19) | + ((pwrctrl->md_mask_b & 0x3) << 20) | + ((pwrctrl->sspm_mask_b & 0x1) << 22) | + ((pwrctrl->scp_mask_b & 0x1) << 23) | + ((pwrctrl->srcclkeni_mask_b & 0x1) << 24) | + ((pwrctrl->md_apsrc_1_sel & 0x1) << 25) | + ((pwrctrl->md_apsrc_0_sel & 0x1) << 26) | + ((pwrctrl->conn_ddr_en_dbc_en & 0x1) << 27) | + ((pwrctrl->conn_mask_b & 0x1) << 28) | + ((pwrctrl->conn_apsrc_sel & 0x1) << 29)); + + mmio_write_32(SPM_SRC_REQ, + ((pwrctrl->spm_apsrc_req & 0x1) << 0) | + ((pwrctrl->spm_f26m_req & 0x1) << 1) | + ((pwrctrl->spm_infra_req & 0x1) << 3) | + ((pwrctrl->spm_vrf18_req & 0x1) << 4) | + ((pwrctrl->spm_ddren_req & 0x1) << 7) | + ((pwrctrl->spm_rsv_src_req & 0x7) << 8) | + ((pwrctrl->spm_ddren_2_req & 0x1) << 11) | + ((pwrctrl->cpu_md_dvfs_sop_force_on & 0x1) << 16)); + + mmio_write_32(SPM_SRC_MASK, + ((pwrctrl->csyspwreq_mask & 0x1) << 0) | + ((pwrctrl->ccif0_md_event_mask_b & 0x1) << 1) | + ((pwrctrl->ccif0_ap_event_mask_b & 0x1) << 2) | + ((pwrctrl->ccif1_md_event_mask_b & 0x1) << 3) | + ((pwrctrl->ccif1_ap_event_mask_b & 0x1) << 4) | + ((pwrctrl->ccif2_md_event_mask_b & 0x1) << 5) | + ((pwrctrl->ccif2_ap_event_mask_b & 0x1) << 6) | + ((pwrctrl->ccif3_md_event_mask_b & 0x1) << 7) | + ((pwrctrl->ccif3_ap_event_mask_b & 0x1) << 8) | + ((pwrctrl->md_srcclkena_0_infra_mask_b & 0x1) << 9) | + ((pwrctrl->md_srcclkena_1_infra_mask_b & 0x1) << 10) | + ((pwrctrl->conn_srcclkena_infra_mask_b & 0x1) << 11) | + ((pwrctrl->ufs_infra_req_mask_b & 0x1) << 12) | + ((pwrctrl->srcclkeni_infra_mask_b & 0x1) << 13) | + ((pwrctrl->md_apsrc_req_0_infra_mask_b & 0x1) << 14) | + ((pwrctrl->md_apsrc_req_1_infra_mask_b & 0x1) << 15) | + ((pwrctrl->conn_apsrcreq_infra_mask_b & 0x1) << 16) | + ((pwrctrl->ufs_srcclkena_mask_b & 0x1) << 17) | + ((pwrctrl->md_vrf18_req_0_mask_b & 0x1) << 18) | + ((pwrctrl->md_vrf18_req_1_mask_b & 0x1) << 19) | + ((pwrctrl->ufs_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->gce_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->conn_infra_req_mask_b & 0x1) << 22) | + ((pwrctrl->gce_apsrc_req_mask_b & 0x1) << 23) | + ((pwrctrl->disp0_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->disp1_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->mfg_req_mask_b & 0x1) << 26) | + ((pwrctrl->vdec_req_mask_b & 0x1) << 27)); + + mmio_write_32(SPM_SRC2_MASK, + ((pwrctrl->md_ddr_en_0_mask_b & 0x1) << 0) | + ((pwrctrl->md_ddr_en_1_mask_b & 0x1) << 1) | + ((pwrctrl->conn_ddr_en_mask_b & 0x1) << 2) | + ((pwrctrl->ddren_sspm_apsrc_req_mask_b & 0x1) << 3) | + ((pwrctrl->ddren_scp_apsrc_req_mask_b & 0x1) << 4) | + ((pwrctrl->disp0_ddren_mask_b & 0x1) << 5) | + ((pwrctrl->disp1_ddren_mask_b & 0x1) << 6) | + ((pwrctrl->gce_ddren_mask_b & 0x1) << 7) | + ((pwrctrl->ddren_emi_self_refresh_ch0_mask_b & 0x1) + << 8) | + ((pwrctrl->ddren_emi_self_refresh_ch1_mask_b & 0x1) + << 9)); + + mmio_write_32(SPM_WAKEUP_EVENT_MASK, + ((pwrctrl->spm_wakeup_event_mask & 0xffffffff) << 0)); + + mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK, + ((pwrctrl->spm_wakeup_event_ext_mask & 0xffffffff) + << 0)); + + mmio_write_32(SPM_SRC3_MASK, + ((pwrctrl->md_ddr_en_2_0_mask_b & 0x1) << 0) | + ((pwrctrl->md_ddr_en_2_1_mask_b & 0x1) << 1) | + ((pwrctrl->conn_ddr_en_2_mask_b & 0x1) << 2) | + ((pwrctrl->ddren2_sspm_apsrc_req_mask_b & 0x1) << 3) | + ((pwrctrl->ddren2_scp_apsrc_req_mask_b & 0x1) << 4) | + ((pwrctrl->disp0_ddren2_mask_b & 0x1) << 5) | + ((pwrctrl->disp1_ddren2_mask_b & 0x1) << 6) | + ((pwrctrl->gce_ddren2_mask_b & 0x1) << 7) | + ((pwrctrl->ddren2_emi_self_refresh_ch0_mask_b & 0x1) + << 8) | + ((pwrctrl->ddren2_emi_self_refresh_ch1_mask_b & 0x1) + << 9)); + + mmio_write_32(MP0_CPU0_WFI_EN, + ((pwrctrl->mp0_cpu0_wfi_en & 0x1) << 0)); + mmio_write_32(MP0_CPU1_WFI_EN, + ((pwrctrl->mp0_cpu1_wfi_en & 0x1) << 0)); + mmio_write_32(MP0_CPU2_WFI_EN, + ((pwrctrl->mp0_cpu2_wfi_en & 0x1) << 0)); + mmio_write_32(MP0_CPU3_WFI_EN, + ((pwrctrl->mp0_cpu3_wfi_en & 0x1) << 0)); + + mmio_write_32(MP1_CPU0_WFI_EN, + ((pwrctrl->mp1_cpu0_wfi_en & 0x1) << 0)); + mmio_write_32(MP1_CPU1_WFI_EN, + ((pwrctrl->mp1_cpu1_wfi_en & 0x1) << 0)); + mmio_write_32(MP1_CPU2_WFI_EN, + ((pwrctrl->mp1_cpu2_wfi_en & 0x1) << 0)); + mmio_write_32(MP1_CPU3_WFI_EN, + ((pwrctrl->mp1_cpu3_wfi_en & 0x1) << 0)); +} + +void spm_disable_pcm_timer(void) +{ + mmio_clrsetbits_32(PCM_CON1, PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); +} + +void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) +{ + uint32_t val, mask, isr; + + val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; + mmio_write_32(PCM_TIMER_VAL, val); + mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_TIMER_EN_LSB); + + mask = pwrctrl->wake_src; + + if (pwrctrl->csyspwreq_mask) + mask &= ~WAKE_SRC_R12_CSYSPWREQ_B; + + mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask); + + isr = mmio_read_32(SPM_IRQ_MASK) & SPM_TWAM_IRQ_MASK_LSB; + mmio_write_32(SPM_IRQ_MASK, isr | ISRM_RET_IRQ_AUX); +} + +void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) +{ + mmio_write_32(SPM_SW_FLAG, pwrctrl->pcm_flags); + mmio_write_32(SPM_SW_RSV_2, pwrctrl->pcm_flags1); +} + +void spm_set_pcm_wdt(int en) +{ + if (en) { + mmio_clrsetbits_32(PCM_CON1, PCM_WDT_WAKE_MODE_LSB, + SPM_REGWR_CFG_KEY); + + if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) + mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); + mmio_write_32(PCM_WDT_VAL, + mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); + mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_WDT_EN_LSB); + } else { + mmio_clrsetbits_32(PCM_CON1, PCM_WDT_EN_LSB, + SPM_REGWR_CFG_KEY); + } +} + +void spm_send_cpu_wakeup_event(void) +{ + mmio_write_32(PCM_REG_DATA_INI, 0); + mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1); +} + +void spm_get_wakeup_status(struct wake_status *wakesta) +{ + wakesta->assert_pc = mmio_read_32(PCM_REG_DATA_INI); + wakesta->r12 = mmio_read_32(SPM_SW_RSV_0); + wakesta->r12_ext = mmio_read_32(PCM_REG12_EXT_DATA); + wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); + wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); + wakesta->wake_misc = mmio_read_32(SPM_BSI_D0_SR); + wakesta->timer_out = mmio_read_32(SPM_BSI_D1_SR); + wakesta->r13 = mmio_read_32(PCM_REG13_DATA); + wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA); + wakesta->req_sta = mmio_read_32(SRC_REQ_STA); + wakesta->sw_flag = mmio_read_32(SPM_SW_FLAG); + wakesta->sw_flag1 = mmio_read_32(SPM_SW_RSV_2); + wakesta->r15 = mmio_read_32(PCM_REG15_DATA); + wakesta->debug_flag = mmio_read_32(SPM_SW_DEBUG); + wakesta->debug_flag1 = mmio_read_32(WDT_LATCH_SPARE0_FIX); + wakesta->event_reg = mmio_read_32(SPM_BSI_D2_SR); + wakesta->isr = mmio_read_32(SPM_IRQ_STA); +} + +void spm_clean_after_wakeup(void) +{ + mmio_write_32(SPM_SW_RSV_0, + mmio_read_32(SPM_WAKEUP_STA) | + mmio_read_32(SPM_SW_RSV_0)); + mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0); + mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~0); + mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM); + mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM); + mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL); +} + +void spm_output_wake_reason(struct wake_status *wakesta, const char *scenario) +{ + uint32_t i; + + if (wakesta->assert_pc != 0) { + INFO("%s: PCM ASSERT AT %u, ULPOSC_CON = 0x%x\n", + scenario, wakesta->assert_pc, mmio_read_32(ULPOSC_CON)); + goto spm_debug_flags; + } + + for (i = 0; i <= 31; i++) { + if (wakesta->r12 & (1U << i)) { + INFO("%s: wake up by %s, timer_out = %u\n", + scenario, wakeup_src_str[i], wakesta->timer_out); + break; + } + } + +spm_debug_flags: + INFO("r15 = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n", + wakesta->r15, wakesta->r13, wakesta->debug_flag, + wakesta->debug_flag1); + INFO("sw_flag = 0x%x 0x%x, r12 = 0x%x, r12_ext = 0x%x\n", + wakesta->sw_flag, wakesta->sw_flag1, wakesta->r12, + wakesta->r12_ext); + INFO("idle_sta = 0x%x, req_sta = 0x%x, event_reg = 0x%x\n", + wakesta->idle_sta, wakesta->req_sta, wakesta->event_reg); + INFO("isr = 0x%x, raw_sta = 0x%x, raw_ext_sta = 0x%x\n", + wakesta->isr, wakesta->raw_sta, wakesta->raw_ext_sta); + INFO("wake_misc = 0x%x\n", wakesta->wake_misc); +} + +void spm_boot_init(void) +{ + NOTICE("%s() start\n", __func__); + + spm_lock_init(); + mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); + + NOTICE("%s() end\n", __func__); +} diff --git a/plat/mediatek/mt8183/drivers/spm/spm.h b/plat/mediatek/mt8183/drivers/spm/spm.h new file mode 100644 index 000000000..b2e83dc7a --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm.h @@ -0,0 +1,2552 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPM_H +#define SPM_H + +/************************************** + * Define and Declare + **************************************/ + +#define POWERON_CONFIG_EN (SPM_BASE + 0x000) +#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) +#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) +#define SPM_CLK_CON (SPM_BASE + 0x00C) +#define SPM_CLK_SETTLE (SPM_BASE + 0x010) +#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) +#define PCM_CON0 (SPM_BASE + 0x018) +#define PCM_CON1 (SPM_BASE + 0x01C) +#define PCM_IM_PTR (SPM_BASE + 0x020) +#define PCM_IM_LEN (SPM_BASE + 0x024) +#define PCM_REG_DATA_INI (SPM_BASE + 0x028) +#define PCM_PWR_IO_EN (SPM_BASE + 0x02C) +#define PCM_TIMER_VAL (SPM_BASE + 0x030) +#define PCM_WDT_VAL (SPM_BASE + 0x034) +#define PCM_IM_HOST_RW_PTR (SPM_BASE + 0x038) +#define PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03C) +#define PCM_EVENT_VECTOR0 (SPM_BASE + 0x040) +#define PCM_EVENT_VECTOR1 (SPM_BASE + 0x044) +#define PCM_EVENT_VECTOR2 (SPM_BASE + 0x048) +#define PCM_EVENT_VECTOR3 (SPM_BASE + 0x04C) +#define PCM_EVENT_VECTOR4 (SPM_BASE + 0x050) +#define PCM_EVENT_VECTOR5 (SPM_BASE + 0x054) +#define PCM_EVENT_VECTOR6 (SPM_BASE + 0x058) +#define PCM_EVENT_VECTOR7 (SPM_BASE + 0x05C) +#define PCM_EVENT_VECTOR8 (SPM_BASE + 0x060) +#define PCM_EVENT_VECTOR9 (SPM_BASE + 0x064) +#define PCM_EVENT_VECTOR10 (SPM_BASE + 0x068) +#define PCM_EVENT_VECTOR11 (SPM_BASE + 0x06C) +#define PCM_EVENT_VECTOR12 (SPM_BASE + 0x070) +#define PCM_EVENT_VECTOR13 (SPM_BASE + 0x074) +#define PCM_EVENT_VECTOR14 (SPM_BASE + 0x078) +#define PCM_EVENT_VECTOR15 (SPM_BASE + 0x07C) +#define PCM_EVENT_VECTOR_EN (SPM_BASE + 0x080) +#define SPM_SRAM_RSV_CON (SPM_BASE + 0x088) +#define SPM_SWINT (SPM_BASE + 0x08C) +#define SPM_SWINT_SET (SPM_BASE + 0x090) +#define SPM_SWINT_CLR (SPM_BASE + 0x094) +#define SPM_SCP_MAILBOX (SPM_BASE + 0x098) +#define SCP_SPM_MAILBOX (SPM_BASE + 0x09C) +#define SPM_TWAM_CON (SPM_BASE + 0x0A0) +#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4) +#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8) +#define SPM_SCP_IRQ (SPM_BASE + 0x0AC) +#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) +#define SPM_IRQ_MASK (SPM_BASE + 0x0B4) +#define SPM_SRC_REQ (SPM_BASE + 0x0B8) +#define SPM_SRC_MASK (SPM_BASE + 0x0BC) +#define SPM_SRC2_MASK (SPM_BASE + 0x0C0) +#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0C4) +#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0C8) +#define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x0CC) +#define SCP_CLK_CON (SPM_BASE + 0x0D0) +#define PCM_DEBUG_CON (SPM_BASE + 0x0D4) +#define DDR_EN_DBC_LEN (SPM_BASE + 0x0D8) +#define AHB_BUS_CON (SPM_BASE + 0x0DC) +#define SPM_SRC3_MASK (SPM_BASE + 0x0E0) +#define DDR_EN_EMI_DBC_CON (SPM_BASE + 0x0E4) +#define SSPM_CLK_CON (SPM_BASE + 0x0E8) +#define PCM_REG0_DATA (SPM_BASE + 0x100) +#define PCM_REG1_DATA (SPM_BASE + 0x104) +#define PCM_REG2_DATA (SPM_BASE + 0x108) +#define PCM_REG3_DATA (SPM_BASE + 0x10C) +#define PCM_REG4_DATA (SPM_BASE + 0x110) +#define PCM_REG5_DATA (SPM_BASE + 0x114) +#define PCM_REG6_DATA (SPM_BASE + 0x118) +#define PCM_REG7_DATA (SPM_BASE + 0x11C) +#define PCM_REG8_DATA (SPM_BASE + 0x120) +#define PCM_REG9_DATA (SPM_BASE + 0x124) +#define PCM_REG10_DATA (SPM_BASE + 0x128) +#define PCM_REG11_DATA (SPM_BASE + 0x12C) +#define PCM_REG12_DATA (SPM_BASE + 0x130) +#define PCM_REG13_DATA (SPM_BASE + 0x134) +#define PCM_REG14_DATA (SPM_BASE + 0x138) +#define PCM_REG15_DATA (SPM_BASE + 0x13C) +#define PCM_REG12_MASK_B_STA (SPM_BASE + 0x140) +#define PCM_REG12_EXT_DATA (SPM_BASE + 0x144) +#define PCM_REG12_EXT_MASK_B_STA (SPM_BASE + 0x148) +#define PCM_EVENT_REG_STA (SPM_BASE + 0x14C) +#define PCM_TIMER_OUT (SPM_BASE + 0x150) +#define PCM_WDT_OUT (SPM_BASE + 0x154) +#define SPM_IRQ_STA (SPM_BASE + 0x158) +#define SPM_WAKEUP_STA (SPM_BASE + 0x15C) +#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x160) +#define SPM_WAKEUP_MISC (SPM_BASE + 0x164) +#define BUS_PROTECT_RDY (SPM_BASE + 0x168) +#define BUS_PROTECT2_RDY (SPM_BASE + 0x16C) +#define SUBSYS_IDLE_STA (SPM_BASE + 0x170) +#define CPU_IDLE_STA (SPM_BASE + 0x174) +#define PCM_FSM_STA (SPM_BASE + 0x178) +#define SRC_REQ_STA (SPM_BASE + 0x17C) +#define PWR_STATUS (SPM_BASE + 0x180) +#define PWR_STATUS_2ND (SPM_BASE + 0x184) +#define CPU_PWR_STATUS (SPM_BASE + 0x188) +#define CPU_PWR_STATUS_2ND (SPM_BASE + 0x18C) +#define MISC_STA (SPM_BASE + 0x190) +#define SPM_SRC_RDY_STA (SPM_BASE + 0x194) +#define DRAMC_DBG_LATCH (SPM_BASE + 0x19C) +#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1A0) +#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1A4) +#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1A8) +#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1AC) +#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1B0) +#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1B4) +#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1B8) +#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1BC) +#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1C0) +#define SPM_DVFS_STA (SPM_BASE + 0x1C8) +#define BUS_PROTECT3_RDY (SPM_BASE + 0x1CC) +#define SRC_DDREN_STA (SPM_BASE + 0x1E0) +#define MCU_PWR_CON (SPM_BASE + 0x200) +#define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204) +#define MP0_CPU0_PWR_CON (SPM_BASE + 0x208) +#define MP0_CPU1_PWR_CON (SPM_BASE + 0x20C) +#define MP0_CPU2_PWR_CON (SPM_BASE + 0x210) +#define MP0_CPU3_PWR_CON (SPM_BASE + 0x214) +#define MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218) +#define MP1_CPU0_PWR_CON (SPM_BASE + 0x21C) +#define MP1_CPU1_PWR_CON (SPM_BASE + 0x220) +#define MP1_CPU2_PWR_CON (SPM_BASE + 0x224) +#define MP1_CPU3_PWR_CON (SPM_BASE + 0x228) +#define MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240) +#define MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244) +#define MP0_CPU0_L1_PDN (SPM_BASE + 0x248) +#define MP0_CPU1_L1_PDN (SPM_BASE + 0x24C) +#define MP0_CPU2_L1_PDN (SPM_BASE + 0x250) +#define MP0_CPU3_L1_PDN (SPM_BASE + 0x254) +#define MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258) +#define MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C) +#define MP1_CPU0_L1_PDN (SPM_BASE + 0x260) +#define MP1_CPU1_L1_PDN (SPM_BASE + 0x264) +#define MP1_CPU2_L1_PDN (SPM_BASE + 0x268) +#define MP1_CPU3_L1_PDN (SPM_BASE + 0x26C) +#define CPU_EXT_BUCK_ISO (SPM_BASE + 0x290) +#define DUMMY1_PWR_CON (SPM_BASE + 0x2B0) +#define BYPASS_SPMC (SPM_BASE + 0x2B4) +#define SPMC_DORMANT_ENABLE (SPM_BASE + 0x2B8) +#define ARMPLL_CLK_CON (SPM_BASE + 0x2BC) +#define SPMC_IN_RET (SPM_BASE + 0x2C0) +#define VDE_PWR_CON (SPM_BASE + 0x300) +#define VEN_PWR_CON (SPM_BASE + 0x304) +#define ISP_PWR_CON (SPM_BASE + 0x308) +#define DIS_PWR_CON (SPM_BASE + 0x30C) +#define MFG_CORE1_PWR_CON (SPM_BASE + 0x310) +#define AUDIO_PWR_CON (SPM_BASE + 0x314) +#define IFR_PWR_CON (SPM_BASE + 0x318) +#define DPY_PWR_CON (SPM_BASE + 0x31C) +#define MD1_PWR_CON (SPM_BASE + 0x320) +#define VPU_TOP_PWR_CON (SPM_BASE + 0x324) +#define CONN_PWR_CON (SPM_BASE + 0x32C) +#define VPU_CORE2_PWR_CON (SPM_BASE + 0x330) +#define MFG_ASYNC_PWR_CON (SPM_BASE + 0x334) +#define MFG_PWR_CON (SPM_BASE + 0x338) +#define VPU_CORE0_PWR_CON (SPM_BASE + 0x33C) +#define VPU_CORE1_PWR_CON (SPM_BASE + 0x340) +#define CAM_PWR_CON (SPM_BASE + 0x344) +#define MFG_2D_PWR_CON (SPM_BASE + 0x348) +#define MFG_CORE0_PWR_CON (SPM_BASE + 0x34C) +#define SYSRAM_CON (SPM_BASE + 0x350) +#define SYSROM_CON (SPM_BASE + 0x354) +#define SSPM_SRAM_CON (SPM_BASE + 0x358) +#define SCP_SRAM_CON (SPM_BASE + 0x35C) +#define UFS_SRAM_CON (SPM_BASE + 0x36C) +#define DUMMY_SRAM_CON (SPM_BASE + 0x380) +#define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x390) +#define MD_SRAM_ISO_CON (SPM_BASE + 0x394) +#define MD_EXTRA_PWR_CON (SPM_BASE + 0x398) +#define EXT_BUCK_CON (SPM_BASE + 0x3A0) +#define MBIST_EFUSE_REPAIR_ACK_STA (SPM_BASE + 0x3D0) +#define SPM_DVFS_CON (SPM_BASE + 0x400) +#define SPM_MDBSI_CON (SPM_BASE + 0x404) +#define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x408) +#define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x40C) +#define SPM_BSI_GEN (SPM_BASE + 0x410) +#define SPM_BSI_EN_SR (SPM_BASE + 0x414) +#define SPM_BSI_CLK_SR (SPM_BASE + 0x418) +#define SPM_BSI_D0_SR (SPM_BASE + 0x41C) +#define SPM_BSI_D1_SR (SPM_BASE + 0x420) +#define SPM_BSI_D2_SR (SPM_BASE + 0x424) +#define SPM_AP_SEMA (SPM_BASE + 0x428) +#define SPM_SPM_SEMA (SPM_BASE + 0x42C) +#define AP_MDSRC_REQ (SPM_BASE + 0x430) +#define SPM2MD_DVFS_CON (SPM_BASE + 0x438) +#define MD2SPM_DVFS_CON (SPM_BASE + 0x43C) +#define DRAMC_DPY_CLK_SW_CON_RSV (SPM_BASE + 0x440) +#define DPY_LP_CON (SPM_BASE + 0x444) +#define CPU_DVFS_REQ (SPM_BASE + 0x448) +#define SPM_PLL_CON (SPM_BASE + 0x44C) +#define SPM_EMI_BW_MODE (SPM_BASE + 0x450) +#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x454) +#define ULPOSC_CON (SPM_BASE + 0x458) +#define SPM2MM_CON (SPM_BASE + 0x45C) +#define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x460) +#define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x464) +#define SPM_S1_MODE_CH (SPM_BASE + 0x468) +#define EMI_SELF_REFRESH_CH_STA (SPM_BASE + 0x46C) +#define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x470) +#define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x474) +#define DRAMC_DMYRD_CON (SPM_BASE + 0x478) +#define SPM_DRS_CON (SPM_BASE + 0x47C) +#define SPM_SEMA_M0 (SPM_BASE + 0x480) +#define SPM_SEMA_M1 (SPM_BASE + 0x484) +#define SPM_SEMA_M2 (SPM_BASE + 0x488) +#define SPM_SEMA_M3 (SPM_BASE + 0x48C) +#define SPM_SEMA_M4 (SPM_BASE + 0x490) +#define SPM_SEMA_M5 (SPM_BASE + 0x494) +#define SPM_SEMA_M6 (SPM_BASE + 0x498) +#define SPM_SEMA_M7 (SPM_BASE + 0x49C) +#define SPM_MAS_PAUSE_MM_MASK_B (SPM_BASE + 0x4A0) +#define SPM_MAS_PAUSE_MCU_MASK_B (SPM_BASE + 0x4A4) +#define SRAM_DREQ_ACK (SPM_BASE + 0x4AC) +#define SRAM_DREQ_CON (SPM_BASE + 0x4B0) +#define SRAM_DREQ_CON_SET (SPM_BASE + 0x4B4) +#define SRAM_DREQ_CON_CLR (SPM_BASE + 0x4B8) +#define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x4BC) +#define SPM_SSPM_IRQ (SPM_BASE + 0x4C0) +#define SPM2PMCU_INT (SPM_BASE + 0x4C4) +#define SPM2PMCU_INT_SET (SPM_BASE + 0x4C8) +#define SPM2PMCU_INT_CLR (SPM_BASE + 0x4CC) +#define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x4D0) +#define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x4D4) +#define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x4D8) +#define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x4DC) +#define PMCU2SPM_INT (SPM_BASE + 0x4E0) +#define PMCU2SPM_INT_SET (SPM_BASE + 0x4E4) +#define PMCU2SPM_INT_CLR (SPM_BASE + 0x4E8) +#define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x4EC) +#define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x4F0) +#define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x4F4) +#define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x4F8) +#define PMCU2SPM_CFG (SPM_BASE + 0x4FC) +#define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x500) +#define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x504) +#define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x508) +#define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x50C) +#define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x510) +#define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x514) +#define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x518) +#define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x51C) +#define MP0_CPU0_WFI_EN (SPM_BASE + 0x530) +#define MP0_CPU1_WFI_EN (SPM_BASE + 0x534) +#define MP0_CPU2_WFI_EN (SPM_BASE + 0x538) +#define MP0_CPU3_WFI_EN (SPM_BASE + 0x53C) +#define MP1_CPU0_WFI_EN (SPM_BASE + 0x540) +#define MP1_CPU1_WFI_EN (SPM_BASE + 0x544) +#define MP1_CPU2_WFI_EN (SPM_BASE + 0x548) +#define MP1_CPU3_WFI_EN (SPM_BASE + 0x54C) +#define MP0_L2CFLUSH (SPM_BASE + 0x554) +#define MP1_L2CFLUSH (SPM_BASE + 0x558) +#define CPU_PTPOD2_CON (SPM_BASE + 0x560) +#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570) +#define ROOT_CORE_ADDR (SPM_BASE + 0x574) +#define CPU_SPARE_CON (SPM_BASE + 0x580) +#define CPU_SPARE_CON_SET (SPM_BASE + 0x584) +#define CPU_SPARE_CON_CLR (SPM_BASE + 0x588) +#define SPM2SW_MAILBOX_0 (SPM_BASE + 0x5D0) +#define SPM2SW_MAILBOX_1 (SPM_BASE + 0x5D4) +#define SPM2SW_MAILBOX_2 (SPM_BASE + 0x5D8) +#define SPM2SW_MAILBOX_3 (SPM_BASE + 0x5DC) +#define SW2SPM_INT (SPM_BASE + 0x5E0) +#define SW2SPM_INT_SET (SPM_BASE + 0x5E4) +#define SW2SPM_INT_CLR (SPM_BASE + 0x5E8) +#define SW2SPM_MAILBOX_0 (SPM_BASE + 0x5EC) +#define SW2SPM_MAILBOX_1 (SPM_BASE + 0x5F0) +#define SW2SPM_MAILBOX_2 (SPM_BASE + 0x5F4) +#define SW2SPM_MAILBOX_3 (SPM_BASE + 0x5F8) +#define SW2SPM_CFG (SPM_BASE + 0x5FC) +#define SPM_SW_FLAG (SPM_BASE + 0x600) +#define SPM_SW_DEBUG (SPM_BASE + 0x604) +#define SPM_SW_RSV_0 (SPM_BASE + 0x608) +#define SPM_SW_RSV_1 (SPM_BASE + 0x60C) +#define SPM_SW_RSV_2 (SPM_BASE + 0x610) +#define SPM_SW_RSV_3 (SPM_BASE + 0x614) +#define SPM_SW_RSV_4 (SPM_BASE + 0x618) +#define SPM_SW_RSV_5 (SPM_BASE + 0x61C) +#define SPM_RSV_CON (SPM_BASE + 0x620) +#define SPM_RSV_STA (SPM_BASE + 0x624) +#define SPM_RSV_CON1 (SPM_BASE + 0x628) +#define SPM_RSV_STA1 (SPM_BASE + 0x62C) +#define SPM_PASR_DPD_0 (SPM_BASE + 0x630) +#define SPM_PASR_DPD_1 (SPM_BASE + 0x634) +#define SPM_PASR_DPD_2 (SPM_BASE + 0x638) +#define SPM_PASR_DPD_3 (SPM_BASE + 0x63C) +#define SPM_SPARE_CON (SPM_BASE + 0x640) +#define SPM_SPARE_CON_SET (SPM_BASE + 0x644) +#define SPM_SPARE_CON_CLR (SPM_BASE + 0x648) +#define SPM_SW_RSV_6 (SPM_BASE + 0x64C) +#define SPM_SW_RSV_7 (SPM_BASE + 0x650) +#define SPM_SW_RSV_8 (SPM_BASE + 0x654) +#define SPM_SW_RSV_9 (SPM_BASE + 0x658) +#define SPM_SW_RSV_10 (SPM_BASE + 0x65C) +#define SPM_SW_RSV_18 (SPM_BASE + 0x67C) +#define SPM_SW_RSV_19 (SPM_BASE + 0x680) +#define DVFSRC_EVENT_MASK_CON (SPM_BASE + 0x690) +#define DVFSRC_EVENT_FORCE_ON (SPM_BASE + 0x694) +#define DVFSRC_EVENT_SEL (SPM_BASE + 0x698) +#define SPM_DVFS_EVENT_STA (SPM_BASE + 0x69C) +#define SPM_DVFS_EVENT_STA1 (SPM_BASE + 0x6A0) +#define SPM_DVFS_LEVEL (SPM_BASE + 0x6A4) +#define DVFS_ABORT_STA (SPM_BASE + 0x6A8) +#define DVFS_ABORT_OTHERS_MASK (SPM_BASE + 0x6AC) +#define SPM_DFS_LEVEL (SPM_BASE + 0x6B0) +#define SPM_DVS_LEVEL (SPM_BASE + 0x6B4) +#define SPM_DVFS_MISC (SPM_BASE + 0x6B8) +#define SPARE_SRC_REQ_MASK (SPM_BASE + 0x6C0) +#define SCP_VCORE_LEVEL (SPM_BASE + 0x6C4) +#define SC_MM_CK_SEL_CON (SPM_BASE + 0x6C8) +#define SPARE_ACK_STA (SPM_BASE + 0x6F0) +#define SPARE_ACK_MASK (SPM_BASE + 0x6F4) +#define SPM_DVFS_CON1 (SPM_BASE + 0x700) +#define SPM_DVFS_CON1_STA (SPM_BASE + 0x704) +#define SPM_DVFS_CMD0 (SPM_BASE + 0x710) +#define SPM_DVFS_CMD1 (SPM_BASE + 0x714) +#define SPM_DVFS_CMD2 (SPM_BASE + 0x718) +#define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) +#define SPM_DVFS_CMD4 (SPM_BASE + 0x720) +#define SPM_DVFS_CMD5 (SPM_BASE + 0x724) +#define SPM_DVFS_CMD6 (SPM_BASE + 0x728) +#define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) +#define SPM_DVFS_CMD8 (SPM_BASE + 0x730) +#define SPM_DVFS_CMD9 (SPM_BASE + 0x734) +#define SPM_DVFS_CMD10 (SPM_BASE + 0x738) +#define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) +#define SPM_DVFS_CMD12 (SPM_BASE + 0x740) +#define SPM_DVFS_CMD13 (SPM_BASE + 0x744) +#define SPM_DVFS_CMD14 (SPM_BASE + 0x748) +#define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) +#define WDT_LATCH_SPARE0_FIX (SPM_BASE + 0x780) +#define WDT_LATCH_SPARE1_FIX (SPM_BASE + 0x784) +#define WDT_LATCH_SPARE2_FIX (SPM_BASE + 0x788) +#define WDT_LATCH_SPARE3_FIX (SPM_BASE + 0x78C) +#define SPARE_ACK_IN_FIX (SPM_BASE + 0x790) +#define DCHA_LATCH_RSV0_FIX (SPM_BASE + 0x794) +#define DCHB_LATCH_RSV0_FIX (SPM_BASE + 0x798) +#define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) +#define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) +#define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) +#define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) +#define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) +#define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) +#define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) +#define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) +#define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) +#define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) +#define WDT_LATCH_SPARE0 (SPM_BASE + 0x828) +#define WDT_LATCH_SPARE1 (SPM_BASE + 0x82C) +#define WDT_LATCH_SPARE2 (SPM_BASE + 0x830) +#define WDT_LATCH_SPARE3 (SPM_BASE + 0x834) +#define PCM_WDT_LATCH_10 (SPM_BASE + 0x838) +#define PCM_WDT_LATCH_11 (SPM_BASE + 0x83C) +#define DCHA_GATING_LATCH_0 (SPM_BASE + 0x840) +#define DCHA_GATING_LATCH_1 (SPM_BASE + 0x844) +#define DCHA_GATING_LATCH_2 (SPM_BASE + 0x848) +#define DCHA_GATING_LATCH_3 (SPM_BASE + 0x84C) +#define DCHA_GATING_LATCH_4 (SPM_BASE + 0x850) +#define DCHA_GATING_LATCH_5 (SPM_BASE + 0x854) +#define DCHA_GATING_LATCH_6 (SPM_BASE + 0x858) +#define DCHA_GATING_LATCH_7 (SPM_BASE + 0x85C) +#define DCHB_GATING_LATCH_0 (SPM_BASE + 0x860) +#define DCHB_GATING_LATCH_1 (SPM_BASE + 0x864) +#define DCHB_GATING_LATCH_2 (SPM_BASE + 0x868) +#define DCHB_GATING_LATCH_3 (SPM_BASE + 0x86C) +#define DCHB_GATING_LATCH_4 (SPM_BASE + 0x870) +#define DCHB_GATING_LATCH_5 (SPM_BASE + 0x874) +#define DCHB_GATING_LATCH_6 (SPM_BASE + 0x878) +#define DCHB_GATING_LATCH_7 (SPM_BASE + 0x87C) +#define DCHA_LATCH_RSV0 (SPM_BASE + 0x880) +#define DCHB_LATCH_RSV0 (SPM_BASE + 0x884) +#define PCM_WDT_LATCH_12 (SPM_BASE + 0x888) +#define PCM_WDT_LATCH_13 (SPM_BASE + 0x88C) +#define SPM_PC_TRACE_CON (SPM_BASE + 0x8C0) +#define SPM_PC_TRACE_G0 (SPM_BASE + 0x8C4) +#define SPM_PC_TRACE_G1 (SPM_BASE + 0x8C8) +#define SPM_PC_TRACE_G2 (SPM_BASE + 0x8CC) +#define SPM_PC_TRACE_G3 (SPM_BASE + 0x8D0) +#define SPM_PC_TRACE_G4 (SPM_BASE + 0x8D4) +#define SPM_PC_TRACE_G5 (SPM_BASE + 0x8D8) +#define SPM_PC_TRACE_G6 (SPM_BASE + 0x8DC) +#define SPM_PC_TRACE_G7 (SPM_BASE + 0x8E0) +#define SPM_ACK_CHK_CON (SPM_BASE + 0x900) +#define SPM_ACK_CHK_PC (SPM_BASE + 0x904) +#define SPM_ACK_CHK_SEL (SPM_BASE + 0x908) +#define SPM_ACK_CHK_TIMER (SPM_BASE + 0x90C) +#define SPM_ACK_CHK_STA (SPM_BASE + 0x910) +#define SPM_ACK_CHK_LATCH (SPM_BASE + 0x914) +#define SPM_ACK_CHK_CON2 (SPM_BASE + 0x920) +#define SPM_ACK_CHK_PC2 (SPM_BASE + 0x924) +#define SPM_ACK_CHK_SEL2 (SPM_BASE + 0x928) +#define SPM_ACK_CHK_TIMER2 (SPM_BASE + 0x92C) +#define SPM_ACK_CHK_STA2 (SPM_BASE + 0x930) +#define SPM_ACK_CHK_LATCH2 (SPM_BASE + 0x934) +#define SPM_ACK_CHK_CON3 (SPM_BASE + 0x940) +#define SPM_ACK_CHK_PC3 (SPM_BASE + 0x944) +#define SPM_ACK_CHK_SEL3 (SPM_BASE + 0x948) +#define SPM_ACK_CHK_TIMER3 (SPM_BASE + 0x94C) +#define SPM_ACK_CHK_STA3 (SPM_BASE + 0x950) +#define SPM_ACK_CHK_LATCH3 (SPM_BASE + 0x954) +#define SPM_ACK_CHK_CON4 (SPM_BASE + 0x960) +#define SPM_ACK_CHK_PC4 (SPM_BASE + 0x964) +#define SPM_ACK_CHK_SEL4 (SPM_BASE + 0x968) +#define SPM_ACK_CHK_TIMER4 (SPM_BASE + 0x96C) +#define SPM_ACK_CHK_STA4 (SPM_BASE + 0x970) +#define SPM_ACK_CHK_LATCH4 (SPM_BASE + 0x974) + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ +#define MD_BCLK_CG_EN_LSB (1U << 1) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ +#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ +/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ +#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ +/* SPM_CLK_CON (0x10006000+0x00C) */ +#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ +#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ +#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ +#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ +#define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ +#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ +#define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */ +#define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ +#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ +#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ +#define SRCLKEN1_EN_LSB (1U << 14) /* 1b */ +#define SCP_DCM_EN_LSB (1U << 15) /* 1b */ +#define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */ +#define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */ +/* SPM_CLK_SETTLE (0x10006000+0x010) */ +#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ +/* SPM_AP_STANDBY_CON (0x10006000+0x014) */ +#define WFI_OP_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */ +#define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ +#define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ +#define MM_MASK_B_LSB (1U << 16) /* 2b */ +#define MD_DDR_EN_0_DBC_EN_LSB (1U << 18) /* 1b */ +#define MD_DDR_EN_1_DBC_EN_LSB (1U << 19) /* 1b */ +#define MD_MASK_B_LSB (1U << 20) /* 2b */ +#define SSPM_MASK_B_LSB (1U << 22) /* 1b */ +#define SCP_MASK_B_LSB (1U << 23) /* 1b */ +#define SRCCLKENI_MASK_B_LSB (1U << 24) /* 1b */ +#define MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ +#define MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ +#define CONN_DDR_EN_DBC_EN_LSB (1U << 27) /* 1b */ +#define CONN_MASK_B_LSB (1U << 28) /* 1b */ +#define CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_KICK_L_LSB (1U << 0) /* 1b */ +#define IM_KICK_L_LSB (1U << 1) /* 1b */ +#define PCM_CK_EN_LSB (1U << 2) /* 1b */ +#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ +#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ +#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* PCM_CON1 (0x10006000+0x01C) */ +#define IM_SLAVE_LSB (1U << 0) /* 1b */ +#define IM_SLEEP_LSB (1U << 1) /* 1b */ +#define MIF_APBEN_LSB (1U << 3) /* 1b */ +#define IM_PDN_LSB (1U << 4) /* 1b */ +#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ +#define IM_NONRP_EN_LSB (1U << 6) /* 1b */ +#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ +#define PCM_WDT_EN_LSB (1U << 8) /* 1b */ +#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ +#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ +#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ +#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ +#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ +#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* PCM_IM_PTR (0x10006000+0x020) */ +#define PCM_IM_PTR_LSB (1U << 0) /* 32b */ +/* PCM_IM_LEN (0x10006000+0x024) */ +#define PCM_IM_LEN_LSB (1U << 0) /* 13b */ +/* PCM_REG_DATA_INI (0x10006000+0x028) */ +#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ +/* PCM_PWR_IO_EN (0x10006000+0x02C) */ +#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ +#define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */ +/* PCM_TIMER_VAL (0x10006000+0x030) */ +#define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ +/* PCM_WDT_VAL (0x10006000+0x034) */ +#define PCM_WDT_VAL_LSB (1U << 0) /* 32b */ +/* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */ +#define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */ +#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ +#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ +/* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */ +#define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */ +/* PCM_EVENT_VECTOR0 (0x10006000+0x040) */ +#define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR1 (0x10006000+0x044) */ +#define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR2 (0x10006000+0x048) */ +#define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */ +#define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR4 (0x10006000+0x050) */ +#define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR5 (0x10006000+0x054) */ +#define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR6 (0x10006000+0x058) */ +#define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */ +#define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR8 (0x10006000+0x060) */ +#define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR9 (0x10006000+0x064) */ +#define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR10 (0x10006000+0x068) */ +#define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */ +#define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR12 (0x10006000+0x070) */ +#define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR13 (0x10006000+0x074) */ +#define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR14 (0x10006000+0x078) */ +#define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */ +#define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */ +#define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */ +/* SPM_SRAM_RSV_CON (0x10006000+0x088) */ +#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ +/* SPM_SWINT (0x10006000+0x08C) */ +#define SPM_SWINT_LSB (1U << 0) /* 10b */ +/* SPM_SWINT_SET (0x10006000+0x090) */ +#define SPM_SWINT_SET_LSB (1U << 0) /* 10b */ +/* SPM_SWINT_CLR (0x10006000+0x094) */ +#define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */ +/* SPM_SCP_MAILBOX (0x10006000+0x098) */ +#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ +/* SCP_SPM_MAILBOX (0x10006000+0x09C) */ +#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CON (0x10006000+0x0A0) */ +#define TWAM_ENABLE_LSB (1U << 0) /* 1b */ +#define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */ +#define TWAM_SW_RST_LSB (1U << 2) /* 1b */ +#define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */ +#define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */ +#define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */ +#define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */ +#define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */ +#define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */ +#define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */ +#define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */ +/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ +#define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ +#define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */ +/* SPM_SCP_IRQ (0x10006000+0x0AC) */ +#define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */ +#define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */ +/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ +#define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */ +/* SPM_IRQ_MASK (0x10006000+0x0B4) */ +#define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */ +#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ +#define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */ +/* SPM_SRC_REQ (0x10006000+0x0B8) */ +#define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ +#define SPM_F26M_REQ_LSB (1U << 1) /* 1b */ +#define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ +#define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ +#define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */ +#define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */ +#define SPM_DDREN_2_REQ_LSB (1U << 11) /* 1b */ +#define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */ +/* SPM_SRC_MASK (0x10006000+0x0BC) */ +#define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */ +#define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */ +#define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */ +#define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */ +#define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */ +#define CCIF2_MD_EVENT_MASK_B_LSB (1U << 5) /* 1b */ +#define CCIF2_AP_EVENT_MASK_B_LSB (1U << 6) /* 1b */ +#define CCIF3_MD_EVENT_MASK_B_LSB (1U << 7) /* 1b */ +#define CCIF3_AP_EVENT_MASK_B_LSB (1U << 8) /* 1b */ +#define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 9) /* 1b */ +#define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 10) /* 1b */ +#define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 11) /* 1b */ +#define UFS_INFRA_REQ_MASK_B_LSB (1U << 12) /* 1b */ +#define SRCCLKENI_INFRA_MASK_B_LSB (1U << 13) /* 1b */ +#define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 14) /* 1b */ +#define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 15) /* 1b */ +#define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 16) /* 1b */ +#define UFS_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ +#define MD_VRF18_REQ_0_MASK_B_LSB (1U << 18) /* 1b */ +#define MD_VRF18_REQ_1_MASK_B_LSB (1U << 19) /* 1b */ +#define UFS_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ +#define GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ +#define CONN_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ +#define GCE_APSRC_REQ_MASK_B_LSB (1U << 23) /* 1b */ +#define DISP0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ +#define DISP1_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ +#define MFG_REQ_MASK_B_LSB (1U << 26) /* 1b */ +#define VDEC_REQ_MASK_B_LSB (1U << 27) /* 1b */ +/* SPM_SRC2_MASK (0x10006000+0x0C0) */ +#define MD_DDR_EN_0_MASK_B_LSB (1U << 0) /* 1b */ +#define MD_DDR_EN_1_MASK_B_LSB (1U << 1) /* 1b */ +#define CONN_DDR_EN_MASK_B_LSB (1U << 2) /* 1b */ +#define DDREN_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define DDREN_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ +#define DISP0_DDREN_MASK_B_LSB (1U << 5) /* 1b */ +#define DISP1_DDREN_MASK_B_LSB (1U << 6) /* 1b */ +#define GCE_DDREN_MASK_B_LSB (1U << 7) /* 1b */ +#define DDREN_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ +#define DDREN_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ +#define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */ +#define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0CC) */ +#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ +/* SCP_CLK_CON (0x10006000+0x0D0) */ +#define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ +#define SCP_SECURE_V_REQ_MASK_LSB (1U << 1) /* 1b */ +#define SCP_SLP_REQ_LSB (1U << 2) /* 1b */ +#define SCP_SLP_ACK_LSB (1U << 3) /* 1b */ +/* PCM_DEBUG_CON (0x10006000+0x0D4) */ +#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ +/* DDR_EN_DBC_LEN (0x10006000+0x0D8) */ +#define MD_DDR_EN_0_DBC_LEN_LSB (1U << 0) /* 10b */ +#define MD_DDR_EN_1_DBC_LEN_LSB (1U << 10) /* 10b */ +#define CONN_DDR_EN_DBC_LEN_LSB (1U << 20) /* 10b */ +/* AHB_BUS_CON (0x10006000+0x0DC) */ +#define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */ +#define REG_AHB_LOCK_LSB (1U << 8) /* 1b */ +/* SPM_SRC3_MASK (0x10006000+0x0E0) */ +#define MD_DDR_EN_2_0_MASK_B_LSB (1U << 0) /* 1b */ +#define MD_DDR_EN_2_1_MASK_B_LSB (1U << 1) /* 1b */ +#define CONN_DDR_EN_2_MASK_B_LSB (1U << 2) /* 1b */ +#define DDREN2_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define DDREN2_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ +#define DISP0_DDREN2_MASK_B_LSB (1U << 5) /* 1b */ +#define DISP1_DDREN2_MASK_B_LSB (1U << 6) /* 1b */ +#define GCE_DDREN2_MASK_B_LSB (1U << 7) /* 1b */ +#define DDREN2_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ +#define DDREN2_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ +/* DDR_EN_EMI_DBC_CON (0x10006000+0x0E4) */ +#define EMI_SELF_REFRESH_CH0_DBC_LEN_LSB (1U << 0) /* 10b */ +#define EMI_SELF_REFRESH_CH0_DBC_EN_LSB (1U << 10) /* 1b */ +#define EMI_SELF_REFRESH_CH1_DBC_LEN_LSB (1U << 16) /* 10b */ +#define EMI_SELF_REFRESH_CH1_DBC_EN_LSB (1U << 26) /* 1b */ +/* SSPM_CLK_CON (0x10006000+0x0E8) */ +#define SSPM_26M_CK_SEL_LSB (1U << 0) /* 1b */ +/* PCM_REG0_DATA (0x10006000+0x100) */ +#define PCM_REG0_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG1_DATA (0x10006000+0x104) */ +#define PCM_REG1_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG2_DATA (0x10006000+0x108) */ +#define PCM_REG2_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG3_DATA (0x10006000+0x10C) */ +#define PCM_REG3_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG4_DATA (0x10006000+0x110) */ +#define PCM_REG4_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG5_DATA (0x10006000+0x114) */ +#define PCM_REG5_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG6_DATA (0x10006000+0x118) */ +#define PCM_REG6_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG7_DATA (0x10006000+0x11C) */ +#define PCM_REG7_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG8_DATA (0x10006000+0x120) */ +#define PCM_REG8_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG9_DATA (0x10006000+0x124) */ +#define PCM_REG9_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG10_DATA (0x10006000+0x128) */ +#define PCM_REG10_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG11_DATA (0x10006000+0x12C) */ +#define PCM_REG11_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_DATA (0x10006000+0x130) */ +#define PCM_REG12_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG13_DATA (0x10006000+0x134) */ +#define PCM_REG13_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG14_DATA (0x10006000+0x138) */ +#define PCM_REG14_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG15_DATA (0x10006000+0x13C) */ +#define PCM_REG15_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_MASK_B_STA (0x10006000+0x140) */ +#define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_EXT_DATA (0x10006000+0x144) */ +#define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */ +#define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */ +/* PCM_EVENT_REG_STA (0x10006000+0x14C) */ +#define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */ +/* PCM_TIMER_OUT (0x10006000+0x150) */ +#define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */ +/* PCM_WDT_OUT (0x10006000+0x154) */ +#define PCM_WDT_OUT_LSB (1U << 0) /* 32b */ +/* SPM_IRQ_STA (0x10006000+0x158) */ +#define SPM_ACK_CHK_WAKEUP_LSB (1U << 1) /* 1b */ +#define TWAM_IRQ_LSB (1U << 2) /* 1b */ +#define PCM_IRQ_LSB (1U << 3) /* 1b */ +/* #define SPM_SWINT_LSB (1U << 4) */ /* 10b */ +/* SPM_WAKEUP_STA (0x10006000+0x15C) */ +#define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */ +#define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_MISC (0x10006000+0x164) */ +#define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */ +#define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */ +#define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */ +/* BUS_PROTECT_RDY (0x10006000+0x168) */ +#define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT2_RDY (0x10006000+0x16C) */ +#define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */ +/* SUBSYS_IDLE_STA (0x10006000+0x170) */ +#define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */ +/* CPU_IDLE_STA (0x10006000+0x174) */ +#define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */ +#define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */ +#define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */ +#define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */ +#define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */ +#define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */ +#define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */ +#define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */ +#define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */ +#define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */ +#define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */ +#define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */ +#define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */ +#define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */ +#define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */ +#define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */ +#define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */ +#define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */ +#define MCUSYS_IDLE_LSB (1U << 23) /* 1b */ +/* PCM_FSM_STA (0x10006000+0x178) */ +#define EXEC_INST_OP_LSB (1U << 0) /* 4b */ +#define PC_STATE_LSB (1U << 4) /* 3b */ +#define IM_STATE_LSB (1U << 7) /* 3b */ +#define MASTER_STATE_LSB (1U << 10) /* 5b */ +#define EVENT_FSM_LSB (1U << 15) /* 3b */ +#define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */ +#define PCM_KICK_LSB (1U << 21) /* 1b */ +#define IM_KICK_LSB (1U << 22) /* 1b */ +#define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */ +#define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */ +/* SRC_REQ_STA (0x10006000+0x17C) */ +#define SRC_REQ_STA_LSB (1U << 0) /* 32b */ +/* PWR_STATUS (0x10006000+0x180) */ +#define PWR_STATUS_LSB (1U << 0) /* 32b */ +/* PWR_STATUS_2ND (0x10006000+0x184) */ +#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ +/* CPU_PWR_STATUS (0x10006000+0x188) */ +#define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */ +/* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */ +#define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ +/* MISC_STA (0x10006000+0x190) */ +#define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */ +/* SPM_SRC_RDY_STA (0x10006000+0x194) */ +#define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */ +#define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */ +/* DRAMC_DBG_LATCH (0x10006000+0x19C) */ +#define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */ +#define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */ +#define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */ +#define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */ +#define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */ +#define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */ +#define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */ +#define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */ +#define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */ +#define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_STA (0x10006000+0x1C8) */ +#define MD_DVFS_ERROR_STATUS_LSB (1U << 0) /* 1b */ +/* BUS_PROTECT3_RDY (0x10006000+0x1CC) */ +#define BUS_PROTECT_MM_RDY_LSB (1U << 0) /* 16b */ +#define BUS_PROTECT_MCU_RDY_LSB (1U << 16) /* 16b */ +/* SRC_DDREN_STA (0x10006000+0x1E0) */ +#define SRC_DDREN_STA_LSB (1U << 0) /* 32b */ +/* MCU_PWR_CON (0x10006000+0x200) */ +#define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MCU_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MCU_PWR_ON_LSB (1U << 2) /* 1b */ +#define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */ +#define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU0_PWR_CON (0x10006000+0x208) */ +#define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU1_PWR_CON (0x10006000+0x20C) */ +#define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU2_PWR_CON (0x10006000+0x210) */ +#define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU3_PWR_CON (0x10006000+0x214) */ +#define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */ +#define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU0_PWR_CON (0x10006000+0x21C) */ +#define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU1_PWR_CON (0x10006000+0x220) */ +#define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU2_PWR_CON (0x10006000+0x224) */ +#define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU3_PWR_CON (0x10006000+0x228) */ +#define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */ +#define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */ +#define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU0_L1_PDN (0x10006000+0x248) */ +#define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU1_L1_PDN (0x10006000+0x24C) */ +#define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU2_L1_PDN (0x10006000+0x250) */ +#define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU3_L1_PDN (0x10006000+0x254) */ +#define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */ +#define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */ +#define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU0_L1_PDN (0x10006000+0x260) */ +#define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU1_L1_PDN (0x10006000+0x264) */ +#define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU2_L1_PDN (0x10006000+0x268) */ +#define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU3_L1_PDN (0x10006000+0x26C) */ +#define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* CPU_EXT_BUCK_ISO (0x10006000+0x290) */ +#define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ +#define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ +#define MP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */ +/* DUMMY1_PWR_CON (0x10006000+0x2B0) */ +#define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */ +#define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +/* BYPASS_SPMC (0x10006000+0x2B4) */ +#define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */ +/* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */ +#define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */ +#define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */ +/* ARMPLL_CLK_CON (0x10006000+0x2BC) */ +#define REG_SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 3b */ +#define REG_SC_ARM_CLK_OFF_LSB (1U << 3) /* 3b */ +#define REG_SC_ARMPLLOUT_OFF_LSB (1U << 6) /* 3b */ +#define REG_SC_ARMPLL_OFF_LSB (1U << 9) /* 3b */ +#define REG_SC_ARMPLL_S_OFF_LSB (1U << 12) /* 3b */ +/* SPMC_IN_RET (0x10006000+0x2C0) */ +#define SPMC_STATUS_LSB (1U << 0) /* 8b */ +/* VDE_PWR_CON (0x10006000+0x300) */ +#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VDE_PWR_ON_LSB (1U << 2) /* 1b */ +#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* VEN_PWR_CON (0x10006000+0x304) */ +#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VEN_PWR_ON_LSB (1U << 2) /* 1b */ +#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* ISP_PWR_CON (0x10006000+0x308) */ +#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define ISP_PWR_ON_LSB (1U << 2) /* 1b */ +#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* DIS_PWR_CON (0x10006000+0x30C) */ +#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DIS_PWR_ON_LSB (1U << 2) /* 1b */ +#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_CORE1_PWR_CON (0x10006000+0x310) */ +#define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* AUDIO_PWR_CON (0x10006000+0x314) */ +#define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define AUD_PWR_ISO_LSB (1U << 1) /* 1b */ +#define AUD_PWR_ON_LSB (1U << 2) /* 1b */ +#define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* IFR_PWR_CON (0x10006000+0x318) */ +#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ +#define IFR_PWR_ON_LSB (1U << 2) /* 1b */ +#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* DPY_PWR_CON (0x10006000+0x31C) */ +#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DPY_PWR_ON_LSB (1U << 2) /* 1b */ +#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MD1_PWR_CON (0x10006000+0x320) */ +#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MD1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ +/* VPU_TOP_PWR_CON (0x10006000+0x324) */ +#define VPU_TOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_TOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_TOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_TOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_TOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_TOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_TOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_TOP_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_TOP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_TOP_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_TOP_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* CONN_PWR_CON (0x10006000+0x32C) */ +#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CONN_PWR_ON_LSB (1U << 2) /* 1b */ +#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* VPU_CORE2_PWR_CON (0x10006000+0x330) */ +#define VPU_CORE2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE2_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE2_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE2_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE2_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* MFG_ASYNC_PWR_CON (0x10006000+0x334) */ +#define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_PWR_CON (0x10006000+0x338) */ +#define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* VPU_CORE0_PWR_CON (0x10006000+0x33C) */ +#define VPU_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE0_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE0_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE0_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* VPU_CORE1_PWR_CON (0x10006000+0x340) */ +#define VPU_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE1_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE1_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE1_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* CAM_PWR_CON (0x10006000+0x344) */ +#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CAM_PWR_ON_LSB (1U << 2) /* 1b */ +#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_2D_PWR_CON (0x10006000+0x348) */ +#define MFG_2D_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_2D_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_2D_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_2D_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_2D_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_2D_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_2D_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_CORE0_PWR_CON (0x10006000+0x34C) */ +#define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_CORE0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_CORE0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* SYSRAM_CON (0x10006000+0x350) */ +#define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ +#define IFR_SRAMROM_SRAM_PDN_LSB (1U << 16) /* 8b */ +/* SYSROM_CON (0x10006000+0x354) */ +#define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */ +/* SSPM_SRAM_CON (0x10006000+0x358) */ +#define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* SCP_SRAM_CON (0x10006000+0x35C) */ +#define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* UFS_SRAM_CON (0x10006000+0x36C) */ +#define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ +#define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ +/* DUMMY_SRAM_CON (0x10006000+0x380) */ +#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ +#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ +/* MD_EXT_BUCK_ISO_CON (0x10006000+0x390) */ +#define VMODEM_BUCK_ELS_EN_LSB (1U << 0) /* 1b */ +#define VMD_BUCK_ELS_EN_LSB (1U << 1) /* 1b */ +/* MD_SRAM_ISO_CON (0x10006000+0x394) */ +#define MD1_SRAM_ISOINT_B_LSB (1U << 0) /* 1b */ +/* MD_EXTRA_PWR_CON (0x10006000+0x398) */ +#define MD1_PWR_PROT_REQ_STA_LSB (1U << 0) /* 1b */ +#define MD2_PWR_PROT_REQ_STA_LSB (1U << 1) /* 1b */ +/* EXT_BUCK_CON (0x10006000+0x3A0) */ +#define RG_VA09_ON_LSB (1U << 0) /* 1b */ +/* MBIST_EFUSE_REPAIR_ACK_STA (0x10006000+0x3D0) */ +#define MBIST_EFUSE_REPAIR_ACK_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON (0x10006000+0x400) */ +#define SPM_DVFS_CON_LSB (1U << 0) /* 4b */ +#define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */ +/* SPM_MDBSI_CON (0x10006000+0x404) */ +#define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */ +/* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */ +#define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */ +#define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_BSI_GEN (0x10006000+0x410) */ +#define SPM_BSI_START_LSB (1U << 0) /* 1b */ +/* SPM_BSI_EN_SR (0x10006000+0x414) */ +#define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_CLK_SR (0x10006000+0x418) */ +#define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D0_SR (0x10006000+0x41C) */ +#define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D1_SR (0x10006000+0x420) */ +#define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D2_SR (0x10006000+0x424) */ +#define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */ +/* SPM_AP_SEMA (0x10006000+0x428) */ +#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ +/* SPM_SPM_SEMA (0x10006000+0x42C) */ +#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ +/* AP_MDSRC_REQ (0x10006000+0x430) */ +#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ +#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ +#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ +#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ +#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ +#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ +/* SPM2MD_DVFS_CON (0x10006000+0x438) */ +#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ +/* MD2SPM_DVFS_CON (0x10006000+0x43C) */ +#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ +/* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */ +#define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */ +#define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */ +#define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */ +#define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */ +#define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */ +#define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */ +#define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */ +/* DPY_LP_CON (0x10006000+0x444) */ +#define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */ +/* CPU_DVFS_REQ (0x10006000+0x448) */ +#define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ +/* SPM_PLL_CON (0x10006000+0x44C) */ +#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ +#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ +#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ +#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ +#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ +#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ +#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ +#define SC_SSPMK_CK_OFF_LSB (1U << 17) /* 1b */ +/* SPM_EMI_BW_MODE (0x10006000+0x450) */ +#define EMI_BW_MODE_LSB (1U << 0) /* 1b */ +#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ +#define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ +#define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ +/* AP2MD_PEER_WAKEUP (0x10006000+0x454) */ +#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ +/* ULPOSC_CON (0x10006000+0x458) */ +#define ULPOSC_EN_LSB (1U << 0) /* 1b */ +#define ULPOSC_RST_LSB (1U << 1) /* 1b */ +#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ +#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ +/* SPM2MM_CON (0x10006000+0x45C) */ +#define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ +#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ +#define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ +#define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ +#define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ +#define MM2SPM_FORCE_ULTRA_ACK_LSB (1U << 16) /* 1b */ +#define MM2SPM_DBL_OSTD_ACT_ACK_LSB (1U << 17) /* 1b */ +#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ +#define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ +#define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ +/* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */ +#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */ +#define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */ +#define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */ +#define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */ +#define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */ +#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */ +#define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */ +#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */ +#define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */ +#define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */ +#define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */ +#define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */ +#define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */ +#define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */ +#define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */ +#define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */ +#define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */ +#define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */ +#define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */ +#define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */ +#define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */ +#define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */ +#define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */ +#define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */ +#define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */ +#define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */ +#define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */ +#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */ +#define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */ +/* SPM_S1_MODE_CH (0x10006000+0x468) */ +#define SPM_S1_MODE_CH_LSB (1U << 0) /* 2b */ +#define S1_EMI_CK_SWITCH_LSB (1U << 8) /* 2b */ +/* EMI_SELF_REFRESH_CH_STA (0x10006000+0x46C) */ +#define EMI_SELF_REFRESH_CH_LSB (1U << 0) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */ +#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */ +#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */ +#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */ +#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */ +#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */ +#define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */ +#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */ +#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 8) /* 2b */ +#define SW_SHU_RESTORE_SEL_LSB (1U << 10) /* 2b */ +#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 12) /* 2b */ +#define SW_DPHY_RXDLY_TRACK_EN_SEL_LSB (1U << 14) /* 2b */ +#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 16) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */ +#define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */ +#define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */ +#define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */ +#define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */ +#define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */ +#define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */ +#define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */ +#define SW_DPY_BCLK_ENABLE_LSB (1U << 8) /* 2b */ +#define SW_SHU_RESTORE_LSB (1U << 10) /* 2b */ +#define SW_DPHY_PRECAL_UP_LSB (1U << 12) /* 2b */ +#define SW_DPHY_RXDLY_TRACK_EN_LSB (1U << 14) /* 2b */ +#define SW_TX_TRACKING_DIS_LSB (1U << 16) /* 2b */ +/* DRAMC_DMYRD_CON (0x10006000+0x478) */ +#define DRAMC_DMYRD_EN_CH0_LSB (1U << 0) /* 1b */ +#define DRAMC_DMYRD_INTV_SEL_CH0_LSB (1U << 1) /* 1b */ +#define DRAMC_DMYRD_EN_MOD_SEL_CH0_LSB (1U << 2) /* 1b */ +#define DRAMC_DMYRD_EN_CH1_LSB (1U << 8) /* 1b */ +#define DRAMC_DMYRD_INTV_SEL_CH1_LSB (1U << 9) /* 1b */ +#define DRAMC_DMYRD_EN_MOD_SEL_CH1_LSB (1U << 10) /* 1b */ +/* SPM_DRS_CON (0x10006000+0x47C) */ +#define SPM_DRS_DIS_REQ_CH0_LSB (1U << 0) /* 1b */ +#define SPM_DRS_DIS_REQ_CH1_LSB (1U << 1) /* 1b */ +#define SPM_DRS_DIS_ACK_CH0_LSB (1U << 8) /* 1b */ +#define SPM_DRS_DIS_ACK_CH1_LSB (1U << 9) /* 1b */ +/* SPM_SEMA_M0 (0x10006000+0x480) */ +#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M1 (0x10006000+0x484) */ +#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M2 (0x10006000+0x488) */ +#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M3 (0x10006000+0x48C) */ +#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M4 (0x10006000+0x490) */ +#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M5 (0x10006000+0x494) */ +#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M6 (0x10006000+0x498) */ +#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M7 (0x10006000+0x49C) */ +#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ +/* SPM_MAS_PAUSE_MM_MASK_B (0x10006000+0x4A0) */ +#define SPM_MAS_PAUSE_MM_MASK_B_LSB (1U << 0) /* 16b */ +/* SPM_MAS_PAUSE_MCU_MASK_B (0x10006000+0x4A4) */ +#define SPM_MAS_PAUSE_MCU_MASK_B_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_ACK (0x10006000+0x4AC) */ +#define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON (0x10006000+0x4B0) */ +#define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */ +#define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */ +#define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */ +/* SPM2EMI_ENTER_ULPM (0x10006000+0x4BC) */ +#define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ +/* SPM_SSPM_IRQ (0x10006000+0x4C0) */ +#define SPM_SSPM_IRQ_LSB (1U << 0) /* 1b */ +#define SPM_SSPM_IRQ_SEL_LSB (1U << 4) /* 1b */ +/* SPM2PMCU_INT (0x10006000+0x4C4) */ +#define SPM2PMCU_INT_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_INT_SET (0x10006000+0x4C8) */ +#define SPM2PMCU_INT_SET_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_INT_CLR (0x10006000+0x4CC) */ +#define SPM2PMCU_INT_CLR_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_MAILBOX_0 (0x10006000+0x4D0) */ +#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_1 (0x10006000+0x4D4) */ +#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_2 (0x10006000+0x4D8) */ +#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_3 (0x10006000+0x4DC) */ +#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_INT (0x10006000+0x4E0) */ +#define PMCU2SPM_INT_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_INT_SET (0x10006000+0x4E4) */ +#define PMCU2SPM_INT_SET_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_INT_CLR (0x10006000+0x4E8) */ +#define PMCU2SPM_INT_CLR_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_MAILBOX_0 (0x10006000+0x4EC) */ +#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_1 (0x10006000+0x4F0) */ +#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_2 (0x10006000+0x4F4) */ +#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_3 (0x10006000+0x4F8) */ +#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_CFG (0x10006000+0x4FC) */ +#define PMCU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ +#define SPM_PMCU_MAILBOX_REQ_LSB (1U << 8) /* 1b */ +/* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */ +#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */ +#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */ +#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */ +#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */ +#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */ +#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */ +#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */ +#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU0_WFI_EN (0x10006000+0x530) */ +#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU1_WFI_EN (0x10006000+0x534) */ +#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU2_WFI_EN (0x10006000+0x538) */ +#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU3_WFI_EN (0x10006000+0x53C) */ +#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU0_WFI_EN (0x10006000+0x540) */ +#define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU1_WFI_EN (0x10006000+0x544) */ +#define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU2_WFI_EN (0x10006000+0x548) */ +#define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU3_WFI_EN (0x10006000+0x54C) */ +#define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_L2CFLUSH (0x10006000+0x554) */ +#define MP0_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ +#define MP0_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ +/* MP1_L2CFLUSH (0x10006000+0x558) */ +#define MP1_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ +#define MP1_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ +/* CPU_PTPOD2_CON (0x10006000+0x560) */ +#define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */ +#define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */ +#define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */ +#define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */ +#define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */ +#define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */ +/* ROOT_CPUTOP_ADDR (0x10006000+0x570) */ +#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ +/* ROOT_CORE_ADDR (0x10006000+0x574) */ +#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON (0x10006000+0x580) */ +#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON_SET (0x10006000+0x584) */ +#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON_CLR (0x10006000+0x588) */ +#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_0 (0x10006000+0x5D0) */ +#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_1 (0x10006000+0x5D4) */ +#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_2 (0x10006000+0x5D8) */ +#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_3 (0x10006000+0x5DC) */ +#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* SW2SPM_INT (0x10006000+0x5E0) */ +#define SW2SPM_INT_LSB (1U << 0) /* 4b */ +/* SW2SPM_INT_SET (0x10006000+0x5E4) */ +#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ +/* SW2SPM_INT_CLR (0x10006000+0x5E8) */ +#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ +/* SW2SPM_MAILBOX_0 (0x10006000+0x5EC) */ +#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_1 (0x10006000+0x5F0) */ +#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_2 (0x10006000+0x5F4) */ +#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_3 (0x10006000+0x5F8) */ +#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* SW2SPM_CFG (0x10006000+0x5FC) */ +#define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ +#define SPM_SW_MAILBOX_REQ_LSB (1U << 8) /* 1b */ +/* SPM_SW_FLAG (0x10006000+0x600) */ +#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ +/* SPM_SW_DEBUG (0x10006000+0x604) */ +#define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_0 (0x10006000+0x608) */ +#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_1 (0x10006000+0x60C) */ +#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_2 (0x10006000+0x610) */ +#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_3 (0x10006000+0x614) */ +#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_4 (0x10006000+0x618) */ +#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_5 (0x10006000+0x61C) */ +#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ +/* SPM_RSV_CON (0x10006000+0x620) */ +#define SPM_RSV_CON_LSB (1U << 0) /* 16b */ +/* SPM_RSV_STA (0x10006000+0x624) */ +#define SPM_RSV_STA_LSB (1U << 0) /* 16b */ +/* SPM_RSV_CON1 (0x10006000+0x628) */ +#define SPM_RSV_CON1_LSB (1U << 0) /* 16b */ +/* SPM_RSV_STA1 (0x10006000+0x62C) */ +#define SPM_RSV_STA1_LSB (1U << 0) /* 16b */ +/* SPM_PASR_DPD_0 (0x10006000+0x630) */ +#define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_1 (0x10006000+0x634) */ +#define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_2 (0x10006000+0x638) */ +#define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_3 (0x10006000+0x63C) */ +#define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON (0x10006000+0x640) */ +#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON_SET (0x10006000+0x644) */ +#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON_CLR (0x10006000+0x648) */ +#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_6 (0x10006000+0x64C) */ +#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_7 (0x10006000+0x650) */ +#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_8 (0x10006000+0x654) */ +#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_9 (0x10006000+0x658) */ +#define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_10 (0x10006000+0x65C) */ +#define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_18 (0x10006000+0x67C) */ +#define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_19 (0x10006000+0x680) */ +#define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */ +/* DVFSRC_EVENT_MASK_CON (0x10006000+0x690) */ +#define DVFSRC_EVENT_MASK_B_LSB (1U << 0) /* 16b */ +#define DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 16) /* 1b */ +/* DVFSRC_EVENT_FORCE_ON (0x10006000+0x694) */ +#define DVFSRC_EVENT_FORCE_ON_LSB (1U << 0) /* 16b */ +#define DVFSRC_EVENT_TRIGGER_FORCE_ON_LSB (1U << 16) /* 1b */ +/* DVFSRC_EVENT_SEL (0x10006000+0x698) */ +#define DVFSRC_EVENT_SEL_LSB (1U << 0) /* 16b */ +/* SPM_DVFS_EVENT_STA (0x10006000+0x69C) */ +#define SPM_DVFS_EVENT_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_EVENT_STA1 (0x10006000+0x6A0) */ +#define SPM_DVFS_EVENT_STA1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_LEVEL (0x10006000+0x6A4) */ +#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 16b */ +/* DVFS_ABORT_STA (0x10006000+0x6A8) */ +#define RC2SPM_EVENT_ABORT_D2T_LSB (1U << 0) /* 16b */ +#define RC2SPM_EVENT_ABORT_MASK_OR_LSB (1U << 16) /* 1b */ +/* DVFS_ABORT_OTHERS_MASK (0x10006000+0x6AC) */ +#define DVFS_ABORT_OTHERS_MASK_B_LSB (1U << 0) /* 16b */ +/* SPM_DFS_LEVEL (0x10006000+0x6B0) */ +#define SPM_DFS_LEVEL_LSB (1U << 0) /* 4b */ +/* SPM_DVS_LEVEL (0x10006000+0x6B4) */ +#define SPM_VCORE_LEVEL_LSB (1U << 0) /* 8b */ +#define SPM_VSRAM_LEVEL_LSB (1U << 8) /* 8b */ +#define SPM_VMODEM_LEVEL_LSB (1U << 16) /* 8b */ +/* SPM_DVFS_MISC (0x10006000+0x6B8) */ +#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ +#define MSDC_DVFS_LEVEL_LSB (1U << 1) /* 4b */ +#define SDIO_READY_TO_SPM_LSB (1U << 7) /* 1b */ +#define MD2AP_CENTRAL_BUCK_GEAR_REQ_D2T_LSB (1U << 8) /* 1b */ +#define MD2AP_CENTRAL_BUCK_GEAR_RDY_D2T_LSB (1U << 9) /* 1b */ +/* SPARE_SRC_REQ_MASK (0x10006000+0x6C0) */ +#define SPARE1_DDREN_MASK_B_LSB (1U << 0) /* 1b */ +#define SPARE1_APSRC_REQ_MASK_B_LSB (1U << 1) /* 1b */ +#define SPARE1_VRF18_REQ_MASK_B_LSB (1U << 2) /* 1b */ +#define SPARE1_INFRA_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define SPARE1_SRCCLKENA_MASK_B_LSB (1U << 4) /* 1b */ +#define SPARE1_DDREN_2_MASK_B_LSB (1U << 5) /* 1b */ +#define SPARE2_DDREN_MASK_B_LSB (1U << 8) /* 1b */ +#define SPARE2_APSRC_REQ_MASK_B_LSB (1U << 9) /* 1b */ +#define SPARE2_VRF18_REQ_MASK_B_LSB (1U << 10) /* 1b */ +#define SPARE2_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ +#define SPARE2_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ +#define SPARE2_DDREN_2_MASK_B_LSB (1U << 13) /* 1b */ +/* SCP_VCORE_LEVEL (0x10006000+0x6C4) */ +#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 8b */ +/* SC_MM_CK_SEL_CON (0x10006000+0x6C8) */ +#define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ +#define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ +/* SPARE_ACK_STA (0x10006000+0x6F0) */ +#define SPARE_ACK_SYNC_LSB (1U << 0) /* 32b */ +/* SPARE_ACK_MASK (0x10006000+0x6F4) */ +#define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON1 (0x10006000+0x700) */ +#define SPM_DVFS_CON1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON1_STA (0x10006000+0x704) */ +#define SPM_DVFS_CON1_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD0 (0x10006000+0x710) */ +#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD1 (0x10006000+0x714) */ +#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD2 (0x10006000+0x718) */ +#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD3 (0x10006000+0x71C) */ +#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD4 (0x10006000+0x720) */ +#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD5 (0x10006000+0x724) */ +#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD6 (0x10006000+0x728) */ +#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD7 (0x10006000+0x72C) */ +#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD8 (0x10006000+0x730) */ +#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD9 (0x10006000+0x734) */ +#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD10 (0x10006000+0x738) */ +#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD11 (0x10006000+0x73C) */ +#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD12 (0x10006000+0x740) */ +#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD13 (0x10006000+0x744) */ +#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD14 (0x10006000+0x748) */ +#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD15 (0x10006000+0x74C) */ +#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE0_FIX (0x10006000+0x780) */ +#define WDT_LATCH_SPARE0_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE1_FIX (0x10006000+0x784) */ +#define WDT_LATCH_SPARE1_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE2_FIX (0x10006000+0x788) */ +#define WDT_LATCH_SPARE2_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE3_FIX (0x10006000+0x78C) */ +#define WDT_LATCH_SPARE3_FIX_LSB (1U << 0) /* 32b */ +/* SPARE_ACK_IN_FIX (0x10006000+0x790) */ +#define SPARE_ACK_IN_FIX_LSB (1U << 0) /* 32b */ +/* DCHA_LATCH_RSV0_FIX (0x10006000+0x794) */ +#define DCHA_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ +/* DCHB_LATCH_RSV0_FIX (0x10006000+0x798) */ +#define DCHB_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_0 (0x10006000+0x800) */ +#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_1 (0x10006000+0x804) */ +#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_2 (0x10006000+0x808) */ +#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ +#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_4 (0x10006000+0x810) */ +#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_5 (0x10006000+0x814) */ +#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_6 (0x10006000+0x818) */ +#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ +#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_8 (0x10006000+0x820) */ +#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_9 (0x10006000+0x824) */ +#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE0 (0x10006000+0x828) */ +#define WDT_LATCH_SPARE0_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE1 (0x10006000+0x82C) */ +#define WDT_LATCH_SPARE1_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE2 (0x10006000+0x830) */ +#define WDT_LATCH_SPARE2_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE3 (0x10006000+0x834) */ +#define WDT_LATCH_SPARE3_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_10 (0x10006000+0x838) */ +#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_11 (0x10006000+0x83C) */ +#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_0 (0x10006000+0x840) */ +#define DCHA_GATING_LATCH_0_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_1 (0x10006000+0x844) */ +#define DCHA_GATING_LATCH_1_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_2 (0x10006000+0x848) */ +#define DCHA_GATING_LATCH_2_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_3 (0x10006000+0x84C) */ +#define DCHA_GATING_LATCH_3_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_4 (0x10006000+0x850) */ +#define DCHA_GATING_LATCH_4_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_5 (0x10006000+0x854) */ +#define DCHA_GATING_LATCH_5_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_6 (0x10006000+0x858) */ +#define DCHA_GATING_LATCH_6_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_7 (0x10006000+0x85C) */ +#define DCHA_GATING_LATCH_7_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_0 (0x10006000+0x860) */ +#define DCHB_GATING_LATCH_0_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_1 (0x10006000+0x864) */ +#define DCHB_GATING_LATCH_1_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_2 (0x10006000+0x868) */ +#define DCHB_GATING_LATCH_2_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_3 (0x10006000+0x86C) */ +#define DCHB_GATING_LATCH_3_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_4 (0x10006000+0x870) */ +#define DCHB_GATING_LATCH_4_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_5 (0x10006000+0x874) */ +#define DCHB_GATING_LATCH_5_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_6 (0x10006000+0x878) */ +#define DCHB_GATING_LATCH_6_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_7 (0x10006000+0x87C) */ +#define DCHB_GATING_LATCH_7_LSB (1U << 0) /* 32b */ +/* DCHA_LATCH_RSV0 (0x10006000+0x880) */ +#define DCHA_LATCH_RSV0_LSB (1U << 0) /* 32b */ +/* DCHB_LATCH_RSV0 (0x10006000+0x884) */ +#define DCHB_LATCH_RSV0_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_12 (0x10006000+0x888) */ +#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_13 (0x10006000+0x88C) */ +#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ +/* SPM_PC_TRACE_CON (0x10006000+0x8C0) */ +#define SPM_PC_TRACE_OFFSET_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE_HW_EN_LSB (1U << 16) /* 1b */ +#define SPM_PC_TRACE_SW_LSB (1U << 17) /* 1b */ +/* SPM_PC_TRACE_G0 (0x10006000+0x8C4) */ +#define SPM_PC_TRACE0_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE1_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G1 (0x10006000+0x8C8) */ +#define SPM_PC_TRACE2_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE3_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G2 (0x10006000+0x8CC) */ +#define SPM_PC_TRACE4_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE5_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G3 (0x10006000+0x8D0) */ +#define SPM_PC_TRACE6_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE7_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G4 (0x10006000+0x8D4) */ +#define SPM_PC_TRACE8_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE9_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G5 (0x10006000+0x8D8) */ +#define SPM_PC_TRACE10_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE11_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G6 (0x10006000+0x8DC) */ +#define SPM_PC_TRACE12_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE13_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G7 (0x10006000+0x8E0) */ +#define SPM_PC_TRACE14_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE15_LSB (1U << 16) /* 12b */ +/* SPM_ACK_CHK_CON (0x10006000+0x900) */ +#define SPM_ACK_CHK_SW_EN_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC (0x10006000+0x904) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL (0x10006000+0x908) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER (0x10006000+0x90C) */ +#define SPM_ACK_CHK_TIMER_VAL_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA (0x10006000+0x910) */ +#define SPM_ACK_CHK_STA_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH (0x10006000+0x914) */ +#define SPM_ACK_CHK_LATCH_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON2 (0x10006000+0x920) */ +#define SPM_ACK_CHK_SW_EN2_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL2_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER2_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ2_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN2_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN2_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN2_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN2_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN2_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE2_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL2_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC2 (0x10006000+0x924) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL2_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL2 (0x10006000+0x928) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL2_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL2_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL2_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL2_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER2 (0x10006000+0x92C) */ +#define SPM_ACK_CHK_TIMER_VAL2_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA2 (0x10006000+0x930) */ +#define SPM_ACK_CHK_STA2_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH2 (0x10006000+0x934) */ +#define SPM_ACK_CHK_LATCH2_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON3 (0x10006000+0x940) */ +#define SPM_ACK_CHK_SW_EN3_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL3_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER3_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ3_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN3_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN3_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN3_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN3_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN3_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE3_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL3_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC3 (0x10006000+0x944) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL3_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL3 (0x10006000+0x948) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL3_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL3_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL3_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL3_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER3 (0x10006000+0x94C) */ +#define SPM_ACK_CHK_TIMER_VAL3_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA3 (0x10006000+0x950) */ +#define SPM_ACK_CHK_STA3_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH3 (0x10006000+0x954) */ +#define SPM_ACK_CHK_LATCH3_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON4 (0x10006000+0x960) */ +#define SPM_ACK_CHK_SW_EN4_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL4_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER4_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ4_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN4_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN4_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN4_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN4_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN4_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE4_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL4_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC4 (0x10006000+0x964) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL4_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL4 (0x10006000+0x968) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL4_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL4_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL4_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL4_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER4 (0x10006000+0x96C) */ +#define SPM_ACK_CHK_TIMER_VAL4_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA4 (0x10006000+0x970) */ +#define SPM_ACK_CHK_STA4_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH4 (0x10006000+0x974) */ +#define SPM_ACK_CHK_LATCH4_LSB (1U << 0) /* 32b */ + +/* --- SPM Flag Define --- */ +#define SPM_FLAG_DIS_CPU_PDN (1U << 0) +#define SPM_FLAG_DIS_INFRA_PDN (1U << 1) +#define SPM_FLAG_DIS_DDRPHY_PDN (1U << 2) +#define SPM_FLAG_DIS_VCORE_DVS (1U << 3) +#define SPM_FLAG_DIS_VCORE_DFS (1U << 4) +#define SPM_FLAG_DIS_COMMON_SCENARIO (1U << 5) +#define SPM_FLAG_DIS_BUS_CLOCK_OFF (1U << 6) +#define SPM_FLAG_DIS_ATF_ABORT (1U << 7) +#define SPM_FLAG_KEEP_CSYSPWRUPACK_HIGH (1U << 8) +#define SPM_FLAG_DIS_VPROC_VSRAM_DVS (1U << 9) +#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10) +#define SPM_FLAG_EN_MET_DEBUG_USAGE (1U << 11) +#define SPM_FLAG_SODI_CG_MODE (1U << 12) +#define SPM_FLAG_SODI_NO_EVENT (1U << 13) +#define SPM_FLAG_ENABLE_SODI3 (1U << 14) +#define SPM_FLAG_DISABLE_MMSYS_DVFS (1U << 15) +#define SPM_FLAG_DIS_SYSRAM_SLEEP (1U << 16) +#define SPM_FLAG_DIS_SSPM_SRAM_SLEEP (1U << 17) +#define SPM_FLAG_DIS_VMODEM_DVS (1U << 18) +#define SPM_FLAG_SUSPEND_OPTION (1U << 19) +#define SPM_FLAG_DEEPIDLE_OPTION (1U << 20) +#define SPM_FLAG_SODI_OPTION (1U << 21) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT22 (1U << 22) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT23 (1U << 23) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT24 (1U << 24) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT25 (1U << 25) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT26 (1U << 26) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT27 (1U << 27) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT28 (1U << 28) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT29 (1U << 29) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT30 (1U << 30) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT31 (1U << 31) + +/* --- SPM Flag1 Define --- */ +#define SPM_FLAG1_RESERVED_BIT0 (1U << 0) +#define SPM_FLAG1_ENABLE_CPU_DORMANT (1U << 1) +#define SPM_FLAG1_ENABLE_CPU_SLEEP_VOLT (1U << 2) +#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 3) +#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 4) +#define SPM_FLAG1_VCORE_LP_0P7V (1U << 5) +#define SPM_FLAG1_DISABLE_MCDSR (1U << 6) +#define SPM_FLAG1_DISABLE_NO_RESUME (1U << 7) +#define SPM_FLAG1_BIG_BUCK_OFF_ENABLE (1U << 8) +#define SPM_FLAG1_BIG_BUCK_ON_ENABLE (1U << 9) +#define SPM_FLAG1_RESERVED_BIT10 (1U << 10) +#define SPM_FLAG1_RESERVED_BIT11 (1U << 11) +#define SPM_FLAG1_RESERVED_BIT12 (1U << 12) +#define SPM_FLAG1_RESERVED_BIT13 (1U << 13) +#define SPM_FLAG1_RESERVED_BIT14 (1U << 14) +#define SPM_FLAG1_DIS_ARMPLL_OFF (1U << 15) +#define SPM_FLAG1_DIS_AXI_BUS_TO_26M (1U << 16) +#define SPM_FLAG1_DIS_IMP_DIS (1U << 17) +#define SPM_FLAG1_DIS_IMP_COPY (1U << 18) +#define SPM_FLAG1_DIS_EMI_TOGGLE_WORKAROUND (1U << 19) +#define SPM_FLAG1_DIS_DRAM_ENTER_SREF (1U << 20) +#define SPM_FLAG1_DIS_DRAM_DLL_OFF (1U << 21) +#define SPM_FLAG1_DIS_PHYPLL_OFF (1U << 22) +#define SPM_FLAG1_DIS_MPLL_OFF (1U << 23) +#define SPM_FLAG1_DIS_SYSPLL_OFF (1U << 24) +#define SPM_FLAG1_DIS_TOP_AXI_CLK_OFF (1U << 25) +#define SPM_FLAG1_DIS_PCM_26M_SWITCH (1U << 26) +#define SPM_FLAG1_DIS_CKSQ_OFF (1U << 27) +#define SPM_FLAG1_DIS_SRCVOLTEN_OFF (1U << 28) +#define SPM_FLAG1_DIS_CHB_CG_FREE_EN (1U << 29) +#define SPM_FLAG1_DIS_CHA_DCM_RES (1U << 30) +#define SPM_FLAG1_DIS_SW_MR4 (1U << 31) + +/* --- SPM DEBUG Define --- */ +#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0) +#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1) +#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2) +#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3) +#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4) +#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5) +#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6) +#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7) +#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8) +#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9) +#define SPM_DBG_DEBUG_IDX_NFC_CKBUF_ON (1U << 10) +#define SPM_DBG_DEBUG_IDX_NFC_CKBUF_OFF (1U << 11) +#define SPM_DBG_DEBUG_IDX_CPU_PDN (1U << 12) +#define SPM_DBG_DEBUG_IDX_DPD (1U << 13) +#define SPM_DBG_DEBUG_IDX_CONN_CKBUF_ON (1U << 14) +#define SPM_DBG_DEBUG_IDX_CONN_CKBUF_OFF (1U << 15) +#define SPM_DBG_DEBUG_IDX_VCORE_DVFS_START (1U << 16) +#define SPM_DBG_DEBUG_IDX_DDREN2_WAKE (1U << 17) +#define SPM_DBG_DEBUG_IDX_DDREN2_SLEEP (1U << 18) +#define SPM_DBG_DEBUG_IDX_SSPM_WFI (1U << 19) +#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 20) +#define SPM_DBG_RESERVED_BIT21 (1U << 21) +#define SPM_DBG_RESERVED_BIT22 (1U << 22) +#define SPM_DBG_RESERVED_BIT23 (1U << 23) +#define SPM_DBG_RESERVED_BIT24 (1U << 24) +#define SPM_DBG_RESERVED_BIT25 (1U << 25) +#define SPM_DBG_RESERVED_BIT26 (1U << 26) +#define SPM_DBG_SODI1_FLAG (1U << 27) +#define SPM_DBG_SODI3_FLAG (1U << 28) +#define SPM_DBG_VCORE_DVFS_FLAG (1U << 29) +#define SPM_DBG_DEEPIDLE_FLAG (1U << 30) +#define SPM_DBG_SUSPEND_FLAG (1U << 31) + +/* --- SPM DEBUG1 Define --- */ +#define SPM_DBG1_DRAM_SREF_ACK_TO (1U << 0) +#define SPM_DBG1_PWRAP_SLEEP_ACK_TO (1U << 1) +#define SPM_DBG1_PWRAP_SPI_ACK_TO (1U << 2) +#define SPM_DBG1_DRAM_GATE_ERR_DDREN_WAKEUP (1U << 3) +#define SPM_DBG1_DRAM_GATE_ERR_LEAVE_LP_SCN (1U << 4) +#define SPM_DBG1_RESERVED_BIT5 (1U << 5) +#define SPM_DBG1_RESERVED_BIT6 (1U << 6) +#define SPM_DBG1_RESERVED_BIT7 (1U << 7) +#define SPM_DBG1_RESERVED_BIT8 (1U << 8) +#define SPM_DBG1_RESERVED_BIT9 (1U << 9) +#define SPM_DBG1_RESERVED_BIT10 (1U << 10) +#define SPM_DBG1_RESERVED_BIT11 (1U << 11) +#define SPM_DBG1_RESERVED_BIT12 (1U << 12) +#define SPM_DBG1_RESERVED_BIT13 (1U << 13) +#define SPM_DBG1_RESERVED_BIT14 (1U << 14) +#define SPM_DBG1_RESERVED_BIT15 (1U << 15) +#define SPM_DBG1_RESERVED_BIT16 (1U << 16) +#define SPM_DBG1_RESERVED_BIT17 (1U << 17) +#define SPM_DBG1_RESERVED_BIT18 (1U << 18) +#define SPM_DBG1_RESERVED_BIT19 (1U << 19) +#define SPM_DBG1_RESERVED_BIT20 (1U << 20) +#define SPM_DBG1_RESERVED_BIT21 (1U << 21) +#define SPM_DBG1_RESERVED_BIT22 (1U << 22) +#define SPM_DBG1_RESERVED_BIT23 (1U << 23) +#define SPM_DBG1_RESERVED_BIT24 (1U << 24) +#define SPM_DBG1_RESERVED_BIT25 (1U << 25) +#define SPM_DBG1_RESERVED_BIT26 (1U << 26) +#define SPM_DBG1_RESERVED_BIT27 (1U << 27) +#define SPM_DBG1_RESERVED_BIT28 (1U << 28) +#define SPM_DBG1_RESERVED_BIT29 (1U << 29) +#define SPM_DBG1_RESERVED_BIT30 (1U << 30) +#define SPM_DBG1_RESERVED_BIT31 (1U << 31) + +/* --- R0 Define --- */ +#define R0_SC_26M_CK_OFF (1U << 0) +#define R0_BIT1 (1U << 1) +#define R0_SC_MEM_CK_OFF (1U << 2) +#define R0_SC_AXI_CK_OFF (1U << 3) +#define R0_SC_DR_GATE_RETRY_EN_PCM (1U << 4) +#define R0_SC_MD26M_CK_OFF (1U << 5) +#define R0_SC_DPY_MODE_SW_PCM (1U << 6) +#define R0_SC_DMSUS_OFF_PCM (1U << 7) +#define R0_SC_DPY_2ND_DLL_EN_PCM (1U << 8) +#define R0_BIT9 (1U << 9) +#define R0_SC_MPLLOUT_OFF (1U << 10) +#define R0_SC_TX_TRACKING_DIS (1U << 11) +#define R0_SC_DPY_DLL_EN_PCM (1U << 12) +#define R0_SC_DPY_DLL_CK_EN_PCM (1U << 13) +#define R0_SC_DPY_VREF_EN_PCM (1U << 14) +#define R0_SC_PHYPLL_EN_PCM (1U << 15) +#define R0_SC_DDRPHY_FB_CK_EN_PCM (1U << 16) +#define R0_SC_DPY_BCLK_ENABLE (1U << 17) +#define R0_SC_MPLL_OFF (1U << 18) +#define R0_SC_SHU_RESTORE (1U << 19) +#define R0_SC_CKSQ0_OFF (1U << 20) +#define R0_SC_CKSQ1_OFF (1U << 21) +#define R0_SC_DR_SHU_EN_PCM (1U << 22) +#define R0_SC_DPHY_PRECAL_UP (1U << 23) +#define R0_SC_MPLL_S_OFF (1U << 24) +#define R0_SC_DPHY_RXDLY_TRACK_EN (1U << 25) +#define R0_SC_PHYPLL_SHU_EN_PCM (1U << 26) +#define R0_SC_PHYPLL2_SHU_EN_PCM (1U << 27) +#define R0_SC_PHYPLL_MODE_SW_PCM (1U << 28) +#define R0_SC_PHYPLL2_MODE_SW_PCM (1U << 29) +#define R0_SC_DR_SHU_LEVEL_PCM0 (1U << 30) +#define R0_SC_DR_SHU_LEVEL_PCM1 (1U << 31) + +/* --- R7 Define --- */ +#define R7_PWRAP_SLEEP_REQ (1U << 0) +#define R7_EMI_CLK_OFF_REQ (1U << 1) +#define R7_TOP_MAS_PAU_REQ (1U << 2) +#define R7_SPM2CKSYS_MEM_CK_MUX_UPDATE (1U << 3) +#define R7_PCM_CK_SEL0 (1U << 4) +#define R7_PCM_CK_SEL1 (1U << 5) +#define R7_SPM2RC_DVS_DONE (1U << 6) +#define R7_FREQH_PAUSE_MPLL (1U << 7) +#define R7_SC_26M_CK_SEL (1U << 8) +#define R7_PCM_TIMER_SET (1U << 9) +#define R7_PCM_TIMER_CLR (1U << 10) +#define R7_SRCVOLTEN (1U << 11) +#define R7_CSYSPWRUPACK (1U << 12) +#define R7_IM_SLEEP_ENABLE (1U << 13) +#define R7_SRCCLKENO_0 (1U << 14) +#define R7_SYSRST (1U << 15) +#define R7_MD_APSRC_ACK (1U << 16) +#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17) +#define R7_SC_AXI_DCM_DIS (1U << 18) +#define R7_FREQH_PAUSE_MAIN (1U << 19) +#define R7_FREQH_PAUSE_MEM (1U << 20) +#define R7_SRCCLKENO_1 (1U << 21) +#define R7_WDT_KICK_P (1U << 22) +#define R7_SPM2RC_EVENT_ABORT_ACK (1U << 23) +#define R7_WAKEUP_EXT_W_SEL (1U << 24) +#define R7_WAKEUP_EXT_R_SEL (1U << 25) +#define R7_PMIC_IRQ_REQ_EN (1U << 26) +#define R7_FORCE_26M_WAKE (1U << 27) +#define R7_FORCE_APSRC_WAKE (1U << 28) +#define R7_FORCE_INFRA_WAKE (1U << 29) +#define R7_FORCE_VRF18_WAKE (1U << 30) +#define R7_SC_DR_SHORT_QUEUE_PCM (1U << 31) + +/* --- R12 Define --- */ +#define R12_PCM_TIMER (1U << 0) +#define R12_SSPM_WDT_EVENT_B (1U << 1) +#define R12_KP_IRQ_B (1U << 2) +#define R12_APWDT_EVENT_B (1U << 3) +#define R12_APXGPT1_EVENT_B (1U << 4) +#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5) +#define R12_EINT_EVENT_B (1U << 6) +#define R12_CONN_WDT_IRQ_B (1U << 7) +#define R12_CCIF0_EVENT_B (1U << 8) +#define R12_LOWBATTERY_IRQ_B (1U << 9) +#define R12_SSPM_SPM_IRQ_B (1U << 10) +#define R12_SCP_SPM_IRQ_B (1U << 11) +#define R12_SCP_WDT_EVENT_B (1U << 12) +#define R12_PCM_WDT_WAKEUP_B (1U << 13) +#define R12_USB_CDSC_B (1U << 14) +#define R12_USB_POWERDWN_B (1U << 15) +#define R12_SYS_TIMER_EVENT_B (1U << 16) +#define R12_EINT_EVENT_SECURE_B (1U << 17) +#define R12_CCIF1_EVENT_B (1U << 18) +#define R12_UART0_IRQ_B (1U << 19) +#define R12_AFE_IRQ_MCU_B (1U << 20) +#define R12_THERM_CTRL_EVENT_B (1U << 21) +#define R12_SYS_CIRQ_IRQ_B (1U << 22) +#define R12_MD2AP_PEER_EVENT_B (1U << 23) +#define R12_CSYSPWREQ_B (1U << 24) +#define R12_MD1_WDT_B (1U << 25) +#define R12_CLDMA_EVENT_B (1U << 26) +#define R12_SEJ_WDT_GPT_B (1U << 27) +#define R12_ALL_SSPM_WAKEUP_B (1U << 28) +#define R12_CPU_IRQ_B (1U << 29) +#define R12_CPU_WFI_AND_B (1U << 30) +#define R12_MCUSYS_IDLE_TO_EMI_ALL_B (1U << 31) + +/* --- R12ext Define --- */ +#define R12EXT_26M_WAKE (1U << 0) +#define R12EXT_26M_SLEEP (1U << 1) +#define R12EXT_INFRA_WAKE (1U << 2) +#define R12EXT_INFRA_SLEEP (1U << 3) +#define R12EXT_APSRC_WAKE (1U << 4) +#define R12EXT_APSRC_SLEEP (1U << 5) +#define R12EXT_VRF18_WAKE (1U << 6) +#define R12EXT_VRF18_SLEEP (1U << 7) +#define R12EXT_DVFS_ALL_STATE (1U << 8) +#define R12EXT_DVFS_LEVEL_STATE0 (1U << 9) +#define R12EXT_DVFS_LEVEL_STATE1 (1U << 10) +#define R12EXT_DVFS_LEVEL_STATE2 (1U << 11) +#define R12EXT_DDREN_WAKE (1U << 12) +#define R12EXT_DDREN_SLEEP (1U << 13) +#define R12EXT_NFC_CLK_BUF_WAKE (1U << 14) +#define R12EXT_NFC_CLK_BUF_SLEEP (1U << 15) +#define R12EXT_CONN_CLK_BUF_WAKE (1U << 16) +#define R12EXT_CONN_CLK_BUF_SLEEP (1U << 17) +#define R12EXT_MD_DVFS_ERROR_STATUS (1U << 18) +#define R12EXT_DVFS_LEVEL_STATE3 (1U << 19) +#define R12EXT_DVFS_LEVEL_STATE4 (1U << 20) +#define R12EXT_DVFS_LEVEL_STATE5 (1U << 21) +#define R12EXT_DVFS_LEVEL_STATE6 (1U << 22) +#define R12EXT_DVFS_LEVEL_STATE7 (1U << 23) +#define R12EXT_DVFS_LEVEL_STATE8 (1U << 24) +#define R12EXT_DVFS_LEVEL_STATE9 (1U << 25) +#define R12EXT_DVFS_LEVEL_STATE_G0 (1U << 26) +#define R12EXT_DVFS_LEVEL_STATE_G1 (1U << 27) +#define R12EXT_DVFS_LEVEL_STATE_G2 (1U << 28) +#define R12EXT_DVFS_LEVEL_STATE_G3 (1U << 29) +#define R12EXT_HYBRID_DDREN_SLEEP (1U << 30) +#define R12EXT_HYBRID_DDREN_WAKE (1U << 31) + +/* --- R13 Define --- */ +#define R13_EXT_SRCCLKENI_0 (1U << 0) +#define R13_EXT_SRCCLKENI_1 (1U << 1) +#define R13_MD1_SRCCLKENA (1U << 2) +#define R13_MD1_APSRC_REQ (1U << 3) +#define R13_CONN_DDR_EN (1U << 4) +#define R13_MD2_SRCCLKENA (1U << 5) +#define R13_SSPM_SRCCLKENA (1U << 6) +#define R13_SSPM_APSRC_REQ (1U << 7) +#define R13_MD_STATE (1U << 8) +#define R13_EMI_CLK_OFF_2_ACK (1U << 9) +#define R13_MM_STATE (1U << 10) +#define R13_SSPM_STATE (1U << 11) +#define R13_MD_DDR_EN (1U << 12) +#define R13_CONN_STATE (1U << 13) +#define R13_CONN_SRCCLKENA (1U << 14) +#define R13_CONN_APSRC_REQ (1U << 15) +#define R13_SLEEP_EVENT_STA (1U << 16) +#define R13_WAKE_EVENT_STA (1U << 17) +#define R13_EMI_IDLE (1U << 18) +#define R13_CSYSPWRUPREQ (1U << 19) +#define R13_PWRAP_SLEEP_ACK (1U << 20) +#define R13_EMI_CLK_OFF_ACK_ALL (1U << 21) +#define R13_TOP_MAS_PAU_ACK (1U << 22) +#define R13_SW_DMDRAMCSHU_ACK_ALL (1U << 23) +#define R13_RC2SPM_EVENT_ABORT_MASK_OR (1U << 24) +#define R13_DR_SHORT_QUEUE_ACK_ALL (1U << 25) +#define R13_INFRA_AUX_IDLE (1U << 26) +#define R13_DVFS_ALL_STATE (1U << 27) +#define R13_RC2SPM_EVENT_ABORT_OR (1U << 28) +#define R13_DRAMC_SPCMD_APSRC_REQ (1U << 29) +#define R13_MD1_VRF18_REQ (1U << 30) +#define R13_C2K_VRF18_REQ (1U << 31) + +#define is_cpu_pdn(flags) (!((flags) & SPM_FLAG_DIS_CPU_PDN)) +#define is_infra_pdn(flags) (!((flags) & SPM_FLAG_DIS_INFRA_PDN)) +#define is_ddrphy_pdn(flags) (!((flags) & SPM_FLAG_DIS_DDRPHY_PDN)) + +#define MP0_SPMC_SRAM_DORMANT_EN (1<<0) +#define MP1_SPMC_SRAM_DORMANT_EN (1<<1) +#define MP2_SPMC_SRAM_DORMANT_EN (1<<2) + +#define EVENT_VEC(event, resume, imme, pc) \ + (((pc) << 16) | \ + (!!(imme) << 7) | \ + (!!(resume) << 6) | \ + ((event) & 0x3f)) + +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +/************************************** + * Config and Parameter + **************************************/ +#define POWER_ON_VAL1_DEF 0x00015800 +#define PCM_FSM_STA_DEF 0x00108490 +#define SPM_WAKEUP_EVENT_MASK_DEF 0xF0F92218 +#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +/************************************** + * Define and Declare + **************************************/ +/* PCM_PWR_IO_EN */ +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +/* SPM_SWINT */ +#define PCM_SW_INT0 (1U << 0) +#define PCM_SW_INT1 (1U << 1) +#define PCM_SW_INT2 (1U << 2) +#define PCM_SW_INT3 (1U << 3) +#define PCM_SW_INT4 (1U << 4) +#define PCM_SW_INT5 (1U << 5) +#define PCM_SW_INT6 (1U << 6) +#define PCM_SW_INT7 (1U << 7) +#define PCM_SW_INT8 (1U << 8) +#define PCM_SW_INT9 (1U << 9) +#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ + PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ + PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ + PCM_SW_INT0) +/* SPM_IRQ_MASK */ +#define ISRM_TWAM (1U << 2) +#define ISRM_PCM_RETURN (1U << 3) +#define ISRM_RET_IRQ0 (1U << 8) +#define ISRM_RET_IRQ1 (1U << 9) +#define ISRM_RET_IRQ2 (1U << 10) +#define ISRM_RET_IRQ3 (1U << 11) +#define ISRM_RET_IRQ4 (1U << 12) +#define ISRM_RET_IRQ5 (1U << 13) +#define ISRM_RET_IRQ6 (1U << 14) +#define ISRM_RET_IRQ7 (1U << 15) +#define ISRM_RET_IRQ8 (1U << 16) +#define ISRM_RET_IRQ9 (1U << 17) +#define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | \ + ISRM_RET_IRQ7 | ISRM_RET_IRQ6 | \ + ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \ + ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | \ + ISRM_RET_IRQ1) +#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM (1U << 2) +#define ISRS_PCM_RETURN (1U << 3) +#define ISRS_SW_INT0 (1U << 4) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* SPM_WAKEUP_MISC */ +#define WAKE_MISC_TWAM (1U << 18) +#define WAKE_MISC_PCM_TIMER (1U << 19) +#define WAKE_MISC_CPU_WAKE (1U << 20) + +enum SPM_WAKE_SRC_LIST { + WAKE_SRC_R12_PCM_TIMER = (1U << 0), + WAKE_SRC_R12_SSPM_WDT_EVENT_B = (1U << 1), + WAKE_SRC_R12_KP_IRQ_B = (1U << 2), + WAKE_SRC_R12_APWDT_EVENT_B = (1U << 3), + WAKE_SRC_R12_APXGPT1_EVENT_B = (1U << 4), + WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B = (1U << 5), + WAKE_SRC_R12_EINT_EVENT_B = (1U << 6), + WAKE_SRC_R12_CONN_WDT_IRQ_B = (1U << 7), + WAKE_SRC_R12_CCIF0_EVENT_B = (1U << 8), + WAKE_SRC_R12_LOWBATTERY_IRQ_B = (1U << 9), + WAKE_SRC_R12_SSPM_SPM_IRQ_B = (1U << 10), + WAKE_SRC_R12_SCP_SPM_IRQ_B = (1U << 11), + WAKE_SRC_R12_SCP_WDT_EVENT_B = (1U << 12), + WAKE_SRC_R12_PCM_WDT_WAKEUP_B = (1U << 13), + WAKE_SRC_R12_USB_CDSC_B = (1U << 14), + WAKE_SRC_R12_USB_POWERDWN_B = (1U << 15), + WAKE_SRC_R12_SYS_TIMER_EVENT_B = (1U << 16), + WAKE_SRC_R12_EINT_EVENT_SECURE_B = (1U << 17), + WAKE_SRC_R12_CCIF1_EVENT_B = (1U << 18), + WAKE_SRC_R12_UART0_IRQ_B = (1U << 19), + WAKE_SRC_R12_AFE_IRQ_MCU_B = (1U << 20), + WAKE_SRC_R12_THERM_CTRL_EVENT_B = (1U << 21), + WAKE_SRC_R12_SYS_CIRQ_IRQ_B = (1U << 22), + WAKE_SRC_R12_MD2AP_PEER_EVENT_B = (1U << 23), + WAKE_SRC_R12_CSYSPWREQ_B = (1U << 24), + WAKE_SRC_R12_MD1_WDT_B = (1U << 25), + WAKE_SRC_R12_CLDMA_EVENT_B = (1U << 26), + WAKE_SRC_R12_SEJ_WDT_GPT_B = (1U << 27), + WAKE_SRC_R12_ALL_SSPM_WAKEUP_B = (1U << 28), + WAKE_SRC_R12_CPU_IRQ_B = (1U << 29), + WAKE_SRC_R12_CPU_WFI_AND_B = (1U << 30), +}; + +struct pcm_desc { + const char *version; + const uint32_t *base; + const uint32_t base_dma; + const uint32_t size; + const uint32_t sess; + const uint32_t replace; + const uint32_t addr_2nd; + const uint32_t reserved; + + uint32_t vec0; + uint32_t vec1; + uint32_t vec2; + uint32_t vec3; + uint32_t vec4; + uint32_t vec5; + uint32_t vec6; + uint32_t vec7; + uint32_t vec8; + uint32_t vec9; + uint32_t vec10; + uint32_t vec11; + uint32_t vec12; + uint32_t vec13; + uint32_t vec14; + uint32_t vec15; +}; + +struct pwr_ctrl { + uint32_t pcm_flags; + uint32_t pcm_flags1; + uint32_t timer_val; + uint32_t wake_src; + + /* SPM_AP_STANDBY_CON */ + uint8_t wfi_op; + uint8_t mp0_cputop_idle_mask; + uint8_t mp1_cputop_idle_mask; + uint8_t mcusys_idle_mask; + uint8_t mm_mask_b; + uint8_t md_ddr_en_0_dbc_en; + uint8_t md_ddr_en_1_dbc_en; + uint8_t md_mask_b; + uint8_t sspm_mask_b; + uint8_t scp_mask_b; + uint8_t srcclkeni_mask_b; + uint8_t md_apsrc_1_sel; + uint8_t md_apsrc_0_sel; + uint8_t conn_ddr_en_dbc_en; + uint8_t conn_mask_b; + uint8_t conn_apsrc_sel; + + /* SPM_SRC_REQ */ + uint8_t spm_apsrc_req; + uint8_t spm_f26m_req; + uint8_t spm_infra_req; + uint8_t spm_vrf18_req; + uint8_t spm_ddren_req; + uint8_t spm_rsv_src_req; + uint8_t spm_ddren_2_req; + uint8_t cpu_md_dvfs_sop_force_on; + + /* SPM_SRC_MASK */ + uint8_t csyspwreq_mask; + uint8_t ccif0_md_event_mask_b; + uint8_t ccif0_ap_event_mask_b; + uint8_t ccif1_md_event_mask_b; + uint8_t ccif1_ap_event_mask_b; + uint8_t ccif2_md_event_mask_b; + uint8_t ccif2_ap_event_mask_b; + uint8_t ccif3_md_event_mask_b; + uint8_t ccif3_ap_event_mask_b; + uint8_t md_srcclkena_0_infra_mask_b; + uint8_t md_srcclkena_1_infra_mask_b; + uint8_t conn_srcclkena_infra_mask_b; + uint8_t ufs_infra_req_mask_b; + uint8_t srcclkeni_infra_mask_b; + uint8_t md_apsrc_req_0_infra_mask_b; + uint8_t md_apsrc_req_1_infra_mask_b; + uint8_t conn_apsrcreq_infra_mask_b; + uint8_t ufs_srcclkena_mask_b; + uint8_t md_vrf18_req_0_mask_b; + uint8_t md_vrf18_req_1_mask_b; + uint8_t ufs_vrf18_req_mask_b; + uint8_t gce_vrf18_req_mask_b; + uint8_t conn_infra_req_mask_b; + uint8_t gce_apsrc_req_mask_b; + uint8_t disp0_apsrc_req_mask_b; + uint8_t disp1_apsrc_req_mask_b; + uint8_t mfg_req_mask_b; + uint8_t vdec_req_mask_b; + + /* SPM_SRC2_MASK */ + uint8_t md_ddr_en_0_mask_b; + uint8_t md_ddr_en_1_mask_b; + uint8_t conn_ddr_en_mask_b; + uint8_t ddren_sspm_apsrc_req_mask_b; + uint8_t ddren_scp_apsrc_req_mask_b; + uint8_t disp0_ddren_mask_b; + uint8_t disp1_ddren_mask_b; + uint8_t gce_ddren_mask_b; + uint8_t ddren_emi_self_refresh_ch0_mask_b; + uint8_t ddren_emi_self_refresh_ch1_mask_b; + + /* SPM_WAKEUP_EVENT_MASK */ + uint32_t spm_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + uint32_t spm_wakeup_event_ext_mask; + + /* SPM_SRC3_MASK */ + uint8_t md_ddr_en_2_0_mask_b; + uint8_t md_ddr_en_2_1_mask_b; + uint8_t conn_ddr_en_2_mask_b; + uint8_t ddren2_sspm_apsrc_req_mask_b; + uint8_t ddren2_scp_apsrc_req_mask_b; + uint8_t disp0_ddren2_mask_b; + uint8_t disp1_ddren2_mask_b; + uint8_t gce_ddren2_mask_b; + uint8_t ddren2_emi_self_refresh_ch0_mask_b; + uint8_t ddren2_emi_self_refresh_ch1_mask_b; + + uint8_t mp0_cpu0_wfi_en; + uint8_t mp0_cpu1_wfi_en; + uint8_t mp0_cpu2_wfi_en; + uint8_t mp0_cpu3_wfi_en; + + uint8_t mp1_cpu0_wfi_en; + uint8_t mp1_cpu1_wfi_en; + uint8_t mp1_cpu2_wfi_en; + uint8_t mp1_cpu3_wfi_en; +}; + +struct wake_status { + uint32_t assert_pc; + uint32_t r12; + uint32_t r12_ext; + uint32_t raw_sta; + uint32_t raw_ext_sta; + uint32_t wake_misc; + uint32_t timer_out; + uint32_t r13; + uint32_t r15; + uint32_t idle_sta; + uint32_t req_sta; + uint32_t debug_flag; + uint32_t debug_flag1; + uint32_t event_reg; + uint32_t isr; + uint32_t sw_flag; + uint32_t sw_flag1; + uint32_t log_index; +}; + +typedef struct spm_data { + unsigned int cmd; + union { + struct { + unsigned int sys_timestamp_l; + unsigned int sys_timestamp_h; + unsigned int sys_src_clk_l; + unsigned int sys_src_clk_h; + unsigned int spm_opt; + } suspend; + struct { + unsigned int args1; + unsigned int args2; + unsigned int args3; + unsigned int args4; + unsigned int args5; + unsigned int args6; + unsigned int args7; + } args; + } u; +} spm_data_t; + +enum { + SPM_SUSPEND, + SPM_RESUME +}; + +extern void spm_disable_pcm_timer(void); +extern void spm_set_bootaddr(unsigned long bootaddr); +extern void spm_set_cpu_status(int cpu); +extern void spm_set_power_control(const struct pwr_ctrl *pwrctrl); +extern void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); +extern void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl); +extern void spm_send_cpu_wakeup_event(void); +extern void spm_get_wakeup_status(struct wake_status *wakesta); +extern void spm_clean_after_wakeup(void); +extern void spm_output_wake_reason(struct wake_status *wakesta, + const char *scenario); +extern void spm_set_pcm_wdt(int en); +extern void spm_lock_get(void); +extern void spm_lock_release(void); +extern void spm_boot_init(void); +extern const char *spm_get_firmware_version(void); + +#endif /* SPM_H */ diff --git a/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c new file mode 100644 index 000000000..ce8527263 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +#define SLEEP_REG_MD_SPM_DVFS_CMD20 (SLEEP_REG_MD_BASE + 0x010) +#define SLEEP_REG_MD_SPM_DVFS_CMD21 (SLEEP_REG_MD_BASE + 0x014) +#define SLEEP_REG_MD_SPM_DVFS_CMD22 (SLEEP_REG_MD_BASE + 0x018) +#define SLEEP_REG_MD_SPM_DVFS_CMD23 (SLEEP_REG_MD_BASE + 0x01C) + +/* PMIC_WRAP -> PMIC MT6358 */ +#define VCORE_BASE_UV 50000 +#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) +#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV) + +#define DEFAULT_VOLT_VSRAM (100000) +#define DEFAULT_VOLT_VCORE (100000) +#define NR_PMIC_WRAP_CMD (NR_IDX_ALL) +#define MAX_RETRY_COUNT (100) +#define SPM_DATA_SHIFT (16) + +#define BUCK_VCORE_ELR0 0x14AA +#define BUCK_VPROC12_CON0 0x1408 +#define BUCK_VPROC11_CON0 0x1388 +#define TOP_SPI_CON0 0x044C +#define LDO_VSRAM_PROC12_CON0 0x1B88 +#define LDO_VSRAM_PROC11_CON0 0x1B46 +#define BUCK_VMODEM_ELR0 0x15A6 + +struct pmic_wrap_cmd { + unsigned long cmd_addr; + unsigned long cmd_wdata; +}; + +struct pmic_wrap_setting { + enum pmic_wrap_phase_id phase; + struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD]; + struct { + struct { + unsigned long cmd_addr; + unsigned long cmd_wdata; + } _[NR_PMIC_WRAP_CMD]; + const int nr_idx; + } set[NR_PMIC_WRAP_PHASE]; +}; + +static struct pmic_wrap_setting pw = { + .phase = NR_PMIC_WRAP_PHASE, + .addr = {{0, 0} }, + .set[PMIC_WRAP_PHASE_ALLINONE] = { + ._[CMD_0] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(70000),}, + ._[CMD_1] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(80000),}, + ._[CMD_2] = {BUCK_VPROC12_CON0, 0x3,}, + ._[CMD_3] = {BUCK_VPROC12_CON0, 0x1,}, + ._[CMD_4] = {BUCK_VPROC11_CON0, 0x3,}, + ._[CMD_5] = {BUCK_VPROC11_CON0, 0x1,}, + ._[CMD_6] = {TOP_SPI_CON0, 0x1,}, + ._[CMD_7] = {TOP_SPI_CON0, 0x0,}, + ._[CMD_8] = {BUCK_VPROC12_CON0, 0x0,}, + ._[CMD_9] = {BUCK_VPROC12_CON0, 0x1,}, + ._[CMD_10] = {BUCK_VPROC11_CON0, 0x0,}, + ._[CMD_11] = {BUCK_VPROC11_CON0, 0x1,}, + ._[CMD_12] = {LDO_VSRAM_PROC12_CON0, 0x0,}, + ._[CMD_13] = {LDO_VSRAM_PROC12_CON0, 0x1,}, + ._[CMD_14] = {LDO_VSRAM_PROC11_CON0, 0x0,}, + ._[CMD_15] = {LDO_VSRAM_PROC11_CON0, 0x1,}, + ._[CMD_20] = {BUCK_VMODEM_ELR0, VOLT_TO_PMIC_VAL(55000),}, + ._[CMD_21] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(60000),}, + ._[CMD_22] = {LDO_VSRAM_PROC11_CON0, 0x3,}, + ._[CMD_23] = {LDO_VSRAM_PROC11_CON0, 0x1,}, + .nr_idx = NR_IDX_ALL + } +}; + +void _mt_spm_pmic_table_init(void) +{ + struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = { + {(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,}, + {(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,}, + {(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,}, + {(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,}, + {(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,}, + {(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,}, + {(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,}, + {(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,}, + {(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,}, + {(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,}, + {(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,}, + {(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,}, + {(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,}, + {(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,}, + {(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,}, + {(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,}, + {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD20, + (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD20,}, + {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD21, + (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD21,}, + {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD22, + (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD22,}, + {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD23, + (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD23,} + }; + + memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default)); +} + +void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase) +{ + uint32_t idx, addr, data; + + if (phase >= NR_PMIC_WRAP_PHASE) + return; + + if (pw.phase == phase) + return; + + if (pw.addr[0].cmd_addr == 0) + _mt_spm_pmic_table_init(); + + pw.phase = phase; + + mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | + BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB); + for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { + addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; + data = pw.set[phase]._[idx].cmd_wdata; + mmio_write_32(pw.addr[idx].cmd_addr, addr | data); + } +} + +void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, + uint32_t cmd_wdata) +{ + uint32_t addr; + + if (phase >= NR_PMIC_WRAP_PHASE) + return; + + if (idx >= pw.set[phase].nr_idx) + return; + + pw.set[phase]._[idx].cmd_wdata = cmd_wdata; + + mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | + BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB); + if (pw.phase == phase) { + addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; + mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); + } +} + +uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx) +{ + if (phase >= NR_PMIC_WRAP_PHASE) + return 0; + + if (idx >= pw.set[phase].nr_idx) + return 0; + + return pw.set[phase]._[idx].cmd_wdata; +} + diff --git a/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h new file mode 100644 index 000000000..194d34717 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/**************************************************************** + * Auto generated by DE, please DO NOT modify this file directly. + *****************************************************************/ + +#ifndef SPM_PMIC_WRAP__H +#define SPM_PMIC_WRAP__H + +enum pmic_wrap_phase_id { + PMIC_WRAP_PHASE_ALLINONE, + NR_PMIC_WRAP_PHASE +}; + +/* IDX mapping */ +enum { + CMD_0, /* 0x0 *//* PMIC_WRAP_PHASE_ALLINONE */ + CMD_1, /* 0x1 */ + CMD_2, /* 0x2 */ + CMD_3, /* 0x3 */ + CMD_4, /* 0x4 */ + CMD_5, /* 0x5 */ + CMD_6, /* 0x6 */ + CMD_7, /* 0x7 */ + CMD_8, /* 0x8 */ + CMD_9, /* 0x9 */ + CMD_10, /* 0xA */ + CMD_11, /* 0xB */ + CMD_12, /* 0xC */ + CMD_13, /* 0xD */ + CMD_14, /* 0xE */ + CMD_15, /* 0xF */ + CMD_20, /* 0x14 */ + CMD_21, /* 0x15 */ + CMD_22, /* 0x16 */ + CMD_23, /* 0x17 */ + NR_IDX_ALL +}; + +/* APIs */ +void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase); +void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, + uint32_t idx, uint32_t cmd_wdata); +uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx); +#endif /* SPM_PMIC_WRAP__H */ + diff --git a/plat/mediatek/mt8183/drivers/spm/spm_suspend.c b/plat/mediatek/mt8183/drivers/spm/spm_suspend.c new file mode 100644 index 000000000..b9ac19f1f --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm_suspend.c @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPM_SYSCLK_SETTLE 99 + +#define WAKE_SRC_FOR_SUSPEND \ + (WAKE_SRC_R12_PCM_TIMER | \ + WAKE_SRC_R12_SSPM_WDT_EVENT_B | \ + WAKE_SRC_R12_KP_IRQ_B | \ + WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B | \ + WAKE_SRC_R12_EINT_EVENT_B | \ + WAKE_SRC_R12_CONN_WDT_IRQ_B | \ + WAKE_SRC_R12_CCIF0_EVENT_B | \ + WAKE_SRC_R12_SSPM_SPM_IRQ_B | \ + WAKE_SRC_R12_SCP_SPM_IRQ_B | \ + WAKE_SRC_R12_SCP_WDT_EVENT_B | \ + WAKE_SRC_R12_USB_CDSC_B | \ + WAKE_SRC_R12_USB_POWERDWN_B | \ + WAKE_SRC_R12_SYS_TIMER_EVENT_B | \ + WAKE_SRC_R12_EINT_EVENT_SECURE_B | \ + WAKE_SRC_R12_CCIF1_EVENT_B | \ + WAKE_SRC_R12_MD2AP_PEER_EVENT_B | \ + WAKE_SRC_R12_MD1_WDT_B | \ + WAKE_SRC_R12_CLDMA_EVENT_B | \ + WAKE_SRC_R12_SEJ_WDT_GPT_B) + +#define SLP_PCM_FLAGS \ + (SPM_FLAG_DIS_VCORE_DVS | SPM_FLAG_DIS_VCORE_DFS | \ + SPM_FLAG_DIS_ATF_ABORT | SPM_FLAG_DISABLE_MMSYS_DVFS | \ + SPM_FLAG_DIS_INFRA_PDN | SPM_FLAG_SUSPEND_OPTION) + +#define SLP_PCM_FLAGS1 \ + (SPM_FLAG1_DISABLE_MCDSR) + +static const struct pwr_ctrl suspend_ctrl = { + .wake_src = WAKE_SRC_FOR_SUSPEND, + .pcm_flags = SLP_PCM_FLAGS, + .pcm_flags1 = SLP_PCM_FLAGS1, + + /* SPM_AP_STANDBY_CON */ + .wfi_op = 0x1, + .mp0_cputop_idle_mask = 0, + .mp1_cputop_idle_mask = 0, + .mcusys_idle_mask = 0, + .mm_mask_b = 0, + .md_ddr_en_0_dbc_en = 0x1, + .md_ddr_en_1_dbc_en = 0, + .md_mask_b = 0x1, + .sspm_mask_b = 0x1, + .scp_mask_b = 0x1, + .srcclkeni_mask_b = 0x1, + .md_apsrc_1_sel = 0, + .md_apsrc_0_sel = 0, + .conn_ddr_en_dbc_en = 0x1, + .conn_mask_b = 0x1, + .conn_apsrc_sel = 0, + + /* SPM_SRC_REQ */ + .spm_apsrc_req = 0, + .spm_f26m_req = 0, + .spm_infra_req = 0, + .spm_vrf18_req = 0, + .spm_ddren_req = 0, + .spm_rsv_src_req = 0, + .spm_ddren_2_req = 0, + .cpu_md_dvfs_sop_force_on = 0, + + /* SPM_SRC_MASK */ + .csyspwreq_mask = 0x1, + .ccif0_md_event_mask_b = 0x1, + .ccif0_ap_event_mask_b = 0x1, + .ccif1_md_event_mask_b = 0x1, + .ccif1_ap_event_mask_b = 0x1, + .ccif2_md_event_mask_b = 0x1, + .ccif2_ap_event_mask_b = 0x1, + .ccif3_md_event_mask_b = 0x1, + .ccif3_ap_event_mask_b = 0x1, + .md_srcclkena_0_infra_mask_b = 0x1, + .md_srcclkena_1_infra_mask_b = 0, + .conn_srcclkena_infra_mask_b = 0, + .ufs_infra_req_mask_b = 0, + .srcclkeni_infra_mask_b = 0, + .md_apsrc_req_0_infra_mask_b = 0x1, + .md_apsrc_req_1_infra_mask_b = 0x1, + .conn_apsrcreq_infra_mask_b = 0x1, + .ufs_srcclkena_mask_b = 0, + .md_vrf18_req_0_mask_b = 0, + .md_vrf18_req_1_mask_b = 0, + .ufs_vrf18_req_mask_b = 0, + .gce_vrf18_req_mask_b = 0, + .conn_infra_req_mask_b = 0x1, + .gce_apsrc_req_mask_b = 0, + .disp0_apsrc_req_mask_b = 0, + .disp1_apsrc_req_mask_b = 0, + .mfg_req_mask_b = 0, + .vdec_req_mask_b = 0, + + /* SPM_SRC2_MASK */ + .md_ddr_en_0_mask_b = 0x1, + .md_ddr_en_1_mask_b = 0, + .conn_ddr_en_mask_b = 0x1, + .ddren_sspm_apsrc_req_mask_b = 0x1, + .ddren_scp_apsrc_req_mask_b = 0x1, + .disp0_ddren_mask_b = 0x1, + .disp1_ddren_mask_b = 0x1, + .gce_ddren_mask_b = 0x1, + .ddren_emi_self_refresh_ch0_mask_b = 0, + .ddren_emi_self_refresh_ch1_mask_b = 0, + + /* SPM_WAKEUP_EVENT_MASK */ + .spm_wakeup_event_mask = 0xF1782218, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .spm_wakeup_event_ext_mask = 0xFFFFFFFF, + + /* SPM_SRC3_MASK */ + .md_ddr_en_2_0_mask_b = 0x1, + .md_ddr_en_2_1_mask_b = 0, + .conn_ddr_en_2_mask_b = 0x1, + .ddren2_sspm_apsrc_req_mask_b = 0x1, + .ddren2_scp_apsrc_req_mask_b = 0x1, + .disp0_ddren2_mask_b = 0, + .disp1_ddren2_mask_b = 0, + .gce_ddren2_mask_b = 0, + .ddren2_emi_self_refresh_ch0_mask_b = 0, + .ddren2_emi_self_refresh_ch1_mask_b = 0, + + .mp0_cpu0_wfi_en = 0x1, + .mp0_cpu1_wfi_en = 0x1, + .mp0_cpu2_wfi_en = 0x1, + .mp0_cpu3_wfi_en = 0x1, + + .mp1_cpu0_wfi_en = 0x1, + .mp1_cpu1_wfi_en = 0x1, + .mp1_cpu2_wfi_en = 0x1, + .mp1_cpu3_wfi_en = 0x1 +}; + +static uint32_t spm_set_sysclk_settle(void) +{ + mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE); + return mmio_read_32(SPM_CLK_SETTLE); +} + +void go_to_sleep_before_wfi(void) +{ + int cpu = MPIDR_AFFLVL0_VAL(read_mpidr()); + uint32_t settle; + + settle = spm_set_sysclk_settle(); + spm_set_cpu_status(cpu); + spm_set_power_control(&suspend_ctrl); + spm_set_wakeup_event(&suspend_ctrl); + spm_set_pcm_flags(&suspend_ctrl); + spm_send_cpu_wakeup_event(); + spm_set_pcm_wdt(0); + spm_disable_pcm_timer(); + + if (is_infra_pdn(suspend_ctrl.pcm_flags)) + mt_uart_save(); + + if (!mt_console_uart_cg_status()) + console_switch_state(CONSOLE_FLAG_BOOT); + + INFO("cpu%d: \"%s\", wakesrc = 0x%x, pcm_con1 = 0x%x\n", + cpu, spm_get_firmware_version(), suspend_ctrl.wake_src, + mmio_read_32(PCM_CON1)); + INFO("settle = %u, sec = %u, sw_flag = 0x%x 0x%x, src_req = 0x%x\n", + settle, mmio_read_32(PCM_TIMER_VAL) / 32768, + suspend_ctrl.pcm_flags, suspend_ctrl.pcm_flags1, + mmio_read_32(SPM_SRC_REQ)); + + if (!mt_console_uart_cg_status()) + console_switch_state(CONSOLE_FLAG_RUNTIME); +} + +static void go_to_sleep_after_wfi(void) +{ + struct wake_status spm_wakesta; + + if (is_infra_pdn(suspend_ctrl.pcm_flags)) + mt_uart_restore(); + + spm_set_pcm_wdt(0); + spm_get_wakeup_status(&spm_wakesta); + spm_clean_after_wakeup(); + + if (!mt_console_uart_cg_status()) + console_switch_state(CONSOLE_FLAG_BOOT); + + spm_output_wake_reason(&spm_wakesta, "suspend"); + + if (!mt_console_uart_cg_status()) + console_switch_state(CONSOLE_FLAG_RUNTIME); +} + +static void spm_enable_armpll_l(void) +{ + /* power on */ + mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x1); + + /* clear isolation */ + mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x2); + + /* enable pll */ + mmio_setbits_32(ARMPLL_L_CON0, 0x1); + + /* Add 20us delay for turning on PLL */ + udelay(20); +} + +static void spm_disable_armpll_l(void) +{ + /* disable pll */ + mmio_clrbits_32(ARMPLL_L_CON0, 0x1); + + /* isolation */ + mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x2); + + /* power off */ + mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x1); +} + +void spm_system_suspend(void) +{ + spm_disable_armpll_l(); + bcpu_enable(0); + bcpu_sram_enable(0); + spm_lock_get(); + go_to_sleep_before_wfi(); + spm_lock_release(); +} + +void spm_system_suspend_finish(void) +{ + spm_lock_get(); + go_to_sleep_after_wfi(); + spm_lock_release(); + spm_enable_armpll_l(); + bcpu_sram_enable(1); + bcpu_enable(1); +} diff --git a/plat/mediatek/mt8183/drivers/spm/spm_suspend.h b/plat/mediatek/mt8183/drivers/spm/spm_suspend.h new file mode 100644 index 000000000..e127c2e7e --- /dev/null +++ b/plat/mediatek/mt8183/drivers/spm/spm_suspend.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SPM_SUSPEND_H__ +#define __SPM_SUSPEND_H__ + +void spm_system_suspend(void); +void spm_system_suspend_finish(void); + +#endif /* __SPM_SUSPEND_H__*/ diff --git a/plat/mediatek/mt8183/include/plat_debug.h b/plat/mediatek/mt8183/include/plat_debug.h index e51a6ea83..c9d73cc83 100644 --- a/plat/mediatek/mt8183/include/plat_debug.h +++ b/plat/mediatek/mt8183/include/plat_debug.h @@ -24,8 +24,6 @@ #define BIT_CA15M_L2PARITY_EN (1 << 1) #define BIT_CA15M_LASTPC_DIS (1 << 8) -#define MP1_CPUTOP_PWR_CON 0x10006218 - #define MCU_ALL_PWR_ON_CTRL 0x0c530b58 #define PLAT_MTK_CIRCULAR_BUFFER_UNLOCK 0xefab4133 #define PLAT_MTK_CIRCULAR_BUFFER_LOCK 0xefab4134 diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h index dab265b47..766e76659 100644 --- a/plat/mediatek/mt8183/include/platform_def.h +++ b/plat/mediatek/mt8183/include/platform_def.h @@ -41,6 +41,7 @@ #define APMIXEDSYS (IO_PHYS + 0xC000) #define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200) #define ARMPLL_L_CON0 (APMIXEDSYS + 0x210) +#define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c) #define MAINPLL_CON0 (APMIXEDSYS + 0x220) #define CCIPLL_CON0 (APMIXEDSYS + 0x290) @@ -74,6 +75,7 @@ #define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604) #define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0) #define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4) +#define EMI_WFIFO (MCUCFG_BASE + 0x0b5c) /******************************************************************************* * GIC related constants diff --git a/plat/mediatek/mt8183/include/spm.h b/plat/mediatek/mt8183/include/spm.h deleted file mode 100644 index 208d760d6..000000000 --- a/plat/mediatek/mt8183/include/spm.h +++ /dev/null @@ -1,1715 +0,0 @@ -/* - * Copyright (c) 2019, MediaTek Inc. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_H -#define SPM_H - -#define POWERON_CONFIG_EN (SPM_BASE + 0x000) -#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) -#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) -#define SPM_CLK_CON (SPM_BASE + 0x00C) -#define SPM_CLK_SETTLE (SPM_BASE + 0x010) -#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) -#define PCM_CON0 (SPM_BASE + 0x018) -#define PCM_CON1 (SPM_BASE + 0x01C) -#define PCM_IM_PTR (SPM_BASE + 0x020) -#define PCM_IM_LEN (SPM_BASE + 0x024) -#define PCM_REG_DATA_INI (SPM_BASE + 0x028) -#define PCM_PWR_IO_EN (SPM_BASE + 0x02C) -#define PCM_TIMER_VAL (SPM_BASE + 0x030) -#define PCM_WDT_VAL (SPM_BASE + 0x034) -#define PCM_IM_HOST_RW_PTR (SPM_BASE + 0x038) -#define PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03C) -#define PCM_EVENT_VECTOR0 (SPM_BASE + 0x040) -#define PCM_EVENT_VECTOR1 (SPM_BASE + 0x044) -#define PCM_EVENT_VECTOR2 (SPM_BASE + 0x048) -#define PCM_EVENT_VECTOR3 (SPM_BASE + 0x04C) -#define PCM_EVENT_VECTOR4 (SPM_BASE + 0x050) -#define PCM_EVENT_VECTOR5 (SPM_BASE + 0x054) -#define PCM_EVENT_VECTOR6 (SPM_BASE + 0x058) -#define PCM_EVENT_VECTOR7 (SPM_BASE + 0x05C) -#define PCM_EVENT_VECTOR8 (SPM_BASE + 0x060) -#define PCM_EVENT_VECTOR9 (SPM_BASE + 0x064) -#define PCM_EVENT_VECTOR10 (SPM_BASE + 0x068) -#define PCM_EVENT_VECTOR11 (SPM_BASE + 0x06C) -#define PCM_EVENT_VECTOR12 (SPM_BASE + 0x070) -#define PCM_EVENT_VECTOR13 (SPM_BASE + 0x074) -#define PCM_EVENT_VECTOR14 (SPM_BASE + 0x078) -#define PCM_EVENT_VECTOR15 (SPM_BASE + 0x07C) -#define PCM_EVENT_VECTOR_EN (SPM_BASE + 0x080) -#define SPM_SWINT (SPM_BASE + 0x08C) -#define SPM_SWINT_SET (SPM_BASE + 0x090) -#define SPM_SWINT_CLR (SPM_BASE + 0x094) -#define SPM_SCP_MAILBOX (SPM_BASE + 0x098) -#define SPM_SCP_IRQ (SPM_BASE + 0x09C) -#define SPM_TWAM_CON (SPM_BASE + 0x0A0) -#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4) -#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8) -#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) -#define SPM_IRQ_MASK (SPM_BASE + 0x0B4) -#define SPM_SRC_REQ (SPM_BASE + 0x0B8) -#define SPM_SRC_MASK (SPM_BASE + 0x0BC) -#define SPM_SRC2_MASK (SPM_BASE + 0x0C0) -#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0C4) -#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0C8) -#define SCP_CLK_CON (SPM_BASE + 0x0D0) -#define PCM_DEBUG_CON (SPM_BASE + 0x0D4) -#define PCM_REG0_DATA (SPM_BASE + 0x100) -#define PCM_REG1_DATA (SPM_BASE + 0x104) -#define PCM_REG2_DATA (SPM_BASE + 0x108) -#define PCM_REG3_DATA (SPM_BASE + 0x10C) -#define PCM_REG4_DATA (SPM_BASE + 0x110) -#define PCM_REG5_DATA (SPM_BASE + 0x114) -#define PCM_REG6_DATA (SPM_BASE + 0x118) -#define PCM_REG7_DATA (SPM_BASE + 0x11C) -#define PCM_REG8_DATA (SPM_BASE + 0x120) -#define PCM_REG9_DATA (SPM_BASE + 0x124) -#define PCM_REG10_DATA (SPM_BASE + 0x128) -#define PCM_REG11_DATA (SPM_BASE + 0x12C) -#define PCM_REG12_DATA (SPM_BASE + 0x130) -#define PCM_REG13_DATA (SPM_BASE + 0x134) -#define PCM_REG14_DATA (SPM_BASE + 0x138) -#define PCM_REG15_DATA (SPM_BASE + 0x13C) -#define PCM_REG12_MASK_B_STA (SPM_BASE + 0x140) -#define PCM_REG12_EXT_DATA (SPM_BASE + 0x144) -#define PCM_REG12_EXT_MASK_B_STA (SPM_BASE + 0x148) -#define PCM_EVENT_REG_STA (SPM_BASE + 0x14C) -#define PCM_TIMER_OUT (SPM_BASE + 0x150) -#define PCM_WDT_OUT (SPM_BASE + 0x154) -#define SPM_IRQ_STA (SPM_BASE + 0x158) -#define SPM_WAKEUP_STA (SPM_BASE + 0x15C) -#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x160) -#define SPM_WAKEUP_MISC (SPM_BASE + 0x164) -#define BUS_PROTECT_RDY (SPM_BASE + 0x168) -#define BUS_PROTECT2_RDY (SPM_BASE + 0x16C) -#define SUBSYS_IDLE_STA (SPM_BASE + 0x170) -#define CPU_IDLE_STA (SPM_BASE + 0x174) -#define PCM_FSM_STA (SPM_BASE + 0x178) -#define PWR_STATUS (SPM_BASE + 0x180) -#define PWR_STATUS_2ND (SPM_BASE + 0x184) -#define CPU_PWR_STATUS (SPM_BASE + 0x188) -#define CPU_PWR_STATUS_2ND (SPM_BASE + 0x18C) -#define PCM_WDT_LATCH_0 (SPM_BASE + 0x190) -#define PCM_WDT_LATCH_1 (SPM_BASE + 0x194) -#define PCM_WDT_LATCH_2 (SPM_BASE + 0x198) -#define DRAMC_DBG_LATCH (SPM_BASE + 0x19C) -#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1A0) -#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1A4) -#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1A8) -#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1AC) -#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1B0) -#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1B4) -#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1B8) -#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1BC) -#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1C0) -#define PCM_WDT_LATCH_3 (SPM_BASE + 0x1C4) -#define SPM_SRC_RDY_STA (SPM_BASE + 0x1D0) -#define MISC_STA (SPM_BASE + 0x1D4) -#define MCU_PWR_CON (SPM_BASE + 0x200) -#define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204) -#define MP0_CPU0_PWR_CON (SPM_BASE + 0x208) -#define MP0_CPU1_PWR_CON (SPM_BASE + 0x20C) -#define MP0_CPU2_PWR_CON (SPM_BASE + 0x210) -#define MP0_CPU3_PWR_CON (SPM_BASE + 0x214) -#define MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218) -#define MP1_CPU0_PWR_CON (SPM_BASE + 0x21C) -#define MP1_CPU1_PWR_CON (SPM_BASE + 0x220) -#define MP1_CPU2_PWR_CON (SPM_BASE + 0x224) -#define MP1_CPU3_PWR_CON (SPM_BASE + 0x228) -#define MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240) -#define MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244) -#define MP0_CPU0_L1_PDN (SPM_BASE + 0x248) -#define MP0_CPU1_L1_PDN (SPM_BASE + 0x24C) -#define MP0_CPU2_L1_PDN (SPM_BASE + 0x250) -#define MP0_CPU3_L1_PDN (SPM_BASE + 0x254) -#define MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258) -#define MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C) -#define MP1_CPU0_L1_PDN (SPM_BASE + 0x260) -#define MP1_CPU1_L1_PDN (SPM_BASE + 0x264) -#define MP1_CPU2_L1_PDN (SPM_BASE + 0x268) -#define MP1_CPU3_L1_PDN (SPM_BASE + 0x26C) -#define CPU_EXT_BUCK_ISO (SPM_BASE + 0x290) -#define DUMMY1_PWR_CON (SPM_BASE + 0x2B0) -#define BYPASS_SPMC (SPM_BASE + 0x2B4) -#define SPMC_DORMANT_ENABLE (SPM_BASE + 0x2B8) -#define ARMPLL_CLK_CON (SPM_BASE + 0x2BC) -#define SPMC_IN_RET (SPM_BASE + 0x2C0) -#define VDE_PWR_CON (SPM_BASE + 0x300) -#define VEN_PWR_CON (SPM_BASE + 0x304) -#define ISP_PWR_CON (SPM_BASE + 0x308) -#define DIS_PWR_CON (SPM_BASE + 0x30C) -#define MJC_PWR_CON (SPM_BASE + 0x310) -#define AUDIO_PWR_CON (SPM_BASE + 0x314) -#define IFR_PWR_CON (SPM_BASE + 0x318) -#define DPY_PWR_CON (SPM_BASE + 0x31C) -#define MD1_PWR_CON (SPM_BASE + 0x320) -#define MD2_PWR_CON (SPM_BASE + 0x324) -#define C2K_PWR_CON (SPM_BASE + 0x328) -#define CONN_PWR_CON (SPM_BASE + 0x32C) -#define VCOREPDN_PWR_CON (SPM_BASE + 0x330) -#define MFG_ASYNC_PWR_CON (SPM_BASE + 0x334) -#define MFG_PWR_CON (SPM_BASE + 0x338) -#define MFG_CORE0_PWR_CON (SPM_BASE + 0x33C) -#define MFG_CORE1_PWR_CON (SPM_BASE + 0x340) -#define CAM_PWR_CON (SPM_BASE + 0x344) -#define SYSRAM_CON (SPM_BASE + 0x350) -#define SYSROM_CON (SPM_BASE + 0x354) -#define SCP_SRAM_CON (SPM_BASE + 0x358) -#define GCPU_SRAM_CON (SPM_BASE + 0x35C) -#define MDSYS_INTF_INFRA_PWR_CON (SPM_BASE + 0x360) -#define MDSYS_INTF_MD1_PWR_CON (SPM_BASE + 0x364) -#define MDSYS_INTF_C2K_PWR_CON (SPM_BASE + 0x368) -#define BSI_TOP_SRAM_CON (SPM_BASE + 0x370) -#define DVFSP_SRAM_CON (SPM_BASE + 0x374) -#define MD_EXT_BUCK_ISO (SPM_BASE + 0x390) -#define DUMMY2_PWR_CON (SPM_BASE + 0x3B0) -#define MD1_OUTPUT_PISO_S_EN_IZ (SPM_BASE + 0x3B4) -#define SPM_DVFS_CON (SPM_BASE + 0x400) -#define SPM_MDBSI_CON (SPM_BASE + 0x404) -#define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x408) -#define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x40C) -#define SPM_BSI_GEN (SPM_BASE + 0x410) -#define SPM_BSI_EN_SR (SPM_BASE + 0x414) -#define SPM_BSI_CLK_SR (SPM_BASE + 0x418) -#define SPM_BSI_D0_SR (SPM_BASE + 0x41C) -#define SPM_BSI_D1_SR (SPM_BASE + 0x420) -#define SPM_BSI_D2_SR (SPM_BASE + 0x424) -#define SPM_AP_SEMA (SPM_BASE + 0x428) -#define SPM_SPM_SEMA (SPM_BASE + 0x42C) -#define AP2MD_CROSS_TRIGGER (SPM_BASE + 0x430) -#define AP_MDSRC_REQ (SPM_BASE + 0x434) -#define SPM2MD_DVFS_CON (SPM_BASE + 0x438) -#define MD2SPM_DVFS_CON (SPM_BASE + 0x43C) -#define DRAMC_DPY_CLK_SW_CON_RSV (SPM_BASE + 0x440) -#define DPY_LP_CON (SPM_BASE + 0x444) -#define CPU_DVFS_REQ (SPM_BASE + 0x448) -#define SPM_PLL_CON (SPM_BASE + 0x44C) -#define SPM_EMI_BW_MODE (SPM_BASE + 0x450) -#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x454) -#define ULPOSC_CON (SPM_BASE + 0x458) -#define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x460) -#define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x464) -#define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x470) -#define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x474) -#define SPM_SEMA_M0 (SPM_BASE + 0x480) -#define SPM_SEMA_M1 (SPM_BASE + 0x484) -#define SPM_SEMA_M2 (SPM_BASE + 0x488) -#define SPM_SEMA_M3 (SPM_BASE + 0x48C) -#define SPM_SEMA_M4 (SPM_BASE + 0x490) -#define SPM_SEMA_M5 (SPM_BASE + 0x494) -#define SPM_SEMA_M6 (SPM_BASE + 0x498) -#define SPM_SEMA_M7 (SPM_BASE + 0x49C) -#define SPM_SEMA_M8 (SPM_BASE + 0x4A0) -#define SPM_SEMA_M9 (SPM_BASE + 0x4A4) -#define SRAM_DREQ_ACK (SPM_BASE + 0x4AC) -#define SRAM_DREQ_CON (SPM_BASE + 0x4B0) -#define SRAM_DREQ_CON_SET (SPM_BASE + 0x4B4) -#define SRAM_DREQ_CON_CLR (SPM_BASE + 0x4B8) -#define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x500) -#define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x504) -#define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x508) -#define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x50C) -#define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x510) -#define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x514) -#define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x518) -#define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x51C) -#define MP0_CPU0_WFI_EN (SPM_BASE + 0x530) -#define MP0_CPU1_WFI_EN (SPM_BASE + 0x534) -#define MP0_CPU2_WFI_EN (SPM_BASE + 0x538) -#define MP0_CPU3_WFI_EN (SPM_BASE + 0x53C) -#define MP1_CPU0_WFI_EN (SPM_BASE + 0x540) -#define MP1_CPU1_WFI_EN (SPM_BASE + 0x544) -#define MP1_CPU2_WFI_EN (SPM_BASE + 0x548) -#define MP1_CPU3_WFI_EN (SPM_BASE + 0x54C) -#define CPU_PTPOD2_CON (SPM_BASE + 0x560) -#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570) -#define ROOT_CORE_ADDR (SPM_BASE + 0x574) -#define CPU_SPARE_CON (SPM_BASE + 0x580) -#define CPU_SPARE_CON_SET (SPM_BASE + 0x584) -#define CPU_SPARE_CON_CLR (SPM_BASE + 0x588) -#define SPM_SW_FLAG (SPM_BASE + 0x600) -#define SPM_SW_DEBUG (SPM_BASE + 0x604) -#define SPM_SW_RSV_0 (SPM_BASE + 0x608) -#define SPM_SW_RSV_1 (SPM_BASE + 0x60C) -#define SPM_SW_RSV_2 (SPM_BASE + 0x610) -#define SPM_SW_RSV_3 (SPM_BASE + 0x614) -#define SPM_SW_RSV_4 (SPM_BASE + 0x618) -#define SPM_SW_RSV_5 (SPM_BASE + 0x61C) -#define SPM_RSV_CON (SPM_BASE + 0x620) -#define SPM_RSV_STA (SPM_BASE + 0x624) -#define SPM_PASR_DPD_0 (SPM_BASE + 0x630) -#define SPM_PASR_DPD_1 (SPM_BASE + 0x634) -#define SPM_PASR_DPD_2 (SPM_BASE + 0x638) -#define SPM_PASR_DPD_3 (SPM_BASE + 0x63C) -#define SPM_SPARE_CON (SPM_BASE + 0x640) -#define SPM_SPARE_CON_SET (SPM_BASE + 0x644) -#define SPM_SPARE_CON_CLR (SPM_BASE + 0x648) -#define SPM_SW_RSV_6 (SPM_BASE + 0x64C) -#define SPM_SW_RSV_7 (SPM_BASE + 0x650) -#define SPM_SW_RSV_8 (SPM_BASE + 0x654) -#define SPM_SW_RSV_9 (SPM_BASE + 0x658) -#define SPM_SW_RSV_10 (SPM_BASE + 0x65C) -#define SPM_SW_RSV_11 (SPM_BASE + 0x660) -#define SPM_SW_RSV_12 (SPM_BASE + 0x664) -#define SPM_SW_RSV_13 (SPM_BASE + 0x668) -#define SPM_SW_RSV_14 (SPM_BASE + 0x66C) -#define SPM_SW_RSV_15 (SPM_BASE + 0x670) -#define SPM_SW_RSV_16 (SPM_BASE + 0x674) -#define SPM_SW_RSV_17 (SPM_BASE + 0x678) -#define SPM_SW_RSV_18 (SPM_BASE + 0x67C) -#define SPM_SW_RSV_19 (SPM_BASE + 0x680) -#define SW_CRTL_EVENT (SPM_BASE + 0x690) - - -#define MP1_CPU3_PWR_STA_MASK (1U << 19) -#define MP1_CPU2_PWR_STA_MASK (1U << 18) -#define MP1_CPU1_PWR_STA_MASK (1U << 17) -#define MP1_CPU0_PWR_STA_MASK (1U << 16) -#define MP1_CPUTOP_PWR_STA_MASK (1U << 15) -#define MCU_PWR_STA_MASK (1U << 14) -#define MP0_CPU3_PWR_STA_MASK (1U << 12) -#define MP0_CPU2_PWR_STA_MASK (1U << 11) -#define MP0_CPU1_PWR_STA_MASK (1U << 10) -#define MP0_CPU0_PWR_STA_MASK (1U << 9) -#define MP0_CPUTOP_PWR_STA_MASK (1U << 8) - - -#define MP1_CPU3_STANDBYWFI (1U << 17) -#define MP1_CPU2_STANDBYWFI (1U << 16) -#define MP1_CPU1_STANDBYWFI (1U << 15) -#define MP1_CPU0_STANDBYWFI (1U << 14) -#define MP0_CPU3_STANDBYWFI (1U << 13) -#define MP0_CPU2_STANDBYWFI (1U << 12) -#define MP0_CPU1_STANDBYWFI (1U << 11) -#define MP0_CPU0_STANDBYWFI (1U << 10) - -#define MP0_SPMC_SRAM_DORMANT_EN (1<<0) -#define MP1_SPMC_SRAM_DORMANT_EN (1<<1) -#define MP2_SPMC_SRAM_DORMANT_EN (1<<2) - -/* POWERON_CONFIG_EN (0x10006000+0x000) */ -#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ -#define PROJECT_CODE_LSB (1U << 16) /* 16b */ - -/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ -#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ - -/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ -#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ - -/* SPM_CLK_CON (0x10006000+0x00C) */ -#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ -#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ -#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ -#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ -#define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ -#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ -#define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */ -#define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ -#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ -#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ -#define SRCLKEN1_EN_LSB (1U << 14) /* 1b */ -#define SCP_DCM_EN_LSB (1U << 15) /* 1b */ -#define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */ -#define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */ - -/* SPM_CLK_SETTLE (0x10006000+0x010) */ -#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ - -/* SPM_AP_STANDBY_CON (0x10006000+0x014) */ -#define WFI_OP_LSB (1U << 0) /* 1b */ -#define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */ -#define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ -#define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ -#define MM_MASK_B_LSB (1U << 16) /* 2b */ -#define MD_DDR_EN_DBC_EN_LSB (1U << 18) /* 1b */ -#define MD_MASK_B_LSB (1U << 19) /* 2b */ -#define SCP_MASK_B_LSB (1U << 21) /* 1b */ -#define LTE_MASK_B_LSB (1U << 22) /* 1b */ -#define SRCCLKENI_MASK_B_LSB (1U << 23) /* 1b */ -#define MD_APSRC_1_SEL_LSB (1U << 24) /* 1b */ -#define MD_APSRC_0_SEL_LSB (1U << 25) /* 1b */ -#define CONN_MASK_B_LSB (1U << 26) /* 1b */ -#define CONN_APSRC_SEL_LSB (1U << 27) /* 1b */ - -/* PCM_CON0 (0x10006000+0x018) */ -#define PCM_KICK_L_LSB (1U << 0) /* 1b */ -#define IM_KICK_L_LSB (1U << 1) /* 1b */ -#define PCM_CK_EN_LSB (1U << 2) /* 1b */ -#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ -#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ -#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ -#define PROJECT_CODE_LSB (1U << 16) /* 16b */ - -/* PCM_CON1 (0x10006000+0x01C) */ -#define IM_SLAVE_LSB (1U << 0) /* 1b */ -#define IM_SLEEP_LSB (1U << 1) /* 1b */ -#define MIF_APBEN_LSB (1U << 3) /* 1b */ -#define IM_PDN_LSB (1U << 4) /* 1b */ -#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ -#define IM_NONRP_EN_LSB (1U << 6) /* 1b */ -#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ -#define PCM_WDT_EN_LSB (1U << 8) /* 1b */ -#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ -#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ -#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ -#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ -#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ -#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ -#define PROJECT_CODE_LSB (1U << 16) /* 16b */ - -/* PCM_IM_PTR (0x10006000+0x020) */ -#define PCM_IM_PTR_LSB (1U << 0) /* 32b */ - -/* PCM_IM_LEN (0x10006000+0x024) */ -#define PCM_IM_LEN_LSB (1U << 0) /* 13b */ - -/* PCM_REG_DATA_INI (0x10006000+0x028) */ -#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ - -/* PCM_PWR_IO_EN (0x10006000+0x02C) */ -#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ -#define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */ - -/* PCM_TIMER_VAL (0x10006000+0x030) */ -#define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_VAL (0x10006000+0x034) */ -#define PCM_WDT_VAL_LSB (1U << 0) /* 32b */ - -/* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */ -#define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */ -#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ -#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ - -/* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */ -#define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */ - -/* PCM_EVENT_VECTOR0 (0x10006000+0x040) */ -#define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR1 (0x10006000+0x044) */ -#define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR2 (0x10006000+0x048) */ -#define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */ -#define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR4 (0x10006000+0x050) */ -#define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR5 (0x10006000+0x054) */ -#define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR6 (0x10006000+0x058) */ -#define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */ -#define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR8 (0x10006000+0x060) */ -#define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR9 (0x10006000+0x064) */ -#define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR10 (0x10006000+0x068) */ -#define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */ -#define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR12 (0x10006000+0x070) */ -#define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR13 (0x10006000+0x074) */ -#define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR14 (0x10006000+0x078) */ -#define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */ -#define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */ -#define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */ -#define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */ -#define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */ - -/* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */ -#define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */ - -/* SPM_SWINT (0x10006000+0x08C) */ -#define SPM_SWINT_LSB (1U << 0) /* 10b */ - -/* SPM_SWINT_SET (0x10006000+0x090) */ -#define SPM_SWINT_SET_LSB (1U << 0) /* 10b */ - -/* SPM_SWINT_CLR (0x10006000+0x094) */ -#define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */ - -/* SPM_SCP_MAILBOX (0x10006000+0x098) */ -#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ - -/* SPM_SCP_IRQ (0x10006000+0x09C) */ -#define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */ -#define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */ - -/* SPM_TWAM_CON (0x10006000+0x0A0) */ -#define TWAM_ENABLE_LSB (1U << 0) /* 1b */ -#define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */ -#define TWAM_SW_RST_LSB (1U << 2) /* 1b */ -#define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */ -#define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */ -#define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */ -#define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */ -#define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */ -#define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */ -#define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */ -#define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */ - -/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ -#define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ -#define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */ - -/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ -#define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */ - -/* SPM_IRQ_MASK (0x10006000+0x0B4) */ -#define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */ -#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ -#define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */ - -/* SPM_SRC_REQ (0x10006000+0x0B8) */ -#define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ -#define SPM_F26M_REQ_LSB (1U << 1) /* 1b */ -#define SPM_LTE_REQ_LSB (1U << 2) /* 1b */ -#define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ -#define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ -#define SPM_DVFS_REQ_LSB (1U << 5) /* 1b */ -#define SPM_DVFS_FORCE_DOWN_LSB (1U << 6) /* 1b */ -#define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */ -#define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */ -#define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */ - -/* SPM_SRC_MASK (0x10006000+0x0BC) */ -#define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */ -#define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */ -#define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */ -#define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */ -#define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */ -#define CCIFMD_MD1_EVENT_MASK_B_LSB (1U << 5) /* 1b */ -#define CCIFMD_MD2_EVENT_MASK_B_LSB (1U << 6) /* 1b */ -#define DSI0_VSYNC_MASK_B_LSB (1U << 7) /* 1b */ -#define DSI1_VSYNC_MASK_B_LSB (1U << 8) /* 1b */ -#define DPI_VSYNC_MASK_B_LSB (1U << 9) /* 1b */ -#define ISP0_VSYNC_MASK_B_LSB (1U << 10) /* 1b */ -#define ISP1_VSYNC_MASK_B_LSB (1U << 11) /* 1b */ -#define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 12) /* 1b */ -#define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 13) /* 1b */ -#define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 14) /* 1b */ -#define MD32_SRCCLKENA_INFRA_MASK_B_LSB (1U << 15) /* 1b */ -#define SRCCLKENI_INFRA_MASK_B_LSB (1U << 16) /* 1b */ -#define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 17) /* 1b */ -#define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 18) /* 1b */ -#define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 19) /* 1b */ -#define MD32_APSRCREQ_INFRA_MASK_B_LSB (1U << 20) /* 1b */ -#define MD_DDR_EN_0_MASK_B_LSB (1U << 21) /* 1b */ -#define MD_DDR_EN_1_MASK_B_LSB (1U << 22) /* 1b */ -#define MD_VRF18_REQ_0_MASK_B_LSB (1U << 23) /* 1b */ -#define MD_VRF18_REQ_1_MASK_B_LSB (1U << 24) /* 1b */ -#define MD1_DVFS_REQ_MASK_LSB (1U << 25) /* 2b */ -#define CPU_DVFS_REQ_MASK_LSB (1U << 27) /* 1b */ -#define EMI_BW_DVFS_REQ_MASK_LSB (1U << 28) /* 1b */ -#define MD_SRCCLKENA_0_DVFS_REQ_MASK_B_LSB (1U << 29) /* 1b */ -#define MD_SRCCLKENA_1_DVFS_REQ_MASK_B_LSB (1U << 30) /* 1b */ -#define CONN_SRCCLKENA_DVFS_REQ_MASK_B_LSB (1U << 31) /* 1b */ - -/* SPM_SRC2_MASK (0x10006000+0x0C0) */ -#define DVFS_HALT_MASK_B_LSB (1U << 0) /* 5b */ -#define VDEC_REQ_MASK_B_LSB (1U << 6) /* 1b */ -#define GCE_REQ_MASK_B_LSB (1U << 7) /* 1b */ -#define CPU_MD_DVFS_REQ_MERGE_MASK_B_LSB (1U << 8) /* 1b */ -#define MD_DDR_EN_DVFS_HALT_MASK_B_LSB (1U << 9) /* 2b */ -#define DSI0_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 11) /* 1b */ -#define DSI1_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 12) /* 1b */ -#define DPI_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 13) /* 1b */ -#define ISP0_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 14) /* 1b */ -#define ISP1_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 15) /* 1b */ -#define CONN_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */ -#define DISP_REQ_MASK_B_LSB (1U << 17) /* 1b */ -#define DISP1_REQ_MASK_B_LSB (1U << 18) /* 1b */ -#define MFG_REQ_MASK_B_LSB (1U << 19) /* 1b */ -#define C2K_PS_RCCIF_WAKE_MASK_B_LSB (1U << 20) /* 1b */ -#define C2K_L1_RCCIF_WAKE_MASK_B_LSB (1U << 21) /* 1b */ -#define PS_C2K_RCCIF_WAKE_MASK_B_LSB (1U << 22) /* 1b */ -#define L1_C2K_RCCIF_WAKE_MASK_B_LSB (1U << 23) /* 1b */ -#define SDIO_ON_DVFS_REQ_MASK_B_LSB (1U << 24) /* 1b */ -#define EMI_BOOST_DVFS_REQ_MASK_B_LSB (1U << 25) /* 1b */ -#define CPU_MD_EMI_DVFS_REQ_PROT_DIS_LSB (1U << 26) /* 1b */ -#define DRAMC_SPCMD_APSRC_REQ_MASK_B_LSB (1U << 27) /* 1b */ - -/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ -#define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ - -/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */ -#define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */ - -/* SCP_CLK_CON (0x10006000+0x0D0) */ -#define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ - -/* PCM_DEBUG_CON (0x10006000+0x0D4) */ -#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ - -/* PCM_REG0_DATA (0x10006000+0x100) */ -#define PCM_REG0_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG1_DATA (0x10006000+0x104) */ -#define PCM_REG1_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG2_DATA (0x10006000+0x108) */ -#define PCM_REG2_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG3_DATA (0x10006000+0x10C) */ -#define PCM_REG3_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG4_DATA (0x10006000+0x110) */ -#define PCM_REG4_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG5_DATA (0x10006000+0x114) */ -#define PCM_REG5_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG6_DATA (0x10006000+0x118) */ -#define PCM_REG6_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG7_DATA (0x10006000+0x11C) */ -#define PCM_REG7_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG8_DATA (0x10006000+0x120) */ -#define PCM_REG8_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG9_DATA (0x10006000+0x124) */ -#define PCM_REG9_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG10_DATA (0x10006000+0x128) */ -#define PCM_REG10_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG11_DATA (0x10006000+0x12C) */ -#define PCM_REG11_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG12_DATA (0x10006000+0x130) */ -#define PCM_REG12_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG13_DATA (0x10006000+0x134) */ -#define PCM_REG13_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG14_DATA (0x10006000+0x138) */ -#define PCM_REG14_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG15_DATA (0x10006000+0x13C) */ -#define PCM_REG15_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG12_MASK_B_STA (0x10006000+0x140) */ -#define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */ - -/* PCM_REG12_EXT_DATA (0x10006000+0x144) */ -#define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */ - -/* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */ -#define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */ - -/* PCM_EVENT_REG_STA (0x10006000+0x14C) */ -#define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */ - -/* PCM_TIMER_OUT (0x10006000+0x150) */ -#define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_OUT (0x10006000+0x154) */ -#define PCM_WDT_OUT_LSB (1U << 0) /* 32b */ - -/* SPM_IRQ_STA (0x10006000+0x158) */ -#define TWAM_IRQ_LSB (1U << 2) /* 1b */ -#define PCM_IRQ_LSB (1U << 3) /* 1b */ -#define SPM_IRQ_SWINT_LSB (1U << 4) /* 10b */ - -/* SPM_WAKEUP_STA (0x10006000+0x15C) */ -#define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */ - -/* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */ -#define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */ - -/* SPM_WAKEUP_MISC (0x10006000+0x164) */ -#define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */ -#define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */ -#define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */ - -/* BUS_PROTECT_RDY (0x10006000+0x168) */ -#define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */ - -/* BUS_PROTECT2_RDY (0x10006000+0x16C) */ -#define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */ - -/* SUBSYS_IDLE_STA (0x10006000+0x170) */ -#define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */ - -/* CPU_IDLE_STA (0x10006000+0x174) */ -#define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */ -#define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */ -#define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */ -#define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */ -#define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */ -#define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */ -#define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */ -#define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */ -#define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */ -#define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */ -#define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */ -#define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */ -#define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */ -#define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */ -#define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */ -#define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */ -#define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */ -#define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */ -#define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */ -#define MCUSYS_IDLE_LSB (1U << 23) /* 1b */ - -/* PCM_FSM_STA (0x10006000+0x178) */ -#define EXEC_INST_OP_LSB (1U << 0) /* 4b */ -#define PC_STATE_LSB (1U << 4) /* 3b */ -#define IM_STATE_LSB (1U << 7) /* 3b */ -#define MASTER_STATE_LSB (1U << 10) /* 5b */ -#define EVENT_FSM_LSB (1U << 15) /* 3b */ -#define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */ -#define PCM_KICK_LSB (1U << 21) /* 1b */ -#define IM_KICK_LSB (1U << 22) /* 1b */ -#define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */ -#define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */ - -/* PWR_STATUS (0x10006000+0x180) */ -#define PWR_STATUS_LSB (1U << 0) /* 32b */ - -/* PWR_STATUS_2ND (0x10006000+0x184) */ -#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ - -/* CPU_PWR_STATUS (0x10006000+0x188) */ -#define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */ - -/* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */ -#define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_LATCH_0 (0x10006000+0x190) */ -#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_LATCH_1 (0x10006000+0x194) */ -#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_LATCH_2 (0x10006000+0x198) */ -#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ - -/* DRAMC_DBG_LATCH (0x10006000+0x19C) */ -#define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */ -#define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */ -#define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */ -#define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */ -#define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */ -#define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */ -#define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */ -#define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */ -#define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */ - -/* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */ -#define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */ - -/* PCM_WDT_LATCH_3 (0x10006000+0x1C4) */ -#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ - -/* SPM_SRC_RDY_STA (0x10006000+0x1D0) */ -#define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */ -#define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */ - -/* MISC_STA (0x10006000+0x1D4) */ -#define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */ - -/* MCU_PWR_CON (0x10006000+0x200) */ -#define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MCU_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MCU_PWR_ON_LSB (1U << 2) /* 1b */ -#define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */ -#define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPU0_PWR_CON (0x10006000+0x208) */ -#define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPU1_PWR_CON (0x10006000+0x20C) */ -#define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPU2_PWR_CON (0x10006000+0x210) */ -#define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPU3_PWR_CON (0x10006000+0x214) */ -#define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */ -#define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP1_CPU0_PWR_CON (0x10006000+0x21C) */ -#define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP1_CPU1_PWR_CON (0x10006000+0x220) */ -#define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP1_CPU2_PWR_CON (0x10006000+0x224) */ -#define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP1_CPU3_PWR_CON (0x10006000+0x228) */ -#define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ -#define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ -#define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ -#define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ -#define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ -#define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ -#define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ - -/* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */ -#define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ -#define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */ -#define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ -#define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ - -/* MP0_CPU0_L1_PDN (0x10006000+0x248) */ -#define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP0_CPU1_L1_PDN (0x10006000+0x24C) */ -#define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP0_CPU2_L1_PDN (0x10006000+0x250) */ -#define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP0_CPU3_L1_PDN (0x10006000+0x254) */ -#define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */ -#define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ -#define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */ -#define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ -#define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPU0_L1_PDN (0x10006000+0x260) */ -#define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPU1_L1_PDN (0x10006000+0x264) */ -#define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPU2_L1_PDN (0x10006000+0x268) */ -#define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* MP1_CPU3_L1_PDN (0x10006000+0x26C) */ -#define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ -#define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ - -/* CPU_EXT_BUCK_ISO (0x10006000+0x290) */ -#define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ -#define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ - -/* DUMMY1_PWR_CON (0x10006000+0x2B0) */ -#define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */ -#define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* BYPASS_SPMC (0x10006000+0x2B4) */ -#define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */ - -/* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */ -#define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */ -#define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */ - -/* ARMPLL_CLK_CON (0x10006000+0x2BC) */ -#define MUXSEL_SC_CCIPLL_LSB (1U << 0) /* 1b */ -#define MUXSEL_SC_ARMPLL1_LSB (1U << 1) /* 1b */ -#define MUXSEL_SC_ARMPLL2_LSB (1U << 2) /* 1b */ -#define REG_SC_ARM_CLK_OFF_LSB (1U << 8) /* 4b */ -#define REG_SC_ARMPLL_OFF_LSB (1U << 12) /* 4b */ -#define REG_SC_ARMPLLOUT_OFF_LSB (1U << 16) /* 4b */ -#define REG_SC_FHC_PAUSE_LSB (1U << 20) /* 4b */ -#define REG_SC_ARMPLL_S_OFF_LSB (1U << 24) /* 4b */ - -/* SPMC_IN_RET (0x10006000+0x2C0) */ -#define SPMC_STATUS_LSB (1U << 0) /* 8b */ - -/* VDE_PWR_CON (0x10006000+0x300) */ -#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ -#define VDE_PWR_ON_LSB (1U << 2) /* 1b */ -#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* VEN_PWR_CON (0x10006000+0x304) */ -#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ -#define VEN_PWR_ON_LSB (1U << 2) /* 1b */ -#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* ISP_PWR_CON (0x10006000+0x308) */ -#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ -#define ISP_PWR_ON_LSB (1U << 2) /* 1b */ -#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* DIS_PWR_CON (0x10006000+0x30C) */ -#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ -#define DIS_PWR_ON_LSB (1U << 2) /* 1b */ -#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* MJC_PWR_CON (0x10006000+0x310) */ -#define MJC_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MJC_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MJC_PWR_ON_LSB (1U << 2) /* 1b */ -#define MJC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MJC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MJC_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define MJC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* AUDIO_PWR_CON (0x10006000+0x314) */ -#define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define AUD_PWR_ISO_LSB (1U << 1) /* 1b */ -#define AUD_PWR_ON_LSB (1U << 2) /* 1b */ -#define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* IFR_PWR_CON (0x10006000+0x318) */ -#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ -#define IFR_PWR_ON_LSB (1U << 2) /* 1b */ -#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* DPY_PWR_CON (0x10006000+0x31C) */ -#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ -#define DPY_PWR_ON_LSB (1U << 2) /* 1b */ -#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* MD1_PWR_CON (0x10006000+0x320) */ -#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MD1_PWR_ON_LSB (1U << 2) /* 1b */ -#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ - -/* MD2_PWR_CON (0x10006000+0x324) */ -#define MD2_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MD2_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MD2_PWR_ON_LSB (1U << 2) /* 1b */ -#define MD2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MD2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MD2_SRAM_PDN_LSB (1U << 8) /* 1b */ - -/* C2K_PWR_CON (0x10006000+0x328) */ -#define C2K_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define C2K_PWR_ISO_LSB (1U << 1) /* 1b */ -#define C2K_PWR_ON_LSB (1U << 2) /* 1b */ -#define C2K_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define C2K_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* CONN_PWR_CON (0x10006000+0x32C) */ -#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ -#define CONN_PWR_ON_LSB (1U << 2) /* 1b */ -#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */ -#define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ - -/* VCOREPDN_PWR_CON (0x10006000+0x330) */ -#define VCOREPDN_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define VCOREPDN_PWR_ISO_LSB (1U << 1) /* 1b */ -#define VCOREPDN_PWR_ON_LSB (1U << 2) /* 1b */ -#define VCOREPDN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define VCOREPDN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* MFG_ASYNC_PWR_CON (0x10006000+0x334) */ -#define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */ -#define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* MFG_PWR_CON (0x10006000+0x338) */ -#define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MFG_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MFG_PWR_ON_LSB (1U << 2) /* 1b */ -#define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MFG_SRAM_PDN_LSB (1U << 8) /* 6b */ -#define MFG_SRAM_PDN_ACK_LSB (1U << 16) /* 6b */ - -/* MFG_CORE0_PWR_CON (0x10006000+0x33C) */ -#define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ -#define MFG_CORE0_ON_2ND_LSB (1U << 3) /* 1b */ -#define MFG_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MFG_CORE0_SRAM_PDN_LSB (1U << 5) /* 1b */ -#define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 6) /* 1b */ - -/* MFG_CORE1_PWR_CON (0x10006000+0x340) */ -#define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ -#define MFG_CORE1_ON_2ND_LSB (1U << 3) /* 1b */ -#define MFG_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */ -#define MFG_CORE1_SRAM_PDN_LSB (1U << 5) /* 1b */ -#define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 6) /* 1b */ - -/* CAM_PWR_CON (0x10006000+0x344) */ -#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ -#define CAM_PWR_ON_LSB (1U << 2) /* 1b */ -#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* SYSRAM_CON (0x10006000+0x350) */ -#define IFR_SRAMROM_SRAM_PDN_LSB (1U << 0) /* 8b */ -#define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 8) /* 8b */ -#define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 16) /* 8b */ -#define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 24) /* 8b */ - -/* SYSROM_CON (0x10006000+0x354) */ -#define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */ - -/* SCP_SRAM_CON (0x10006000+0x358) */ -#define SCP_SRAM_PDN_LSB (1U << 0) /* 1b */ -#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ -#define SCP_SRAM_ISOINT_B_LSB (1U << 8) /* 1b */ - -/* GCPU_SRAM_CON (0x10006000+0x35C) */ -#define GCPU_SRAM_PDN_LSB (1U << 0) /* 4b */ -#define GCPU_SRAM_CKISO_LSB (1U << 4) /* 4b */ -#define GCPU_SRAM_SLEEP_B_LSB (1U << 8) /* 4b */ -#define GCPU_SRAM_ISOINT_B_LSB (1U << 12) /* 4b */ - -/* MDSYS_INTF_INFRA_PWR_CON (0x10006000+0x360) */ -#define MDSYS_INTF_INFRA_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MDSYS_INTF_INFRA_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MDSYS_INTF_INFRA_PWR_ON_LSB (1U << 2) /* 1b */ -#define MDSYS_INTF_INFRA_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MDSYS_INTF_INFRA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* MDSYS_INTF_MD1_PWR_CON (0x10006000+0x364) */ -#define MDSYS_INTF_MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MDSYS_INTF_MD1_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MDSYS_INTF_MD1_PWR_ON_LSB (1U << 2) /* 1b */ -#define MDSYS_INTF_MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MDSYS_INTF_MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* MDSYS_INTF_C2K_PWR_CON (0x10006000+0x368) */ -#define MDSYS_INTF_C2K_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define MDSYS_INTF_C2K_PWR_ISO_LSB (1U << 1) /* 1b */ -#define MDSYS_INTF_C2K_PWR_ON_LSB (1U << 2) /* 1b */ -#define MDSYS_INTF_C2K_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define MDSYS_INTF_C2K_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ - -/* BSI_TOP_SRAM_CON (0x10006000+0x370) */ -#define BSI_TOP_SRAM_PDN_LSB (1U << 0) /* 7b */ -#define BSI_TOP_SRAM_DSLP_LSB (1U << 7) /* 7b */ -#define BSI_TOP_SRAM_SLEEP_B_LSB (1U << 14) /* 7b */ -#define BSI_TOP_SRAM_ISOINT_B_LSB (1U << 21) /* 7b */ -#define BSI_TOP_SRAM_ISO_EN_LSB (1U << 28) /* 2b */ - -/* DVFSP_SRAM_CON (0x10006000+0x374) */ -#define DVFSP_SRAM_PDN_LSB (1U << 0) /* 2b */ -#define DVFSP_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ -#define DVFSP_SRAM_ISOINT_B_LSB (1U << 8) /* 2b */ - -/* MD_EXT_BUCK_ISO (0x10006000+0x390) */ -#define MD_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ - -/* DUMMY2_PWR_CON (0x10006000+0x3B0) */ -#define DUMMY2_PWR_RST_B_LSB (1U << 0) /* 1b */ -#define DUMMY2_PWR_ISO_LSB (1U << 1) /* 1b */ -#define DUMMY2_PWR_ON_LSB (1U << 2) /* 1b */ -#define DUMMY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ -#define DUMMY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ -#define DUMMY2_SRAM_PDN_LSB (1U << 8) /* 4b */ -#define DUMMY2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ - -/* MD1_OUTPUT_PISO_S_EN_IZ (0x10006000+0x3B4) */ -#define MD1_OUTPUT_PISO_S_EN_IZ_LSB (1U << 0) /* 1b */ - -/* SPM_DVFS_CON (0x10006000+0x400) */ -#define SPM_DVFS_CON_LSB (1U << 0) /* 4b */ -#define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */ - -/* SPM_MDBSI_CON (0x10006000+0x404) */ -#define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */ - -/* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */ -#define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */ - -/* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */ -#define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */ - -/* SPM_BSI_GEN (0x10006000+0x410) */ -#define SPM_BSI_START_LSB (1U << 0) /* 1b */ - -/* SPM_BSI_EN_SR (0x10006000+0x414) */ -#define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */ - -/* SPM_BSI_CLK_SR (0x10006000+0x418) */ -#define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */ - -/* SPM_BSI_D0_SR (0x10006000+0x41C) */ -#define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */ - -/* SPM_BSI_D1_SR (0x10006000+0x420) */ -#define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */ - -/* SPM_BSI_D2_SR (0x10006000+0x424) */ -#define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */ - -/* SPM_AP_SEMA (0x10006000+0x428) */ -#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ - -/* SPM_SPM_SEMA (0x10006000+0x42C) */ -#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ - -/* AP2MD_CROSS_TRIGGER (0x10006000+0x430) */ -#define AP2MD_CROSS_TRIGGER_REQ_LSB (1U << 0) /* 1b */ -#define AP2MD_CROSS_TRIGGER_ACK_LSB (1U << 1) /* 1b */ - -/* AP_MDSRC_REQ (0x10006000+0x434) */ -#define AP_MD1SRC_REQ_LSB (1U << 0) /* 1b */ -#define AP_MD2SRC_REQ_LSB (1U << 1) /* 1b */ -#define AP_MD1SRC_ACK_LSB (1U << 4) /* 1b */ -#define AP_MD2SRC_ACK_LSB (1U << 5) /* 1b */ - -/* SPM2MD_DVFS_CON (0x10006000+0x438) */ -#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 16b */ - -/* MD2SPM_DVFS_CON (0x10006000+0x43C) */ -#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 16b */ - -/* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */ -#define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */ -#define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */ -#define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */ -#define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */ -#define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */ -#define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */ -#define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */ - -/* DPY_LP_CON (0x10006000+0x444) */ -#define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */ - -/* CPU_DVFS_REQ (0x10006000+0x448) */ -#define CPU_DVFS_REQ_LSB (1U << 0) /* 16b */ -#define DVFS_HALT_LSB (1U << 16) /* 1b */ -#define MD_DVFS_ERROR_STATUS_LSB (1U << 17) /* 1b */ - -/* SPM_PLL_CON (0x10006000+0x44C) */ -#define SC_MPLLOUT_OFF_LSB (1U << 0) /* 1b */ -#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ -#define SC_MPLL_OFF_LSB (1U << 4) /* 1b */ -#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ -#define SC_MPLL_S_OFF_LSB (1U << 8) /* 1b */ -#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ -#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ -#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */ - -/* SPM_EMI_BW_MODE (0x10006000+0x450) */ -#define EMI_BW_MODE_LSB (1U << 0) /* 1b */ -#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ - -/* AP2MD_PEER_WAKEUP (0x10006000+0x454) */ -#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ - -/* ULPOSC_CON (0x10006000+0x458) */ -#define ULPOSC_EN_LSB (1U << 0) /* 1b */ -#define ULPOSC_RST_LSB (1U << 1) /* 1b */ -#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ - -/* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */ -#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */ -#define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */ -#define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */ -#define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */ -#define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */ -#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */ -#define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */ -#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */ -#define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */ -#define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */ -#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */ -#define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */ -#define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */ -#define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */ -#define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */ -#define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */ - -/* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */ -#define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */ -#define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */ -#define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */ -#define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */ -#define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */ -#define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */ -#define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */ -#define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */ -#define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */ -#define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */ -#define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */ -#define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */ -#define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */ -#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */ -#define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */ - -/* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */ -#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */ -#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */ -#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */ -#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */ -#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */ -#define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */ -#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */ - -/* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */ -#define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */ -#define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */ -#define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */ -#define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */ -#define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */ -#define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */ -#define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */ -#define SPM2MM_ULTRAREQ_LSB (1U << 8) /* 1b */ -#define SPM2MD_ULTRAREQ_LSB (1U << 9) /* 1b */ -#define SPM2MM_ULTRAACK_D2T_LSB (1U << 30) /* 1b */ -#define SPM2MD_ULTRAACK_D2T_LSB (1U << 31) /* 1b */ - -/* SPM_SEMA_M0 (0x10006000+0x480) */ -#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M1 (0x10006000+0x484) */ -#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M2 (0x10006000+0x488) */ -#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M3 (0x10006000+0x48C) */ -#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M4 (0x10006000+0x490) */ -#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M5 (0x10006000+0x494) */ -#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M6 (0x10006000+0x498) */ -#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M7 (0x10006000+0x49C) */ -#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M8 (0x10006000+0x4A0) */ -#define SPM_SEMA_M8_LSB (1U << 0) /* 8b */ - -/* SPM_SEMA_M9 (0x10006000+0x4A4) */ -#define SPM_SEMA_M9_LSB (1U << 0) /* 8b */ - -/* SRAM_DREQ_ACK (0x10006000+0x4AC) */ -#define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */ - -/* SRAM_DREQ_CON (0x10006000+0x4B0) */ -#define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */ - -/* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */ -#define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */ - -/* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */ -#define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */ - -/* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */ -#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ - -/* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */ -#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ - -/* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */ -#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ - -/* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */ -#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ - -/* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */ -#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ - -/* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */ -#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ - -/* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */ -#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ - -/* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */ -#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ -#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ - -/* MP0_CPU0_WFI_EN (0x10006000+0x530) */ -#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP0_CPU1_WFI_EN (0x10006000+0x534) */ -#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP0_CPU2_WFI_EN (0x10006000+0x538) */ -#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP0_CPU3_WFI_EN (0x10006000+0x53C) */ -#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP1_CPU0_WFI_EN (0x10006000+0x540) */ -#define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP1_CPU1_WFI_EN (0x10006000+0x544) */ -#define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP1_CPU2_WFI_EN (0x10006000+0x548) */ -#define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ - -/* MP1_CPU3_WFI_EN (0x10006000+0x54C) */ -#define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ - -/* CPU_PTPOD2_CON (0x10006000+0x560) */ -#define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */ -#define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */ -#define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */ -#define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */ -#define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */ -#define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */ - -/* ROOT_CPUTOP_ADDR (0x10006000+0x570) */ -#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ - -/* ROOT_CORE_ADDR (0x10006000+0x574) */ -#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ - -/* CPU_SPARE_CON (0x10006000+0x580) */ -#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ - -/* CPU_SPARE_CON_SET (0x10006000+0x584) */ -#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ - -/* CPU_SPARE_CON_CLR (0x10006000+0x588) */ -#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ - -/* SPM_SW_FLAG (0x10006000+0x600) */ -#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ - -/* SPM_SW_DEBUG (0x10006000+0x604) */ -#define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_0 (0x10006000+0x608) */ -#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_1 (0x10006000+0x60C) */ -#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_2 (0x10006000+0x610) */ -#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_3 (0x10006000+0x614) */ -#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_4 (0x10006000+0x618) */ -#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_5 (0x10006000+0x61C) */ -#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ - -/* SPM_RSV_CON (0x10006000+0x620) */ -#define SPM_RSV_CON_LSB (1U << 0) /* 16b */ - -/* SPM_RSV_STA (0x10006000+0x624) */ -#define SPM_RSV_STA_LSB (1U << 0) /* 16b */ - -/* SPM_PASR_DPD_0 (0x10006000+0x630) */ -#define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */ - -/* SPM_PASR_DPD_1 (0x10006000+0x634) */ -#define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */ - -/* SPM_PASR_DPD_2 (0x10006000+0x638) */ -#define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */ - -/* SPM_PASR_DPD_3 (0x10006000+0x63C) */ -#define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */ - -/* SPM_SPARE_CON (0x10006000+0x640) */ -#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ - -/* SPM_SPARE_CON_SET (0x10006000+0x644) */ -#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ - -/* SPM_SPARE_CON_CLR (0x10006000+0x648) */ -#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_6 (0x10006000+0x64C) */ -#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_7 (0x10006000+0x650) */ -#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_8 (0x10006000+0x654) */ -#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_9 (0x10006000+0x658) */ -#define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_10 (0x10006000+0x65C) */ -#define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_11 (0x10006000+0x660) */ -#define SPM_SW_RSV_11_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_12 (0x10006000+0x664) */ -#define SPM_SW_RSV_12_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_13 (0x10006000+0x668) */ -#define SPM_SW_RSV_13_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_14 (0x10006000+0x66C) */ -#define SPM_SW_RSV_14_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_15 (0x10006000+0x670) */ -#define SPM_SW_RSV_15_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_16 (0x10006000+0x674) */ -#define SPM_SW_RSV_16_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_17 (0x10006000+0x678) */ -#define SPM_SW_RSV_17_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_18 (0x10006000+0x67C) */ -#define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */ - -/* SPM_SW_RSV_19 (0x10006000+0x680) */ -#define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */ - -/* SW_CRTL_EVENT (0x10006000+0x690) */ -#define SW_CRTL_EVENT_ON_LSB (1U << 0) /* 1b */ - -#define SPM_PROJECT_CODE 0xb16 - -#define SPM_REGWR_EN (1U << 0) -#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) - -#define SPM_CPU_PDN_DIS (1U << 0) -#define SPM_INFRA_PDN_DIS (1U << 1) -#define SPM_DDRPHY_PDN_DIS (1U << 2) -#define SPM_DUALVCORE_PDN_DIS (1U << 3) -#define SPM_PASR_DIS (1U << 4) -#define SPM_DPD_DIS (1U << 5) -#define SPM_SODI_DIS (1U << 6) -#define SPM_MEMPLL_RESET (1U << 7) -#define SPM_MAINPLL_PDN_DIS (1U << 8) -#define SPM_CPU_DVS_DIS (1U << 9) -#define SPM_CPU_DORMANT (1U << 10) -#define SPM_EXT_VSEL_GPIO103 (1U << 11) -#define SPM_DDR_HIGH_SPEED (1U << 12) -#define SPM_OPT (1U << 13) - -#define POWER_ON_VAL1_DEF 0x15820 -#define PCM_FSM_STA_DEF 0x48490 -#define PCM_END_FSM_STA_DEF 0x08490 -#define PCM_END_FSM_STA_MASK 0x3fff0 -#define PCM_HANDSHAKE_SEND1 0xbeefbeef - -#define PCM_WDT_TIMEOUT (30 * 32768) -#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) - -#define CON0_PCM_KICK (1U << 0) -#define CON0_IM_KICK (1U << 1) -#define CON0_IM_SLEEP_DVS (1U << 3) -#define CON0_PCM_SW_RESET (1U << 15) -#define CON0_CFG_KEY (SPM_PROJECT_CODE << 16) - -#define CON1_IM_SLAVE (1U << 0) -#define CON1_MIF_APBEN (1U << 3) -#define CON1_PCM_TIMER_EN (1U << 5) -#define CON1_IM_NONRP_EN (1U << 6) -#define CON1_PCM_WDT_EN (1U << 8) -#define CON1_PCM_WDT_WAKE_MODE (1U << 9) -#define CON1_SPM_SRAM_SLP_B (1U << 10) -#define CON1_SPM_SRAM_ISO_B (1U << 11) -#define CON1_EVENT_LOCK_EN (1U << 12) -#define CON1_CFG_KEY (SPM_PROJECT_CODE << 16) - -#define PCM_PWRIO_EN_R0 (1U << 0) -#define PCM_PWRIO_EN_R7 (1U << 7) -#define PCM_RF_SYNC_R0 (1U << 16) -#define PCM_RF_SYNC_R2 (1U << 18) -#define PCM_RF_SYNC_R6 (1U << 22) -#define PCM_RF_SYNC_R7 (1U << 23) - -#define CC_SYSCLK0_EN_0 (1U << 0) -#define CC_SYSCLK0_EN_1 (1U << 1) -#define CC_SYSCLK1_EN_0 (1U << 2) -#define CC_SYSCLK1_EN_1 (1U << 3) -#define CC_SYSSETTLE_SEL (1U << 4) -#define CC_LOCK_INFRA_DCM (1U << 5) -#define CC_SRCLKENA_MASK_0 (1U << 6) -#define CC_CXO32K_RM_EN_MD1 (1U << 9) -#define CC_CXO32K_RM_EN_MD2 (1U << 10) -#define CC_CLKSQ1_SEL (1U << 12) -#define CC_DISABLE_DORM_PWR (1U << 14) -#define CC_MD32_DCM_EN (1U << 18) - -#define WFI_OP_AND 1 -#define WFI_OP_OR 0 - -#define WAKE_MISC_PCM_TIMER (1U << 19) -#define WAKE_MISC_CPU_WAKE (1U << 20) - -/* define WAKE_SRC_XXX */ -#define WAKE_SRC_SPM_MERGE (1 << 0) -#define WAKE_SRC_KP (1 << 2) -#define WAKE_SRC_WDT (1 << 3) -#define WAKE_SRC_GPT (1 << 4) -#define WAKE_SRC_EINT (1 << 6) -#define WAKE_SRC_LOW_BAT (1 << 9) -#define WAKE_SRC_MD32 (1 << 10) -#define WAKE_SRC_USB_CD (1 << 14) -#define WAKE_SRC_USB_PDN (1 << 15) -#define WAKE_SRC_AFE (1 << 20) -#define WAKE_SRC_THERM (1 << 21) -#define WAKE_SRC_SYSPWREQ (1 << 24) -#define WAKE_SRC_SEJ (1 << 27) -#define WAKE_SRC_ALL_MD32 (1 << 28) -#define WAKE_SRC_CPU_IRQ (1 << 29) - -#define spm_read(addr) mmio_read_32(addr) -#define spm_write(addr, val) mmio_write_32(addr, val) - -#endif /* SPM_H */ diff --git a/plat/mediatek/mt8183/plat_debug.c b/plat/mediatek/mt8183/plat_debug.c index 51816dba1..2f0b67dc0 100644 --- a/plat/mediatek/mt8183/plat_debug.c +++ b/plat/mediatek/mt8183/plat_debug.c @@ -9,6 +9,7 @@ #include #include #include +#include void circular_buffer_setup(void) { diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c index 83c8d4cdc..9e0a92051 100644 --- a/plat/mediatek/mt8183/plat_pm.c +++ b/plat/mediatek/mt8183/plat_pm.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include #define MTK_LOCAL_STATE_OFF 2 @@ -147,6 +149,54 @@ static void __dead2 plat_mtk_system_reset(void) panic(); } +static void plat_mtk_power_domain_suspend(const psci_power_state_t *state) +{ + uint64_t mpidr = read_mpidr(); + int cpu = MPIDR_AFFLVL0_VAL(mpidr); + int cluster = MPIDR_AFFLVL1_VAL(mpidr); + + spm_system_suspend(); + + /* init cpu reset arch as AARCH64 */ + mcucfg_init_archstate(cluster, cpu, 1); + mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); + spm_set_bootaddr(secure_entrypoint); + + /* Prevent interrupts from spuriously waking up this cpu */ + mt_gic_cpuif_disable(); + mt_gic_irq_save(); + + if (state->pwr_domain_state[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF) { + plat_mtk_cci_disable(); + disable_scu(mpidr); + } +} + +static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state) +{ + uint64_t mpidr = read_mpidr(); + + mt_gic_init(); + mt_gic_irq_restore(); + + if (state->pwr_domain_state[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF) { + enable_scu(mpidr); + plat_mtk_cci_enable(); + plat_dcm_restore_cluster_on(mpidr); + } + + mmio_write_32(EMI_WFIFO, 0xf); + spm_system_suspend_finish(); +} + +static void plat_mtk_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + assert(PLAT_MAX_PWR_LVL >= 2); + + for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) + req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; +} + /******************************************************************************* * MTK_platform handler called when an affinity instance is about to be turned * on. The level and mpidr determine the affinity instance. @@ -156,12 +206,12 @@ static const plat_psci_ops_t plat_plat_pm_ops = { .pwr_domain_on = plat_mtk_power_domain_on, .pwr_domain_on_finish = plat_mtk_power_domain_on_finish, .pwr_domain_off = plat_mtk_power_domain_off, - .pwr_domain_suspend = NULL, - .pwr_domain_suspend_finish = NULL, + .pwr_domain_suspend = plat_mtk_power_domain_suspend, + .pwr_domain_suspend_finish = plat_mtk_power_domain_suspend_finish, .system_off = plat_mtk_system_off, .system_reset = plat_mtk_system_reset, .validate_power_state = NULL, - .get_sys_suspend_power_state = NULL, + .get_sys_suspend_power_state = plat_mtk_get_sys_suspend_power_state, }; int plat_setup_psci_ops(uintptr_t sec_entrypoint, diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index 3053a87f5..302b4692f 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -12,6 +12,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/drivers/spmc/ \ -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \ + -I${MTK_PLAT_SOC}/drivers/spm/ \ -I${MTK_PLAT_SOC}/drivers/rtc/ \ -I${MTK_PLAT_SOC}/drivers/uart/ \ -I${MTK_PLAT_SOC}/include/ @@ -47,6 +48,9 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm_pmic_wrap.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ ${MTK_PLAT_SOC}/drivers/uart/uart.c \ ${MTK_PLAT_SOC}/plat_pm.c \ -- cgit v1.2.3 From 9fc34bbd8d804b5a89472b714a55ccfe7931f2ae Mon Sep 17 00:00:00 2001 From: kenny liang Date: Wed, 21 Aug 2019 21:17:49 +0800 Subject: mediatek: mt8183: add MTK SSPM driver Add MTK SSPM driver. Signed-off-by: kenny liang Change-Id: I30dd9a95456b8c3c8d18fd22120824eec97634ee --- plat/mediatek/mt8183/drivers/sspm/sspm.c | 159 +++++++++++++++++++++++++++++++ plat/mediatek/mt8183/drivers/sspm/sspm.h | 32 +++++++ plat/mediatek/mt8183/platform.mk | 4 +- 3 files changed, 194 insertions(+), 1 deletion(-) create mode 100644 plat/mediatek/mt8183/drivers/sspm/sspm.c create mode 100644 plat/mediatek/mt8183/drivers/sspm/sspm.h diff --git a/plat/mediatek/mt8183/drivers/sspm/sspm.c b/plat/mediatek/mt8183/drivers/sspm/sspm.c new file mode 100644 index 000000000..391763818 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/sspm/sspm.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include +#include +#include +#include + +static void memcpy_to_sspm(uint32_t dst, uint32_t *src, uint32_t len) +{ + while (len--) { + mmio_write_32(dst, *src); + dst += sizeof(uint32_t); + src++; + } +} + +static void memcpy_from_sspm(uint32_t *dst, uint32_t src, uint32_t len) +{ + while (len--) { + *dst = mmio_read_32(src); + dst++; + src += sizeof(uint32_t); + } +} + +int sspm_mbox_read(uint32_t slot, uint32_t *data, uint32_t len) +{ + if (slot >= 32) { + ERROR("%s:slot = %d\n", __func__, slot); + return -EINVAL; + } + + if (data) + memcpy_from_sspm(data, + MBOX3_BASE + slot * 4, + len); + + return 0; +} + +int sspm_mbox_write(uint32_t slot, uint32_t *data, uint32_t len) +{ + if (slot >= 32) { + ERROR("%s:slot = %d\n", __func__, slot); + return -EINVAL; + } + + if (data) + memcpy_to_sspm(MBOX3_BASE + slot * 4, + data, + len); + + return 0; +} + +static int sspm_ipi_check_ack(uint32_t id) +{ + int ret = 0; + + if (id == IPI_ID_PLATFORM) { + if ((mmio_read_32(MBOX0_BASE + MBOX_IN_IRQ_OFS) & 0x1) == 0x1) + ret = -EINPROGRESS; + } else if (id == IPI_ID_SUSPEND) { + if ((mmio_read_32(MBOX1_BASE + MBOX_IN_IRQ_OFS) & 0x2) == 0x2) + ret = -EINPROGRESS; + } else { + ERROR("%s: id = %d\n", __func__, id); + ret = -EINVAL; + } + + return ret; +} + +int sspm_ipi_send_non_blocking(uint32_t id, uint32_t *data) +{ + int ret = 0; + + ret = sspm_ipi_check_ack(id); + if (ret) + return ret; + + if (id == IPI_ID_PLATFORM) { + memcpy_to_sspm(MBOX0_BASE + PINR_OFFSET_PLATFORM * 4, + data, + PINR_SIZE_PLATFORM); + dsb(); + mmio_write_32(MBOX0_BASE + MBOX_OUT_IRQ_OFS, 0x1); + } else if (id == IPI_ID_SUSPEND) { + memcpy_to_sspm(MBOX1_BASE + PINR_OFFSET_SUSPEND * 4, + data, + PINR_SIZE_SUSPEND); + dsb(); + mmio_write_32(MBOX1_BASE + MBOX_OUT_IRQ_OFS, + 0x2); + } + + return 0; +} + +int sspm_ipi_recv_non_blocking(uint32_t id, uint32_t *data, uint32_t len) +{ + int ret = 0; + + ret = sspm_ipi_check_ack(id); + if (ret == -EINPROGRESS) { + if (id == IPI_ID_PLATFORM) { + memcpy_from_sspm(data, + MBOX0_BASE + PINR_OFFSET_PLATFORM * 4, + len); + dsb(); + /* clear interrupt bit*/ + mmio_write_32(MBOX0_BASE + MBOX_IN_IRQ_OFS, + 0x1); + ret = 0; + } else if (id == IPI_ID_SUSPEND) { + memcpy_from_sspm(data, + MBOX1_BASE + PINR_OFFSET_SUSPEND * 4, + len); + dsb(); + /* clear interrupt bit*/ + mmio_write_32(MBOX1_BASE + MBOX_IN_IRQ_OFS, + 0x2); + ret = 0; + } + } else if (ret == 0) { + ret = -EBUSY; + } + + return ret; +} + +int sspm_alive_show(void) +{ + uint32_t ipi_data, count; + int ret = 0; + + count = 5; + ipi_data = 0xdead; + + if (sspm_ipi_send_non_blocking(IPI_ID_PLATFORM, &ipi_data) != 0) { + ERROR("sspm init send fail! ret=%d\n", ret); + return -1; + } + + while (sspm_ipi_recv_non_blocking(IPI_ID_PLATFORM, + &ipi_data, + sizeof(ipi_data)) + && count) { + mdelay(100); + count--; + } + + return (ipi_data == 1) ? 0 : -1; +} diff --git a/plat/mediatek/mt8183/drivers/sspm/sspm.h b/plat/mediatek/mt8183/drivers/sspm/sspm.h new file mode 100644 index 000000000..2c2cc10ea --- /dev/null +++ b/plat/mediatek/mt8183/drivers/sspm/sspm.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __SSPM_H__ +#define __SSPM_H__ +/* These should sync with sspm.bin */ +#define IPI_ID_PLATFORM 0 +#define IPI_ID_SUSPEND 6 +#define PINR_OFFSET_PLATFORM 0 +#define PINR_SIZE_PLATFORM 3 +#define PINR_OFFSET_SUSPEND 2 +#define PINR_SIZE_SUSPEND 8 + +#define MBOX0_BASE 0x10450000 +#define MBOX1_BASE 0x10460000 +#define MBOX3_BASE 0x10480000 +#define MBOX_OUT_IRQ_OFS 0x1000 +#define MBOX_IN_IRQ_OFS 0x1004 + +#define SHAREMBOX_OFFSET_MCDI 0 +#define SHAREMBOX_SIZE_MCDI 20 +#define SHAREMBOX_OFFSET_SUSPEND 26 +#define SHAREMBOX_SIZE_SUSPEND 6 + +int sspm_mbox_read(uint32_t slot, uint32_t *data, uint32_t len); +int sspm_mbox_write(uint32_t slot, uint32_t *data, uint32_t len); +int sspm_ipi_send_non_blocking(uint32_t id, uint32_t *data); +int sspm_ipi_recv_non_blocking(uint32_t slot, uint32_t *data, uint32_t len); +int sspm_alive_show(void); +#endif /* __SSPM_H__ */ diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index 302b4692f..5bf504b19 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -13,6 +13,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \ -I${MTK_PLAT_SOC}/drivers/spm/ \ + -I${MTK_PLAT_SOC}/drivers/sspm/ \ -I${MTK_PLAT_SOC}/drivers/rtc/ \ -I${MTK_PLAT_SOC}/drivers/uart/ \ -I${MTK_PLAT_SOC}/include/ @@ -59,7 +60,8 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/plat_dcm.c \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ ${MTK_PLAT_SOC}/plat_debug.c \ - ${MTK_PLAT_SOC}/scu.c + ${MTK_PLAT_SOC}/scu.c \ + ${MTK_PLAT_SOC}/drivers/sspm/sspm.c # Enable workarounds for selected Cortex-A53 erratas. ERRATA_A53_826319 := 0 -- cgit v1.2.3 From 539061b8235f966aef27c0d03a912ede9d16b845 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Wed, 21 Aug 2019 22:49:49 +0800 Subject: mediatek: mt8183: add MTK MCDI driver Add MCDI driver for power saving. Signed-off-by: kenny liang Change-Id: I93ecff4d7581f678be09dd8fb5dfaaccd5f2c22c --- plat/mediatek/mt8183/bl31_plat_setup.c | 2 + plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c | 259 ++++++++++++++ plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h | 34 ++ plat/mediatek/mt8183/include/sspm_reg.h | 41 +++ plat/mediatek/mt8183/plat_pm.c | 502 ++++++++++++++++++++++----- plat/mediatek/mt8183/platform.mk | 2 + 6 files changed, 757 insertions(+), 83 deletions(-) create mode 100644 plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c create mode 100644 plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h create mode 100644 plat/mediatek/mt8183/include/sspm_reg.h diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c index fd3a5b0b7..ec387f4d6 100644 --- a/plat/mediatek/mt8183/bl31_plat_setup.c +++ b/plat/mediatek/mt8183/bl31_plat_setup.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -148,6 +149,7 @@ void bl31_platform_setup(void) spmc_init(); #endif spm_boot_init(); + mcdi_init(); } /******************************************************************************* diff --git a/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c new file mode 100644 index 000000000..29eebcb98 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +static inline uint32_t mcdi_mbox_read(uint32_t id) +{ + return mmio_read_32(SSPM_MBOX_3_BASE + (id << 2)); +} + +static inline void mcdi_mbox_write(uint32_t id, uint32_t val) +{ + mmio_write_32(SSPM_MBOX_3_BASE + (id << 2), val); +} + +void sspm_set_bootaddr(uint32_t bootaddr) +{ + mcdi_mbox_write(MCDI_MBOX_BOOTADDR, bootaddr); +} + +void sspm_cluster_pwr_off_notify(uint32_t cluster) +{ + mcdi_mbox_write(MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE + cluster, 1); +} + +void sspm_cluster_pwr_on_notify(uint32_t cluster) +{ + mcdi_mbox_write(MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE + cluster, 0); +} + +void sspm_standbywfi_irq_enable(uint32_t cpu_idx) +{ + mmio_write_32(SSPM_CFGREG_ACAO_INT_SET, STANDBYWFI_EN(cpu_idx)); +} + +uint32_t mcdi_avail_cpu_mask_read(void) +{ + return mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK); +} + +uint32_t mcdi_avail_cpu_mask_write(uint32_t mask) +{ + mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, mask); + + return mask; +} + +uint32_t mcdi_avail_cpu_mask_set(uint32_t mask) +{ + uint32_t m; + + m = mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK); + m |= mask; + mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, m); + + return m; +} + +uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask) +{ + uint32_t m; + + m = mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK); + m &= ~mask; + mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, m); + + return m; +} + +uint32_t mcdi_cpu_cluster_pwr_stat_read(void) +{ + return mcdi_mbox_read(MCDI_MBOX_CPU_CLUSTER_PWR_STAT); +} + +#define PAUSE_BIT 1 +#define CLUSTER_OFF_OFS 20 +#define CPU_OFF_OFS 24 +#define CLUSTER_ON_OFS 4 +#define CPU_ON_OFS 8 + +static uint32_t target_mask(int cluster, int cpu_idx, bool on) +{ + uint32_t t = 0; + + if (on) { + if (cluster >= 0) + t |= BIT(cluster + CLUSTER_ON_OFS); + + if (cpu_idx >= 0) + t |= BIT(cpu_idx + CPU_ON_OFS); + } else { + if (cluster >= 0) + t |= BIT(cluster + CLUSTER_OFF_OFS); + + if (cpu_idx >= 0) + t |= BIT(cpu_idx + CPU_OFF_OFS); + } + + return t; +} + +void mcdi_pause_clr(int cluster, int cpu_idx, bool on) +{ + uint32_t tgt = target_mask(cluster, cpu_idx, on); + uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION); + + m &= ~tgt; + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); +} + +void mcdi_pause_set(int cluster, int cpu_idx, bool on) +{ + uint32_t tgt = target_mask(cluster, cpu_idx, on); + uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION); + uint32_t tgtn = target_mask(-1, cpu_idx, !on); + + /* request on and off at the same time to ensure it can be paused */ + m |= tgt | tgtn; + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); + + /* wait pause_ack */ + while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK)) + ; + + /* clear non-requested operation */ + m &= ~tgtn; + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); +} + +void mcdi_pause(void) +{ + uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) | BIT(PAUSE_BIT); + + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); + + /* wait pause_ack */ + while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK)) + ; +} + +void mcdi_unpause(void) +{ + uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) & ~BIT(PAUSE_BIT); + + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); +} + +void mcdi_hotplug_wait_ack(int cluster, int cpu_idx, bool on) +{ + uint32_t tgt = target_mask(cluster, cpu_idx, on); + uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); + + /* wait until ack */ + while (!(ack & tgt)) + ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); +} + +void mcdi_hotplug_clr(int cluster, int cpu_idx, bool on) +{ + uint32_t tgt = target_mask(cluster, cpu_idx, on); + uint32_t tgt_cpu = target_mask(-1, cpu_idx, on); + uint32_t cmd = mcdi_mbox_read(MCDI_MBOX_HP_CMD); + uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); + + if (!(cmd & tgt)) + return; + + /* wait until ack */ + while (!(ack & tgt_cpu)) + ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); + + cmd &= ~tgt; + mcdi_mbox_write(MCDI_MBOX_HP_CMD, cmd); +} + +void mcdi_hotplug_set(int cluster, int cpu_idx, bool on) +{ + uint32_t tgt = target_mask(cluster, cpu_idx, on); + uint32_t tgt_cpu = target_mask(-1, cpu_idx, on); + uint32_t cmd = mcdi_mbox_read(MCDI_MBOX_HP_CMD); + uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); + + if ((cmd & tgt) == tgt) + return; + + /* wait until ack clear */ + while (ack & tgt_cpu) + ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK); + + cmd |= tgt; + mcdi_mbox_write(MCDI_MBOX_HP_CMD, cmd); +} + +bool check_mcdi_ctl_stat(void) +{ + uint32_t clk_regs[] = {0x100010ac, 0x100010c8}; + uint32_t clk_mask[] = {0x00028000, 0x00000018}; + uint32_t tgt = target_mask(0, 0, true); + uint32_t m; + int i; + + /* check clk status */ + for (i = 0; i < ARRAY_SIZE(clk_regs); i++) { + if (mmio_read_32(clk_regs[i]) & clk_mask[i]) { + WARN("mcdi: clk check fail.\n"); + return false; + } + } + + /* check mcdi cmd handling */ + m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) | BIT(PAUSE_BIT); + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); + + i = 500; + while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK) && --i > 0) + udelay(10); + + m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) & ~BIT(PAUSE_BIT); + mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m); + + if (i == 0) { + WARN("mcdi: pause_action fail.\n"); + return false; + } + + /* check mcdi cmd handling */ + if (mcdi_mbox_read(MCDI_MBOX_HP_CMD) || + mcdi_mbox_read(MCDI_MBOX_HP_ACK)) { + WARN("mcdi: hp_cmd fail.\n"); + return false; + } + + mcdi_mbox_write(MCDI_MBOX_HP_CMD, tgt); + + i = 500; + while ((mcdi_mbox_read(MCDI_MBOX_HP_ACK) & tgt) != tgt && --i > 0) + udelay(10); + + mcdi_mbox_write(MCDI_MBOX_HP_CMD, 0); + + if (i == 0) { + WARN("mcdi: hp_ack fail.\n"); + return false; + } + + return true; +} + +void mcdi_init(void) +{ + mcdi_avail_cpu_mask_write(0x01); /* cpu0 default on */ +} diff --git a/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h new file mode 100644 index 000000000..9a40df1ca --- /dev/null +++ b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MTK_MCDI_H__ +#define __MTK_MCDI_H__ + +#include + +void sspm_set_bootaddr(uint32_t bootaddr); +void sspm_standbywfi_irq_enable(uint32_t cpu_idx); +void sspm_cluster_pwr_off_notify(uint32_t cluster); +void sspm_cluster_pwr_on_notify(uint32_t cluster); + +uint32_t mcdi_avail_cpu_mask_read(void); +uint32_t mcdi_avail_cpu_mask_write(uint32_t mask); +uint32_t mcdi_avail_cpu_mask_set(uint32_t mask); +uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask); +uint32_t mcdi_cpu_cluster_pwr_stat_read(void); + +void mcdi_pause(void); +void mcdi_unpause(void); +void mcdi_pause_set(int cluster, int cpu_idx, bool on); +void mcdi_pause_clr(int cluster, int cpu_idx, bool on); +void mcdi_hotplug_set(int cluster, int cpu_idx, bool on); +void mcdi_hotplug_clr(int cluster, int cpu_idx, bool on); +void mcdi_hotplug_wait_ack(int cluster, int cpu_idx, bool on); + +bool check_mcdi_ctl_stat(void); +void mcdi_init(void); + +#endif /* __MTK_MCDI_H__ */ diff --git a/plat/mediatek/mt8183/include/sspm_reg.h b/plat/mediatek/mt8183/include/sspm_reg.h new file mode 100644 index 000000000..3f1ac869c --- /dev/null +++ b/plat/mediatek/mt8183/include/sspm_reg.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SSPM_REG_H__ +#define __SSPM_REG_H__ + +#include "platform_def.h" + +#define SSPM_CFGREG_RSV_RW_REG0 (SSPM_CFGREG_BASE + 0x0100) +#define SSPM_CFGREG_ACAO_INT_SET (SSPM_CFGREG_BASE + 0x00D8) +#define SSPM_CFGREG_ACAO_INT_CLR (SSPM_CFGREG_BASE + 0x00DC) +#define SSPM_CFGREG_ACAO_WAKEUP_EN (SSPM_CFGREG_BASE + 0x0204) + +#define STANDBYWFI_EN(n) (1 << (n + 8)) +#define GIC_IRQOUT_EN(n) (1 << (n + 0)) + +#define NF_MCDI_MBOX 19 +#define MCDI_MBOX_CLUSTER_0_CAN_POWER_OFF 0 +#define MCDI_MBOX_CLUSTER_1_CAN_POWER_OFF 1 +#define MCDI_MBOX_BUCK_POWER_OFF_MASK 2 +#define MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE 3 +#define MCDI_MBOX_CLUSTER_1_ATF_ACTION_DONE 4 +#define MCDI_MBOX_BOOTADDR 5 +#define MCDI_MBOX_PAUSE_ACTION 6 +#define MCDI_MBOX_AVAIL_CPU_MASK 7 +#define MCDI_MBOX_CPU_CLUSTER_PWR_STAT 8 +#define MCDI_MBOX_ACTION_STAT 9 +#define MCDI_MBOX_CLUSTER_0_CNT 10 +#define MCDI_MBOX_CLUSTER_1_CNT 11 +#define MCDI_MBOX_CPU_ISOLATION_MASK 12 +#define MCDI_MBOX_PAUSE_ACK 13 +#define MCDI_MBOX_PENDING_ON_EVENT 14 +#define MCDI_MBOX_PROF_CMD 15 +#define MCDI_MBOX_DRCC_CALI_DONE 16 +#define MCDI_MBOX_HP_CMD 17 +#define MCDI_MBOX_HP_ACK 18 + +#endif /* __SSPM_REG_H__ */ diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c index 9e0a92051..555b3895c 100644 --- a/plat/mediatek/mt8183/plat_pm.c +++ b/plat/mediatek/mt8183/plat_pm.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -27,9 +28,101 @@ #include #include #include +#include #include -#define MTK_LOCAL_STATE_OFF 2 +/* Local power state for power domains in Run state. */ +#define MTK_LOCAL_STATE_RUN 0 +/* Local power state for retention. */ +#define MTK_LOCAL_STATE_RET 1 +/* Local power state for OFF/power-down. */ +#define MTK_LOCAL_STATE_OFF 2 + +#if PSCI_EXTENDED_STATE_ID +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define MTK_LOCAL_PSTATE_WIDTH 4 +#define MTK_LOCAL_PSTATE_MASK ((1 << MTK_LOCAL_PSTATE_WIDTH) - 1) + +/* Macros to construct the composite power state */ + +/* Make composite power state parameter till power level 0 */ + +#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) + +#else /* !PSCI_EXTENDED_STATE_ID */ + +#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) + +#endif /* PSCI_EXTENDED_STATE_ID */ + +/* Make composite power state parameter till power level 1 */ +#define mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl1_state) << MTK_LOCAL_PSTATE_WIDTH) | \ + mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) + +/* Make composite power state parameter till power level 2 */ +#define mtk_make_pwrstate_lvl2( \ + lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl2_state) << (MTK_LOCAL_PSTATE_WIDTH * 2)) | \ + mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) + +#define MTK_PWR_LVL0 0 +#define MTK_PWR_LVL1 1 +#define MTK_PWR_LVL2 2 + +/* Macros to read the MTK power domain state */ +#define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0] +#define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1] +#define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ? \ + (state)->pwr_domain_state[MTK_PWR_LVL2] : 0) + +#if PSCI_EXTENDED_STATE_ID +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +const unsigned int mtk_pm_idle_states[] = { + /* State-id - 0x001 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN, + MTK_LOCAL_STATE_RET, MTK_PWR_LVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x002 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN, + MTK_LOCAL_STATE_OFF, MTK_PWR_LVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x022 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_OFF, + MTK_LOCAL_STATE_OFF, MTK_PWR_LVL1, PSTATE_TYPE_POWERDOWN), +#if PLAT_MAX_PWR_LVL > MTK_PWR_LVL1 + /* State-id - 0x222 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_OFF, MTK_LOCAL_STATE_OFF, + MTK_LOCAL_STATE_OFF, MTK_PWR_LVL2, PSTATE_TYPE_POWERDOWN), +#endif + 0, +}; +#endif + +#define CPU_IDX(cluster, cpu) ((cluster << 2) + cpu) +#define ON true +#define OFF false + +/* Pause MCDI when CPU hotplug */ +static bool HP_SSPM_PAUSE; +/* CPU Hotplug by SSPM */ +static bool HP_SSPM_CTRL = true; +/* Turn off cluster when CPU hotplug off */ +static bool HP_CLUSTER_OFF = true; +/* Turn off cluster when CPU MCDI off */ +static bool MCDI_C2 = true; +/* Enable MCDI */ +static bool MCDI_SSPM = true; static uintptr_t secure_entrypoint; @@ -40,30 +133,171 @@ static void mp1_L2_desel_config(void) dsb(); } +static bool clst_single_pwr(int cluster, int cpu) +{ + uint32_t cpu_mask[2] = {0x00001e00, 0x000f0000}; + uint32_t cpu_pwr_bit[] = {9, 10, 11, 12, 16, 17, 18, 19}; + int my_idx = (cluster << 2) + cpu; + uint32_t pwr_stat = mmio_read_32(0x10006180); + + return !(pwr_stat & (cpu_mask[cluster] & ~BIT(cpu_pwr_bit[my_idx]))); +} + +static bool clst_single_on(int cluster, int cpu) +{ + uint32_t cpu_mask[2] = {0x0f, 0xf0}; + int my_idx = (cluster << 2) + cpu; + uint32_t on_stat = mcdi_avail_cpu_mask_read(); + + return !(on_stat & (cpu_mask[cluster] & ~BIT(my_idx))); +} + +static void plat_cluster_pwrdwn_common(uint64_t mpidr, int cluster) +{ + if (cluster > 0) + mt_gic_sync_dcm_enable(); + + /* Disable coherency */ + plat_mtk_cci_disable(); + disable_scu(mpidr); +} + +static void plat_cluster_pwron_common(uint64_t mpidr, int cluster) +{ + if (cluster > 0) { + l2c_parity_check_setup(); + circular_buffer_setup(); + mp1_L2_desel_config(); + mt_gic_sync_dcm_disable(); + } + + /* Enable coherency */ + enable_scu(mpidr); + plat_mtk_cci_enable(); + /* Enable big core dcm */ + plat_dcm_restore_cluster_on(mpidr); + /* Enable rgu dcm */ + plat_dcm_rgu_enable(); +} + +static void plat_cpu_standby(plat_local_state_t cpu_state) +{ + unsigned int scr; + + scr = read_scr_el3(); + write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); + + isb(); + dsb(); + wfi(); + + write_scr_el3(scr); +} + +static void mcdi_ctrl_before_hotplug_on(int cluster, int cpu) +{ + if (!HP_SSPM_CTRL && HP_SSPM_PAUSE && MCDI_SSPM) { + mcdi_pause_clr(cluster, CPU_IDX(cluster, cpu), OFF); + mcdi_pause_set(cluster, CPU_IDX(cluster, cpu), ON); + } +} + +static void mcdi_ctrl_before_hotplug_off(int cluster, int cpu, bool cluster_off) +{ + if (!HP_SSPM_CTRL && HP_SSPM_PAUSE && MCDI_SSPM) + mcdi_pause_set(cluster_off ? cluster : -1, + CPU_IDX(cluster, cpu), OFF); +} + +static void mcdi_ctrl_cluster_cpu_off(int cluster, int cpu, bool cluster_off) +{ + if (MCDI_SSPM) { + sspm_set_bootaddr(secure_entrypoint); + + sspm_standbywfi_irq_enable(CPU_IDX(cluster, cpu)); + + if (cluster_off) + sspm_cluster_pwr_off_notify(cluster); + else + sspm_cluster_pwr_on_notify(cluster); + } +} + +static void mcdi_ctrl_suspend(void) +{ + if (MCDI_SSPM) + mcdi_pause(); +} + +static void mcdi_ctrl_resume(void) +{ + if (MCDI_SSPM) + mcdi_unpause(); +} + +static void hotplug_ctrl_cluster_on(int cluster, int cpu) +{ + if (HP_SSPM_CTRL && MCDI_SSPM) { + mcdi_hotplug_clr(cluster, CPU_IDX(cluster, cpu), OFF); + mcdi_hotplug_set(cluster, -1, ON); + mcdi_hotplug_wait_ack(cluster, -1, ON); + } else { + /* power on cluster */ + if (!spm_get_cluster_powerstate(cluster)) + spm_poweron_cluster(cluster); + } +} + +static void hotplug_ctrl_cpu_on(int cluster, int cpu) +{ + if (HP_SSPM_CTRL && MCDI_SSPM) + mcdi_hotplug_set(cluster, CPU_IDX(cluster, cpu), ON); + else + spm_poweron_cpu(cluster, cpu); +} + +static void hotplug_ctrl_cpu_on_finish(int cluster, int cpu) +{ + spm_disable_cpu_auto_off(cluster, cpu); + + if (HP_SSPM_CTRL && MCDI_SSPM) + mcdi_hotplug_clr(cluster, CPU_IDX(cluster, cpu), ON); + else if (HP_SSPM_PAUSE && MCDI_SSPM) + mcdi_pause_clr(cluster, CPU_IDX(cluster, cpu), ON); + + mcdi_avail_cpu_mask_set(BIT(CPU_IDX(cluster, cpu))); +} + +static void hotplug_ctrl_cluster_cpu_off(int cluster, int cpu, bool cluster_off) +{ + mcdi_avail_cpu_mask_clr(BIT(CPU_IDX(cluster, cpu))); + + if (HP_SSPM_CTRL && MCDI_SSPM) { + mcdi_hotplug_set(cluster_off ? cluster : -1, + CPU_IDX(cluster, cpu), OFF); + } else { + spm_enable_cpu_auto_off(cluster, cpu); + + if (cluster_off) + spm_enable_cluster_auto_off(cluster); + + spm_set_cpu_power_off(cluster, cpu); + } +} + static int plat_mtk_power_domain_on(unsigned long mpidr) { int cpu = MPIDR_AFFLVL0_VAL(mpidr); int cluster = MPIDR_AFFLVL1_VAL(mpidr); - INFO("%s():%d: mpidr: %lx, c.c: %d.%d\n", - __func__, __LINE__, mpidr, cluster, cpu); - - /* power on cluster */ - if (!spm_get_cluster_powerstate(cluster)) { - spm_poweron_cluster(cluster); - if (cluster == 1) { - l2c_parity_check_setup(); - circular_buffer_setup(); - mp1_L2_desel_config(); - mt_gic_sync_dcm_disable(); - } - } + mcdi_ctrl_before_hotplug_on(cluster, cpu); + hotplug_ctrl_cluster_on(cluster, cpu); /* init cpu reset arch as AARCH64 */ mcucfg_init_archstate(cluster, cpu, 1); mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); - spm_poweron_cpu(cluster, cpu); + hotplug_ctrl_cpu_on(cluster, cpu); return PSCI_E_SUCCESS; } @@ -73,53 +307,189 @@ static void plat_mtk_power_domain_off(const psci_power_state_t *state) uint64_t mpidr = read_mpidr(); int cpu = MPIDR_AFFLVL0_VAL(mpidr); int cluster = MPIDR_AFFLVL1_VAL(mpidr); + const plat_local_state_t *pds = state->pwr_domain_state; + bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); + bool cluster_off = (HP_CLUSTER_OFF && afflvl1 && + clst_single_on(cluster, cpu)); - INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu); - - /* Prevent interrupts from spuriously waking up this cpu */ mt_gic_cpuif_disable(); - spm_enable_cpu_auto_off(cluster, cpu); + if (cluster_off) + plat_cluster_pwrdwn_common(mpidr, cluster); - if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) { - if (cluster == 1) - mt_gic_sync_dcm_enable(); + mcdi_ctrl_before_hotplug_off(cluster, cpu, cluster_off); + hotplug_ctrl_cluster_cpu_off(cluster, cpu, cluster_off); +} - plat_mtk_cci_disable(); - spm_enable_cluster_auto_off(cluster); - } +static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state) +{ + uint64_t mpidr = read_mpidr(); + int cpu = MPIDR_AFFLVL0_VAL(mpidr); + int cluster = MPIDR_AFFLVL1_VAL(mpidr); + const plat_local_state_t *pds = state->pwr_domain_state; + bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); + + if (afflvl1) + plat_cluster_pwron_common(mpidr, cluster); - spm_set_cpu_power_off(cluster, cpu); + mt_gic_pcpu_init(); + mt_gic_cpuif_enable(); + + hotplug_ctrl_cpu_on_finish(cluster, cpu); } -static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state) +static void plat_mtk_power_domain_suspend(const psci_power_state_t *state) { uint64_t mpidr = read_mpidr(); int cpu = MPIDR_AFFLVL0_VAL(mpidr); int cluster = MPIDR_AFFLVL1_VAL(mpidr); + const plat_local_state_t *pds = state->pwr_domain_state; + bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); + bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF); + bool cluster_off = MCDI_C2 && afflvl1 && clst_single_pwr(cluster, cpu); - INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu); + /* init cpu reset arch as AARCH64 */ + mcucfg_init_archstate(cluster, cpu, 1); + mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); + + mt_gic_cpuif_disable(); + mt_gic_irq_save(); + plat_dcm_mcsi_a_backup(); - assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF); + if (cluster_off || afflvl2) + plat_cluster_pwrdwn_common(mpidr, cluster); - if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) { - enable_scu(mpidr); + if (afflvl2) { + spm_data_t spm_d = { .cmd = SPM_SUSPEND }; + uint32_t *d = (uint32_t *)&spm_d; + uint32_t l = sizeof(spm_d) / sizeof(uint32_t); - /* Enable coherency if this cluster was off */ - plat_mtk_cci_enable(); - /* Enable big core dcm if this cluster was on */ - plat_dcm_restore_cluster_on(mpidr); - /* Enable rgu dcm if this cluster was off */ - plat_dcm_rgu_enable(); + mcdi_ctrl_suspend(); + + spm_set_bootaddr(secure_entrypoint); + + if (MCDI_SSPM) + sspm_ipi_send_non_blocking(IPI_ID_SUSPEND, d); + + spm_system_suspend(); + + if (MCDI_SSPM) + while (sspm_ipi_recv_non_blocking(IPI_ID_SUSPEND, d, l)) + ; + } else { + mcdi_ctrl_cluster_cpu_off(cluster, cpu, cluster_off); } +} - spm_disable_cpu_auto_off(cluster, cpu); +static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state) +{ + uint64_t mpidr = read_mpidr(); + int cluster = MPIDR_AFFLVL1_VAL(mpidr); + const plat_local_state_t *pds = state->pwr_domain_state; + bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF); - /* Enable the gic cpu interface */ - mt_gic_pcpu_init(); - mt_gic_cpuif_enable(); + if (afflvl2) { + spm_data_t spm_d = { .cmd = SPM_RESUME }; + uint32_t *d = (uint32_t *)&spm_d; + uint32_t l = sizeof(spm_d) / sizeof(uint32_t); + + mt_gic_init(); + mt_gic_irq_restore(); + mmio_write_32(EMI_WFIFO, 0xf); + + if (MCDI_SSPM) + sspm_ipi_send_non_blocking(IPI_ID_SUSPEND, d); + + spm_system_suspend_finish(); + + if (MCDI_SSPM) + while (sspm_ipi_recv_non_blocking(IPI_ID_SUSPEND, d, l)) + ; + + mcdi_ctrl_resume(); + } + + plat_cluster_pwron_common(mpidr, cluster); + + plat_dcm_mcsi_a_restore(); } +#if PSCI_EXTENDED_STATE_ID + +static int plat_mtk_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int state_id; + int i; + + assert(req_state); + + if (!MCDI_SSPM) + return PSCI_E_INVALID_PARAMS; + + /* + * Currently we are using a linear search for finding the matching + * entry in the idle power state array. This can be made a binary + * search if the number of entries justify the additional complexity. + */ + for (i = 0; !!mtk_pm_idle_states[i]; i++) { + if (power_state == mtk_pm_idle_states[i]) + break; + } + + /* Return error if entry not found in the idle state array */ + if (!mtk_pm_idle_states[i]) + return PSCI_E_INVALID_PARAMS; + + i = 0; + state_id = psci_get_pstate_id(power_state); + + /* Parse the State ID and populate the state info parameter */ + while (state_id) { + req_state->pwr_domain_state[i++] = state_id & + MTK_LOCAL_PSTATE_MASK; + state_id >>= MTK_LOCAL_PSTATE_WIDTH; + } + + return PSCI_E_SUCCESS; +} + +#else /* if !PSCI_EXTENDED_STATE_ID */ + +static int plat_mtk_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int pstate = psci_get_pstate_type(power_state); + int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + int i; + + assert(req_state); + + if (pwr_lvl > PLAT_MAX_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) { + /* + * It's possible to enter standby only on power level 0 + * Ignore any other power level. + */ + if (pwr_lvl != 0) + return PSCI_E_INVALID_PARAMS; + + req_state->pwr_domain_state[MTK_PWR_LVL0] = MTK_LOCAL_STATE_RET; + } else if (!MCDI_SSPM) { + return PSCI_E_INVALID_PARAMS; + } else { + for (i = 0; i <= pwr_lvl; i++) + req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; + } + + return PSCI_E_SUCCESS; +} + +#endif /* PSCI_EXTENDED_STATE_ID */ + /******************************************************************************* * MTK handlers to shutdown/reboot the system ******************************************************************************/ @@ -149,46 +519,6 @@ static void __dead2 plat_mtk_system_reset(void) panic(); } -static void plat_mtk_power_domain_suspend(const psci_power_state_t *state) -{ - uint64_t mpidr = read_mpidr(); - int cpu = MPIDR_AFFLVL0_VAL(mpidr); - int cluster = MPIDR_AFFLVL1_VAL(mpidr); - - spm_system_suspend(); - - /* init cpu reset arch as AARCH64 */ - mcucfg_init_archstate(cluster, cpu, 1); - mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); - spm_set_bootaddr(secure_entrypoint); - - /* Prevent interrupts from spuriously waking up this cpu */ - mt_gic_cpuif_disable(); - mt_gic_irq_save(); - - if (state->pwr_domain_state[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF) { - plat_mtk_cci_disable(); - disable_scu(mpidr); - } -} - -static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state) -{ - uint64_t mpidr = read_mpidr(); - - mt_gic_init(); - mt_gic_irq_restore(); - - if (state->pwr_domain_state[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF) { - enable_scu(mpidr); - plat_mtk_cci_enable(); - plat_dcm_restore_cluster_on(mpidr); - } - - mmio_write_32(EMI_WFIFO, 0xf); - spm_system_suspend_finish(); -} - static void plat_mtk_get_sys_suspend_power_state(psci_power_state_t *req_state) { assert(PLAT_MAX_PWR_LVL >= 2); @@ -202,7 +532,7 @@ static void plat_mtk_get_sys_suspend_power_state(psci_power_state_t *req_state) * on. The level and mpidr determine the affinity instance. ******************************************************************************/ static const plat_psci_ops_t plat_plat_pm_ops = { - .cpu_standby = NULL, + .cpu_standby = plat_cpu_standby, .pwr_domain_on = plat_mtk_power_domain_on, .pwr_domain_on_finish = plat_mtk_power_domain_on_finish, .pwr_domain_off = plat_mtk_power_domain_off, @@ -210,7 +540,7 @@ static const plat_psci_ops_t plat_plat_pm_ops = { .pwr_domain_suspend_finish = plat_mtk_power_domain_suspend_finish, .system_off = plat_mtk_system_off, .system_reset = plat_mtk_system_reset, - .validate_power_state = NULL, + .validate_power_state = plat_mtk_validate_power_state, .get_sys_suspend_power_state = plat_mtk_get_sys_suspend_power_state, }; @@ -219,5 +549,11 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, { *psci_ops = &plat_plat_pm_ops; secure_entrypoint = sec_entrypoint; + + if (!check_mcdi_ctl_stat()) { + HP_SSPM_CTRL = false; + MCDI_SSPM = false; + } + return 0; } diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index 5bf504b19..efa7e9e27 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -9,6 +9,7 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/drivers/ \ + -I${MTK_PLAT_SOC}/drivers/mcdi/ \ -I${MTK_PLAT_SOC}/drivers/spmc/ \ -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \ @@ -48,6 +49,7 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c \ ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ + ${MTK_PLAT_SOC}/drivers/mcdi/mtk_mcdi.c \ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \ ${MTK_PLAT_SOC}/drivers/spm/spm.c \ ${MTK_PLAT_SOC}/drivers/spm/spm_pmic_wrap.c \ -- cgit v1.2.3 From 5cfdfc3c6200e1db3c635341e0a923a1ee9d14d8 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 16 Sep 2019 12:13:49 +0100 Subject: amlogic: scpi: Add support to retrieve chip ID Both kernel and U-Boot use a SMC call to the secure monitor to get the chip ID. This call is translated by BL31 to a call to the SCP to retrieve the ID. Add a new SiP call and the backing SCPI command. Signed-off-by: Carlo Caione Change-Id: Ib128f5645ee92866e7ebbcd550dacd33f573524b --- plat/amlogic/common/aml_scpi.c | 23 +++++++++++++++++++++ plat/amlogic/common/aml_sip_svc.c | 33 +++++++++++++++++++++++++++++++ plat/amlogic/common/include/aml_private.h | 1 + plat/amlogic/gxbb/gxbb_def.h | 1 + plat/amlogic/gxl/gxl_def.h | 1 + 5 files changed, 59 insertions(+) diff --git a/plat/amlogic/common/aml_scpi.c b/plat/amlogic/common/aml_scpi.c index 728bcd061..c8a6772c0 100644 --- a/plat/amlogic/common/aml_scpi.c +++ b/plat/amlogic/common/aml_scpi.c @@ -25,6 +25,7 @@ #define SCPI_CMD_JTAG_SET_STATE 0xC0 #define SCPI_CMD_EFUSE_READ 0xC2 +#define SCPI_CMD_CHIP_ID 0xC6 #define SCPI_CMD_COPY_FW 0xd4 #define SCPI_CMD_SET_FW_ADDR 0xd3 @@ -142,6 +143,28 @@ void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, aml_mhu_secure_message_end(); } +uint32_t aml_scpi_get_chip_id(uint8_t *obuff, uint32_t osize) +{ + uint32_t *response; + size_t resp_size; + + if ((osize != 16) && (osize != 12)) + return 0; + + aml_mhu_secure_message_start(); + aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_CHIP_ID, osize)); + aml_scpi_secure_message_receive((void *)&response, &resp_size); + aml_mhu_secure_message_end(); + + if (!((resp_size == 16) && (osize == 16)) && + !((resp_size == 0) && (osize == 12))) + return 0; + + memcpy((void *)obuff, (const void *)response, osize); + + return osize; +} + static inline void aml_scpi_copy_scp_data(uint8_t *data, size_t len) { void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD; diff --git a/plat/amlogic/common/aml_sip_svc.c b/plat/amlogic/common/aml_sip_svc.c index 8a9b070d8..ab4c01563 100644 --- a/plat/amlogic/common/aml_sip_svc.c +++ b/plat/amlogic/common/aml_sip_svc.c @@ -9,9 +9,39 @@ #include #include #include +#include #include "aml_private.h" +struct aml_cpu_info { + uint32_t version; + uint8_t chip_id[16]; +}; + +static int aml_sip_get_chip_id(uint64_t version) +{ + struct aml_cpu_info *info = (void *)AML_SHARE_MEM_OUTPUT_BASE; + uint32_t size; + + if (version > 2) + return -1; + + memset(info, 0, sizeof(struct aml_cpu_info)); + + if (version == 2) { + info->version = 2; + size = 16; + } else { + info->version = 1; + size = 12; + } + + if (aml_scpi_get_chip_id(info->chip_id, size) == 0) + return -1; + + return 0; +} + /******************************************************************************* * This function is responsible for handling all SiP calls ******************************************************************************/ @@ -47,6 +77,9 @@ static uintptr_t aml_sip_handler(uint32_t smc_fid, aml_scpi_jtag_set_state(AML_JTAG_STATE_OFF, x1); SMC_RET1(handle, 0); + case AML_SM_GET_CHIP_ID: + SMC_RET1(handle, aml_sip_get_chip_id(x1)); + default: ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid); break; diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h index 492374568..724f382fb 100644 --- a/plat/amlogic/common/include/aml_private.h +++ b/plat/amlogic/common/include/aml_private.h @@ -31,6 +31,7 @@ uint32_t aml_scpi_efuse_read(void *dst, uint32_t base, uint32_t size); void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3); void aml_scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); +uint32_t aml_scpi_get_chip_id(uint8_t *obuff, uint32_t osize); /* Peripherals */ void aml_thermal_unknown(void); diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h index 2f6d1d2ae..59d9cc9ac 100644 --- a/plat/amlogic/gxbb/gxbb_def.h +++ b/plat/amlogic/gxbb/gxbb_def.h @@ -106,6 +106,7 @@ #define AML_SM_JTAG_ON U(0x82000040) #define AML_SM_JTAG_OFF U(0x82000041) +#define AML_SM_GET_CHIP_ID U(0x82000044) #define AML_JTAG_STATE_ON U(0) #define AML_JTAG_STATE_OFF U(1) diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h index 6f49ed2b0..1e1a934d8 100644 --- a/plat/amlogic/gxl/gxl_def.h +++ b/plat/amlogic/gxl/gxl_def.h @@ -116,6 +116,7 @@ #define AML_SM_JTAG_ON U(0x82000040) #define AML_SM_JTAG_OFF U(0x82000041) +#define AML_SM_GET_CHIP_ID U(0x82000044) #define AML_JTAG_STATE_ON U(0) #define AML_JTAG_STATE_OFF U(1) -- cgit v1.2.3 From 26d943935345db2210da2cf72a0e381f468a32e1 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 18 Sep 2019 10:12:35 +0100 Subject: amlogic: sha_dma: Move register mappings to platform header The registers location for the SHA DMA driver is not unique for the different platforms. Move the mapping out of the driver and into the platform-specific header. Signed-off-by: Carlo Caione Change-Id: Ice64637844a3cb384b01e466cb8c1cea5f764129 --- drivers/amlogic/crypto/sha_dma.c | 5 +---- plat/amlogic/gxbb/gxbb_def.h | 4 ++++ plat/amlogic/gxl/gxl_def.h | 4 ++++ 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/amlogic/crypto/sha_dma.c b/drivers/amlogic/crypto/sha_dma.c index d48ded987..fceb1c0d3 100644 --- a/drivers/amlogic/crypto/sha_dma.c +++ b/drivers/amlogic/crypto/sha_dma.c @@ -9,10 +9,7 @@ #include #include -#define AML_SHA_DMA_BASE 0xc883e000 - -#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08) -#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18) +#include "aml_private.h" #define ASD_MODE_SHA224 0x7 #define ASD_MODE_SHA256 0x6 diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h index 2f6d1d2ae..2c9262406 100644 --- a/plat/amlogic/gxbb/gxbb_def.h +++ b/plat/amlogic/gxbb/gxbb_def.h @@ -95,6 +95,10 @@ #define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) #define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430) +#define AML_SHA_DMA_BASE UL(0xC883E000) +#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08) +#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18) + /******************************************************************************* * System Monitor Call IDs and arguments ******************************************************************************/ diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h index 6f49ed2b0..ea19338e7 100644 --- a/plat/amlogic/gxl/gxl_def.h +++ b/plat/amlogic/gxl/gxl_def.h @@ -105,6 +105,10 @@ #define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) #define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430) +#define AML_SHA_DMA_BASE UL(0xC883E000) +#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08) +#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18) + /******************************************************************************* * System Monitor Call IDs and arguments ******************************************************************************/ -- cgit v1.2.3 From edcadeb7b83b772ae1d9ff072a960ddf573befc2 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 18 Sep 2019 11:03:10 +0100 Subject: amlogic: makefile: Use PLAT variable when possible To address the file names. Signed-off-by: Carlo Caione Change-Id: Ib79b8dfa032a1db012c5031d47de61e1a16b5f9a --- plat/amlogic/gxbb/platform.mk | 6 +++--- plat/amlogic/gxl/platform.mk | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk index 57167b077..62384d2aa 100644 --- a/plat/amlogic/gxbb/platform.mk +++ b/plat/amlogic/gxbb/platform.mk @@ -22,9 +22,9 @@ GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ drivers/amlogic/console/aarch64/meson_console.S \ - ${AML_PLAT_SOC}/gxbb_bl31_setup.c \ - ${AML_PLAT_SOC}/gxbb_pm.c \ - ${AML_PLAT_SOC}/gxbb_common.c \ + ${AML_PLAT_SOC}/${PLAT}_bl31_setup.c \ + ${AML_PLAT_SOC}/${PLAT}_pm.c \ + ${AML_PLAT_SOC}/${PLAT}_common.c \ ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ ${AML_PLAT_COMMON}/aml_efuse.c \ ${AML_PLAT_COMMON}/aml_mhu.c \ diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk index 2e47670f0..641d177bc 100644 --- a/plat/amlogic/gxl/platform.mk +++ b/plat/amlogic/gxl/platform.mk @@ -25,9 +25,9 @@ GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ drivers/amlogic/console/aarch64/meson_console.S \ - ${AML_PLAT_SOC}/gxl_bl31_setup.c \ - ${AML_PLAT_SOC}/gxl_pm.c \ - ${AML_PLAT_SOC}/gxl_common.c \ + ${AML_PLAT_SOC}/${PLAT}_bl31_setup.c \ + ${AML_PLAT_SOC}/${PLAT}_pm.c \ + ${AML_PLAT_SOC}/${PLAT}_common.c \ ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ ${AML_PLAT_COMMON}/aml_efuse.c \ ${AML_PLAT_COMMON}/aml_mhu.c \ -- cgit v1.2.3 From f8631f51392f0688c70cfd53dc66422404e00e16 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 14 Sep 2019 18:01:16 +0800 Subject: drivers: partition: support different block size The block size of some storage device is 4096-byte long, such as UFS. But PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by PLAT_PARTITION_BLOCK_SIZE. Make it configurable in platform. Signed-off-by: Haojian Zhuang Change-Id: Iada05f7c646d0a0f2c0d3b8545540b3cb7153de3 --- docs/getting_started/porting-guide.rst | 7 +++++++ drivers/partition/gpt.c | 5 +++-- drivers/partition/partition.c | 14 +++++++------- include/drivers/partition/gpt.h | 4 ++-- include/drivers/partition/partition.h | 10 +++++++++- 5 files changed, 28 insertions(+), 12 deletions(-) diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index 5786dd384..97ed1fa43 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -546,6 +546,13 @@ optionally be defined: PLAT_PARTITION_MAX_ENTRIES := 12 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) +- **PLAT_PARTITION_BLOCK_SIZE** + The size of partition block. It could be either 512 bytes or 4096 bytes. + The default value is 512. + `For example, define the build flag in platform.mk`_: + PLAT_PARTITION_BLOCK_SIZE := 4096 + $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) + The following constant is optional. It should be defined to override the default behaviour of the ``assert()`` function (for example, to save memory). diff --git a/drivers/partition/gpt.c b/drivers/partition/gpt.c index 4577f06a2..1b804deef 100644 --- a/drivers/partition/gpt.c +++ b/drivers/partition/gpt.c @@ -52,9 +52,10 @@ int parse_gpt_entry(gpt_entry_t *gpt_entry, partition_entry_t *entry) if (result != 0) { return result; } - entry->start = (uint64_t)gpt_entry->first_lba * PARTITION_BLOCK_SIZE; + entry->start = (uint64_t)gpt_entry->first_lba * + PLAT_PARTITION_BLOCK_SIZE; entry->length = (uint64_t)(gpt_entry->last_lba - gpt_entry->first_lba + 1) * - PARTITION_BLOCK_SIZE; + PLAT_PARTITION_BLOCK_SIZE; return 0; } diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c index 7fdbf5385..68133eaf4 100644 --- a/drivers/partition/partition.c +++ b/drivers/partition/partition.c @@ -15,7 +15,7 @@ #include #include -static uint8_t mbr_sector[PARTITION_BLOCK_SIZE]; +static uint8_t mbr_sector[PLAT_PARTITION_BLOCK_SIZE]; static partition_entry_list_t list; #if LOG_LEVEL >= LOG_LEVEL_VERBOSE @@ -57,15 +57,15 @@ static int load_mbr_header(uintptr_t image_handle, mbr_entry_t *mbr_entry) return result; } result = io_read(image_handle, (uintptr_t)&mbr_sector, - PARTITION_BLOCK_SIZE, &bytes_read); + PLAT_PARTITION_BLOCK_SIZE, &bytes_read); if (result != 0) { WARN("Failed to read data (%i)\n", result); return result; } /* Check MBR boot signature. */ - if ((mbr_sector[PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) || - (mbr_sector[PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) { + if ((mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) || + (mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) { return -ENOENT; } offset = (uintptr_t)&mbr_sector + MBR_PRIMARY_ENTRY_OFFSET; @@ -120,15 +120,15 @@ static int load_mbr_entry(uintptr_t image_handle, mbr_entry_t *mbr_entry, return result; } result = io_read(image_handle, (uintptr_t)&mbr_sector, - PARTITION_BLOCK_SIZE, &bytes_read); + PLAT_PARTITION_BLOCK_SIZE, &bytes_read); if (result != 0) { WARN("Failed to read data (%i)\n", result); return result; } /* Check MBR boot signature. */ - if ((mbr_sector[PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) || - (mbr_sector[PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) { + if ((mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) || + (mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) { return -ENOENT; } offset = (uintptr_t)&mbr_sector + diff --git a/include/drivers/partition/gpt.h b/include/drivers/partition/gpt.h index 3ae160fdc..d923e9535 100644 --- a/include/drivers/partition/gpt.h +++ b/include/drivers/partition/gpt.h @@ -10,9 +10,9 @@ #include #define PARTITION_TYPE_GPT 0xee -#define GPT_HEADER_OFFSET PARTITION_BLOCK_SIZE +#define GPT_HEADER_OFFSET PLAT_PARTITION_BLOCK_SIZE #define GPT_ENTRY_OFFSET (GPT_HEADER_OFFSET + \ - PARTITION_BLOCK_SIZE) + PLAT_PARTITION_BLOCK_SIZE) #define GUID_LEN 16 #define GPT_SIGNATURE "EFI PART" diff --git a/include/drivers/partition/partition.h b/include/drivers/partition/partition.h index d94c7824a..5f6483373 100644 --- a/include/drivers/partition/partition.h +++ b/include/drivers/partition/partition.h @@ -17,7 +17,15 @@ CASSERT(PLAT_PARTITION_MAX_ENTRIES <= 128, assert_plat_partition_max_entries); -#define PARTITION_BLOCK_SIZE 512 +#if !PLAT_PARTITION_BLOCK_SIZE +# define PLAT_PARTITION_BLOCK_SIZE 512 +#endif /* PLAT_PARTITION_BLOCK_SIZE */ + +CASSERT((PLAT_PARTITION_BLOCK_SIZE == 512) || + (PLAT_PARTITION_BLOCK_SIZE == 4096), + assert_plat_partition_block_size); + +#define LEGACY_PARTITION_BLOCK_SIZE 512 #define EFI_NAMELEN 36 -- cgit v1.2.3 From c61cf58fbf4eebaa85de793c012a7b647866a3ed Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 14 Sep 2019 18:43:51 +0800 Subject: hikey960: fix to load FIP by partition table Avoid to load FIP by hacking address. Load it by partition table instead. Signed-off-by: Haojian Zhuang Change-Id: Ib476d024a51e4b9705441a0007d78f9fdf0ca078 --- plat/hisilicon/hikey960/hikey960_bl2_setup.c | 6 +++++ plat/hisilicon/hikey960/hikey960_def.h | 3 --- plat/hisilicon/hikey960/hikey960_io_storage.c | 32 ++++++++++++++++++++++++--- plat/hisilicon/hikey960/hikey960_private.h | 1 + plat/hisilicon/hikey960/platform.mk | 4 ++++ 5 files changed, 40 insertions(+), 6 deletions(-) diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c index fc9ddab0d..35d76921d 100644 --- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #ifdef SPD_opteed @@ -263,6 +264,11 @@ int hikey960_bl2_handle_post_image_load(unsigned int image_id) * This function can be used by the platforms to update/use image * information for given `image_id`. ******************************************************************************/ +int bl2_plat_handle_pre_image_load(unsigned int image_id) +{ + return hikey960_set_fip_addr(image_id, "fip"); +} + int bl2_plat_handle_post_image_load(unsigned int image_id) { return hikey960_bl2_handle_post_image_load(image_id); diff --git a/plat/hisilicon/hikey960/hikey960_def.h b/plat/hisilicon/hikey960/hikey960_def.h index 4ea3acd51..9651d7891 100644 --- a/plat/hisilicon/hikey960/hikey960_def.h +++ b/plat/hisilicon/hikey960/hikey960_def.h @@ -44,9 +44,6 @@ #define PL011_UART_CLK_IN_HZ 19200000 #define UFS_BASE 0 -/* FIP partition */ -#define HIKEY960_FIP_BASE (UFS_BASE + 0x1400000) -#define HIKEY960_FIP_MAX_SIZE (12 << 20) #define HIKEY960_UFS_DESC_BASE 0x20000000 #define HIKEY960_UFS_DESC_SIZE 0x00200000 /* 2MB */ diff --git a/plat/hisilicon/hikey960/hikey960_io_storage.c b/plat/hisilicon/hikey960/hikey960_io_storage.c index a4e83897e..e1c5845fb 100644 --- a/plat/hisilicon/hikey960/hikey960_io_storage.c +++ b/plat/hisilicon/hikey960/hikey960_io_storage.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -36,9 +37,12 @@ static int check_fip(const uintptr_t spec); size_t ufs_read_lun3_blks(int lba, uintptr_t buf, size_t size); size_t ufs_write_lun3_blks(int lba, const uintptr_t buf, size_t size); -static const io_block_spec_t ufs_fip_spec = { - .offset = HIKEY960_FIP_BASE, - .length = HIKEY960_FIP_MAX_SIZE, +static io_block_spec_t ufs_fip_spec; + +static const io_block_spec_t ufs_gpt_spec = { + .offset = 0, + .length = PLAT_PARTITION_BLOCK_SIZE * + (PLAT_PARTITION_MAX_ENTRIES / 4 + 2), }; static const io_block_dev_spec_t ufs_dev_spec = { @@ -199,6 +203,11 @@ static const struct plat_io_policy policies[] = { check_fip }, #endif /* TRUSTED_BOARD_BOOT */ + [GPT_IMAGE_ID] = { + &ufs_dev_handle, + (uintptr_t)&ufs_gpt_spec, + check_ufs + }, }; static int check_ufs(const uintptr_t spec) @@ -253,6 +262,23 @@ void hikey960_io_setup(void) (void)result; } +int hikey960_set_fip_addr(unsigned int image_id, const char *name) +{ + const partition_entry_t *entry; + + if (ufs_fip_spec.length == 0) { + partition_init(GPT_IMAGE_ID); + entry = get_partition_entry(name); + if (entry == NULL) { + ERROR("Could NOT find the %s partition!\n", name); + return -ENOENT; + } + ufs_fip_spec.offset = entry->start; + ufs_fip_spec.length = entry->length; + } + return 0; +} + /* Return an IO device handle and specification which can be used to access * an image. Use this to enforce platform load policy */ diff --git a/plat/hisilicon/hikey960/hikey960_private.h b/plat/hisilicon/hikey960/hikey960_private.h index 9a18dd620..54bf50134 100644 --- a/plat/hisilicon/hikey960/hikey960_private.h +++ b/plat/hisilicon/hikey960/hikey960_private.h @@ -26,6 +26,7 @@ void hikey960_init_mmu_el3(unsigned long total_base, unsigned long coh_limit); void hikey960_io_setup(void); int hikey960_read_boardid(unsigned int *id); +int hikey960_set_fip_addr(unsigned int image_id, const char *name); void hikey960_clk_init(void); void hikey960_pmu_init(void); void hikey960_regulator_enable(void); diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk index 4f2c3c699..6cb53c7b6 100644 --- a/plat/hisilicon/hikey960/platform.mk +++ b/plat/hisilicon/hikey960/platform.mk @@ -22,11 +22,13 @@ COLD_BOOT_SINGLE_CPU := 1 PLAT_PL061_MAX_GPIOS := 176 PROGRAMMABLE_RESET_ADDRESS := 1 ENABLE_SVE_FOR_NS := 0 +PLAT_PARTITION_BLOCK_SIZE := 4096 # Process flags $(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID)) $(eval $(call add_define,CRASH_CONSOLE_BASE)) $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) +$(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) # Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images # in the FIP if the platform requires. @@ -75,6 +77,8 @@ BL2_SOURCES += common/desc_image_load.c \ drivers/io/io_block.c \ drivers/io/io_fip.c \ drivers/io/io_storage.c \ + drivers/partition/gpt.c \ + drivers/partition/partition.c \ drivers/synopsys/ufs/dw_ufs.c \ drivers/ufs/ufs.c \ lib/cpus/aarch64/cortex_a53.S \ -- cgit v1.2.3 From deb330cb3837cddf251cea5d804634ad75d48c19 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 14 Sep 2019 19:18:01 +0800 Subject: hikey: fix to load FIP by partition table. Avoid to load FIP by hacking address. Load it by partition table instead. Signed-off-by: Haojian Zhuang Change-Id: I0283fc2e6e459bff14de19d92db4158e05106ee4 --- plat/hisilicon/hikey/hikey_bl2_setup.c | 5 +++++ plat/hisilicon/hikey/hikey_io_storage.c | 32 +++++++++++++++++++++++++++++--- plat/hisilicon/hikey/hikey_private.h | 2 ++ plat/hisilicon/hikey/include/hikey_def.h | 2 -- plat/hisilicon/hikey/platform.mk | 2 ++ 5 files changed, 38 insertions(+), 5 deletions(-) diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c index 2f96efcdb..96136ec12 100644 --- a/plat/hisilicon/hikey/hikey_bl2_setup.c +++ b/plat/hisilicon/hikey/hikey_bl2_setup.c @@ -114,6 +114,11 @@ uint32_t hikey_get_spsr_for_bl33_entry(void) } #endif /* __aarch64__ */ +int bl2_plat_handle_pre_image_load(unsigned int image_id) +{ + return hikey_set_fip_addr(image_id, "fastboot"); +} + int hikey_bl2_handle_post_image_load(unsigned int image_id) { int err = 0; diff --git a/plat/hisilicon/hikey/hikey_io_storage.c b/plat/hisilicon/hikey/hikey_io_storage.c index 11dd97334..fd610d8c0 100644 --- a/plat/hisilicon/hikey/hikey_io_storage.c +++ b/plat/hisilicon/hikey/hikey_io_storage.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -43,9 +44,12 @@ static uintptr_t fip_dev_handle; static int check_emmc(const uintptr_t spec); static int check_fip(const uintptr_t spec); -static const io_block_spec_t emmc_fip_spec = { - .offset = HIKEY_FIP_BASE, - .length = HIKEY_FIP_MAX_SIZE, +static io_block_spec_t emmc_fip_spec; + +static const io_block_spec_t emmc_gpt_spec = { + .offset = 0, + .length = PLAT_PARTITION_BLOCK_SIZE * + (PLAT_PARTITION_MAX_ENTRIES / 4 + 2), }; static const io_block_dev_spec_t emmc_dev_spec = { @@ -213,6 +217,11 @@ static const struct plat_io_policy policies[] = { check_fip }, #endif /* TRUSTED_BOARD_BOOT */ + [GPT_IMAGE_ID] = { + &emmc_dev_handle, + (uintptr_t)&emmc_gpt_spec, + check_emmc + }, }; static int check_emmc(const uintptr_t spec) @@ -267,6 +276,23 @@ void hikey_io_setup(void) (void)result; } +int hikey_set_fip_addr(unsigned int image_id, const char *name) +{ + const partition_entry_t *entry; + + if (emmc_fip_spec.length == 0) { + partition_init(GPT_IMAGE_ID); + entry = get_partition_entry(name); + if (entry == NULL) { + ERROR("Could NOT find the %s partition!\n", name); + return -ENOENT; + } + emmc_fip_spec.offset = entry->start; + emmc_fip_spec.length = entry->length; + } + return 0; +} + /* Return an IO device handle and specification which can be used to access * an image. Use this to enforce platform load policy */ diff --git a/plat/hisilicon/hikey/hikey_private.h b/plat/hisilicon/hikey/hikey_private.h index d82a0794a..b75bc723d 100644 --- a/plat/hisilicon/hikey/hikey_private.h +++ b/plat/hisilicon/hikey/hikey_private.h @@ -72,4 +72,6 @@ int hikey_write_serialno(struct random_serial_num *serialno); void init_acpu_dvfs(void); +int hikey_set_fip_addr(unsigned int image_id, const char *name); + #endif /* HIKEY_PRIVATE_H */ diff --git a/plat/hisilicon/hikey/include/hikey_def.h b/plat/hisilicon/hikey/include/hikey_def.h index 4fb3e56a1..590700daf 100644 --- a/plat/hisilicon/hikey/include/hikey_def.h +++ b/plat/hisilicon/hikey/include/hikey_def.h @@ -84,8 +84,6 @@ #define HIKEY_BL1_MMC_DATA_SIZE 0x0000B000 #define EMMC_BASE 0 -#define HIKEY_FIP_BASE (EMMC_BASE + (4 << 20)) -#define HIKEY_FIP_MAX_SIZE (8 << 20) #define HIKEY_EMMC_RPMB_BASE (EMMC_BASE + 0) #define HIKEY_EMMC_RPMB_MAX_SIZE (128 << 10) #define HIKEY_EMMC_USERDATA_BASE (EMMC_BASE + 0) diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk index 7fd897cda..fbf743292 100644 --- a/plat/hisilicon/hikey/platform.mk +++ b/plat/hisilicon/hikey/platform.mk @@ -76,6 +76,8 @@ BL2_SOURCES += common/desc_image_load.c \ drivers/io/io_fip.c \ drivers/io/io_storage.c \ drivers/mmc/mmc.c \ + drivers/partition/gpt.c \ + drivers/partition/partition.c \ drivers/synopsys/emmc/dw_mmc.c \ lib/cpus/aarch64/cortex_a53.S \ plat/hisilicon/hikey/aarch64/hikey_helpers.S \ -- cgit v1.2.3 From 301d27d998892c054dec925264f81b11dcd64822 Mon Sep 17 00:00:00 2001 From: Radoslaw Biernacki Date: Thu, 17 May 2018 22:19:11 +0200 Subject: qemu: introducing sub-platforms to qemu platform This commit change the plat/qemu directory structure into: `-- plat `-- qemu |-- common (files shared with all qemu subplatforms) |-- qemu (original qemu platform) |-- qemu_sbsa (new sqemu_sbsa platform) |-- subplat1 `-- subplat2 This opens the possibility of adding new qemu sub-platforms which reuse existing common platform code. The first platform which will leverage new structure will be SBSA platform. Signed-off-by: Radoslaw Biernacki Signed-off-by: Sandrine Bailleux Change-Id: Id0d8133e1fffc1b574b69aa2770ebc02bb837a9b --- plat/qemu/aarch32/plat_helpers.S | 133 ---------- plat/qemu/aarch64/plat_helpers.S | 129 ---------- plat/qemu/common/aarch32/plat_helpers.S | 133 ++++++++++ plat/qemu/common/aarch64/plat_helpers.S | 129 ++++++++++ plat/qemu/common/include/plat_macros.S | 26 ++ plat/qemu/common/qemu_bl1_setup.c | 62 +++++ plat/qemu/common/qemu_bl2_mem_params_desc.c | 151 +++++++++++ plat/qemu/common/qemu_bl2_setup.c | 219 ++++++++++++++++ plat/qemu/common/qemu_bl31_setup.c | 103 ++++++++ plat/qemu/common/qemu_common.c | 142 ++++++++++ plat/qemu/common/qemu_console.c | 23 ++ plat/qemu/common/qemu_gicv2.c | 39 +++ plat/qemu/common/qemu_gicv3.c | 46 ++++ plat/qemu/common/qemu_image_load.c | 34 +++ plat/qemu/common/qemu_io_storage.c | 384 ++++++++++++++++++++++++++++ plat/qemu/common/qemu_pm.c | 227 ++++++++++++++++ plat/qemu/common/qemu_private.h | 36 +++ plat/qemu/common/qemu_rotpk.S | 15 ++ plat/qemu/common/qemu_stack_protector.c | 24 ++ plat/qemu/common/qemu_trusted_boot.c | 36 +++ plat/qemu/common/sp_min/sp_min-qemu.mk | 22 ++ plat/qemu/common/sp_min/sp_min_setup.c | 147 +++++++++++ plat/qemu/common/topology.c | 57 +++++ plat/qemu/include/plat_macros.S | 26 -- plat/qemu/include/platform_def.h | 257 ------------------- plat/qemu/platform.mk | 186 -------------- plat/qemu/qemu/include/platform_def.h | 257 +++++++++++++++++++ plat/qemu/qemu/platform.mk | 190 ++++++++++++++ plat/qemu/qemu_bl1_setup.c | 62 ----- plat/qemu/qemu_bl2_mem_params_desc.c | 151 ----------- plat/qemu/qemu_bl2_setup.c | 219 ---------------- plat/qemu/qemu_bl31_setup.c | 103 -------- plat/qemu/qemu_common.c | 142 ---------- plat/qemu/qemu_console.c | 23 -- plat/qemu/qemu_gicv2.c | 39 --- plat/qemu/qemu_gicv3.c | 46 ---- plat/qemu/qemu_image_load.c | 34 --- plat/qemu/qemu_io_storage.c | 384 ---------------------------- plat/qemu/qemu_pm.c | 227 ---------------- plat/qemu/qemu_private.h | 36 --- plat/qemu/qemu_rotpk.S | 15 -- plat/qemu/qemu_stack_protector.c | 24 -- plat/qemu/qemu_trusted_boot.c | 36 --- plat/qemu/sp_min/sp_min-qemu.mk | 22 -- plat/qemu/sp_min/sp_min_setup.c | 147 ----------- plat/qemu/topology.c | 57 ----- 46 files changed, 2502 insertions(+), 2498 deletions(-) delete mode 100644 plat/qemu/aarch32/plat_helpers.S delete mode 100644 plat/qemu/aarch64/plat_helpers.S create mode 100644 plat/qemu/common/aarch32/plat_helpers.S create mode 100644 plat/qemu/common/aarch64/plat_helpers.S create mode 100644 plat/qemu/common/include/plat_macros.S create mode 100644 plat/qemu/common/qemu_bl1_setup.c create mode 100644 plat/qemu/common/qemu_bl2_mem_params_desc.c create mode 100644 plat/qemu/common/qemu_bl2_setup.c create mode 100644 plat/qemu/common/qemu_bl31_setup.c create mode 100644 plat/qemu/common/qemu_common.c create mode 100644 plat/qemu/common/qemu_console.c create mode 100644 plat/qemu/common/qemu_gicv2.c create mode 100644 plat/qemu/common/qemu_gicv3.c create mode 100644 plat/qemu/common/qemu_image_load.c create mode 100644 plat/qemu/common/qemu_io_storage.c create mode 100644 plat/qemu/common/qemu_pm.c create mode 100644 plat/qemu/common/qemu_private.h create mode 100644 plat/qemu/common/qemu_rotpk.S create mode 100644 plat/qemu/common/qemu_stack_protector.c create mode 100644 plat/qemu/common/qemu_trusted_boot.c create mode 100644 plat/qemu/common/sp_min/sp_min-qemu.mk create mode 100644 plat/qemu/common/sp_min/sp_min_setup.c create mode 100644 plat/qemu/common/topology.c delete mode 100644 plat/qemu/include/plat_macros.S delete mode 100644 plat/qemu/include/platform_def.h delete mode 100644 plat/qemu/platform.mk create mode 100644 plat/qemu/qemu/include/platform_def.h create mode 100644 plat/qemu/qemu/platform.mk delete mode 100644 plat/qemu/qemu_bl1_setup.c delete mode 100644 plat/qemu/qemu_bl2_mem_params_desc.c delete mode 100644 plat/qemu/qemu_bl2_setup.c delete mode 100644 plat/qemu/qemu_bl31_setup.c delete mode 100644 plat/qemu/qemu_common.c delete mode 100644 plat/qemu/qemu_console.c delete mode 100644 plat/qemu/qemu_gicv2.c delete mode 100644 plat/qemu/qemu_gicv3.c delete mode 100644 plat/qemu/qemu_image_load.c delete mode 100644 plat/qemu/qemu_io_storage.c delete mode 100644 plat/qemu/qemu_pm.c delete mode 100644 plat/qemu/qemu_private.h delete mode 100644 plat/qemu/qemu_rotpk.S delete mode 100644 plat/qemu/qemu_stack_protector.c delete mode 100644 plat/qemu/qemu_trusted_boot.c delete mode 100644 plat/qemu/sp_min/sp_min-qemu.mk delete mode 100644 plat/qemu/sp_min/sp_min_setup.c delete mode 100644 plat/qemu/topology.c diff --git a/plat/qemu/aarch32/plat_helpers.S b/plat/qemu/aarch32/plat_helpers.S deleted file mode 100644 index aebcfa78f..000000000 --- a/plat/qemu/aarch32/plat_helpers.S +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - - .globl plat_my_core_pos - .globl plat_get_my_entrypoint - .globl platform_mem_init - .globl plat_qemu_calc_core_pos - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl plat_crash_console_flush - .globl plat_secondary_cold_boot_setup - .globl plat_get_my_entrypoint - .globl plat_is_my_cpu_primary - - -func plat_my_core_pos - ldcopr r0, MPIDR - b plat_qemu_calc_core_pos -endfunc plat_my_core_pos - -/* - * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); - * With this function: CorePos = (ClusterId * 4) + CoreId - */ -func plat_qemu_calc_core_pos - and r1, r0, #MPIDR_CPU_MASK - and r0, r0, #MPIDR_CLUSTER_MASK - add r0, r1, r0, LSR #6 - bx lr -endfunc plat_qemu_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_is_my_cpu_primary (void); - * - * Find out whether the current cpu is the primary - * cpu. - * ----------------------------------------------------- - */ -func plat_is_my_cpu_primary - ldcopr r0, MPIDR - ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - and r0, r1 - cmp r0, #QEMU_PRIMARY_CPU - moveq r0, #1 - movne r0, #0 - bx lr -endfunc plat_is_my_cpu_primary - - /* ----------------------------------------------------- - * void plat_secondary_cold_boot_setup (void); - * - * This function performs any platform specific actions - * needed for a secondary cpu after a cold reset e.g - * mark the cpu's presence, mechanism to place it in a - * holding pen etc. - * ----------------------------------------------------- - */ -func plat_secondary_cold_boot_setup - /* Calculate address of our hold entry */ - bl plat_my_core_pos - lsl r0, r0, #PLAT_QEMU_HOLD_ENTRY_SHIFT - mov_imm r2, PLAT_QEMU_HOLD_BASE - - /* Wait until we have a go */ -poll_mailbox: - ldr r1, [r2, r0] - cmp r1, #0 - beq 1f - mov_imm r0, PLAT_QEMU_TRUSTED_MAILBOX_BASE - ldr r1, [r0] - bx r1 -1: - wfe - b poll_mailbox -endfunc plat_secondary_cold_boot_setup - -func plat_get_my_entrypoint - /* TODO support warm boot */ - mov r0, #0 - bx lr -endfunc plat_get_my_entrypoint - -func platform_mem_init - bx lr -endfunc platform_mem_init - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * Function to initialize the crash console - * without a C Runtime to print crash report. - * Clobber list : x0, x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm r0, PLAT_QEMU_CRASH_UART_BASE - mov_imm r1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ - mov_imm r2, PLAT_QEMU_CONSOLE_BAUDRATE - b console_pl011_core_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(int c) - * Function to print a character on the crash - * console without a C Runtime. - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm r1, PLAT_QEMU_CRASH_UART_BASE - b console_pl011_core_putc -endfunc plat_crash_console_putc - - /* --------------------------------------------- - * int plat_crash_console_flush(int c) - * Function to force a write of all buffered - * data that hasn't been output. - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func plat_crash_console_flush - mov_imm r0, PLAT_QEMU_CRASH_UART_BASE - b console_pl011_core_flush -endfunc plat_crash_console_flush - diff --git a/plat/qemu/aarch64/plat_helpers.S b/plat/qemu/aarch64/plat_helpers.S deleted file mode 100644 index 13a5ee461..000000000 --- a/plat/qemu/aarch64/plat_helpers.S +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - - .globl plat_my_core_pos - .globl plat_get_my_entrypoint - .globl platform_mem_init - .globl plat_qemu_calc_core_pos - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl plat_crash_console_flush - .globl plat_secondary_cold_boot_setup - .globl plat_get_my_entrypoint - .globl plat_is_my_cpu_primary - -func plat_my_core_pos - mrs x0, mpidr_el1 - b plat_qemu_calc_core_pos -endfunc plat_my_core_pos - -/* - * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); - * With this function: CorePos = (ClusterId * 4) + CoreId - */ -func plat_qemu_calc_core_pos - and x1, x0, #MPIDR_CPU_MASK - and x0, x0, #MPIDR_CLUSTER_MASK - add x0, x1, x0, LSR #6 - ret -endfunc plat_qemu_calc_core_pos - - /* ----------------------------------------------------- - * unsigned int plat_is_my_cpu_primary (void); - * - * Find out whether the current cpu is the primary - * cpu. - * ----------------------------------------------------- - */ -func plat_is_my_cpu_primary - mrs x0, mpidr_el1 - and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #QEMU_PRIMARY_CPU - cset w0, eq - ret -endfunc plat_is_my_cpu_primary - - /* ----------------------------------------------------- - * void plat_secondary_cold_boot_setup (void); - * - * This function performs any platform specific actions - * needed for a secondary cpu after a cold reset e.g - * mark the cpu's presence, mechanism to place it in a - * holding pen etc. - * ----------------------------------------------------- - */ -func plat_secondary_cold_boot_setup - /* Calculate address of our hold entry */ - bl plat_my_core_pos - lsl x0, x0, #PLAT_QEMU_HOLD_ENTRY_SHIFT - mov_imm x2, PLAT_QEMU_HOLD_BASE - - /* Wait until we have a go */ -poll_mailbox: - ldr x1, [x2, x0] - cbz x1, 1f - mov_imm x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE - ldr x1, [x0] - br x1 -1: - wfe - b poll_mailbox -endfunc plat_secondary_cold_boot_setup - -func plat_get_my_entrypoint - /* TODO support warm boot */ - mov x0, #0 - ret -endfunc plat_get_my_entrypoint - -func platform_mem_init - ret -endfunc platform_mem_init - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * Function to initialize the crash console - * without a C Runtime to print crash report. - * Clobber list : x0, x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, PLAT_QEMU_CRASH_UART_BASE - mov_imm x1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ - mov_imm x2, PLAT_QEMU_CONSOLE_BAUDRATE - b console_pl011_core_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(int c) - * Function to print a character on the crash - * console without a C Runtime. - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, PLAT_QEMU_CRASH_UART_BASE - b console_pl011_core_putc -endfunc plat_crash_console_putc - - /* --------------------------------------------- - * int plat_crash_console_flush(int c) - * Function to force a write of all buffered - * data that hasn't been output. - * Out : return -1 on error else return 0. - * Clobber list : x0, x1 - * --------------------------------------------- - */ -func plat_crash_console_flush - mov_imm x0, PLAT_QEMU_CRASH_UART_BASE - b console_pl011_core_flush -endfunc plat_crash_console_flush - diff --git a/plat/qemu/common/aarch32/plat_helpers.S b/plat/qemu/common/aarch32/plat_helpers.S new file mode 100644 index 000000000..aebcfa78f --- /dev/null +++ b/plat/qemu/common/aarch32/plat_helpers.S @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + + .globl plat_my_core_pos + .globl plat_get_my_entrypoint + .globl platform_mem_init + .globl plat_qemu_calc_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + + +func plat_my_core_pos + ldcopr r0, MPIDR + b plat_qemu_calc_core_pos +endfunc plat_my_core_pos + +/* + * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); + * With this function: CorePos = (ClusterId * 4) + CoreId + */ +func plat_qemu_calc_core_pos + and r1, r0, #MPIDR_CPU_MASK + and r0, r0, #MPIDR_CLUSTER_MASK + add r0, r1, r0, LSR #6 + bx lr +endfunc plat_qemu_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + ldcopr r0, MPIDR + ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + and r0, r1 + cmp r0, #QEMU_PRIMARY_CPU + moveq r0, #1 + movne r0, #0 + bx lr +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* Calculate address of our hold entry */ + bl plat_my_core_pos + lsl r0, r0, #PLAT_QEMU_HOLD_ENTRY_SHIFT + mov_imm r2, PLAT_QEMU_HOLD_BASE + + /* Wait until we have a go */ +poll_mailbox: + ldr r1, [r2, r0] + cmp r1, #0 + beq 1f + mov_imm r0, PLAT_QEMU_TRUSTED_MAILBOX_BASE + ldr r1, [r0] + bx r1 +1: + wfe + b poll_mailbox +endfunc plat_secondary_cold_boot_setup + +func plat_get_my_entrypoint + /* TODO support warm boot */ + mov r0, #0 + bx lr +endfunc plat_get_my_entrypoint + +func platform_mem_init + bx lr +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm r0, PLAT_QEMU_CRASH_UART_BASE + mov_imm r1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ + mov_imm r2, PLAT_QEMU_CONSOLE_BAUDRATE + b console_pl011_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm r1, PLAT_QEMU_CRASH_UART_BASE + b console_pl011_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush(int c) + * Function to force a write of all buffered + * data that hasn't been output. + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm r0, PLAT_QEMU_CRASH_UART_BASE + b console_pl011_core_flush +endfunc plat_crash_console_flush + diff --git a/plat/qemu/common/aarch64/plat_helpers.S b/plat/qemu/common/aarch64/plat_helpers.S new file mode 100644 index 000000000..13a5ee461 --- /dev/null +++ b/plat/qemu/common/aarch64/plat_helpers.S @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + + .globl plat_my_core_pos + .globl plat_get_my_entrypoint + .globl platform_mem_init + .globl plat_qemu_calc_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_qemu_calc_core_pos +endfunc plat_my_core_pos + +/* + * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); + * With this function: CorePos = (ClusterId * 4) + CoreId + */ +func plat_qemu_calc_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc plat_qemu_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #QEMU_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* Calculate address of our hold entry */ + bl plat_my_core_pos + lsl x0, x0, #PLAT_QEMU_HOLD_ENTRY_SHIFT + mov_imm x2, PLAT_QEMU_HOLD_BASE + + /* Wait until we have a go */ +poll_mailbox: + ldr x1, [x2, x0] + cbz x1, 1f + mov_imm x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE + ldr x1, [x0] + br x1 +1: + wfe + b poll_mailbox +endfunc plat_secondary_cold_boot_setup + +func plat_get_my_entrypoint + /* TODO support warm boot */ + mov x0, #0 + ret +endfunc plat_get_my_entrypoint + +func platform_mem_init + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, PLAT_QEMU_CRASH_UART_BASE + mov_imm x1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ + mov_imm x2, PLAT_QEMU_CONSOLE_BAUDRATE + b console_pl011_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_QEMU_CRASH_UART_BASE + b console_pl011_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush(int c) + * Function to force a write of all buffered + * data that hasn't been output. + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x0, PLAT_QEMU_CRASH_UART_BASE + b console_pl011_core_flush +endfunc plat_crash_console_flush + diff --git a/plat/qemu/common/include/plat_macros.S b/plat/qemu/common/include/plat_macros.S new file mode 100644 index 000000000..b6cdb0714 --- /dev/null +++ b/plat/qemu/common/include/plat_macros.S @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include +#include + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + mov_imm x17, GICC_BASE + mov_imm x16, GICD_BASE + arm_print_gic_regs + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/qemu/common/qemu_bl1_setup.c b/plat/qemu/common/qemu_bl1_setup.c new file mode 100644 index 000000000..67f33273f --- /dev/null +++ b/plat/qemu/common/qemu_bl1_setup.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include + +#include "qemu_private.h" + +/* Data structure which holds the extents of the trusted SRAM for BL1*/ +static meminfo_t bl1_tzram_layout; + + +meminfo_t *bl1_plat_sec_mem_layout(void) +{ + return &bl1_tzram_layout; +} + +/******************************************************************************* + * Perform any BL1 specific platform actions. + ******************************************************************************/ +void bl1_early_platform_setup(void) +{ + /* Initialize the console to provide early debug support */ + qemu_console_init(); + + /* Allow BL1 to see the whole Trusted RAM */ + bl1_tzram_layout.total_base = BL_RAM_BASE; + bl1_tzram_layout.total_size = BL_RAM_SIZE; +} + +/****************************************************************************** + * Perform the very early platform specific architecture setup. This only + * does basic initialization. Later architectural setup (bl1_arch_setup()) + * does not do anything platform specific. + *****************************************************************************/ +#ifdef __aarch64__ +#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__) +#else +#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__) +#endif + +void bl1_plat_arch_setup(void) +{ + QEMU_CONFIGURE_BL1_MMU(bl1_tzram_layout.total_base, + bl1_tzram_layout.total_size, + BL_CODE_BASE, BL1_CODE_END, + BL1_RO_DATA_BASE, BL1_RO_DATA_END, + BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); +} + +void bl1_platform_setup(void) +{ + plat_qemu_io_setup(); +} diff --git a/plat/qemu/common/qemu_bl2_mem_params_desc.c b/plat/qemu/common/qemu_bl2_mem_params_desc.c new file mode 100644 index 000000000..a01f2dc91 --- /dev/null +++ b/plat/qemu/common/qemu_bl2_mem_params_desc.c @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +/******************************************************************************* + * Following descriptor provides BL image/ep information that gets used + * by BL2 to load the images and also subset of this information is + * passed to next BL image. The image loading sequence is managed by + * populating the images in required loading order. The image execution + * sequence is managed by populating the `next_handoff_image_id` with + * the next executable image id. + ******************************************************************************/ +static bl_mem_params_node_t bl2_mem_params_descs[] = { +#ifdef EL3_PAYLOAD_BASE + /* Fill EL3 payload related information (BL31 is EL3 payload) */ + { .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = EL3_PAYLOAD_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +#else /* EL3_PAYLOAD_BASE */ +#ifdef __aarch64__ + /* Fill BL31 related information */ + { .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), +# if DEBUG + .ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL, +# endif + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + +# ifdef QEMU_LOAD_BL32 + .next_handoff_image_id = BL32_IMAGE_ID, +# else + .next_handoff_image_id = BL33_IMAGE_ID, +# endif + }, +#endif /* __aarch64__ */ +# ifdef QEMU_LOAD_BL32 + +#ifdef __aarch64__ +#define BL32_EP_ATTRIBS (SECURE | EXECUTABLE) +#define BL32_IMG_ATTRIBS 0 +#else +#define BL32_EP_ATTRIBS (SECURE | EXECUTABLE | EP_FIRST_EXE) +#define BL32_IMG_ATTRIBS IMAGE_ATTRIB_PLAT_SETUP +#endif + + /* Fill BL32 related information */ + { .image_id = BL32_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, BL32_EP_ATTRIBS), + .ep_info.pc = BL32_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, + image_info_t, BL32_IMG_ATTRIBS), + + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + + .next_handoff_image_id = BL33_IMAGE_ID, + }, + + /* + * Fill BL32 external 1 related information. + * A typical use for extra1 image is with OP-TEE where it is the + * pager image. + */ + { .image_id = BL32_EXTRA1_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, + image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + + /* + * Fill BL32 external 2 related information. + * A typical use for extra2 image is with OP-TEE where it is the + * paged image. + */ + { .image_id = BL32_EXTRA2_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, + image_info_t, IMAGE_ATTRIB_SKIP_LOADING), +#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE) + .image_info.image_base = QEMU_OPTEE_PAGEABLE_LOAD_BASE, + .image_info.image_max_size = QEMU_OPTEE_PAGEABLE_LOAD_SIZE, +#endif + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +# endif /* QEMU_LOAD_BL32 */ + + /* Fill BL33 related information */ + { .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, NON_SECURE | EXECUTABLE), +# ifdef PRELOADED_BL33_BASE + .ep_info.pc = PRELOADED_BL33_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, + IMAGE_ATTRIB_SKIP_LOADING), +# else /* PRELOADED_BL33_BASE */ + .ep_info.pc = NS_IMAGE_OFFSET, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, + 0), + .image_info.image_base = NS_IMAGE_OFFSET, + .image_info.image_max_size = NS_DRAM0_BASE + NS_DRAM0_SIZE - + NS_IMAGE_OFFSET, +# endif /* !PRELOADED_BL33_BASE */ + + .next_handoff_image_id = INVALID_IMAGE_ID, + } +#endif /* !EL3_PAYLOAD_BASE */ +}; + +REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c new file mode 100644 index 000000000..166d2454e --- /dev/null +++ b/plat/qemu/common/qemu_bl2_setup.c @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "qemu_private.h" + + +/* Data structure which holds the extents of the trusted SRAM for BL2 */ +static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); + +void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + meminfo_t *mem_layout = (void *)arg1; + + /* Initialize the console to provide early debug support */ + qemu_console_init(); + + /* Setup the BL2 memory layout */ + bl2_tzram_layout = *mem_layout; + + plat_qemu_io_setup(); +} + +static void security_setup(void) +{ + /* + * This is where a TrustZone address space controller and other + * security related peripherals, would be configured. + */ +} + +static void update_dt(void) +{ + int ret; + void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE; + + ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE); + if (ret < 0) { + ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret); + return; + } + + if (dt_add_psci_node(fdt)) { + ERROR("Failed to add PSCI Device Tree node\n"); + return; + } + + if (dt_add_psci_cpu_enable_methods(fdt)) { + ERROR("Failed to add PSCI cpu enable methods in Device Tree\n"); + return; + } + + ret = fdt_pack(fdt); + if (ret < 0) + ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret); +} + +void bl2_platform_setup(void) +{ + security_setup(); + update_dt(); + + /* TODO Initialize timer */ +} + +#ifdef __aarch64__ +#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__) +#else +#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__) +#endif + +void bl2_plat_arch_setup(void) +{ + QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base, + bl2_tzram_layout.total_size, + BL_CODE_BASE, BL_CODE_END, + BL_RO_DATA_BASE, BL_RO_DATA_END, + BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); +} + +/******************************************************************************* + * Gets SPSR for BL32 entry + ******************************************************************************/ +static uint32_t qemu_get_spsr_for_bl32_entry(void) +{ +#ifdef __aarch64__ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL3-2 image. + */ + return 0; +#else + return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, + DISABLE_ALL_EXCEPTIONS); +#endif +} + +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +static uint32_t qemu_get_spsr_for_bl33_entry(void) +{ + uint32_t spsr; +#ifdef __aarch64__ + unsigned int mode; + + /* Figure out what mode we enter the non-secure world in */ + mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); +#else + spsr = SPSR_MODE32(MODE32_svc, + plat_get_ns_image_entrypoint() & 0x1, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); +#endif + return spsr; +} + +static int qemu_bl2_handle_post_image_load(unsigned int image_id) +{ + int err = 0; + bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); +#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE) + bl_mem_params_node_t *pager_mem_params = NULL; + bl_mem_params_node_t *paged_mem_params = NULL; +#endif + + assert(bl_mem_params); + + switch (image_id) { + case BL32_IMAGE_ID: +#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE) + pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); + assert(pager_mem_params); + + paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); + assert(paged_mem_params); + + err = parse_optee_header(&bl_mem_params->ep_info, + &pager_mem_params->image_info, + &paged_mem_params->image_info); + if (err != 0) { + WARN("OPTEE header parse error.\n"); + } + +#if defined(SPD_opteed) + /* + * OP-TEE expect to receive DTB address in x2. + * This will be copied into x2 by dispatcher. + */ + bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE; +#else /* case AARCH32_SP_OPTEE */ + bl_mem_params->ep_info.args.arg0 = + bl_mem_params->ep_info.args.arg1; + bl_mem_params->ep_info.args.arg1 = 0; + bl_mem_params->ep_info.args.arg2 = PLAT_QEMU_DT_BASE; + bl_mem_params->ep_info.args.arg3 = 0; +#endif +#endif + bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry(); + break; + + case BL33_IMAGE_ID: +#ifdef AARCH32_SP_OPTEE + /* AArch32 only core: OP-TEE expects NSec EP in register LR */ + pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); + assert(pager_mem_params); + pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; +#endif + + /* BL33 expects to receive the primary CPU MPID (through r0) */ + bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); + bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry(); + break; + default: + /* Do nothing in default case */ + break; + } + + return err; +} + +/******************************************************************************* + * This function can be used by the platforms to update/use image + * information for given `image_id`. + ******************************************************************************/ +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + return qemu_bl2_handle_post_image_load(image_id); +} + +uintptr_t plat_get_ns_image_entrypoint(void) +{ + return NS_IMAGE_OFFSET; +} diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c new file mode 100644 index 000000000..4d36b0391 --- /dev/null +++ b/plat/qemu/common/qemu_bl31_setup.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +#include "qemu_private.h" + +/* + * Placeholder variables for copying the arguments that have been passed to + * BL3-1 from BL2. + */ +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +/******************************************************************************* + * Perform any BL3-1 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before + * they are lost (potentially). This needs to be done before the MMU is + * initialized so that the memory layout can be used while creating page + * tables. BL2 has flushed this information to memory, so we are guaranteed + * to pick up good data. + ******************************************************************************/ +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + /* Initialize the console to provide early debug support */ + qemu_console_init(); + + /* + * Check params passed from BL2 + */ + bl_params_t *params_from_bl2 = (bl_params_t *)arg0; + + assert(params_from_bl2); + assert(params_from_bl2->h.type == PARAM_BL_PARAMS); + assert(params_from_bl2->h.version >= VERSION_2); + + bl_params_node_t *bl_params = params_from_bl2->head; + + /* + * Copy BL33 and BL32 (if present), entry point information. + * They are stored in Secure RAM, in BL2's address space. + */ + while (bl_params) { + if (bl_params->image_id == BL32_IMAGE_ID) + bl32_image_ep_info = *bl_params->ep_info; + + if (bl_params->image_id == BL33_IMAGE_ID) + bl33_image_ep_info = *bl_params->ep_info; + + bl_params = bl_params->next_params_info; + } + + if (!bl33_image_ep_info.pc) + panic(); +} + +void bl31_plat_arch_setup(void) +{ + qemu_configure_mmu_el3(BL31_BASE, (BL31_END - BL31_BASE), + BL_CODE_BASE, BL_CODE_END, + BL_RO_DATA_BASE, BL_RO_DATA_END, + BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); +} + +void bl31_platform_setup(void) +{ + plat_qemu_gic_init(); +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image + * for the security state specified. BL3-3 corresponds to the non-secure + * image type while BL3-2 corresponds to the secure image type. A NULL + * pointer is returned if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(sec_state_is_valid(type)); + next_image_info = (type == NON_SECURE) + ? &bl33_image_ep_info : &bl32_image_ep_info; + /* + * None of the images on the ARM development platforms can have 0x0 + * as the entrypoint + */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c new file mode 100644 index 000000000..56bf9532f --- /dev/null +++ b/plat/qemu/common/qemu_common.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +#include "qemu_private.h" + +#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ + DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#ifdef DEVICE1_BASE +#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ + DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#ifdef DEVICE2_BASE +#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ + DEVICE2_SIZE, \ + MT_DEVICE | MT_RO | MT_SECURE) +#endif + +#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ + SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \ + MT_MEMORY | MT_RO | MT_SECURE) + +/* + * Table of regions for various BL stages to map using the MMU. + * This doesn't include TZRAM as the 'mem_layout' argument passed to + * arm_configure_mmu_elx() will give the available subset of that, + */ +#ifdef IMAGE_BL1 +static const mmap_region_t plat_qemu_mmap[] = { + MAP_FLASH0, + MAP_SHARED_RAM, + MAP_DEVICE0, +#ifdef MAP_DEVICE1 + MAP_DEVICE1, +#endif +#ifdef MAP_DEVICE2 + MAP_DEVICE2, +#endif + {0} +}; +#endif +#ifdef IMAGE_BL2 +static const mmap_region_t plat_qemu_mmap[] = { + MAP_FLASH0, + MAP_SHARED_RAM, + MAP_DEVICE0, +#ifdef MAP_DEVICE1 + MAP_DEVICE1, +#endif +#ifdef MAP_DEVICE2 + MAP_DEVICE2, +#endif + MAP_NS_DRAM0, + MAP_BL32_MEM, + {0} +}; +#endif +#ifdef IMAGE_BL31 +static const mmap_region_t plat_qemu_mmap[] = { + MAP_SHARED_RAM, + MAP_DEVICE0, +#ifdef MAP_DEVICE1 + MAP_DEVICE1, +#endif + MAP_BL32_MEM, + {0} +}; +#endif +#ifdef IMAGE_BL32 +static const mmap_region_t plat_qemu_mmap[] = { + MAP_SHARED_RAM, + MAP_DEVICE0, +#ifdef MAP_DEVICE1 + MAP_DEVICE1, +#endif + {0} +}; +#endif + +/******************************************************************************* + * Macro generating the code for the function setting up the pagetables as per + * the platform memory map & initialize the mmu, for the given exception level + ******************************************************************************/ + +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void qemu_configure_mmu_##_el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long code_start, \ + unsigned long code_limit, \ + unsigned long ro_start, \ + unsigned long ro_limit, \ + unsigned long coh_start, \ + unsigned long coh_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(code_start, code_start, \ + code_limit - code_start, \ + MT_CODE | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_RO_DATA | MT_SECURE); \ + mmap_add_region(coh_start, coh_start, \ + coh_limit - coh_start, \ + MT_DEVICE | MT_RW | MT_SECURE); \ + mmap_add(plat_qemu_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_##_el(0); \ + } + +/* Define EL1 and EL3 variants of the function initialising the MMU */ +#ifdef __aarch64__ +DEFINE_CONFIGURE_MMU_EL(el1) +DEFINE_CONFIGURE_MMU_EL(el3) +#else +DEFINE_CONFIGURE_MMU_EL(svc_mon) +#endif + + diff --git a/plat/qemu/common/qemu_console.c b/plat/qemu/common/qemu_console.c new file mode 100644 index 000000000..fec182892 --- /dev/null +++ b/plat/qemu/common/qemu_console.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +static console_pl011_t console; + +void qemu_console_init(void) +{ + (void)console_pl011_register(PLAT_QEMU_BOOT_UART_BASE, + PLAT_QEMU_BOOT_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE, &console); + + console_set_scope(&console.console, CONSOLE_FLAG_BOOT | + CONSOLE_FLAG_RUNTIME); +} + diff --git a/plat/qemu/common/qemu_gicv2.c b/plat/qemu/common/qemu_gicv2.c new file mode 100644 index 000000000..fb566227a --- /dev/null +++ b/plat/qemu/common/qemu_gicv2.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +static const interrupt_prop_t qemu_interrupt_props[] = { + PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), + PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) +}; + +static const struct gicv2_driver_data plat_gicv2_driver_data = { + .gicd_base = GICD_BASE, + .gicc_base = GICC_BASE, + .interrupt_props = qemu_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), +}; + +void plat_qemu_gic_init(void) +{ + /* Initialize the gic cpu and distributor interfaces */ + gicv2_driver_init(&plat_gicv2_driver_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +void qemu_pwr_gic_on_finish(void) +{ + /* TODO: This setup is needed only after a cold boot */ + gicv2_pcpu_distif_init(); + + /* Enable the gic cpu interface */ + gicv2_cpuif_enable(); +} diff --git a/plat/qemu/common/qemu_gicv3.c b/plat/qemu/common/qemu_gicv3.c new file mode 100644 index 000000000..28572c5ef --- /dev/null +++ b/plat/qemu/common/qemu_gicv3.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +static const interrupt_prop_t qemu_interrupt_props[] = { + PLATFORM_G1S_PROPS(INTR_GROUP1S), + PLATFORM_G0_PROPS(INTR_GROUP0) +}; + +static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr) +{ + return (unsigned int)plat_core_pos_by_mpidr(mpidr); +} + +static const gicv3_driver_data_t qemu_gicv3_driver_data = { + .gicd_base = GICD_BASE, + .gicr_base = GICR_BASE, + .interrupt_props = qemu_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = qemu_rdistif_base_addrs, + .mpidr_to_core_pos = qemu_mpidr_to_core_pos +}; + +void plat_qemu_gic_init(void) +{ + gicv3_driver_init(&qemu_gicv3_driver_data); + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +void qemu_pwr_gic_on_finish(void) +{ + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} diff --git a/plat/qemu/common/qemu_image_load.c b/plat/qemu/common/qemu_image_load.c new file mode 100644 index 000000000..9970d1de7 --- /dev/null +++ b/plat/qemu/common/qemu_image_load.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/******************************************************************************* + * This function is a wrapper of a common function which flushes the data + * structures so that they are visible in memory for the next BL image. + ******************************************************************************/ +void plat_flush_next_bl_params(void) +{ + flush_bl_params_desc(); +} + +/******************************************************************************* + * This function is a wrapper of a common function which returns the list of + * loadable images. + ******************************************************************************/ +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +/******************************************************************************* + * This function is a wrapper of a common function which returns the data + * structures of the next BL image. + ******************************************************************************/ +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +} diff --git a/plat/qemu/common/qemu_io_storage.c b/plat/qemu/common/qemu_io_storage.c new file mode 100644 index 000000000..0e81cd199 --- /dev/null +++ b/plat/qemu/common/qemu_io_storage.c @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Semihosting filenames */ +#define BL2_IMAGE_NAME "bl2.bin" +#define BL31_IMAGE_NAME "bl31.bin" +#define BL32_IMAGE_NAME "bl32.bin" +#define BL32_EXTRA1_IMAGE_NAME "bl32_extra1.bin" +#define BL32_EXTRA2_IMAGE_NAME "bl32_extra2.bin" +#define BL33_IMAGE_NAME "bl33.bin" + +#if TRUSTED_BOARD_BOOT +#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt" +#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" +#define SOC_FW_KEY_CERT_NAME "soc_fw_key.crt" +#define TOS_FW_KEY_CERT_NAME "tos_fw_key.crt" +#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt" +#define SOC_FW_CONTENT_CERT_NAME "soc_fw_content.crt" +#define TOS_FW_CONTENT_CERT_NAME "tos_fw_content.crt" +#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt" +#endif /* TRUSTED_BOARD_BOOT */ + + + +/* IO devices */ +static const io_dev_connector_t *fip_dev_con; +static uintptr_t fip_dev_handle; +static const io_dev_connector_t *memmap_dev_con; +static uintptr_t memmap_dev_handle; +static const io_dev_connector_t *sh_dev_con; +static uintptr_t sh_dev_handle; + +static const io_block_spec_t fip_block_spec = { + .offset = PLAT_QEMU_FIP_BASE, + .length = PLAT_QEMU_FIP_MAX_SIZE +}; + +static const io_uuid_spec_t bl2_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, +}; + +static const io_uuid_spec_t bl31_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, +}; + +static const io_uuid_spec_t bl32_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + +static const io_uuid_spec_t bl32_extra1_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, +}; + +static const io_uuid_spec_t bl32_extra2_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, +}; + +static const io_uuid_spec_t bl33_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +#if TRUSTED_BOARD_BOOT +static const io_uuid_spec_t tb_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FW_CERT, +}; + +static const io_uuid_spec_t trusted_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_KEY_CERT, +}; + +static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = { + .uuid = UUID_SOC_FW_KEY_CERT, +}; + +static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, +}; + +static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, +}; + +static const io_uuid_spec_t soc_fw_cert_uuid_spec = { + .uuid = UUID_SOC_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t tos_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t nt_fw_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, +}; +#endif /* TRUSTED_BOARD_BOOT */ + +static const io_file_spec_t sh_file_spec[] = { + [BL2_IMAGE_ID] = { + .path = BL2_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL31_IMAGE_ID] = { + .path = BL31_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL32_IMAGE_ID] = { + .path = BL32_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL32_EXTRA1_IMAGE_ID] = { + .path = BL32_EXTRA1_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL32_EXTRA2_IMAGE_ID] = { + .path = BL32_EXTRA2_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL33_IMAGE_ID] = { + .path = BL33_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_BOOT_FW_CERT_ID] = { + .path = TRUSTED_BOOT_FW_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [TRUSTED_KEY_CERT_ID] = { + .path = TRUSTED_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [SOC_FW_KEY_CERT_ID] = { + .path = SOC_FW_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + .path = TOS_FW_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + .path = NT_FW_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [SOC_FW_CONTENT_CERT_ID] = { + .path = SOC_FW_CONTENT_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + .path = TOS_FW_CONTENT_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + .path = NT_FW_CONTENT_CERT_NAME, + .mode = FOPEN_MODE_RB + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + + + +static int open_fip(const uintptr_t spec); +static int open_memmap(const uintptr_t spec); + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +/* By default, ARM platforms load images from the FIP */ +static const struct plat_io_policy policies[] = { + [FIP_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&fip_block_spec, + open_memmap + }, + [BL2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl2_uuid_spec, + open_fip + }, + [BL31_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_uuid_spec, + open_fip + }, + [BL32_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_uuid_spec, + open_fip + }, + [BL32_EXTRA1_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra1_uuid_spec, + open_fip + }, + [BL32_EXTRA2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra2_uuid_spec, + open_fip + }, + [BL33_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_uuid_spec, + open_fip + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_BOOT_FW_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tb_fw_cert_uuid_spec, + open_fip + }, + [TRUSTED_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&trusted_key_cert_uuid_spec, + open_fip + }, + [SOC_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_key_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_key_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_key_cert_uuid_spec, + open_fip + }, + [SOC_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_cert_uuid_spec, + open_fip + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + +static int open_fip(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if a Firmware Image Package is available */ + result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); + if (result == 0) { + result = io_open(fip_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using FIP\n"); + io_close(local_image_handle); + } + } + return result; +} + +static int open_memmap(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(memmap_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Memmap\n"); + io_close(local_image_handle); + } + } + return result; +} + +static int open_semihosting(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if the file exists on semi-hosting.*/ + result = io_dev_init(sh_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(sh_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Semi-hosting IO\n"); + io_close(local_image_handle); + } + } + return result; +} + +void plat_qemu_io_setup(void) +{ + int io_result; + + io_result = register_io_dev_fip(&fip_dev_con); + assert(io_result == 0); + + io_result = register_io_dev_memmap(&memmap_dev_con); + assert(io_result == 0); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, + &fip_dev_handle); + assert(io_result == 0); + + io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, + &memmap_dev_handle); + assert(io_result == 0); + + /* Register the additional IO devices on this platform */ + io_result = register_io_dev_sh(&sh_dev_con); + assert(io_result == 0); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(sh_dev_con, (uintptr_t)NULL, &sh_dev_handle); + assert(io_result == 0); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} + +static int get_alt_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result = open_semihosting((const uintptr_t)&sh_file_spec[image_id]); + + if (result == 0) { + *dev_handle = sh_dev_handle; + *image_spec = (uintptr_t)&sh_file_spec[image_id]; + } + + return result; +} + +/* + * Return an IO device handle and specification which can be used to access + * an image. Use this to enforce platform load policy + */ +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + if (result == 0) { + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + } else { + VERBOSE("Trying alternative IO\n"); + result = get_alt_image_source(image_id, dev_handle, image_spec); + } + + return result; +} diff --git a/plat/qemu/common/qemu_pm.c b/plat/qemu/common/qemu_pm.c new file mode 100644 index 000000000..a199688df --- /dev/null +++ b/plat/qemu/common/qemu_pm.c @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include +#include + +#include "qemu_private.h" + +/* + * The secure entry point to be used on warm reset. + */ +static unsigned long secure_entrypoint; + +/* Make composite power state parameter till power level 0 */ +#if PSCI_EXTENDED_STATE_ID + +#define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) +#else +#define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) +#endif /* PSCI_EXTENDED_STATE_ID */ + + +#define qemu_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ + qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) + + + +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +static const unsigned int qemu_pm_idle_states[] = { + /* State-id - 0x01 */ + qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, + MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x02 */ + qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, + MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x22 */ + qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, + MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), + 0, +}; + +/******************************************************************************* + * Platform handler called to check the validity of the power state + * parameter. The power state parameter has to be a composite power state. + ******************************************************************************/ +static int qemu_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int state_id; + int i; + + assert(req_state); + + /* + * Currently we are using a linear search for finding the matching + * entry in the idle power state array. This can be made a binary + * search if the number of entries justify the additional complexity. + */ + for (i = 0; !!qemu_pm_idle_states[i]; i++) { + if (power_state == qemu_pm_idle_states[i]) + break; + } + + /* Return error if entry not found in the idle state array */ + if (!qemu_pm_idle_states[i]) + return PSCI_E_INVALID_PARAMS; + + i = 0; + state_id = psci_get_pstate_id(power_state); + + /* Parse the State ID and populate the state info parameter */ + while (state_id) { + req_state->pwr_domain_state[i++] = state_id & + PLAT_LOCAL_PSTATE_MASK; + state_id >>= PLAT_LOCAL_PSTATE_WIDTH; + } + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Platform handler called to check the validity of the non secure + * entrypoint. + ******************************************************************************/ +static int qemu_validate_ns_entrypoint(uintptr_t entrypoint) +{ + /* + * Check if the non secure entrypoint lies within the non + * secure DRAM. + */ + if ((entrypoint >= NS_DRAM0_BASE) && + (entrypoint < (NS_DRAM0_BASE + NS_DRAM0_SIZE))) + return PSCI_E_SUCCESS; + return PSCI_E_INVALID_ADDRESS; +} + +/******************************************************************************* + * Platform handler called when a CPU is about to enter standby. + ******************************************************************************/ +static void qemu_cpu_standby(plat_local_state_t cpu_state) +{ + + assert(cpu_state == PLAT_LOCAL_STATE_RET); + + /* + * Enter standby state + * dsb is good practice before using wfi to enter low power states + */ + dsb(); + wfi(); +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +static int qemu_pwr_domain_on(u_register_t mpidr) +{ + int rc = PSCI_E_SUCCESS; + unsigned pos = plat_core_pos_by_mpidr(mpidr); + uint64_t *hold_base = (uint64_t *)PLAT_QEMU_HOLD_BASE; + + hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO; + sev(); + + return rc; +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void qemu_pwr_domain_off(const psci_power_state_t *target_state) +{ + assert(0); +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be suspended. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void qemu_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + assert(0); +} + +/******************************************************************************* + * Platform handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +void qemu_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == + PLAT_LOCAL_STATE_OFF); + + qemu_pwr_gic_on_finish(); +} + +/******************************************************************************* + * Platform handler called when a power domain has just been powered on after + * having been suspended earlier. The target_state encodes the low power state + * that each level has woken up from. + ******************************************************************************/ +void qemu_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + assert(0); +} + +/******************************************************************************* + * Platform handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 qemu_system_off(void) +{ + ERROR("QEMU System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 qemu_system_reset(void) +{ + ERROR("QEMU System Reset: operation not handled.\n"); + panic(); +} + +static const plat_psci_ops_t plat_qemu_psci_pm_ops = { + .cpu_standby = qemu_cpu_standby, + .pwr_domain_on = qemu_pwr_domain_on, + .pwr_domain_off = qemu_pwr_domain_off, + .pwr_domain_suspend = qemu_pwr_domain_suspend, + .pwr_domain_on_finish = qemu_pwr_domain_on_finish, + .pwr_domain_suspend_finish = qemu_pwr_domain_suspend_finish, + .system_off = qemu_system_off, + .system_reset = qemu_system_reset, + .validate_power_state = qemu_validate_power_state, + .validate_ns_entrypoint = qemu_validate_ns_entrypoint +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + uintptr_t *mailbox = (void *) PLAT_QEMU_TRUSTED_MAILBOX_BASE; + + *mailbox = sec_entrypoint; + secure_entrypoint = (unsigned long) sec_entrypoint; + *psci_ops = &plat_qemu_psci_pm_ops; + + return 0; +} diff --git a/plat/qemu/common/qemu_private.h b/plat/qemu/common/qemu_private.h new file mode 100644 index 000000000..71ea4de10 --- /dev/null +++ b/plat/qemu/common/qemu_private.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef QEMU_PRIVATE_H +#define QEMU_PRIVATE_H + +#include + +void qemu_configure_mmu_svc_mon(unsigned long total_base, + unsigned long total_size, + unsigned long code_start, unsigned long code_limit, + unsigned long ro_start, unsigned long ro_limit, + unsigned long coh_start, unsigned long coh_limit); + +void qemu_configure_mmu_el1(unsigned long total_base, unsigned long total_size, + unsigned long code_start, unsigned long code_limit, + unsigned long ro_start, unsigned long ro_limit, + unsigned long coh_start, unsigned long coh_limit); + +void qemu_configure_mmu_el3(unsigned long total_base, unsigned long total_size, + unsigned long code_start, unsigned long code_limit, + unsigned long ro_start, unsigned long ro_limit, + unsigned long coh_start, unsigned long coh_limit); + +void plat_qemu_io_setup(void); +unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); + +void qemu_console_init(void); + +void plat_qemu_gic_init(void); +void qemu_pwr_gic_on_finish(void); + +#endif /* QEMU_PRIVATE_H */ diff --git a/plat/qemu/common/qemu_rotpk.S b/plat/qemu/common/qemu_rotpk.S new file mode 100644 index 000000000..5d1b83f40 --- /dev/null +++ b/plat/qemu/common/qemu_rotpk.S @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .global qemu_rotpk_hash + .global qemu_rotpk_hash_end +qemu_rotpk_hash: + /* DER header */ + .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 + .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 + /* SHA256 */ + .incbin ROTPK_HASH +qemu_rotpk_hash_end: diff --git a/plat/qemu/common/qemu_stack_protector.c b/plat/qemu/common/qemu_stack_protector.c new file mode 100644 index 000000000..c226158ad --- /dev/null +++ b/plat/qemu/common/qemu_stack_protector.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL) + +u_register_t plat_get_stack_protector_canary(void) +{ + /* + * Ideally, a random number should be returned instead of the + * combination of a timer's value and a compile-time constant. + * As the virt platform does not have any random number generator, + * this is better than nothing but not necessarily really secure. + */ + return RANDOM_CANARY_VALUE ^ read_cntpct_el0(); +} + diff --git a/plat/qemu/common/qemu_trusted_boot.c b/plat/qemu/common/qemu_trusted_boot.c new file mode 100644 index 000000000..1ef7e431b --- /dev/null +++ b/plat/qemu/common/qemu_trusted_boot.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +extern char qemu_rotpk_hash[], qemu_rotpk_hash_end[]; + +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + *key_ptr = qemu_rotpk_hash; + *key_len = qemu_rotpk_hash_end - qemu_rotpk_hash; + *flags = ROTPK_IS_HASH; + + return 0; +} + +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + *nv_ctr = 0; + + return 0; +} + +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + return 1; +} + +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + return get_mbedtls_heap_helper(heap_addr, heap_size); +} diff --git a/plat/qemu/common/sp_min/sp_min-qemu.mk b/plat/qemu/common/sp_min/sp_min-qemu.mk new file mode 100644 index 000000000..e93a0c231 --- /dev/null +++ b/plat/qemu/common/sp_min/sp_min-qemu.mk @@ -0,0 +1,22 @@ +# +# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BL32_SOURCES += plat/qemu/sp_min/sp_min_setup.c \ + plat/qemu/aarch32/plat_helpers.S \ + plat/qemu/qemu_pm.c \ + plat/qemu/topology.c + +BL32_SOURCES += lib/cpus/aarch32/aem_generic.S \ + lib/cpus/aarch32/cortex_a15.S + +BL32_SOURCES += plat/common/aarch32/platform_mp_stack.S \ + plat/common/plat_psci_common.c \ + plat/common/plat_gicv2.c + + +BL32_SOURCES += drivers/arm/gic/v2/gicv2_helpers.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/common/gic_common.c diff --git a/plat/qemu/common/sp_min/sp_min_setup.c b/plat/qemu/common/sp_min/sp_min_setup.c new file mode 100644 index 000000000..7ec657b79 --- /dev/null +++ b/plat/qemu/common/sp_min/sp_min_setup.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../qemu_private.h" + +#if RESET_TO_SP_MIN +#error qemu does not support RESET_TO_SP_MIN +#endif + +static entry_point_info_t bl33_image_ep_info; + +/****************************************************************************** + * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 + * interrupts. + *****************************************************************************/ +#define PLATFORM_G1S_PROPS(grp) \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL) + +#define PLATFORM_G0_PROPS(grp) + +static const interrupt_prop_t stih410_interrupt_props[] = { + PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), + PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) +}; + +static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; + +static const struct gicv2_driver_data plat_gicv2_driver_data = { + .gicd_base = GICD_BASE, + .gicc_base = GICC_BASE, + .interrupt_props = stih410_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(stih410_interrupt_props), + .target_masks = target_mask_array, + .target_masks_num = ARRAY_SIZE(target_mask_array), +}; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) +{ + entry_point_info_t *next_image_info = &bl33_image_ep_info; + + /* + * None of the images on the ARM development platforms can have 0x0 + * as the entrypoint + */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + bl_params_t *params_from_bl2 = (bl_params_t *)arg0; + + /* Initialize the console to provide early debug support */ + qemu_console_init(); + + ERROR("qemu sp_min, console init\n"); + /* + * Check params passed from BL2 + */ + assert(params_from_bl2); + assert(params_from_bl2->h.type == PARAM_BL_PARAMS); + assert(params_from_bl2->h.version >= VERSION_2); + + bl_params_node_t *bl_params = params_from_bl2->head; + + /* + * Copy BL33 entry point information from BL2's address space. + */ + while (bl_params) { + if (bl_params->image_id == BL33_IMAGE_ID) + bl33_image_ep_info = *bl_params->ep_info; + + bl_params = bl_params->next_params_info; + } + + if (!bl33_image_ep_info.pc) + panic(); +} + +void sp_min_plat_arch_setup(void) +{ + qemu_configure_mmu_svc_mon(BL32_RO_BASE, BL32_END - BL32_RO_BASE, + BL_CODE_BASE, BL_CODE_END, + BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); + +} + +void sp_min_platform_setup(void) +{ + /* Initialize the gic cpu and distributor interfaces */ + gicv2_driver_init(&plat_gicv2_driver_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} + +void sp_min_plat_fiq_handler(uint32_t id) +{ + VERBOSE("[sp_min] interrupt #%d\n", id); +} diff --git a/plat/qemu/common/topology.c b/plat/qemu/common/topology.c new file mode 100644 index 000000000..6352706e9 --- /dev/null +++ b/plat/qemu/common/topology.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include "qemu_private.h" + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first node */ + PLATFORM_CLUSTER0_CORE_COUNT, + /* Number of children for the second node */ + PLATFORM_CLUSTER1_CORE_COUNT, +}; + +/******************************************************************************* + * This function returns the ARM default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) + return -1; + + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) + return -1; + + return plat_qemu_calc_core_pos(mpidr); +} diff --git a/plat/qemu/include/plat_macros.S b/plat/qemu/include/plat_macros.S deleted file mode 100644 index b6cdb0714..000000000 --- a/plat/qemu/include/plat_macros.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef PLAT_MACROS_S -#define PLAT_MACROS_S - -#include -#include - - /* --------------------------------------------- - * The below required platform porting macro - * prints out relevant GIC and CCI registers - * whenever an unhandled exception is taken in - * BL31. - * Clobbers: x0 - x10, x16, x17, sp - * --------------------------------------------- - */ - .macro plat_crash_print_regs - mov_imm x17, GICC_BASE - mov_imm x16, GICD_BASE - arm_print_gic_regs - .endm - -#endif /* PLAT_MACROS_S */ diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h deleted file mode 100644 index d7f77cc78..000000000 --- a/plat/qemu/include/platform_def.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLATFORM_DEF_H -#define PLATFORM_DEF_H - -#include -#include -#include -#include - -/* Special value used to verify platform parameters from BL2 to BL3-1 */ -#define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL - -#define PLATFORM_STACK_SIZE 0x1000 - -#if ARM_ARCH_MAJOR == 7 -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#define PLATFORM_CLUSTER1_CORE_COUNT 0 -#else -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#endif -#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ - PLATFORM_CLUSTER1_CORE_COUNT) - -#define QEMU_PRIMARY_CPU 0 - -#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ - PLATFORM_CORE_COUNT) -#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 - -#define PLAT_MAX_RET_STATE U(1) -#define PLAT_MAX_OFF_STATE U(2) - -/* Local power state for power domains in Run state. */ -#define PLAT_LOCAL_STATE_RUN U(0) -/* Local power state for retention. Valid only for CPU power domains */ -#define PLAT_LOCAL_STATE_RET U(1) -/* - * Local power state for OFF/power-down. Valid for CPU and cluster power - * domains. - */ -#define PLAT_LOCAL_STATE_OFF 2 - -/* - * Macros used to parse state information from State-ID if it is using the - * recommended encoding for State-ID. - */ -#define PLAT_LOCAL_PSTATE_WIDTH 4 -#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) - -/* - * Some data must be aligned on the biggest cache line size in the platform. - * This is known only to the platform as it might have a combination of - * integrated and external caches. - */ -#define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) - -/* - * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", - * and secure DRAM. - */ -#define SEC_ROM_BASE 0x00000000 -#define SEC_ROM_SIZE 0x00020000 - -#define NS_DRAM0_BASE 0x40000000 -#define NS_DRAM0_SIZE 0x3de00000 - -#define SEC_SRAM_BASE 0x0e000000 -#define SEC_SRAM_SIZE 0x00060000 - -#define SEC_DRAM_BASE 0x0e100000 -#define SEC_DRAM_SIZE 0x00f00000 - -/* Load pageable part of OP-TEE 2MB above secure DRAM base */ -#define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) -#define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 - -/* - * ARM-TF lives in SRAM, partition it here - */ - -#define SHARED_RAM_BASE SEC_SRAM_BASE -#define SHARED_RAM_SIZE 0x00001000 - -#define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE -#define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) -#define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) -#define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ - PLAT_QEMU_HOLD_ENTRY_SIZE) -#define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 -#define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) -#define PLAT_QEMU_HOLD_STATE_WAIT 0 -#define PLAT_QEMU_HOLD_STATE_GO 1 - -#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) -#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) - -/* - * BL1 specific defines. - * - * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of - * addresses. - * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using - * the current BL1 RW debug size plus a little space for growth. - */ -#define BL1_RO_BASE SEC_ROM_BASE -#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) -#define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) -#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) - -/* - * BL2 specific defines. - * - * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug - * size plus a little space for growth. - */ -#define BL2_BASE (BL31_BASE - 0x25000) -#define BL2_LIMIT BL31_BASE - -/* - * BL3-1 specific defines. - * - * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the - * current BL3-1 debug size plus a little space for growth. - */ -#define BL31_BASE (BL31_LIMIT - 0x20000) -#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) -#define BL31_PROGBITS_LIMIT BL1_RW_BASE - - -/* - * BL3-2 specific defines. - * - * BL3-2 can execute from Secure SRAM, or Secure DRAM. - */ -#define BL32_SRAM_BASE BL_RAM_BASE -#define BL32_SRAM_LIMIT BL31_BASE -#define BL32_DRAM_BASE SEC_DRAM_BASE -#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE) - -#define SEC_SRAM_ID 0 -#define SEC_DRAM_ID 1 - -#if BL32_RAM_LOCATION_ID == SEC_SRAM_ID -# define BL32_MEM_BASE BL_RAM_BASE -# define BL32_MEM_SIZE BL_RAM_SIZE -# define BL32_BASE BL32_SRAM_BASE -# define BL32_LIMIT BL32_SRAM_LIMIT -#elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID -# define BL32_MEM_BASE SEC_DRAM_BASE -# define BL32_MEM_SIZE SEC_DRAM_SIZE -# define BL32_BASE BL32_DRAM_BASE -# define BL32_LIMIT BL32_DRAM_LIMIT -#else -# error "Unsupported BL32_RAM_LOCATION_ID value" -#endif - -#define NS_IMAGE_OFFSET 0x60000000 - -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) -#define MAX_MMAP_REGIONS 10 -#define MAX_XLAT_TABLES 6 -#define MAX_IO_DEVICES 3 -#define MAX_IO_HANDLES 4 - -/* - * PL011 related constants - */ -#define UART0_BASE 0x09000000 -#define UART1_BASE 0x09040000 -#define UART0_CLK_IN_HZ 1 -#define UART1_CLK_IN_HZ 1 - -#define PLAT_QEMU_BOOT_UART_BASE UART0_BASE -#define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ - -#define PLAT_QEMU_CRASH_UART_BASE UART1_BASE -#define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ - -#define PLAT_QEMU_CONSOLE_BAUDRATE 115200 - -#define QEMU_FLASH0_BASE 0x04000000 -#define QEMU_FLASH0_SIZE 0x04000000 - -#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE -#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE - -#define DEVICE0_BASE 0x08000000 -#define DEVICE0_SIZE 0x01000000 -#define DEVICE1_BASE 0x09000000 -#define DEVICE1_SIZE 0x00041000 - -/* - * GIC related constants - */ - -#define GICD_BASE 0x8000000 -#define GICC_BASE 0x8010000 -#define GICR_BASE 0x80A0000 - - -#define QEMU_IRQ_SEC_SGI_0 8 -#define QEMU_IRQ_SEC_SGI_1 9 -#define QEMU_IRQ_SEC_SGI_2 10 -#define QEMU_IRQ_SEC_SGI_3 11 -#define QEMU_IRQ_SEC_SGI_4 12 -#define QEMU_IRQ_SEC_SGI_5 13 -#define QEMU_IRQ_SEC_SGI_6 14 -#define QEMU_IRQ_SEC_SGI_7 15 - -/****************************************************************************** - * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 - * interrupts. - *****************************************************************************/ -#define PLATFORM_G1S_PROPS(grp) \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE) - -#define PLATFORM_G0_PROPS(grp) - -/* - * DT related constants - */ -#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE -#define PLAT_QEMU_DT_MAX_SIZE 0x100000 - -/* - * System counter - */ -#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16) - -#endif /* PLATFORM_DEF_H */ diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk deleted file mode 100644 index bc4a21bc0..000000000 --- a/plat/qemu/platform.mk +++ /dev/null @@ -1,186 +0,0 @@ -# -# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -# Use the GICv2 driver on QEMU by default -QEMU_USE_GIC_DRIVER := QEMU_GICV2 - -ifeq (${ARM_ARCH_MAJOR},7) -# ARMv7 Qemu support in trusted firmware expects the Cortex-A15 model. -# Qemu Cortex-A15 model does not implement the virtualization extension. -# For this reason, we cannot set ARM_CORTEX_A15=yes and must define all -# the ARMv7 build directives. -MARCH32_DIRECTIVE := -mcpu=cortex-a15 -$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)) -$(eval $(call add_define,ARMV7_SUPPORTS_GENERIC_TIMER)) -# Qemu expects a BL32 boot stage. -NEED_BL32 := yes -endif # ARMv7 - -ifeq (${SPD},opteed) -add-lib-optee := yes -endif -ifeq ($(AARCH32_SP),optee) -add-lib-optee := yes -endif - -include lib/libfdt/libfdt.mk - -ifeq ($(NEED_BL32),yes) -$(eval $(call add_define,QEMU_LOAD_BL32)) -endif - -PLAT_PATH := plat/qemu/ -PLAT_INCLUDES := -Iplat/qemu/include - -ifeq (${ARM_ARCH_MAJOR},8) -PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH} -endif - -PLAT_BL_COMMON_SOURCES := plat/qemu/qemu_common.c \ - plat/qemu/qemu_console.c \ - drivers/arm/pl011/${ARCH}/pl011_console.S \ - -include lib/xlat_tables_v2/xlat_tables.mk -PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} - -ifneq (${TRUSTED_BOARD_BOOT},0) - - include drivers/auth/mbedtls/mbedtls_crypto.mk - include drivers/auth/mbedtls/mbedtls_x509.mk - - AUTH_SOURCES := drivers/auth/auth_mod.c \ - drivers/auth/crypto_mod.c \ - drivers/auth/img_parser_mod.c \ - drivers/auth/tbbr/tbbr_cot.c - - BL1_SOURCES += ${AUTH_SOURCES} \ - bl1/tbbr/tbbr_img_desc.c \ - plat/common/tbbr/plat_tbbr.c \ - plat/qemu/qemu_trusted_boot.c \ - $(PLAT_PATH)/qemu_rotpk.S - - BL2_SOURCES += ${AUTH_SOURCES} \ - plat/common/tbbr/plat_tbbr.c \ - plat/qemu/qemu_trusted_boot.c \ - $(PLAT_PATH)/qemu_rotpk.S - - ROT_KEY = $(BUILD_PLAT)/rot_key.pem - ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin - - $(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) - - $(BUILD_PLAT)/bl1/qemu_rotpk.o: $(ROTPK_HASH) - $(BUILD_PLAT)/bl2/qemu_rotpk.o: $(ROTPK_HASH) - - certificates: $(ROT_KEY) - - $(ROT_KEY): - @echo " OPENSSL $@" - $(Q)openssl genrsa 2048 > $@ 2>/dev/null - - $(ROTPK_HASH): $(ROT_KEY) - @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null -endif - -BL1_SOURCES += drivers/io/io_semihosting.c \ - drivers/io/io_storage.c \ - drivers/io/io_fip.c \ - drivers/io/io_memmap.c \ - lib/semihosting/semihosting.c \ - lib/semihosting/${ARCH}/semihosting_call.S \ - plat/qemu/qemu_io_storage.c \ - plat/qemu/${ARCH}/plat_helpers.S \ - plat/qemu/qemu_bl1_setup.c - -ifeq (${ARM_ARCH_MAJOR},8) -BL1_SOURCES += lib/cpus/aarch64/aem_generic.S \ - lib/cpus/aarch64/cortex_a53.S \ - lib/cpus/aarch64/cortex_a57.S -else -BL1_SOURCES += lib/cpus/${ARCH}/cortex_a15.S -endif - -BL2_SOURCES += drivers/io/io_semihosting.c \ - drivers/io/io_storage.c \ - drivers/io/io_fip.c \ - drivers/io/io_memmap.c \ - lib/semihosting/semihosting.c \ - lib/semihosting/${ARCH}/semihosting_call.S\ - plat/qemu/qemu_io_storage.c \ - plat/qemu/${ARCH}/plat_helpers.S \ - plat/qemu/qemu_bl2_setup.c \ - common/fdt_fixup.c \ - plat/qemu/qemu_bl2_mem_params_desc.c \ - plat/qemu/qemu_image_load.c \ - common/desc_image_load.c - -ifeq ($(add-lib-optee),yes) -BL2_SOURCES += lib/optee/optee_utils.c -endif - -QEMU_GICV2_SOURCES := drivers/arm/gic/v2/gicv2_helpers.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/common/gic_common.c \ - plat/common/plat_gicv2.c \ - plat/qemu/qemu_gicv2.c - -QEMU_GICV3_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \ - drivers/arm/gic/v3/gicv3_main.c \ - drivers/arm/gic/common/gic_common.c \ - plat/common/plat_gicv3.c \ - plat/qemu/qemu_gicv3.c - -ifeq (${QEMU_USE_GIC_DRIVER}, QEMU_GICV2) -QEMU_GIC_SOURCES := ${QEMU_GICV2_SOURCES} -else ifeq (${QEMU_USE_GIC_DRIVER}, QEMU_GICV3) -QEMU_GIC_SOURCES := ${QEMU_GICV3_SOURCES} -else -$(error "Incorrect GIC driver chosen for QEMU platform") -endif - -ifeq (${ARM_ARCH_MAJOR},8) -BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ - lib/cpus/aarch64/cortex_a53.S \ - lib/cpus/aarch64/cortex_a57.S \ - plat/common/plat_psci_common.c \ - plat/qemu/qemu_pm.c \ - plat/qemu/topology.c \ - plat/qemu/aarch64/plat_helpers.S \ - plat/qemu/qemu_bl31_setup.c \ - ${QEMU_GIC_SOURCES} -endif - -# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images -# in the FIP if the platform requires. -ifneq ($(BL32_EXTRA1),) -$(eval $(call TOOL_ADD_IMG,bl32_extra1,--tos-fw-extra1)) -endif -ifneq ($(BL32_EXTRA2),) -$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2)) -endif - -SEPARATE_CODE_AND_RODATA := 1 -ENABLE_STACK_PROTECTOR := 0 -ifneq ($(ENABLE_STACK_PROTECTOR), 0) - PLAT_BL_COMMON_SOURCES += plat/qemu/qemu_stack_protector.c -endif - -BL32_RAM_LOCATION := tdram -ifeq (${BL32_RAM_LOCATION}, tsram) - BL32_RAM_LOCATION_ID = SEC_SRAM_ID -else ifeq (${BL32_RAM_LOCATION}, tdram) - BL32_RAM_LOCATION_ID = SEC_DRAM_ID -else - $(error "Unsupported BL32_RAM_LOCATION value") -endif - -# Process flags -$(eval $(call add_define,BL32_RAM_LOCATION_ID)) - -# Do not enable SVE -ENABLE_SVE_FOR_NS := 0 diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h new file mode 100644 index 000000000..d7f77cc78 --- /dev/null +++ b/plat/qemu/qemu/include/platform_def.h @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include +#include +#include + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define PLATFORM_STACK_SIZE 0x1000 + +#if ARM_ARCH_MAJOR == 7 +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#else +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#endif +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ + PLATFORM_CLUSTER1_CORE_COUNT) + +#define QEMU_PRIMARY_CPU 0 + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 + +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET U(1) +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF 2 + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH 4 +#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/* + * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", + * and secure DRAM. + */ +#define SEC_ROM_BASE 0x00000000 +#define SEC_ROM_SIZE 0x00020000 + +#define NS_DRAM0_BASE 0x40000000 +#define NS_DRAM0_SIZE 0x3de00000 + +#define SEC_SRAM_BASE 0x0e000000 +#define SEC_SRAM_SIZE 0x00060000 + +#define SEC_DRAM_BASE 0x0e100000 +#define SEC_DRAM_SIZE 0x00f00000 + +/* Load pageable part of OP-TEE 2MB above secure DRAM base */ +#define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) +#define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 + +/* + * ARM-TF lives in SRAM, partition it here + */ + +#define SHARED_RAM_BASE SEC_SRAM_BASE +#define SHARED_RAM_SIZE 0x00001000 + +#define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE +#define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) +#define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) +#define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ + PLAT_QEMU_HOLD_ENTRY_SIZE) +#define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 +#define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) +#define PLAT_QEMU_HOLD_STATE_WAIT 0 +#define PLAT_QEMU_HOLD_STATE_GO 1 + +#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) +#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) + +/* + * BL1 specific defines. + * + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using + * the current BL1 RW debug size plus a little space for growth. + */ +#define BL1_RO_BASE SEC_ROM_BASE +#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) +#define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) +#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) + +/* + * BL2 specific defines. + * + * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug + * size plus a little space for growth. + */ +#define BL2_BASE (BL31_BASE - 0x25000) +#define BL2_LIMIT BL31_BASE + +/* + * BL3-1 specific defines. + * + * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the + * current BL3-1 debug size plus a little space for growth. + */ +#define BL31_BASE (BL31_LIMIT - 0x20000) +#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) +#define BL31_PROGBITS_LIMIT BL1_RW_BASE + + +/* + * BL3-2 specific defines. + * + * BL3-2 can execute from Secure SRAM, or Secure DRAM. + */ +#define BL32_SRAM_BASE BL_RAM_BASE +#define BL32_SRAM_LIMIT BL31_BASE +#define BL32_DRAM_BASE SEC_DRAM_BASE +#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE) + +#define SEC_SRAM_ID 0 +#define SEC_DRAM_ID 1 + +#if BL32_RAM_LOCATION_ID == SEC_SRAM_ID +# define BL32_MEM_BASE BL_RAM_BASE +# define BL32_MEM_SIZE BL_RAM_SIZE +# define BL32_BASE BL32_SRAM_BASE +# define BL32_LIMIT BL32_SRAM_LIMIT +#elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID +# define BL32_MEM_BASE SEC_DRAM_BASE +# define BL32_MEM_SIZE SEC_DRAM_SIZE +# define BL32_BASE BL32_DRAM_BASE +# define BL32_LIMIT BL32_DRAM_LIMIT +#else +# error "Unsupported BL32_RAM_LOCATION_ID value" +#endif + +#define NS_IMAGE_OFFSET 0x60000000 + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define MAX_MMAP_REGIONS 10 +#define MAX_XLAT_TABLES 6 +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/* + * PL011 related constants + */ +#define UART0_BASE 0x09000000 +#define UART1_BASE 0x09040000 +#define UART0_CLK_IN_HZ 1 +#define UART1_CLK_IN_HZ 1 + +#define PLAT_QEMU_BOOT_UART_BASE UART0_BASE +#define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ + +#define PLAT_QEMU_CRASH_UART_BASE UART1_BASE +#define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ + +#define PLAT_QEMU_CONSOLE_BAUDRATE 115200 + +#define QEMU_FLASH0_BASE 0x04000000 +#define QEMU_FLASH0_SIZE 0x04000000 + +#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE +#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE + +#define DEVICE0_BASE 0x08000000 +#define DEVICE0_SIZE 0x01000000 +#define DEVICE1_BASE 0x09000000 +#define DEVICE1_SIZE 0x00041000 + +/* + * GIC related constants + */ + +#define GICD_BASE 0x8000000 +#define GICC_BASE 0x8010000 +#define GICR_BASE 0x80A0000 + + +#define QEMU_IRQ_SEC_SGI_0 8 +#define QEMU_IRQ_SEC_SGI_1 9 +#define QEMU_IRQ_SEC_SGI_2 10 +#define QEMU_IRQ_SEC_SGI_3 11 +#define QEMU_IRQ_SEC_SGI_4 12 +#define QEMU_IRQ_SEC_SGI_5 13 +#define QEMU_IRQ_SEC_SGI_6 14 +#define QEMU_IRQ_SEC_SGI_7 15 + +/****************************************************************************** + * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 + * interrupts. + *****************************************************************************/ +#define PLATFORM_G1S_PROPS(grp) \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE) + +#define PLATFORM_G0_PROPS(grp) + +/* + * DT related constants + */ +#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE +#define PLAT_QEMU_DT_MAX_SIZE 0x100000 + +/* + * System counter + */ +#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk new file mode 100644 index 000000000..5fda2cd47 --- /dev/null +++ b/plat/qemu/qemu/platform.mk @@ -0,0 +1,190 @@ +# +# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Use the GICv2 driver on QEMU by default +QEMU_USE_GIC_DRIVER := QEMU_GICV2 + +ifeq (${ARM_ARCH_MAJOR},7) +# ARMv7 Qemu support in trusted firmware expects the Cortex-A15 model. +# Qemu Cortex-A15 model does not implement the virtualization extension. +# For this reason, we cannot set ARM_CORTEX_A15=yes and must define all +# the ARMv7 build directives. +MARCH32_DIRECTIVE := -mcpu=cortex-a15 +$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)) +$(eval $(call add_define,ARMV7_SUPPORTS_GENERIC_TIMER)) +# Qemu expects a BL32 boot stage. +NEED_BL32 := yes +endif # ARMv7 + +ifeq (${SPD},opteed) +add-lib-optee := yes +endif +ifeq ($(AARCH32_SP),optee) +add-lib-optee := yes +endif + +include lib/libfdt/libfdt.mk + +ifeq ($(NEED_BL32),yes) +$(eval $(call add_define,QEMU_LOAD_BL32)) +endif + +PLAT_QEMU_PATH := plat/qemu/qemu +PLAT_QEMU_COMMON_PATH := plat/qemu/common +PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ + -I${PLAT_QEMU_COMMON_PATH}/include \ + -I${PLAT_QEMU_PATH}/include \ + -Iinclude/common/tbbr + +ifeq (${ARM_ARCH_MAJOR},8) +PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH} +endif + +PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \ + drivers/arm/pl011/${ARCH}/pl011_console.S + +include lib/xlat_tables_v2/xlat_tables.mk +PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} + +ifneq (${TRUSTED_BOARD_BOOT},0) + + include drivers/auth/mbedtls/mbedtls_crypto.mk + include drivers/auth/mbedtls/mbedtls_x509.mk + + AUTH_SOURCES := drivers/auth/auth_mod.c \ + drivers/auth/crypto_mod.c \ + drivers/auth/img_parser_mod.c \ + drivers/auth/tbbr/tbbr_cot.c + + BL1_SOURCES += ${AUTH_SOURCES} \ + bl1/tbbr/tbbr_img_desc.c \ + plat/common/tbbr/plat_tbbr.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_trusted_boot.c \ + $(PLAT_QEMU_COMMON_PATH)/qemu_rotpk.S + + BL2_SOURCES += ${AUTH_SOURCES} \ + plat/common/tbbr/plat_tbbr.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_trusted_boot.c \ + $(PLAT_QEMU_COMMON_PATH)/qemu_rotpk.S + + ROT_KEY = $(BUILD_PLAT)/rot_key.pem + ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin + + $(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) + + $(BUILD_PLAT)/bl1/qemu_rotpk.o: $(ROTPK_HASH) + $(BUILD_PLAT)/bl2/qemu_rotpk.o: $(ROTPK_HASH) + + certificates: $(ROT_KEY) + + $(ROT_KEY): + @echo " OPENSSL $@" + $(Q)openssl genrsa 2048 > $@ 2>/dev/null + + $(ROTPK_HASH): $(ROT_KEY) + @echo " OPENSSL $@" + $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + openssl dgst -sha256 -binary > $@ 2>/dev/null +endif + +BL1_SOURCES += drivers/io/io_semihosting.c \ + drivers/io/io_storage.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + lib/semihosting/semihosting.c \ + lib/semihosting/${ARCH}/semihosting_call.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ + ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c + +ifeq (${ARM_ARCH_MAJOR},8) +BL1_SOURCES += lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S +else +BL1_SOURCES += lib/cpus/${ARCH}/cortex_a15.S +endif + +BL2_SOURCES += drivers/io/io_semihosting.c \ + drivers/io/io_storage.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + lib/semihosting/semihosting.c \ + lib/semihosting/${ARCH}/semihosting_call.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ + ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \ + common/fdt_fixup.c \ + common/desc_image_load.c + +ifeq ($(add-lib-optee),yes) +BL2_SOURCES += lib/optee/optee_utils.c +endif + +QEMU_GICV2_SOURCES := drivers/arm/gic/v2/gicv2_helpers.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/common/gic_common.c \ + plat/common/plat_gicv2.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_gicv2.c + +QEMU_GICV3_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \ + drivers/arm/gic/v3/gicv3_main.c \ + drivers/arm/gic/common/gic_common.c \ + plat/common/plat_gicv3.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c + +ifeq (${QEMU_USE_GIC_DRIVER}, QEMU_GICV2) +QEMU_GIC_SOURCES := ${QEMU_GICV2_SOURCES} +else ifeq (${QEMU_USE_GIC_DRIVER}, QEMU_GICV3) +QEMU_GIC_SOURCES := ${QEMU_GICV3_SOURCES} +else +$(error "Incorrect GIC driver chosen for QEMU platform") +endif + +ifeq (${ARM_ARCH_MAJOR},8) +BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + plat/common/plat_psci_common.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \ + ${PLAT_QEMU_COMMON_PATH}/topology.c \ + ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \ + ${QEMU_GIC_SOURCES} +endif + +# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images +# in the FIP if the platform requires. +ifneq ($(BL32_EXTRA1),) +$(eval $(call TOOL_ADD_IMG,bl32_extra1,--tos-fw-extra1)) +endif +ifneq ($(BL32_EXTRA2),) +$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2)) +endif + +SEPARATE_CODE_AND_RODATA := 1 +ENABLE_STACK_PROTECTOR := 0 +ifneq ($(ENABLE_STACK_PROTECTOR), 0) + PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c +endif + +BL32_RAM_LOCATION := tdram +ifeq (${BL32_RAM_LOCATION}, tsram) + BL32_RAM_LOCATION_ID = SEC_SRAM_ID +else ifeq (${BL32_RAM_LOCATION}, tdram) + BL32_RAM_LOCATION_ID = SEC_DRAM_ID +else + $(error "Unsupported BL32_RAM_LOCATION value") +endif + +# Process flags +$(eval $(call add_define,BL32_RAM_LOCATION_ID)) + +# Do not enable SVE +ENABLE_SVE_FOR_NS := 0 diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c deleted file mode 100644 index 67f33273f..000000000 --- a/plat/qemu/qemu_bl1_setup.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include - -#include "qemu_private.h" - -/* Data structure which holds the extents of the trusted SRAM for BL1*/ -static meminfo_t bl1_tzram_layout; - - -meminfo_t *bl1_plat_sec_mem_layout(void) -{ - return &bl1_tzram_layout; -} - -/******************************************************************************* - * Perform any BL1 specific platform actions. - ******************************************************************************/ -void bl1_early_platform_setup(void) -{ - /* Initialize the console to provide early debug support */ - qemu_console_init(); - - /* Allow BL1 to see the whole Trusted RAM */ - bl1_tzram_layout.total_base = BL_RAM_BASE; - bl1_tzram_layout.total_size = BL_RAM_SIZE; -} - -/****************************************************************************** - * Perform the very early platform specific architecture setup. This only - * does basic initialization. Later architectural setup (bl1_arch_setup()) - * does not do anything platform specific. - *****************************************************************************/ -#ifdef __aarch64__ -#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__) -#else -#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__) -#endif - -void bl1_plat_arch_setup(void) -{ - QEMU_CONFIGURE_BL1_MMU(bl1_tzram_layout.total_base, - bl1_tzram_layout.total_size, - BL_CODE_BASE, BL1_CODE_END, - BL1_RO_DATA_BASE, BL1_RO_DATA_END, - BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); -} - -void bl1_platform_setup(void) -{ - plat_qemu_io_setup(); -} diff --git a/plat/qemu/qemu_bl2_mem_params_desc.c b/plat/qemu/qemu_bl2_mem_params_desc.c deleted file mode 100644 index a01f2dc91..000000000 --- a/plat/qemu/qemu_bl2_mem_params_desc.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -/******************************************************************************* - * Following descriptor provides BL image/ep information that gets used - * by BL2 to load the images and also subset of this information is - * passed to next BL image. The image loading sequence is managed by - * populating the images in required loading order. The image execution - * sequence is managed by populating the `next_handoff_image_id` with - * the next executable image id. - ******************************************************************************/ -static bl_mem_params_node_t bl2_mem_params_descs[] = { -#ifdef EL3_PAYLOAD_BASE - /* Fill EL3 payload related information (BL31 is EL3 payload) */ - { .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, - entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = EL3_PAYLOAD_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, -#else /* EL3_PAYLOAD_BASE */ -#ifdef __aarch64__ - /* Fill BL31 related information */ - { .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, - entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), -# if DEBUG - .ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL, -# endif - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, - -# ifdef QEMU_LOAD_BL32 - .next_handoff_image_id = BL32_IMAGE_ID, -# else - .next_handoff_image_id = BL33_IMAGE_ID, -# endif - }, -#endif /* __aarch64__ */ -# ifdef QEMU_LOAD_BL32 - -#ifdef __aarch64__ -#define BL32_EP_ATTRIBS (SECURE | EXECUTABLE) -#define BL32_IMG_ATTRIBS 0 -#else -#define BL32_EP_ATTRIBS (SECURE | EXECUTABLE | EP_FIRST_EXE) -#define BL32_IMG_ATTRIBS IMAGE_ATTRIB_PLAT_SETUP -#endif - - /* Fill BL32 related information */ - { .image_id = BL32_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, - entry_point_info_t, BL32_EP_ATTRIBS), - .ep_info.pc = BL32_BASE, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, - image_info_t, BL32_IMG_ATTRIBS), - - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - - .next_handoff_image_id = BL33_IMAGE_ID, - }, - - /* - * Fill BL32 external 1 related information. - * A typical use for extra1 image is with OP-TEE where it is the - * pager image. - */ - { .image_id = BL32_EXTRA1_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, - entry_point_info_t, SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, - image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, - - /* - * Fill BL32 external 2 related information. - * A typical use for extra2 image is with OP-TEE where it is the - * paged image. - */ - { .image_id = BL32_EXTRA2_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, - entry_point_info_t, SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, - image_info_t, IMAGE_ATTRIB_SKIP_LOADING), -#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE) - .image_info.image_base = QEMU_OPTEE_PAGEABLE_LOAD_BASE, - .image_info.image_max_size = QEMU_OPTEE_PAGEABLE_LOAD_SIZE, -#endif - .next_handoff_image_id = INVALID_IMAGE_ID, - }, -# endif /* QEMU_LOAD_BL32 */ - - /* Fill BL33 related information */ - { .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, - entry_point_info_t, NON_SECURE | EXECUTABLE), -# ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, - IMAGE_ATTRIB_SKIP_LOADING), -# else /* PRELOADED_BL33_BASE */ - .ep_info.pc = NS_IMAGE_OFFSET, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, - 0), - .image_info.image_base = NS_IMAGE_OFFSET, - .image_info.image_max_size = NS_DRAM0_BASE + NS_DRAM0_SIZE - - NS_IMAGE_OFFSET, -# endif /* !PRELOADED_BL33_BASE */ - - .next_handoff_image_id = INVALID_IMAGE_ID, - } -#endif /* !EL3_PAYLOAD_BASE */ -}; - -REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c deleted file mode 100644 index 166d2454e..000000000 --- a/plat/qemu/qemu_bl2_setup.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "qemu_private.h" - - -/* Data structure which holds the extents of the trusted SRAM for BL2 */ -static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); - -void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, - u_register_t arg2, u_register_t arg3) -{ - meminfo_t *mem_layout = (void *)arg1; - - /* Initialize the console to provide early debug support */ - qemu_console_init(); - - /* Setup the BL2 memory layout */ - bl2_tzram_layout = *mem_layout; - - plat_qemu_io_setup(); -} - -static void security_setup(void) -{ - /* - * This is where a TrustZone address space controller and other - * security related peripherals, would be configured. - */ -} - -static void update_dt(void) -{ - int ret; - void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE; - - ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE); - if (ret < 0) { - ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret); - return; - } - - if (dt_add_psci_node(fdt)) { - ERROR("Failed to add PSCI Device Tree node\n"); - return; - } - - if (dt_add_psci_cpu_enable_methods(fdt)) { - ERROR("Failed to add PSCI cpu enable methods in Device Tree\n"); - return; - } - - ret = fdt_pack(fdt); - if (ret < 0) - ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret); -} - -void bl2_platform_setup(void) -{ - security_setup(); - update_dt(); - - /* TODO Initialize timer */ -} - -#ifdef __aarch64__ -#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__) -#else -#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__) -#endif - -void bl2_plat_arch_setup(void) -{ - QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base, - bl2_tzram_layout.total_size, - BL_CODE_BASE, BL_CODE_END, - BL_RO_DATA_BASE, BL_RO_DATA_END, - BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); -} - -/******************************************************************************* - * Gets SPSR for BL32 entry - ******************************************************************************/ -static uint32_t qemu_get_spsr_for_bl32_entry(void) -{ -#ifdef __aarch64__ - /* - * The Secure Payload Dispatcher service is responsible for - * setting the SPSR prior to entry into the BL3-2 image. - */ - return 0; -#else - return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, - DISABLE_ALL_EXCEPTIONS); -#endif -} - -/******************************************************************************* - * Gets SPSR for BL33 entry - ******************************************************************************/ -static uint32_t qemu_get_spsr_for_bl33_entry(void) -{ - uint32_t spsr; -#ifdef __aarch64__ - unsigned int mode; - - /* Figure out what mode we enter the non-secure world in */ - mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; - - /* - * TODO: Consider the possibility of specifying the SPSR in - * the FIP ToC and allowing the platform to have a say as - * well. - */ - spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); -#else - spsr = SPSR_MODE32(MODE32_svc, - plat_get_ns_image_entrypoint() & 0x1, - SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); -#endif - return spsr; -} - -static int qemu_bl2_handle_post_image_load(unsigned int image_id) -{ - int err = 0; - bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); -#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE) - bl_mem_params_node_t *pager_mem_params = NULL; - bl_mem_params_node_t *paged_mem_params = NULL; -#endif - - assert(bl_mem_params); - - switch (image_id) { - case BL32_IMAGE_ID: -#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE) - pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); - assert(pager_mem_params); - - paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); - assert(paged_mem_params); - - err = parse_optee_header(&bl_mem_params->ep_info, - &pager_mem_params->image_info, - &paged_mem_params->image_info); - if (err != 0) { - WARN("OPTEE header parse error.\n"); - } - -#if defined(SPD_opteed) - /* - * OP-TEE expect to receive DTB address in x2. - * This will be copied into x2 by dispatcher. - */ - bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE; -#else /* case AARCH32_SP_OPTEE */ - bl_mem_params->ep_info.args.arg0 = - bl_mem_params->ep_info.args.arg1; - bl_mem_params->ep_info.args.arg1 = 0; - bl_mem_params->ep_info.args.arg2 = PLAT_QEMU_DT_BASE; - bl_mem_params->ep_info.args.arg3 = 0; -#endif -#endif - bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry(); - break; - - case BL33_IMAGE_ID: -#ifdef AARCH32_SP_OPTEE - /* AArch32 only core: OP-TEE expects NSec EP in register LR */ - pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); - assert(pager_mem_params); - pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; -#endif - - /* BL33 expects to receive the primary CPU MPID (through r0) */ - bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); - bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry(); - break; - default: - /* Do nothing in default case */ - break; - } - - return err; -} - -/******************************************************************************* - * This function can be used by the platforms to update/use image - * information for given `image_id`. - ******************************************************************************/ -int bl2_plat_handle_post_image_load(unsigned int image_id) -{ - return qemu_bl2_handle_post_image_load(image_id); -} - -uintptr_t plat_get_ns_image_entrypoint(void) -{ - return NS_IMAGE_OFFSET; -} diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c deleted file mode 100644 index 4d36b0391..000000000 --- a/plat/qemu/qemu_bl31_setup.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -#include "qemu_private.h" - -/* - * Placeholder variables for copying the arguments that have been passed to - * BL3-1 from BL2. - */ -static entry_point_info_t bl32_image_ep_info; -static entry_point_info_t bl33_image_ep_info; - -/******************************************************************************* - * Perform any BL3-1 early platform setup. Here is an opportunity to copy - * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before - * they are lost (potentially). This needs to be done before the MMU is - * initialized so that the memory layout can be used while creating page - * tables. BL2 has flushed this information to memory, so we are guaranteed - * to pick up good data. - ******************************************************************************/ -void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, - u_register_t arg2, u_register_t arg3) -{ - /* Initialize the console to provide early debug support */ - qemu_console_init(); - - /* - * Check params passed from BL2 - */ - bl_params_t *params_from_bl2 = (bl_params_t *)arg0; - - assert(params_from_bl2); - assert(params_from_bl2->h.type == PARAM_BL_PARAMS); - assert(params_from_bl2->h.version >= VERSION_2); - - bl_params_node_t *bl_params = params_from_bl2->head; - - /* - * Copy BL33 and BL32 (if present), entry point information. - * They are stored in Secure RAM, in BL2's address space. - */ - while (bl_params) { - if (bl_params->image_id == BL32_IMAGE_ID) - bl32_image_ep_info = *bl_params->ep_info; - - if (bl_params->image_id == BL33_IMAGE_ID) - bl33_image_ep_info = *bl_params->ep_info; - - bl_params = bl_params->next_params_info; - } - - if (!bl33_image_ep_info.pc) - panic(); -} - -void bl31_plat_arch_setup(void) -{ - qemu_configure_mmu_el3(BL31_BASE, (BL31_END - BL31_BASE), - BL_CODE_BASE, BL_CODE_END, - BL_RO_DATA_BASE, BL_RO_DATA_END, - BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); -} - -void bl31_platform_setup(void) -{ - plat_qemu_gic_init(); -} - -unsigned int plat_get_syscnt_freq2(void) -{ - return SYS_COUNTER_FREQ_IN_TICKS; -} - -/******************************************************************************* - * Return a pointer to the 'entry_point_info' structure of the next image - * for the security state specified. BL3-3 corresponds to the non-secure - * image type while BL3-2 corresponds to the secure image type. A NULL - * pointer is returned if the image does not exist. - ******************************************************************************/ -entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) -{ - entry_point_info_t *next_image_info; - - assert(sec_state_is_valid(type)); - next_image_info = (type == NON_SECURE) - ? &bl33_image_ep_info : &bl32_image_ep_info; - /* - * None of the images on the ARM development platforms can have 0x0 - * as the entrypoint - */ - if (next_image_info->pc) - return next_image_info; - else - return NULL; -} diff --git a/plat/qemu/qemu_common.c b/plat/qemu/qemu_common.c deleted file mode 100644 index 56bf9532f..000000000 --- a/plat/qemu/qemu_common.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include - -#include "qemu_private.h" - -#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ - DEVICE0_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#ifdef DEVICE1_BASE -#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ - DEVICE1_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) -#endif - -#ifdef DEVICE2_BASE -#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ - DEVICE2_SIZE, \ - MT_DEVICE | MT_RO | MT_SECURE) -#endif - -#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ - SHARED_RAM_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) - -#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \ - MT_MEMORY | MT_RO | MT_SECURE) - -/* - * Table of regions for various BL stages to map using the MMU. - * This doesn't include TZRAM as the 'mem_layout' argument passed to - * arm_configure_mmu_elx() will give the available subset of that, - */ -#ifdef IMAGE_BL1 -static const mmap_region_t plat_qemu_mmap[] = { - MAP_FLASH0, - MAP_SHARED_RAM, - MAP_DEVICE0, -#ifdef MAP_DEVICE1 - MAP_DEVICE1, -#endif -#ifdef MAP_DEVICE2 - MAP_DEVICE2, -#endif - {0} -}; -#endif -#ifdef IMAGE_BL2 -static const mmap_region_t plat_qemu_mmap[] = { - MAP_FLASH0, - MAP_SHARED_RAM, - MAP_DEVICE0, -#ifdef MAP_DEVICE1 - MAP_DEVICE1, -#endif -#ifdef MAP_DEVICE2 - MAP_DEVICE2, -#endif - MAP_NS_DRAM0, - MAP_BL32_MEM, - {0} -}; -#endif -#ifdef IMAGE_BL31 -static const mmap_region_t plat_qemu_mmap[] = { - MAP_SHARED_RAM, - MAP_DEVICE0, -#ifdef MAP_DEVICE1 - MAP_DEVICE1, -#endif - MAP_BL32_MEM, - {0} -}; -#endif -#ifdef IMAGE_BL32 -static const mmap_region_t plat_qemu_mmap[] = { - MAP_SHARED_RAM, - MAP_DEVICE0, -#ifdef MAP_DEVICE1 - MAP_DEVICE1, -#endif - {0} -}; -#endif - -/******************************************************************************* - * Macro generating the code for the function setting up the pagetables as per - * the platform memory map & initialize the mmu, for the given exception level - ******************************************************************************/ - -#define DEFINE_CONFIGURE_MMU_EL(_el) \ - void qemu_configure_mmu_##_el(unsigned long total_base, \ - unsigned long total_size, \ - unsigned long code_start, \ - unsigned long code_limit, \ - unsigned long ro_start, \ - unsigned long ro_limit, \ - unsigned long coh_start, \ - unsigned long coh_limit) \ - { \ - mmap_add_region(total_base, total_base, \ - total_size, \ - MT_MEMORY | MT_RW | MT_SECURE); \ - mmap_add_region(code_start, code_start, \ - code_limit - code_start, \ - MT_CODE | MT_SECURE); \ - mmap_add_region(ro_start, ro_start, \ - ro_limit - ro_start, \ - MT_RO_DATA | MT_SECURE); \ - mmap_add_region(coh_start, coh_start, \ - coh_limit - coh_start, \ - MT_DEVICE | MT_RW | MT_SECURE); \ - mmap_add(plat_qemu_mmap); \ - init_xlat_tables(); \ - \ - enable_mmu_##_el(0); \ - } - -/* Define EL1 and EL3 variants of the function initialising the MMU */ -#ifdef __aarch64__ -DEFINE_CONFIGURE_MMU_EL(el1) -DEFINE_CONFIGURE_MMU_EL(el3) -#else -DEFINE_CONFIGURE_MMU_EL(svc_mon) -#endif - - diff --git a/plat/qemu/qemu_console.c b/plat/qemu/qemu_console.c deleted file mode 100644 index fec182892..000000000 --- a/plat/qemu/qemu_console.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -static console_pl011_t console; - -void qemu_console_init(void) -{ - (void)console_pl011_register(PLAT_QEMU_BOOT_UART_BASE, - PLAT_QEMU_BOOT_UART_CLK_IN_HZ, - PLAT_QEMU_CONSOLE_BAUDRATE, &console); - - console_set_scope(&console.console, CONSOLE_FLAG_BOOT | - CONSOLE_FLAG_RUNTIME); -} - diff --git a/plat/qemu/qemu_gicv2.c b/plat/qemu/qemu_gicv2.c deleted file mode 100644 index fb566227a..000000000 --- a/plat/qemu/qemu_gicv2.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -static const interrupt_prop_t qemu_interrupt_props[] = { - PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), - PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) -}; - -static const struct gicv2_driver_data plat_gicv2_driver_data = { - .gicd_base = GICD_BASE, - .gicc_base = GICC_BASE, - .interrupt_props = qemu_interrupt_props, - .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), -}; - -void plat_qemu_gic_init(void) -{ - /* Initialize the gic cpu and distributor interfaces */ - gicv2_driver_init(&plat_gicv2_driver_data); - gicv2_distif_init(); - gicv2_pcpu_distif_init(); - gicv2_cpuif_enable(); -} - -void qemu_pwr_gic_on_finish(void) -{ - /* TODO: This setup is needed only after a cold boot */ - gicv2_pcpu_distif_init(); - - /* Enable the gic cpu interface */ - gicv2_cpuif_enable(); -} diff --git a/plat/qemu/qemu_gicv3.c b/plat/qemu/qemu_gicv3.c deleted file mode 100644 index 28572c5ef..000000000 --- a/plat/qemu/qemu_gicv3.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -static const interrupt_prop_t qemu_interrupt_props[] = { - PLATFORM_G1S_PROPS(INTR_GROUP1S), - PLATFORM_G0_PROPS(INTR_GROUP0) -}; - -static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT]; - -static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr) -{ - return (unsigned int)plat_core_pos_by_mpidr(mpidr); -} - -static const gicv3_driver_data_t qemu_gicv3_driver_data = { - .gicd_base = GICD_BASE, - .gicr_base = GICR_BASE, - .interrupt_props = qemu_interrupt_props, - .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), - .rdistif_num = PLATFORM_CORE_COUNT, - .rdistif_base_addrs = qemu_rdistif_base_addrs, - .mpidr_to_core_pos = qemu_mpidr_to_core_pos -}; - -void plat_qemu_gic_init(void) -{ - gicv3_driver_init(&qemu_gicv3_driver_data); - gicv3_distif_init(); - gicv3_rdistif_init(plat_my_core_pos()); - gicv3_cpuif_enable(plat_my_core_pos()); -} - -void qemu_pwr_gic_on_finish(void) -{ - gicv3_rdistif_init(plat_my_core_pos()); - gicv3_cpuif_enable(plat_my_core_pos()); -} diff --git a/plat/qemu/qemu_image_load.c b/plat/qemu/qemu_image_load.c deleted file mode 100644 index 9970d1de7..000000000 --- a/plat/qemu/qemu_image_load.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -/******************************************************************************* - * This function is a wrapper of a common function which flushes the data - * structures so that they are visible in memory for the next BL image. - ******************************************************************************/ -void plat_flush_next_bl_params(void) -{ - flush_bl_params_desc(); -} - -/******************************************************************************* - * This function is a wrapper of a common function which returns the list of - * loadable images. - ******************************************************************************/ -bl_load_info_t *plat_get_bl_image_load_info(void) -{ - return get_bl_load_info_from_mem_params_desc(); -} - -/******************************************************************************* - * This function is a wrapper of a common function which returns the data - * structures of the next BL image. - ******************************************************************************/ -bl_params_t *plat_get_next_bl_params(void) -{ - return get_next_bl_params_from_mem_params_desc(); -} diff --git a/plat/qemu/qemu_io_storage.c b/plat/qemu/qemu_io_storage.c deleted file mode 100644 index 0e81cd199..000000000 --- a/plat/qemu/qemu_io_storage.c +++ /dev/null @@ -1,384 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Semihosting filenames */ -#define BL2_IMAGE_NAME "bl2.bin" -#define BL31_IMAGE_NAME "bl31.bin" -#define BL32_IMAGE_NAME "bl32.bin" -#define BL32_EXTRA1_IMAGE_NAME "bl32_extra1.bin" -#define BL32_EXTRA2_IMAGE_NAME "bl32_extra2.bin" -#define BL33_IMAGE_NAME "bl33.bin" - -#if TRUSTED_BOARD_BOOT -#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt" -#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" -#define SOC_FW_KEY_CERT_NAME "soc_fw_key.crt" -#define TOS_FW_KEY_CERT_NAME "tos_fw_key.crt" -#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt" -#define SOC_FW_CONTENT_CERT_NAME "soc_fw_content.crt" -#define TOS_FW_CONTENT_CERT_NAME "tos_fw_content.crt" -#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt" -#endif /* TRUSTED_BOARD_BOOT */ - - - -/* IO devices */ -static const io_dev_connector_t *fip_dev_con; -static uintptr_t fip_dev_handle; -static const io_dev_connector_t *memmap_dev_con; -static uintptr_t memmap_dev_handle; -static const io_dev_connector_t *sh_dev_con; -static uintptr_t sh_dev_handle; - -static const io_block_spec_t fip_block_spec = { - .offset = PLAT_QEMU_FIP_BASE, - .length = PLAT_QEMU_FIP_MAX_SIZE -}; - -static const io_uuid_spec_t bl2_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, -}; - -static const io_uuid_spec_t bl31_uuid_spec = { - .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, -}; - -static const io_uuid_spec_t bl32_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32, -}; - -static const io_uuid_spec_t bl32_extra1_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, -}; - -static const io_uuid_spec_t bl32_extra2_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, -}; - -static const io_uuid_spec_t bl33_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, -}; - -#if TRUSTED_BOARD_BOOT -static const io_uuid_spec_t tb_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FW_CERT, -}; - -static const io_uuid_spec_t trusted_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_KEY_CERT, -}; - -static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = { - .uuid = UUID_SOC_FW_KEY_CERT, -}; - -static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, -}; - -static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, -}; - -static const io_uuid_spec_t soc_fw_cert_uuid_spec = { - .uuid = UUID_SOC_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t tos_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t nt_fw_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, -}; -#endif /* TRUSTED_BOARD_BOOT */ - -static const io_file_spec_t sh_file_spec[] = { - [BL2_IMAGE_ID] = { - .path = BL2_IMAGE_NAME, - .mode = FOPEN_MODE_RB - }, - [BL31_IMAGE_ID] = { - .path = BL31_IMAGE_NAME, - .mode = FOPEN_MODE_RB - }, - [BL32_IMAGE_ID] = { - .path = BL32_IMAGE_NAME, - .mode = FOPEN_MODE_RB - }, - [BL32_EXTRA1_IMAGE_ID] = { - .path = BL32_EXTRA1_IMAGE_NAME, - .mode = FOPEN_MODE_RB - }, - [BL32_EXTRA2_IMAGE_ID] = { - .path = BL32_EXTRA2_IMAGE_NAME, - .mode = FOPEN_MODE_RB - }, - [BL33_IMAGE_ID] = { - .path = BL33_IMAGE_NAME, - .mode = FOPEN_MODE_RB - }, -#if TRUSTED_BOARD_BOOT - [TRUSTED_BOOT_FW_CERT_ID] = { - .path = TRUSTED_BOOT_FW_CERT_NAME, - .mode = FOPEN_MODE_RB - }, - [TRUSTED_KEY_CERT_ID] = { - .path = TRUSTED_KEY_CERT_NAME, - .mode = FOPEN_MODE_RB - }, - [SOC_FW_KEY_CERT_ID] = { - .path = SOC_FW_KEY_CERT_NAME, - .mode = FOPEN_MODE_RB - }, - [TRUSTED_OS_FW_KEY_CERT_ID] = { - .path = TOS_FW_KEY_CERT_NAME, - .mode = FOPEN_MODE_RB - }, - [NON_TRUSTED_FW_KEY_CERT_ID] = { - .path = NT_FW_KEY_CERT_NAME, - .mode = FOPEN_MODE_RB - }, - [SOC_FW_CONTENT_CERT_ID] = { - .path = SOC_FW_CONTENT_CERT_NAME, - .mode = FOPEN_MODE_RB - }, - [TRUSTED_OS_FW_CONTENT_CERT_ID] = { - .path = TOS_FW_CONTENT_CERT_NAME, - .mode = FOPEN_MODE_RB - }, - [NON_TRUSTED_FW_CONTENT_CERT_ID] = { - .path = NT_FW_CONTENT_CERT_NAME, - .mode = FOPEN_MODE_RB - }, -#endif /* TRUSTED_BOARD_BOOT */ -}; - - - -static int open_fip(const uintptr_t spec); -static int open_memmap(const uintptr_t spec); - -struct plat_io_policy { - uintptr_t *dev_handle; - uintptr_t image_spec; - int (*check)(const uintptr_t spec); -}; - -/* By default, ARM platforms load images from the FIP */ -static const struct plat_io_policy policies[] = { - [FIP_IMAGE_ID] = { - &memmap_dev_handle, - (uintptr_t)&fip_block_spec, - open_memmap - }, - [BL2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl2_uuid_spec, - open_fip - }, - [BL31_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl31_uuid_spec, - open_fip - }, - [BL32_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_uuid_spec, - open_fip - }, - [BL32_EXTRA1_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra1_uuid_spec, - open_fip - }, - [BL32_EXTRA2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra2_uuid_spec, - open_fip - }, - [BL33_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl33_uuid_spec, - open_fip - }, -#if TRUSTED_BOARD_BOOT - [TRUSTED_BOOT_FW_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tb_fw_cert_uuid_spec, - open_fip - }, - [TRUSTED_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&trusted_key_cert_uuid_spec, - open_fip - }, - [SOC_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&soc_fw_key_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_key_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_key_cert_uuid_spec, - open_fip - }, - [SOC_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&soc_fw_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_cert_uuid_spec, - open_fip - }, -#endif /* TRUSTED_BOARD_BOOT */ -}; - -static int open_fip(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - /* See if a Firmware Image Package is available */ - result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); - if (result == 0) { - result = io_open(fip_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using FIP\n"); - io_close(local_image_handle); - } - } - return result; -} - -static int open_memmap(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); - if (result == 0) { - result = io_open(memmap_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using Memmap\n"); - io_close(local_image_handle); - } - } - return result; -} - -static int open_semihosting(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - /* See if the file exists on semi-hosting.*/ - result = io_dev_init(sh_dev_handle, (uintptr_t)NULL); - if (result == 0) { - result = io_open(sh_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using Semi-hosting IO\n"); - io_close(local_image_handle); - } - } - return result; -} - -void plat_qemu_io_setup(void) -{ - int io_result; - - io_result = register_io_dev_fip(&fip_dev_con); - assert(io_result == 0); - - io_result = register_io_dev_memmap(&memmap_dev_con); - assert(io_result == 0); - - /* Open connections to devices and cache the handles */ - io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, - &fip_dev_handle); - assert(io_result == 0); - - io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, - &memmap_dev_handle); - assert(io_result == 0); - - /* Register the additional IO devices on this platform */ - io_result = register_io_dev_sh(&sh_dev_con); - assert(io_result == 0); - - /* Open connections to devices and cache the handles */ - io_result = io_dev_open(sh_dev_con, (uintptr_t)NULL, &sh_dev_handle); - assert(io_result == 0); - - /* Ignore improbable errors in release builds */ - (void)io_result; -} - -static int get_alt_image_source(unsigned int image_id, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int result = open_semihosting((const uintptr_t)&sh_file_spec[image_id]); - - if (result == 0) { - *dev_handle = sh_dev_handle; - *image_spec = (uintptr_t)&sh_file_spec[image_id]; - } - - return result; -} - -/* - * Return an IO device handle and specification which can be used to access - * an image. Use this to enforce platform load policy - */ -int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int result; - const struct plat_io_policy *policy; - - assert(image_id < ARRAY_SIZE(policies)); - - policy = &policies[image_id]; - result = policy->check(policy->image_spec); - if (result == 0) { - *image_spec = policy->image_spec; - *dev_handle = *(policy->dev_handle); - } else { - VERBOSE("Trying alternative IO\n"); - result = get_alt_image_source(image_id, dev_handle, image_spec); - } - - return result; -} diff --git a/plat/qemu/qemu_pm.c b/plat/qemu/qemu_pm.c deleted file mode 100644 index a199688df..000000000 --- a/plat/qemu/qemu_pm.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include -#include -#include -#include - -#include "qemu_private.h" - -/* - * The secure entry point to be used on warm reset. - */ -static unsigned long secure_entrypoint; - -/* Make composite power state parameter till power level 0 */ -#if PSCI_EXTENDED_STATE_ID - -#define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ - (((lvl0_state) << PSTATE_ID_SHIFT) | \ - ((type) << PSTATE_TYPE_SHIFT)) -#else -#define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ - (((lvl0_state) << PSTATE_ID_SHIFT) | \ - ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ - ((type) << PSTATE_TYPE_SHIFT)) -#endif /* PSCI_EXTENDED_STATE_ID */ - - -#define qemu_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ - (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ - qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) - - - -/* - * The table storing the valid idle power states. Ensure that the - * array entries are populated in ascending order of state-id to - * enable us to use binary search during power state validation. - * The table must be terminated by a NULL entry. - */ -static const unsigned int qemu_pm_idle_states[] = { - /* State-id - 0x01 */ - qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, - MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), - /* State-id - 0x02 */ - qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, - MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), - /* State-id - 0x22 */ - qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, - MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), - 0, -}; - -/******************************************************************************* - * Platform handler called to check the validity of the power state - * parameter. The power state parameter has to be a composite power state. - ******************************************************************************/ -static int qemu_validate_power_state(unsigned int power_state, - psci_power_state_t *req_state) -{ - unsigned int state_id; - int i; - - assert(req_state); - - /* - * Currently we are using a linear search for finding the matching - * entry in the idle power state array. This can be made a binary - * search if the number of entries justify the additional complexity. - */ - for (i = 0; !!qemu_pm_idle_states[i]; i++) { - if (power_state == qemu_pm_idle_states[i]) - break; - } - - /* Return error if entry not found in the idle state array */ - if (!qemu_pm_idle_states[i]) - return PSCI_E_INVALID_PARAMS; - - i = 0; - state_id = psci_get_pstate_id(power_state); - - /* Parse the State ID and populate the state info parameter */ - while (state_id) { - req_state->pwr_domain_state[i++] = state_id & - PLAT_LOCAL_PSTATE_MASK; - state_id >>= PLAT_LOCAL_PSTATE_WIDTH; - } - - return PSCI_E_SUCCESS; -} - -/******************************************************************************* - * Platform handler called to check the validity of the non secure - * entrypoint. - ******************************************************************************/ -static int qemu_validate_ns_entrypoint(uintptr_t entrypoint) -{ - /* - * Check if the non secure entrypoint lies within the non - * secure DRAM. - */ - if ((entrypoint >= NS_DRAM0_BASE) && - (entrypoint < (NS_DRAM0_BASE + NS_DRAM0_SIZE))) - return PSCI_E_SUCCESS; - return PSCI_E_INVALID_ADDRESS; -} - -/******************************************************************************* - * Platform handler called when a CPU is about to enter standby. - ******************************************************************************/ -static void qemu_cpu_standby(plat_local_state_t cpu_state) -{ - - assert(cpu_state == PLAT_LOCAL_STATE_RET); - - /* - * Enter standby state - * dsb is good practice before using wfi to enter low power states - */ - dsb(); - wfi(); -} - -/******************************************************************************* - * Platform handler called when a power domain is about to be turned on. The - * mpidr determines the CPU to be turned on. - ******************************************************************************/ -static int qemu_pwr_domain_on(u_register_t mpidr) -{ - int rc = PSCI_E_SUCCESS; - unsigned pos = plat_core_pos_by_mpidr(mpidr); - uint64_t *hold_base = (uint64_t *)PLAT_QEMU_HOLD_BASE; - - hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO; - sev(); - - return rc; -} - -/******************************************************************************* - * Platform handler called when a power domain is about to be turned off. The - * target_state encodes the power state that each level should transition to. - ******************************************************************************/ -void qemu_pwr_domain_off(const psci_power_state_t *target_state) -{ - assert(0); -} - -/******************************************************************************* - * Platform handler called when a power domain is about to be suspended. The - * target_state encodes the power state that each level should transition to. - ******************************************************************************/ -void qemu_pwr_domain_suspend(const psci_power_state_t *target_state) -{ - assert(0); -} - -/******************************************************************************* - * Platform handler called when a power domain has just been powered on after - * being turned off earlier. The target_state encodes the low power state that - * each level has woken up from. - ******************************************************************************/ -void qemu_pwr_domain_on_finish(const psci_power_state_t *target_state) -{ - assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == - PLAT_LOCAL_STATE_OFF); - - qemu_pwr_gic_on_finish(); -} - -/******************************************************************************* - * Platform handler called when a power domain has just been powered on after - * having been suspended earlier. The target_state encodes the low power state - * that each level has woken up from. - ******************************************************************************/ -void qemu_pwr_domain_suspend_finish(const psci_power_state_t *target_state) -{ - assert(0); -} - -/******************************************************************************* - * Platform handlers to shutdown/reboot the system - ******************************************************************************/ -static void __dead2 qemu_system_off(void) -{ - ERROR("QEMU System Off: operation not handled.\n"); - panic(); -} - -static void __dead2 qemu_system_reset(void) -{ - ERROR("QEMU System Reset: operation not handled.\n"); - panic(); -} - -static const plat_psci_ops_t plat_qemu_psci_pm_ops = { - .cpu_standby = qemu_cpu_standby, - .pwr_domain_on = qemu_pwr_domain_on, - .pwr_domain_off = qemu_pwr_domain_off, - .pwr_domain_suspend = qemu_pwr_domain_suspend, - .pwr_domain_on_finish = qemu_pwr_domain_on_finish, - .pwr_domain_suspend_finish = qemu_pwr_domain_suspend_finish, - .system_off = qemu_system_off, - .system_reset = qemu_system_reset, - .validate_power_state = qemu_validate_power_state, - .validate_ns_entrypoint = qemu_validate_ns_entrypoint -}; - -int plat_setup_psci_ops(uintptr_t sec_entrypoint, - const plat_psci_ops_t **psci_ops) -{ - uintptr_t *mailbox = (void *) PLAT_QEMU_TRUSTED_MAILBOX_BASE; - - *mailbox = sec_entrypoint; - secure_entrypoint = (unsigned long) sec_entrypoint; - *psci_ops = &plat_qemu_psci_pm_ops; - - return 0; -} diff --git a/plat/qemu/qemu_private.h b/plat/qemu/qemu_private.h deleted file mode 100644 index 71ea4de10..000000000 --- a/plat/qemu/qemu_private.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef QEMU_PRIVATE_H -#define QEMU_PRIVATE_H - -#include - -void qemu_configure_mmu_svc_mon(unsigned long total_base, - unsigned long total_size, - unsigned long code_start, unsigned long code_limit, - unsigned long ro_start, unsigned long ro_limit, - unsigned long coh_start, unsigned long coh_limit); - -void qemu_configure_mmu_el1(unsigned long total_base, unsigned long total_size, - unsigned long code_start, unsigned long code_limit, - unsigned long ro_start, unsigned long ro_limit, - unsigned long coh_start, unsigned long coh_limit); - -void qemu_configure_mmu_el3(unsigned long total_base, unsigned long total_size, - unsigned long code_start, unsigned long code_limit, - unsigned long ro_start, unsigned long ro_limit, - unsigned long coh_start, unsigned long coh_limit); - -void plat_qemu_io_setup(void); -unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); - -void qemu_console_init(void); - -void plat_qemu_gic_init(void); -void qemu_pwr_gic_on_finish(void); - -#endif /* QEMU_PRIVATE_H */ diff --git a/plat/qemu/qemu_rotpk.S b/plat/qemu/qemu_rotpk.S deleted file mode 100644 index 5d1b83f40..000000000 --- a/plat/qemu/qemu_rotpk.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - - .global qemu_rotpk_hash - .global qemu_rotpk_hash_end -qemu_rotpk_hash: - /* DER header */ - .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 - .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 - /* SHA256 */ - .incbin ROTPK_HASH -qemu_rotpk_hash_end: diff --git a/plat/qemu/qemu_stack_protector.c b/plat/qemu/qemu_stack_protector.c deleted file mode 100644 index c226158ad..000000000 --- a/plat/qemu/qemu_stack_protector.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL) - -u_register_t plat_get_stack_protector_canary(void) -{ - /* - * Ideally, a random number should be returned instead of the - * combination of a timer's value and a compile-time constant. - * As the virt platform does not have any random number generator, - * this is better than nothing but not necessarily really secure. - */ - return RANDOM_CANARY_VALUE ^ read_cntpct_el0(); -} - diff --git a/plat/qemu/qemu_trusted_boot.c b/plat/qemu/qemu_trusted_boot.c deleted file mode 100644 index 1ef7e431b..000000000 --- a/plat/qemu/qemu_trusted_boot.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -extern char qemu_rotpk_hash[], qemu_rotpk_hash_end[]; - -int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, - unsigned int *flags) -{ - *key_ptr = qemu_rotpk_hash; - *key_len = qemu_rotpk_hash_end - qemu_rotpk_hash; - *flags = ROTPK_IS_HASH; - - return 0; -} - -int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) -{ - *nv_ctr = 0; - - return 0; -} - -int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) -{ - return 1; -} - -int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) -{ - return get_mbedtls_heap_helper(heap_addr, heap_size); -} diff --git a/plat/qemu/sp_min/sp_min-qemu.mk b/plat/qemu/sp_min/sp_min-qemu.mk deleted file mode 100644 index e93a0c231..000000000 --- a/plat/qemu/sp_min/sp_min-qemu.mk +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -BL32_SOURCES += plat/qemu/sp_min/sp_min_setup.c \ - plat/qemu/aarch32/plat_helpers.S \ - plat/qemu/qemu_pm.c \ - plat/qemu/topology.c - -BL32_SOURCES += lib/cpus/aarch32/aem_generic.S \ - lib/cpus/aarch32/cortex_a15.S - -BL32_SOURCES += plat/common/aarch32/platform_mp_stack.S \ - plat/common/plat_psci_common.c \ - plat/common/plat_gicv2.c - - -BL32_SOURCES += drivers/arm/gic/v2/gicv2_helpers.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/common/gic_common.c diff --git a/plat/qemu/sp_min/sp_min_setup.c b/plat/qemu/sp_min/sp_min_setup.c deleted file mode 100644 index 7ec657b79..000000000 --- a/plat/qemu/sp_min/sp_min_setup.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../qemu_private.h" - -#if RESET_TO_SP_MIN -#error qemu does not support RESET_TO_SP_MIN -#endif - -static entry_point_info_t bl33_image_ep_info; - -/****************************************************************************** - * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 - * interrupts. - *****************************************************************************/ -#define PLATFORM_G1S_PROPS(grp) \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL) - -#define PLATFORM_G0_PROPS(grp) - -static const interrupt_prop_t stih410_interrupt_props[] = { - PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), - PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) -}; - -static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; - -static const struct gicv2_driver_data plat_gicv2_driver_data = { - .gicd_base = GICD_BASE, - .gicc_base = GICC_BASE, - .interrupt_props = stih410_interrupt_props, - .interrupt_props_num = ARRAY_SIZE(stih410_interrupt_props), - .target_masks = target_mask_array, - .target_masks_num = ARRAY_SIZE(target_mask_array), -}; - -/******************************************************************************* - * Return a pointer to the 'entry_point_info' structure of the next image for - * the security state specified. BL33 corresponds to the non-secure image type - * while BL32 corresponds to the secure image type. A NULL pointer is returned - * if the image does not exist. - ******************************************************************************/ -entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) -{ - entry_point_info_t *next_image_info = &bl33_image_ep_info; - - /* - * None of the images on the ARM development platforms can have 0x0 - * as the entrypoint - */ - if (next_image_info->pc) - return next_image_info; - else - return NULL; -} - -void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, - u_register_t arg2, u_register_t arg3) -{ - bl_params_t *params_from_bl2 = (bl_params_t *)arg0; - - /* Initialize the console to provide early debug support */ - qemu_console_init(); - - ERROR("qemu sp_min, console init\n"); - /* - * Check params passed from BL2 - */ - assert(params_from_bl2); - assert(params_from_bl2->h.type == PARAM_BL_PARAMS); - assert(params_from_bl2->h.version >= VERSION_2); - - bl_params_node_t *bl_params = params_from_bl2->head; - - /* - * Copy BL33 entry point information from BL2's address space. - */ - while (bl_params) { - if (bl_params->image_id == BL33_IMAGE_ID) - bl33_image_ep_info = *bl_params->ep_info; - - bl_params = bl_params->next_params_info; - } - - if (!bl33_image_ep_info.pc) - panic(); -} - -void sp_min_plat_arch_setup(void) -{ - qemu_configure_mmu_svc_mon(BL32_RO_BASE, BL32_END - BL32_RO_BASE, - BL_CODE_BASE, BL_CODE_END, - BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); - -} - -void sp_min_platform_setup(void) -{ - /* Initialize the gic cpu and distributor interfaces */ - gicv2_driver_init(&plat_gicv2_driver_data); - gicv2_distif_init(); - gicv2_pcpu_distif_init(); - gicv2_cpuif_enable(); -} - -unsigned int plat_get_syscnt_freq2(void) -{ - return SYS_COUNTER_FREQ_IN_TICKS; -} - -void sp_min_plat_fiq_handler(uint32_t id) -{ - VERBOSE("[sp_min] interrupt #%d\n", id); -} diff --git a/plat/qemu/topology.c b/plat/qemu/topology.c deleted file mode 100644 index 6352706e9..000000000 --- a/plat/qemu/topology.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include - -#include "qemu_private.h" - -/* The power domain tree descriptor */ -static unsigned char power_domain_tree_desc[] = { - /* Number of root nodes */ - PLATFORM_CLUSTER_COUNT, - /* Number of children for the first node */ - PLATFORM_CLUSTER0_CORE_COUNT, - /* Number of children for the second node */ - PLATFORM_CLUSTER1_CORE_COUNT, -}; - -/******************************************************************************* - * This function returns the ARM default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) - return -1; - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) - return -1; - - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) - return -1; - - return plat_qemu_calc_core_pos(mpidr); -} -- cgit v1.2.3 From 9a006ad10509cf158089470ef713f7edde073eaf Mon Sep 17 00:00:00 2001 From: Radoslaw Biernacki Date: Thu, 17 May 2018 22:19:35 +0200 Subject: qemu: Simplify the image size calculation Patch introduce the macro NS_IMAGE_MAX_SIZE to simplify the image size calculation. Use of additional parenthesis removes the possibility of improper calculations due nested macro expansion for subtraction. In case of platforms with DRAM window over 32bits, patch also removes potential problems with type casting, as meminfo.image_size is uint32_t but macro calculations were done in 64bit space. Signed-off-by: Radoslaw Biernacki Change-Id: I2d05a2d9dd6000dba6114df53262995cf85af018 --- plat/qemu/common/qemu_bl2_mem_params_desc.c | 5 ++--- plat/qemu/qemu/include/platform_def.h | 3 ++- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/qemu/common/qemu_bl2_mem_params_desc.c b/plat/qemu/common/qemu_bl2_mem_params_desc.c index a01f2dc91..f8b9066df 100644 --- a/plat/qemu/common/qemu_bl2_mem_params_desc.c +++ b/plat/qemu/common/qemu_bl2_mem_params_desc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -139,8 +139,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), .image_info.image_base = NS_IMAGE_OFFSET, - .image_info.image_max_size = NS_DRAM0_BASE + NS_DRAM0_SIZE - - NS_IMAGE_OFFSET, + .image_info.image_max_size = NS_IMAGE_MAX_SIZE, # endif /* !PRELOADED_BL33_BASE */ .next_handoff_image_id = INVALID_IMAGE_ID, diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h index d7f77cc78..a90573712 100644 --- a/plat/qemu/qemu/include/platform_def.h +++ b/plat/qemu/qemu/include/platform_def.h @@ -165,7 +165,8 @@ # error "Unsupported BL32_RAM_LOCATION_ID value" #endif -#define NS_IMAGE_OFFSET 0x60000000 +#define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) +#define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) -- cgit v1.2.3 From 382ddb3dd46ada0d7439d2d95bb0de3b3abb6d9d Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 20 Sep 2019 08:40:54 +0800 Subject: rockchip: Fix typo for TF content text The 'txet' should be 'text'. Change-Id: I2217a1adf50c3b86f3087b83c77d9291b280627c Signed-off-by: Kever Yang --- plat/rockchip/px30/include/platform_def.h | 2 +- plat/rockchip/rk3288/include/shared/bl32_param.h | 2 +- plat/rockchip/rk3328/include/platform_def.h | 2 +- plat/rockchip/rk3368/include/platform_def.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/rockchip/px30/include/platform_def.h b/plat/rockchip/px30/include/platform_def.h index c101cdc81..8e70a7031 100644 --- a/plat/rockchip/px30/include/platform_def.h +++ b/plat/rockchip/px30/include/platform_def.h @@ -69,7 +69,7 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF txet, ro, rw, Size: 512KB */ +/* TF text, ro, rw, Size: 512KB */ #define TZRAM_BASE (0x0) #define TZRAM_SIZE (0x80000) diff --git a/plat/rockchip/rk3288/include/shared/bl32_param.h b/plat/rockchip/rk3288/include/shared/bl32_param.h index 743dad41b..950e41d66 100644 --- a/plat/rockchip/rk3288/include/shared/bl32_param.h +++ b/plat/rockchip/rk3288/include/shared/bl32_param.h @@ -10,7 +10,7 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF txet, ro, rw, Size: 2MB */ +/* TF text, ro, rw, Size: 2MB */ #define TZRAM_BASE (0x0) #define TZRAM_SIZE (0x200000) diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h index 3104d9fcb..1120fb84c 100644 --- a/plat/rockchip/rk3328/include/platform_def.h +++ b/plat/rockchip/rk3328/include/platform_def.h @@ -66,7 +66,7 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF txet, ro, rw, Size: 512KB */ +/* TF text, ro, rw, Size: 512KB */ #define TZRAM_BASE (0x0) #define TZRAM_SIZE (0x80000) diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h index 7b3cc6eba..6c2cffa8c 100644 --- a/plat/rockchip/rk3368/include/platform_def.h +++ b/plat/rockchip/rk3368/include/platform_def.h @@ -67,7 +67,7 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF txet, ro, rw, Size: 512KB */ +/* TF text, ro, rw, Size: 512KB */ #define TZRAM_BASE (0x0) #define TZRAM_SIZE (0x80000) -- cgit v1.2.3 From 0aad563c74807195cc7fe2208d17e2d889157f1e Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 19 Sep 2019 10:37:36 +0800 Subject: rockchip: Update BL31_BASE to 0x40000 Rockchip platform is using the first 1MB of DRAM as secure ram space, and there is a vendor loader who loads and runs the BL31/BL32/BL33, this loader is usually load by SoC BootRom to the start addres of DRAM, we need to reserve enough space for this loader so that it doesn't need to do the relocate when loading the BL31. eg. We use U-Boot SPL to load ATF BL31 and U-Boot proper as BL33, the SPL TEXT BASE is offset 0 of DRAM which is decide by Bootrom; if we update the BL31_BASE to offset 0x40000(256KB), then the 0~0x40000 should be enough for SPL and no need to do the relocate while the space size 0x10000(64KB) may not enough for SPL. After this update, the BL31 can use the rest 768KB of the first 1MB, which is also enough, and the loader who is using BL31 elf file can support this update without any change. Change-Id: I66dc685594d77f10f9a49c3be015fd6729250ece Signed-off-by: Kever Yang --- plat/rockchip/px30/include/platform_def.h | 2 +- plat/rockchip/rk3288/include/shared/bl32_param.h | 6 +++--- plat/rockchip/rk3328/include/platform_def.h | 2 +- plat/rockchip/rk3368/include/platform_def.h | 2 +- plat/rockchip/rk3399/include/shared/bl31_param.h | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/plat/rockchip/px30/include/platform_def.h b/plat/rockchip/px30/include/platform_def.h index 8e70a7031..9dccab82b 100644 --- a/plat/rockchip/px30/include/platform_def.h +++ b/plat/rockchip/px30/include/platform_def.h @@ -79,7 +79,7 @@ /* * Put BL3-1 at the top of the Trusted RAM */ -#define BL31_BASE (TZRAM_BASE + 0x10000) +#define BL31_BASE (TZRAM_BASE + 0x40000) #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) /******************************************************************************* diff --git a/plat/rockchip/rk3288/include/shared/bl32_param.h b/plat/rockchip/rk3288/include/shared/bl32_param.h index 950e41d66..ffdb2f38c 100644 --- a/plat/rockchip/rk3288/include/shared/bl32_param.h +++ b/plat/rockchip/rk3288/include/shared/bl32_param.h @@ -10,9 +10,9 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF text, ro, rw, Size: 2MB */ +/* TF text, ro, rw, Size: 1MB */ #define TZRAM_BASE (0x0) -#define TZRAM_SIZE (0x200000) +#define TZRAM_SIZE (0x100000) /******************************************************************************* * BL32 specific defines. @@ -20,7 +20,7 @@ /* * Put BL32 at the top of the Trusted RAM */ -#define BL32_BASE (TZRAM_BASE + 0x100000) +#define BL32_BASE (TZRAM_BASE + 0x40000) #define BL32_LIMIT (TZRAM_BASE + TZRAM_SIZE) #endif /* BL32_PARAM_H */ diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h index 1120fb84c..baac12d3b 100644 --- a/plat/rockchip/rk3328/include/platform_def.h +++ b/plat/rockchip/rk3328/include/platform_def.h @@ -76,7 +76,7 @@ /* * Put BL3-1 at the top of the Trusted RAM */ -#define BL31_BASE (TZRAM_BASE + 0x10000) +#define BL31_BASE (TZRAM_BASE + 0x40000) #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) /******************************************************************************* diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h index 6c2cffa8c..9334a83ae 100644 --- a/plat/rockchip/rk3368/include/platform_def.h +++ b/plat/rockchip/rk3368/include/platform_def.h @@ -77,7 +77,7 @@ /* * Put BL3-1 at the top of the Trusted RAM */ -#define BL31_BASE (TZRAM_BASE + 0x10000) +#define BL31_BASE (TZRAM_BASE + 0x40000) #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) /******************************************************************************* diff --git a/plat/rockchip/rk3399/include/shared/bl31_param.h b/plat/rockchip/rk3399/include/shared/bl31_param.h index e7f2226cd..6e7e8ba09 100644 --- a/plat/rockchip/rk3399/include/shared/bl31_param.h +++ b/plat/rockchip/rk3399/include/shared/bl31_param.h @@ -20,7 +20,7 @@ /* * Put BL31 at the top of the Trusted RAM */ -#define BL31_BASE (TZRAM_BASE + 0x1000) +#define BL31_BASE (TZRAM_BASE + 0x40000) #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) #endif /* BL31_PARAM_H */ -- cgit v1.2.3 From 019b03a3001a61f7d42fa70abee6c284f542b2d2 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Fri, 20 Sep 2019 09:13:14 +0100 Subject: Fix MTE support from causing unused variable warnings assert() calls are removed in release builds, and if that assert call is the only use of a variable, an unused variable warning will be triggered in a release build. This patch fixes this problem when CTX_INCLUDE_MTE_REGS by not using an intermediate variable to store the results of get_armv8_5_mte_support(). Change-Id: I529e10ec0b2c8650d2c3ab52c4f0cecc0b3a670e Signed-off-by: Justin Chadwell --- lib/el3_runtime/aarch64/context_mgmt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index a05ee5a6e..d65e02d5e 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -142,11 +142,11 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is * set. */ - unsigned int mte = get_armv8_5_mte_support(); #if CTX_INCLUDE_MTE_REGS - assert(mte == MTE_IMPLEMENTED_ELX); + assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX); scr_el3 |= SCR_ATA_BIT; #else + unsigned int mte = get_armv8_5_mte_support(); if (mte == MTE_IMPLEMENTED_EL0) { /* * Can enable MTE across both worlds as no MTE registers are -- cgit v1.2.3 From 2966defa542d1efbf77d697b4fcdd79742ddd423 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Fri, 12 Jul 2019 11:37:07 +0100 Subject: doc: Render Marvell platform documents The documentation for Marvell platforms was not included in the rendered document output until now because, while it was mostly valid RST format, the files were saved with a .txt extension. This patch corrects some RST formatting errors, creates a document tree (index page) for the Marvell documents, and adds the Marvell subtree to the main index. Change-Id: Id7d4ac37eded636f8f62322a153e1e5f652ff51a Signed-off-by: Paul Beesley --- docs/plat/index.rst | 1 + docs/plat/marvell/build.rst | 254 ++++++++++++++++++++++++++ docs/plat/marvell/build.txt | 194 -------------------- docs/plat/marvell/index.rst | 14 ++ docs/plat/marvell/misc/mvebu-a8k-addr-map.rst | 49 +++++ docs/plat/marvell/misc/mvebu-a8k-addr-map.txt | 47 ----- docs/plat/marvell/misc/mvebu-amb.rst | 58 ++++++ docs/plat/marvell/misc/mvebu-amb.txt | 45 ----- docs/plat/marvell/misc/mvebu-ccu.rst | 33 ++++ docs/plat/marvell/misc/mvebu-ccu.txt | 23 --- docs/plat/marvell/misc/mvebu-io-win.rst | 46 +++++ docs/plat/marvell/misc/mvebu-io-win.txt | 35 ---- docs/plat/marvell/misc/mvebu-iob.rst | 52 ++++++ docs/plat/marvell/misc/mvebu-iob.txt | 40 ---- docs/plat/marvell/porting.rst | 163 +++++++++++++++++ docs/plat/marvell/porting.txt | 118 ------------ 16 files changed, 670 insertions(+), 502 deletions(-) create mode 100644 docs/plat/marvell/build.rst delete mode 100644 docs/plat/marvell/build.txt create mode 100644 docs/plat/marvell/index.rst create mode 100644 docs/plat/marvell/misc/mvebu-a8k-addr-map.rst delete mode 100644 docs/plat/marvell/misc/mvebu-a8k-addr-map.txt create mode 100644 docs/plat/marvell/misc/mvebu-amb.rst delete mode 100644 docs/plat/marvell/misc/mvebu-amb.txt create mode 100644 docs/plat/marvell/misc/mvebu-ccu.rst delete mode 100644 docs/plat/marvell/misc/mvebu-ccu.txt create mode 100644 docs/plat/marvell/misc/mvebu-io-win.rst delete mode 100644 docs/plat/marvell/misc/mvebu-io-win.txt create mode 100644 docs/plat/marvell/misc/mvebu-iob.rst delete mode 100644 docs/plat/marvell/misc/mvebu-iob.txt create mode 100644 docs/plat/marvell/porting.rst delete mode 100644 docs/plat/marvell/porting.txt diff --git a/docs/plat/index.rst b/docs/plat/index.rst index 595141372..eaeee84f3 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -12,6 +12,7 @@ Platform Ports imx8m intel-stratix10 ls1043a + marvell/index meson-gxbb meson-gxl mt8183 diff --git a/docs/plat/marvell/build.rst b/docs/plat/marvell/build.rst new file mode 100644 index 000000000..c8923e43a --- /dev/null +++ b/docs/plat/marvell/build.rst @@ -0,0 +1,254 @@ +TF-A Build Instructions for Marvell Platforms +============================================= + +This section describes how to compile the Trusted Firmware-A (TF-A) project for Marvell's platforms. + +Build Instructions +------------------ +(1) Set the cross compiler + + .. code:: shell + + > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu- + +(2) Set path for FIP images: + +Set U-Boot image path (relatively to TF-A root or absolute path) + + .. code:: shell + + > export BL33=path/to/u-boot.bin + +For example: if U-Boot project (and its images) is located at ``~/project/u-boot``, +BL33 should be ``~/project/u-boot/u-boot.bin`` + + .. note:: + + *u-boot.bin* should be used and not *u-boot-spl.bin* + +Set MSS/SCP image path (mandatory only for Armada80x0) + + .. code:: shell + + > export SCP_BL2=path/to/mrvl_scp_bl2*.img + +(3) Armada-37x0 build requires WTP tools installation. + +See below in the section "Tools and external components installation". +Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3 + + .. code:: shell + + > sudo apt-get install gcc-arm-linux-gnueabi + +(4) Clean previous build residuals (if any) + + .. code:: shell + + > make distclean + +(5) Build TF-A + +There are several build options: + +- DEBUG + + Default is without debug information (=0). in order to enable it use ``DEBUG=1``. + Must be disabled when building UART recovery images due to current console driver + implementation that is not compatible with Xmodem protocol used for boot image download. + +- LOG_LEVEL + + Defines the level of logging which will be purged to the default output port. + + LOG_LEVEL_NONE 0 + LOG_LEVEL_ERROR 10 + LOG_LEVEL_NOTICE 20 + LOG_LEVEL_WARNING 30 + LOG_LEVEL_INFO 40 + LOG_LEVEL_VERBOSE 50 + +- USE_COHERENT_MEM + + This flag determines whether to include the coherent memory region in the + BL memory map or not. + +- LLC_ENABLE + + Flag defining the LLC (L3) cache state. The cache is enabled by default (``LLC_ENABLE=1``). + +- MARVELL_SECURE_BOOT + + Build trusted(=1)/non trusted(=0) image, default is non trusted. + +- BLE_PATH + + Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds. + The parameter is optional, its default value is ``plat/marvell/a8k/common/ble``. + +- MV_DDR_PATH + + For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0, + it is used for ddr_tool build. + + Usage example: MV_DDR_PATH=path/to/mv_ddr + + The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr + sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter + is necessary for A37x0. + + For the mv_ddr source location, check the section "Tools and external components installation" + +- DDR_TOPOLOGY + + For Armada37x0 only, the DDR topology map index/name, default is 0. + + Supported Options: + - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) + - DDR4 1CS (1): DB-88F3720-DDR4-Modular (512MB) + - DDR3 2CS (2): EspressoBIN V3-V5 (1GB) + - DDR4 2CS (3): DB-88F3720-DDR4-Modular (4GB) + - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB) + - DDR4 1CS (5): EspressoBin V7 (1GB) + - DDR4 2CS (6): EspressoBin V7 (2GB) + - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB + +- CLOCKSPRESET + + For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency, + default is CPU_800_DDR_800. + + - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz + - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz + - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz + - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz + +- BOOTDEV + + For Armada37x0 only, the flash boot device, default is ``SPINOR``. + + Currently, Armada37x0 only supports ``SPINOR``, ``SPINAND``, ``EMMCNORM`` and ``SATA``: + + - SPINOR - SPI NOR flash boot + - SPINAND - SPI NAND flash boot + - EMMCNORM - eMMC Download Mode + + Download boot loader or program code from eMMC flash into CM3 or CA53 + Requires full initialization and command sequence + + - SATA - SATA device boot + +- PARTNUM + + For Armada37x0 only, the boot partition number, default is 0. + + To boot from eMMC, the value should be aligned with the parameter in + U-Boot with name of ``CONFIG_SYS_MMC_ENV_PART``, whose value by default is + 1. For details about CONFIG_SYS_MMC_ENV_PART, please refer to the U-Boot + build instructions. + +- WTMI_IMG + + For Armada37x0 only, the path of the WTMI image can point to an image which + does nothing, an image which supports EFUSE or a customized CM3 firmware + binary. The default image is wtmi.bin that built from sources in WTP + folder, which is the next option. If the default image is OK, then this + option should be skipped. + +- WTP + + For Armada37x0 only, use this parameter to point to wtptools source code + directory, which can be found as a3700_utils.zip in the release. Usage + example: ``WTP=/path/to/a3700_utils`` + + For example, in order to build the image in debug mode with log level up to 'notice' level run + + .. code:: shell + + > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT= all fip + + And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level, + the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS, + the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command + line is as following + + .. code:: shell + + > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \ + MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip + + Supported MARVELL_PLATFORM are: + - a3700 (for both A3720 DB and EspressoBin) + - a70x0 + - a70x0_amc (for AMC board) + - a80x0 + - a80x0_mcbin (for MacciatoBin) + +Special Build Flags +-------------------- + +- PLAT_RECOVERY_IMAGE_ENABLE + When set this option to enable secondary recovery function when build atf. + In order to build UART recovery image this operation should be disabled for + a70x0 and a80x0 because of hardware limitation (boot from secondary image + can interrupt UART recovery process). This MACRO definition is set in + ``plat/marvell/a8k/common/include/platform_def.h`` file. + +For more information about build options, please refer to section +'Summary of build options' in the :ref:`User Guide`. + + +Build output +------------ +Marvell's TF-A compilation generates 7 files: + + - ble.bin - BLe image + - bl1.bin - BL1 image + - bl2.bin - BL2 image + - bl31.bin - BL31 image + - fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images) + - boot-image.bin - TF-A image (contains BL1 and FIP images) + - flash-image.bin - Image which contains boot-image.bin and SPL image. + Should be placed on the boot flash/device. + + +Tools and external components installation +------------------------------------------ + +Armada37x0 Builds require installation of 3 components +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +(1) ARM cross compiler capable of building images for the service CPU (CM3). + This component is usually included in the Linux host packages. + On Debian/Ubuntu hosts the default GNU ARM tool chain can be installed + using the following command + + .. code:: shell + + > sudo apt-get install gcc-arm-linux-gnueabi + + Only if required, the default tool chain prefix ``arm-linux-gnueabi-`` can be + overwritten using the environment variable ``CROSS_CM3``. + Example for BASH shell + + .. code:: shell + + > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi + +(2) DDR initialization library sources (mv_ddr) available at the following repository + (use the "mv_ddr-armada-atf-mainline" branch): + + https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git + +(3) Armada3700 tools available at the following repository (use the latest release branch): + + https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git + +Armada70x0 and Armada80x0 Builds require installation of an additional component +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +(1) DDR initialization library sources (mv_ddr) available at the following repository + (use the "mv_ddr-armada-atf-mainline" branch): + + https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git + diff --git a/docs/plat/marvell/build.txt b/docs/plat/marvell/build.txt deleted file mode 100644 index 7b75196fa..000000000 --- a/docs/plat/marvell/build.txt +++ /dev/null @@ -1,194 +0,0 @@ -TF-A Build Instructions -====================== - -This section describes how to compile the ARM Trusted Firmware (TF-A) project for Marvell's platforms. - -Build Instructions ------------------- -(1) Set the cross compiler:: - - > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu- - -(2) Set path for FIP images: - - Set U-Boot image path (relatively to TF-A root or absolute path):: - - > export BL33=path/to/u-boot.bin - - For example: if U-Boot project (and its images) is located at ~/project/u-boot, - BL33 should be ~/project/u-boot/u-boot.bin - - .. note:: - - u-boot.bin should be used and not u-boot-spl.bin - - Set MSS/SCP image path (mandatory only for Armada80x0):: - - > export SCP_BL2=path/to/mrvl_scp_bl2*.img - -(3) Armada-37x0 build requires WTP tools installation. - - See below in the section "Tools and external components installation". - Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3:: - - > sudo apt-get install gcc-arm-linux-gnueabi - -(4) Clean previous build residuals (if any):: - - > make distclean - -(5) Build TF-A: - - There are several build options: - - - DEBUG: default is without debug information (=0). in order to enable it use DEBUG=1 - Must be disabled when building UART recovery images due to current console driver - implementation that is not compatible with Xmodem protocol used for boot image download. - - - LOG_LEVEL: defines the level of logging which will be purged to the default output port. - - LOG_LEVEL_NONE 0 - LOG_LEVEL_ERROR 10 - LOG_LEVEL_NOTICE 20 - LOG_LEVEL_WARNING 30 - LOG_LEVEL_INFO 40 - LOG_LEVEL_VERBOSE 50 - - - USE_COHERENT_MEM: This flag determines whether to include the coherent memory region in the - BL memory map or not. - - - LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1). - - - MARVELL_SECURE_BOOT: build trusted(=1)/non trusted(=0) image, default is non trusted. - - - BLE_PATH: - Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds. - The parameter is optional, its default value is "plat/marvell/a8k/common/ble". - - - MV_DDR_PATH: - For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0, - it is used for ddr_tool build. - Usage example: MV_DDR_PATH=path/to/mv_ddr - The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr - sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter - is necessary for A37x0. - For the mv_ddr source location, check the section "Tools and external components installation" - - - DDR_TOPOLOGY: For Armada37x0 only, the DDR topology map index/name, default is 0. - Supported Options: - - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) - - DDR4 1CS (1): DB-88F3720-DDR4-Modular (512MB) - - DDR3 2CS (2): EspressoBIN V3-V5 (1GB) - - DDR4 2CS (3): DB-88F3720-DDR4-Modular (4GB) - - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB) - - DDR4 1CS (5): EspressoBin V7 (1GB) - - DDR4 2CS (6): EspressoBin V7 (2GB) - - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB - - - CLOCKSPRESET: For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency, - default is CPU_800_DDR_800. - - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz - - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz - - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz - - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz - - - BOOTDEV: For Armada37x0 only, the flash boot device, default is SPINOR, - Currently, Armada37x0 only supports SPINOR, SPINAND, EMMCNORM and SATA: - - - SPINOR - SPI NOR flash boot - - SPINAND - SPI NAND flash boot - - EMMCNORM - eMMC Download Mode - Download boot loader or program code from eMMC flash into CM3 or CA53 - Requires full initialization and command sequence - - SATA - SATA device boot - - - PARTNUM: For Armada37x0 only, the boot partition number, default is 0. To boot from eMMC, the value - should be aligned with the parameter in U-Boot with name of CONFIG_SYS_MMC_ENV_PART, whose - value by default is 1. - For details about CONFIG_SYS_MMC_ENV_PART, please refer to the U-Boot build instructions. - - - WTMI_IMG: For Armada37x0 only, the path of the WTMI image can point to an image which does - nothing, an image which supports EFUSE or a customized CM3 firmware binary. The default image - is wtmi.bin that built from sources in WTP folder, which is the next option. If the default - image is OK, then this option should be skipped. - - - WTP: For Armada37x0 only, use this parameter to point to wtptools source code directory, which - can be found as a3700_utils.zip in the release. - Usage example: WTP=/path/to/a3700_utils - - For example, in order to build the image in debug mode with log level up to 'notice' level run:: - - > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT= all fip - - And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level, - the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS, - the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command - line is as following:: - - > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \ - MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip - - Supported MARVELL_PLATFORM are: - - a3700 (for both A3720 DB and EspressoBin) - - a70x0 - - a70x0_amc (for AMC board) - - a80x0 - - a80x0_mcbin (for MacciatoBin) - -Special Build Flags --------------------- - - PLAT_RECOVERY_IMAGE_ENABLE: When set this option to enable secondary recovery function when build - atf. In order to build UART recovery image this operation should be disabled for a70x0 and a80x0 - because of hardware limitation (boot from secondary image can interrupt UART recovery process). - This MACRO definition is set in plat/marvell/a8k/common/include/platform_def.h file - -(for more information about build options, please refer to section 'Summary of build options' in TF-A user-guide: - https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/user-guide.md) - - -Build output -------------- -Marvell's TF-A compilation generates 7 files: - - ble.bin - BLe image - - bl1.bin - BL1 image - - bl2.bin - BL2 image - - bl31.bin - BL31 image - - fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images) - - boot-image.bin - TF-A image (contains BL1 and FIP images) - - flash-image.bin - Image which contains boot-image.bin and SPL image; - should be placed on the boot flash/device. - - -Tools and external components installation -========================================== - -Armada37x0 Builds require installation of 3 components -------------------------------------------------------- - -(1) ARM cross compiler capable of building images for the service CPU (CM3). - This component is usually included in the Linux host packages. - On Debian/Ubuntu hosts the default GNU ARM tool chain can be installed - using the following command:: - - > sudo apt-get install gcc-arm-linux-gnueabi - - Only if required, the default tool chain prefix "arm-linux-gnueabi-" can be - overwritten using the environment variable CROSS_CM3. - Example for BASH shell:: - - > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi - -(2) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv_ddr-armada-atf-mainline" branch):: - https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git - -(3) Armada3700 tools available at the following repository (use the latest release branch):: - https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git - -Armada70x0 and Armada80x0 Builds require installation of an additional component --------------------------------------------------------------------------------- - -(1) DDR initialization library sources (mv_ddr) available at the following repository - (use the "mv_ddr-armada-atf-mainline" branch):: - https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git - diff --git a/docs/plat/marvell/index.rst b/docs/plat/marvell/index.rst new file mode 100644 index 000000000..89ebdc0a4 --- /dev/null +++ b/docs/plat/marvell/index.rst @@ -0,0 +1,14 @@ +Marvell +======= + +.. toctree:: + :maxdepth: 1 + :caption: Contents + + build + porting + misc/mvebu-a8k-addr-map + misc/mvebu-amb + misc/mvebu-ccu + misc/mvebu-io-win + misc/mvebu-iob diff --git a/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst b/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst new file mode 100644 index 000000000..e88a4582b --- /dev/null +++ b/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst @@ -0,0 +1,49 @@ +Address decoding flow and address translation units of Marvell Armada 8K SoC family +=================================================================================== + +:: + + +--------------------------------------------------------------------------------------------------+ + | +-------------+ +--------------+ | + | | Memory +----- DRAM CS | | + |+------------+ +-----------+ +-----------+ | Controller | +--------------+ | + || AP DMA | | | | | +-------------+ | + || SD/eMMC | | CA72 CPUs | | AP MSS | +-------------+ | + || MCI-0/1 | | | | | | Memory | | + |+------+-----+ +--+--------+ +--------+--+ +------------+ | Controller | +-------------+ | + | | | | | +----- Translaton | |AP | | + | | | | | | +-------------+ |Configuration| | + | | | +-----+ +-------------------------Space | | + | | | +-------------+ | CCU | +-------------+ | + | | | | MMU +---------+ Windows | +-----------+ +-------------+ | + | | +-| translation | | Lookup +---- +--------- AP SPI | | + | | +-------------+ | | | | +-------------+ | + | | +-------------+ | | | IO | +-------------+ | + | +------------| SMMU +---------+ | | Windows +--------- AP MCI0/1 | | + | | translation | +------------+ | Lookup | +-------------+ | + | +---------+---+ | | +-------------+ | + | - | | +--------- AP STM | | + | +----------------- | | +-------------+ | + | AP | | +-+---------+ | + +---------------------------------------------------------------|----------------------------------+ + +-------------|-------------------------------------------------|----------------------------------+ + | CP | +-------------+ +------+-----+ +-------------------+ | + | | | | | +------- SB CFG Space | | + | | | DIOB | | | +-------------------+ | + | | | Windows ----------------- IOB | +-------------------+ | + | | | Control | | Windows +------| SB PCIe-0 - PCIe2 | | + | | | | | Lookup | +-------------------+ | + | | +------+------+ | | +-------------------+ | + | | | | +------+ SB NAND | | + | | | +------+-----+ +-------------------+ | + | | | | | + | | | | | + | +------------------+ +------------+ +------+-----+ +-------------------+ | + | | Network Engine | | | | +------- SB SPI-0/SPI-1 | | + | | Security Engine | | PCIe, MSS | | RUNIT | +-------------------+ | + | | SATA, USB | | DMA | | Windows | +-------------------+ | + | | SD/eMMC | | | | Lookup +------- SB Device Bus | | + | | TDM, I2C | | | | | +-------------------+ | + | +------------------+ +------------+ +------------+ | + | | + +--------------------------------------------------------------------------------------------------+ diff --git a/docs/plat/marvell/misc/mvebu-a8k-addr-map.txt b/docs/plat/marvell/misc/mvebu-a8k-addr-map.txt deleted file mode 100644 index 586e8b732..000000000 --- a/docs/plat/marvell/misc/mvebu-a8k-addr-map.txt +++ /dev/null @@ -1,47 +0,0 @@ -Address decoding flow and address translation units of Marvell Armada 8K SoC family - -+--------------------------------------------------------------------------------------------------+ -| +-------------+ +--------------+ | -| | Memory +----- DRAM CS | | -|+------------+ +-----------+ +-----------+ | Controller | +--------------+ | -|| AP DMA | | | | | +-------------+ | -|| SD/eMMC | | CA72 CPUs | | AP MSS | +-------------+ | -|| MCI-0/1 | | | | | | Memory | | -|+------+-----+ +--+--------+ +--------+--+ +------------+ | Controller | +-------------+ | -| | | | | +----- Translaton | |AP | | -| | | | | | +-------------+ |Configuration| | -| | | +-----+ +-------------------------Space | | -| | | +-------------+ | CCU | +-------------+ | -| | | | MMU +---------+ Windows | +-----------+ +-------------+ | -| | +-| translation | | Lookup +---- +--------- AP SPI | | -| | +-------------+ | | | | +-------------+ | -| | +-------------+ | | | IO | +-------------+ | -| +------------| SMMU +---------+ | | Windows +--------- AP MCI0/1 | | -| | translation | +------------+ | Lookup | +-------------+ | -| +---------+---+ | | +-------------+ | -| - | | +--------- AP STM | | -| +----------------- | | +-------------+ | -| AP | | +-+---------+ | -+---------------------------------------------------------------|----------------------------------+ -+-------------|-------------------------------------------------|----------------------------------+ -| CP | +-------------+ +------+-----+ +-------------------+ | -| | | | | +------- SB CFG Space | | -| | | DIOB | | | +-------------------+ | -| | | Windows ----------------- IOB | +-------------------+ | -| | | Control | | Windows +------| SB PCIe-0 - PCIe2 | | -| | | | | Lookup | +-------------------+ | -| | +------+------+ | | +-------------------+ | -| | | | +------+ SB NAND | | -| | | +------+-----+ +-------------------+ | -| | | | | -| | | | | -| +------------------+ +------------+ +------+-----+ +-------------------+ | -| | Network Engine | | | | +------- SB SPI-0/SPI-1 | | -| | Security Engine | | PCIe, MSS | | RUNIT | +-------------------+ | -| | SATA, USB | | DMA | | Windows | +-------------------+ | -| | SD/eMMC | | | | Lookup +------- SB Device Bus | | -| | TDM, I2C | | | | | +-------------------+ | -| +------------------+ +------------+ +------------+ | -| | -+--------------------------------------------------------------------------------------------------+ - diff --git a/docs/plat/marvell/misc/mvebu-amb.rst b/docs/plat/marvell/misc/mvebu-amb.rst new file mode 100644 index 000000000..d734003d6 --- /dev/null +++ b/docs/plat/marvell/misc/mvebu-amb.rst @@ -0,0 +1,58 @@ +AMB - AXI MBUS address decoding +=============================== + +AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs. + +The Runit offers a second level of address windows lookup. It is used to map +transaction towards the CD BootROM, SPI0, SPI1 and Device bus (NOR). + +The Runit contains eight configurable windows. Each window defines a contiguous, +address space and the properties associated with that address space. + +:: + + Unit Bank ATTR + Device-Bus DEV_BOOT_CS 0x2F + DEV_CS0 0x3E + DEV_CS1 0x3D + DEV_CS2 0x3B + DEV_CS3 0x37 + SPI-0 SPI_A_CS0 0x1E + SPI_A_CS1 0x5E + SPI_A_CS2 0x9E + SPI_A_CS3 0xDE + SPI_A_CS4 0x1F + SPI_A_CS5 0x5F + SPI_A_CS6 0x9F + SPI_A_CS7 0xDF + SPI SPI_B_CS0 0x1A + SPI_B_CS1 0x5A + SPI_B_CS2 0x9A + SPI_B_CS3 0xDA + BOOT_ROM BOOT_ROM 0x1D + UART UART 0x01 + +Mandatory functions +------------------- + +- marvell_get_amb_memory_map + Returns the AMB windows configuration and the number of windows + +Mandatory structures +-------------------- + +- amb_memory_map + Array that include the configuration of the windows. Every window/entry is a + struct which has 2 parameters: + + - Base address of the window + - Attribute of the window + +Examples +-------- + +.. code:: c + + struct addr_map_win amb_memory_map[] = { + {0xf900, AMB_DEV_CS0_ID}, + }; diff --git a/docs/plat/marvell/misc/mvebu-amb.txt b/docs/plat/marvell/misc/mvebu-amb.txt deleted file mode 100644 index 2a7a41ec9..000000000 --- a/docs/plat/marvell/misc/mvebu-amb.txt +++ /dev/null @@ -1,45 +0,0 @@ -AMB - AXI MBUS address decoding -------------------------------- - -AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs. - -- The Runit offers a second level of address windows lookup. It is used to map transaction towards -the CD BootROM, SPI0, SPI1 and Device bus (NOR). -- The Runit contains eight configurable windows. Each window defines a contiguous, -address space and the properties associated with that address space. - -Unit Bank ATTR -Device-Bus DEV_BOOT_CS 0x2F - DEV_CS0 0x3E - DEV_CS1 0x3D - DEV_CS2 0x3B - DEV_CS3 0x37 -SPI-0 SPI_A_CS0 0x1E - SPI_A_CS1 0x5E - SPI_A_CS2 0x9E - SPI_A_CS3 0xDE - SPI_A_CS4 0x1F - SPI_A_CS5 0x5F - SPI_A_CS6 0x9F - SPI_A_CS7 0xDF -SPI1 SPI_B_CS0 0x1A - SPI_B_CS1 0x5A - SPI_B_CS2 0x9A - SPI_B_CS3 0xDA -BOOT_ROM BOOT_ROM 0x1D -UART UART 0x01 - -Mandatory functions: - - marvell_get_amb_memory_map - returns the AMB windows configuration and the number of windows - -Mandatory structures: - amb_memory_map - Array that include the configuration of the windows - every window/entry is a struct which has 2 parameters: - - base address of the window - - Attribute of the window - -Examples: - struct addr_map_win amb_memory_map[] = { - {0xf900, AMB_DEV_CS0_ID}, - }; diff --git a/docs/plat/marvell/misc/mvebu-ccu.rst b/docs/plat/marvell/misc/mvebu-ccu.rst new file mode 100644 index 000000000..5bac11faf --- /dev/null +++ b/docs/plat/marvell/misc/mvebu-ccu.rst @@ -0,0 +1,33 @@ +Marvell CCU address decoding bindings +===================================== + +CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs. + +The CCU node includes a description of the address decoding configuration. + +Mandatory functions +------------------- + +- marvell_get_ccu_memory_map + Return the CCU windows configuration and the number of windows of the + specific AP. + +Mandatory structures +-------------------- + +- ccu_memory_map + Array that includes the configuration of the windows. Every window/entry is + a struct which has 3 parameters: + + - Base address of the window + - Size of the window + - Target-ID of the window + +Example +------- + +.. code:: c + + struct addr_map_win ccu_memory_map[] = { + {0x00000000f2000000, 0x00000000e000000, IO_0_TID}, /* IO window */ + }; diff --git a/docs/plat/marvell/misc/mvebu-ccu.txt b/docs/plat/marvell/misc/mvebu-ccu.txt deleted file mode 100644 index 976402761..000000000 --- a/docs/plat/marvell/misc/mvebu-ccu.txt +++ /dev/null @@ -1,23 +0,0 @@ -Marvell CCU address decoding bindings -===================================== - -CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs. - -The CCU node includes a description of the address decoding configuration. - -Mandatory functions: - - marvell_get_ccu_memory_map - return the CCU windows configuration and the number of windows - of the specific AP. - -Mandatory structures: - ccu_memory_map - Array that includes the configuration of the windows - every window/entry is a struct which has 3 parameters: - - Base address of the window - - Size of the window - - Target-ID of the window - -Example: - struct addr_map_win ccu_memory_map[] = { - {0x00000000f2000000, 0x00000000e000000, IO_0_TID}, /* IO window */ - }; diff --git a/docs/plat/marvell/misc/mvebu-io-win.rst b/docs/plat/marvell/misc/mvebu-io-win.rst new file mode 100644 index 000000000..52845ca02 --- /dev/null +++ b/docs/plat/marvell/misc/mvebu-io-win.rst @@ -0,0 +1,46 @@ +Marvell IO WIN address decoding bindings +======================================== + +IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. + +The IO WIN includes a description of the address decoding configuration. + +Transactions that are decoded by CCU windows as IO peripheral, have an additional +layer of decoding. This additional address decoding layer defines one of the +following targets: + +- **0x0** = BootRom +- **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream) +- **0x2** = SPI direct access +- **0x3** = PCIe registers +- **0x4** = MCI Port +- **0x5** = PCIe port + +Mandatory functions +------------------- + +- marvell_get_io_win_memory_map + Returns the IO windows configuration and the number of windows of the + specific AP. + +Mandatory structures +-------------------- + +- io_win_memory_map + Array that include the configuration of the windows. Every window/entry is + a struct which has 3 parameters: + + - Base address of the window + - Size of the window + - Target-ID of the window + +Example +------- + +.. code:: c + + struct addr_map_win io_win_memory_map[] = { + {0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/ + {0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/ + {0x00000000f6000000, 0x000000000100000, MCIPHY_TID}, /* MCI window 1Mb for PHY-reg*/ + }; diff --git a/docs/plat/marvell/misc/mvebu-io-win.txt b/docs/plat/marvell/misc/mvebu-io-win.txt deleted file mode 100644 index c83ad1fd2..000000000 --- a/docs/plat/marvell/misc/mvebu-io-win.txt +++ /dev/null @@ -1,35 +0,0 @@ -Marvell IO WIN address decoding bindings -===================================== - -IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. - -The IO WIN includes a description of the address decoding configuration. - -Transactions that are decoded by CCU windows as IO peripheral, have an additional -layer of decoding. This additional address decoding layer defines one of the -following targets: - 0x0 = BootRom - 0x1 = STM (Serial Trace Macro-cell, a programmer's port into trace stream) - 0x2 = SPI direct access - 0x3 = PCIe registers - 0x4 = MCI Port - 0x5 = PCIe port - -Mandatory functions: - - marvell_get_io_win_memory_map - returns the IO windows configuration and the number of windows - of the specific AP. - -Mandatory structures: - io_win_memory_map - Array that include the configuration of the windows - every window/entry is a struct which has 3 parameters: - - Base address of the window - - Size of the window - - Target-ID of the window - -Example: - struct addr_map_win io_win_memory_map[] = { - {0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/ - {0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/ - {0x00000000f6000000, 0x000000000100000, MCIPHY_TID}, /* MCI window 1Mb for PHY-reg*/ - }; diff --git a/docs/plat/marvell/misc/mvebu-iob.rst b/docs/plat/marvell/misc/mvebu-iob.rst new file mode 100644 index 000000000..d02a7e84c --- /dev/null +++ b/docs/plat/marvell/misc/mvebu-iob.rst @@ -0,0 +1,52 @@ +Marvell IOB address decoding bindings +===================================== + +IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs. + +The IOB includes a description of the address decoding configuration. + +IOB supports up to n (in CP110 n=24) windows for external memory transaction. +When a transaction passes through the IOB, its address is compared to each of +the enabled windows. If there is a hit and it passes the security checks, it is +advanced to the target port. + +Mandatory functions +------------------- + +- marvell_get_iob_memory_map + Returns the IOB windows configuration and the number of windows + +Mandatory structures +-------------------- + +- iob_memory_map + Array that includes the configuration of the windows. Every window/entry is + a struct which has 3 parameters: + + - Base address of the window + - Size of the window + - Target-ID of the window + +Target ID options +----------------- + +- **0x0** = Internal configuration space +- **0x1** = MCI0 +- **0x2** = PEX1_X1 +- **0x3** = PEX2_X1 +- **0x4** = PEX0_X4 +- **0x5** = NAND flash +- **0x6** = RUNIT (NOR/SPI/BootRoom) +- **0x7** = MCI1 + +Example +------- + +.. code:: c + + struct addr_map_win iob_memory_map[] = { + {0x00000000f7000000, 0x0000000001000000, PEX1_TID}, /* PEX1_X1 window */ + {0x00000000f8000000, 0x0000000001000000, PEX2_TID}, /* PEX2_X1 window */ + {0x00000000f6000000, 0x0000000001000000, PEX0_TID}, /* PEX0_X4 window */ + {0x00000000f9000000, 0x0000000001000000, NAND_TID} /* NAND window */ + }; diff --git a/docs/plat/marvell/misc/mvebu-iob.txt b/docs/plat/marvell/misc/mvebu-iob.txt deleted file mode 100644 index 97ec09d0e..000000000 --- a/docs/plat/marvell/misc/mvebu-iob.txt +++ /dev/null @@ -1,40 +0,0 @@ -Marvell IOB address decoding bindings -===================================== - -IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs. - -The IOB includes a description of the address decoding configuration. - -IOB supports up to n (in CP110 n=24) windows for external memory transaction. -When a transaction passes through the IOB, its address is compared to each of -the enabled windows. If there is a hit and it passes the security checks, it is -advanced to the target port. - -Mandatory functions: - - marvell_get_iob_memory_map - returns the IOB windows configuration and the number of windows - -Mandatory structures: - iob_memory_map - Array that include the configuration of the windows - every window/entry is a struct which has 3 parameters: - - Base address of the window - - Size of the window - - Target-ID of the window - -Target ID options: - - 0x0 = Internal configuration space - - 0x1 = MCI0 - - 0x2 = PEX1_X1 - - 0x3 = PEX2_X1 - - 0x4 = PEX0_X4 - - 0x5 = NAND flash - - 0x6 = RUNIT (NOR/SPI/BootRoom) - - 0x7 = MCI1 - -Example: - struct addr_map_win iob_memory_map[] = { - {0x00000000f7000000, 0x0000000001000000, PEX1_TID}, /* PEX1_X1 window */ - {0x00000000f8000000, 0x0000000001000000, PEX2_TID}, /* PEX2_X1 window */ - {0x00000000f6000000, 0x0000000001000000, PEX0_TID}, /* PEX0_X4 window */ - {0x00000000f9000000, 0x0000000001000000, NAND_TID} /* NAND window */ - }; diff --git a/docs/plat/marvell/porting.rst b/docs/plat/marvell/porting.rst new file mode 100644 index 000000000..8fc1c1f6d --- /dev/null +++ b/docs/plat/marvell/porting.rst @@ -0,0 +1,163 @@ +TF-A Porting Guide for Marvell Platforms +======================================== + +This section describes how to port TF-A to a customer board, assuming that the +SoC being used is already supported in TF-A. + + +Source Code Structure +--------------------- + +- The customer platform specific code shall reside under ``plat/marvell//_cust`` + (e.g. 'plat/marvell/a8k/a7040_cust'). +- The platform name for build purposes is called ``_cust`` (e.g. ``a7040_cust``). +- The build system will reuse all files from within the soc directory, and take only the porting + files from the customer platform directory. + +Files that require porting are located at ``plat/marvell//_cust`` directory. + + +Armada-70x0/Armada-80x0 Porting +------------------------------- + +SoC Physical Address Map (marvell_plat_config.c) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This file describes the SoC physical memory mapping to be used for the CCU, +IOWIN, AXI-MBUS and IOB address decode units (Refer to the functional spec for +more details). + +In most cases, using the default address decode windows should work OK. + +In cases where a special physical address map is needed (e.g. Special size for +PCIe MEM windows, large memory mapped SPI flash...), then porting of the SoC +memory map is required. + +.. note:: + For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please + refer to the SoC functional spec, and under + ``docs/marvell/misc/mvebu-[ccu/iob/amb/io-win].txt`` files. + +boot loader recovery (marvell_plat_config.c) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Background: + + Boot rom can skip the current image and choose to boot from next position if a + specific value (``0xDEADB002``) is returned by the ble main function. This + feature is used for boot loader recovery by booting from a valid flash-image + saved in next position on flash (e.g. address 2M in SPI flash). + + Supported options to implement the skip request are: + - GPIO + - I2C + - User defined + +- Porting: + + Under marvell_plat_config.c, implement struct skip_image that includes + specific board parameters. + + .. warning:: + To disable this feature make sure the struct skip_image is not implemented. + +- Example: + +In A7040-DB specific implementation +(``plat/marvell/a8k/a70x0/board/marvell_plat_config.c``), the image skip is +implemented using GPIO: mpp 33 (SW5). + +Before resetting the board make sure there is a valid image on the next flash +address: + + -tftp [valid address] flash-image.bin + -sf update [valid address] 0x2000000 [size] + +Press reset and keep pressing the button connected to the chosen GPIO pin. A +skip image request message is printed on the screen and boot rom boots from the +saved image at the next position. + +DDR Porting (dram_port.c) +~~~~~~~~~~~~~~~~~~~~~~~~~ + +This file defines the dram topology and parameters of the target board. + +The DDR code is part of the BLE component, which is an extension of ARM Trusted +Firmware (TF-A). + +The DDR driver called mv_ddr is released separately apart from TF-A sources. + +The BLE and consequently, the DDR init code is executed at the early stage of +the boot process. + +Each supported platform of the TF-A has its own DDR porting file called +dram_port.c located at ``atf/plat/marvell/a8k//board`` directory. + +Please refer to '/doc/porting_guide.txt' for detailed +porting description. + +The build target directory is "build//release/ble". + +Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Background: + Some of the comphy's parameters value depend on the HW connection between + the SoC and the PHY. Every board type has specific HW characteristics like + wire length. Due to those differences some comphy parameters vary between + board types. Therefore each board type can have its own list of values for + all relevant comphy parameters. The PHY porting layer specifies which + parameters need to be suited and the board designer should provide relevant + values. + + .. seealso:: + For XFI/SFI comphy type there is procedure "rx_training" which eases + process of suiting some of the parameters. Please see :ref:`uboot_cmd` + section: rx_training. + + The PHY porting layer simplifies updating static values per board type, + which are now grouped in one place. + + .. note:: + The parameters for the same type of comphy may vary even for the same + board type, it is because the lanes from comphy-x to some PHY may have + different HW characteristic than lanes from comphy-y to the same + (multiplexed) or other PHY. + +- Porting: + The porting layer for PHY was introduced in TF-A. There is one file + ``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the + defaults. Those default parameters are used only if there is no appropriate + phy-porting-layer.h file under: ``plat/marvell///board/phy-porting-layer.h``. If the phy-porting-layer.h + exists, the phy-default-porting-layer.h is not going to be included. + + .. warning:: + Not all comphy types are already reworked to support the PHY porting + layer, currently the porting layer is supported for XFI/SFI and SATA + comphy types. + + The easiest way to prepare the PHY porting layer for custom board is to copy + existing example to a new platform: + + - cp ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell///board/phy-porting-layer.h" + - adjust relevant parameters or + - if different comphy index is used for specific feature, move it to proper table entry and then adjust. + + .. note:: + The final table size with comphy parameters can be different, depending + on the CP module count for given SoC type. + +- Example: + Example porting layer for armada-8040-db is under: + ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` + + .. note:: + If there is no PHY porting layer for new platform (missing + phy-porting-layer.h), the default values are used + (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is + warned: + + .. warning:: + "Using default comphy parameters - it may be required to suit them for + your board". diff --git a/docs/plat/marvell/porting.txt b/docs/plat/marvell/porting.txt deleted file mode 100644 index f9a39a054..000000000 --- a/docs/plat/marvell/porting.txt +++ /dev/null @@ -1,118 +0,0 @@ -.. _porting: - -TF-A Porting Guide -================= - -This section describes how to port TF-A to a customer board, assuming that the SoC being used is already supported -in TF-A. - - -Source Code Structure ---------------------- -- The customer platform specific code shall reside under "plat/marvell//_cust" - (e.g. 'plat/marvell/a8k/a7040_cust'). -- The platform name for build purposes is called "_cust" (e.g. a7040_cust). -- The build system will reuse all files from within the soc directory, and take only the porting - files from the customer platform directory. - -Files that require porting are located at "plat/marvell//_cust" directory. - - -Armada-70x0/Armada-80x0 Porting -------------------------------- - - - SoC Physical Address Map (marvell_plat_config.c): - - This file describes the SoC physical memory mapping to be used for the CCU, IOWIN, AXI-MBUS and IOB - address decode units (Refer to the functional spec for more details). - - In most cases, using the default address decode windows should work OK. - - In cases where a special physical address map is needed (e.g. Special size for PCIe MEM windows, - large memory mapped SPI flash...), then porting of the SoC memory map is required. - - Note: For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please refer to the SoC functional spec, - and under "docs/marvell/misc/mvebu-[ccu/iob/amb/io-win].txt" files. - - - boot loader recovery (marvell_plat_config.c): - - Background: - boot rom can skip the current image and choose to boot from next position if a specific value - (0xDEADB002) is returned by the ble main function. This feature is used for boot loader recovery - by booting from a valid flash-image saved in next position on flash (e.g. address 2M in SPI flash). - - Supported options to implement the skip request are: - - GPIO - - I2C - - User defined - - - Porting: - Under marvell_plat_config.c, implement struct skip_image that includes specific board parameters. - .. warning:: to disable this feature make sure the struct skip_image is not implemented. - - - Example: - In A7040-DB specific implementation (plat/marvell/a8k/a70x0/board/marvell_plat_config.c), - the image skip is implemented using GPIO: mpp 33 (SW5). - - Before resetting the board make sure there is a valid image on the next flash address: - -tftp [valid address] flash-image.bin - -sf update [valid address] 0x2000000 [size] - - Press reset and keep pressing the button connected to the chosen GPIO pin. A skip image request - message is printed on the screen and boot rom boots from the saved image at the next position. - - - DDR Porting (dram_port.c): - - This file defines the dram topology and parameters of the target board. - - The DDR code is part of the BLE component, which is an extension of ARM Trusted Firmware (TF-A). - - The DDR driver called mv_ddr is released separately apart from TF-A sources. - - The BLE and consequently, the DDR init code is executed at the early stage of the boot process. - - Each supported platform of the TF-A has its own DDR porting file called dram_port.c located at - ``atf/plat/marvell/a8k//board`` directory. - - Please refer to '/doc/porting_guide.txt' for detailed porting description. - - The build target directory is "build//release/ble". - - - Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h) - - Background: - Some of the comphy's parameters value depend on the HW connection between the SoC and the PHY. Every - board type has specific HW characteristics like wire length. Due to those differences some comphy - parameters vary between board types. Therefore each board type can have its own list of values for - all relevant comphy parameters. The PHY porting layer specifies which parameters need to be suited and - the board designer should provide relevant values. - - .. seealso:: - For XFI/SFI comphy type there is procedure "rx_training" which eases process of suiting some of - the parameters. Please see :ref:`uboot_cmd` section: rx_training. - - The PHY porting layer simplifies updating static values per board type, which are now grouped in one place. - - .. note:: - The parameters for the same type of comphy may vary even for the same board type, it is because - the lanes from comphy-x to some PHY may have different HW characteristic than lanes from - comphy-y to the same (multiplexed) or other PHY. - - - Porting: - The porting layer for PHY was introduced in TF-A. There is one file - ``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the defaults. Those default - parameters are used only if there is no appropriate phy-porting-layer.h file under: - ``plat/marvell///board/phy-porting-layer.h``. If the phy-porting-layer.h exists, - the phy-default-porting-layer.h is not going to be included. - - .. warning:: - Not all comphy types are already reworked to support the PHY porting layer, currently the porting - layer is supported for XFI/SFI and SATA comphy types. - - The easiest way to prepare the PHY porting layer for custom board is to copy existing example to a new - platform: - - - cp ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell///board/phy-porting-layer.h" - - adjust relevant parameters or - - if different comphy index is used for specific feature, move it to proper table entry and then adjust. - - .. note:: - The final table size with comphy parameters can be different, depending on the CP module count for - given SoC type. - - - Example: - Example porting layer for armada-8040-db is under: ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` - - .. note:: - If there is no PHY porting layer for new platform (missing phy-porting-layer.h), the default - values are used (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is warned: - - .. warning:: - "Using default comphy parameters - it may be required to suit them for your board". -- cgit v1.2.3 From b1e0b11cc9e8a850a8e479927432068ce62a815a Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Mon, 26 Aug 2019 15:14:51 +0200 Subject: crypto: stm32_hash: Add HASH driver The driver manages the HASH processor IP on STM32MP1 Signed-off-by: Lionel Debieve Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585 --- drivers/st/crypto/stm32_hash.c | 330 ++++++++++++++++++++++++++++++++++++++++ include/drivers/st/stm32_hash.h | 24 +++ 2 files changed, 354 insertions(+) create mode 100644 drivers/st/crypto/stm32_hash.c create mode 100644 include/drivers/st/stm32_hash.h diff --git a/drivers/st/crypto/stm32_hash.c b/drivers/st/crypto/stm32_hash.c new file mode 100644 index 000000000..f72787d33 --- /dev/null +++ b/drivers/st/crypto/stm32_hash.c @@ -0,0 +1,330 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DT_HASH_COMPAT "st,stm32f756-hash" + +#define HASH_CR 0x00U +#define HASH_DIN 0x04U +#define HASH_STR 0x08U +#define HASH_SR 0x24U +#define HASH_HREG(x) (0x310U + ((x) * 0x04U)) + +/* Control Register */ +#define HASH_CR_INIT BIT(2) +#define HASH_CR_DATATYPE_SHIFT U(4) + +#define HASH_CR_ALGO_SHA1 0x0U +#define HASH_CR_ALGO_MD5 BIT(7) +#define HASH_CR_ALGO_SHA224 BIT(18) +#define HASH_CR_ALGO_SHA256 (BIT(18) | BIT(7)) + +/* Status Flags */ +#define HASH_SR_DCIS BIT(1) +#define HASH_SR_BUSY BIT(3) + +/* STR Register */ +#define HASH_STR_NBLW_MASK GENMASK(4, 0) +#define HASH_STR_DCAL BIT(8) + +#define MD5_DIGEST_SIZE 16U +#define SHA1_DIGEST_SIZE 20U +#define SHA224_DIGEST_SIZE 28U +#define SHA256_DIGEST_SIZE 32U + +#define HASH_TIMEOUT_US 10000U + +enum stm32_hash_data_format { + HASH_DATA_32_BITS, + HASH_DATA_16_BITS, + HASH_DATA_8_BITS, + HASH_DATA_1_BIT +}; + +struct stm32_hash_instance { + uintptr_t base; + unsigned int clock; + size_t digest_size; +}; + +struct stm32_hash_remain { + uint32_t buffer; + size_t length; +}; + +/* Expect a single HASH peripheral */ +static struct stm32_hash_instance stm32_hash; +static struct stm32_hash_remain stm32_remain; + +static uintptr_t hash_base(void) +{ + return stm32_hash.base; +} + +static int hash_wait_busy(void) +{ + uint64_t timeout = timeout_init_us(HASH_TIMEOUT_US); + + while ((mmio_read_32(hash_base() + HASH_SR) & HASH_SR_BUSY) != 0U) { + if (timeout_elapsed(timeout)) { + ERROR("%s: busy timeout\n", __func__); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int hash_wait_computation(void) +{ + uint64_t timeout = timeout_init_us(HASH_TIMEOUT_US); + + while ((mmio_read_32(hash_base() + HASH_SR) & HASH_SR_DCIS) == 0U) { + if (timeout_elapsed(timeout)) { + ERROR("%s: busy timeout\n", __func__); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int hash_write_data(uint32_t data) +{ + int ret; + + ret = hash_wait_busy(); + if (ret != 0) { + return ret; + } + + mmio_write_32(hash_base() + HASH_DIN, data); + + return 0; +} + +static void hash_hw_init(enum stm32_hash_algo_mode mode) +{ + uint32_t reg; + + reg = HASH_CR_INIT | (HASH_DATA_8_BITS << HASH_CR_DATATYPE_SHIFT); + + switch (mode) { + case HASH_MD5SUM: + reg |= HASH_CR_ALGO_MD5; + stm32_hash.digest_size = MD5_DIGEST_SIZE; + break; + case HASH_SHA1: + reg |= HASH_CR_ALGO_SHA1; + stm32_hash.digest_size = SHA1_DIGEST_SIZE; + break; + case HASH_SHA224: + reg |= HASH_CR_ALGO_SHA224; + stm32_hash.digest_size = SHA224_DIGEST_SIZE; + break; + /* Default selected algo is SHA256 */ + case HASH_SHA256: + default: + reg |= HASH_CR_ALGO_SHA256; + stm32_hash.digest_size = SHA256_DIGEST_SIZE; + break; + } + + mmio_write_32(hash_base() + HASH_CR, reg); +} + +static int hash_get_digest(uint8_t *digest) +{ + int ret; + uint32_t i; + uint32_t dsg; + + ret = hash_wait_computation(); + if (ret != 0) { + return ret; + } + + for (i = 0U; i < (stm32_hash.digest_size / sizeof(uint32_t)); i++) { + dsg = __builtin_bswap32(mmio_read_32(hash_base() + + HASH_HREG(i))); + memcpy(digest + (i * sizeof(uint32_t)), &dsg, sizeof(uint32_t)); + } + +#if defined(IMAGE_BL2) + /* + * Clean hardware context as HASH could be used later + * by non-secure software + */ + hash_hw_init(HASH_SHA256); +#endif + return 0; +} + +int stm32_hash_update(const uint8_t *buffer, size_t length) +{ + size_t remain_length = length; + int ret = 0; + + if ((length == 0U) || (buffer == NULL)) { + return 0; + } + + stm32mp_clk_enable(stm32_hash.clock); + + if (stm32_remain.length != 0U) { + uint32_t copysize; + + copysize = MIN((sizeof(uint32_t) - stm32_remain.length), + length); + memcpy(((uint8_t *)&stm32_remain.buffer) + stm32_remain.length, + buffer, copysize); + remain_length -= copysize; + buffer += copysize; + if (stm32_remain.length == sizeof(uint32_t)) { + ret = hash_write_data(stm32_remain.buffer); + if (ret != 0) { + goto exit; + } + + zeromem(&stm32_remain, sizeof(stm32_remain)); + } + } + + while (remain_length / sizeof(uint32_t) != 0U) { + uint32_t tmp_buf; + + memcpy(&tmp_buf, buffer, sizeof(uint32_t)); + ret = hash_write_data(tmp_buf); + if (ret != 0) { + goto exit; + } + + buffer += sizeof(uint32_t); + remain_length -= sizeof(uint32_t); + } + + if (remain_length != 0U) { + assert(stm32_remain.length == 0U); + + memcpy((uint8_t *)&stm32_remain.buffer, buffer, remain_length); + stm32_remain.length = remain_length; + } + +exit: + stm32mp_clk_disable(stm32_hash.clock); + + return ret; +} + +int stm32_hash_final(uint8_t *digest) +{ + int ret; + + stm32mp_clk_enable(stm32_hash.clock); + + if (stm32_remain.length != 0U) { + ret = hash_write_data(stm32_remain.buffer); + if (ret != 0) { + stm32mp_clk_disable(stm32_hash.clock); + return ret; + } + + mmio_clrsetbits_32(hash_base() + HASH_STR, HASH_STR_NBLW_MASK, + 8U * stm32_remain.length); + zeromem(&stm32_remain, sizeof(stm32_remain)); + } + + mmio_setbits_32(hash_base() + HASH_STR, HASH_STR_DCAL); + + ret = hash_get_digest(digest); + + stm32mp_clk_disable(stm32_hash.clock); + + return ret; +} + +int stm32_hash_final_update(const uint8_t *buffer, uint32_t length, + uint8_t *digest) +{ + int ret; + + ret = stm32_hash_update(buffer, length); + if (ret != 0) { + return ret; + } + + return stm32_hash_final(digest); +} + +void stm32_hash_init(enum stm32_hash_algo_mode mode) +{ + stm32mp_clk_enable(stm32_hash.clock); + + hash_hw_init(mode); + + stm32mp_clk_disable(stm32_hash.clock); + + zeromem(&stm32_remain, sizeof(stm32_remain)); +} + +int stm32_hash_register(void) +{ + struct dt_node_info hash_info; + int node; + + for (node = dt_get_node(&hash_info, -1, DT_HASH_COMPAT); + node != -FDT_ERR_NOTFOUND; + node = dt_get_node(&hash_info, node, DT_HASH_COMPAT)) { +#if defined(IMAGE_BL2) + if (hash_info.status != DT_DISABLED) { + break; + } +#else + if (hash_info.status == DT_SECURE) { + break; + } +#endif + } + + if (node == -FDT_ERR_NOTFOUND) { + return -ENODEV; + } + + if (hash_info.clock < 0) { + return -EINVAL; + } + + stm32_hash.base = hash_info.base; + stm32_hash.clock = hash_info.clock; + + stm32mp_clk_enable(stm32_hash.clock); + + if (hash_info.reset >= 0) { + stm32mp_reset_assert((unsigned long)hash_info.reset); + udelay(20); + stm32mp_reset_deassert((unsigned long)hash_info.reset); + } + + stm32mp_clk_disable(stm32_hash.clock); + + return 0; +} diff --git a/include/drivers/st/stm32_hash.h b/include/drivers/st/stm32_hash.h new file mode 100644 index 000000000..969d7aa13 --- /dev/null +++ b/include/drivers/st/stm32_hash.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_HASH_H +#define STM32_HASH_H + +enum stm32_hash_algo_mode { + HASH_MD5SUM, + HASH_SHA1, + HASH_SHA224, + HASH_SHA256 +}; + +int stm32_hash_update(const uint8_t *buffer, uint32_t length); +int stm32_hash_final(uint8_t *digest); +int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length, + uint8_t *digest); +void stm32_hash_init(enum stm32_hash_algo_mode mode); +int stm32_hash_register(void); + +#endif /* STM32_HASH_H */ -- cgit v1.2.3 From f700423c1f2426ca3c5ccb9ee4e765743424b074 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Mon, 16 Sep 2019 12:17:09 +0200 Subject: bsec: move bsec_mode_is_closed_device() service to platform This BSEC service is a platform specific service. Implementation moved to the platform part. Signed-off-by: Lionel Debieve Change-Id: I1f70ed48a446860498ed111acce01187568538c9 --- drivers/st/bsec/bsec.c | 18 +----------------- include/drivers/st/bsec.h | 1 - plat/st/common/include/stm32mp_common.h | 1 + plat/st/stm32mp1/stm32mp1_private.c | 13 +++++++++++++ 4 files changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/st/bsec/bsec.c b/drivers/st/bsec/bsec.c index b3c15ee8b..01c369edc 100644 --- a/drivers/st/bsec/bsec.c +++ b/drivers/st/bsec/bsec.c @@ -840,22 +840,6 @@ static uint32_t bsec_power_safmem(bool power) return BSEC_OK; } -/* - * bsec_mode_is_closed_device: read OTP secure sub-mode. - * return: false if open_device and true of closed_device. - */ -bool bsec_mode_is_closed_device(void) -{ - uint32_t value; - - if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) || - (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) { - return true; - } - - return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED; -} - /* * bsec_shadow_read_otp: Load OTP from SAFMEM and provide its value * otp_value: read value. @@ -894,7 +878,7 @@ uint32_t bsec_check_nsec_access_rights(uint32_t otp) if (otp >= STM32MP1_UPPER_OTP_START) { /* Check if BSEC is in OTP-SECURED closed_device state. */ - if (bsec_mode_is_closed_device()) { + if (stm32mp_is_closed_device()) { if (!non_secure_can_access(otp)) { return BSEC_ERROR; } diff --git a/include/drivers/st/bsec.h b/include/drivers/st/bsec.h index 2171550b3..d833e7ab2 100644 --- a/include/drivers/st/bsec.h +++ b/include/drivers/st/bsec.h @@ -199,7 +199,6 @@ bool bsec_read_sp_lock(uint32_t otp); bool bsec_wr_lock(uint32_t otp); uint32_t bsec_otp_lock(uint32_t service, uint32_t value); -bool bsec_mode_is_closed_device(void); uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word); uint32_t bsec_check_nsec_access_rights(uint32_t otp); diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index e20308ee2..59657fdc2 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -19,6 +19,7 @@ void stm32mp_save_boot_ctx_address(uintptr_t address); uintptr_t stm32mp_get_boot_ctx_address(void); bool stm32mp_is_single_core(void); +bool stm32mp_is_closed_device(void); /* Return the base address of the DDR controller */ uintptr_t stm32mp_ddrctrl_base(void); diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index 38ebcef64..e2dcd2af7 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -278,6 +278,19 @@ bool stm32mp_is_single_core(void) return ret; } +/* Return true when device is in closed state */ +bool stm32mp_is_closed_device(void) +{ + uint32_t value; + + if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) || + (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) { + return true; + } + + return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED; +} + uint32_t stm32_iwdg_get_instance(uintptr_t base) { switch (base) { -- cgit v1.2.3 From 4bdb1a7a6a1325343b0f0c375b43e9b874e31fca Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Tue, 3 Sep 2019 12:22:23 +0200 Subject: stm32mp1: add authentication support for stm32image This commit adds authentication binary support for STM32MP1. It prints the bootrom authentication result if signed image is used and authenticates the next loaded STM32 images. It also enables the dynamic translation table support (PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services. Signed-off-by: Lionel Debieve Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51 --- drivers/st/io/io_stm32image.c | 8 +++- fdts/stm32mp157c-security.dtsi | 4 ++ plat/st/common/include/stm32mp_auth.h | 19 ++++++++ plat/st/common/stm32mp_auth.c | 90 +++++++++++++++++++++++++++++++++++ plat/st/stm32mp1/bl2_plat_setup.c | 13 +++++ plat/st/stm32mp1/include/boot_api.h | 36 +++++++++++++- plat/st/stm32mp1/platform.mk | 4 ++ plat/st/stm32mp1/stm32mp1_def.h | 3 ++ 8 files changed, 174 insertions(+), 3 deletions(-) create mode 100644 plat/st/common/include/stm32mp_auth.h create mode 100644 plat/st/common/stm32mp_auth.c diff --git a/drivers/st/io/io_stm32image.c b/drivers/st/io/io_stm32image.c index 971dcce53..413521b1e 100644 --- a/drivers/st/io/io_stm32image.c +++ b/drivers/st/io/io_stm32image.c @@ -246,7 +246,7 @@ static int stm32image_partition_size(io_entity_t *entity, size_t *length) static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read) { - int result = 0; + int result; uint8_t *local_buffer = (uint8_t *)buffer; boot_api_image_header_t *header = (boot_api_image_header_t *)first_lba_buffer; @@ -341,6 +341,12 @@ static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer, header->magic = 0; } + result = stm32mp_auth_image(header, buffer); + if (result != 0) { + ERROR("Authentication Failed (%i)\n", result); + return result; + } + io_close(backend_handle); } diff --git a/fdts/stm32mp157c-security.dtsi b/fdts/stm32mp157c-security.dtsi index f7e55b367..165ffa0cb 100644 --- a/fdts/stm32mp157c-security.dtsi +++ b/fdts/stm32mp157c-security.dtsi @@ -28,6 +28,10 @@ }; }; +&hash1 { + secure-status = "okay"; +}; + &sdmmc1 { compatible = "st,stm32-sdmmc2"; }; diff --git a/plat/st/common/include/stm32mp_auth.h b/plat/st/common/include/stm32mp_auth.h new file mode 100644 index 000000000..3075d18ac --- /dev/null +++ b/plat/st/common/include/stm32mp_auth.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP_AUTH_H +#define STM32MP_AUTH_H + +struct stm32mp_auth_ops { + uint32_t (*check_key)(uint8_t *pubkey_in, uint8_t *pubkey_out); + uint32_t (*verify_signature)(uint8_t *hash_in, uint8_t *pubkey_in, + uint8_t *signature, uint32_t ecc_algo); +}; + +void stm32mp_init_auth(struct stm32mp_auth_ops *init_ptr); +int stm32mp_auth_image(boot_api_image_header_t *header, uintptr_t buffer); + +#endif /* STM32MP_AUTH_H */ diff --git a/plat/st/common/stm32mp_auth.c b/plat/st/common/stm32mp_auth.c new file mode 100644 index 000000000..0ef6d5454 --- /dev/null +++ b/plat/st/common/stm32mp_auth.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include + +static const struct stm32mp_auth_ops *auth_ops; + +void stm32mp_init_auth(struct stm32mp_auth_ops *init_ptr) +{ + if ((init_ptr == NULL) || + (init_ptr->check_key == NULL) || + (init_ptr->verify_signature == NULL) || + (stm32_hash_register() != 0)) { + panic(); + } + + auth_ops = init_ptr; +} + +int stm32mp_auth_image(boot_api_image_header_t *header, uintptr_t buffer) +{ + int ret; + uint8_t image_hash[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES]; + uint32_t header_skip_cksum = sizeof(header->magic) + + sizeof(header->image_signature) + + sizeof(header->payload_checksum); + + /* Check Security Status */ + if (!stm32mp_is_closed_device()) { + if (header->option_flags != 0U) { + WARN("Skip signature check (header option)\n"); + return 0; + } + INFO("Check signature on Open device\n"); + } + + ret = mmap_add_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_BASE, + STM32MP_ROM_SIZE, MT_CODE | MT_SECURE); + if (ret != 0) { + return ret; + } + + /* Check Public Key */ + if (auth_ops->check_key(header->ecc_pubk, NULL) != BOOT_API_RETURN_OK) { + ret = -EINVAL; + goto err; + } + + /* Compute end of header hash and payload hash */ + stm32_hash_init(HASH_SHA256); + + ret = stm32_hash_update((uint8_t *)&header->header_version, + sizeof(boot_api_image_header_t) - + header_skip_cksum); + if (ret != 0) { + ERROR("Hash of header failed, %i\n", ret); + goto err; + } + + ret = stm32_hash_final_update((uint8_t *)buffer, + header->image_length, image_hash); + if (ret != 0) { + ERROR("Hash of payload failed\n"); + goto err; + } + + /* Verify signature */ + if (auth_ops->verify_signature(image_hash, header->ecc_pubk, + header->image_signature, + header->ecc_algo_type) != + BOOT_API_RETURN_OK) { + ret = -EINVAL; + } + +err: + mmap_remove_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_SIZE); + return ret; +} diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index c6aefe324..d9e29b4e8 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -32,6 +32,7 @@ #include static struct console_stm32 console; +static struct stm32mp_auth_ops stm32mp1_auth_ops; static void print_reset_reason(void) { @@ -284,6 +285,12 @@ void bl2_el3_plat_arch_setup(void) stm32mp_print_boardinfo(); + if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { + NOTICE("Bootrom authentication %s\n", + (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? + "failed" : "succeeded"); + } + skip_console_init: if (stm32_iwdg_init() < 0) { panic(); @@ -302,6 +309,12 @@ skip_console_init: ERROR("Cannot save boot interface\n"); } + stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; + stm32mp1_auth_ops.verify_signature = + boot_context->bootrom_ecdsa_verify_signature; + + stm32mp_init_auth(&stm32mp1_auth_ops); + stm32mp1_arch_security_setup(); print_reset_reason(); diff --git a/plat/st/stm32mp1/include/boot_api.h b/plat/st/stm32mp1/include/boot_api.h index c841a7450..2284970fa 100644 --- a/plat/st/stm32mp1/include/boot_api.h +++ b/plat/st/stm32mp1/include/boot_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,16 @@ #include #include +/* + * Possible value of boot context field 'auth_status' + */ +/* No authentication done */ +#define BOOT_API_CTX_AUTH_NO 0x0U +/* Authentication done and failed */ +#define BOOT_API_CTX_AUTH_FAILED 0x1U +/* Authentication done and succeeded */ +#define BOOT_API_CTX_AUTH_SUCCESS 0x2U + /* * Possible value of boot context field 'boot_interface_sel' */ @@ -114,6 +124,8 @@ /* Closed = OTP_CFG0[6] */ #define BOOT_API_OTP_MODE_CLOSED_BIT_POS 6 +#define BOOT_API_RETURN_OK 0x66U + /* * Boot Context related definitions */ @@ -132,7 +144,27 @@ typedef struct { uint16_t boot_interface_instance; uint32_t reserved1[13]; uint32_t otp_afmux_values[3]; - uint32_t reserved[9]; + uint32_t reserved[5]; + uint32_t auth_status; + + /* + * Pointers to bootROM External Secure Services + * - ECDSA check key + * - ECDSA verify signature + * - ECDSA verify signature and go + */ + uint32_t (*bootrom_ecdsa_check_key)(uint8_t *pubkey_in, + uint8_t *pubkey_out); + uint32_t (*bootrom_ecdsa_verify_signature)(uint8_t *hash_in, + uint8_t *pubkey_in, + uint8_t *signature, + uint32_t ecc_algo); + uint32_t (*bootrom_ecdsa_verify_and_go)(uint8_t *hash_in, + uint8_t *pub_key_in, + uint8_t *signature, + uint32_t ecc_algo, + uint32_t *entry_in); + /* * Information specific to an SD boot * Updated each time an SD boot is at least attempted, diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index 83d977039..90b3e3c1e 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -71,7 +71,9 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \ BL2_SOURCES += drivers/io/io_block.c \ drivers/io/io_dummy.c \ drivers/io/io_storage.c \ + drivers/st/crypto/stm32_hash.c \ drivers/st/io/io_stm32image.c \ + plat/st/common/stm32mp_auth.c \ plat/st/common/bl2_io_storage.c \ plat/st/stm32mp1/bl2_plat_setup.c @@ -103,6 +105,8 @@ STM32_TF_ELF := $(STM32_TF_STM32:.stm32=.elf) STM32_TF_DTBFILE := ${BUILD_PLAT}/fdts/${DTB_FILE_NAME} STM32_TF_OBJS := ${BUILD_PLAT}/stm32mp1.o +BL2_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 + # Variables for use with stm32image STM32IMAGEPATH ?= tools/stm32image STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT} diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 0eba8a645..a40852bde 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -19,6 +19,7 @@ #include #include +#include #include #include #include @@ -49,6 +50,8 @@ /******************************************************************************* * STM32MP1 memory map related constants ******************************************************************************/ +#define STM32MP_ROM_BASE U(0x00000000) +#define STM32MP_ROM_SIZE U(0x00020000) #define STM32MP_SYSRAM_BASE U(0x2FFC0000) #define STM32MP_SYSRAM_SIZE U(0x00040000) -- cgit v1.2.3 From e231f3a5f46f3897368521e0b61fec8cad91b35e Mon Sep 17 00:00:00 2001 From: Usama Arif Date: Thu, 19 Sep 2019 10:54:16 +0100 Subject: a5ds: Hold the secondary cpus in pen rather than panic For the secondary CPUs, hold the cpu in wfe rather then panic. This will be needed when multicore support is added to a5ds as the smc call will write to the hold base and signal an event to power on the secondary CPUs. Change-Id: I0ffc2059e9ef894c21375ca5c94def859bfa6599 Signed-off-by: Usama Arif --- plat/arm/board/a5ds/aarch32/a5ds_helpers.S | 82 +++++++++++++++++++++++++++--- plat/arm/board/a5ds/include/platform_def.h | 8 +++ 2 files changed, 83 insertions(+), 7 deletions(-) diff --git a/plat/arm/board/a5ds/aarch32/a5ds_helpers.S b/plat/arm/board/a5ds/aarch32/a5ds_helpers.S index 23a22d9c5..ed7ad9c86 100644 --- a/plat/arm/board/a5ds/aarch32/a5ds_helpers.S +++ b/plat/arm/board/a5ds/aarch32/a5ds_helpers.S @@ -12,17 +12,36 @@ .globl plat_get_my_entrypoint .globl plat_is_my_cpu_primary - /* -------------------------------------------------------------------- + /* ----------------------------------------------------- * void plat_secondary_cold_boot_setup (void); * - * For AArch32, cold-booting secondary CPUs is not yet - * implemented and they panic. - * -------------------------------------------------------------------- + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- */ func plat_secondary_cold_boot_setup -cb_panic: - wfi - b cb_panic + /* Calculate address of our hold entry */ + bl plat_my_core_pos + lsl r0, r0, #A5DS_HOLD_ENTRY_SHIFT + mov_imm r2, A5DS_HOLD_BASE + /* Clear the value stored in the hold address for the specific core */ + mov_imm r3, A5DS_HOLD_STATE_WAIT + str r3, [r2, r0] + dmb ish + + /* Wait until we have a go */ +poll_mailbox: + ldr r1, [r2, r0] + cmp r1, #A5DS_HOLD_STATE_WAIT + beq 1f + mov_imm r0, A5DS_TRUSTED_MAILBOX_BASE + ldr r1, [r0] + bx r1 +1: + wfe + b poll_mailbox endfunc plat_secondary_cold_boot_setup /* --------------------------------------------------------------------- @@ -56,3 +75,52 @@ func plat_is_my_cpu_primary movne r0, #0 bx lr endfunc plat_is_my_cpu_primary + + /* --------------------------------------------------------------------- + * Loads MPIDR in r0 and calls plat_arm_calc_core_pos + * --------------------------------------------------------------------- + */ +func plat_my_core_pos + ldcopr r0, MPIDR + b plat_arm_calc_core_pos + +endfunc plat_my_core_pos + + /* --------------------------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) + * + * Function to calculate the core position on A5DS. + * + * (ClusterId * A5DS_MAX_CPUS_PER_CLUSTER * A5DS_MAX_PE_PER_CPU) + + * (CPUId * A5DS_MAX_PE_PER_CPU) + + * ThreadId + * + * which can be simplified as: + * + * ((ClusterId * A5DS_MAX_CPUS_PER_CLUSTER + CPUId) * A5DS_MAX_PE_PER_CPU) + * + ThreadId + * --------------------------------------------------------------------- + */ +func plat_arm_calc_core_pos + mov r3, r0 + + /* + * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it + * look as if in a multi-threaded implementation + */ + tst r0, #MPIDR_MT_MASK + lsleq r3, r0, #MPIDR_AFFINITY_BITS + + /* Extract individual affinity fields from MPIDR */ + ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS + ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS + ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS + + /* Compute linear position */ + mov r3, #A5DS_MAX_CPUS_PER_CLUSTER + mla r1, r2, r3, r1 + mov r3, #A5DS_MAX_PE_PER_CPU + mla r0, r1, r3, r0 + + bx lr +endfunc plat_arm_calc_core_pos diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h index db65c3778..13c19343f 100644 --- a/plat/arm/board/a5ds/include/platform_def.h +++ b/plat/arm/board/a5ds/include/platform_def.h @@ -325,6 +325,14 @@ /* Mailbox base address */ #define A5DS_TRUSTED_MAILBOX_BASE A5DS_SHARED_RAM_BASE +#define A5DS_TRUSTED_MAILBOX_SIZE (8 + A5DS_HOLD_SIZE) +#define A5DS_HOLD_BASE (A5DS_TRUSTED_MAILBOX_BASE + 8) +#define A5DS_HOLD_SIZE (PLATFORM_CORE_COUNT * \ + A5DS_HOLD_ENTRY_SIZE) +#define A5DS_HOLD_ENTRY_SHIFT 3 +#define A5DS_HOLD_ENTRY_SIZE (1 << A5DS_HOLD_ENTRY_SHIFT) +#define A5DS_HOLD_STATE_WAIT 0 +#define A5DS_HOLD_STATE_GO 1 /* * GIC related constants to cater for GICv2 -- cgit v1.2.3 From ec885bacb247e9a88c0e21406bdf42821eb340c7 Mon Sep 17 00:00:00 2001 From: Usama Arif Date: Thu, 19 Sep 2019 11:07:24 +0100 Subject: a5ds: add multicore support Enable cores 1-3 using psci. On receiving the smc call from kernel, core 0 will bring the secondary cores out pen and signal an event for the cores. Currently on switching the cores is enabled i.e. it is not possible to suspend, switch cores off, etc. Change-Id: I6087e1d2ec650e1d587fd543efc1b08cbb50ae5f Signed-off-by: Usama Arif --- fdts/a5ds.dts | 26 +++++++++++++++++++++ plat/arm/board/a5ds/a5ds_pm.c | 37 ++++++++++++++++++++++++++++++ plat/arm/board/a5ds/include/platform_def.h | 10 ++++---- 3 files changed, 68 insertions(+), 5 deletions(-) diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts index 8bc4adf8a..91212e8a0 100644 --- a/fdts/a5ds.dts +++ b/fdts/a5ds.dts @@ -12,14 +12,40 @@ interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_on = <0x84000003>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a5"; + enable-method = "psci"; reg = <0>; }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + enable-method = "psci"; + reg = <1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + enable-method = "psci"; + reg = <2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + enable-method = "psci"; + reg = <3>; + }; }; memory@80000000 { diff --git a/plat/arm/board/a5ds/a5ds_pm.c b/plat/arm/board/a5ds/a5ds_pm.c index 5fd443b12..98de77d10 100644 --- a/plat/arm/board/a5ds/a5ds_pm.c +++ b/plat/arm/board/a5ds/a5ds_pm.c @@ -6,6 +6,38 @@ #include #include +#include +#include + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +static int a5ds_pwr_domain_on(u_register_t mpidr) +{ + unsigned int pos = plat_core_pos_by_mpidr(mpidr); + uint64_t *hold_base = (uint64_t *)A5DS_HOLD_BASE; + + hold_base[pos] = A5DS_HOLD_STATE_GO; + dsbish(); + sev(); + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Platform handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +void a5ds_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + /* TODO: This setup is needed only after a cold boot*/ + gicv2_pcpu_distif_init(); + + /* Enable the gic cpu interface */ + gicv2_cpuif_enable(); +} /******************************************************************************* * Export the platform handlers via a5ds_psci_pm_ops. The ARM Standard @@ -14,11 +46,16 @@ plat_psci_ops_t a5ds_psci_pm_ops = { /* dummy struct */ .validate_ns_entrypoint = NULL, + .pwr_domain_on = a5ds_pwr_domain_on, + .pwr_domain_on_finish = a5ds_pwr_domain_on_finish }; int __init plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { + uintptr_t *mailbox = (void *)A5DS_TRUSTED_MAILBOX_BASE; + *mailbox = sec_entrypoint; + *psci_ops = &a5ds_psci_pm_ops; return 0; diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h index 13c19343f..e9e4b9aef 100644 --- a/plat/arm/board/a5ds/include/platform_def.h +++ b/plat/arm/board/a5ds/include/platform_def.h @@ -97,9 +97,9 @@ /* Default number of threads per CPU on A5DS */ #define A5DS_MAX_PE_PER_CPU 1 -#define A5DS_CORE_COUNT 1 +#define A5DS_CORE_COUNT 4 -#define A5DS_PRIMARY_CPU 0x0 +#define A5DS_PRIMARY_CPU 0x0 #define FLASH1_BASE UL(0x8000000) #define FLASH1_SIZE UL(0x2800000) @@ -229,11 +229,11 @@ #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) /* Required platform porting definitions */ -#define PLATFORM_CORE_COUNT 1 -#define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \ +#define PLATFORM_CORE_COUNT A5DS_CORE_COUNT +#define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) + 1 -#define PLAT_MAX_PWR_LVL 2 +#define PLAT_MAX_PWR_LVL 2 /* * Other platform porting definitions are provided by included headers -- cgit v1.2.3 From bd363d356f3d0f5c9d64e35eaee166a4c3fc7e5e Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Tue, 23 Jul 2019 15:41:06 +0200 Subject: FVP: Fix plat_set_nv_ctr() function The Fast Models provide a non-volatile counter component, which is used in the Trusted Board Boot implementation to protect against rollback attacks. This component comes in 2 versions (see [1]). - Version 0 is the default and models a locked non-volatile counter, whose value is fixed. - Version 1 of the counter may be incremented in a monotonic fashion. plat_set_nv_ctr() must cope with both versions. This is achieved by: 1) Attempting to write the new value in the counter. 2) Reading the value back. 3) If there is a mismatch, we know the counter upgrade failed. When using version 0 of the counter, no upgrade is possible so the function is expected to fail all the time. However, the code is missing a compiler barrier between the write operation and the next read. Thus, the compiler may optimize and remove the read operation on the basis that the counter value has not changed. With the default optimization level used in TF-A (-Os), this is what's happening. The fix introduced in this patch marks the write and subsequent read accesses to the counter as volatile, such that the compiler makes no assumption about the value of the counter. Note that the comment above plat_set_nv_ctr() was clearly stating that when using the read-only version of the non-volatile counter, "we expect the values in the certificates to always match the RO values so that this function is never called". However, the fact that the counter value was read back seems to contradict this comment, as it is implementing a counter-measure against misuse of the function. The comment has been reworded to avoid any confusion. Without this patch, this bug may be demonstrated on the Base AEM FVP: - Using version 0 of the non-volatile counter (default version). - With certificates embedding a revision number value of 32 (compiling TF-A with TFW_NVCTR_VAL=32). In this configuration, the non-volatile counter is tied to value 31 by default. When BL1 loads the Trusted Boot Firmware certificate, it notices that the two values do not match and tries to upgrade the non-volatile counter. This write operation is expected to fail (because the counter is locked) and the function is expected to return an error but it succeeds instead. As a result, the trusted boot does not abort as soon as it should and incorrectly boots BL2. The boot is finally aborted when BL2 verifies the BL31 image and figures out that the version of the SoC Firmware Key Certificate does not match. On Arm platforms, only certificates signed with the Root-of-Trust Key may trigger an upgrade of the non-volatile Trusted counter. [1] https://developer.arm.com/docs/100964/1160/fast-models-components/peripheral-components/nonvolatilecounter Change-Id: I9979f29c23b47b338b9b484013d1fb86c59db92f Signed-off-by: Sandrine Bailleux --- plat/arm/board/fvp/fvp_trusted_boot.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/plat/arm/board/fvp/fvp_trusted_boot.c b/plat/arm/board/fvp/fvp_trusted_boot.c index 0d160cb1d..dc5076435 100644 --- a/plat/arm/board/fvp/fvp_trusted_boot.c +++ b/plat/arm/board/fvp/fvp_trusted_boot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,39 +8,41 @@ #include #include +#include + #include #include #include /* - * Store a new non-volatile counter value. On some FVP versions, the - * non-volatile counters are RO. On these versions we expect the values in the - * certificates to always match the RO values so that this function is never - * called. + * Store a new non-volatile counter value. + * + * On some FVP versions, the non-volatile counters are read-only so this + * function will always fail. * * Return: 0 = success, Otherwise = error */ int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) { const char *oid; - uint32_t *nv_ctr_addr; + uintptr_t nv_ctr_addr; assert(cookie != NULL); oid = (const char *)cookie; if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) { - nv_ctr_addr = (uint32_t *)TFW_NVCTR_BASE; + nv_ctr_addr = TFW_NVCTR_BASE; } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { - nv_ctr_addr = (uint32_t *)NTFW_CTR_BASE; + nv_ctr_addr = NTFW_CTR_BASE; } else { return 1; } - *(unsigned int *)nv_ctr_addr = nv_ctr; - - /* Verify that the current value is the one we just wrote. */ - if (nv_ctr != (unsigned int)(*nv_ctr_addr)) - return 1; + mmio_write_32(nv_ctr_addr, nv_ctr); - return 0; + /* + * If the FVP models a locked counter then its value cannot be updated + * and the above write operation has been silently ignored. + */ + return (mmio_read_32(nv_ctr_addr) == nv_ctr) ? 0 : 1; } -- cgit v1.2.3 From 6eaf928d66fbded8e190aaa189e1a0810ba79252 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 19 Sep 2019 10:45:28 +0100 Subject: FDT helper functions: Add function documentation Since we moved some functions that amend a DT blob in memory to common code, let's add proper function documentation. This covers the three exported functions in common/fdt_fixup.c. Change-Id: I67d7d27344e62172c789d308662f78d54903cf57 Signed-off-by: Andre Przywara --- common/fdt_fixup.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/common/fdt_fixup.c b/common/fdt_fixup.c index 8843404df..48ae97512 100644 --- a/common/fdt_fixup.c +++ b/common/fdt_fixup.c @@ -29,6 +29,20 @@ static int append_psci_compatible(void *fdt, int offs, const char *str) return fdt_appendprop(fdt, offs, "compatible", str, strlen(str) + 1); } +/******************************************************************************* + * dt_add_psci_node() - Add a PSCI node into an existing device tree + * @fdt: pointer to the device tree blob in memory + * + * Add a device tree node describing PSCI into the root level of an existing + * device tree blob in memory. + * This will add v0.1, v0.2 and v1.0 compatible strings and the standard + * function IDs for v0.1 compatibility. + * An existing PSCI node will not be touched, the function will return success + * in this case. This function will not touch the /cpus enable methods, use + * dt_add_psci_cpu_enable_methods() for that. + * + * Return: 0 on success, -1 otherwise. + ******************************************************************************/ int dt_add_psci_node(void *fdt) { int offs; @@ -113,6 +127,17 @@ static int dt_update_one_cpu_node(void *fdt, int offset) return offs; } +/******************************************************************************* + * dt_add_psci_cpu_enable_methods() - switch CPU nodes in DT to use PSCI + * @fdt: pointer to the device tree blob in memory + * + * Iterate over all CPU device tree nodes (/cpus/cpu@x) in memory to change + * the enable-method to PSCI. This will add the enable-method properties, if + * required, or will change existing properties to read "psci". + * + * Return: 0 on success, or a negative error value otherwise. + ******************************************************************************/ + int dt_add_psci_cpu_enable_methods(void *fdt) { int offs, ret; @@ -130,6 +155,25 @@ int dt_add_psci_cpu_enable_methods(void *fdt) #define HIGH_BITS(x) ((sizeof(x) > 4) ? ((x) >> 32) : (typeof(x))0) +/******************************************************************************* + * fdt_add_reserved_memory() - reserve (secure) memory regions in DT + * @dtb: pointer to the device tree blob in memory + * @node_name: name of the subnode to be used + * @base: physical base address of the reserved region + * @size: size of the reserved region + * + * Add a region of memory to the /reserved-memory node in a device tree in + * memory, creating that node if required. Each region goes into a subnode + * of that node and has a @node_name, a @base address and a @size. + * This will prevent any device tree consumer from using that memory. It + * can be used to announce secure memory regions, as it adds the "no-map" + * property to prevent mapping and speculative operations on that region. + * + * See reserved-memory/reserved-memory.txt in the (Linux kernel) DT binding + * documentation for details. + * + * Return: 0 on success, a negative error value otherwise. + ******************************************************************************/ int fdt_add_reserved_memory(void *dtb, const char *node_name, uintptr_t base, size_t size) { -- cgit v1.2.3 From 66799507c4bbade3a58b833b55bcbe195370fd87 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 19 Sep 2019 10:55:25 +0100 Subject: FDT helper functions: Respect architecture in PSCI function IDs PSCI uses different function IDs for CPU_SUSPEND and CPU_ON, depending on the architecture used (AArch64 or AArch32). For recent PSCI versions the client will determine the right version, but for PSCI v0.1 we need to put some ID in the DT node. At the moment we always add the 64-bit IDs, which is not correct if TF-A is built for AArch32. Use the function IDs matching the TF-A build architecture, for the two IDs where this differs. This only affects legacy OSes using PSCI v0.1. On the way remove the sys_poweroff and sys_reset properties, which were never described in the official PSCI DT binding. Change-Id: If77bc6daec215faeb2dc67112e765aacafd17f33 Signed-off-by: Andre Przywara --- common/fdt_fixup.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/common/fdt_fixup.c b/common/fdt_fixup.c index 48ae97512..99d0eee98 100644 --- a/common/fdt_fixup.c +++ b/common/fdt_fixup.c @@ -29,6 +29,19 @@ static int append_psci_compatible(void *fdt, int offs, const char *str) return fdt_appendprop(fdt, offs, "compatible", str, strlen(str) + 1); } +/* + * Those defines are for PSCI v0.1 legacy clients, which we expect to use + * the same execution state (AArch32/AArch64) as TF-A. + * Kernels running in AArch32 on an AArch64 TF-A should use PSCI v0.2. + */ +#ifdef __aarch64__ +#define PSCI_CPU_SUSPEND_FNID PSCI_CPU_SUSPEND_AARCH64 +#define PSCI_CPU_ON_FNID PSCI_CPU_ON_AARCH64 +#else +#define PSCI_CPU_SUSPEND_FNID PSCI_CPU_SUSPEND_AARCH32 +#define PSCI_CPU_ON_FNID PSCI_CPU_ON_AARCH32 +#endif + /******************************************************************************* * dt_add_psci_node() - Add a PSCI node into an existing device tree * @fdt: pointer to the device tree blob in memory @@ -66,15 +79,11 @@ int dt_add_psci_node(void *fdt) return -1; if (fdt_setprop_string(fdt, offs, "method", "smc")) return -1; - if (fdt_setprop_u32(fdt, offs, "cpu_suspend", PSCI_CPU_SUSPEND_AARCH64)) + if (fdt_setprop_u32(fdt, offs, "cpu_suspend", PSCI_CPU_SUSPEND_FNID)) return -1; if (fdt_setprop_u32(fdt, offs, "cpu_off", PSCI_CPU_OFF)) return -1; - if (fdt_setprop_u32(fdt, offs, "cpu_on", PSCI_CPU_ON_AARCH64)) - return -1; - if (fdt_setprop_u32(fdt, offs, "sys_poweroff", PSCI_SYSTEM_OFF)) - return -1; - if (fdt_setprop_u32(fdt, offs, "sys_reset", PSCI_SYSTEM_RESET)) + if (fdt_setprop_u32(fdt, offs, "cpu_on", PSCI_CPU_ON_FNID)) return -1; return 0; } -- cgit v1.2.3 From 7c0a1877e76b5dc7b6326e3cb670c5156d4d4383 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 4 Aug 2019 10:46:21 +0100 Subject: rpi3: Allow runtime determination of UART base clock rate At the moment the UART input clock rate is hard coded at compile time. This works as long as the GPU firmware always sets up the same rate, which does not seem to be true for the Raspberry Pi 4. In preparation for being able to change this at runtime, add a base clock parameter to the console setup function. This is still hardcoded for the Raspberry Pi 3. Change-Id: I398bc2f1e9b46f7af9a84cb0b33cbe8e78f2d900 Signed-off-by: Andre Przywara --- plat/rpi/common/include/rpi_shared.h | 2 +- plat/rpi/common/rpi3_common.c | 4 ++-- plat/rpi/rpi3/rpi3_bl1_setup.c | 2 +- plat/rpi/rpi3/rpi3_bl2_setup.c | 2 +- plat/rpi/rpi3/rpi3_bl31_setup.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/plat/rpi/common/include/rpi_shared.h b/plat/rpi/common/include/rpi_shared.h index 686343892..de8357162 100644 --- a/plat/rpi/common/include/rpi_shared.h +++ b/plat/rpi/common/include/rpi_shared.h @@ -14,7 +14,7 @@ ******************************************************************************/ /* Utility functions */ -void rpi3_console_init(void); +void rpi3_console_init(unsigned int base_clk_rate); void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, uintptr_t code_start, uintptr_t code_limit, uintptr_t rodata_start, uintptr_t rodata_limit diff --git a/plat/rpi/common/rpi3_common.c b/plat/rpi/common/rpi3_common.c index ab63d98f1..4317b3a26 100644 --- a/plat/rpi/common/rpi3_common.c +++ b/plat/rpi/common/rpi3_common.c @@ -104,14 +104,14 @@ static const mmap_region_t plat_rpi3_mmap[] = { ******************************************************************************/ static console_16550_t rpi3_console; -void rpi3_console_init(void) +void rpi3_console_init(unsigned int base_clk_rate) { int console_scope = CONSOLE_FLAG_BOOT; #if RPI3_RUNTIME_UART != -1 console_scope |= CONSOLE_FLAG_RUNTIME; #endif int rc = console_16550_register(PLAT_RPI3_UART_BASE, - PLAT_RPI3_UART_CLK_IN_HZ, + base_clk_rate, PLAT_RPI3_UART_BAUDRATE, &rpi3_console); if (rc == 0) { diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c index 3ac30e0f0..dcce76e47 100644 --- a/plat/rpi/rpi3/rpi3_bl1_setup.c +++ b/plat/rpi/rpi3/rpi3_bl1_setup.c @@ -35,7 +35,7 @@ void bl1_early_platform_setup(void) 0x80000000); /* Initialize the console to provide early debug support */ - rpi3_console_init(); + rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = BL_RAM_BASE; diff --git a/plat/rpi/rpi3/rpi3_bl2_setup.c b/plat/rpi/rpi3/rpi3_bl2_setup.c index 991c0fcb2..44827c63a 100644 --- a/plat/rpi/rpi3/rpi3_bl2_setup.c +++ b/plat/rpi/rpi3/rpi3_bl2_setup.c @@ -62,7 +62,7 @@ void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, meminfo_t *mem_layout = (meminfo_t *) arg1; /* Initialize the console to provide early debug support */ - rpi3_console_init(); + rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ); /* Enable arch timer */ generic_delay_timer_init(); diff --git a/plat/rpi/rpi3/rpi3_bl31_setup.c b/plat/rpi/rpi3/rpi3_bl31_setup.c index a9efc52b8..c16dbffaa 100644 --- a/plat/rpi/rpi3/rpi3_bl31_setup.c +++ b/plat/rpi/rpi3/rpi3_bl31_setup.c @@ -60,7 +60,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, { /* Initialize the console to provide early debug support */ - rpi3_console_init(); + rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ); /* * In debug builds, a special value is passed in 'arg1' to verify -- cgit v1.2.3 From f5cb15b0c886afaa41c5d3dad8e859b6a41f76ab Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 9 Jul 2019 11:25:57 +0100 Subject: Add basic support for Raspberry Pi 4 The Raspberry Pi 4 is a single board computer with four Cortex-A72 cores. From a TF-A perspective it is quite similar to the Raspberry Pi 3, although it comes with more memory (up to 4GB) and has a GIC. This initial port though differs quite a lot from the existing rpi3 platform port, mainly due to taking a much simpler and more robust approach to loading the non-secure payload: The GPU firmware of the SoC, which is responsible for initial platform setup (including DRAM initialisation), already loads the kernel, device tree and the "armstub" into DRAM. We take advantage of this, by placing just a BL31 component into the armstub8.bin component, which will be executed first, in AArch64 EL3. The non-secure payload can be a kernel or a boot loader (U-Boot or EDK-2), disguised as the "kernel" image and loaded by the GPU firmware. So this is just a BL31-only port, which directly drops into EL2 and executes whatever has been loaded as the "kernel" image, handing over the DTB address in x0. Change-Id: I636f4d1f661821566ad9e341d69ba36f6bbfb546 Signed-off-by: Andre Przywara --- plat/rpi/rpi4/aarch64/plat_helpers.S | 187 +++++++++++++++++++++++++++++++++ plat/rpi/rpi4/include/plat_macros.S | 20 ++++ plat/rpi/rpi4/include/platform_def.h | 197 +++++++++++++++++++++++++++++++++++ plat/rpi/rpi4/include/rpi_hw.h | 115 ++++++++++++++++++++ plat/rpi/rpi4/platform.mk | 108 +++++++++++++++++++ plat/rpi/rpi4/rpi4_bl31_setup.c | 162 ++++++++++++++++++++++++++++ 6 files changed, 789 insertions(+) create mode 100644 plat/rpi/rpi4/aarch64/plat_helpers.S create mode 100644 plat/rpi/rpi4/include/plat_macros.S create mode 100644 plat/rpi/rpi4/include/platform_def.h create mode 100644 plat/rpi/rpi4/include/rpi_hw.h create mode 100644 plat/rpi/rpi4/platform.mk create mode 100644 plat/rpi/rpi4/rpi4_bl31_setup.c diff --git a/plat/rpi/rpi4/aarch64/plat_helpers.S b/plat/rpi/rpi4/aarch64/plat_helpers.S new file mode 100644 index 000000000..46073b791 --- /dev/null +++ b/plat/rpi/rpi4/aarch64/plat_helpers.S @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#include "../include/rpi_hw.h" + + .globl plat_crash_console_flush + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl platform_mem_init + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_reset_handler + .globl plat_rpi3_calc_core_pos + .globl plat_secondary_cold_boot_setup + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * + * This function uses the plat_rpi3_calc_core_pos() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_rpi3_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr); + * + * CorePos = (ClusterId * 4) + CoreId + * ----------------------------------------------------- + */ +func plat_rpi3_calc_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc plat_rpi3_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #RPI4_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* Calculate address of our hold entry */ + bl plat_my_core_pos + lsl x0, x0, #3 + mov_imm x2, PLAT_RPI3_TM_HOLD_BASE + add x0, x0, x2 + + /* + * This code runs way before requesting the warmboot of this core, + * so it is possible to clear the mailbox before getting a request + * to boot. + */ + mov x1, PLAT_RPI3_TM_HOLD_STATE_WAIT + str x1,[x0] + + /* Wait until we have a go */ +poll_mailbox: + wfe + ldr x1, [x0] + cmp x1, PLAT_RPI3_TM_HOLD_STATE_GO + bne poll_mailbox + + /* Jump to the provided entrypoint */ + mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT + ldr x1, [x0] + br x1 +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * uintptr_t plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and a warm + * boot. + * + * This functions returns: + * - 0 for a cold boot. + * - Any other value for a warm boot. + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* TODO: support warm boot */ + mov x0, #0 + ret +endfunc plat_get_my_entrypoint + + /* --------------------------------------------- + * void platform_mem_init (void); + * + * No need to carry out any memory initialization. + * --------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0 - x3 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, PLAT_RPI3_UART_BASE + mov_imm x1, PLAT_RPI4_VPU_CLK_RATE + mov_imm x2, PLAT_RPI3_UART_BAUDRATE + b console_16550_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_RPI3_UART_BASE + b console_16550_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush() + * Function to force a write of all buffered + * data that hasn't been output. + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x0, PLAT_RPI3_UART_BASE + b console_16550_core_flush +endfunc plat_crash_console_flush + + /* --------------------------------------------- + * void plat_reset_handler(void); + * --------------------------------------------- + */ +func plat_reset_handler + /* ------------------------------------------------ + * Set L2 read/write cache latency: + * - L2 Data RAM latency: 3 cycles (0b010) + * - L2 Data RAM setup: 1 cycle (bit 5) + * ------------------------------------------------ + */ + mrs x0, CORTEX_A72_L2CTLR_EL1 + mov x1, #0x22 + orr x0, x0, x1 + msr CORTEX_A72_L2CTLR_EL1, x0 + isb + + ret +endfunc plat_reset_handler diff --git a/plat/rpi/rpi4/include/plat_macros.S b/plat/rpi/rpi4/include/plat_macros.S new file mode 100644 index 000000000..6007d031e --- /dev/null +++ b/plat/rpi/rpi4/include/plat_macros.S @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/rpi/rpi4/include/platform_def.h b/plat/rpi/rpi4/include/platform_def.h new file mode 100644 index 000000000..831d1c3f0 --- /dev/null +++ b/plat/rpi/rpi4/include/platform_def.h @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include +#include +#include + +#include "rpi_hw.h" + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) + +#define PLATFORM_STACK_SIZE ULL(0x1000) + +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT + +#define RPI4_PRIMARY_CPU U(0) + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET U(1) +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF U(2) + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH U(4) +#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +/* + * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and + * secure DRAM. Note that this is all actually DRAM with different names, + * there is no Secure RAM in the Raspberry Pi 4. + */ +#if RPI3_USE_UEFI_MAP +#define SEC_ROM_BASE ULL(0x00000000) +#define SEC_ROM_SIZE ULL(0x00010000) + +/* FIP placed after ROM to append it to BL1 with very little padding. */ +#define PLAT_RPI3_FIP_BASE ULL(0x00020000) +#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x00010000) + +/* Reserve 2M of secure SRAM and DRAM, starting at 2M */ +#define SEC_SRAM_BASE ULL(0x00200000) +#define SEC_SRAM_SIZE ULL(0x00100000) + +#define SEC_DRAM0_BASE ULL(0x00300000) +#define SEC_DRAM0_SIZE ULL(0x00100000) + +/* Windows on ARM requires some RAM at 4M */ +#define NS_DRAM0_BASE ULL(0x00400000) +#define NS_DRAM0_SIZE ULL(0x00C00000) +#else +#define SEC_ROM_BASE ULL(0x00000000) +#define SEC_ROM_SIZE ULL(0x00020000) + +/* FIP placed after ROM to append it to BL1 with very little padding. */ +#define PLAT_RPI3_FIP_BASE ULL(0x00020000) +#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x001E0000) + +/* We have 16M of memory reserved starting at 256M */ +#define SEC_SRAM_BASE ULL(0x10000000) +#define SEC_SRAM_SIZE ULL(0x00100000) + +#define SEC_DRAM0_BASE ULL(0x10100000) +#define SEC_DRAM0_SIZE ULL(0x00F00000) +/* End of reserved memory */ + +#define NS_DRAM0_BASE ULL(0x11000000) +#define NS_DRAM0_SIZE ULL(0x01000000) +#endif /* RPI3_USE_UEFI_MAP */ + +/* + * BL33 entrypoint. + */ +#define PLAT_RPI3_NS_IMAGE_OFFSET NS_DRAM0_BASE +#define PLAT_RPI3_NS_IMAGE_MAX_SIZE NS_DRAM0_SIZE + +/* + * I/O registers. + */ +#define DEVICE0_BASE RPI_IO_BASE +#define DEVICE0_SIZE RPI_IO_SIZE + +/* + * TF-A lives in SRAM, partition it here + */ +#define SHARED_RAM_BASE SEC_SRAM_BASE +#define SHARED_RAM_SIZE ULL(0x00001000) + +#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) +#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) + +/* + * Mailbox to control the secondary cores. All secondary cores are held in a + * wait loop in cold boot. To release them perform the following steps (plus + * any additional barriers that may be needed): + * + * uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT; + * *entrypoint = ADDRESS_TO_JUMP_TO; + * + * uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; + * mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO; + * + * sev(); + */ +#define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE + +/* The secure entry point to be used on warm reset by all CPUs. */ +#define PLAT_RPI3_TM_ENTRYPOINT PLAT_RPI3_TRUSTED_MAILBOX_BASE +#define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8) + +/* Hold entries for each CPU. */ +#define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \ + PLAT_RPI3_TM_ENTRYPOINT_SIZE) +#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8) +#define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \ + PLATFORM_CORE_COUNT) + +#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \ + PLAT_RPI3_TM_HOLD_SIZE) + +#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0) +#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1) + +/* + * BL31 specific defines. + * + * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the + * current BL31 debug size plus a little space for growth. + */ +#define PLAT_MAX_BL31_SIZE ULL(0x20000) + +#define BL31_BASE ULL(0x1000) +#define BL31_LIMIT ULL(0x100000) +#define BL31_PROGBITS_LIMIT ULL(0x100000) + +#define SEC_SRAM_ID 0 +#define SEC_DRAM_ID 1 + +/* + * Other memory-related defines. + */ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) + +#define MAX_MMAP_REGIONS 8 +#define MAX_XLAT_TABLES 4 + +#define MAX_IO_DEVICES U(3) +#define MAX_IO_HANDLES U(4) + +#define MAX_IO_BLOCK_DEVICES U(1) + +/* + * Serial-related constants. + */ +#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE +#define PLAT_RPI3_UART_BAUDRATE ULL(115200) + +/* + * System counter + */ +#define SYS_COUNTER_FREQ_IN_TICKS ULL(54000000) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h new file mode 100644 index 000000000..ed367ee20 --- /dev/null +++ b/plat/rpi/rpi4/include/rpi_hw.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI_HW_H +#define RPI_HW_H + +#include + +/* + * Peripherals + */ + +#define RPI_IO_BASE ULL(0xFE000000) +#define RPI_IO_SIZE ULL(0x02000000) + +/* + * ARM <-> VideoCore mailboxes + */ +#define RPI3_MBOX_OFFSET ULL(0x0000B880) +#define RPI3_MBOX_BASE (RPI_IO_BASE + RPI3_MBOX_OFFSET) +/* VideoCore -> ARM */ +#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) +#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) +#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) +#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) +#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) +/* ARM -> VideoCore */ +#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) +#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) +#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) +#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) +#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) +/* Mailbox status constants */ +#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ +#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ + +/* + * Power management, reset controller, watchdog. + */ +#define RPI3_IO_PM_OFFSET ULL(0x00100000) +#define RPI3_PM_BASE (RPI_IO_BASE + RPI3_IO_PM_OFFSET) +/* Registers on top of RPI3_PM_BASE. */ +#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) +#define RPI3_PM_RSTS_OFFSET ULL(0x00000020) +#define RPI3_PM_WDOG_OFFSET ULL(0x00000024) +/* Watchdog constants */ +#define RPI3_PM_PASSWORD U(0x5A000000) +#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) +#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) +/* + * The RSTS register is used by the VideoCore firmware when booting the + * Raspberry Pi to know which partition to boot from. The partition value is + * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware + * to indicate halt. + */ +#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) + +/* + * Clock controller + */ +#define RPI4_IO_CLOCK_OFFSET ULL(0x00101000) +#define RPI4_CLOCK_BASE (RPI_IO_BASE + RPI4_IO_CLOCK_OFFSET) +#define RPI4_VPU_CLOCK_DIVIDER ULL(0x0000000c) + +/* + * Hardware random number generator. + */ +#define RPI3_IO_RNG_OFFSET ULL(0x00104000) +#define RPI3_RNG_BASE (RPI_IO_BASE + RPI3_IO_RNG_OFFSET) +#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) +#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) +#define RPI3_RNG_DATA_OFFSET ULL(0x00000008) +#define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010) +/* Enable/disable RNG */ +#define RPI3_RNG_CTRL_ENABLE U(0x1) +#define RPI3_RNG_CTRL_DISABLE U(0x0) +/* Number of currently available words */ +#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24) +#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF) +/* Value to mask interrupts caused by the RNG */ +#define RPI3_RNG_INT_MASK_DISABLE U(0x1) + +/* + * Serial port (called 'Mini UART' in the Broadcom documentation). + */ +#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) +#define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET) +#define PLAT_RPI4_VPU_CLK_RATE ULL(1000000000) + +/* + * GPIO controller + */ +#define RPI3_IO_GPIO_OFFSET ULL(0x00200000) +#define RPI3_GPIO_BASE (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET) + +/* + * SDHost controller + */ +#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) +#define RPI3_SDHOST_BASE (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET) + +/* + * GIC interrupt controller + */ +#define RPI_HAVE_GIC +#define RPI4_GIC_GICD_BASE ULL(0xff841000) +#define RPI4_GIC_GICC_BASE ULL(0xff842000) + +#define RPI4_LOCAL_CONTROL_BASE_ADDRESS ULL(0xff800000) +#define RPI4_LOCAL_CONTROL_PRESCALER ULL(0xff800008) + +#endif /* RPI_HW_H */ diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk new file mode 100644 index 000000000..3ff180ea6 --- /dev/null +++ b/plat/rpi/rpi4/platform.mk @@ -0,0 +1,108 @@ +# +# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include lib/libfdt/libfdt.mk +include lib/xlat_tables_v2/xlat_tables.mk + +PLAT_INCLUDES := -Iplat/rpi/common/include \ + -Iplat/rpi/rpi4/include + +PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \ + plat/rpi/common/rpi3_common.c \ + ${XLAT_TABLES_LIB_SRCS} + +BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \ + plat/rpi/rpi4/aarch64/plat_helpers.S \ + drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + drivers/arm/gic/v2/gicv2_main.c \ + plat/common/plat_gicv2.c \ + plat/rpi/rpi4/rpi4_bl31_setup.c \ + plat/rpi/common/rpi3_pm.c \ + plat/common/plat_psci_common.c \ + plat/rpi/common/rpi3_topology.c \ + ${LIBFDT_SRCS} + +# For now we only support BL31, using the kernel loaded by the GPU firmware. +RESET_TO_BL31 := 1 + +# All CPUs enter armstub8.bin. +COLD_BOOT_SINGLE_CPU := 0 + +# Tune compiler for Cortex-A72 +ifeq ($(notdir $(CC)),armclang) + TF_CFLAGS_aarch64 += -mcpu=cortex-a72 +else ifneq ($(findstring clang,$(notdir $(CC))),) + TF_CFLAGS_aarch64 += -mcpu=cortex-a72 +else + TF_CFLAGS_aarch64 += -mtune=cortex-a72 +endif + + +# Enable all errata workarounds for Cortex-A72 +ERRATA_A72_859971 := 1 + +WORKAROUND_CVE_2017_5715 := 1 + +# Add new default target when compiling this platform +all: bl31 + +# Build config flags +# ------------------ + +# Disable stack protector by default +ENABLE_STACK_PROTECTOR := 0 + +# Have different sections for code and rodata +SEPARATE_CODE_AND_RODATA := 1 + +# Use Coherent memory +USE_COHERENT_MEM := 1 + +# Platform build flags +# -------------------- + +# Assume that BL33 isn't the Linux kernel by default +RPI3_DIRECT_LINUX_BOOT := 0 + +# BL33 images are in AArch64 by default +RPI3_BL33_IN_AARCH32 := 0 + +# UART to use at runtime. -1 means the runtime UART is disabled. +# Any other value means the default UART will be used. +RPI3_RUNTIME_UART := 0 + +# Use normal memory mapping for ROM, FIP, SRAM and DRAM +RPI3_USE_UEFI_MAP := 0 + +# Process platform flags +# ---------------------- + +$(eval $(call add_define,RPI3_BL33_IN_AARCH32)) +$(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT)) +ifdef RPI3_PRELOADED_DTB_BASE +$(eval $(call add_define,RPI3_PRELOADED_DTB_BASE)) +endif +$(eval $(call add_define,RPI3_RUNTIME_UART)) +$(eval $(call add_define,RPI3_USE_UEFI_MAP)) + +# Verify build config +# ------------------- +# +ifneq (${RPI3_DIRECT_LINUX_BOOT}, 0) + ifndef RPI3_PRELOADED_DTB_BASE + $(error Error: RPI3_PRELOADED_DTB_BASE needed if RPI3_DIRECT_LINUX_BOOT=1) + endif +endif + +ifeq (${ARCH},aarch32) + $(error Error: AArch32 not supported on rpi4) +endif + +ifneq ($(ENABLE_STACK_PROTECTOR), 0) +PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \ + plat/rpi/common/rpi3_stack_protector.c +endif diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c new file mode 100644 index 000000000..de582b324 --- /dev/null +++ b/plat/rpi/rpi4/rpi4_bl31_setup.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +static const gicv2_driver_data_t rpi4_gic_data = { + .gicd_base = RPI4_GIC_GICD_BASE, + .gicc_base = RPI4_GIC_GICC_BASE, +}; + +/* + * To be filled by the code below. At the moment BL32 is not supported. + * In the future these might be passed down from BL2. + */ +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(sec_state_is_valid(type) != 0); + + next_image_info = (type == NON_SECURE) + ? &bl33_image_ep_info : &bl32_image_ep_info; + + /* None of the images can have 0x0 as the entrypoint. */ + if (next_image_info->pc) { + return next_image_info; + } else { + return NULL; + } +} + +static void ldelay(register_t delay) +{ + __asm__ volatile ( + "1:\tcbz %0, 2f\n\t" + "sub %0, %0, #1\n\t" + "b 1b\n" + "2:" + : "=&r" (delay) : "0" (delay) + ); +} + +/******************************************************************************* + * Perform any BL31 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before + * they are lost (potentially). This needs to be done before the MMU is + * initialized so that the memory layout can be used while creating page + * tables. BL2 has flushed this information to memory, so we are guaranteed + * to pick up good data. + ******************************************************************************/ +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) + +{ + uint32_t div_reg; + + /* + * LOCAL_CONTROL: + * Bit 9 clear: Increment by 1 (vs. 2). + * Bit 8 clear: Timer source is 19.2MHz crystal (vs. APB). + */ + mmio_write_32(RPI4_LOCAL_CONTROL_BASE_ADDRESS, 0); + + /* LOCAL_PRESCALER; divide-by (0x80000000 / register_val) == 1 */ + mmio_write_32(RPI4_LOCAL_CONTROL_PRESCALER, 0x80000000); + + /* Early GPU firmware revisions need a little break here. */ + ldelay(100000); + + /* + * Initialize the console to provide early debug support. + * Different GPU firmware revisions set up the VPU divider differently, + * so read the actual divider register to learn the UART base clock + * rate. The divider is encoded as a 12.12 fixed point number, but we + * just care about the integer part of it. + */ + div_reg = mmio_read_32(RPI4_CLOCK_BASE + RPI4_VPU_CLOCK_DIVIDER); + div_reg = (div_reg >> 12) & 0xfff; + if (div_reg == 0) + div_reg = 1; + rpi3_console_init(PLAT_RPI4_VPU_CLK_RATE / div_reg); + +#if RPI3_DIRECT_LINUX_BOOT + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + +# if RPI3_BL33_IN_AARCH32 + /* + * According to the file ``Documentation/arm/Booting`` of the Linux + * kernel tree, Linux expects: + * r0 = 0 + * r1 = machine type number, optional in DT-only platforms (~0 if so) + * r2 = Physical address of the device tree blob + */ + VERBOSE("rpi4: Preparing to boot 32-bit Linux kernel\n"); + bl33_image_ep_info.args.arg0 = 0U; + bl33_image_ep_info.args.arg1 = ~0U; + bl33_image_ep_info.args.arg2 = (u_register_t) RPI3_PRELOADED_DTB_BASE; +# else + /* + * According to the file ``Documentation/arm64/booting.txt`` of the + * Linux kernel tree, Linux expects the physical address of the device + * tree blob (DTB) in x0, while x1-x3 are reserved for future use and + * must be 0. + */ + VERBOSE("rpi4: Preparing to boot 64-bit Linux kernel\n"); + bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE; + bl33_image_ep_info.args.arg1 = 0ULL; + bl33_image_ep_info.args.arg2 = 0ULL; + bl33_image_ep_info.args.arg3 = 0ULL; +# endif /* RPI3_BL33_IN_AARCH32 */ +#endif /* RPI3_DIRECT_LINUX_BOOT */ +} + +void bl31_plat_arch_setup(void) +{ + rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE, + BL_CODE_BASE, BL_CODE_END, + BL_RO_DATA_BASE, BL_RO_DATA_END +#if USE_COHERENT_MEM + , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END +#endif + ); + + enable_mmu_el3(0); +} + +void bl31_platform_setup(void) +{ + /* Configure the interrupt controller */ + gicv2_driver_init(&rpi4_gic_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} -- cgit v1.2.3 From c4597e13a2925cc6bf802d9376238f5de18b292a Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 10 Jul 2019 18:09:18 +0100 Subject: rpi4: Accommodate "armstub8.bin" header at the beginning of BL31 image The Raspberry Pi GPU firmware checks for a magic value at offset 240 (0xf0) of the armstub8.bin image it loads. If that value matches, it writes the kernel load address and the DTB address into subsequent memory locations. We can use these addresses to avoid hardcoding these values into the BL31 image, to make it more flexible and a drop-in replacement for the official armstub8.bin. Reserving just 16 bytes at offset 240 of the final image file is not easily possible, though, as this location is in the middle of the generic BL31 entry point code. However we can prepend an extra section before the actual BL31 image, to contain the magic and addresses. This needs to be 4KB, because the actual BL31 entry point needs to be page aligned. Use the platform linker script hook that the generic code provides, to add an almost empty 4KB code block before the entry point code. The very first word contains a branch instruction to jump over this page, into the actual entry code. This also gives us plenty of room for the SMP pens later. Change-Id: I38caa5e7195fa39cbef8600933a03d86f09263d6 Signed-off-by: Andre Przywara --- plat/rpi/rpi4/aarch64/armstub8_header.S | 37 +++++++++++++++++++++++++++++++++ plat/rpi/rpi4/include/plat.ld.S | 23 ++++++++++++++++++++ plat/rpi/rpi4/platform.mk | 3 +++ plat/rpi/rpi4/rpi4_bl31_setup.c | 17 +++++++++++++++ 4 files changed, 80 insertions(+) create mode 100644 plat/rpi/rpi4/aarch64/armstub8_header.S create mode 100644 plat/rpi/rpi4/include/plat.ld.S diff --git a/plat/rpi/rpi4/aarch64/armstub8_header.S b/plat/rpi/rpi4/aarch64/armstub8_header.S new file mode 100644 index 000000000..246358d04 --- /dev/null +++ b/plat/rpi/rpi4/aarch64/armstub8_header.S @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * armstub8.bin header to let the GPU firmware recognise this code. + * It will then write the load address of the kernel image and the DT + * after the header magic in RAM, so we can read those addresses at runtime. + */ + +.text + b armstub8_end + +.global stub_magic +.global dtb_ptr32 +.global kernel_entry32 + +.org 0xf0 +armstub8: +stub_magic: + .word 0x5afe570b +stub_version: + .word 0 +dtb_ptr32: + .word 0x0 +kernel_entry32: + .word 0x0 + +/* + * Technically an offset of 0x100 would suffice, but the follow-up code + * (bl31_entrypoint.S at BL31_BASE) needs to be page aligned, so pad here + * till the end of the first 4K page. + */ +.org 0x1000 +armstub8_end: diff --git a/plat/rpi/rpi4/include/plat.ld.S b/plat/rpi/rpi4/include/plat.ld.S new file mode 100644 index 000000000..9262fad8a --- /dev/null +++ b/plat/rpi/rpi4/include/plat.ld.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Stub linker script to provide the armstub8.bin header before the actual + * code. If the GPU firmware finds a magic value at offset 240 in + * armstub8.bin, it will put the DTB and kernel load address in subsequent + * words. We can then read those values to find the proper NS entry point + * and find our DTB more flexibly. + */ + +MEMORY { + PRERAM (rwx): ORIGIN = 0, LENGTH = 4096 +} + +SECTIONS +{ + .armstub8 . : { + *armstub8_header.o(.text*) + KEEP(*(.armstub8)) + } >PRERAM +} diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk index 3ff180ea6..b20251cf4 100644 --- a/plat/rpi/rpi4/platform.mk +++ b/plat/rpi/rpi4/platform.mk @@ -16,6 +16,7 @@ PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \ BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \ plat/rpi/rpi4/aarch64/plat_helpers.S \ + plat/rpi/rpi4/aarch64/armstub8_header.S \ drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_helpers.c \ drivers/arm/gic/v2/gicv2_main.c \ @@ -41,6 +42,8 @@ else TF_CFLAGS_aarch64 += -mtune=cortex-a72 endif +# Add support for platform supplied linker script for BL31 build +$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) # Enable all errata workarounds for Cortex-A72 ERRATA_A72_859971 := 1 diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c index de582b324..58025b27a 100644 --- a/plat/rpi/rpi4/rpi4_bl31_setup.c +++ b/plat/rpi/rpi4/rpi4_bl31_setup.c @@ -13,12 +13,21 @@ #include #include #include +#include #include #include #include +/* + * Fields at the beginning of armstub8.bin. + * While building the BL31 image, we put the stub magic into the binary. + * The GPU firmware detects this at boot time, clears that field as a + * confirmation and puts the kernel and DT address in the following words. + */ +extern uint32_t stub_magic; + static const gicv2_driver_data_t rpi4_gic_data = { .gicd_base = RPI4_GIC_GICD_BASE, .gicc_base = RPI4_GIC_GICC_BASE, @@ -141,6 +150,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void bl31_plat_arch_setup(void) { + /* + * Add the first page of memory, which holds the stub magic, + * the kernel and the DT address. + * This is read-only, as the GPU already populated the header, + * we just need to read it. + */ + mmap_add_region(0, 0, 4096, MT_MEMORY | MT_RO | MT_SECURE); + rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE, BL_CODE_BASE, BL_CODE_END, BL_RO_DATA_BASE, BL_RO_DATA_END -- cgit v1.2.3 From 448fb352f9be697e40b1224df3e33bca863326c6 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 11 Jul 2019 01:42:12 +0100 Subject: rpi4: Determine BL33 entry point at runtime Now that we have the armstub magic value in place, the GPU firmware will write the kernel load address (and DTB address) into our special page, so we can always easily access the actual location without hardcoding any addresses into the BL31 image. Make the compile-time defined PRELOADED_BL33_BASE macro optional, and read the BL33 entry point from the magic location, if the macro was not defined. We do the same for the DTB address. This also splits the currently "common" definition of plat_get_ns_image_entrypoint() to be separate between RPi3 and RPi4. Change-Id: I6f26c0adc6fce2df47786b271c490928b4529abb Signed-off-by: Andre Przywara --- plat/rpi/common/rpi3_common.c | 12 ------------ plat/rpi/rpi3/rpi3_bl31_setup.c | 12 ++++++++++++ plat/rpi/rpi4/platform.mk | 13 ++----------- plat/rpi/rpi4/rpi4_bl31_setup.c | 39 ++++++++++++++++++++++++++++++++++----- 4 files changed, 48 insertions(+), 28 deletions(-) diff --git a/plat/rpi/common/rpi3_common.c b/plat/rpi/common/rpi3_common.c index 4317b3a26..ff3369427 100644 --- a/plat/rpi/common/rpi3_common.c +++ b/plat/rpi/common/rpi3_common.c @@ -175,18 +175,6 @@ void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, init_xlat_tables(); } -/******************************************************************************* - * Return entrypoint of BL33. - ******************************************************************************/ -uintptr_t plat_get_ns_image_entrypoint(void) -{ -#ifdef PRELOADED_BL33_BASE - return PRELOADED_BL33_BASE; -#else - return PLAT_RPI3_NS_IMAGE_OFFSET; -#endif -} - /******************************************************************************* * Gets SPSR for BL32 entry ******************************************************************************/ diff --git a/plat/rpi/rpi3/rpi3_bl31_setup.c b/plat/rpi/rpi3/rpi3_bl31_setup.c index c16dbffaa..24a56139b 100644 --- a/plat/rpi/rpi3/rpi3_bl31_setup.c +++ b/plat/rpi/rpi3/rpi3_bl31_setup.c @@ -47,6 +47,18 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) } } +/******************************************************************************* + * Return entrypoint of BL33. + ******************************************************************************/ +uintptr_t plat_get_ns_image_entrypoint(void) +{ +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else + return PLAT_RPI3_NS_IMAGE_OFFSET; +#endif +} + /******************************************************************************* * Perform any BL31 early platform setup. Here is an opportunity to copy * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk index b20251cf4..6ac21691e 100644 --- a/plat/rpi/rpi4/platform.mk +++ b/plat/rpi/rpi4/platform.mk @@ -68,8 +68,8 @@ USE_COHERENT_MEM := 1 # Platform build flags # -------------------- -# Assume that BL33 isn't the Linux kernel by default -RPI3_DIRECT_LINUX_BOOT := 0 +# There is not much else than a Linux kernel to load at the moment. +RPI3_DIRECT_LINUX_BOOT := 1 # BL33 images are in AArch64 by default RPI3_BL33_IN_AARCH32 := 0 @@ -92,15 +92,6 @@ endif $(eval $(call add_define,RPI3_RUNTIME_UART)) $(eval $(call add_define,RPI3_USE_UEFI_MAP)) -# Verify build config -# ------------------- -# -ifneq (${RPI3_DIRECT_LINUX_BOOT}, 0) - ifndef RPI3_PRELOADED_DTB_BASE - $(error Error: RPI3_PRELOADED_DTB_BASE needed if RPI3_DIRECT_LINUX_BOOT=1) - endif -endif - ifeq (${ARCH},aarch32) $(error Error: AArch32 not supported on rpi4) endif diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c index 58025b27a..f5f74bdd2 100644 --- a/plat/rpi/rpi4/rpi4_bl31_setup.c +++ b/plat/rpi/rpi4/rpi4_bl31_setup.c @@ -27,6 +27,8 @@ * confirmation and puts the kernel and DT address in the following words. */ extern uint32_t stub_magic; +extern uint32_t dtb_ptr32; +extern uint32_t kernel_entry32; static const gicv2_driver_data_t rpi4_gic_data = { .gicd_base = RPI4_GIC_GICD_BASE, @@ -63,6 +65,34 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) } } +uintptr_t plat_get_ns_image_entrypoint(void) +{ +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else + /* Cleared by the GPU if kernel address is valid. */ + if (stub_magic == 0) + return kernel_entry32; + + WARN("Stub magic failure, using default kernel address 0x80000\n"); + return 0x80000; +#endif +} + +static uintptr_t rpi4_get_dtb_address(void) +{ +#ifdef RPI3_PRELOADED_DTB_BASE + return RPI3_PRELOADED_DTB_BASE; +#else + /* Cleared by the GPU if DTB address is valid. */ + if (stub_magic == 0) + return dtb_ptr32; + + WARN("Stub magic failure, DTB address unknown\n"); + return 0; +#endif +} + static void ldelay(register_t delay) { __asm__ volatile ( @@ -114,12 +144,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, div_reg = 1; rpi3_console_init(PLAT_RPI4_VPU_CLK_RATE / div_reg); -#if RPI3_DIRECT_LINUX_BOOT bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); - bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); + bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry(); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); +#if RPI3_DIRECT_LINUX_BOOT # if RPI3_BL33_IN_AARCH32 /* * According to the file ``Documentation/arm/Booting`` of the Linux @@ -131,7 +160,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, VERBOSE("rpi4: Preparing to boot 32-bit Linux kernel\n"); bl33_image_ep_info.args.arg0 = 0U; bl33_image_ep_info.args.arg1 = ~0U; - bl33_image_ep_info.args.arg2 = (u_register_t) RPI3_PRELOADED_DTB_BASE; + bl33_image_ep_info.args.arg2 = rpi4_get_dtb_address(); # else /* * According to the file ``Documentation/arm64/booting.txt`` of the @@ -140,7 +169,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, * must be 0. */ VERBOSE("rpi4: Preparing to boot 64-bit Linux kernel\n"); - bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE; + bl33_image_ep_info.args.arg0 = rpi4_get_dtb_address(); bl33_image_ep_info.args.arg1 = 0ULL; bl33_image_ep_info.args.arg2 = 0ULL; bl33_image_ep_info.args.arg3 = 0ULL; -- cgit v1.2.3 From f67fa69cb6937a7fc559bbec4a7acce5edefa888 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 11 Jul 2019 01:45:39 +0100 Subject: rpi4: Amend DTB to advertise PSCI The device tree provided by the official Raspberry Pi firmware uses spin tables for SMP bringup. One of the benefit of having TF-A is that it provides PSCI services, so let's rewrite the DTB to advertise PSCI instead of spin tables. This uses the (newly exported) routine from the QEMU platform port. Change-Id: Ifddcb14041ca253a333f8c2d5e97a42db152470c Signed-off-by: Andre Przywara --- plat/rpi/rpi4/platform.mk | 1 + plat/rpi/rpi4/rpi4_bl31_setup.c | 57 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk index 6ac21691e..2038021a0 100644 --- a/plat/rpi/rpi4/platform.mk +++ b/plat/rpi/rpi4/platform.mk @@ -25,6 +25,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \ plat/rpi/common/rpi3_pm.c \ plat/common/plat_psci_common.c \ plat/rpi/common/rpi3_topology.c \ + common/fdt_fixup.c \ ${LIBFDT_SRCS} # For now we only support BL31, using the kernel loaded by the GPU firmware. diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c index f5f74bdd2..e1b6c8976 100644 --- a/plat/rpi/rpi4/rpi4_bl31_setup.c +++ b/plat/rpi/rpi4/rpi4_bl31_setup.c @@ -9,12 +9,15 @@ #include #include +#include #include #include #include #include #include #include +#include +#include #include @@ -179,6 +182,18 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void bl31_plat_arch_setup(void) { + /* + * Is the dtb_ptr32 pointer valid? If yes, map the DTB region. + * We map the 2MB region the DTB start address lives in, plus + * the next 2MB, to have enough room for expansion. + */ + if (stub_magic == 0) { + unsigned long long dtb_region = dtb_ptr32; + + dtb_region &= ~0x1fffff; /* Align to 2 MB. */ + mmap_add_region(dtb_region, dtb_region, 4U << 20, + MT_MEMORY | MT_RW | MT_NS); + } /* * Add the first page of memory, which holds the stub magic, * the kernel and the DT address. @@ -198,8 +213,50 @@ void bl31_plat_arch_setup(void) enable_mmu_el3(0); } +static uint32_t dtb_size(const void *dtb) +{ + const uint32_t *dtb_header = dtb; + + return fdt32_to_cpu(dtb_header[1]); +} + +static void rpi4_prepare_dtb(void) +{ + void *dtb = (void *)rpi4_get_dtb_address(); + int ret; + + /* Return if no device tree is detected */ + if (fdt_check_header(dtb) != 0) + return; + + ret = fdt_open_into(dtb, dtb, 0x100000); + if (ret < 0) { + ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret); + return; + } + + if (dt_add_psci_node(dtb)) { + ERROR("Failed to add PSCI Device Tree node\n"); + return; + } + + if (dt_add_psci_cpu_enable_methods(dtb)) { + ERROR("Failed to add PSCI cpu enable methods in Device Tree\n"); + return; + } + + ret = fdt_pack(dtb); + if (ret < 0) + ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret); + + clean_dcache_range((uintptr_t)dtb, dtb_size(dtb)); + INFO("Changed device tree to advertise PSCI.\n"); +} + void bl31_platform_setup(void) { + rpi4_prepare_dtb(); + /* Configure the interrupt controller */ gicv2_driver_init(&rpi4_gic_data); gicv2_distif_init(); -- cgit v1.2.3 From 2b19e2f361ac9be69f0f19ed7a25b1a038d91fc3 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 22 Jul 2019 00:04:40 +0100 Subject: rpi4: Reserve resident BL31 region from non-secure world The GPU firmware loads the armstub8.bin (BL31) image at address 0, the beginning of DRAM. As this holds the resident PSCI code and the SMP pens, the non-secure world should better know about this, to avoid accessing memory owned by TF-A. This is particularly criticial as the Raspberry Pi 4 does not feature a secure memory controller, so overwriting code is a very real danger. Use the newly introduced function to add a node into reserved-memory node, where non-secure world can check for regions to be excluded from its mappings. Reserve the first 512KB of memory for now. We can refine this later if need be. Change-Id: I00e55e70c5c02615320d79ff35bc32b805d30770 Signed-off-by: Andre Przywara --- plat/rpi/rpi4/rpi4_bl31_setup.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c index e1b6c8976..8dfadf730 100644 --- a/plat/rpi/rpi4/rpi4_bl31_setup.c +++ b/plat/rpi/rpi4/rpi4_bl31_setup.c @@ -245,6 +245,10 @@ static void rpi4_prepare_dtb(void) return; } + /* Reserve memory used by Trusted Firmware. */ + if (fdt_add_reserved_memory(dtb, "atf@0", 0, 0x80000)) + WARN("Failed to add reserved memory nodes to DT.\n"); + ret = fdt_pack(dtb); if (ret < 0) ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret); -- cgit v1.2.3 From 882c0ff6ba65800046a851735cc848b76810196a Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 09:04:27 +0100 Subject: rpi4: Cleanup memory regions, move pens to first page Now that we have the SMP pens in the first page of DRAM, we can get rid of all the fancy RPi3 memory regions that our RPi4 port does not really need. This avoids using up memory all over the place, restricting ATF to just run in the first 512KB of DRAM. Remove the now unused regions. This also moves the SMP pens into our first memory page (holding the firmware magic), where the original firmware put them, but where there is also enough space for them. Since the pens will require code execution privileges, we amend the memory attributes used for that page to include write and execution rights. Change-Id: I131633abeb4a4d7b9057e737b9b0d163b73e47c6 Signed-off-by: Andre Przywara --- plat/rpi/rpi4/include/platform_def.h | 68 +++--------------------------------- plat/rpi/rpi4/rpi4_bl31_setup.c | 5 ++- 2 files changed, 6 insertions(+), 67 deletions(-) diff --git a/plat/rpi/rpi4/include/platform_def.h b/plat/rpi/rpi4/include/platform_def.h index 831d1c3f0..a9ecdba20 100644 --- a/plat/rpi/rpi4/include/platform_def.h +++ b/plat/rpi/rpi4/include/platform_def.h @@ -58,70 +58,12 @@ #define CACHE_WRITEBACK_SHIFT U(6) #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) -/* - * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and - * secure DRAM. Note that this is all actually DRAM with different names, - * there is no Secure RAM in the Raspberry Pi 4. - */ -#if RPI3_USE_UEFI_MAP -#define SEC_ROM_BASE ULL(0x00000000) -#define SEC_ROM_SIZE ULL(0x00010000) - -/* FIP placed after ROM to append it to BL1 with very little padding. */ -#define PLAT_RPI3_FIP_BASE ULL(0x00020000) -#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x00010000) - -/* Reserve 2M of secure SRAM and DRAM, starting at 2M */ -#define SEC_SRAM_BASE ULL(0x00200000) -#define SEC_SRAM_SIZE ULL(0x00100000) - -#define SEC_DRAM0_BASE ULL(0x00300000) -#define SEC_DRAM0_SIZE ULL(0x00100000) - -/* Windows on ARM requires some RAM at 4M */ -#define NS_DRAM0_BASE ULL(0x00400000) -#define NS_DRAM0_SIZE ULL(0x00C00000) -#else -#define SEC_ROM_BASE ULL(0x00000000) -#define SEC_ROM_SIZE ULL(0x00020000) - -/* FIP placed after ROM to append it to BL1 with very little padding. */ -#define PLAT_RPI3_FIP_BASE ULL(0x00020000) -#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x001E0000) - -/* We have 16M of memory reserved starting at 256M */ -#define SEC_SRAM_BASE ULL(0x10000000) -#define SEC_SRAM_SIZE ULL(0x00100000) - -#define SEC_DRAM0_BASE ULL(0x10100000) -#define SEC_DRAM0_SIZE ULL(0x00F00000) -/* End of reserved memory */ - -#define NS_DRAM0_BASE ULL(0x11000000) -#define NS_DRAM0_SIZE ULL(0x01000000) -#endif /* RPI3_USE_UEFI_MAP */ - -/* - * BL33 entrypoint. - */ -#define PLAT_RPI3_NS_IMAGE_OFFSET NS_DRAM0_BASE -#define PLAT_RPI3_NS_IMAGE_MAX_SIZE NS_DRAM0_SIZE - /* * I/O registers. */ #define DEVICE0_BASE RPI_IO_BASE #define DEVICE0_SIZE RPI_IO_SIZE -/* - * TF-A lives in SRAM, partition it here - */ -#define SHARED_RAM_BASE SEC_SRAM_BASE -#define SHARED_RAM_SIZE ULL(0x00001000) - -#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) -#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) - /* * Mailbox to control the secondary cores. All secondary cores are held in a * wait loop in cold boot. To release them perform the following steps (plus @@ -135,10 +77,8 @@ * * sev(); */ -#define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE - /* The secure entry point to be used on warm reset by all CPUs. */ -#define PLAT_RPI3_TM_ENTRYPOINT PLAT_RPI3_TRUSTED_MAILBOX_BASE +#define PLAT_RPI3_TM_ENTRYPOINT 0x100 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8) /* Hold entries for each CPU. */ @@ -160,11 +100,11 @@ * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the * current BL31 debug size plus a little space for growth. */ -#define PLAT_MAX_BL31_SIZE ULL(0x20000) +#define PLAT_MAX_BL31_SIZE ULL(0x80000) #define BL31_BASE ULL(0x1000) -#define BL31_LIMIT ULL(0x100000) -#define BL31_PROGBITS_LIMIT ULL(0x100000) +#define BL31_LIMIT ULL(0x80000) +#define BL31_PROGBITS_LIMIT ULL(0x80000) #define SEC_SRAM_ID 0 #define SEC_DRAM_ID 1 diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c index 8dfadf730..f8bc259f2 100644 --- a/plat/rpi/rpi4/rpi4_bl31_setup.c +++ b/plat/rpi/rpi4/rpi4_bl31_setup.c @@ -197,10 +197,9 @@ void bl31_plat_arch_setup(void) /* * Add the first page of memory, which holds the stub magic, * the kernel and the DT address. - * This is read-only, as the GPU already populated the header, - * we just need to read it. + * This also holds the secondary CPU's entrypoints and mailboxes. */ - mmap_add_region(0, 0, 4096, MT_MEMORY | MT_RO | MT_SECURE); + mmap_add_region(0, 0, 4096, MT_NON_CACHEABLE | MT_RW | MT_SECURE); rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE, BL_CODE_BASE, BL_CODE_END, -- cgit v1.2.3 From 3903a8cd108188dc2dcfc5b3cb820b639c5fce01 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 21 Jul 2019 01:45:31 +0100 Subject: rpi4: Add GIC maintenance interrupt to GIC DT node For being able to use the virtualisation support the GIC offers, we need to know the interrupt number of the maintenance interrupt. This information is missing from the official RPi4 device tree. Use libfdt to add the "interrupts" property to the GIC node, which allows hypervisors like KVM or Xen to be able to use the GIC's help on virtualising interrupts. Change-Id: Iab84f0885a5bf29fb84ca8f385e8a39d27700c75 Signed-off-by: Andre Przywara --- plat/rpi/rpi4/rpi4_bl31_setup.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c index f8bc259f2..39aa3e45d 100644 --- a/plat/rpi/rpi4/rpi4_bl31_setup.c +++ b/plat/rpi/rpi4/rpi4_bl31_setup.c @@ -222,7 +222,8 @@ static uint32_t dtb_size(const void *dtb) static void rpi4_prepare_dtb(void) { void *dtb = (void *)rpi4_get_dtb_address(); - int ret; + uint32_t gic_int_prop[3]; + int ret, offs; /* Return if no device tree is detected */ if (fdt_check_header(dtb) != 0) @@ -248,6 +249,12 @@ static void rpi4_prepare_dtb(void) if (fdt_add_reserved_memory(dtb, "atf@0", 0, 0x80000)) WARN("Failed to add reserved memory nodes to DT.\n"); + offs = fdt_node_offset_by_compatible(dtb, 0, "arm,gic-400"); + gic_int_prop[0] = cpu_to_fdt32(1); // PPI + gic_int_prop[1] = cpu_to_fdt32(9); // PPI #9 + gic_int_prop[2] = cpu_to_fdt32(0x0f04); // all cores, level high + fdt_setprop(dtb, offs, "interrupts", gic_int_prop, 12); + ret = fdt_pack(dtb); if (ret < 0) ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret); -- cgit v1.2.3 From 1a7422ebd092342fa1f4d420eb4642b0134f36ca Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 18:07:51 +0100 Subject: rpi4: Add stdout-path to device tree Some device tree users like to find a pointer to the standard serial console in the device tree, in the "stdout-path" property of the /chosen node. Add the location of the Mini UART in that property, so that DT users are happy, for instance Linux' earlycon detection. Change-Id: I178e55016e5640de5ab0bc6e061944bd3583ea96 Signed-off-by: Andre Przywara --- plat/rpi/rpi4/rpi4_bl31_setup.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c index 39aa3e45d..53ab0c2e2 100644 --- a/plat/rpi/rpi4/rpi4_bl31_setup.c +++ b/plat/rpi/rpi4/rpi4_bl31_setup.c @@ -255,6 +255,9 @@ static void rpi4_prepare_dtb(void) gic_int_prop[2] = cpu_to_fdt32(0x0f04); // all cores, level high fdt_setprop(dtb, offs, "interrupts", gic_int_prop, 12); + offs = fdt_path_offset(dtb, "/chosen"); + fdt_setprop_string(dtb, offs, "stdout-path", "serial0"); + ret = fdt_pack(dtb); if (ret < 0) ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret); -- cgit v1.2.3 From e0dea671dceebe935201f1c4796cac5774af152f Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 22 Jul 2019 10:31:10 +0100 Subject: rpi4: Add initial documentation file As the Raspberry Pi4 port is now in a usable state, add the build instructions together with some background information to the documentation directory. The port differs quite a bit from the Raspberry Pi 3, so we use a separate file for that. Change-Id: I7d9f5967fdf3ec3bfe97d78141f59cbcf03388d4 Signed-off-by: Andre Przywara --- docs/plat/rpi4.rst | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 docs/plat/rpi4.rst diff --git a/docs/plat/rpi4.rst b/docs/plat/rpi4.rst new file mode 100644 index 000000000..0f529c103 --- /dev/null +++ b/docs/plat/rpi4.rst @@ -0,0 +1,85 @@ +Raspberry Pi 4 +============== + +The `Raspberry Pi 4`_ is an inexpensive single-board computer that contains four +Arm Cortex-A72 cores. Also in contrast to previous Raspberry Pi versions this +model has a GICv2 interrupt controller. + +This port is a minimal port to support loading non-secure EL2 payloads such +as a 64-bit Linux kernel. Other payloads such as U-Boot or EDK-II should work +as well, but have not been tested at this point. + +**IMPORTANT NOTE**: This port isn't secure. All of the memory used is DRAM, +which is available from both the Non-secure and Secure worlds. The SoC does +not seem to feature a secure memory controller of any kind, so portions of +DRAM can't be protected properly from the Non-secure world. + +Build Instructions +------------------ + +There are no real configuration options at this point, so there is only +one universal binary (bl31.bin), which can be built with: + +.. code:: shell + + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi4 DEBUG=1 + +Copy the generated build/rpi4/debug/bl31.bin to the SD card, either +renaming it to ``armstub8.bin`` or adding an entry starting with ``armstub=``, +then followed by the respective file name to ``config.txt``. +You should have AArch64 code in the file loaded as the "kernel", as BL31 +will drop into AArch64/EL2 to the respective load address. +arm64 Linux kernels are known to work this way. + +Other options that should be set in ``config.txt`` to properly boot 64-bit +kernels are: + +:: + + enable_uart=1 + arm_64bit=1 + enable_gic=1 + +The BL31 code will patch the provided device tree blob in memory to advertise +PSCI support, also will add a reserved-memory node to the DT to tell the +non-secure payload to not touch the resident TF-A code. + +If you connect a serial cable between the Mini UART and your computer, and +connect to it (for example, with ``screen /dev/ttyUSB0 115200``) you should +see some text from BL31, followed by the output of the EL2 payload. +The command line provided is read from the ``cmdline.txt`` file on the SD card. + +TF-A port design +---------------- + +In contrast to the existing Raspberry Pi 3 port this one here is a BL31-only +port, also it deviates quite a lot from the RPi3 port in many other ways. +There is not so much difference between the two models, so eventually those +two could be (more) unified in the future. + +As with the previous models, the GPU and its firmware are the first entity to +run after the SoC gets its power. The on-chip Boot ROM loads the next stage +(bootcode.bin) from flash (EEPROM), which is again GPU code. +This part knows how to access the MMC controller and how to parse a FAT +filesystem, so it will load further compononents and configuration files +from the first FAT partition on the SD card. + +To accommodate this existing way of configuring and setting up the board, +we use as much of this workflow as possible. +If bootcode.bin finds a file called ``armstub8.bin`` on the SD card or it gets +pointed to such code by finding a ``armstub=`` key in ``config.txt``, it will +load this file to the beginning of DRAM (address 0) and execute it in +AArch64 EL3. +But before doing that, it will also load a "kernel" and the device tree into +memory. The load addresses have a default, but can also be changed by +setting them in ``config.txt``. If the GPU firmware finds a magic value in the +armstub image file, it will put those two load addresses in memory locations +near the beginning of memory, where TF-A code picks them up. + +To keep things simple, we will just use the kernel load address as the BL33 +entry point, also put the DTB address in the x0 register, as requested by +the arm64 Linux kernel boot protocol. This does not necessarily mean that +the EL2 payload needs to be a Linux kernel, a bootloader or any other kernel +would work as well, as long as it can cope with having the DT address in +register x0. If the payload has other means of finding the device tree, it +could ignore this address as well. -- cgit v1.2.3 From f1e0f15262cf3f19bf2edd93a0d70d6903e2733c Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Wed, 25 Sep 2019 12:58:36 +0000 Subject: doc: Fix platform port inclusion This patch: - Adds any leftover platform ports that were not having their documentation built (not in the index.rst table of contents) - Corrects a handful of RST formatting errors that cause poor rendering - Reorders the list of platforms so that they are displayed in alphabetical order Change-Id: If8c135a822d581c3c5c4fca2936d501ccfd2e94c Signed-off-by: Paul Beesley --- docs/plat/hikey.rst | 10 +++++----- docs/plat/hikey960.rst | 10 +++++----- docs/plat/index.rst | 20 ++++++++++++-------- docs/plat/intel-agilex.rst | 1 + docs/plat/intel-stratix10.rst | 1 + docs/plat/poplar.rst | 12 ++++++------ 6 files changed, 30 insertions(+), 24 deletions(-) diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst index 74ff2f46c..372d38867 100644 --- a/docs/plat/hikey.rst +++ b/docs/plat/hikey.rst @@ -1,15 +1,15 @@ -Description -=========== +HiKey +===== HiKey is one of 96boards. Hisilicon Kirin6220 processor is installed on HiKey. More information are listed in `link`_. How to build -============ +------------ Code Locations --------------- +~~~~~~~~~~~~~~ - Trusted Firmware-A: `link `__ @@ -33,7 +33,7 @@ Code Locations `link `__ Build Procedure ---------------- +~~~~~~~~~~~~~~~ - Fetch all the above repositories into local host. Make all the repositories in the same ${BUILD\_PATH}. diff --git a/docs/plat/hikey960.rst b/docs/plat/hikey960.rst index 7ddb0b104..3d42a77c5 100644 --- a/docs/plat/hikey960.rst +++ b/docs/plat/hikey960.rst @@ -1,15 +1,15 @@ -Description -=========== +HiKey960 +======== HiKey960 is one of 96boards. Hisilicon Hi3660 processor is installed on HiKey960. More information are listed in `link`_. How to build -============ +------------ Code Locations --------------- +~~~~~~~~~~~~~~ - Trusted Firmware-A: `link `__ @@ -30,7 +30,7 @@ Code Locations `link `__ Build Procedure ---------------- +~~~~~~~~~~~~~~~ - Fetch all the above 5 repositories into local host. Make all the repositories in the same ${BUILD\_PATH}. diff --git a/docs/plat/index.rst b/docs/plat/index.rst index eaeee84f3..2695d4e81 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -7,24 +7,28 @@ Platform Ports :numbered: allwinner + meson-gxbb + meson-gxl fvp_ve - imx8 - imx8m + hikey + hikey960 + intel-agilex intel-stratix10 - ls1043a marvell/index - meson-gxbb - meson-gxl mt8183 nvidia-tegra + warp7 + imx8 + imx8m + ls1043a + poplar qemu + rpi3 rcar-gen3 rockchip - rpi3 socionext-uniphier - stm32mp1 synquacer + stm32mp1 ti-k3 - warp7 xilinx-versal xilinx-zynqmp diff --git a/docs/plat/intel-agilex.rst b/docs/plat/intel-agilex.rst index 015a195a8..ff27b6b5f 100644 --- a/docs/plat/intel-agilex.rst +++ b/docs/plat/intel-agilex.rst @@ -67,6 +67,7 @@ Boot trace ---------- :: + INFO: DDR: DRAM calibration success. INFO: ECC is disabled. NOTICE: BL2: v2.1(debug) diff --git a/docs/plat/intel-stratix10.rst b/docs/plat/intel-stratix10.rst index 77a45a478..7f8d18e03 100644 --- a/docs/plat/intel-stratix10.rst +++ b/docs/plat/intel-stratix10.rst @@ -67,6 +67,7 @@ Boot trace ---------- :: + INFO: DDR: DRAM calibration success. INFO: ECC is disabled. INFO: Init HPS NOC's DDR Scheduler. diff --git a/docs/plat/poplar.rst b/docs/plat/poplar.rst index 5884ed945..215f55142 100644 --- a/docs/plat/poplar.rst +++ b/docs/plat/poplar.rst @@ -1,5 +1,5 @@ -Description -=========== +Poplar +====== Poplar is the first development board compliant with the 96Boards Enterprise Edition TV Platform specification. @@ -35,10 +35,10 @@ must happen prior to invoking Trusted Firmware-A: l-loader --> Trusted Firmware-A --> u-boot How to build -============ +------------ Code Locations --------------- +~~~~~~~~~~~~~~ - Trusted Firmware-A: `link `__ @@ -50,7 +50,7 @@ Code Locations `link `__ Build Procedure ---------------- +~~~~~~~~~~~~~~~ - Fetch all the above 3 repositories into local host. Make all the repositories in the same ${BUILD\_PATH}. @@ -89,7 +89,7 @@ The system will boot into a u-boot shell which you can then use to write the working firmware to eMMC. Boot trace -========== +---------- :: -- cgit v1.2.3 From ec834925f3cb5cb3934010bbc8077293e610d2ac Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Wed, 15 May 2019 18:25:41 -0500 Subject: GICv3: Enable multi socket GIC redistributor frame discovery This patch provides declaration and definition of new GICv3 driver API: gicv3_rdistif_probe().This function delegates the responsibility of discovering the corresponding Redistributor base frame to each CPU itself. It is a modified version of gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform unlike the previous approach in which only the Primary CPU did the discovery of all the Redistributor frames for every CPU. The flush operations as part of gicv3_driver_init() function are made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY because the GICv3 driver data structure contents are accessed by CPU with D-Cache turned off during power down operations. Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268 Signed-off-by: Madhukar Pappireddy --- drivers/arm/gic/v3/gicv3_main.c | 147 ++++++++++++++++++++++++++++++---------- include/drivers/arm/gicv3.h | 3 +- 2 files changed, 115 insertions(+), 35 deletions(-) diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 94a20ba07..f37133096 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -16,7 +16,6 @@ #include "gicv3_private.h" const gicv3_driver_data_t *gicv3_driver_data; -static unsigned int gicv2_compat; /* * Spinlock to guard registers needing read-modify-write. APIs protected by this @@ -60,51 +59,61 @@ static spinlock_t gic_lock; void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) { unsigned int gic_version; + unsigned int gicv2_compat; assert(plat_driver_data != NULL); assert(plat_driver_data->gicd_base != 0U); - assert(plat_driver_data->gicr_base != 0U); assert(plat_driver_data->rdistif_num != 0U); assert(plat_driver_data->rdistif_base_addrs != NULL); assert(IS_IN_EL3()); - assert(plat_driver_data->interrupt_props_num > 0 ? - plat_driver_data->interrupt_props != NULL : 1); + assert((plat_driver_data->interrupt_props_num != 0U) ? + (plat_driver_data->interrupt_props != NULL) : 1); /* Check for system register support */ -#ifdef __aarch64__ +#ifndef __aarch64__ + assert((read_id_pfr1() & + (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); +#else assert((read_id_aa64pfr0_el1() & (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); -#else - assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); -#endif /* __aarch64__ */ +#endif /* !__aarch64__ */ /* The GIC version should be 3.0 */ gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); - gic_version >>= PIDR2_ARCH_REV_SHIFT; + gic_version >>= PIDR2_ARCH_REV_SHIFT; gic_version &= PIDR2_ARCH_REV_MASK; assert(gic_version == ARCH_REV_GICV3); /* - * Find out whether the GIC supports the GICv2 compatibility mode. The - * ARE_S bit resets to 0 if supported + * Find out whether the GIC supports the GICv2 compatibility mode. + * The ARE_S bit resets to 0 if supported */ gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); gicv2_compat >>= CTLR_ARE_S_SHIFT; - gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); - - /* - * Find the base address of each implemented Redistributor interface. - * The number of interfaces should be equal to the number of CPUs in the - * system. The memory for saving these addresses has to be allocated by - * the platform port - */ - gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, - plat_driver_data->rdistif_num, - plat_driver_data->gicr_base, - plat_driver_data->mpidr_to_core_pos); - + gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; + + if (plat_driver_data->gicr_base != 0U) { + /* + * Find the base address of each implemented Redistributor interface. + * The number of interfaces should be equal to the number of CPUs in the + * system. The memory for saving these addresses has to be allocated by + * the platform port + */ + gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, + plat_driver_data->rdistif_num, + plat_driver_data->gicr_base, + plat_driver_data->mpidr_to_core_pos); +#if !HW_ASSISTED_COHERENCY + /* + * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. + */ + flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), + plat_driver_data->rdistif_num * + sizeof(*(plat_driver_data->rdistif_base_addrs))); +#endif + } gicv3_driver_data = plat_driver_data; /* @@ -112,19 +121,19 @@ void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) * enabled. When the secondary CPU boots up, it initializes the * GICC/GICR interface with the caches disabled. Hence flush the * driver data to ensure coherency. This is not required if the - * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY - * enabled. + * platform has HW_ASSISTED_COHERENCY enabled. */ -#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) - flush_dcache_range((uintptr_t) &gicv3_driver_data, - sizeof(gicv3_driver_data)); - flush_dcache_range((uintptr_t) gicv3_driver_data, - sizeof(*gicv3_driver_data)); +#if !HW_ASSISTED_COHERENCY + flush_dcache_range((uintptr_t)&gicv3_driver_data, + sizeof(gicv3_driver_data)); + flush_dcache_range((uintptr_t)gicv3_driver_data, + sizeof(*gicv3_driver_data)); #endif - INFO("GICv3 %s legacy support detected." - " ARM GICV3 driver initialized in EL3\n", - gicv2_compat ? "with" : "without"); + INFO("GICv3 with%s legacy support detected." + " ARM GICv3 driver initialized in EL3\n", + (gicv2_compat == 0U) ? "" : "out"); + } /******************************************************************************* @@ -192,6 +201,7 @@ void gicv3_rdistif_init(unsigned int proc_num) gicv3_rdistif_on(proc_num); gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + assert(gicr_base != 0U); /* Set the default attribute of all SGIs and PPIs */ gicv3_ppi_sgi_config_defaults(gicr_base); @@ -313,6 +323,7 @@ void gicv3_cpuif_disable(unsigned int proc_num) /* Mark the connected core as asleep */ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + assert(gicr_base != 0U); gicv3_rdistif_mark_core_asleep(gicr_base); } @@ -1081,3 +1092,71 @@ unsigned int gicv3_set_pmr(unsigned int mask) return old_mask; } + +/******************************************************************************* + * This function delegates the responsibility of discovering the corresponding + * Redistributor frames to each CPU itself. It is a modified version of + * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform + * unlike the previous way in which only the Primary CPU did the discovery of + * all the Redistributor frames for every CPU. It also handles the scenario in + * which the frames of various CPUs are not contiguous in physical memory. + ******************************************************************************/ +int gicv3_rdistif_probe(const uintptr_t gicr_frame) +{ + u_register_t mpidr; + unsigned int proc_num, proc_self; + uint64_t typer_val; + uintptr_t rdistif_base; + bool gicr_frame_found = false; + + assert(gicv3_driver_data->gicr_base == 0U); + + /* Ensure this function is called with Data Cache enabled */ +#ifndef __aarch64__ + assert((read_sctlr() & SCTLR_C_BIT) != 0U); +#else + assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); +#endif /* !__aarch64__ */ + + proc_self = gicv3_driver_data->mpidr_to_core_pos(read_mpidr_el1()); + rdistif_base = gicr_frame; + do { + typer_val = gicr_read_typer(rdistif_base); + if (gicv3_driver_data->mpidr_to_core_pos != NULL) { + mpidr = mpidr_from_gicr_typer(typer_val); + proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); + } else { + proc_num = (unsigned int)(typer_val >> TYPER_PROC_NUM_SHIFT) & + TYPER_PROC_NUM_MASK; + } + if (proc_num == proc_self) { + /* The base address doesn't need to be initialized on + * every warm boot. + */ + if (gicv3_driver_data->rdistif_base_addrs[proc_num] != 0U) + return 0; + gicv3_driver_data->rdistif_base_addrs[proc_num] = + rdistif_base; + gicr_frame_found = true; + break; + } + rdistif_base += (uintptr_t)(ULL(1) << GICR_PCPUBASE_SHIFT); + } while ((typer_val & TYPER_LAST_BIT) == 0U); + + if (!gicr_frame_found) + return -1; + + /* + * Flush the driver data to ensure coherency. This is + * not required if platform has HW_ASSISTED_COHERENCY + * enabled. + */ +#if !HW_ASSISTED_COHERENCY + /* + * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. + */ + flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), + sizeof(*(gicv3_driver_data->rdistif_base_addrs))); +#endif + return 0; /* Found matching GICR frame */ +} diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 9c72d4dff..c4f42d04d 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -366,6 +366,7 @@ typedef struct gicv3_its_ctx { * GICv3 EL3 driver API ******************************************************************************/ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); +int gicv3_rdistif_probe(const uintptr_t gicr_frame); void gicv3_distif_init(void); void gicv3_rdistif_init(unsigned int proc_num); void gicv3_rdistif_on(unsigned int proc_num); -- cgit v1.2.3 From 10107707196d67731de57126b846169c5b29aac0 Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Mon, 12 Aug 2019 18:31:33 -0500 Subject: Adding new optional PSCI hook pwr_domain_on_finish_late This PSCI hook is similar to pwr_domain_on_finish but is guaranteed to be invoked with the respective core and cluster are participating in coherency. This will be necessary to safely invoke the new GICv3 API which modifies shared GIC data structures concurrently. Change-Id: I8e54f05c9d4ef5712184c9c18ba45ac97a29eb7a Signed-off-by: Madhukar Pappireddy --- docs/getting_started/porting-guide.rst | 13 +++++++++++++ include/lib/psci/psci.h | 4 +++- lib/psci/psci_on.c | 10 +++++++++- 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index 5786dd384..af36b6a5f 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -2202,6 +2202,19 @@ immediately before the CPU was turned on. It indicates which power domains above the CPU might require initialization due to having previously been in low power states. The generic code expects the handler to succeed. +plat_psci_ops.pwr_domain_on_finish_late() [optional] +........................................................... + +This optional function is called by the PSCI implementation after the calling +CPU is fully powered on with respective data caches enabled. The calling CPU and +the associated cluster are guaranteed to be participating in coherency. This +function gives the flexibility to perform any platform-specific actions safely, +such as initialization or modification of shared data structures, without the +overhead of explicit cache maintainace operations. + +The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` +operation. The generic code expects the handler to succeed. + plat_psci_ops.pwr_domain_suspend_finish() ......................................... diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h index 04e5e3d72..7f7b7e3ff 100644 --- a/include/lib/psci/psci.h +++ b/include/lib/psci/psci.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -301,6 +301,8 @@ typedef struct plat_psci_ops { const psci_power_state_t *target_state); void (*pwr_domain_suspend)(const psci_power_state_t *target_state); void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); + void (*pwr_domain_on_finish_late)( + const psci_power_state_t *target_state); void (*pwr_domain_suspend_finish)( const psci_power_state_t *target_state); void __dead2 (*pwr_domain_pwr_down_wfi)( diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c index aa6b324ed..470b4f33e 100644 --- a/lib/psci/psci_on.c +++ b/lib/psci/psci_on.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -181,6 +181,14 @@ void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info) psci_do_pwrup_cache_maintenance(); #endif + /* + * Plat. management: Perform any platform specific actions which + * can only be done with the cpu and the cluster guaranteed to + * be coherent. + */ + if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL) + psci_plat_pm_ops->pwr_domain_on_finish_late(state_info); + /* * All the platform specific actions for turning this cpu * on have completed. Perform enough arch.initialization -- cgit v1.2.3 From 6806cd2381901d424b40ba3f17d23f5ffa4ca57e Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Mon, 10 Jun 2019 16:54:36 -0500 Subject: Migrate ARM platforms to use the new GICv3 API This patch invokes the new function gicv3_rdistif_probe() in the ARM platform specific gicv3 driver. Since this API modifies the shared GIC related data structure, it must be invoked coherently by using the platform specific pwr_domain_on_finish_late hook. Change-Id: I6efb17d5da61545a1c5a6641b8f58472b31e62a8 Signed-off-by: Madhukar Pappireddy --- include/plat/arm/css/common/css_pm.h | 1 + plat/arm/board/fvp/fvp_pm.c | 18 ++++++++++++++---- plat/arm/common/arm_gicv3.c | 20 ++++++++++++++++++-- plat/arm/css/common/css_pm.c | 22 +++++++++++++++++----- 4 files changed, 50 insertions(+), 11 deletions(-) diff --git a/include/plat/arm/css/common/css_pm.h b/include/plat/arm/css/common/css_pm.h index b82ff47e7..93f86162e 100644 --- a/include/plat/arm/css/common/css_pm.h +++ b/include/plat/arm/css/common/css_pm.h @@ -27,6 +27,7 @@ static inline unsigned int css_system_pwr_state(const psci_power_state_t *state) int css_pwr_domain_on(u_register_t mpidr); void css_pwr_domain_on_finish(const psci_power_state_t *target_state); +void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state); void css_pwr_domain_off(const psci_power_state_t *target_state); void css_pwr_domain_suspend(const psci_power_state_t *target_state); void css_pwr_domain_suspend_finish( diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c index 42dec8dfc..0a62543fa 100644 --- a/plat/arm/board/fvp/fvp_pm.c +++ b/plat/arm/board/fvp/fvp_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -247,10 +247,19 @@ static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) { fvp_power_domain_on_finish_common(target_state); - /* Enable the gic cpu interface */ +} + +/******************************************************************************* + * FVP handler called when a power domain has just been powered on and the cpu + * and its cluster are fully participating in coherent transaction on the + * interconnect. Data cache must be enabled for CPU at this point. + ******************************************************************************/ +static void fvp_pwr_domain_on_finish_late(const psci_power_state_t *target_state) +{ + /* Program GIC per-cpu distributor or re-distributor interface */ plat_arm_gic_pcpu_init(); - /* Program the gic per-cpu distributor or re-distributor interface */ + /* Enable GIC CPU interface */ plat_arm_gic_cpuif_enable(); } @@ -272,7 +281,7 @@ static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state fvp_power_domain_on_finish_common(target_state); - /* Enable the gic cpu interface */ + /* Enable GIC CPU interface */ plat_arm_gic_cpuif_enable(); } @@ -397,6 +406,7 @@ plat_psci_ops_t plat_arm_psci_pm_ops = { .pwr_domain_off = fvp_pwr_domain_off, .pwr_domain_suspend = fvp_pwr_domain_suspend, .pwr_domain_on_finish = fvp_pwr_domain_on_finish, + .pwr_domain_on_finish_late = fvp_pwr_domain_on_finish_late, .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, .system_off = fvp_system_off, .system_reset = fvp_system_reset, diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index 7f4957fa9..fef53761c 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include @@ -67,7 +68,7 @@ static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr) static const gicv3_driver_data_t arm_gic_data __unused = { .gicd_base = PLAT_ARM_GICD_BASE, - .gicr_base = PLAT_ARM_GICR_BASE, + .gicr_base = 0U, .interrupt_props = arm_interrupt_props, .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), .rdistif_num = PLATFORM_CORE_COUNT, @@ -86,6 +87,11 @@ void __init plat_arm_gic_driver_init(void) #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \ (defined(__aarch64__) && defined(IMAGE_BL31)) gicv3_driver_init(&arm_gic_data); + + if (gicv3_rdistif_probe(PLAT_ARM_GICR_BASE) == -1) { + ERROR("No GICR base frame found for Primary CPU\n"); + panic(); + } #endif } @@ -116,10 +122,20 @@ void plat_arm_gic_cpuif_disable(void) } /****************************************************************************** - * ARM common helper to initialize the per-cpu redistributor interface in GICv3 + * ARM common helper function to iterate over all GICR frames and discover the + * corresponding per-cpu redistributor frame as well as initialize the + * corresponding interface in GICv3. At the moment, Arm platforms do not have + * non-contiguous GICR frames. *****************************************************************************/ void plat_arm_gic_pcpu_init(void) { + int result; + + result = gicv3_rdistif_probe(PLAT_ARM_GICR_BASE); + if (result == -1) { + ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); + panic(); + } gicv3_rdistif_init(plat_my_core_pos()); } diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c index f6fc6aa7a..01c674f82 100644 --- a/plat/arm/css/common/css_pm.c +++ b/plat/arm/css/common/css_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -76,9 +76,6 @@ static void css_pwr_domain_on_finisher_common( { assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); - /* Enable the gic cpu interface */ - plat_arm_gic_cpuif_enable(); - /* * Perform the common cluster specific operations i.e enable coherency * if this cluster was off. @@ -100,10 +97,21 @@ void css_pwr_domain_on_finish(const psci_power_state_t *target_state) /* Assert that the system power domain need not be initialized */ assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); + css_pwr_domain_on_finisher_common(target_state); +} + +/******************************************************************************* + * Handler called when a power domain has just been powered on and the cpu + * and its cluster are fully participating in coherent transaction on the + * interconnect. Data cache must be enabled for CPU at this point. + ******************************************************************************/ +void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state) +{ /* Program the gic per-cpu distributor or re-distributor interface */ plat_arm_gic_pcpu_init(); - css_pwr_domain_on_finisher_common(target_state); + /* Enable the gic cpu interface */ + plat_arm_gic_cpuif_enable(); } /******************************************************************************* @@ -185,6 +193,9 @@ void css_pwr_domain_suspend_finish( arm_system_pwr_domain_resume(); css_pwr_domain_on_finisher_common(target_state); + + /* Enable the gic cpu interface */ + plat_arm_gic_cpuif_enable(); } /******************************************************************************* @@ -306,6 +317,7 @@ static int css_translate_power_state_by_mpidr(u_register_t mpidr, plat_psci_ops_t plat_arm_psci_pm_ops = { .pwr_domain_on = css_pwr_domain_on, .pwr_domain_on_finish = css_pwr_domain_on_finish, + .pwr_domain_on_finish_late = css_pwr_domain_on_finish_late, .pwr_domain_off = css_pwr_domain_off, .cpu_standby = css_cpu_standby, .pwr_domain_suspend = css_pwr_domain_suspend, -- cgit v1.2.3 From cdb8c52f922b5c4d972e398a72ac89d100937507 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 18 Sep 2019 11:29:48 +0100 Subject: amlogic: g12a: Add support for the S905X2 (G12A) platform Introduce the preliminary support for the Amlogic S905X2 (G12A) SoC. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux. Tested on a SEI510 board. Signed-off-by: Carlo Caione Change-Id: Ife958f10e815a4530292c45446adb71239f3367f --- docs/maintainers.rst | 8 ++ docs/plat/meson-g12a.rst | 27 ++++ plat/amlogic/g12a/g12a_bl31_setup.c | 142 ++++++++++++++++++++ plat/amlogic/g12a/g12a_common.c | 125 ++++++++++++++++++ plat/amlogic/g12a/g12a_def.h | 135 +++++++++++++++++++ plat/amlogic/g12a/g12a_pm.c | 215 +++++++++++++++++++++++++++++++ plat/amlogic/g12a/include/platform_def.h | 63 +++++++++ plat/amlogic/g12a/platform.mk | 91 +++++++++++++ 8 files changed, 806 insertions(+) create mode 100644 docs/plat/meson-g12a.rst create mode 100644 plat/amlogic/g12a/g12a_bl31_setup.c create mode 100644 plat/amlogic/g12a/g12a_common.c create mode 100644 plat/amlogic/g12a/g12a_def.h create mode 100644 plat/amlogic/g12a/g12a_pm.c create mode 100644 plat/amlogic/g12a/include/platform_def.h create mode 100644 plat/amlogic/g12a/platform.mk diff --git a/docs/maintainers.rst b/docs/maintainers.rst index 7731c72ec..d997baace 100644 --- a/docs/maintainers.rst +++ b/docs/maintainers.rst @@ -48,6 +48,14 @@ Amlogic Meson S905x (GXL) platform port :F: drivers/amlogic/gxl :F: plat/amlogic/gxl/ +Amlogic Meson S905X2 (G12A) platform port +--------------------------------------- +:M: Carlo Caione +:G: `carlo.caione`_ +:F: docs/plat/meson-g12a.rst +:F: drivers/amlogic/g12a +:F: plat/amlogic/g12a/ + Armv7-A architecture port ------------------------- :M: Etienne Carriere diff --git a/docs/plat/meson-g12a.rst b/docs/plat/meson-g12a.rst new file mode 100644 index 000000000..1021da47c --- /dev/null +++ b/docs/plat/meson-g12a.rst @@ -0,0 +1,27 @@ +Amlogic Meson S905X2 (G12A) +========================== + +The Amlogic Meson S905X2 is a SoC with a quad core Arm Cortex-A53 running at +~1.8GHz. It also contains a Cortex-M3 used as SCP. + +This port is a minimal implementation of BL31 capable of booting mainline U-Boot +and Linux: + +- SCPI support. +- Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0 + can't be turned off, so there is a workaround to hide this from the caller. +- GICv2 driver set up. +- Basic SIP services (read efuse data, enable/disable JTAG). + +In order to build it: + +.. code:: shell + + CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=g12a + +This port has been tested on a SEI510 board. After building it, follow the +instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the +mentioned **bl31.img** by the one built from this port. + +.. _gxlimg repository: https://github.com/repk/gxlimg/blob/master/README.g12a +.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/board/amlogic/sei510/README diff --git a/plat/amlogic/g12a/g12a_bl31_setup.c b/plat/amlogic/g12a/g12a_bl31_setup.c new file mode 100644 index 000000000..77057a17f --- /dev/null +++ b/plat/amlogic/g12a/g12a_bl31_setup.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "aml_private.h" + +/* + * Placeholder variables for copying the arguments that have been passed to + * BL31 from BL2. + */ +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; +static image_info_t bl30_image_info; +static image_info_t bl301_image_info; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + next_image_info = (type == NON_SECURE) ? + &bl33_image_ep_info : &bl32_image_ep_info; + + /* None of the images can have 0x0 as the entrypoint. */ + if (next_image_info->pc != 0U) + return next_image_info; + + return NULL; +} + +/******************************************************************************* + * Perform any BL31 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before + * they are lost (potentially). This needs to be done before the MMU is + * initialized so that the memory layout can be used while creating page + * tables. BL2 has flushed this information to memory, so we are guaranteed + * to pick up good data. + ******************************************************************************/ +struct g12a_bl31_param { + param_header_t h; + image_info_t *bl31_image_info; + entry_point_info_t *bl32_ep_info; + image_info_t *bl32_image_info; + entry_point_info_t *bl33_ep_info; + image_info_t *bl33_image_info; + image_info_t *scp_image_info[]; +}; + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + struct g12a_bl31_param *from_bl2; + + /* Initialize the console to provide early debug support */ + aml_console_init(); + + from_bl2 = (struct g12a_bl31_param *)arg0; + + /* Check params passed from BL2 are not NULL. */ + assert(from_bl2 != NULL); + assert(from_bl2->h.type == PARAM_BL31); + assert(from_bl2->h.version >= VERSION_1); + + /* + * Copy BL32 and BL33 entry point information. It is stored in Secure + * RAM, in BL2's address space. + */ + bl32_image_ep_info = *from_bl2->bl32_ep_info; + bl33_image_ep_info = *from_bl2->bl33_ep_info; + + if (bl33_image_ep_info.pc == 0U) { + ERROR("BL31: BL33 entrypoint not obtained from BL2\n"); + panic(); + } + + bl30_image_info = *from_bl2->scp_image_info[0]; + bl301_image_info = *from_bl2->scp_image_info[1]; +} + +void bl31_plat_arch_setup(void) +{ + aml_setup_page_tables(); + + enable_mmu_el3(0); +} + +/******************************************************************************* + * GICv2 driver setup information + ******************************************************************************/ +static const interrupt_prop_t g12a_interrupt_props[] = { + INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL) +}; + +static const gicv2_driver_data_t g12a_gic_data = { + .gicd_base = AML_GICD_BASE, + .gicc_base = AML_GICC_BASE, + .interrupt_props = g12a_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(g12a_interrupt_props) +}; + +void bl31_platform_setup(void) +{ + aml_mhu_secure_init(); + + gicv2_driver_init(&g12a_gic_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} diff --git a/plat/amlogic/g12a/g12a_common.c b/plat/amlogic/g12a/g12a_common.c new file mode 100644 index 000000000..e74ed0466 --- /dev/null +++ b/plat/amlogic/g12a/g12a_common.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Platform memory map regions + ******************************************************************************/ +#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \ + AML_NSDRAM0_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_NS_SHARE_MEM MAP_REGION_FLAT(AML_NS_SHARE_MEM_BASE, \ + AML_NS_SHARE_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_SEC_SHARE_MEM MAP_REGION_FLAT(AML_SEC_SHARE_MEM_BASE, \ + AML_SEC_SHARE_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \ + AML_SEC_DEVICE0_SIZE, \ + MT_DEVICE | MT_RW) + +#define MAP_HDCP_RX MAP_REGION_FLAT(AML_HDCP_RX_BASE, \ + AML_HDCP_RX_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_HDCP_TX MAP_REGION_FLAT(AML_HDCP_TX_BASE, \ + AML_HDCP_TX_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_GIC_DEVICE MAP_REGION_FLAT(AML_GIC_DEVICE_BASE, \ + AML_GIC_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \ + AML_SEC_DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \ + AML_SEC_DEVICE2_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \ + AML_TZRAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +static const mmap_region_t g12a_mmap[] = { + MAP_NSDRAM0, + MAP_NS_SHARE_MEM, + MAP_SEC_SHARE_MEM, + MAP_SEC_DEVICE0, + MAP_HDCP_RX, + MAP_HDCP_TX, + MAP_GIC_DEVICE, + MAP_SEC_DEVICE1, + MAP_SEC_DEVICE2, + MAP_TZRAM, + {0} +}; + +/******************************************************************************* + * Per-image regions + ******************************************************************************/ +#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \ + BL31_END - BL31_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) + +#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \ + BL_RO_DATA_END - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) + +#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/******************************************************************************* + * Function that sets up the translation tables. + ******************************************************************************/ +void aml_setup_page_tables(void) +{ +#if IMAGE_BL31 + const mmap_region_t g12a_bl_mmap[] = { + MAP_BL31, + MAP_BL_CODE, + MAP_BL_RO_DATA, +#if USE_COHERENT_MEM + MAP_BL_COHERENT, +#endif + {0} + }; +#endif + + mmap_add(g12a_bl_mmap); + + mmap_add(g12a_mmap); + + init_xlat_tables(); +} + +/******************************************************************************* + * Function that returns the system counter frequency + ******************************************************************************/ +unsigned int plat_get_syscnt_freq2(void) +{ + mmio_clrbits_32(AML_SYS_CPU_CFG7, ~0xFDFFFFFF); + mmio_clrbits_32(AML_AO_TIMESTAMP_CNTL, ~0xFFFFFE00); + + return AML_OSC24M_CLK_IN_HZ; +} diff --git a/plat/amlogic/g12a/g12a_def.h b/plat/amlogic/g12a/g12a_def.h new file mode 100644 index 000000000..d032815f6 --- /dev/null +++ b/plat/amlogic/g12a/g12a_def.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef G12A_DEF_H +#define G12A_DEF_H + +#include + +/******************************************************************************* + * System oscillator + ******************************************************************************/ +#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ + +/******************************************************************************* + * Memory regions + ******************************************************************************/ +#define AML_HDCP_RX_BASE UL(0xFFE0D000) +#define AML_HDCP_RX_SIZE UL(0x00002000) + +#define AML_HDCP_TX_BASE UL(0xFFE01000) +#define AML_HDCP_TX_SIZE UL(0x00001000) + +#define AML_NS_SHARE_MEM_BASE UL(0x05000000) +#define AML_NS_SHARE_MEM_SIZE UL(0x00100000) + +#define AML_SEC_SHARE_MEM_BASE UL(0x05200000) +#define AML_SEC_SHARE_MEM_SIZE UL(0x00100000) + +#define AML_GIC_DEVICE_BASE UL(0xFFC00000) +#define AML_GIC_DEVICE_SIZE UL(0x00008000) + +#define AML_NSDRAM0_BASE UL(0x01000000) +#define AML_NSDRAM0_SIZE UL(0x0F000000) + +#define BL31_BASE UL(0x05100000) +#define BL31_SIZE UL(0x00100000) +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + +/* Shared memory used for SMC services */ +#define AML_SHARE_MEM_INPUT_BASE UL(0x050FE000) +#define AML_SHARE_MEM_OUTPUT_BASE UL(0x050FF000) + +#define AML_SEC_DEVICE0_BASE UL(0xFFD00000) +#define AML_SEC_DEVICE0_SIZE UL(0x00026000) + +#define AML_SEC_DEVICE1_BASE UL(0xFF800000) +#define AML_SEC_DEVICE1_SIZE UL(0x0000A000) + +#define AML_TZRAM_BASE UL(0xFFFA0000) +#define AML_TZRAM_SIZE UL(0x00048000) + +/* Mailboxes */ +#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xFFFE7800) +#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xFFFE7A00) +#define AML_PSCI_MAILBOX_BASE UL(0xFFFE7F00) + +#define AML_SEC_DEVICE2_BASE UL(0xFF620000) +#define AML_SEC_DEVICE2_SIZE UL(0x00028000) + +/******************************************************************************* + * GIC-400 and interrupt handling related constants + ******************************************************************************/ +#define AML_GICD_BASE UL(0xFFC01000) +#define AML_GICC_BASE UL(0xFFC02000) + +#define IRQ_SEC_PHY_TIMER 29 + +#define IRQ_SEC_SGI_0 8 +#define IRQ_SEC_SGI_1 9 +#define IRQ_SEC_SGI_2 10 +#define IRQ_SEC_SGI_3 11 +#define IRQ_SEC_SGI_4 12 +#define IRQ_SEC_SGI_5 13 +#define IRQ_SEC_SGI_6 14 +#define IRQ_SEC_SGI_7 15 +#define IRQ_SEC_SGI_8 16 + +/******************************************************************************* + * UART definitions + ******************************************************************************/ +#define AML_UART0_AO_BASE UL(0xFF803000) +#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ +#define AML_UART_BAUDRATE U(115200) + +/******************************************************************************* + * Memory-mapped I/O Registers + ******************************************************************************/ +#define AML_AO_TIMESTAMP_CNTL UL(0xFF8000B4) + +#define AML_SYS_CPU_CFG7 UL(0xFF634664) + +#define AML_AO_RTI_STATUS_REG3 UL(0xFF80001C) +#define AML_AO_RTI_SCP_STAT UL(0xFF80023C) +#define AML_AO_RTI_SCP_READY_OFF U(0x14) +#define AML_A0_RTI_SCP_READY_MASK U(3) +#define AML_AO_RTI_SCP_IS_READY(v) \ + ((((v) >> AML_AO_RTI_SCP_READY_OFF) & \ + AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK) + +#define AML_HIU_MAILBOX_SET_0 UL(0xFF63C404) +#define AML_HIU_MAILBOX_STAT_0 UL(0xFF63C408) +#define AML_HIU_MAILBOX_CLR_0 UL(0xFF63C40C) +#define AML_HIU_MAILBOX_SET_3 UL(0xFF63C428) +#define AML_HIU_MAILBOX_STAT_3 UL(0xFF63C42C) +#define AML_HIU_MAILBOX_CLR_3 UL(0xFF63C430) + +#define AML_SHA_DMA_BASE UL(0xFF63E000) +#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08) +#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x28) + +/******************************************************************************* + * System Monitor Call IDs and arguments + ******************************************************************************/ +#define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) +#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) + +#define AML_SM_EFUSE_READ U(0x82000030) +#define AML_SM_EFUSE_USER_MAX U(0x82000033) + +#define AML_SM_JTAG_ON U(0x82000040) +#define AML_SM_JTAG_OFF U(0x82000041) +#define AML_SM_GET_CHIP_ID U(0x82000044) + +#define AML_JTAG_STATE_ON U(0) +#define AML_JTAG_STATE_OFF U(1) + +#define AML_JTAG_M3_AO U(0) +#define AML_JTAG_M3_EE U(1) +#define AML_JTAG_A53_AO U(2) +#define AML_JTAG_A53_EE U(3) + +#endif /* G12A_DEF_H */ diff --git a/plat/amlogic/g12a/g12a_pm.c b/plat/amlogic/g12a/g12a_pm.c new file mode 100644 index 000000000..c9fe3e977 --- /dev/null +++ b/plat/amlogic/g12a/g12a_pm.c @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "aml_private.h" + +#define SCPI_POWER_ON 0 +#define SCPI_POWER_RETENTION 1 +#define SCPI_POWER_OFF 3 + +#define SCPI_SYSTEM_SHUTDOWN 0 +#define SCPI_SYSTEM_REBOOT 1 + +static uintptr_t g12a_sec_entrypoint; +static volatile uint32_t g12a_cpu0_go; + +static void g12a_pm_set_reset_addr(u_register_t mpidr, uint64_t value) +{ + unsigned int core = plat_calc_core_pos(mpidr); + uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); + + mmio_write_64(cpu_mailbox_addr, value); +} + +static void g12a_pm_reset(u_register_t mpidr) +{ + unsigned int core = plat_calc_core_pos(mpidr); + uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8; + + mmio_write_32(cpu_mailbox_addr, 0); +} + +static void __dead2 g12a_system_reset(void) +{ + INFO("BL31: PSCI_SYSTEM_RESET\n"); + + u_register_t mpidr = read_mpidr_el1(); + uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3); + int ret; + + NOTICE("BL31: Reboot reason: 0x%x\n", status); + + status &= 0xFFFF0FF0; + + console_flush(); + + mmio_write_32(AML_AO_RTI_STATUS_REG3, status); + + ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT); + + if (ret != 0) { + ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret); + panic(); + } + + g12a_pm_reset(mpidr); + + wfi(); + + ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n"); + panic(); +} + +static void __dead2 g12a_system_off(void) +{ + INFO("BL31: PSCI_SYSTEM_OFF\n"); + + u_register_t mpidr = read_mpidr_el1(); + int ret; + + ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); + + if (ret != 0) { + ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret); + panic(); + } + + g12a_pm_set_reset_addr(mpidr, 0); + g12a_pm_reset(mpidr); + + wfi(); + + ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n"); + panic(); +} + +static int32_t g12a_pwr_domain_on(u_register_t mpidr) +{ + unsigned int core = plat_calc_core_pos(mpidr); + + /* CPU0 can't be turned OFF */ + if (core == AML_PRIMARY_CPU) { + VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); + + g12a_cpu0_go = 1; + flush_dcache_range((uintptr_t)&g12a_cpu0_go, + sizeof(g12a_cpu0_go)); + dsb(); + isb(); + + sev(); + + return PSCI_E_SUCCESS; + } + + g12a_pm_set_reset_addr(mpidr, g12a_sec_entrypoint); + aml_scpi_set_css_power_state(mpidr, + SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); + dmbsy(); + sev(); + + return PSCI_E_SUCCESS; +} + +static void g12a_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + unsigned int core = plat_calc_core_pos(read_mpidr_el1()); + + assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == + PLAT_LOCAL_STATE_OFF); + + if (core == AML_PRIMARY_CPU) { + g12a_cpu0_go = 0; + flush_dcache_range((uintptr_t)&g12a_cpu0_go, + sizeof(g12a_cpu0_go)); + dsb(); + isb(); + } + + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +static void g12a_pwr_domain_off(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int core = plat_calc_core_pos(mpidr); + + gicv2_cpuif_disable(); + + /* CPU0 can't be turned OFF */ + if (core == AML_PRIMARY_CPU) + return; + + aml_scpi_set_css_power_state(mpidr, + SCPI_POWER_OFF, SCPI_POWER_ON, + SCPI_POWER_ON); +} + +static void __dead2 g12a_pwr_domain_pwr_down_wfi(const psci_power_state_t + *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int core = plat_calc_core_pos(mpidr); + + /* CPU0 can't be turned OFF, emulate it with a WFE loop */ + if (core == AML_PRIMARY_CPU) { + VERBOSE("BL31: CPU0 entering wait loop...\n"); + + while (g12a_cpu0_go == 0) + wfe(); + + VERBOSE("BL31: CPU0 resumed.\n"); + + /* + * Because setting CPU0's warm reset entrypoint through PSCI + * mailbox and/or mmio mapped RVBAR (0xda834650) does not seem + * to work, jump to it manually. + * In order to avoid an assert, MMU has to be disabled. + */ + disable_mmu_el3(); + ((void(*)(void))g12a_sec_entrypoint)(); + } + + dsbsy(); + g12a_pm_set_reset_addr(mpidr, 0); + g12a_pm_reset(mpidr); + + for (;;) + wfi(); +} + +/******************************************************************************* + * Platform handlers and setup function. + ******************************************************************************/ +static const plat_psci_ops_t g12a_ops = { + .pwr_domain_on = g12a_pwr_domain_on, + .pwr_domain_on_finish = g12a_pwr_domain_on_finish, + .pwr_domain_off = g12a_pwr_domain_off, + .pwr_domain_pwr_down_wfi = g12a_pwr_domain_pwr_down_wfi, + .system_off = g12a_system_off, + .system_reset = g12a_system_reset +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + g12a_sec_entrypoint = sec_entrypoint; + *psci_ops = &g12a_ops; + g12a_cpu0_go = 0; + return 0; +} diff --git a/plat/amlogic/g12a/include/platform_def.h b/plat/amlogic/g12a/include/platform_def.h new file mode 100644 index 000000000..23d816dd4 --- /dev/null +++ b/plat/amlogic/g12a/include/platform_def.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include + +#include "../g12a_def.h" + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +#define PLATFORM_STACK_SIZE UL(0x1000) + +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT + +#define AML_PRIMARY_CPU U(0) + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET U(1) +/* Local power state for power-down. Valid for CPU and cluster power domains. */ +#define PLAT_LOCAL_STATE_OFF U(2) + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH U(4) +#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +/* Memory-related defines */ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) + +#define MAX_MMAP_REGIONS 16 +#define MAX_XLAT_TABLES 8 + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/amlogic/g12a/platform.mk b/plat/amlogic/g12a/platform.mk new file mode 100644 index 000000000..b0c91b063 --- /dev/null +++ b/plat/amlogic/g12a/platform.mk @@ -0,0 +1,91 @@ +# +# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include lib/xlat_tables_v2/xlat_tables.mk + +AML_PLAT := plat/amlogic +AML_PLAT_SOC := ${AML_PLAT}/${PLAT} +AML_PLAT_COMMON := ${AML_PLAT}/common + +DOIMAGEPATH ?= tools/amlogic +DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage + +PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ + -I${AML_PLAT_SOC}/include \ + -I${AML_PLAT_COMMON}/include + +GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c + +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + plat/common/plat_psci_common.c \ + drivers/amlogic/console/aarch64/meson_console.S \ + ${AML_PLAT_SOC}/${PLAT}_bl31_setup.c \ + ${AML_PLAT_SOC}/${PLAT}_pm.c \ + ${AML_PLAT_SOC}/${PLAT}_common.c \ + ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ + ${AML_PLAT_COMMON}/aml_efuse.c \ + ${AML_PLAT_COMMON}/aml_mhu.c \ + ${AML_PLAT_COMMON}/aml_scpi.c \ + ${AML_PLAT_COMMON}/aml_sip_svc.c \ + ${AML_PLAT_COMMON}/aml_thermal.c \ + ${AML_PLAT_COMMON}/aml_topology.c \ + ${AML_PLAT_COMMON}/aml_console.c \ + drivers/amlogic/crypto/sha_dma.c \ + ${XLAT_TABLES_LIB_SRCS} \ + ${GIC_SOURCES} + +# Tune compiler for Cortex-A53 +ifeq ($(notdir $(CC)),armclang) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else ifneq ($(findstring clang,$(notdir $(CC))),) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else + TF_CFLAGS_aarch64 += -mtune=cortex-a53 +endif + +# Build config flags +# ------------------ + +# Enable all errata workarounds for Cortex-A53 +ERRATA_A53_855873 := 1 +ERRATA_A53_819472 := 1 +ERRATA_A53_824069 := 1 +ERRATA_A53_827319 := 1 + +WORKAROUND_CVE_2017_5715 := 0 + +# Have different sections for code and rodata +SEPARATE_CODE_AND_RODATA := 1 + +# Use Coherent memory +USE_COHERENT_MEM := 1 + +# Verify build config +# ------------------- + +ifneq (${RESET_TO_BL31}, 0) + $(error Error: ${PLAT} needs RESET_TO_BL31=0) +endif + +ifeq (${ARCH},aarch32) + $(error Error: AArch32 not supported on ${PLAT}) +endif + +all: ${BUILD_PLAT}/bl31.img +distclean realclean clean: cleanimage + +cleanimage: + ${Q}${MAKE} -C ${DOIMAGEPATH} clean + +${DOIMAGETOOL}: + ${Q}${MAKE} -C ${DOIMAGEPATH} + +${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL} + ${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img + -- cgit v1.2.3 From c3e8b0be9bde36d220beea5d0452ecd04dcd94c6 Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Tue, 20 Aug 2019 15:22:44 +0100 Subject: AArch32: Disable Secure Cycle Counter This patch changes implementation for disabling Secure Cycle Counter. For ARMv8.5 the counter gets disabled by setting SDCR.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR.DP bit. In 'include\aarch32\arch.h' header file new ARMv8.5-PMU related definitions were added. Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8 Signed-off-by: Alexei Fedorov --- bl32/sp_min/aarch32/entrypoint.S | 20 +----------- include/arch/aarch32/arch.h | 5 +++ include/arch/aarch32/el3_common_macros.S | 30 ++++++++++++++++-- include/arch/aarch32/smccc_macros.S | 54 ++++++++++++++++++++++++++++---- lib/el3_runtime/aarch32/context_mgmt.c | 26 ++++++++++++--- 5 files changed, 104 insertions(+), 31 deletions(-) diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index 2ffef6a2e..0a684754c 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -183,15 +183,6 @@ func sp_min_handle_smc stcopr r0, SCR isb - /* - * Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode. - * Also, the PMCR.LC field has an architecturally UNKNOWN value on reset - * and so set to 1 as ARM has deprecated use of PMCR.LC=0. - */ - ldcopr r0, PMCR - orr r0, r0, #(PMCR_LC_BIT | PMCR_DP_BIT) - stcopr r0, PMCR - ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */ /* Check whether an SMC64 is issued */ tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT) @@ -236,15 +227,6 @@ func sp_min_handle_fiq stcopr r0, SCR isb - /* - * Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode. - * Also, the PMCR.LC field has an architecturally UNKNOWN value on reset - * and so set to 1 as ARM has deprecated use of PMCR.LC=0. - */ - ldcopr r0, PMCR - orr r0, r0, #(PMCR_LC_BIT | PMCR_DP_BIT) - stcopr r0, PMCR - push {r2, r3} bl sp_min_fiq pop {r0, r3} diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 34036d785..20175481f 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -162,6 +162,7 @@ #define SDCR_SPD_DISABLE U(0x2) #define SDCR_SPD_ENABLE U(0x3) #define SDCR_SCCD_BIT (U(1) << 23) +#define SDCR_SPME_BIT (U(1) << 17) #define SDCR_RESET_VAL U(0x0) /* HSCTLR definitions */ @@ -243,6 +244,8 @@ #define VTTBR_BADDR_SHIFT U(0) /* HDCR definitions */ +#define HDCR_HLP_BIT (U(1) << 26) +#define HDCR_HPME_BIT (U(1) << 7) #define HDCR_RESET_VAL U(0x0) /* HSTR definitions */ @@ -419,8 +422,10 @@ #define PMCR_N_SHIFT U(11) #define PMCR_N_MASK U(0x1f) #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) +#define PMCR_LP_BIT (U(1) << 7) #define PMCR_LC_BIT (U(1) << 6) #define PMCR_DP_BIT (U(1) << 5) +#define PMCR_RESET_VAL U(0x0) /******************************************************************************* * Definitions of register offsets, fields and macros for CPU system diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 0bd897814..c62d7d772 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -112,15 +112,41 @@ * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from * Secure EL1 are disabled. * - * SDCR: Set to one so that cycle counting by PMCCNTR is prohibited in - * Secure state. This bit is RES0 in versions of the architecture + * SDCR.SCCD: Set to one so that cycle counting by PMCCNTR is prohibited + * in Secure state. This bit is RES0 in versions of the architecture * earlier than ARMv8.5, setting it to 1 doesn't have any effect on * them. * --------------------------------------------------------------------- */ ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE) | SDCR_SCCD_BIT) stcopr r0, SDCR + + /* --------------------------------------------------------------------- + * Initialise PMCR, setting all fields rather than relying + * on hw. Some fields are architecturally UNKNOWN on reset. + * + * PMCR.LP: Set to one so that event counter overflow, that + * is recorded in PMOVSCLR[0-30], occurs on the increment + * that changes PMEVCNTR[63] from 1 to 0, when ARMv8.5-PMU + * is implemented. This bit is RES0 in versions of the architecture + * earlier than ARMv8.5, setting it to 1 doesn't have any effect + * on them. + * This bit is Reserved, UNK/SBZP in ARMv7. + * + * PMCR.LC: Set to one so that cycle counter overflow, that + * is recorded in PMOVSCLR[31], occurs on the increment + * that changes PMCCNTR[63] from 1 to 0. + * This bit is Reserved, UNK/SBZP in ARMv7. + * + * PMCR.DP: Set to one to prohibit cycle counting whilst in Secure mode. + * --------------------------------------------------------------------- + */ + ldr r0, =(PMCR_RESET_VAL | PMCR_DP_BIT | PMCR_LC_BIT | \ + PMCR_LP_BIT) +#else + ldr r0, =(PMCR_RESET_VAL | PMCR_DP_BIT) #endif + stcopr r0, PMCR /* * If Data Independent Timing (DIT) functionality is implemented, diff --git a/include/arch/aarch32/smccc_macros.S b/include/arch/aarch32/smccc_macros.S index 1fe6c64dc..4ec229218 100644 --- a/include/arch/aarch32/smccc_macros.S +++ b/include/arch/aarch32/smccc_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -58,7 +58,6 @@ stm r0!, {r2} stcopr r4, SCR - isb #else /* Save the banked registers including the current SPSR and LR */ mrs r4, sp_usr @@ -85,10 +84,34 @@ /* lr_mon is already saved by caller */ ldcopr r4, SCR + +#if ARM_ARCH_MAJOR > 7 + /* + * Check if earlier initialization of SDCR.SCCD to 1 + * failed, meaning that ARMv8-PMU is not implemented, + * cycle counting is not disabled and PMCR should be + * saved in Non-secure context. + */ + ldcopr r5, SDCR + tst r5, #SDCR_SCCD_BIT + bne 1f +#endif + /* Secure Cycle Counter is not disabled */ #endif - str r4, [sp, #SMC_CTX_SCR] - ldcopr r4, PMCR - str r4, [sp, #SMC_CTX_PMCR] + ldcopr r5, PMCR + + /* Check caller's security state */ + tst r4, #SCR_NS_BIT + beq 2f + + /* Save PMCR if called from Non-secure state */ + str r5, [sp, #SMC_CTX_PMCR] + + /* Disable cycle counter when event counting is prohibited */ +2: orr r5, r5, #PMCR_DP_BIT + stcopr r5, PMCR + isb +1: str r4, [sp, #SMC_CTX_SCR] .endm /* @@ -113,12 +136,31 @@ stcopr r1, SCR isb + /* + * Restore PMCR when returning to Non-secure state + */ + tst r1, #SCR_NS_BIT + beq 2f + + /* + * Back to Non-secure state + */ +#if ARM_ARCH_MAJOR > 7 + /* + * Check if earlier initialization SDCR.SCCD to 1 + * failed, meaning that ARMv8-PMU is not implemented and + * PMCR should be restored from Non-secure context. + */ + ldcopr r1, SDCR + tst r1, #SDCR_SCCD_BIT + bne 2f +#endif /* * Restore the PMCR register. */ ldr r1, [r0, #SMC_CTX_PMCR] stcopr r1, PMCR - +2: /* Restore the banked registers including the current SPSR */ add r1, r0, #SMC_CTX_SP_USR diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c index a4702fcc6..73d1e354d 100644 --- a/lib/el3_runtime/aarch32/context_mgmt.c +++ b/lib/el3_runtime/aarch32/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -281,10 +281,28 @@ void cm_prepare_el3_exit(uint32_t security_state) * * HDCR.HPMN: Set to value of PMCR.N which is the * architecturally-defined reset value. + * + * HDCR.HLP: Set to one so that event counter + * overflow, that is recorded in PMOVSCLR[0-30], + * occurs on the increment that changes + * PMEVCNTR[63] from 1 to 0, when ARMv8.5-PMU is + * implemented. This bit is RES0 in versions of the + * architecture earlier than ARMv8.5, setting it to 1 + * doesn't have any effect on them. + * This bit is Reserved, UNK/SBZP in ARMv7. + * + * HDCR.HPME: Set to zero to disable EL2 Event + * counters. */ - write_hdcr(HDCR_RESET_VAL | - ((read_pmcr() & PMCR_N_BITS) >> PMCR_N_SHIFT)); - +#if (ARM_ARCH_MAJOR > 7) + write_hdcr((HDCR_RESET_VAL | HDCR_HLP_BIT | + ((read_pmcr() & PMCR_N_BITS) >> + PMCR_N_SHIFT)) & ~HDCR_HPME_BIT); +#else + write_hdcr((HDCR_RESET_VAL | + ((read_pmcr() & PMCR_N_BITS) >> + PMCR_N_SHIFT)) & ~HDCR_HPME_BIT); +#endif /* * Set HSTR to its architectural reset value so that * access to system registers in the cproc=1111 -- cgit v1.2.3 From a4668c36f1fca75bce99cb706ba7c27e0c16454d Mon Sep 17 00:00:00 2001 From: Artsem Artsemenka Date: Mon, 16 Sep 2019 15:11:21 +0100 Subject: Cortex_hercules: Add support for Hercules-AE Not tested on FVP Model. Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9 Signed-off-by: Artsem Artsemenka --- include/lib/cpus/aarch64/cortex_hercules_ae.h | 14 ++++ lib/cpus/aarch64/cortex_hercules_ae.S | 100 ++++++++++++++++++++++++++ plat/arm/board/fvp/platform.mk | 3 +- 3 files changed, 116 insertions(+), 1 deletion(-) create mode 100644 include/lib/cpus/aarch64/cortex_hercules_ae.h create mode 100644 lib/cpus/aarch64/cortex_hercules_ae.S diff --git a/include/lib/cpus/aarch64/cortex_hercules_ae.h b/include/lib/cpus/aarch64/cortex_hercules_ae.h new file mode 100644 index 000000000..795563bc3 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_hercules_ae.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_HERCULES_AE_H +#define CORTEX_HERCULES_AE_H + +#include + +#define CORTEX_HERCULES_AE_MIDR U(0x410FD420) + +#endif /* CORTEX_HERCULES_AE_H */ diff --git a/lib/cpus/aarch64/cortex_hercules_ae.S b/lib/cpus/aarch64/cortex_hercules_ae.S new file mode 100644 index 000000000..c4a216353 --- /dev/null +++ b/lib/cpus/aarch64/cortex_hercules_ae.S @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "cortex_hercules_ae must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-Hercules-AE + * ------------------------------------------------- + */ +#if ENABLE_AMU +func cortex_hercules_ae_reset_func + /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ + mrs x0, actlr_el3 + bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT + msr actlr_el3, x0 + + /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ + mrs x0, actlr_el2 + bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT + msr actlr_el2, x0 + + /* Enable group0 counters */ + mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK + msr CPUAMCNTENSET0_EL0, x0 + + /* Enable group1 counters */ + mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK + msr CPUAMCNTENSET1_EL0, x0 + isb + + ret +endfunc cortex_hercules_ae_reset_func +#endif + + /* ------------------------------------------------------- + * HW will do the cache maintenance while powering down + * ------------------------------------------------------- + */ +func cortex_hercules_ae_core_pwr_dwn + /* ------------------------------------------------------- + * Enable CPU power down bit in power control register + * ------------------------------------------------------- + */ + mrs x0, CORTEX_HERCULES_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT + msr CORTEX_HERCULES_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_hercules_ae_core_pwr_dwn + + /* + * Errata printing function for cortex_hercules_ae. Must follow AAPCS. + */ +#if REPORT_ERRATA +func cortex_hercules_ae_errata_report + ret +endfunc cortex_hercules_ae_errata_report +#endif + + /* ------------------------------------------------------- + * This function provides cortex_hercules_ae specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * ------------------------------------------------------- + */ +.section .rodata.cortex_hercules_ae_regs, "aS" +cortex_hercules_ae_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_hercules_ae_cpu_reg_dump + adr x6, cortex_hercules_ae_regs + mrs x8, CORTEX_HERCULES_CPUECTLR_EL1 + ret +endfunc cortex_hercules_ae_cpu_reg_dump + +#if ENABLE_AMU +#define HERCULES_AE_RESET_FUNC cortex_hercules_ae_reset_func +#else +#define HERCULES_AE_RESET_FUNC CPU_NO_RESET_FUNC +#endif + +declare_cpu_ops cortex_hercules_ae, CORTEX_HERCULES_AE_MIDR, \ + HERCULES_AE_RESET_FUNC, \ + cortex_hercules_ae_core_pwr_dwn diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 1e7cfce5e..2bba6bd09 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -115,7 +115,8 @@ else lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/neoverse_e1.S \ lib/cpus/aarch64/neoverse_zeus.S \ - lib/cpus/aarch64/cortex_hercules.S + lib/cpus/aarch64/cortex_hercules.S \ + lib/cpus/aarch64/cortex_hercules_ae.S endif # AArch64/AArch32 cores FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ -- cgit v1.2.3 From 35010bb80390bca016110cced25b41ad2b355919 Mon Sep 17 00:00:00 2001 From: zelalem-aweke Date: Fri, 20 Sep 2019 11:15:20 -0500 Subject: doc: Migrate to Linaro release 19.06 - Updated Linaro release version number to 19.06 - Updated links to Linaro instructions and releases - Removed the Linaro old releases link Signed-off-by: zelalem-aweke Change-Id: Ib786728106961e89182b42183e7b889f6fc74190 --- docs/getting_started/user-guide.rst | 37 +++++++++++++++++-------------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 44bfb7a33..9c1c3a2e8 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -9,7 +9,7 @@ is outside the scope of this document. This document assumes that the reader has previous experience running a fully bootable Linux software stack on Juno or FVP using the prebuilt binaries and -filesystems provided by `Linaro`_. Further information may be found in the +filesystems provided by Linaro. Further information may be found in the `Linaro instructions`_. It also assumes that the user understands the role of the different software components required to boot a Linux system: @@ -48,15 +48,10 @@ Install the required packages to build TF-A with the following command: sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev -TF-A has been tested with Linaro Release 18.04. - Download and install the AArch32 (arm-eabi) or AArch64 little-endian (aarch64-linux-gnu) GCC cross compiler. If you would like to use the latest features available, download GCC 8.3-2019.03 compiler from -`arm Developer page`_. Otherwise, the `Linaro Release Notes`_ documents which -version of the compiler to use for a given Linaro Release. Also, these -`Linaro instructions`_ provide further guidance and a script, which can be used -to download Linaro deliverables automatically. +`Arm Developer page`_. Optionally, TF-A can be built using clang version 4.0 or newer or Arm Compiler 6. See instructions below on how to switch the default compiler. @@ -73,6 +68,10 @@ In addition, the following optional packages and tools may be needed: This tool can be found in most Linux distributions. Inkscape is needed to generate the actual \*.png files. +TF-A has been tested with pre-built binaries and file systems from +`Linaro Release 19.06`_. Alternatively, you can build the binaries from +source using instructions provided at the `Arm Platforms User guide`_. + Getting the TF-A source code ---------------------------- @@ -127,7 +126,7 @@ Building TF-A ------------- - Before building TF-A, the environment variable ``CROSS_COMPILE`` must point - to the Linaro cross compiler. + to the cross compiler. For AArch64: @@ -1401,7 +1400,7 @@ a single FIP binary. It assumes that a `Linaro Release`_ has been installed. separately for AArch32. - Before building BL32, the environment variable ``CROSS_COMPILE`` must point - to the AArch32 Linaro cross compiler. + to the AArch32 cross compiler. .. code:: shell @@ -1422,7 +1421,7 @@ a single FIP binary. It assumes that a `Linaro Release`_ has been installed. make realclean - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE`` - must point to the AArch64 Linaro cross compiler. + must point to the AArch64 cross compiler. .. code:: shell @@ -2154,11 +2153,9 @@ Running the software on Juno This version of TF-A has been tested on variants r0, r1 and r2 of Juno. -To execute the software stack on Juno, the version of the Juno board recovery -image indicated in the `Linaro Release Notes`_ must be installed. If you have an -earlier version installed or are unsure which version is installed, please -re-install the recovery image by following the -`Instructions for using Linaro's deliverables on Juno`_. +To execute the software stack on Juno, installing the latest Arm Platforms +software deliverables is recommended. Please install the deliverables by +following the `Instructions for using Linaro's deliverables on Juno`_. Preparing TF-A images ~~~~~~~~~~~~~~~~~~~~~ @@ -2193,11 +2190,11 @@ wakeup interrupt from RTC. *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* -.. _arm Developer page: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads -.. _Linaro: `Linaro Release Notes`_ -.. _Linaro Release: `Linaro Release Notes`_ -.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes -.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables +.. _Arm Developer page: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads +.. _Linaro Release: http://releases.linaro.org/members/arm/platforms +.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 +.. _Linaro instructions: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about +.. _Arm Platforms User guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/user-guide.rst .. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno .. _Arm Platforms Portal: https://community.arm.com/dev-platforms/ .. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio -- cgit v1.2.3 From 558a6f444d54f419e90ead976bf28cf25797f4e4 Mon Sep 17 00:00:00 2001 From: Radoslaw Biernacki Date: Thu, 17 May 2018 22:52:49 +0200 Subject: qemu/qemu_sbsa: Adding Qemu SBSA platform This patch introduces Qemu SBSA platform. Both platform specific files where copied from qemu/qemu with changes for DRAM base above 32bit and removal of ARMv7 conditional defines/code. Documentation is aligned to rest of SBSA patches along the series and planed changes in edk2-platform repo. Fixes ARM-software/tf-issues#602 Signed-off-by: Radoslaw Biernacki Change-Id: I8ebc34eedb2268365e479ef05654b2df1b99128c --- docs/plat/qemu_sbsa.rst | 48 ++++++ plat/qemu/qemu_sbsa/include/platform_def.h | 243 +++++++++++++++++++++++++++++ plat/qemu/qemu_sbsa/platform.mk | 101 ++++++++++++ 3 files changed, 392 insertions(+) create mode 100644 docs/plat/qemu_sbsa.rst create mode 100644 plat/qemu/qemu_sbsa/include/platform_def.h create mode 100644 plat/qemu/qemu_sbsa/platform.mk diff --git a/docs/plat/qemu_sbsa.rst b/docs/plat/qemu_sbsa.rst new file mode 100644 index 000000000..e04a63c77 --- /dev/null +++ b/docs/plat/qemu_sbsa.rst @@ -0,0 +1,48 @@ +Trusted Firmware-A for QEMU SBSA target +======================================== + +Trusted Firmware-A (TF-A) implements the EL3 firmware layer for QEMU SBSA +Armv8-A. While running Qemu from command line, we need to supply two Flash +images. First Secure BootRom is supplied by -pflash argument. This Flash image +is made by EDK2 build system by composing BL1 and FIP. Second parameter for Qemu +is responsible for Non-secure rom which also given with -pflash argument and +contains of UEFI and EFI variables (also made by EDK2 build system). Semihosting +is not used + +When QEMU starts all CPUs are released simultaneously, BL1 selects a +primary CPU to handle the boot and the secondaries are placed in a polling +loop to be released by normal world via PSCI. + +BL2 edits the FDT, generated by QEMU at run-time to add a node describing PSCI +and also enable methods for the CPUs. + +Current limitations: + +- Only cold boot is supported +- No instructions for how to load a BL32 (Secure Payload) + +To build TF-A: + +:: + + git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa + cd tfa + export CROSS_COMPILE=aarch64-linux-gnu- + make PLAT=qemu_sbsa all fip + +Images will be placed at build/qemu_sbsa/release (bl1.bin and fip.bin). +Need to copy them into top directory for EDK2 compilation. + +:: + + cp build/qemu_sbsa/release/bl1.bin ../ + cp build/qemu_sbsa/release/fip.bin ../ + +Those images cannot be used by itself (no semihosing support). Flash images are built by +EDK2 build system, refer to edk2-platform repo for full build instructions. + +:: + + git clone https://github.com/tianocore/edk2-platforms.git + Platform/Qemu/SbsaQemu/Readme.md + diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h new file mode 100644 index 000000000..c57a5e857 --- /dev/null +++ b/plat/qemu/qemu_sbsa/include/platform_def.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include +#include + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define PLATFORM_STACK_SIZE 0x1000 + +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ + PLATFORM_CLUSTER1_CORE_COUNT) + +#define QEMU_PRIMARY_CPU 0 + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 + +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 2 + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN 0 +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET 1 +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF 2 + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH 4 +#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/* + * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", + * and secure DRAM. + */ +#define SEC_ROM_BASE 0x00000000 +#define SEC_ROM_SIZE 0x00020000 + +#define NS_DRAM0_BASE 0x10000000000ULL +#define NS_DRAM0_SIZE 0x00020000000 + +#define SEC_SRAM_BASE 0x20000000 +#define SEC_SRAM_SIZE 0x20000000 + +/* + * RAD just placeholders, need to be chosen after finalizing mem map + */ +#define SEC_DRAM_BASE 0x1000 +#define SEC_DRAM_SIZE 0x1000 + +/* Load pageable part of OP-TEE 2MB above secure DRAM base */ +#define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) +#define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 + +/* + * ARM-TF lives in SRAM, partition it here + */ + +#define SHARED_RAM_BASE SEC_SRAM_BASE +#define SHARED_RAM_SIZE 0x00001000 + +#define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE +#define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) +#define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) +#define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ + PLAT_QEMU_HOLD_ENTRY_SIZE) +#define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 +#define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) +#define PLAT_QEMU_HOLD_STATE_WAIT 0 +#define PLAT_QEMU_HOLD_STATE_GO 1 + +#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) +#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) + +/* + * BL1 specific defines. + * + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using + * the current BL1 RW debug size plus a little space for growth. + */ +#define BL1_RO_BASE SEC_ROM_BASE +#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) +#define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) +#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) + +/* + * BL2 specific defines. + * + * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug + * size plus a little space for growth. + */ +#define BL2_BASE (BL31_BASE - 0x1D000) +#define BL2_LIMIT BL31_BASE + +/* + * BL3-1 specific defines. + * + * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the + * current BL3-1 debug size plus a little space for growth. + */ +#define BL31_BASE (BL31_LIMIT - 0x20000) +#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) +#define BL31_PROGBITS_LIMIT BL1_RW_BASE + + +/* + * BL3-2 specific defines. + * + * BL3-2 can execute from Secure SRAM, or Secure DRAM. + */ +#define BL32_SRAM_BASE BL_RAM_BASE +#define BL32_SRAM_LIMIT BL31_BASE +#define BL32_DRAM_BASE SEC_DRAM_BASE +#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE) + +#define BL32_MEM_BASE BL_RAM_BASE +#define BL32_MEM_SIZE BL_RAM_SIZE +#define BL32_BASE BL32_SRAM_BASE +#define BL32_LIMIT BL32_SRAM_LIMIT + +#define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) +#define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 42) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 42) +#define MAX_MMAP_REGIONS 11 +#define MAX_XLAT_TABLES 10 +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/* + * PL011 related constants + */ +#define UART0_BASE 0x60000000 +#define UART1_BASE 0x60030000 +#define UART0_CLK_IN_HZ 1 +#define UART1_CLK_IN_HZ 1 + +#define PLAT_QEMU_BOOT_UART_BASE UART0_BASE +#define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ + +#define PLAT_QEMU_CRASH_UART_BASE UART1_BASE +#define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ + +#define PLAT_QEMU_CONSOLE_BAUDRATE 115200 + +#define QEMU_FLASH0_BASE 0x00000000 +#define QEMU_FLASH0_SIZE 0x10000000 +#define QEMU_FLASH1_BASE 0x10000000 +#define QEMU_FLASH1_SIZE 0x10000000 + +#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE +#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE + +/* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */ +#define DEVICE0_BASE 0x40000000 +#define DEVICE0_SIZE 0x04080000 +/* This is map from NORMAL_UART up to SECURE_UART_MM */ +#define DEVICE1_BASE 0x60000000 +#define DEVICE1_SIZE 0x00041000 + +/* + * GIC related constants + * We use GICv3 where CPU Interface registers are not memory mapped + */ +#define GICD_BASE 0x40060000 +#define GICR_BASE 0x40080000 +#define GICC_BASE 0x0 + +#define QEMU_IRQ_SEC_SGI_0 8 +#define QEMU_IRQ_SEC_SGI_1 9 +#define QEMU_IRQ_SEC_SGI_2 10 +#define QEMU_IRQ_SEC_SGI_3 11 +#define QEMU_IRQ_SEC_SGI_4 12 +#define QEMU_IRQ_SEC_SGI_5 13 +#define QEMU_IRQ_SEC_SGI_6 14 +#define QEMU_IRQ_SEC_SGI_7 15 + +/****************************************************************************** + * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 + * interrupts. + *****************************************************************************/ +#define PLATFORM_G1S_PROPS(grp) \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE) + +#define PLATFORM_G0_PROPS(grp) + +/* + * DT related constants + */ +#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE +#define PLAT_QEMU_DT_MAX_SIZE 0x10000 + +/* + * System counter + */ +#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16) + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk new file mode 100644 index 000000000..0d6047da1 --- /dev/null +++ b/plat/qemu/qemu_sbsa/platform.mk @@ -0,0 +1,101 @@ +# +# Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +CRASH_REPORTING := 1 + +include lib/libfdt/libfdt.mk + +# Enable new version of image loading on QEMU platforms +LOAD_IMAGE_V2 := 1 + +ifeq ($(NEED_BL32),yes) +$(eval $(call add_define,QEMU_LOAD_BL32)) +endif + +PLAT_QEMU_PATH := plat/qemu/qemu_sbsa +PLAT_QEMU_COMMON_PATH := plat/qemu/common +PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ + -I${PLAT_QEMU_COMMON_PATH}/include \ + -I${PLAT_QEMU_PATH}/include \ + -Iinclude/common/tbbr + +PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH} + +PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \ + drivers/arm/pl011/${ARCH}/pl011_console.S + +include lib/xlat_tables_v2/xlat_tables.mk +PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} + +BL1_SOURCES += drivers/io/io_semihosting.c \ + drivers/io/io_storage.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + lib/semihosting/semihosting.c \ + lib/semihosting/${ARCH}/semihosting_call.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ + ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c + +BL1_SOURCES += lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S + +BL2_SOURCES += drivers/io/io_semihosting.c \ + drivers/io/io_storage.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + lib/semihosting/semihosting.c \ + lib/semihosting/${ARCH}/semihosting_call.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ + ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \ + common/fdt_fixup.c \ + $(LIBFDT_SRCS) +ifeq (${LOAD_IMAGE_V2},1) +BL2_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \ + common/desc_image_load.c +endif + +QEMU_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \ + drivers/arm/gic/v3/gicv3_main.c \ + drivers/arm/gic/common/gic_common.c \ + plat/common/plat_gicv3.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c + +BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + plat/common/plat_psci_common.c \ + ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \ + ${PLAT_QEMU_COMMON_PATH}/topology.c \ + ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \ + ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \ + ${QEMU_GIC_SOURCES} + +SEPARATE_CODE_AND_RODATA := 1 +ENABLE_STACK_PROTECTOR := 0 +ifneq ($(ENABLE_STACK_PROTECTOR), 0) + PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c +endif + +MULTI_CONSOLE_API := 1 + +# Disable the PSCI platform compatibility layer +ENABLE_PLAT_COMPAT := 0 + +# Use known base for UEFI if not given from command line +# By default BL33 is at FLASH1 base +PRELOADED_BL33_BASE ?= 0x10000000 + +# Qemu SBSA plafrom only support SEC_SRAM +BL32_RAM_LOCATION_ID = SEC_SRAM_ID +$(eval $(call add_define,BL32_RAM_LOCATION_ID)) + +# Do not enable SVE +ENABLE_SVE_FOR_NS := 0 -- cgit v1.2.3 From fa405e3b82ae9ed764e6f37745e612c86a8be183 Mon Sep 17 00:00:00 2001 From: Radoslaw Biernacki Date: Thu, 7 Jun 2018 20:14:36 +0200 Subject: qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1 This patch adds mapping for secure FLASH0 for qemu/virt and qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both platforms share common code, changes in common defines was necessary. For qemu_sbsa, this patch adds necessary mapping in order to boot without semi-hosting from secure FLASH0. EFI need to stay in FLASH1 (share it with variables) since it need to "run in place" in non secure domain. Changes for this are under RFC at edk2-platforms mailing list: https://patches.linaro.org/patch/171327/ (edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc). In docs qemu/virt is described as using semi-hosting, therefore this change should be orthogonal to existing assumptions while giving possibility to store both bl1 and fip in FLASH0 at some point (additional changes required for that). Signed-off-by: Radoslaw Biernacki Change-Id: I782bc3637c91c01eaee680b3c5c408e24b4b6e28 --- plat/qemu/common/qemu_common.c | 7 ++++++- plat/qemu/qemu/include/platform_def.h | 10 ++++++---- plat/qemu/qemu_sbsa/include/platform_def.h | 4 ++-- 3 files changed, 14 insertions(+), 7 deletions(-) diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c index 56bf9532f..365cfb7f0 100644 --- a/plat/qemu/common/qemu_common.c +++ b/plat/qemu/common/qemu_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,6 +41,9 @@ #define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \ MT_MEMORY | MT_RO | MT_SECURE) +#define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \ + MT_MEMORY | MT_RO | MT_SECURE) + /* * Table of regions for various BL stages to map using the MMU. * This doesn't include TZRAM as the 'mem_layout' argument passed to @@ -49,6 +52,7 @@ #ifdef IMAGE_BL1 static const mmap_region_t plat_qemu_mmap[] = { MAP_FLASH0, + MAP_FLASH1, MAP_SHARED_RAM, MAP_DEVICE0, #ifdef MAP_DEVICE1 @@ -63,6 +67,7 @@ static const mmap_region_t plat_qemu_mmap[] = { #ifdef IMAGE_BL2 static const mmap_region_t plat_qemu_mmap[] = { MAP_FLASH0, + MAP_FLASH1, MAP_SHARED_RAM, MAP_DEVICE0, #ifdef MAP_DEVICE1 diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h index a90573712..c6b4db506 100644 --- a/plat/qemu/qemu/include/platform_def.h +++ b/plat/qemu/qemu/include/platform_def.h @@ -170,7 +170,7 @@ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) -#define MAX_MMAP_REGIONS 10 +#define MAX_MMAP_REGIONS 11 #define MAX_XLAT_TABLES 6 #define MAX_IO_DEVICES 3 #define MAX_IO_HANDLES 4 @@ -191,11 +191,13 @@ #define PLAT_QEMU_CONSOLE_BAUDRATE 115200 -#define QEMU_FLASH0_BASE 0x04000000 +#define QEMU_FLASH0_BASE 0x00000000 #define QEMU_FLASH0_SIZE 0x04000000 +#define QEMU_FLASH1_BASE 0x04000000 +#define QEMU_FLASH1_SIZE 0x04000000 -#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE -#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE +#define PLAT_QEMU_FIP_BASE QEMU_FLASH1_BASE +#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH1_SIZE #define DEVICE0_BASE 0x08000000 #define DEVICE0_SIZE 0x01000000 diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h index c57a5e857..333b21cc1 100644 --- a/plat/qemu/qemu_sbsa/include/platform_def.h +++ b/plat/qemu/qemu_sbsa/include/platform_def.h @@ -178,8 +178,8 @@ #define QEMU_FLASH1_BASE 0x10000000 #define QEMU_FLASH1_SIZE 0x10000000 -#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE -#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE +#define PLAT_QEMU_FIP_BASE 0x00008000 +#define PLAT_QEMU_FIP_MAX_SIZE 0x00020000 /* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */ #define DEVICE0_BASE 0x40000000 -- cgit v1.2.3 From b48691eda0f414654f94d871febd1035add1d22f Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Thu, 26 Sep 2019 11:29:21 +0100 Subject: doc: Fix GCC version to 8.3-2019.03 Change-Id: I3b866e927d93f4b690aa4891940fc8afabf4146e Signed-off-by: Louis Mayencourt --- docs/getting_started/user-guide.rst | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 9c1c3a2e8..6dad31058 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -49,9 +49,7 @@ Install the required packages to build TF-A with the following command: sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev Download and install the AArch32 (arm-eabi) or AArch64 little-endian -(aarch64-linux-gnu) GCC cross compiler. If you would like to use the latest -features available, download GCC 8.3-2019.03 compiler from -`Arm Developer page`_. +(aarch64-linux-gnu) GCC 8.3-2019.03 cross compiler from `Arm Developer page`_. Optionally, TF-A can be built using clang version 4.0 or newer or Arm Compiler 6. See instructions below on how to switch the default compiler. -- cgit v1.2.3 From 0a12302c3ff290fd5925313d7ba834209eeed671 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Mon, 27 May 2019 09:32:00 +0200 Subject: Add missing support for BL2_AT_EL3 in XIP memory Add the missing flag for aarch32 XIP memory mode. It was previously added in aarch64 only. Minor: Correct the aarch64 missing flag. Signed-off-by: Lionel Debieve Change-Id: Iac0a7581a1fd580aececa75f97deb894858f776f --- include/arch/aarch32/el3_common_macros.S | 2 +- include/arch/aarch64/el3_common_macros.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index c62d7d772..7559de446 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -339,7 +339,7 @@ bl zeromem #endif -#ifdef IMAGE_BL1 +#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) /* ----------------------------------------------------- * Copy data from ROM to RAM. * ----------------------------------------------------- diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 53396d44b..ee20d5b2d 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -366,7 +366,7 @@ bl zeromem #endif -#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM) +#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) adrp x0, __DATA_RAM_START__ add x0, x0, :lo12:__DATA_RAM_START__ adrp x1, __DATA_ROM_START__ -- cgit v1.2.3 From 6ad216dca5e388f9aa1518a20a81c836c7eb2d21 Mon Sep 17 00:00:00 2001 From: Imre Kis Date: Thu, 18 Jul 2019 14:30:03 +0200 Subject: Introducing support for Cortex-A65 Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47 Signed-off-by: Imre Kis --- include/lib/cpus/aarch64/cortex_a65.h | 31 ++++++++++++++ lib/cpus/aarch64/cortex_a65.S | 81 +++++++++++++++++++++++++++++++++++ plat/arm/board/fvp/platform.mk | 3 +- 3 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 include/lib/cpus/aarch64/cortex_a65.h create mode 100644 lib/cpus/aarch64/cortex_a65.S diff --git a/include/lib/cpus/aarch64/cortex_a65.h b/include/lib/cpus/aarch64/cortex_a65.h new file mode 100644 index 000000000..0df34c9ce --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a65.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A65_H +#define CORTEX_A65_H + +#include + +#define CORTEX_A65_MIDR U(0x410FD060) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ + +#define CORTEX_A65_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A65_H */ diff --git a/lib/cpus/aarch64/cortex_a65.S b/lib/cpus/aarch64/cortex_a65.S new file mode 100644 index 000000000..666324c1e --- /dev/null +++ b/lib/cpus/aarch64/cortex_a65.S @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if !HW_ASSISTED_COHERENCY +#error "Cortex-A65 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS +#error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +/* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A65. + * Shall clobber: x0-x19 + * ------------------------------------------------- + */ +func cortex_a65_reset_func + mov x19, x30 + +#if ERRATA_DSU_936184 + bl errata_dsu_936184_wa +#endif + + ret x19 +endfunc cortex_a65_reset_func + +func cortex_a65_cpu_pwr_dwn + mrs x0, CORTEX_A65_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_A65_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_a65_cpu_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex-A65. Must follow AAPCS. + */ +func cortex_a65_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_DSU_936184, cortex_a65, dsu_936184 + + ldp x8, x30, [sp], #16 + ret +endfunc cortex_a65_errata_report +#endif + +.section .rodata.cortex_a65_regs, "aS" +cortex_a65_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a65_cpu_reg_dump + adr x6, cortex_a65_regs + mrs x8, CORTEX_A65_ECTLR_EL1 + ret +endfunc cortex_a65_cpu_reg_dump + +declare_cpu_ops cortex_a65, CORTEX_A65_MIDR, \ + cortex_a65_reset_func, \ + cortex_a65_cpu_pwr_dwn diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 2bba6bd09..c8e2169c3 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -116,7 +116,8 @@ else lib/cpus/aarch64/neoverse_e1.S \ lib/cpus/aarch64/neoverse_zeus.S \ lib/cpus/aarch64/cortex_hercules.S \ - lib/cpus/aarch64/cortex_hercules_ae.S + lib/cpus/aarch64/cortex_hercules_ae.S \ + lib/cpus/aarch64/cortex_a65.S endif # AArch64/AArch32 cores FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ -- cgit v1.2.3 From 1b0174efdb9f7f2a998864a015b16980a19e7803 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Fri, 23 Aug 2019 10:23:34 +0800 Subject: mediatek: mt8183: add DEVAPC driver to control protection Add DEVAPC driver to control protection. Signed-off-by: kenny liang Change-Id: I6a6dd1c0bffa372b6df2cb604ca5e02eabbb9d26 --- plat/mediatek/mt8183/bl31_plat_setup.c | 3 + plat/mediatek/mt8183/drivers/devapc/devapc.c | 231 +++++++++++++ plat/mediatek/mt8183/drivers/devapc/devapc.h | 499 +++++++++++++++++++++++++++ plat/mediatek/mt8183/platform.mk | 2 + 4 files changed, 735 insertions(+) create mode 100644 plat/mediatek/mt8183/drivers/devapc/devapc.c create mode 100644 plat/mediatek/mt8183/drivers/devapc/devapc.h diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c index ec387f4d6..75694964d 100644 --- a/plat/mediatek/mt8183/bl31_plat_setup.c +++ b/plat/mediatek/mt8183/bl31_plat_setup.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -135,6 +136,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, ******************************************************************************/ void bl31_platform_setup(void) { + devapc_init(); + platform_setup_cpu(); generic_delay_timer_init(); diff --git a/plat/mediatek/mt8183/drivers/devapc/devapc.c b/plat/mediatek/mt8183/drivers/devapc/devapc.c new file mode 100644 index 000000000..9d76aa547 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/devapc/devapc.c @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +static void set_master_transaction(uint32_t master_index, + enum TRANSACTION transaction_type) +{ + uintptr_t base; + uint32_t master_register_index; + uint32_t master_set_index; + uint32_t set_bit; + + master_register_index = master_index / (MOD_NO_IN_1_DEVAPC * 2); + master_set_index = master_index % (MOD_NO_IN_1_DEVAPC * 2); + + base = DEVAPC_INFRA_MAS_SEC_0 + master_register_index * 4; + + set_bit = 0x1 << master_set_index; + if (transaction_type == SECURE_TRANSACTION) + mmio_setbits_32(base, set_bit); + else + mmio_clrbits_32(base, set_bit); +} + +static void set_master_domain(uint32_t master_index, enum MASK_DOM domain) +{ + uintptr_t base; + uint32_t domain_reg; + uint32_t domain_index; + uint32_t clr_bit; + uint32_t set_bit; + + domain_reg = master_index / MASTER_MOD_NO_IN_1_DEVAPC; + domain_index = master_index % MASTER_MOD_NO_IN_1_DEVAPC; + clr_bit = 0xF << (4 * domain_index); + set_bit = domain << (4 * domain_index); + + base = DEVAPC_INFRA_MAS_DOM_0 + domain_reg * 4; + mmio_clrsetbits_32(base, clr_bit, set_bit); +} + +static void set_master_domain_remap_infra(enum MASK_DOM domain_emi_view, + enum MASK_DOM domain_infra_view) +{ + uintptr_t base; + uint32_t clr_bit; + uint32_t set_bit; + + if (domain_emi_view < DOMAIN_10) { + base = DEVAPC_INFRA_DOM_RMP_0; + clr_bit = 0x7 << (domain_emi_view * 3); + set_bit = domain_infra_view << (domain_emi_view * 3); + mmio_clrsetbits_32(base, clr_bit, set_bit); + } else if (domain_emi_view > DOMAIN_10) { + base = DEVAPC_INFRA_DOM_RMP_1; + domain_emi_view = domain_emi_view - DOMAIN_11; + clr_bit = 0x7 << (domain_emi_view * 3 + 1); + set_bit = domain_infra_view << (domain_emi_view * 3 + 1); + mmio_clrsetbits_32(base, clr_bit, set_bit); + } else { + base = DEVAPC_INFRA_DOM_RMP_0; + clr_bit = 0x3 << (domain_emi_view * 3); + set_bit = domain_infra_view << (domain_emi_view * 3); + mmio_clrsetbits_32(base, clr_bit, set_bit); + + base = DEVAPC_INFRA_DOM_RMP_1; + set_bit = (domain_infra_view & 0x4) >> 2; + mmio_clrsetbits_32(base, 0x1, set_bit); + } +} + +static void set_master_domain_remap_mm(enum MASK_DOM domain_emi_view, + enum MASK_DOM domain_mm_view) +{ + uintptr_t base; + uint32_t clr_bit; + uint32_t set_bit; + + base = DEVAPC_MM_DOM_RMP_0; + clr_bit = 0x3 << (domain_emi_view * 2); + set_bit = domain_mm_view << (domain_emi_view * 2); + + mmio_clrsetbits_32(base, clr_bit, set_bit); +} + +static void set_module_apc(enum DAPC_SLAVE_TYPE slave_type, uint32_t module, + enum MASK_DOM domain_num, + enum APC_ATTR permission_control) +{ + uintptr_t base; + uint32_t apc_index; + uint32_t apc_set_index; + uint32_t clr_bit; + uint32_t set_bit; + + apc_index = module / MOD_NO_IN_1_DEVAPC; + apc_set_index = module % MOD_NO_IN_1_DEVAPC; + clr_bit = 0x3 << (apc_set_index * 2); + set_bit = permission_control << (apc_set_index * 2); + + if (slave_type == DAPC_INFRA_SLAVE && module <= SLAVE_INFRA_MAX_INDEX) + base = DEVAPC_INFRA_D0_APC_0 + domain_num * 0x100 + + apc_index * 4; + else if (slave_type == DAPC_MM_SLAVE && module <= SLAVE_MM_MAX_INDEX) + base = DEVAPC_MM_D0_APC_0 + domain_num * 0x100 + apc_index * 4; + else + return; + + mmio_clrsetbits_32(base, clr_bit, set_bit); +} + +static void set_default_master_transaction(void) +{ + set_master_transaction(MASTER_SSPM, SECURE_TRANSACTION); +} + +static void set_default_master_domain(void) +{ + set_master_domain(MASTER_SCP, DOMAIN_1); + set_master_domain_remap_infra(DOMAIN_1, DOMAIN_1); + set_master_domain_remap_mm(DOMAIN_1, DOMAIN_1); + + set_master_domain(MASTER_SPM, DOMAIN_2); + set_master_domain_remap_infra(DOMAIN_2, DOMAIN_2); + set_master_domain_remap_mm(DOMAIN_2, DOMAIN_2); + + set_master_domain(MASTER_SSPM, DOMAIN_2); + set_master_domain_remap_infra(DOMAIN_2, DOMAIN_2); + set_master_domain_remap_mm(DOMAIN_2, DOMAIN_2); +} + +static void set_default_slave_permission(void) +{ + uint32_t module_index; + uint32_t infra_size; + uint32_t mm_size; + + infra_size = sizeof(D_APC_INFRA_Devices) / sizeof(struct DEVICE_INFO); + mm_size = sizeof(D_APC_MM_Devices) / sizeof(struct DEVICE_INFO); + + for (module_index = 0; module_index < infra_size; module_index++) { + if (D_APC_INFRA_Devices[module_index].d0_permission > 0) { + set_module_apc(DAPC_INFRA_SLAVE, module_index, DOMAIN_0, + D_APC_INFRA_Devices[module_index].d0_permission); + } + if (D_APC_INFRA_Devices[module_index].d1_permission > 0) { + set_module_apc(DAPC_INFRA_SLAVE, module_index, DOMAIN_1, + D_APC_INFRA_Devices[module_index].d1_permission); + } + if (D_APC_INFRA_Devices[module_index].d2_permission > 0) { + set_module_apc(DAPC_INFRA_SLAVE, module_index, DOMAIN_2, + D_APC_INFRA_Devices[module_index].d2_permission); + } + } + + for (module_index = 0; module_index < mm_size; module_index++) { + if (D_APC_MM_Devices[module_index].d0_permission > 0) { + set_module_apc(DAPC_MM_SLAVE, module_index, DOMAIN_0, + D_APC_MM_Devices[module_index].d0_permission); + } + if (D_APC_MM_Devices[module_index].d1_permission > 0) { + set_module_apc(DAPC_MM_SLAVE, module_index, DOMAIN_1, + D_APC_MM_Devices[module_index].d1_permission); + } + if (D_APC_MM_Devices[module_index].d2_permission > 0) { + set_module_apc(DAPC_MM_SLAVE, module_index, DOMAIN_2, + D_APC_MM_Devices[module_index].d2_permission); + } + } +} + +static void dump_devapc(void) +{ + int i; + + INFO("[DEVAPC] dump DEVAPC registers:\n"); + + for (i = 0; i < 13; i++) { + INFO("[DEVAPC] (INFRA)D0_APC_%d = 0x%x, " + "(INFRA)D1_APC_%d = 0x%x, " + "(INFRA)D2_APC_%d = 0x%x\n", + i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + i * 4), + i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + 0x100 + i * 4), + i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + 0x200 + i * 4)); + } + + for (i = 0; i < 9; i++) { + INFO("[DEVAPC] (MM)D0_APC_%d = 0x%x, " + "(MM)D1_APC_%d = 0x%x, " + "(MM)D2_APC_%d = 0x%x\n", + i, mmio_read_32(DEVAPC_MM_D0_APC_0 + i * 4), + i, mmio_read_32(DEVAPC_MM_D0_APC_0 + 0x100 + i * 4), + i, mmio_read_32(DEVAPC_MM_D0_APC_0 + 0x200 + i * 4)); + } + + for (i = 0; i < 4; i++) { + INFO("[DEVAPC] MAS_DOM_%d = 0x%x\n", i, + mmio_read_32(DEVAPC_INFRA_MAS_DOM_0 + i * 4)); + } + + INFO("[DEVAPC] MAS_SEC_0 = 0x%x\n", + mmio_read_32(DEVAPC_INFRA_MAS_SEC_0)); + + INFO("[DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x%x, " + "(INFRA)MAS_DOMAIN_REMAP_1 = 0x%x\n", + mmio_read_32(DEVAPC_INFRA_DOM_RMP_0), + mmio_read_32(DEVAPC_INFRA_DOM_RMP_1)); + + INFO("[DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x%x\n", + mmio_read_32(DEVAPC_MM_DOM_RMP_0)); +} + +void devapc_init(void) +{ + mmio_write_32(DEVAPC_INFRA_APC_CON, 0x80000001); + mmio_write_32(DEVAPC_MM_APC_CON, 0x80000001); + mmio_write_32(DEVAPC_MD_APC_CON, 0x80000001); + + set_default_master_transaction(); + set_default_master_domain(); + set_default_slave_permission(); + dump_devapc(); +} + diff --git a/plat/mediatek/mt8183/drivers/devapc/devapc.h b/plat/mediatek/mt8183/drivers/devapc/devapc.h new file mode 100644 index 000000000..042a8ffea --- /dev/null +++ b/plat/mediatek/mt8183/drivers/devapc/devapc.h @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DEVAPC_H +#define DEVAPC_H + +#include + +#define DEVAPC_AO_INFRA_BASE 0x1000E000 +#define DEVAPC_AO_MM_BASE 0x1001C000 +#define DEVAPC_AO_MD_BASE 0x10019000 + +#define DEVAPC_INFRA_D0_APC_0 (DEVAPC_AO_INFRA_BASE + 0x0000) +#define DEVAPC_INFRA_MAS_DOM_0 (DEVAPC_AO_INFRA_BASE + 0x0A00) +#define DEVAPC_INFRA_MAS_SEC_0 (DEVAPC_AO_INFRA_BASE + 0x0B00) +#define DEVAPC_INFRA_DOM_RMP_0 (DEVAPC_AO_INFRA_BASE + 0x0D00) +#define DEVAPC_INFRA_DOM_RMP_1 (DEVAPC_AO_INFRA_BASE + 0x0D04) +#define DEVAPC_INFRA_APC_CON (DEVAPC_AO_INFRA_BASE + 0x0F00) + +#define DEVAPC_MD_APC_CON (DEVAPC_AO_MD_BASE + 0x0F00) + +#define DEVAPC_MM_D0_APC_0 (DEVAPC_AO_MM_BASE + 0x0000) +#define DEVAPC_MM_DOM_RMP_0 (DEVAPC_AO_MM_BASE + 0x0D00) +#define DEVAPC_MM_APC_CON (DEVAPC_AO_MM_BASE + 0x0F00) + +#define MOD_NO_IN_1_DEVAPC 16 +#define MASTER_MOD_NO_IN_1_DEVAPC 8 +#define SLAVE_INFRA_MAX_INDEX 195 +#define SLAVE_MM_MAX_INDEX 140 + +enum { + MASTER_SCP = 0, + MASTER_SPM = 10, + MASTER_SSPM = 27 +}; + +enum MASK_DOM { + DOMAIN_0 = 0, + DOMAIN_1, + DOMAIN_2, + DOMAIN_3, + DOMAIN_4, + DOMAIN_5, + DOMAIN_6, + DOMAIN_7, + DOMAIN_8, + DOMAIN_9, + DOMAIN_10, + DOMAIN_11 +}; + +enum TRANSACTION { + NON_SECURE_TRANSACTION = 0, + SECURE_TRANSACTION +}; + +enum DAPC_SLAVE_TYPE { + DAPC_INFRA_SLAVE = 0, + DAPC_MM_SLAVE +}; + +enum APC_ATTR { + NO_SEC = 0, + S_RW_ONLY, + S_RW_NS_R, + FORBID, +}; + +struct DEVICE_INFO { + uint8_t d0_permission; + uint8_t d1_permission; + uint8_t d2_permission; +}; + +#define PERMISSION(DEV_NAME, ATTR1, ATTR2, ATTR3) \ +{(uint8_t)ATTR1, (uint8_t)ATTR2, (uint8_t)ATTR3} + +static const struct DEVICE_INFO D_APC_INFRA_Devices[] = { +/* module, domain0, domain1, domain2 */ + +/* 0 */ +PERMISSION("INFRA_AO_TOPCKGEN", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("INFRA_AO_INFRASYS_CONFIG_REGS", NO_SEC, FORBID, NO_SEC), +PERMISSION("IO_CFG", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_PERICFG", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_EFUSE_AO_DEBUG", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_GPIO", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_SLEEP_CONTROLLER", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_TOPRGU", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_APXGPT", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_RESERVE", NO_SEC, FORBID, NO_SEC), + +/* 10 */ +PERMISSION("INFRA_AO_SEJ", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_AP_CIRQ_EINT", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_APMIXEDSYS", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("INFRA_AO_PMIC_WRAP", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_DEVICE_APC_AO_INFRA_PERI", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_SLEEP_CONTROLLER_MD", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_KEYPAD", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_TOP_MISC", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_DVFS_CTRL_PROC", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_MBIST_AO_REG", NO_SEC, FORBID, NO_SEC), + +/* 20 */ +PERMISSION("INFRA_AO_CLDMA_AO_AP", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_DEVICE_MPU", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_AES_TOP_0", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_SYS_TIMER", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_MDEM_TEMP_SHARE", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_DEVICE_APC_AO_MD", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_SECURITY_AO", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_TOPCKGEN_REG", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_DEVICE_APC_AO_MM", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC), + +/* 30 */ +PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_SYS_CIRQ", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_MM_IOMMU", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_EFUSE_PDN_DEBUG", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DEVICE_APC", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DBG_TRACKER", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_CCIF0_AP", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_CCIF0_MD", NO_SEC, FORBID, NO_SEC), + +/* 40 */ +PERMISSION("INFRASYS_CCIF1_AP", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_CCIF1_MD", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_MBIST", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_INFRA_PDN_REGISTER", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_TRNG", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DX_CC", NO_SEC, FORBID, NO_SEC), +PERMISSION("MD_CCIF_MD1", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_CQ_DMA", NO_SEC, FORBID, NO_SEC), +PERMISSION("MD_CCIF_MD2", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_SRAMROM", NO_SEC, FORBID, NO_SEC), + +/* 50 */ +PERMISSION("ANA_MIPI_DSI0", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("ANA_MIPI_CSI0", NO_SEC, FORBID, NO_SEC), +PERMISSION("ANA_MIPI_CSI1", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_EMI", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_CLDMA_PDN", NO_SEC, FORBID, NO_SEC), +PERMISSION("CLDMA_PDN_MD_MISC", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_MD", NO_SEC, FORBID, NO_SEC), +PERMISSION("BPI_BSI_SLV0", NO_SEC, FORBID, NO_SEC), + +/* 60 */ +PERMISSION("BPI_BSI_SLV1", NO_SEC, FORBID, NO_SEC), +PERMISSION("BPI_BSI_SLV2", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_EMI_MPU", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DVFS_PROC", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DRAMC_CH0_TOP0", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DRAMC_CH0_TOP1", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DRAMC_CH0_TOP2", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DRAMC_CH0_TOP3", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DRAMC_CH0_TOP4", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DRAMC_CH1_TOP0", NO_SEC, FORBID, NO_SEC), + +/* 70 */ +PERMISSION("INFRASYS_DRAMC_CH1_TOP1", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DRAMC_CH1_TOP2", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DRAMC_CH1_TOP3", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DRAMC_CH1_TOP4", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_GCE", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_CCIF2_AP", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_CCIF2_MD", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_CCIF3_AP", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_CCIF3_MD", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRA_AO_PWRMCU Partition 1", S_RW_NS_R, FORBID, NO_SEC), + +/* 80 */ +PERMISSION("INFRA_AO_PWRMCU Partition 2", S_RW_NS_R, FORBID, NO_SEC), +PERMISSION("INFRA_AO_PWRMCU Partition 3", S_RW_NS_R, FORBID, NO_SEC), +PERMISSION("INFRA_AO_PWRMCU Partition 4", S_RW_NS_R, FORBID, NO_SEC), +PERMISSION("INFRA_AO_PWRMCU Partition 5", S_RW_NS_R, FORBID, NO_SEC), +PERMISSION("INFRA_AO_PWRMCU Partition 6", S_RW_NS_R, FORBID, NO_SEC), +PERMISSION("INFRA_AO_PWRMCU Partition 7", S_RW_NS_R, FORBID, NO_SEC), +PERMISSION("INFRA_AO_PWRMCU Partition 8", S_RW_NS_R, FORBID, NO_SEC), +PERMISSION("INFRA_AO_SCP", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("INFRA_AO_MCUCFG", NO_SEC, FORBID, NO_SEC), +PERMISSION("INFRASYS_DBUGSYS", NO_SEC, FORBID, NO_SEC), + +/* 90 */ +PERMISSION("PERISYS_APDMA", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_AUXADC", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_UART0", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("PERISYS_UART1", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_UART2", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_I2C6", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_PWM", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_I2C0", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_I2C1", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_I2C2", NO_SEC, FORBID, NO_SEC), + +/* 100 */ +PERMISSION("PERISYS_SPI0", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_PTP", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_BTIF", NO_SEC, FORBID, NO_SEC), +PERMISSION("RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_DISP_PWM", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_I2C3", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_SPI1", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_I2C4", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_SPI2", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_SPI3", NO_SEC, FORBID, NO_SEC), + +/* 110 */ +PERMISSION("PERISYS_I2C1_IMM", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_I2C2_IMM", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_I2C5", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_I2C5_IMM", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_SPI4", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_SPI5", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_I2C7", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_I2C8", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_USB", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_USB_2_0_SUB", NO_SEC, FORBID, NO_SEC), + +/* 120 */ +PERMISSION("PERISYS_AUDIO", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_MSDC0", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_MSDC1", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_MSDC2", NO_SEC, FORBID, NO_SEC), +PERMISSION("RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_UFS", NO_SEC, FORBID, NO_SEC), +PERMISSION("RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_RESERVE_0", NO_SEC, FORBID, NO_SEC), + +/* 130 */ +PERMISSION("EAST_RESERVE_1", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_RESERVE_2", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_RESERVE_3", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_RESERVE_4", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_IO_CFG_RT", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_RESERVE_6", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_RESERVE_7", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_CSI0_TOP_AO", NO_SEC, FORBID, NO_SEC), +PERMISSION("RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_RESERVE_A", NO_SEC, FORBID, NO_SEC), + +/* 140 */ +PERMISSION("EAST_RESERVE_B", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_RESERVE_C", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_RESERVE_D", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_RESERVE_E", NO_SEC, FORBID, NO_SEC), +PERMISSION("EAST_RESERVE_F", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_RESERVE_0", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_RESERVE_1", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_IO_CFG_RM", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_IO_CFG_RB", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_EFUSE", NO_SEC, FORBID, NO_SEC), + +/* 150 */ +PERMISSION("SOUTH_RESERVE_5", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_RESERVE_6", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_RESERVE_7", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_RESERVE_8", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_RESERVE_9", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_RESERVE_A", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_RESERVE_B", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_RESERVE_C", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_RESERVE_D", NO_SEC, FORBID, NO_SEC), +PERMISSION("SOUTH_RESERVE_E", NO_SEC, FORBID, NO_SEC), + +/* 160 */ +PERMISSION("SOUTH_RESERVE_F", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_RESERVE_0", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_MSDC1_PAD_MACRO", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_RESERVE_2", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_RESERVE_3", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_RESERVE_4", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_MIPI_TX_CONFIG", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_RESERVE_6", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_IO_CFG_LB", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_IO_CFG_LM", NO_SEC, FORBID, NO_SEC), + +/* 170 */ +PERMISSION("WEST_IO_CFG_BL", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_RESERVE_A", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_RESERVE_B", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_RESERVE_C", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_RESERVE_D", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_RESERVE_E", NO_SEC, FORBID, NO_SEC), +PERMISSION("WEST_RESERVE_F", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_RESERVE_0", NO_SEC, FORBID, NO_SEC), +PERMISSION("EFUSE_TOP", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_IO_CFG_LT", NO_SEC, FORBID, NO_SEC), + +/* 180 */ +PERMISSION("NORTH_IO_CFG_TL", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_USB20 PHY", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_MSDC0 PAD MACRO", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_RESERVE_6", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_RESERVE_7", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_RESERVE_8", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_RESERVE_9", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_UFS_MPHY", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_RESERVE_B", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_RESERVE_C", NO_SEC, FORBID, NO_SEC), + +/* 190 */ +PERMISSION("NORTH_RESERVE_D", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_RESERVE_E", NO_SEC, FORBID, NO_SEC), +PERMISSION("NORTH_RESERVE_F", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_CONN", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_MD_VIOLATION", NO_SEC, FORBID, NO_SEC), +PERMISSION("PERISYS_RESERVE", NO_SEC, FORBID, NO_SEC) +}; + +static const struct DEVICE_INFO D_APC_MM_Devices[] = { +/* module, domain0, domain1, domain2 */ + +/* 0 */ +PERMISSION("G3D_CONFIG", NO_SEC, FORBID, NO_SEC), +PERMISSION("MFG VAD", NO_SEC, FORBID, NO_SEC), +PERMISSION("SC0 VAD", NO_SEC, FORBID, NO_SEC), +PERMISSION("MFG_OTHERS", NO_SEC, FORBID, NO_SEC), +PERMISSION("MMSYS_CONFIG", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("MDP_RDMA0", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("MDP_RDMA1", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("MDP_RSZ0", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("MDP_RSZ1", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("MDP_WROT0", NO_SEC, NO_SEC, NO_SEC), + +/* 10 */ +PERMISSION("MDP_WDMA", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("MDP_TDSHP", NO_SEC, FORBID, NO_SEC), +PERMISSION("DISP_OVL0", NO_SEC, FORBID, NO_SEC), +PERMISSION("DISP_OVL0_2L", NO_SEC, FORBID, NO_SEC), +PERMISSION("DISP_OVL1_2L", NO_SEC, FORBID, NO_SEC), +PERMISSION("DISP_RDMA0", NO_SEC, FORBID, NO_SEC), +PERMISSION("DISP_RDMA1", NO_SEC, FORBID, NO_SEC), +PERMISSION("DISP_WDMA0", NO_SEC, FORBID, NO_SEC), +PERMISSION("DISP_COLOR0", NO_SEC, FORBID, NO_SEC), +PERMISSION("DISP_CCORR0", NO_SEC, FORBID, NO_SEC), + +/* 20 */ +PERMISSION("DISP_AAL0", NO_SEC, FORBID, NO_SEC), +PERMISSION("DISP_GAMMA0", NO_SEC, FORBID, NO_SEC), +PERMISSION("DISP_DITHER0", NO_SEC, FORBID, NO_SEC), +PERMISSION("DSI_SPLIT", NO_SEC, FORBID, NO_SEC), +PERMISSION("DSI0", NO_SEC, FORBID, NO_SEC), +PERMISSION("DPI", NO_SEC, FORBID, NO_SEC), +PERMISSION("MM_MUTEX", NO_SEC, FORBID, NO_SEC), +PERMISSION("SMI_LARB0", NO_SEC, FORBID, NO_SEC), +PERMISSION("SMI_LARB1", NO_SEC, FORBID, NO_SEC), +PERMISSION("SMI_COMMON", NO_SEC, FORBID, NO_SEC), + +/* 30 */ +PERMISSION("DISP_RSZ", NO_SEC, FORBID, NO_SEC), +PERMISSION("MDP_AAL", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("MDP_CCORR", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("DBI", NO_SEC, FORBID, NO_SEC), +PERMISSION("MMSYS_OTHERS", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_CONFIG", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("IMGSYS_SMI_LARB1", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_DISP_A0", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("IMGSYS_DISP_A1", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_DISP_A2", NO_SEC, FORBID, NO_SEC), + +/* 40 */ +PERMISSION("IMGSYS_DISP_A3", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_DISP_A4", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_DISP_A5", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_DPE", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_RSC", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_WPEA", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_FDVT", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("IMGSYS_OWE", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_WPEB", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_MFB", NO_SEC, FORBID, NO_SEC), + +/* 50 */ +PERMISSION("IMGSYS_SMI_LARB2", NO_SEC, FORBID, NO_SEC), +PERMISSION("IMGSYS_OTHERS", NO_SEC, FORBID, NO_SEC), +PERMISSION("VENCSYS_GLOBAL_CON", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("VENCSYSSYS_SMI_LARB4", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("VENCSYS_VENC", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("VENCSYS_JPGENC", NO_SEC, FORBID, NO_SEC), +PERMISSION("VENCSYS_MBIST_CTRL", NO_SEC, FORBID, NO_SEC), +PERMISSION("VENCSYS_OTHERS", NO_SEC, FORBID, NO_SEC), +PERMISSION("VDECSYS_GLOBAL_CON", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("VDECSYS_SMI_LARB1", NO_SEC, FORBID, NO_SEC), + +/* 60 */ +PERMISSION("VDECSYS_FULL_TOP", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("VDECSYS_OTHERS", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAMSYS_TOP", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_LARB6", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("CAMSYS_LARB3", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("CAMSYS_CAM_TOP", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("CAMSYS_CAM_A", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("CAMSYS_CAM_A", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("CAMSYS_CAM_B", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("CAMSYS_CAM_B", NO_SEC, NO_SEC, NO_SEC), + +/* 70 */ +PERMISSION("CAMSYS_CAM_C", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("CAMSYS_CAM_C", NO_SEC, NO_SEC, NO_SEC), +PERMISSION("CAMSYS_CAM_TOP_SET", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_A_SET", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_A_SET", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_B_SET", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_B_SET", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_C_SET", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_C_SET", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_TOP_INNER", NO_SEC, FORBID, NO_SEC), + +/* 80 */ +PERMISSION("CAMSYS_CAM_A_INNER", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_A_INNER", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_B_INNER", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_B_INNER", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_C_INNER", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_C_INNER", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_A_EXT", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_B_EXT", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_C_EXT", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_TOP_CLR", NO_SEC, FORBID, NO_SEC), + +/* 90 */ +PERMISSION("CAMSYS_CAM_A_CLR", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_A_CLR", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_B_CLR", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_B_CLR", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_C_CLR", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_C_CLR", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_A_EXT", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_B_EXT", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_C_EXT", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAM_RESERVE", NO_SEC, FORBID, NO_SEC), + +/* 100 */ +PERMISSION("CAMSYS_SENINF_A", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_SENINF_B", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_SENINF_C", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_SENINF_D", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_SENINF_E", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_SENINF_F", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_SENINF_G", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_SENINF_H", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAMSV_A", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAMSV_B", NO_SEC, FORBID, NO_SEC), + +/* 110 */ +PERMISSION("CAMSYS_CAMSV_C", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CAMSV_D", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_MD32 DMEM_12", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_RESEVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CCU_CTL", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CCU_H2T_A", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CCU_T2H_A", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_RESERVE", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_CCU_DMA", NO_SEC, FORBID, NO_SEC), + +/* 120 */ +PERMISSION("CAMSYS_TSF", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_MD32_PMEM_24", NO_SEC, FORBID, NO_SEC), +PERMISSION("CAMSYS_OTHERS", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_CFG", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_ADL_CTRL", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREA_DMEM_0_128KB", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREA_DMEM_128_256KB", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREA_IMEM_256KB", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREA_CONTROL", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREA_DEBUG", NO_SEC, FORBID, NO_SEC), + +/* 130 */ +PERMISSION("VPUSYS_COREB_DMEM_0_128KB", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREB_DMEM_128_256KB", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREB_IMEM_256KB", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREB_CONTROL", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREB_DEBUG", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREC_DMEM_0_128KB", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREC_DMEM_128_256KB", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREC_IMEM_256KB", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREC_CONTROL", NO_SEC, FORBID, NO_SEC), +PERMISSION("VPUSYS_COREC_DEBUG", NO_SEC, FORBID, NO_SEC), + +/* 140 */ +PERMISSION("VPUSYS_OTHERS", NO_SEC, FORBID, NO_SEC) +}; + +void devapc_init(void); + +#endif /* DEVAPC_H */ + diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index efa7e9e27..71aa44ef5 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -9,6 +9,7 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/drivers/ \ + -I${MTK_PLAT_SOC}/drivers/devapc/ \ -I${MTK_PLAT_SOC}/drivers/mcdi/ \ -I${MTK_PLAT_SOC}/drivers/spmc/ \ -I${MTK_PLAT_SOC}/drivers/gpio/ \ @@ -46,6 +47,7 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT}/common/params_setup.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ ${MTK_PLAT_SOC}/aarch64/platform_common.c \ + ${MTK_PLAT_SOC}/drivers/devapc/devapc.c \ ${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c \ ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ -- cgit v1.2.3 From f25ea7e3ac3626ded4b89120376b2e5ce959f6d3 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Fri, 23 Aug 2019 15:50:58 +0800 Subject: mediatek: mt8183: add EMI MPU driver for DRAM protection Add EMI MPU driver for DRAM protection. Signed-off-by: kenny liang Change-Id: I0355e084184b5396ad8ac99fff6ef9d050fb5e96 --- plat/mediatek/mt8183/bl31_plat_setup.c | 3 + plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c | 153 +++++++++++++++++++++++++ plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h | 106 +++++++++++++++++ plat/mediatek/mt8183/include/platform_def.h | 1 + plat/mediatek/mt8183/platform.mk | 2 + 5 files changed, 265 insertions(+) create mode 100644 plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c create mode 100644 plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c index 75694964d..8204d7717 100644 --- a/plat/mediatek/mt8183/bl31_plat_setup.c +++ b/plat/mediatek/mt8183/bl31_plat_setup.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -138,6 +139,8 @@ void bl31_platform_setup(void) { devapc_init(); + emi_mpu_init(); + platform_setup_cpu(); generic_delay_timer_init(); diff --git a/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c new file mode 100644 index 000000000..64d854885 --- /dev/null +++ b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +int is_4GB(void) +{ + return 0; /* 8183 doesn't use 4GB */ +} + +/* + * emi_mpu_set_region_protection: protect a region. + * @start: start address of the region + * @end: end address of the region + * @region: EMI MPU region id + * @access_permission: EMI MPU access permission + * Return 0 for success, otherwise negative status code. + */ +int emi_mpu_set_region_protection( + unsigned long start, unsigned long end, + int region, + unsigned int access_permission) +{ + int ret = 0; + + if (end <= start) { + ERROR("[EMI][MTEE][MPU] Invalid address!.\n"); + return -1; + } + + if (is_4GB()) { + /* 4GB mode: emi_addr = phy_addr & 0xffff */ + start = EMI_PHY_OFFSET & 0xffff; + end = EMI_PHY_OFFSET & 0xffff; + } else { + /* non-4GB mode: emi_addr = phy_addr - MEM_OFFSET */ + start = start - EMI_PHY_OFFSET; + end = end - EMI_PHY_OFFSET; + } + + /*Address 64KB alignment*/ + start = start >> 16; + end = end >> 16; + + switch (region) { + case 0: + mmio_write_32(EMI_MPU_APC0, 0); + mmio_write_32(EMI_MPU_SA0, start); + mmio_write_32(EMI_MPU_EA0, end); + mmio_write_32(EMI_MPU_APC0, access_permission); + break; + + case 1: + mmio_write_32(EMI_MPU_APC1, 0); + mmio_write_32(EMI_MPU_SA1, start); + mmio_write_32(EMI_MPU_EA1, end); + mmio_write_32(EMI_MPU_APC1, access_permission); + break; + + case 2: + mmio_write_32(EMI_MPU_APC2, 0); + mmio_write_32(EMI_MPU_SA2, start); + mmio_write_32(EMI_MPU_EA2, end); + mmio_write_32(EMI_MPU_APC2, access_permission); + break; + + case 3: + mmio_write_32(EMI_MPU_APC3, 0); + mmio_write_32(EMI_MPU_SA3, start); + mmio_write_32(EMI_MPU_EA3, end); + mmio_write_32(EMI_MPU_APC3, access_permission); + break; + + case 4: + mmio_write_32(EMI_MPU_APC4, 0); + mmio_write_32(EMI_MPU_SA4, start); + mmio_write_32(EMI_MPU_EA4, end); + mmio_write_32(EMI_MPU_APC4, access_permission); + break; + + case 5: + mmio_write_32(EMI_MPU_APC5, 0); + mmio_write_32(EMI_MPU_SA5, start); + mmio_write_32(EMI_MPU_EA5, end); + mmio_write_32(EMI_MPU_APC5, access_permission); + break; + + case 6: + mmio_write_32(EMI_MPU_APC6, 0); + mmio_write_32(EMI_MPU_SA6, start); + mmio_write_32(EMI_MPU_EA6, end); + mmio_write_32(EMI_MPU_APC6, access_permission); + break; + + case 7: + mmio_write_32(EMI_MPU_APC7, 0); + mmio_write_32(EMI_MPU_SA7, start); + mmio_write_32(EMI_MPU_EA7, end); + mmio_write_32(EMI_MPU_APC7, access_permission); + break; + + default: + ret = -1; + break; + } + + return ret; +} + +void dump_emi_mpu_regions(void) +{ + unsigned int apc, sa, ea; + unsigned int apc_addr = EMI_MPU_APC0; + unsigned int sa_addr = EMI_MPU_SA0; + unsigned int ea_addr = EMI_MPU_EA0; + int i; + + for (i = 0; i < 8; ++i) { + apc = mmio_read_32(apc_addr + i * 4); + sa = mmio_read_32(sa_addr + i * 4); + ea = mmio_read_32(ea_addr + i * 4); + WARN("region %d:\n", i); + WARN("\tapc:0x%x, sa:0x%x, ea:0x%x\n", apc, sa, ea); + } +} + +void emi_mpu_init(void) +{ + /* Set permission */ + emi_mpu_set_region_protection(0x40000000UL, 0x4FFFFFFFUL, 0, + (FORBIDDEN << 3 | FORBIDDEN << 6)); + emi_mpu_set_region_protection(0x50000000UL, 0x528FFFFFUL, 1, + (FORBIDDEN << 6)); + emi_mpu_set_region_protection(0x52900000UL, 0x5FFFFFFFUL, 2, + (FORBIDDEN << 3 | FORBIDDEN << 6)); + emi_mpu_set_region_protection(0x60000000UL, 0x7FFFFFFFUL, 3, + (FORBIDDEN << 3 | FORBIDDEN << 6)); + emi_mpu_set_region_protection(0x80000000UL, 0x9FFFFFFFUL, 4, + (FORBIDDEN << 3 | FORBIDDEN << 6)); + emi_mpu_set_region_protection(0xA0000000UL, 0xBFFFFFFFUL, 5, + (FORBIDDEN << 3 | FORBIDDEN << 6)); + emi_mpu_set_region_protection(0xC0000000UL, 0xDFFFFFFFUL, 6, + (FORBIDDEN << 3 | FORBIDDEN << 6)); + emi_mpu_set_region_protection(0xE0000000UL, 0xFFFFFFFFUL, 7, + (FORBIDDEN << 3 | FORBIDDEN << 6)); + dump_emi_mpu_regions(); +} + diff --git a/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h new file mode 100644 index 000000000..b67ea563f --- /dev/null +++ b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EMI_MPU_H +#define __EMI_MPU_H + +#include + +#define EMI_MPUP (EMI_BASE + 0x01D8) +#define EMI_MPUQ (EMI_BASE + 0x01E0) +#define EMI_MPUR (EMI_BASE + 0x01E8) +#define EMI_MPUS (EMI_BASE + 0x01F0) +#define EMI_MPUT (EMI_BASE + 0x01F8) +#define EMI_MPUY (EMI_BASE + 0x0220) +#define EMI_MPU_CTRL (EMI_MPU_BASE + 0x0000) +#define EMI_MPUD0_ST (EMI_BASE + 0x0160) +#define EMI_MPUD1_ST (EMI_BASE + 0x0164) +#define EMI_MPUD2_ST (EMI_BASE + 0x0168) +#define EMI_MPUD3_ST (EMI_BASE + 0x016C) +#define EMI_MPUD0_ST2 (EMI_BASE + 0x0200) +#define EMI_MPUD1_ST2 (EMI_BASE + 0x0204) +#define EMI_MPUD2_ST2 (EMI_BASE + 0x0208) +#define EMI_MPUD3_ST2 (EMI_BASE + 0x020C) + +#define EMI_PHY_OFFSET (0x40000000UL) +#define EIGHT_DOMAIN + +#define NO_PROTECTION (0) +#define SEC_RW (1) +#define SEC_RW_NSEC_R (2) +#define SEC_RW_NSEC_W (3) +#define SEC_R_NSEC_R (4) +#define FORBIDDEN (5) +#define SEC_R_NSEC_RW (6) + +#define SECURE_OS_MPU_REGION_ID (0) +#define ATF_MPU_REGION_ID (1) + +#ifdef EIGHT_DOMAIN +#define SET_ACCESS_PERMISSON(d7, d6, d5, d4, d3, d2, d1, d0) \ + (((d7) << 21) | ((d6) << 18) | ((d5) << 15) | ((d4) << 12) \ + | ((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0)) +#else +#define SET_ACCESS_PERMISSON(d3, d2, d1, d0) \ + (((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0)) +#endif + +//#define EMI_MPU_BASE (0x1020E000U) + +#define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100) +#define EMI_MPU_SA1 (EMI_MPU_BASE + 0x104) +#define EMI_MPU_SA2 (EMI_MPU_BASE + 0x108) +#define EMI_MPU_SA3 (EMI_MPU_BASE + 0x10C) +#define EMI_MPU_SA4 (EMI_MPU_BASE + 0x110) +#define EMI_MPU_SA5 (EMI_MPU_BASE + 0x114) +#define EMI_MPU_SA6 (EMI_MPU_BASE + 0x118) +#define EMI_MPU_SA7 (EMI_MPU_BASE + 0x11C) + +#define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200) +#define EMI_MPU_EA1 (EMI_MPU_BASE + 0x204) +#define EMI_MPU_EA2 (EMI_MPU_BASE + 0x208) +#define EMI_MPU_EA3 (EMI_MPU_BASE + 0x20C) +#define EMI_MPU_EA4 (EMI_MPU_BASE + 0x210) +#define EMI_MPU_EA5 (EMI_MPU_BASE + 0x214) +#define EMI_MPU_EA6 (EMI_MPU_BASE + 0x218) +#define EMI_MPU_EA7 (EMI_MPU_BASE + 0x21C) + +#define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300) +#define EMI_MPU_APC1 (EMI_MPU_BASE + 0x304) +#define EMI_MPU_APC2 (EMI_MPU_BASE + 0x308) +#define EMI_MPU_APC3 (EMI_MPU_BASE + 0x30C) +#define EMI_MPU_APC4 (EMI_MPU_BASE + 0x310) +#define EMI_MPU_APC5 (EMI_MPU_BASE + 0x314) +#define EMI_MPU_APC6 (EMI_MPU_BASE + 0x318) +#define EMI_MPU_APC7 (EMI_MPU_BASE + 0x31C) + +#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800) +#define EMI_MPU_CTRL_D1 (EMI_MPU_BASE + 0x804) +#define EMI_MPU_CTRL_D2 (EMI_MPU_BASE + 0x808) +#define EMI_MPU_CTRL_D3 (EMI_MPU_BASE + 0x80C) +#define EMI_MPU_CTRL_D4 (EMI_MPU_BASE + 0x810) +#define EMI_MPU_CTRL_D5 (EMI_MPU_BASE + 0x814) +#define EMI_MPU_CTRL_D6 (EMI_MPU_BASE + 0x818) +#define EMI_MPU_CTRL_D7 (EMI_MPU_BASE + 0x81C) + +#define EMI_MPU_MASK_D0 (EMI_MPU_BASE + 0x900) +#define EMI_MPU_MASK_D1 (EMI_MPU_BASE + 0x904) +#define EMI_MPU_MASK_D2 (EMI_MPU_BASE + 0x908) +#define EMI_MPU_MASK_D3 (EMI_MPU_BASE + 0x90C) +#define EMI_MPU_MASK_D4 (EMI_MPU_BASE + 0x910) +#define EMI_MPU_MASK_D5 (EMI_MPU_BASE + 0x914) +#define EMI_MPU_MASK_D6 (EMI_MPU_BASE + 0x918) +#define EMI_MPU_MASK_D7 (EMI_MPU_BASE + 0x91C) + +int emi_mpu_set_region_protection( + unsigned long start, unsigned long end, + int region, + unsigned int access_permission); + +void dump_emi_mpu_regions(void); +void emi_mpu_init(void); + +#endif /* __EMI_MPU_H */ diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h index 766e76659..0a1e038b3 100644 --- a/plat/mediatek/mt8183/include/platform_def.h +++ b/plat/mediatek/mt8183/include/platform_def.h @@ -25,6 +25,7 @@ #define MCUCFG_BASE 0x0c530000 #define CFG_SF_CTRL 0x0c510014 #define CFG_SF_INI 0x0c510010 +#define EMI_BASE (IO_PHYS + 0x219000) #define EMI_MPU_BASE (IO_PHYS + 0x226000) #define TRNG_base (IO_PHYS + 0x20f000) #define MT_GIC_BASE 0x0c000000 diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index 71aa44ef5..597e18b90 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -9,6 +9,7 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/drivers/ \ + -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \ -I${MTK_PLAT_SOC}/drivers/devapc/ \ -I${MTK_PLAT_SOC}/drivers/mcdi/ \ -I${MTK_PLAT_SOC}/drivers/spmc/ \ @@ -58,6 +59,7 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ ${MTK_PLAT_SOC}/drivers/uart/uart.c \ + ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \ ${MTK_PLAT_SOC}/plat_pm.c \ ${MTK_PLAT_SOC}/plat_topology.c \ ${MTK_PLAT_SOC}/plat_mt_gic.c \ -- cgit v1.2.3 From 59ffec157ca8d675165f122c901c1ff198a810bc Mon Sep 17 00:00:00 2001 From: Usama Arif Date: Thu, 26 Sep 2019 16:07:53 +0100 Subject: a5ds: Add handler for when user tries to switch off secondary cores a5ds only has always-on power domain and there is no power control present. However, without the pwr_domain_off handler, the kernel panics when the user will try to switch off secondary cores. The a5ds_pwr_domain_off handler will prevent kernel from crashing, i.e. the kernel will attempt but fail to shut down the secondary CPUs if the user tries to switch them offline. Change-Id: I3c2239a1b6f035113ddbdda063c8495000cbe30c Signed-off-by: Usama Arif --- plat/arm/board/a5ds/a5ds_pm.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/plat/arm/board/a5ds/a5ds_pm.c b/plat/arm/board/a5ds/a5ds_pm.c index 98de77d10..cc734b005 100644 --- a/plat/arm/board/a5ds/a5ds_pm.c +++ b/plat/arm/board/a5ds/a5ds_pm.c @@ -3,6 +3,7 @@ * * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include @@ -39,6 +40,18 @@ void a5ds_pwr_domain_on_finish(const psci_power_state_t *target_state) gicv2_cpuif_enable(); } +/******************************************************************************* + * Platform handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + * a5ds only has always-on power domain and there is no power control present. + ******************************************************************************/ +void a5ds_pwr_domain_off(const psci_power_state_t *target_state) +{ + ERROR("CPU_OFF not supported on this platform\n"); + assert(false); + panic(); +} + /******************************************************************************* * Export the platform handlers via a5ds_psci_pm_ops. The ARM Standard * platform layer will take care of registering the handlers with PSCI. @@ -47,7 +60,8 @@ plat_psci_ops_t a5ds_psci_pm_ops = { /* dummy struct */ .validate_ns_entrypoint = NULL, .pwr_domain_on = a5ds_pwr_domain_on, - .pwr_domain_on_finish = a5ds_pwr_domain_on_finish + .pwr_domain_on_finish = a5ds_pwr_domain_on_finish, + .pwr_domain_off = a5ds_pwr_domain_off }; int __init plat_setup_psci_ops(uintptr_t sec_entrypoint, -- cgit v1.2.3 From 19e2af7977937b13513f448e0e162df9847b4068 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 2 Oct 2019 16:33:41 +0200 Subject: crypto: stm32_hash: align stm32_hash_update() prototype Use size_t for length parameter in header file, as in .c file. Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec Signed-off-by: Yann Gautier --- include/drivers/st/stm32_hash.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drivers/st/stm32_hash.h b/include/drivers/st/stm32_hash.h index 969d7aa13..df04730d6 100644 --- a/include/drivers/st/stm32_hash.h +++ b/include/drivers/st/stm32_hash.h @@ -14,7 +14,7 @@ enum stm32_hash_algo_mode { HASH_SHA256 }; -int stm32_hash_update(const uint8_t *buffer, uint32_t length); +int stm32_hash_update(const uint8_t *buffer, size_t length); int stm32_hash_final(uint8_t *digest); int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length, uint8_t *digest); -- cgit v1.2.3 From 57f4b6f83974b17e0aae04e17f9d95a5659ac88b Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Fri, 16 Aug 2019 16:49:41 +0200 Subject: mmc: increase delay between ACMD41 retries In the SD Specification, Power Up Diagram of Card figure, the Timeout value for initialization process (ACMD41 command retries) is 1 second. Align to match MMC cards (in mmc_send_op_cond()) and Linux kernel code, and set the delay between ACMD41 command retries to 10ms. Change-Id: I2e07cb9944e7d7b72f2d4b13e0505e6751458091 Signed-off-by: Yann Gautier --- drivers/mmc/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index db6f3f9e4..b5f6a10d3 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -361,7 +361,7 @@ static int sd_send_op_cond(void) return 0; } - mdelay(1); + mdelay(10); } ERROR("ACMD41 failed after %d retries\n", SEND_OP_COND_MAX_RETRIES); -- cgit v1.2.3 From 2dc9fe70da6788ff69856ed247b10a59173431c3 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Mon, 29 Jul 2019 14:46:16 +0200 Subject: fdts: stm32mp1: move FDCAN to PLL4_R LTDC modifies the clock frequency to adapt it to the display. Such frequency change is not detected by the FDCAN driver that instead caches the value at probe and pretends to use it later. This change fixes the issue by moving the FDCAN to PLL4_R, leaving the LTDC alone on PLL4_Q. Signed-off-by: Antonio Borneo Signed-off-by: Yann Gautier Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58 --- fdts/stm32mp157a-avenger96.dts | 2 +- fdts/stm32mp157a-dk1.dts | 2 +- fdts/stm32mp157c-ed1.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts index 9df72b444..907940c78 100644 --- a/fdts/stm32mp157a-avenger96.dts +++ b/fdts/stm32mp157a-avenger96.dts @@ -246,7 +246,7 @@ CLK_UART6_HSI CLK_UART78_HSI CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4Q + CLK_FDCAN_PLL4R CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts index b17d50194..4ea83f7cd 100644 --- a/fdts/stm32mp157a-dk1.dts +++ b/fdts/stm32mp157a-dk1.dts @@ -266,7 +266,7 @@ CLK_UART6_HSI CLK_UART78_HSI CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4Q + CLK_FDCAN_PLL4R CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts index ed55725b0..779492552 100644 --- a/fdts/stm32mp157c-ed1.dts +++ b/fdts/stm32mp157c-ed1.dts @@ -272,7 +272,7 @@ CLK_UART6_HSI CLK_UART78_HSI CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4Q + CLK_FDCAN_PLL4R CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q -- cgit v1.2.3 From 243b61d15aaa59794e73769de7be64f02223cfad Mon Sep 17 00:00:00 2001 From: Nicolas Le Bayon Date: Wed, 11 Sep 2019 15:58:31 +0200 Subject: gpio: stm32_gpio: do not mix error code types Change-Id: I84f8a99be2dcdf7c51fbecdb324df8e2f32cc855 Signed-off-by: Nicolas Le Bayon Signed-off-by: Yann Gautier --- drivers/st/gpio/stm32_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c index 343ad6c1d..a13c341a8 100644 --- a/drivers/st/gpio/stm32_gpio.c +++ b/drivers/st/gpio/stm32_gpio.c @@ -165,7 +165,7 @@ int dt_set_pinctrl_config(int node) void *fdt; if (fdt_get_address(&fdt) == 0) { - return -ENOENT; + return -FDT_ERR_NOTFOUND; } if (status == DT_DISABLED) { -- cgit v1.2.3 From 78f02ae2968dd0a78e0e686f8cf0886fa296f4eb Mon Sep 17 00:00:00 2001 From: Imre Kis Date: Mon, 22 Jul 2019 14:36:30 +0200 Subject: Introducing support for Cortex-A65AE Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422 Signed-off-by: Imre Kis --- include/lib/cpus/aarch64/cortex_a65ae.h | 31 +++++++++++++ lib/cpus/aarch64/cortex_a65ae.S | 81 +++++++++++++++++++++++++++++++++ plat/arm/board/fvp/platform.mk | 3 +- 3 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 include/lib/cpus/aarch64/cortex_a65ae.h create mode 100644 lib/cpus/aarch64/cortex_a65ae.S diff --git a/include/lib/cpus/aarch64/cortex_a65ae.h b/include/lib/cpus/aarch64/cortex_a65ae.h new file mode 100644 index 000000000..bd4a881a3 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a65ae.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A65AE_H +#define CORTEX_A65AE_H + +#include + +#define CORTEX_A65AE_MIDR U(0x410FD430) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65AE_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65AE_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ + +#define CORTEX_A65AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A65AE_H */ diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S new file mode 100644 index 000000000..ac6583ebc --- /dev/null +++ b/lib/cpus/aarch64/cortex_a65ae.S @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if !HW_ASSISTED_COHERENCY +#error "Cortex-A65AE must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS +#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +/* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A65. + * Shall clobber: x0-x19 + * ------------------------------------------------- + */ +func cortex_a65ae_reset_func + mov x19, x30 + +#if ERRATA_DSU_936184 + bl errata_dsu_936184_wa +#endif + + ret x19 +endfunc cortex_a65ae_reset_func + +func cortex_a65ae_cpu_pwr_dwn + mrs x0, CORTEX_A65AE_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_A65AE_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_a65ae_cpu_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex-A65AE. Must follow AAPCS. + */ +func cortex_a65ae_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_DSU_936184, cortex_a65ae, dsu_936184 + + ldp x8, x30, [sp], #16 + ret +endfunc cortex_a65ae_errata_report +#endif + +.section .rodata.cortex_a65ae_regs, "aS" +cortex_a65ae_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a65ae_cpu_reg_dump + adr x6, cortex_a65ae_regs + mrs x8, CORTEX_A65AE_ECTLR_EL1 + ret +endfunc cortex_a65ae_cpu_reg_dump + +declare_cpu_ops cortex_a65ae, CORTEX_A65AE_MIDR, \ + cortex_a65ae_reset_func, \ + cortex_a65ae_cpu_pwr_dwn diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index c8e2169c3..317f0bada 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -117,7 +117,8 @@ else lib/cpus/aarch64/neoverse_zeus.S \ lib/cpus/aarch64/cortex_hercules.S \ lib/cpus/aarch64/cortex_hercules_ae.S \ - lib/cpus/aarch64/cortex_a65.S + lib/cpus/aarch64/cortex_a65.S \ + lib/cpus/aarch64/cortex_a65ae.S endif # AArch64/AArch32 cores FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ -- cgit v1.2.3 From 530ceda57288aa931d0c8ba7b3066340d587cc9b Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Tue, 1 Oct 2019 13:58:23 +0100 Subject: TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U This patch adds support for ARMv8.3-PAuth in BL1 SMC calls and BL2U image for firmware updates by programming APIAKey_EL1 registers and enabling Pointer Authentication in EL3 and EL1 respectively. Change-Id: I875d952aba8242caf74fb5f4f2d2af6f0c768c08 Signed-off-by: Alexei Fedorov --- bl1/aarch64/bl1_exceptions.S | 9 +++++++++ bl1/bl1_main.c | 10 ++++++++++ bl2u/aarch64/bl2u_entrypoint.S | 9 +++++++++ lib/extensions/pauth/pauth_helpers.S | 28 ++++++++++++++++++++++++++-- 4 files changed, 54 insertions(+), 2 deletions(-) diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index 3e72e39f2..9bba6eef3 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -226,6 +226,15 @@ smc_handler: */ bl save_gp_pmcr_pauth_regs +#if ENABLE_PAUTH + /* ----------------------------------------------------- + * Load and program stored APIAKey firmware key. + * Re-enable pointer authentication in EL3, as it was + * disabled before jumping to the next boot image. + * ----------------------------------------------------- + */ + bl pauth_load_bl1_apiakey_enable +#endif /* ----------------------------------------------------- * Populate the parameters for the SMC handler. We * already have x0-x4 in place. x5 will point to a diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index 2bb85114f..cd6fe7d5e 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -31,6 +31,10 @@ DEFINE_SVC_UUID2(bl1_svc_uid, static void bl1_load_bl2(void); +#if ENABLE_PAUTH +uint64_t bl1_apiakey[2]; +#endif + /******************************************************************************* * Helper utility to calculate the BL2 memory layout taking into consideration * the BL1 RW data assuming that it is at the top of the memory layout. @@ -131,6 +135,12 @@ void bl1_main(void) /* Perform platform setup in BL1. */ bl1_platform_setup(); +#if ENABLE_PAUTH + /* Store APIAKey_EL1 key */ + bl1_apiakey[0] = read_apiakeylo_el1(); + bl1_apiakey[1] = read_apiakeyhi_el1(); +#endif /* ENABLE_PAUTH */ + /* Get the image id of next image to load and run. */ image_id = bl1_plat_get_next_image_id(); diff --git a/bl2u/aarch64/bl2u_entrypoint.S b/bl2u/aarch64/bl2u_entrypoint.S index 452869ea9..3e37b44f7 100644 --- a/bl2u/aarch64/bl2u_entrypoint.S +++ b/bl2u/aarch64/bl2u_entrypoint.S @@ -102,6 +102,15 @@ func bl2u_entrypoint bl bl2u_early_platform_setup bl bl2u_plat_arch_setup +#if ENABLE_PAUTH + /* --------------------------------------------- + * Program APIAKey_EL1 + * and enable pointer authentication. + * --------------------------------------------- + */ + bl pauth_init_enable_el1 +#endif + /* --------------------------------------------- * Jump to bl2u_main function. * --------------------------------------------- diff --git a/lib/extensions/pauth/pauth_helpers.S b/lib/extensions/pauth/pauth_helpers.S index c6808de5b..d483c7df7 100644 --- a/lib/extensions/pauth/pauth_helpers.S +++ b/lib/extensions/pauth/pauth_helpers.S @@ -13,6 +13,7 @@ .global pauth_init_enable_el3 .global pauth_disable_el3 .globl pauth_load_bl31_apiakey + .globl pauth_load_bl1_apiakey_enable /* ------------------------------------------------------------- * Program APIAKey_EL1 and enable pointer authentication in EL1 @@ -97,9 +98,9 @@ func pauth_disable_el3 endfunc pauth_disable_el3 /* ------------------------------------------------------------- - * The following function strictly follows the AArch64 PCS + * The following functions strictly follow the AArch64 PCS * to use x9-x17 (temporary caller-saved registers) to load - * the APIAKey_EL1 used by the firmware. + * the APIAKey_EL1 and enable pointer authentication. * ------------------------------------------------------------- */ func pauth_load_bl31_apiakey @@ -115,3 +116,26 @@ func pauth_load_bl31_apiakey isb ret endfunc pauth_load_bl31_apiakey + +func pauth_load_bl1_apiakey_enable + /* Load instruction key A used by the Trusted Firmware */ + adrp x9, bl1_apiakey + add x9, x9, :lo12:bl1_apiakey + ldp x10, x11, [x9] + + /* Program instruction key A */ + msr APIAKeyLo_EL1, x10 + msr APIAKeyHi_EL1, x11 + + /* Enable pointer authentication */ + mrs x9, sctlr_el3 + orr x9, x9, #SCTLR_EnIA_BIT + +#if ENABLE_BTI + /* Enable PAC branch type compatibility */ + bic x9, x9, #SCTLR_BT_BIT +#endif + msr sctlr_el3, x9 + isb + ret +endfunc pauth_load_bl1_apiakey_enable -- cgit v1.2.3 From 0711ee5cbc5645b55de1a751bd52dc8ce02ae037 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Tue, 24 Sep 2019 16:59:56 +0200 Subject: delay: timeout detection support Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT. timeout_init_us(some_timeout_us); returns a reference to detect timeout for the provided microsecond delay value from current time. timeout_elapsed(reference) return true/false whether the reference timeout is elapsed. Cherry picked from OP-TEE implementation [1]. [1] commit 33d30a74502b ("core: timeout detection support") Minor: - Remove stm32mp platform duplicated implementation. - Add new include in marvell ble.mk Signed-off-by: Etienne Carriere Signed-off-by: Lionel Debieve Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c --- include/drivers/delay_timer.h | 25 ++++++++++++++++++++++++- plat/marvell/a8k/common/ble/ble.mk | 1 + plat/st/common/include/stm32mp_common.h | 18 ------------------ 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/include/drivers/delay_timer.h b/include/drivers/delay_timer.h index 684f1c3c3..e5044cc6e 100644 --- a/include/drivers/delay_timer.h +++ b/include/drivers/delay_timer.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Linaro Limited * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,8 +8,11 @@ #ifndef DELAY_TIMER_H #define DELAY_TIMER_H +#include #include +#include + /******************************************************************** * A simple timer driver providing synchronous delay functionality. * The driver must be initialized with a structure that provides a @@ -23,6 +27,25 @@ typedef struct timer_ops { uint32_t clk_div; } timer_ops_t; +static inline uint64_t timeout_cnt_us2cnt(uint32_t us) +{ + return ((uint64_t)us * (uint64_t)read_cntfrq_el0()) / 1000000ULL; +} + +static inline uint64_t timeout_init_us(uint32_t us) +{ + uint64_t cnt = timeout_cnt_us2cnt(us); + + cnt += read_cntfrq_el0(); + + return cnt; +} + +static inline bool timeout_elapsed(uint64_t expire_cnt) +{ + return read_cntpct_el0() > expire_cnt; +} + void mdelay(uint32_t msec); void udelay(uint32_t usec); void timer_init(const timer_ops_t *ops_ptr); diff --git a/plat/marvell/a8k/common/ble/ble.mk b/plat/marvell/a8k/common/ble/ble.mk index b24083fc3..b6a9cd291 100644 --- a/plat/marvell/a8k/common/ble/ble.mk +++ b/plat/marvell/a8k/common/ble/ble.mk @@ -19,6 +19,7 @@ BLE_SOURCES += $(BLE_PATH)/ble_main.c \ PLAT_INCLUDES += -I$(MV_DDR_PATH) \ -I$(CURDIR)/include \ + -I$(CURDIR)/include/arch/aarch64 \ -I$(CURDIR)/include/lib/libc \ -I$(CURDIR)/include/lib/libc/aarch64 \ -I$(CURDIR)/drivers/marvell diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index 59657fdc2..4f8567979 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -1,6 +1,5 @@ /* * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved - * Copyright (c) 2018-2019, Linaro Limited * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,8 +11,6 @@ #include -#include - /* Functions to save and get boot context address given by ROM code */ void stm32mp_save_boot_ctx_address(uintptr_t address); uintptr_t stm32mp_get_boot_ctx_address(void); @@ -82,21 +79,6 @@ unsigned long stm32mp_clk_get_rate(unsigned long id); /* Initialise the IO layer and register platform IO devices */ void stm32mp_io_setup(void); -static inline uint64_t arm_cnt_us2cnt(uint32_t us) -{ - return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL; -} - -static inline uint64_t timeout_init_us(uint32_t us) -{ - return read_cntpct_el0() + arm_cnt_us2cnt(us); -} - -static inline bool timeout_elapsed(uint64_t expire) -{ - return read_cntpct_el0() > expire; -} - /* * Check that the STM32 header of a .stm32 binary image is valid * @param header: pointer to the stm32 image header -- cgit v1.2.3 From c97cba4ea44910df1f7b1af5dba79013fb44c383 Mon Sep 17 00:00:00 2001 From: Soby Mathew Date: Wed, 25 Sep 2019 14:03:41 +0100 Subject: Fix the CAS spinlock implementation Make the spinlock implementation use ARMv8.1-LSE CAS instruction based on a platform build option. The CAS-based implementation used to be unconditionally selected for all ARM8.1+ platforms. The previous CAS spinlock implementation had a bug wherein the spin_unlock() implementation had an `sev` after `stlr` which is not sufficient. A dsb is needed to ensure that the stlr completes prior to the sev. Having a dsb is heavyweight and a better solution would be to use load exclusive semantics to monitor the lock and wake up from wfe when a store happens to the lock. The patch implements the same. Change-Id: I5283ce4a889376e4cc01d1b9d09afa8229a2e522 Signed-off-by: Soby Mathew Signed-off-by: Olivier Deprez --- Makefile | 11 +++++++ docs/design/firmware-design.rst | 7 +++-- docs/getting_started/user-guide.rst | 4 +++ lib/locks/exclusive/aarch64/spinlock.S | 53 ++++++++++++---------------------- make_helpers/defaults.mk | 5 ++++ 5 files changed, 43 insertions(+), 37 deletions(-) diff --git a/Makefile b/Makefile index 32918c385..18800cb83 100644 --- a/Makefile +++ b/Makefile @@ -141,6 +141,15 @@ else $(error Unknown BRANCH_PROTECTION value ${BRANCH_PROTECTION}) endif +# USE_SPINLOCK_CAS requires AArch64 build +ifeq (${USE_SPINLOCK_CAS},1) +ifneq (${ARCH},aarch64) + $(error USE_SPINLOCK_CAS requires AArch64) +else + $(info USE_SPINLOCK_CAS is an experimental feature) +endif +endif + ################################################################################ # Toolchain ################################################################################ @@ -690,6 +699,7 @@ $(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY)) $(eval $(call assert_boolean,BL2_AT_EL3)) $(eval $(call assert_boolean,BL2_IN_XIP_MEM)) $(eval $(call assert_boolean,BL2_INV_DCACHE)) +$(eval $(call assert_boolean,USE_SPINLOCK_CAS)) $(eval $(call assert_numeric,ARM_ARCH_MAJOR)) $(eval $(call assert_numeric,ARM_ARCH_MINOR)) @@ -755,6 +765,7 @@ $(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY)) $(eval $(call add_define,BL2_AT_EL3)) $(eval $(call add_define,BL2_IN_XIP_MEM)) $(eval $(call add_define,BL2_INV_DCACHE)) +$(eval $(call add_define,USE_SPINLOCK_CAS)) ifeq (${SANITIZE_UB},trap) $(eval $(call add_define,MONITOR_TRAPS)) diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index dc0820826..2cbd9c946 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -2540,8 +2540,11 @@ Armv8.1-A This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when ``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. -- The Compare and Swap instruction is used to implement spinlocks. Otherwise, - the load-/store-exclusive instruction pair is used. +- By default, a load-/store-exclusive instruction pair is used to implement + spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the + spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction. + Notice this instruction is only available in AArch64 execution state, so + the option is only available to AArch64 builds. Armv8.2-A ~~~~~~~~~ diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 44bfb7a33..ae276f25d 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -820,6 +820,10 @@ Common build options reduces SRAM usage. Refer to `Library at ROM`_ for further details. Default is 0. +- ``USE_SPINLOCK_CAS``: Setting this build flag to 1 selects the spinlock + implementation variant using the ARMv8.1-LSE compare-and-swap instruction. + Notice this option is experimental and only available to AArch64 builds. + - ``V``: Verbose build. If assigned anything other than 0, the build commands are printed. Default is 0. diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S index d0569f1cd..e941b8a34 100644 --- a/lib/locks/exclusive/aarch64/spinlock.S +++ b/lib/locks/exclusive/aarch64/spinlock.S @@ -9,56 +9,38 @@ .globl spin_lock .globl spin_unlock -#if ARM_ARCH_AT_LEAST(8, 1) +#if USE_SPINLOCK_CAS +#if !ARM_ARCH_AT_LEAST(8, 1) +#error USE_SPINLOCK_CAS option requires at least an ARMv8.1 platform +#endif /* * When compiled for ARMv8.1 or later, choose spin locks based on Compare and * Swap instruction. */ -# define USE_CAS 1 - -/* - * Lock contenders using CAS, upon failing to acquire the lock, wait with the - * monitor in open state. Therefore, a normal store upon unlocking won't - * generate an SEV. Use explicit SEV instruction with CAS unlock. - */ -# define COND_SEV() sev - -#else - -# define USE_CAS 0 - -/* - * Lock contenders using exclusive pairs, upon failing to acquire the lock, wait - * with the monitor in exclusive state. A normal store upon unlocking will - * implicitly generate an envent; so, no explicit SEV with unlock is required. - */ -# define COND_SEV() - -#endif - -#if USE_CAS /* * Acquire lock using Compare and Swap instruction. * - * Compare for 0 with acquire semantics, and swap 1. Wait until CAS returns - * 0. + * Compare for 0 with acquire semantics, and swap 1. If failed to acquire, use + * load exclusive semantics to monitor the address and enter WFE. * * void spin_lock(spinlock_t *lock); */ func spin_lock mov w2, #1 - sevl -1: +1: mov w1, wzr +2: casa w1, w2, [x0] + cbz w1, 3f + ldxr w1, [x0] + cbz w1, 2b wfe - mov w1, wzr - casa w1, w2, [x0] - cbnz w1, 1b + b 1b +3: ret endfunc spin_lock -#else /* !USE_CAS */ +#else /* !USE_SPINLOCK_CAS */ /* * Acquire lock using load-/store-exclusive instruction pair. @@ -76,17 +58,18 @@ l2: ldaxr w1, [x0] ret endfunc spin_lock -#endif /* USE_CAS */ +#endif /* USE_SPINLOCK_CAS */ /* * Release lock previously acquired by spin_lock. * - * Unconditionally write 0, and conditionally generate an event. + * Use store-release to unconditionally clear the spinlock variable. + * Store operation generates an event to all cores waiting in WFE + * when address is monitored by the global monitor. * * void spin_unlock(spinlock_t *lock); */ func spin_unlock stlr wzr, [x0] - COND_SEV() ret endfunc spin_unlock diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index b6f76559c..b7fb173b1 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -234,3 +234,8 @@ else endif SANITIZE_UB := off + +# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock +# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. +# Default: disabled +USE_SPINLOCK_CAS := 0 -- cgit v1.2.3 From 80942622fe760c23f0a677eac48aff37e90f4251 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Tue, 20 Aug 2019 15:51:24 -0500 Subject: Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6 --- bl31/aarch64/ea_delegate.S | 39 +++++++++++--- docs/design/cpu-specific-build-macros.rst | 3 ++ include/lib/cpus/aarch64/cpu_macros.S | 19 +++++-- include/lib/cpus/aarch64/neoverse_n1.h | 3 ++ lib/cpus/aarch64/cpu_helpers.S | 21 ++++++++ lib/cpus/aarch64/neoverse_n1.S | 85 ++++++++++++++++++++++++++++++- lib/cpus/cpu-ops.mk | 8 +++ 7 files changed, 167 insertions(+), 11 deletions(-) diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S index 6e71a063a..3cc4d56a3 100644 --- a/bl31/aarch64/ea_delegate.S +++ b/bl31/aarch64/ea_delegate.S @@ -11,7 +11,8 @@ #include #include #include - +#include +#include .globl handle_lower_el_ea_esb .globl enter_lower_el_sync_ea @@ -35,9 +36,9 @@ endfunc handle_lower_el_ea_esb /* * This function forms the tail end of Synchronous Exception entry from lower - * EL, and expects to handle only Synchronous External Aborts from lower EL. If - * any other kind of exception is detected, then this function reports unhandled - * exception. + * EL, and expects to handle Synchronous External Aborts from lower EL and CPU + * Implementation Defined Exceptions. If any other kind of exception is detected, + * then this function reports unhandled exception. * * Since it's part of exception vector, this function doesn't expect any GP * registers to have been saved. It delegates the handling of the EA to platform @@ -58,12 +59,33 @@ func enter_lower_el_sync_ea b.eq 1f cmp x30, #EC_DABORT_LOWER_EL - b.ne 2f + b.eq 1f + + /* Save GP registers */ + stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + + /* Get the cpu_ops pointer */ + bl get_cpu_ops_ptr + + /* Get the cpu_ops exception handler */ + ldr x0, [x0, #CPU_E_HANDLER_FUNC] + + /* + * If the reserved function pointer is NULL, this CPU does not have an + * implementation defined exception handler function + */ + cbz x0, 2f + mrs x1, esr_el3 + ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH + blr x0 + b 2f 1: /* Test for EA bit in the instruction syndrome */ mrs x30, esr_el3 - tbz x30, #ESR_ISS_EABORT_EA_BIT, 2f + tbz x30, #ESR_ISS_EABORT_EA_BIT, 3f /* * Save general purpose and ARMv8.3-PAuth registers (if enabled). @@ -84,6 +106,11 @@ func enter_lower_el_sync_ea b delegate_sync_ea 2: + ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + +3: /* Synchronous exceptions other than the above are assumed to be EA */ ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] no_ret report_unhandled_exception diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index d3fe89d62..a392eea2b 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -258,6 +258,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index 044aacaf4..c83824d77 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -43,6 +43,7 @@ .equ CPU_MIDR_SIZE, CPU_WORD_SIZE .equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE .equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE + .equ CPU_E_HANDLER_FUNC_SIZE, CPU_WORD_SIZE .equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE .equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS .equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE @@ -83,7 +84,8 @@ .equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE .equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE .equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE - .equ CPU_PWR_DWN_OPS, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE + .equ CPU_E_HANDLER_FUNC, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE + .equ CPU_PWR_DWN_OPS, CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE .equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE .equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE .equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE @@ -139,6 +141,8 @@ * This is a placeholder for future per CPU operations. Currently * some CPUs use this entry to set a function to disable the * workaround for CVE-2018-3639. + * _e_handler: + * This is a placeholder for future per CPU exception handlers. * _power_down_ops: * Comma-separated list of functions to perform power-down * operatios on the CPU. At least one, and up to @@ -149,7 +153,7 @@ * used to handle power down at subsequent levels */ .macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \ - _extra1:req, _extra2:req, _power_down_ops:vararg + _extra1:req, _extra2:req, _e_handler:req, _power_down_ops:vararg .section cpu_ops, "a" .align 3 .type cpu_ops_\_name, %object @@ -159,6 +163,7 @@ #endif .quad \_extra1 .quad \_extra2 + .quad \_e_handler #ifdef IMAGE_BL31 /* Insert list of functions */ fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops @@ -203,15 +208,21 @@ .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \ _power_down_ops:vararg - declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, \ + declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, \ \_power_down_ops .endm + .macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \ + _e_handler:req, _power_down_ops:vararg + declare_cpu_ops_base \_name, \_midr, \_resetfunc, \ + 0, 0, \_e_handler, \_power_down_ops + .endm + .macro declare_cpu_ops_wa _name:req, _midr:req, \ _resetfunc:req, _extra1:req, _extra2:req, \ _power_down_ops:vararg declare_cpu_ops_base \_name, \_midr, \_resetfunc, \ - \_extra1, \_extra2, \_power_down_ops + \_extra1, \_extra2, 0, \_power_down_ops .endm #if REPORT_ERRATA diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index f90aa2ea4..fa733ce1b 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -12,6 +12,9 @@ /* Neoverse N1 MIDR for revision 0 */ #define NEOVERSE_N1_MIDR U(0x410fd0c0) +/* Exception Syndrome register EC code for IC Trap */ +#define NEOVERSE_N1_EC_IC_TRAP U(0x1f) + /******************************************************************************* * CPU Power Control register specific definitions. ******************************************************************************/ diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index de1177c39..808c7f807 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -227,6 +227,27 @@ func cpu_rev_var_hs ret endfunc cpu_rev_var_hs +/* + * Compare the CPU's revision-variant (x0) with a given range (x1 - x2), for errata + * application purposes. If the revision-variant is between or includes the given + * values, this indicates that errata applies; otherwise not. + * + * Shall clobber: x0-x4 + */ + .globl cpu_rev_var_range +func cpu_rev_var_range + mov x3, #ERRATA_APPLIES + mov x4, #ERRATA_NOT_APPLIES + cmp x0, x1 + csel x1, x3, x4, hs + cbz x1, 1f + cmp x0, x2 + csel x1, x3, x4, ls +1: + mov x0, x1 + ret +endfunc cpu_rev_var_range + #if REPORT_ERRATA /* * void print_errata_status(void); diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 31e7a3a71..c9bb005e3 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -9,6 +9,7 @@ #include #include #include +#include /* Hardware handled coherency */ #if HW_ASSISTED_COHERENCY == 0 @@ -20,6 +21,10 @@ #error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +#if ERRATA_N1_IC_TRAP + .global neoverse_n1_errata_ic_trap_handler +#endif + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1043202. * This applies to revision r0p0 and r1p0 of Neoverse N1. @@ -337,6 +342,41 @@ func check_errata_1315703 b cpu_rev_var_ls endfunc check_errata_1315703 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Erratum 1542419. + * This applies to revisions r3p0 - r4p0 of Neoverse N1 + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1542419_wa + /* Compare x0 against revision r3p0 and r4p0 */ + mov x17, x30 + bl check_errata_1542419 + cbz x0, 1f + + /* Apply instruction patching sequence */ + ldr x0, =0x0 + msr CPUPSELR_EL3, x0 + ldr x0, =0xEE670D35 + msr CPUPOR_EL3, x0 + ldr x0, =0xFFFF0FFF + msr CPUPMR_EL3, x0 + ldr x0, =0x08000020007D + msr CPUPCR_EL3, x0 + isb +1: + ret x17 +endfunc errata_n1_1542419_wa + +func check_errata_1542419 + /* Applies to everything r3p0 - r4p0. */ + mov x1, #0x30 + mov x2, #0x40 + b cpu_rev_var_range +endfunc check_errata_1542419 + func neoverse_n1_reset_func mov x19, x30 @@ -406,6 +446,11 @@ func neoverse_n1_reset_func bl errata_n1_1315703_wa #endif +#if ERRATA_N1_1542419 + mov x0, x18 + bl errata_n1_1542419_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -471,6 +516,7 @@ func neoverse_n1_errata_report report_errata ERRATA_N1_1262888, neoverse_n1, 1262888 report_errata ERRATA_N1_1275112, neoverse_n1, 1275112 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 + report_errata ERRATA_N1_1542419, neoverse_n1, 1542419 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 ldp x8, x30, [sp], #16 @@ -478,6 +524,42 @@ func neoverse_n1_errata_report endfunc neoverse_n1_errata_report #endif +/* + * Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB + * inner-shareable invalidation to an arbitrary address followed by a DSB. + * + * x1: Exception Syndrome + */ +func neoverse_n1_errata_ic_trap_handler + cmp x1, #NEOVERSE_N1_EC_IC_TRAP + b.ne 1f + tlbi vae3is, xzr + dsb sy + + # Skip the IC instruction itself + mrs x3, elr_el3 + add x3, x3, #4 + msr elr_el3, x3 + + ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + +#if IMAGE_BL31 && RAS_EXTENSION + /* + * Issue Error Synchronization Barrier to synchronize SErrors before + * exiting EL3. We're running with EAs unmasked, so any synchronized + * errors would be taken immediately; therefore no need to inspect + * DISR_EL1 register. + */ + esb +#endif + eret +1: + ret +endfunc neoverse_n1_errata_ic_trap_handler + /* --------------------------------------------- * This function provides neoverse_n1 specific * register information for crash reporting. @@ -497,6 +579,7 @@ func neoverse_n1_cpu_reg_dump ret endfunc neoverse_n1_cpu_reg_dump -declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ +declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \ neoverse_n1_reset_func, \ + neoverse_n1_errata_ic_trap_handler, \ neoverse_n1_core_pwr_dwn diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 260402351..078888ebf 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -278,6 +278,10 @@ ERRATA_N1_1275112 ?=0 # to revisions before r3p1 of the Neoverse N1 cpu. ERRATA_N1_1315703 ?=1 +# Flag to apply erratum 1542419 workaround during reset. This erratum applies +# to revisions r3p0 - r4p0 of the Neoverse N1 cpu. +ERRATA_N1_1542419 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -507,6 +511,10 @@ $(eval $(call add_define,ERRATA_N1_1275112)) $(eval $(call assert_boolean,ERRATA_N1_1315703)) $(eval $(call add_define,ERRATA_N1_1315703)) +# Process ERRATA_N1_1542419 flag +$(eval $(call assert_boolean,ERRATA_N1_1542419)) +$(eval $(call add_define,ERRATA_N1_1542419)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- cgit v1.2.3 From 2a7adf2567aa103ced4a9a9b3ef8344935716d25 Mon Sep 17 00:00:00 2001 From: Petre-Ionut Tudor Date: Thu, 3 Oct 2019 17:09:08 +0100 Subject: Explicitly disable the SPME bit in MDCR_EL3 Currently the MDCR_EL3 initialisation implicitly disables MDCR_EL3.SPME by using mov_imm. This patch makes the SPME bit more visible by explicitly disabling it and documenting its use in different versions of the architecture. Signed-off-by: Petre-Ionut Tudor Change-Id: I221fdf314f01622f46ac5aa43388f59fa17a29b3 --- include/arch/aarch64/el3_common_macros.S | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index ee20d5b2d..378e827ce 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -113,11 +113,18 @@ * prohibited in Secure state. This bit is RES0 in versions of the * architecture earlier than ARMv8.5, setting it to 1 doesn't have any * effect on them. + * + * MDCR_EL3.SPME: Set to zero so that event counting by the programmable + * counters PMEVCNTR_EL0 is prohibited in Secure state. If ARMv8.2 + * Debug is not implemented this bit does not have any effect on the + * counters unless there is support for the implementation defined + * authentication interface ExternalSecureNoninvasiveDebugEnabled(). * --------------------------------------------------------------------- */ mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \ - ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT)) + ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | MDCR_TDA_BIT | \ + MDCR_TPM_BIT)) msr mdcr_el3, x0 -- cgit v1.2.3 From e43ed98b801b8d6583d6854cd57d4beec9f314de Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Fri, 4 Oct 2019 10:37:48 +0000 Subject: doc: Add more missing platforms Add meson-g12a, qemu-sbsa and rpi4 to the documentation index so that they will have their docs rendered and integrated into the table of contents. Change-Id: Id972bf2fee67312dd7bff29f92bea67842e62431 Signed-off-by: Paul Beesley --- docs/plat/index.rst | 3 +++ docs/plat/qemu-sbsa.rst | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ docs/plat/qemu_sbsa.rst | 48 ------------------------------------------------ 3 files changed, 51 insertions(+), 48 deletions(-) create mode 100644 docs/plat/qemu-sbsa.rst delete mode 100644 docs/plat/qemu_sbsa.rst diff --git a/docs/plat/index.rst b/docs/plat/index.rst index 2695d4e81..d0b4827bb 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -9,6 +9,7 @@ Platform Ports allwinner meson-gxbb meson-gxl + meson-g12a fvp_ve hikey hikey960 @@ -23,7 +24,9 @@ Platform Ports ls1043a poplar qemu + qemu-sbsa rpi3 + rpi4 rcar-gen3 rockchip socionext-uniphier diff --git a/docs/plat/qemu-sbsa.rst b/docs/plat/qemu-sbsa.rst new file mode 100644 index 000000000..51fe41404 --- /dev/null +++ b/docs/plat/qemu-sbsa.rst @@ -0,0 +1,48 @@ +QEMU SBSA Target +================ + +Trusted Firmware-A (TF-A) implements the EL3 firmware layer for QEMU SBSA +Armv8-A. While running Qemu from command line, we need to supply two Flash +images. First Secure BootRom is supplied by -pflash argument. This Flash image +is made by EDK2 build system by composing BL1 and FIP. Second parameter for Qemu +is responsible for Non-secure rom which also given with -pflash argument and +contains of UEFI and EFI variables (also made by EDK2 build system). Semihosting +is not used + +When QEMU starts all CPUs are released simultaneously, BL1 selects a +primary CPU to handle the boot and the secondaries are placed in a polling +loop to be released by normal world via PSCI. + +BL2 edits the FDT, generated by QEMU at run-time to add a node describing PSCI +and also enable methods for the CPUs. + +Current limitations: + +- Only cold boot is supported +- No instructions for how to load a BL32 (Secure Payload) + +To build TF-A: + +:: + + git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa + cd tfa + export CROSS_COMPILE=aarch64-linux-gnu- + make PLAT=qemu_sbsa all fip + +Images will be placed at build/qemu_sbsa/release (bl1.bin and fip.bin). +Need to copy them into top directory for EDK2 compilation. + +:: + + cp build/qemu_sbsa/release/bl1.bin ../ + cp build/qemu_sbsa/release/fip.bin ../ + +Those images cannot be used by itself (no semihosing support). Flash images are built by +EDK2 build system, refer to edk2-platform repo for full build instructions. + +:: + + git clone https://github.com/tianocore/edk2-platforms.git + Platform/Qemu/SbsaQemu/Readme.md + diff --git a/docs/plat/qemu_sbsa.rst b/docs/plat/qemu_sbsa.rst deleted file mode 100644 index e04a63c77..000000000 --- a/docs/plat/qemu_sbsa.rst +++ /dev/null @@ -1,48 +0,0 @@ -Trusted Firmware-A for QEMU SBSA target -======================================== - -Trusted Firmware-A (TF-A) implements the EL3 firmware layer for QEMU SBSA -Armv8-A. While running Qemu from command line, we need to supply two Flash -images. First Secure BootRom is supplied by -pflash argument. This Flash image -is made by EDK2 build system by composing BL1 and FIP. Second parameter for Qemu -is responsible for Non-secure rom which also given with -pflash argument and -contains of UEFI and EFI variables (also made by EDK2 build system). Semihosting -is not used - -When QEMU starts all CPUs are released simultaneously, BL1 selects a -primary CPU to handle the boot and the secondaries are placed in a polling -loop to be released by normal world via PSCI. - -BL2 edits the FDT, generated by QEMU at run-time to add a node describing PSCI -and also enable methods for the CPUs. - -Current limitations: - -- Only cold boot is supported -- No instructions for how to load a BL32 (Secure Payload) - -To build TF-A: - -:: - - git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa - cd tfa - export CROSS_COMPILE=aarch64-linux-gnu- - make PLAT=qemu_sbsa all fip - -Images will be placed at build/qemu_sbsa/release (bl1.bin and fip.bin). -Need to copy them into top directory for EDK2 compilation. - -:: - - cp build/qemu_sbsa/release/bl1.bin ../ - cp build/qemu_sbsa/release/fip.bin ../ - -Those images cannot be used by itself (no semihosing support). Flash images are built by -EDK2 build system, refer to edk2-platform repo for full build instructions. - -:: - - git clone https://github.com/tianocore/edk2-platforms.git - Platform/Qemu/SbsaQemu/Readme.md - -- cgit v1.2.3 From 9d811b856ec1d10a1285aa2c43c3e1f3a411d54b Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 8 Oct 2019 11:13:06 +0200 Subject: delay: correct timeout_init_us() The function has to use read_cntpct_el0() to update the counter, and not read_cntfrq_el0(). Change-Id: I9c676466e784c3122e9ffc2d87e66708797086e7 Signed-off-by: Yann Gautier --- include/drivers/delay_timer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drivers/delay_timer.h b/include/drivers/delay_timer.h index e5044cc6e..20a554357 100644 --- a/include/drivers/delay_timer.h +++ b/include/drivers/delay_timer.h @@ -36,7 +36,7 @@ static inline uint64_t timeout_init_us(uint32_t us) { uint64_t cnt = timeout_cnt_us2cnt(us); - cnt += read_cntfrq_el0(); + cnt += read_cntpct_el0(); return cnt; } -- cgit v1.2.3 From 38d5e150edc82570e1a3e9dc2e95dce96e6fd94e Mon Sep 17 00:00:00 2001 From: Avinash Mehta Date: Tue, 8 Oct 2019 12:09:04 +0100 Subject: Correct UART PL011 initialization calculation Currently for Armv7 plaforms the quotient calculated in pl011 uart init code is moved to register r1. This patch moves the quotient to register r2 as done for other platforms in the udiv instruction. Value of register r2 is then used to calculate the values for IBRD and FBRD register Change-Id: Ie6622f9f0e6d634378b471df5d02823b492c8a24 Signed-off-by: Avinash Mehta --- drivers/arm/pl011/aarch32/pl011_console.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/arm/pl011/aarch32/pl011_console.S b/drivers/arm/pl011/aarch32/pl011_console.S index e1e346c2f..05c8250dc 100644 --- a/drivers/arm/pl011/aarch32/pl011_console.S +++ b/drivers/arm/pl011/aarch32/pl011_console.S @@ -57,7 +57,7 @@ func console_pl011_core_init #if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) push {r0,r3} softudiv r0,r1,r2,r3 - mov r1, r0 + mov r2, r0 pop {r0,r3} #else udiv r2, r1, r2 -- cgit v1.2.3 From 347609510e30f5cc3f33beaad3cf085e8296b883 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Fri, 12 Apr 2019 14:19:42 +0100 Subject: doc: Convert internal links to RST format Currently links between documents are using the format: .rst This was required for services like GitHub because they render each document in isolation - linking to another document is like linking to any other file, just provide the full path. However, with the new approach, the .rst files are only the raw source for the documents. Once the documents have been rendered the output is now in another format (HTML in our case) and so, when linking to another document, the link must point to the rendered version and not the .rst file. The RST spec provides a few methods for linking between content. The parent of this patch enabled the automatic creation of anchors for document titles - we will use these anchors as the targets for our links. Additional anchors can be added by hand if needed, on section and sub-section titles, for example. An example of this new format, for a document with the title "Firmware Design" is :ref:`Firmware Design`. One big advantage of this is that anchors are not dependent on paths. We can then move documents around, even between directories, without breaking any links between documents. Links will need to be updated only if the title of a document changes. Change-Id: I9e2340a61dd424cbd8fd1ecc2dc166f460d81703 Signed-off-by: Paul Beesley --- docs/change-log.rst | 37 ++--- docs/components/arm-sip-service.rst | 8 +- docs/components/exception-handling.rst | 14 +- docs/components/firmware-update.rst | 18 +-- .../platform-interrupt-controller-API.rst | 9 +- docs/components/ras.rst | 7 +- docs/components/sdei.rst | 44 +++--- docs/components/xlat-tables-lib-v2-design.rst | 50 +++---- docs/contents.rst | 165 --------------------- docs/design/auth-framework.rst | 6 +- docs/design/cpu-specific-build-macros.rst | 8 +- docs/design/firmware-design.rst | 121 +++++++-------- docs/design/interrupt-framework-design.rst | 11 +- docs/design/reset-design.rst | 18 +-- docs/design/trusted-board-boot.rst | 21 ++- docs/getting_started/porting-guide.rst | 100 ++++++------- .../getting_started/psci-lib-integration-guide.rst | 20 ++- docs/getting_started/rt-svc-writers-guide.rst | 22 +-- docs/getting_started/user-guide.rst | 64 ++++---- docs/index.rst | 38 ++--- docs/license.rst | 4 +- docs/plat/socionext-uniphier.rst | 16 +- docs/process/contributing.rst | 46 +++--- docs/process/faq.rst | 13 +- docs/process/platform-compatibility-policy.rst | 6 +- docs/process/release-information.rst | 12 +- docs/process/security-hardening.rst | 6 +- docs/process/security.rst | 47 +++--- 28 files changed, 352 insertions(+), 579 deletions(-) delete mode 100644 docs/contents.rst diff --git a/docs/change-log.rst b/docs/change-log.rst index 70aafc063..0a89aa6f8 100644 --- a/docs/change-log.rst +++ b/docs/change-log.rst @@ -22,8 +22,8 @@ New Features and ``CTX_INCLUDE_PAUTH_REGS`` build flags, pointer authentication can be enabled in EL3 and S-EL1/0. - See the `Firmware Design`_ document for additional details on the use of - pointer authentication. + See the :ref:`Firmware Design` document for additional details on the use + of pointer authentication. - Enable Data Independent Timing (DIT) in EL3, where supported @@ -1359,7 +1359,7 @@ New features The PSCI library has been refactored to allow integration with **EL3 Runtime Software**. This is software that is executing at the highest secure privilege which is EL3 in AArch64 or Secure SVC/Monitor mode in AArch32. See - `PSCI Integration Guide`_. + :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. Included is a minimal AArch32 Secure Payload, **SP-MIN**, that illustrates the usage and integration of the PSCI library with EL3 Runtime Software @@ -1402,11 +1402,11 @@ New features Commits now must have a 'Signed-off-by:' field to certify that the contribution has been made under the terms of the - `Developer Certificate of Origin`_. + :download:`Developer Certificate of Origin <../dco.txt>`. A signed CLA is no longer required. - The `Contribution Guide`_ has been updated to reflect this change. + The :ref:`Contributor's Guide` has been updated to reflect this change. - Introduced Performance Measurement Framework (PMF) which provides support for capturing, storing, dumping and retrieving time-stamps to measure the @@ -1620,13 +1620,13 @@ New features - Added the following new design documents: - - `Authentication framework`_ - - `Firmware Update`_ - - `TF-A Reset Design`_ - - `Power Domain Topology Design`_ + - :ref:`Authentication Framework & Chain of Trust` + - :ref:`Firmware Update (FWU)` + - :ref:`CPU Reset` + - :ref:`PSCI Power Domain Tree Structure` - Applied the new image terminology to the code base and documentation, as - described in the `image terminology document`_. + described in the :ref:`Image Terminology` document. - The build system has been reworked to improve readability and facilitate adding future extensions. @@ -1694,7 +1694,8 @@ Issues resolved since last release ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - The Trusted Board Boot implementation has been redesigned to provide greater - modularity and scalability. See the `Authentication Framework`_ document. + modularity and scalability. See the + :ref:`Authentication Framework & Chain of Trust` document. All missing mandatory features are now implemented. - The FVP and Juno ports may now use the hash of the ROTPK stored in the @@ -1826,7 +1827,7 @@ New features create mappings only for areas in the memory map that it needs. - A Secure Payload Dispatcher (OPTEED) for the OP-TEE Trusted OS has been - added. Details of using it with TF-A can be found in `OP-TEE Dispatcher`_ + added. Details of using it with TF-A can be found in :ref:`OP-TEE Dispatcher` Issues resolved since last release ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2423,16 +2424,6 @@ releases of TF-A. *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* .. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf -.. _PSCI Integration Guide: ./getting_started/psci-lib-integration-guide.rst -.. _Developer Certificate of Origin: ../dco.txt -.. _Contribution Guide: ./process/contributing.rst -.. _Authentication framework: ./design/auth-framework.rst -.. _Firmware Update: ./design/firmware-update.rst -.. _Firmware Design: ./design/firmware-design.rst -.. _TF-A Reset Design: ./design/reset-design.rst -.. _Power Domain Topology Design: ./design/psci-pd-tree.rst -.. _image terminology document: ./getting_started/image-terminology.rst -.. _Authentication Framework: ./design/auth-framework.rst -.. _OP-TEE Dispatcher: ./spd/optee-dispatcher.rst .. _tf-issue#501: https://github.com/ARM-software/tf-issues/issues/501 .. _PR#1002: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193 +.. _mbed TLS releases: https://tls.mbed.org/tech-updates/releases diff --git a/docs/components/arm-sip-service.rst b/docs/components/arm-sip-service.rst index e450d3756..2d58586b9 100644 --- a/docs/components/arm-sip-service.rst +++ b/docs/components/arm-sip-service.rst @@ -24,9 +24,9 @@ file. Performance Measurement Framework (PMF) --------------------------------------- -The `Performance Measurement Framework`_ +The :ref:`Performance Measurement Framework ` allows callers to retrieve timestamps captured at various paths in TF-A -execution. It's described in detail in `Firmware Design document`_. +execution. Execution State Switching service --------------------------------- @@ -89,8 +89,6 @@ respectively. -------------- -*Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.* .. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html -.. _Performance Measurement Framework: ../design/firmware-design.rst#user-content-performance-measurement-framework -.. _Firmware Design document: ../design/firmware-design.rst diff --git a/docs/components/exception-handling.rst b/docs/components/exception-handling.rst index 0d0173318..3f386854f 100644 --- a/docs/components/exception-handling.rst +++ b/docs/components/exception-handling.rst @@ -26,8 +26,8 @@ Introduction Through various control bits in the ``SCR_EL3`` register, the Arm architecture allows for asynchronous exceptions to be routed to EL3. As described in the -`Interrupt Framework Design`_ document, depending on the chosen interrupt -routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of +:ref:`Interrupt Management Framework` document, depending on the chosen +interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of ``SCR_EL3`` register to effect this routing. For most use cases, other than for the purpose of facilitating context switch between Normal and Secure worlds, FIQs and IRQs routed to EL3 are not required to be handled in EL3. @@ -143,8 +143,9 @@ Interrupt handling ------------------ The |EHF| is a client of *Interrupt Management Framework*, and registers the -top-level handler for interrupts that target EL3, as described in the `Interrupt -Framework Design`_ document. This has the following implications. +top-level handler for interrupts that target EL3, as described in the +:ref:`Interrupt Management Framework` document. This has the following +implications: - On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of sufficient priority are signalled as FIQs, and therefore will be routed to @@ -618,9 +619,8 @@ The |EHF| has the following limitations: exception descriptor and the programmed priority of interrupts handled by the dispatcher match. The |EHF| cannot verify that this has been followed. ----- +-------------- -*Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.* -.. _Interrupt Framework Design: ../design/interrupt-framework-design.rst .. _SDEI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf diff --git a/docs/components/firmware-update.rst b/docs/components/firmware-update.rst index 30bdc24b2..2bff00f51 100644 --- a/docs/components/firmware-update.rst +++ b/docs/components/firmware-update.rst @@ -14,8 +14,8 @@ be complemented by other, higher level firmware update software. FWU implements a specific part of the Trusted Board Boot Requirements (TBBR) specification, Arm DEN0006C-1. It should be used in conjunction with the -`Trusted Board Boot`_ design document, which describes the image authentication -parts of the Trusted Firmware-A (TF-A) TBBR implementation. +:ref:`Trusted Board Boot` design document, which describes the image +authentication parts of the Trusted Firmware-A (TF-A) TBBR implementation. Scope ~~~~~ @@ -53,10 +53,11 @@ The primary requirements of the FWU feature are: at other Exception Levels. #. Export a platform interface to provide FWU common code with the information it needs, and to enable platform specific FWU functionality. See the - `Porting Guide`_ for details of this interface. + :ref:`Porting Guide` for details of this interface. TF-A uses abbreviated image terminology for FWU images like for other TF-A -images. An overview of this terminology can be found `here`_. +images. See the :ref:`Image Terminology` document for an explanation of these +terms. The following diagram shows the FWU boot flow for Arm development platforms. Arm CSS platforms like Juno have a System Control Processor (SCP), and these @@ -70,8 +71,8 @@ Image Identification Each FWU image and certificate is identified by a unique ID, defined by the platform, which BL1 uses to fetch an image descriptor (``image_desc_t``) via a call to ``bl1_plat_get_image_desc()``. The same ID is also used to prepare the -Chain of Trust (Refer to the `Authentication Framework Design`_ -for more information). +Chain of Trust (Refer to the :ref:`Authentication Framework & Chain of Trust` +document for more information). The image descriptor includes the following information: @@ -394,11 +395,6 @@ This is only allowed if the image is not being executed. *Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.* -.. _Trusted Board Boot: ../design/trusted-board-boot.rst -.. _Porting Guide: ../getting_started/porting-guide.rst -.. _here: ../getting_started/image-terminology.rst -.. _Authentication Framework Design: ../design/auth-framework.rst .. _Universally Unique Identifier: https://tools.ietf.org/rfc/rfc4122.txt - .. |Flow Diagram| image:: ../resources/diagrams/fwu_flow.png .. |FWU state machine| image:: ../resources/diagrams/fwu_states.png diff --git a/docs/components/platform-interrupt-controller-API.rst b/docs/components/platform-interrupt-controller-API.rst index 7890cd38f..9d02f45c0 100644 --- a/docs/components/platform-interrupt-controller-API.rst +++ b/docs/components/platform-interrupt-controller-API.rst @@ -3,9 +3,8 @@ Platform Interrupt Controller API This document lists the optional platform interrupt controller API that abstracts the runtime configuration and control of interrupt controller from the -generic code. The mandatory APIs are described in the `porting guide`__. - -.. __: ../getting_started/porting-guide.rst#interrupt-management-framework-in-bl31 +generic code. The mandatory APIs are described in the +:ref:`Porting Guide `. Function: unsigned int plat_ic_get_running_priority(void); [optional] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -303,6 +302,6 @@ should return ``INTR_ID_UNAVAILABLE``. In case of Arm standard platforms using GIC, the implementation of the API masks out the interrupt ID field from the acknowledged value from GIC. ----- +-------------- -*Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/components/ras.rst b/docs/components/ras.rst index 137c0c301..3d81f17e9 100644 --- a/docs/components/ras.rst +++ b/docs/components/ras.rst @@ -1,9 +1,6 @@ Reliability, Availability, and Serviceability (RAS) Extensions ============================================================== -.. |EHF| replace:: Exception Handling Framework -.. |TF-A| replace:: Trusted Firmware-A - This document describes |TF-A| support for Arm Reliability, Availability, and Serviceability (RAS) extensions. RAS is a mandatory extension for Armv8.2 and later CPUs, and also an optional extension to the base Armv8.0 architecture. @@ -247,6 +244,6 @@ explicit using `EHF APIs`__. .. __: exception-handling.rst#non-interrupt-flow .. __: exception-handling.rst#activating-and-deactivating-priorities ----- +-------------- -*Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/components/sdei.rst b/docs/components/sdei.rst index 2a777b385..c5275a0b7 100644 --- a/docs/components/sdei.rst +++ b/docs/components/sdei.rst @@ -7,7 +7,7 @@ Trusted Firmware-A (TF-A). Introduction ------------ -`Software Delegated Exception Interface`_ (SDEI) is an Arm specification for +Software Delegated Exception Interface (|SDEI|) is an Arm specification for Non-secure world to register handlers with firmware to receive notifications about system events. Firmware will first receive the system events by way of asynchronous exceptions and, in response, arranges for the registered handler to @@ -50,9 +50,6 @@ The remainder of this document only discusses the design and implementation of SDEI dispatcher in TF-A, and assumes that the reader is familiar with the SDEI specification, the interfaces, and their requirements. -.. [#std-event] Except event 0, which is defined by the SDEI specification as a - standard event. - Defining events --------------- @@ -78,12 +75,10 @@ event descriptors. Both macros take 3 arguments: To define event 0, the macro ``SDEI_DEFINE_EVENT_0()`` should be used. This macro takes only one parameter: an SGI number to signal other PEs. -To define an event that's meant to be `explicitly dispatched`__ (i.e., not as a +To define an event that's meant to be explicitly dispatched (i.e., not as a result of receiving an SDEI interrupt), the macro ``SDEI_EXPLICIT_EVENT()`` should be used. It accepts two parameters: -.. __: `Explicit dispatch of events`_ - - The event number (as above); - Event priority: ``SDEI_MAPF_CRITICAL`` or ``SDEI_MAPF_NORMAL``, as described @@ -110,9 +105,7 @@ Regarding event descriptors: - Statically bound shared and private interrupts must be bound to shared and private interrupts on the platform, respectively. See the section on - `interrupt configuration`__. - - .. __: `Configuration within Exception Handling Framework`_ + `Configuration within Exception Handling Framework`_. - Both arrays should be one-dimensional. The ``REGISTER_SDEI_MAP()`` macro takes care of replicating private events for each PE on the platform. @@ -130,9 +123,8 @@ Event flags ~~~~~~~~~~~ Event flags describe the properties of the event. They are bit maps that can be -``OR``\ ed to form parameters to macros that `define events`__. - -.. __: `Defining events`_ +``OR``\ ed to form parameters to macros that define events (see +`Defining events`_). - ``SDEI_MAPF_DYNAMIC``: Marks the event as dynamic. Dynamic events can be bound to (or released from) any Non-secure interrupt at runtime via the @@ -196,7 +188,7 @@ interrupts for the platform: be configured as *Group 0*. Additionally, on GICv2 systems, the build option ``GICV2_G0_FOR_EL3`` must be set to ``1``. -See also `SDEI porting requirements`_. +See also :ref:`porting_guide_sdei_requirements`. Determining client EL --------------------- @@ -250,10 +242,6 @@ rest of the sequence is similar to that in the `general SDEI dispatch`_: the requested event is dispatched to the client (assuming all the conditions are met), and when the handler completes, the preempted execution resumes. -.. [#critical-event] Examples of critical event are *SError*, *Synchronous - External Abort*, *Fault Handling interrupt*, or *Error - Recovery interrupt* from one of RAS nodes in the system. - Conditions for event dispatch ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -307,10 +295,8 @@ dispatcher: Porting requirements -------------------- -The porting requirements of the SDEI dispatcher are outlined in the `porting -guide`__. - -.. __: `SDEI porting requirements`_ +The porting requirements of the SDEI dispatcher are outlined in the +:ref:`Porting Guide `. Note on writing SDEI event handlers ----------------------------------- @@ -364,10 +350,18 @@ implemented in assembly, following a similar pattern as below: smc #0 b . ----- +-------------- + +*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.* -*Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.* +.. rubric:: Footnotes + +.. [#std-event] Except event 0, which is defined by the SDEI specification as a + standard event. + +.. [#critical-event] Examples of critical events are *SError*, *Synchronous + External Abort*, *Fault Handling interrupt* or *Error + Recovery interrupt* from one of RAS nodes in the system. .. _SDEI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf -.. _SDEI porting requirements: ../getting_started/porting-guide.rst#sdei-porting-requirements .. _Software Delegated Exception Interface: `SDEI specification`_ diff --git a/docs/components/xlat-tables-lib-v2-design.rst b/docs/components/xlat-tables-lib-v2-design.rst index 786dd3bcb..af5151f70 100644 --- a/docs/components/xlat-tables-lib-v2-design.rst +++ b/docs/components/xlat-tables-lib-v2-design.rst @@ -30,8 +30,8 @@ About version 1 and version 2 ----------------------------- This document focuses on version 2 of the library, whose sources are available -in the `lib/xlat_tables_v2`_ directory. Version 1 of the library can still be -found in `lib/xlat_tables`_ directory but it is less flexible and doesn't +in the ``lib/xlat_tables_v2`` directory. Version 1 of the library can still be +found in ``lib/xlat_tables`` directory but it is less flexible and doesn't support dynamic mapping. Although potential bug fixes will be applied to both versions, future features enhancements will focus on version 2 and might not be back-ported to version 1. Therefore, it is recommended to use version 2, @@ -62,7 +62,7 @@ map. It is one of the key interfaces to the library. It is identified by: - its attributes; - its mapping granularity (optional). -See the ``struct mmap_region`` type in `xlat_tables_v2.h`_. +See the ``struct mmap_region`` type in ``xlat_tables_v2.h``. The user usually provides a list of such mmap regions to map and lets the library transpose that in a set of translation tables. As a result, the library @@ -73,7 +73,7 @@ normal memory) as well as the memory access permissions (read-only or read-write, executable or not, secure or non-secure, and so on). In the case of the EL1&0 translation regime, the attributes also specify whether the region is a User region (EL0) or Privileged region (EL1). See the ``MT_xxx`` definitions -in `xlat_tables_v2.h`_. Note that for the EL1&0 translation regime the Execute +in ``xlat_tables_v2.h``. Note that for the EL1&0 translation regime the Execute Never attribute is set simultaneously for both EL1 and EL0. The granularity controls the translation table level to go down to when mapping @@ -162,7 +162,7 @@ coming (for the most part) from platform-specific defines: - size of the virtual address space: ``PLAT_VIRT_ADDR_SPACE_SIZE``; - size of the physical address space: ``PLAT_PHY_ADDR_SPACE_SIZE``. -Please refer to the `Porting Guide`_ for more details about these macros. +Please refer to the :ref:`Porting Guide` for more details about these macros. Static and dynamic memory regions @@ -201,7 +201,7 @@ Library APIs ------------ The external APIs exposed by this library are declared and documented in the -`xlat_tables_v2.h`_ header file. This should be the reference point for +``xlat_tables_v2.h`` header file. This should be the reference point for getting information about the usage of the different APIs this library provides. This section just provides some extra details and clarifications. @@ -284,7 +284,7 @@ The library is divided into 4 modules: provides functions such as ``mmap_add_region_ctx`` that let the caller specify the translation tables context affected by them. - See `xlat_tables_core.c`_. + See ``xlat_tables_core.c``. - **Active context module** @@ -293,14 +293,14 @@ The library is divided into 4 modules: This module provides functions such as ``mmap_add_region``, that directly affect the BL image using them. - See `xlat_tables_context.c`_. + See ``xlat_tables_context.c``. - **Utilities module** Provides additional functionality like debug print of the current state of the translation tables and helpers to query memory attributes and to modify them. - See `xlat_tables_utils.c`_. + See ``xlat_tables_utils.c``. - **Architectural module** @@ -309,7 +309,7 @@ The library is divided into 4 modules: MMU, or calculate the Physical Address Space size. They do not need a translation context to work on. - See `aarch32/xlat_tables_arch.c`_ and `aarch64/xlat_tables_arch.c`_. + See ``aarch32/xlat_tables_arch.c`` and ``aarch64/xlat_tables_arch.c``. From mmap regions to translation tables ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -343,7 +343,7 @@ The mapping function is implemented as a recursive algorithm. It is however bound by the level of depth of the translation tables (the Armv8-A architecture allows up to 4 lookup levels). -By default [#granularity-ref]_, the algorithm will attempt to minimize the +By default [#granularity]_, the algorithm will attempt to minimize the number of translation tables created to satisfy the user's request. It will favour mapping a region using the biggest possible blocks, only creating a sub-table if it is strictly necessary. This is to reduce the memory footprint of @@ -374,9 +374,6 @@ entries in the translation tables are checked to ensure consistency. Please refer to the comments in the source code of the core module for more details about the sorting algorithm in use. -.. [#granularity-ref] That is, when mmap regions do not enforce their mapping - granularity. - TLB maintenance operations ~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -402,20 +399,19 @@ descriptor. Given that the TLBs are not architecturally permitted to hold any invalid translation table entry [#tlb-no-invalid-entry]_, this means that this mapping cannot be cached in the TLBs. -.. [#tlb-reset-ref] See section D4.9 `Translation Lookaside Buffers (TLBs)`, subsection `TLB behavior at reset` in Armv8-A, rev C.a. -.. [#tlb-no-invalid-entry] See section D4.10.1 `General TLB maintenance requirements` in Armv8-A, rev C.a. +.. rubric:: Footnotes + +.. [#granularity] That is, when mmap regions do not enforce their mapping + granularity. + +.. [#tlb-reset-ref] See section D4.9 ``Translation Lookaside Buffers (TLBs)``, + subsection ``TLB behavior at reset`` in Armv8-A, rev C.a. + +.. [#tlb-no-invalid-entry] See section D4.10.1 ``General TLB maintenance + requirements`` in Armv8-A, rev C.a. -------------- -*Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.* - -.. _lib/xlat_tables_v2: ../../lib/xlat_tables_v2 -.. _lib/xlat_tables: ../../lib/xlat_tables -.. _xlat_tables_v2.h: ../../include/lib/xlat_tables/xlat_tables_v2.h -.. _xlat_tables_context.c: ../../lib/xlat_tables_v2/xlat_tables_context.c -.. _xlat_tables_core.c: ../../lib/xlat_tables_v2/xlat_tables_core.c -.. _xlat_tables_utils.c: ../../lib/xlat_tables_v2/xlat_tables_utils.c -.. _aarch32/xlat_tables_arch.c: ../../lib/xlat_tables_v2/aarch32/xlat_tables_arch.c -.. _aarch64/xlat_tables_arch.c: ../../lib/xlat_tables_v2/aarch64/xlat_tables_arch.c -.. _Porting Guide: ../getting_started/porting-guide.rst +*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.* + .. |Alignment Example| image:: ../resources/diagrams/xlat_align.png diff --git a/docs/contents.rst b/docs/contents.rst deleted file mode 100644 index 4909dabe6..000000000 --- a/docs/contents.rst +++ /dev/null @@ -1,165 +0,0 @@ -Trusted Firmware-A Documentation Contents -========================================= - -This document serves as a list of the documentation that is included with the -Trusted Firmware-A source. - -Introduction ------------- - -`About Trusted Firmware-A`_ - -Getting Started ---------------- - -`Frequently-Asked Questions (FAQ)`_ - -`Image Terminology`_ - -`Porting Guide`_ - -`User Guide`_ - -Contributing ------------- - -`Coding Style and Guidelines`_ - -`Contributor Acknowledgements`_ - -`Contributor's Guide`_ - -`License`_ - -`Maintainers`_ - -Processes and Policies ----------------------- - -`Platform Compatibility Policy`_ - -`Release Processes`_ - -Secure Payload Dispatch ------------------------ - -`OP-TEE Dispatcher`_ - -`Trusted Little Kernel (TLK) Dispatcher`_ - -`Trusty Dispatcher`_ - -System Design and Components ----------------------------- - -`Arm CPU Specific Build Macros`_ - -`Arm SiP Services`_ - -`Authentication Framework & Chain of Trust`_ - -`CPU Reset`_ - -`EL3 Runtime Service Writer’s Guide`_ - -`Exception Handling Framework`_ - -`Firmware Design Overview`_ - -`Firmware Update (FWU)`_ - -`Interrupt Management Framework`_ - -`Library at ROM`_ - -`Platform Interrupt Controller API`_ - -`PSCI Library Integration Guide for Armv8-A AArch32 systems`_ - -`PSCI Power Domain Tree design`_ - -`Reliability, Availability, and Serviceability (RAS) Extensions`_ - -`Secure Partition Manager`_ - -`Software Delegated Exception Interface`_ - -`Translation (XLAT) Tables Library`_ - -`Trusted Board Boot Design Guide`_ - -Performance and Testing ------------------------ - -`PSCI Performance Measurements on Arm Juno Development Platform`_ - -Security and Advisories ------------------------ - -`Security Processes`_ - -`TFV-1`_ - -`TFV-2`_ - -`TFV-3`_ - -`TFV-4`_ - -`TFV-5`_ - -`TFV-6`_ - -`TFV-7`_ - -`TFV-8`_ - -Other Documents ---------------- - -`Change Log`_ - -.. _About Trusted Firmware-A: ../readme.rst -.. _Frequently-Asked Questions (FAQ): ./process/faq.rst -.. _Image Terminology: ./getting_started/image-terminology.rst -.. _Porting Guide: ./getting_started/porting-guide.rst -.. _User Guide: ./getting_started/user-guide.rst -.. _Coding Style and Guidelines: ./process/coding-guidelines.rst -.. _Contributor Acknowledgements: ./acknowledgements.rst -.. _`Contributor's Guide`: ./process/contributing.rst -.. _License: ../license.rst -.. _Maintainers: ./maintainers.rst -.. _Platform Compatibility Policy: ./process/platform-compatibility-policy.rst -.. _Release Processes: ./process/release-information.rst -.. _Arm SiP Services: ./components/arm-sip-service.rst -.. _Exception Handling Framework: ./components/exception-handling.rst -.. _Firmware Update (FWU): ./components/firmware-update.rst -.. _Interrupt Management Framework: ./design/interrupt-framework-design.rst -.. _Library at ROM: ./components/romlib-design.rst -.. _Platform Interrupt Controller API: ./components/platform-interrupt-controller-API.rst -.. _`Reliability, Availability, and Serviceability (RAS) Extensions`: ./components/ras.rst -.. _Secure Partition Manager: ./components/secure-partition-manager-design.rst -.. _Software Delegated Exception Interface: ./components/sdei.rst -.. _Translation (XLAT) Tables Library: ./components/xlat-tables-lib-v2-design.rst -.. _OP-TEE Dispatcher: ./components/spd/optee-dispatcher.rst -.. _Trusted Little Kernel (TLK) Dispatcher: ./components/spd/tlk-dispatcher.rst -.. _Trusty Dispatcher: ./components/spd/trusty-dispatcher.rst -.. _Arm CPU Specific Build Macros: ./design/cpu-specific-build-macros.rst -.. _`Authentication Framework & Chain of Trust`: ./design/auth-framework.rst -.. _CPU Reset: ./design/reset-design.rst -.. _`EL3 Runtime Service Writer’s Guide`: ./getting_started/rt-svc-writers-guide.rst -.. _Firmware Design Overview: ./design/firmware-design.rst -.. _PSCI Library Integration Guide for Armv8-A AArch32 systems: ./getting_started/psci-lib-integration-guide.rst -.. _PSCI Power Domain Tree design: ./design/psci-pd-tree.rst -.. _Trusted Board Boot Design Guide: ./design/trusted-board-boot.rst -.. _PSCI Performance Measurements on Arm Juno Development Platform: ./perf/psci-performance-juno.rst -.. _Security Processes: ./process/security.rst -.. _Change Log: ./change-log.rst -.. _TFV-1: ./security_advisories/security-advisory-tfv-1.rst -.. _TFV-2: ./security_advisories/security-advisory-tfv-2.rst -.. _TFV-3: ./security_advisories/security-advisory-tfv-3.rst -.. _TFV-4: ./security_advisories/security-advisory-tfv-4.rst -.. _TFV-5: ./security_advisories/security-advisory-tfv-5.rst -.. _TFV-6: ./security_advisories/security-advisory-tfv-6.rst -.. _TFV-7: ./security_advisories/security-advisory-tfv-7.rst -.. _TFV-8: ./security_advisories/security-advisory-tfv-8.rst diff --git a/docs/design/auth-framework.rst b/docs/design/auth-framework.rst index 7de8ee1e2..93f691b7b 100644 --- a/docs/design/auth-framework.rst +++ b/docs/design/auth-framework.rst @@ -637,9 +637,9 @@ all CoTs must present: The TBBR specifies the additional certificates that must accompany these images for a proper authentication. Details about the TBBR CoT may be found in the -`Trusted Board Boot`_ document. +:ref:`Trusted Board Boot` document. -Following the `Platform Porting Guide`_, a platform must provide unique +Following the :ref:`Porting Guide`, a platform must provide unique identifiers for all the images and certificates that will be loaded during the boot process. If a platform is using the TBBR as a reference for trusted boot, these identifiers can be obtained from ``include/common/tbbr/tbbr_img_def.h``. @@ -967,6 +967,4 @@ The mbedTLS library algorithm support is configured by both the *Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.* -.. _Trusted Board Boot: ./trusted-board-boot.rst -.. _Platform Porting Guide: ../getting_started/porting-guide.rst .. _TBBR-Client specification: https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index a392eea2b..891703bf0 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -29,6 +29,8 @@ vulnerability workarounds should be applied at runtime. platform contains at least 1 CPU that requires dynamic mitigation. Defaults to 0. +.. _arm_cpu_macros_errata_workarounds: + CPU Errata Workarounds ---------------------- @@ -47,9 +49,8 @@ errata notice document. The format of the define used to enable/disable the errata workaround is ``ERRATA__``, where the ``Processor name`` is for example ``A57`` for the ``Cortex_A57`` CPU. -Refer to the section *CPU errata status reporting* in -`Firmware Design guide`_ for information on how to write errata workaround -functions. +Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to +write errata workaround functions. All workarounds are disabled by default. The platform is responsible for enabling these workarounds according to its requirement by defining the @@ -326,6 +327,5 @@ architecture that can be enabled by the platform as desired. .. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html .. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html .. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html -.. _Firmware Design guide: firmware-design.rst .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf .. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index 2cbd9c946..1deacb7f9 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -2,24 +2,27 @@ Firmware Design =============== Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot -Requirements (TBBR) Platform Design Document (PDD) [1]_ for Arm reference -platforms. The TBB sequence starts when the platform is powered on and runs up +Requirements (TBBR) Platform Design Document (PDD) for Arm reference +platforms. + +The TBB sequence starts when the platform is powered on and runs up to the stage where it hands-off control to firmware running in the normal world in DRAM. This is the cold boot path. -TF-A also implements the Power State Coordination Interface PDD [2]_ as a +TF-A also implements the `Power State Coordination Interface PDD`_ as a runtime service. PSCI is the interface from normal world software to firmware implementing power management use-cases (for example, secondary CPU boot, hotplug and idle). Normal world software can access TF-A runtime services via the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be -used as mandated by the SMC Calling Convention [3]_. +used as mandated by the SMC Calling Convention (`SMCCC`_). TF-A implements a framework for configuring and managing interrupts generated in either security state. The details of the interrupt management framework -and its design can be found in TF-A Interrupt Management Design guide [4]_. +and its design can be found in :ref:`Interrupt Management Framework`. TF-A also implements a library for setting up and managing the translation -tables. The details of this library can be found in `Translation tables design`_. +tables. The details of this library can be found in +:ref:`Translation (XLAT) Tables Library`. TF-A can be built to support either AArch64 or AArch32 execution state. @@ -34,7 +37,7 @@ executed by the primary CPU, other than essential CPU initialization executed by all CPUs. The secondary CPUs are kept in a safe platform-specific state until the primary CPU has performed enough initialization to boot them. -Refer to the `Reset Design`_ for more information on the effect of the +Refer to the :ref:`CPU Reset` for more information on the effect of the ``COLD_BOOT_SINGLE_CPU`` platform build option. The cold boot path in this implementation of TF-A depends on the execution @@ -136,15 +139,15 @@ Determination of boot path Whenever a CPU is released from reset, BL1 needs to distinguish between a warm boot and a cold boot. This is done using platform-specific mechanisms (see the -``plat_get_my_entrypoint()`` function in the `Porting Guide`_). In the case of a -warm boot, a CPU is expected to continue execution from a separate +``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case +of a warm boot, a CPU is expected to continue execution from a separate entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in -the `Porting Guide`_) while the primary CPU executes the remaining cold boot path -as described in the following sections. +the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot +path as described in the following sections. This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the -`Reset Design`_ for more information on the effect of the +:ref:`CPU Reset` for more information on the effect of the ``PROGRAMMABLE_RESET_ADDRESS`` platform build option. Architectural initialization @@ -157,8 +160,8 @@ BL1 performs minimal architectural initialization as follows. BL1 sets up simple exception vectors for both synchronous and asynchronous exceptions. The default behavior upon receiving an exception is to populate a status code in the general purpose register ``X0/R0`` and call the - ``plat_report_exception()`` function (see the `Porting Guide`_). The status - code is one of: + ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The + status code is one of: For AArch64: @@ -217,7 +220,7 @@ BL1 performs minimal architectural initialization as follows. - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control to EL3 Runtime Software. - - All SMCs listed in section "BL1 SMC Interface" in the `Firmware Update`_ + - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)` Design Guide are supported for AArch64 only. These SMCs are currently not supported when BL1 is built for AArch32. @@ -307,14 +310,15 @@ Firmware Update detection and execution ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ After performing platform setup, BL1 common code calls -``bl1_plat_get_next_image_id()`` to determine if `Firmware Update`_ is required or -to proceed with the normal boot process. If the platform code returns -``BL2_IMAGE_ID`` then the normal boot sequence is executed as described in the -next section, else BL1 assumes that `Firmware Update`_ is required and execution -passes to the first image in the `Firmware Update`_ process. In either case, BL1 -retrieves a descriptor of the next image by calling ``bl1_plat_get_image_desc()``. -The image descriptor contains an ``entry_point_info_t`` structure, which BL1 -uses to initialize the execution state of the next image. +``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is +required or to proceed with the normal boot process. If the platform code +returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described +in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is +required and execution passes to the first image in the +:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor +of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor +contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the +execution state of the next image. BL2 image load and execution ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -440,7 +444,8 @@ initialization is complete. Hence, BL2 populates a platform-specific area of memory with the entrypoint and Saved Program Status Register (``SPSR``) of the normal world software image. The entrypoint is the load address of the BL33 image. The ``SPSR`` is determined as specified in Section 5.13 of the -`PSCI PDD`_. This information is passed to the EL3 Runtime Software. +`Power State Coordination Interface PDD`_. This information is passed to the +EL3 Runtime Software. AArch64 BL31 (EL3 Runtime Software) execution ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -539,7 +544,7 @@ It then replaces the exception vectors populated by BL1 with its own. BL31 exception vectors implement more elaborate support for handling SMCs since this is the only mechanism to access the runtime services implemented by BL31 (PSCI for example). BL31 checks each SMC for validity as specified by the -`SMC calling convention PDD`_ before passing control to the required SMC +`SMC Calling Convention PDD`_ before passing control to the required SMC handler routine. BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system @@ -812,7 +817,8 @@ data access and all interrupt sources masked: The warm boot entrypoint may be implemented by using TF-A ``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil -the pre-requisites mentioned in the `PSCI Library integration guide`_. +the pre-requisites mentioned in the +:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. EL3 runtime services framework ------------------------------ @@ -1051,7 +1057,9 @@ hooks to be registered with the generic PSCI code to be supported. The PSCI implementation in TF-A is a library which can be integrated with AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to integrating PSCI library with AArch32 EL3 Runtime Software can be found -`here`_. +at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. + +.. _firmware_design_sel1_spd: Secure-EL1 Payloads and Dispatchers ----------------------------------- @@ -1258,7 +1266,7 @@ handling functions. Details for implementing a CPU specific reset handler can be found in Section 8. Details for implementing a platform specific reset handler can be -found in the `Porting Guide`_ (see the ``plat_reset_handler()`` function). +found in the :ref:`Porting Guide` (see the ``plat_reset_handler()`` function). When adding functionality to a reset handler, keep in mind that if a different reset handling behavior is required between the first and the subsequent @@ -1292,6 +1300,8 @@ by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: - Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or ``GIC_INTR_CFG_EDGE``). +.. _firmware_design_cpu_ops_fwk: + CPU specific operations framework --------------------------------- @@ -1333,7 +1343,7 @@ different CPUs during power down and reset handling. The platform can specify any CPU optimization it wants to enable for each CPU. It can also specify the CPU errata workarounds to be applied for each CPU type during reset handling by defining CPU errata compile time macros. Details on these macros -can be found in `CPU specific build macros`_. +can be found in the :ref:`Arm CPU Specific Build Macros` document. The CPU specific operations framework depends on the ``cpu_ops`` structure which needs to be exported for each type of CPU in the platform. It is defined in @@ -1399,6 +1409,8 @@ reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching be reported and a pointer to the ASCII list of register names in a format expected by the crash reporting framework. +.. _firmware_design_cpu_errata_reporting: + CPU errata status reporting ~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -1408,8 +1420,8 @@ build options. Some errata workarounds have potential run-time implications; therefore some are enabled by default, others not. Platform ports shall override build options to enable or disable errata as appropriate. The CPU drivers take care of applying errata workarounds that are enabled and applicable -to a given CPU. Refer to the section titled *CPU Errata Workarounds* in `CPUBM`_ -for more information. +to a given CPU. Refer to :ref:`arm_cpu_macros_errata_workarounds` for more +information. Functions in CPU drivers that apply errata workaround must follow the conventions listed below. @@ -1866,7 +1878,7 @@ BL image during boot. Library at ROM --------------- -Please refer to the `ROMLIB Design`_ document. +Please refer to the :ref:`Library at ROM` document. Firmware Image Package (FIP) ---------------------------- @@ -1978,11 +1990,11 @@ is the smallest possible size of the coherent memory region. By default, all data structures which are susceptible to accesses with mismatched attributes from various CPUs are allocated in a coherent memory -region (refer to section 2.1 of `Porting Guide`_). The coherent memory region -accesses are Outer Shareable, non-cacheable and they can be accessed -with the Device nGnRE attributes when the MMU is turned on. Hence, at the -expense of at least an extra page of memory, TF-A is able to work around -coherency issues due to mismatched memory attributes. +region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory +region accesses are Outer Shareable, non-cacheable and they can be accessed with +the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of +at least an extra page of memory, TF-A is able to work around coherency issues +due to mismatched memory attributes. The alternative to the above approach is to allocate the susceptible data structures in Normal WriteBack WriteAllocate Inner shareable memory. This @@ -2188,7 +2200,7 @@ As mentioned earlier, almost a page of memory can be saved by disabling whether coherent memory should be used. If a platform disables ``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the -`Porting Guide`_). Refer to the reference platform code for examples. +:ref:`Porting Guide`). Refer to the reference platform code for examples. Isolating code and read-only data on separate memory pages ---------------------------------------------------------- @@ -2381,6 +2393,8 @@ are changed within the ``bl31_plat_runtime_setup`` platform hook. The init section section can be reclaimed for any data which is accessed after cold boot initialization and it is upto the platform to make the decision. +.. _firmware_design_pmf: + Performance Measurement Framework --------------------------------- @@ -2529,7 +2543,7 @@ Architecture Extension-specific code is included in the build. Otherwise, TF-A targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values. -See also the *Summary of build options* in `User Guide`_. +See also the *Summary of build options* in :ref:`User Guide`. For details on the Architecture Extension and available features, please refer to the respective Architecture Extension Supplement. @@ -2668,37 +2682,26 @@ linker scripts which have the extension ``.ld``. FDTs provide a description of the hardware platform and are used by the Linux kernel at boot time. These can be found in the ``fdts`` directory. -References ----------- +.. rubric:: References -.. [#] `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ -.. [#] `Power State Coordination Interface PDD`_ -.. [#] `SMC Calling Convention PDD`_ -.. [#] `TF-A Interrupt Management Design guide`_. +- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ + +- `Power State Coordination Interface PDD`_ + +- `SMC Calling Convention PDD`_ + +- :ref:`Interrupt Management Framework` -------------- *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* -.. _Reset Design: ./reset-design.rst -.. _Porting Guide: ../getting_started/porting-guide.rst -.. _Firmware Update: ../components/firmware-update.rst -.. _PSCI PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf -.. _SMC calling convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf -.. _PSCI Library integration guide: ../getting_started/psci-lib-integration-guide.rst +.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf .. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf .. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf -.. _here: ../getting_started/psci-lib-integration-guide.rst -.. _CPU specific build macros: ./cpu-specific-build-macros.rst -.. _CPUBM: ./cpu-specific-build-macros.rst .. _Arm ARM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html -.. _User Guide: ../getting_started/user-guide.rst .. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf -.. _TF-A Interrupt Management Design guide: ./interrupt-framework-design.rst -.. _Translation tables design: ../components/xlat-tables-lib-v2-design.rst -.. _Exception Handling Framework: ../components/exception-handling.rst -.. _ROMLIB Design: ../components/romlib-design.rst .. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a .. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png diff --git a/docs/design/interrupt-framework-design.rst b/docs/design/interrupt-framework-design.rst index 4a864f9c8..d155cb356 100644 --- a/docs/design/interrupt-framework-design.rst +++ b/docs/design/interrupt-framework-design.rst @@ -177,10 +177,10 @@ uses this information to determine whether the IRQ or the FIQ bit should be programmed in ``SCR_EL3`` while applying the routing model for a type of interrupt. The platform provides this information through the ``plat_interrupt_type_to_line()`` API (described in the -`Porting Guide`_). For example, on the FVP port when the platform uses an Arm GICv2 -interrupt controller, Secure-EL1 interrupts are signaled through the FIQ signal -while Non-secure interrupts are signaled through the IRQ signal. This applies -when execution is in either security state. +:ref:`Porting Guide`). For example, on the FVP port when the platform uses an +Arm GICv2 interrupt controller, Secure-EL1 interrupts are signaled through the +FIQ signal while Non-secure interrupts are signaled through the IRQ signal. +This applies when execution is in either security state. Effect of mapping of several interrupt types to one signal ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -255,7 +255,7 @@ is expected to be aware of the secure devices present in the system and their associated interrupt numbers. It should configure the interrupt controller to enable the secure interrupts, ensure that their priority is always higher than the non-secure interrupts and target them to the primary CPU. It should also -export the interface described in the `Porting Guide`_ to enable +export the interface described in the :ref:`Porting Guide` to enable handling of interrupts. In the remainder of this document, for the sake of simplicity a Arm GICv2 system @@ -1013,7 +1013,6 @@ TSP by returning ``SMC_UNK`` error. *Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.* -.. _Porting Guide: ../getting_started/porting-guide.rst .. _SMC calling convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html .. |Image 1| image:: ../resources/diagrams/sec-int-handling.png diff --git a/docs/design/reset-design.rst b/docs/design/reset-design.rst index ccd717a06..a92ceeba7 100644 --- a/docs/design/reset-design.rst +++ b/docs/design/reset-design.rst @@ -6,9 +6,9 @@ resets in Trusted Firmware-A (TF-A). It also describes how the platform integrator can tailor this code to the system configuration to some extent, resulting in a simplified and more optimised boot flow. -This document should be used in conjunction with the `Firmware Design`_, which -provides greater implementation details around the reset code, specifically -for the cold boot path. +This document should be used in conjunction with the :ref:`Firmware Design` +document which provides greater implementation details around the reset code, +specifically for the cold boot path. General reset code flow ----------------------- @@ -109,11 +109,14 @@ images might be done by the Trusted Boot Firmware or by platform code in BL31. Although the Arm FVP platform does not support programming the reset base address dynamically at run-time, it is possible to set the initial value of the -``RVBAR_EL3`` register at start-up. This feature is provided on the Base FVP only. +``RVBAR_EL3`` register at start-up. This feature is provided on the Base FVP +only. + It allows the Arm FVP port to support the ``RESET_TO_BL31`` configuration, in which case the ``bl31.bin`` image must be loaded to its run address in Trusted SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run -address. See the `User Guide`_ for details of running the FVP models in this way. +address. See the :ref:`User Guide` for details of running the FVP models in this +way. Although technically it would be possible to program the reset base address with the right support in the SCP firmware, this is currently not implemented so the @@ -150,10 +153,7 @@ This might be done by the Trusted Boot Firmware or by platform code in BL31. -------------- -*Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.* - -.. _Firmware Design: firmware-design.rst -.. _User Guide: ../getting_started/user-guide.rst +*Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.* .. |Default reset code flow| image:: ../resources/diagrams/default_reset_code.png .. |Reset code flow with programmable reset address| image:: ../resources/diagrams/reset_code_no_boot_type_check.png diff --git a/docs/design/trusted-board-boot.rst b/docs/design/trusted-board-boot.rst index 82be272bf..f3b1c3644 100644 --- a/docs/design/trusted-board-boot.rst +++ b/docs/design/trusted-board-boot.rst @@ -8,8 +8,9 @@ Public-Key-Cryptography Standards (PKCS). This document describes the design of Trusted Firmware-A (TF-A) TBB, which is an implementation of the `Trusted Board Boot Requirements (TBBR)`_ specification, -Arm DEN0006D. It should be used in conjunction with the `Firmware Update`_ -design document, which implements a specific aspect of the TBBR. +Arm DEN0006D. It should be used in conjunction with the +:ref:`Firmware Update (FWU)` design document, which implements a specific aspect +of the TBBR. Chain of Trust -------------- @@ -186,7 +187,8 @@ The next step is executed for all the boot loader images. The Trusted Board Boot implementation spans both generic and platform-specific BL1 and BL2 code, and in tool code on the host build machine. The feature is -enabled through use of specific build flags as described in the `User Guide`_. +enabled through use of specific build flags as described in the +:ref:`User Guide`. On the host machine, a tool generates the certificates, which are included in the FIP along with the boot loader images. These certificates are loaded in @@ -201,10 +203,11 @@ Authentication Framework The authentication framework included in TF-A provides support to implement the desired trusted boot sequence. Arm platforms use this framework to -implement the boot requirements specified in the `TBBR-client`_ document. +implement the boot requirements specified in the +`Trusted Board Boot Requirements (TBBR)`_ document. More information about the authentication framework can be found in the -`Auth Framework`_ document. +:ref:`Authentication Framework & Chain of Trust` document. Certificate Generation Tool --------------------------- @@ -221,15 +224,11 @@ directory. The tool resides in the ``tools/cert_create`` directory. It uses OpenSSL SSL library version 1.0.1 or later to generate the X.509 certificates. Instructions -for building and using the tool can be found in the `User Guide`_. +for building and using the tool can be found in the :ref:`User Guide`. -------------- *Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.* -.. _Firmware Update: ../components/firmware-update.rst .. _X.509 v3: https://tools.ietf.org/rfc/rfc5280.txt -.. _User Guide: ../getting_started/user-guide.rst -.. _Auth Framework: auth-framework.rst -.. _TBBR-client: https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a -.. _Trusted Board Boot Requirements (TBBR): `TBBR-client`_ +.. _Trusted Board Boot Requirements (TBBR): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index 9eb7c17e1..d7157690d 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -13,20 +13,20 @@ Modifications consist of: - Defining certain constants (for example #defines). The platform-specific functions and variables are declared in -`include/plat/common/platform.h`_. The firmware provides a default implementation -of variables and functions to fulfill the optional requirements. These -implementations are all weakly defined; they are provided to ease the porting -effort. Each platform port can override them with its own implementation if the -default implementation is inadequate. +``include/plat/common/platform.h``. The firmware provides a default +implementation of variables and functions to fulfill the optional requirements. +These implementations are all weakly defined; they are provided to ease the +porting effort. Each platform port can override them with its own implementation +if the default implementation is inadequate. Some modifications are common to all Boot Loader (BL) stages. Section 2 discusses these in detail. The subsequent sections discuss the remaining modifications for each BL stage in detail. -This document should be read in conjunction with the TF-A `User Guide`_. +This document should be read in conjunction with the TF-A :ref:`User Guide`. -Please refer to the `Platform compatibility policy`_ for the policy regarding -compatibility and deprecation of these porting interfaces. +Please refer to the :ref:`Platform Compatibility Policy` for the policy +regarding compatibility and deprecation of these porting interfaces. Only Arm development platforms (such as FVP and Juno) may use the functions/definitions in ``include/plat/arm/common/`` and the corresponding @@ -98,7 +98,7 @@ Each platform must ensure that a header file of this name is in the system include path with the following constants defined. This will require updating the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. -Platform ports may optionally use the file `include/plat/common/common_def.h`_, +Platform ports may optionally use the file ``include/plat/common/common_def.h``, which provides typical values for some of the constants below. These values are likely to be suitable for all platform ports. @@ -115,8 +115,8 @@ likely to be suitable for all platform ports. - **#define : PLATFORM_STACK_SIZE** Defines the normal stack memory available to each CPU. This constant is used - by `plat/common/aarch64/platform_mp_stack.S`_ and - `plat/common/aarch64/platform_up_stack.S`_. + by ``plat/common/aarch64/platform_mp_stack.S`` and + ``plat/common/aarch64/platform_up_stack.S``. - **define : CACHE_WRITEBACK_GRANULE** @@ -542,7 +542,7 @@ optionally be defined: Maximum number of partition entries required by the platform. This allows control how much memory is allocated for partition entries. The default value is 128. - `For example, define the build flag in platform.mk`_: + For example, define the build flag in ``platform.mk``: PLAT_PARTITION_MAX_ENTRIES := 12 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) @@ -828,7 +828,8 @@ runtime environment. This function can clobber x0 - x8 and must preserve x9 - x29. This function plays a crucial role in the power domain topology framework in -PSCI and details of this can be found in `Power Domain Topology Design`_. +PSCI and details of this can be found in +:ref:`PSCI Power Domain Tree Structure`. Function : plat_core_pos_by_mpidr() ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -844,7 +845,7 @@ case the ``MPIDR`` is invalid, this function returns -1. This function will only be invoked by BL31 after the power domain topology is initialized and can utilize the C runtime environment. For further details about how TF-A represents the power domain topology and how this relates to the linear CPU -index, please refer `Power Domain Topology Design`_. +index, please refer :ref:`PSCI Power Domain Tree Structure`. Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -895,8 +896,8 @@ of the stack allocated to each CPU is specified by the platform defined constant ``PLATFORM_STACK_SIZE``. Common implementations of this function for the UP and MP BL images are -provided in `plat/common/aarch64/platform_up_stack.S`_ and -`plat/common/aarch64/platform_mp_stack.S`_ +provided in ``plat/common/aarch64/platform_up_stack.S`` and +``plat/common/aarch64/platform_mp_stack.S`` Function : plat_get_my_stack() ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -913,8 +914,8 @@ of the stack allocated to each CPU is specified by the platform defined constant ``PLATFORM_STACK_SIZE``. Common implementations of this function for the UP and MP BL images are -provided in `plat/common/aarch64/platform_up_stack.S`_ and -`plat/common/aarch64/platform_mp_stack.S`_ +provided in ``plat/common/aarch64/platform_up_stack.S`` and +``plat/common/aarch64/platform_mp_stack.S`` Function : plat_report_exception() ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -937,12 +938,12 @@ about the way the platform displays its status information. For AArch64, this function receives the exception type as its argument. Possible values for exceptions types are listed in the -`include/common/bl_common.h`_ header file. Note that these constants are not +``include/common/bl_common.h`` header file. Note that these constants are not related to any architectural exception code; they are just a TF-A convention. For AArch32, this function receives the exception mode as its argument. Possible values for exception modes are listed in the -`include/lib/aarch32/arch.h`_ header file. +``include/lib/aarch32/arch.h`` header file. Function : plat_reset_handler() ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -958,7 +959,7 @@ specific errata workarounds could also be implemented here. The API should preserve the values of callee saved registers x19 to x29. The default implementation doesn't do anything. If a platform needs to override -the default implementation, refer to the `Firmware Design`_ for general +the default implementation, refer to the :ref:`Firmware Design` for general guidelines. Function : plat_disable_acp() @@ -1475,8 +1476,8 @@ Boot Loader Stage 2 (BL2) at EL3 When the platform has a non-TF-A Boot ROM it is desirable to jump directly to BL2 instead of TF-A BL1. In this case BL2 is expected to -execute at EL3 instead of executing at EL1. Refer to the `Firmware -Design`_ for more information. +execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design` +document for more information. All mandatory functions of BL2 must be implemented, except the functions bl2_early_platform_setup and bl2_el3_plat_arch_setup, because @@ -1852,6 +1853,8 @@ calculated by the linker then a link time assertion is raised. A compile time assertion is raised if the value of the constant is not aligned to the cache line boundary. +.. _porting_guide_sdei_requirements: + SDEI porting requirements ~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -1936,7 +1939,7 @@ example, a CPU) is at level 0. If the *power domain* node above a CPU is a logical grouping of CPUs that share some state, then level 1 is that group of CPUs (for example, a cluster), and level 2 is a group of clusters (for example, the system). More details on the power domain topology and its -organization can be found in `Power Domain Topology Design`_. +organization can be found in :ref:`PSCI Power Domain Tree Structure`. BL31's platform initialization code exports a pointer to the platform-specific power management operations required for the PSCI implementation to function @@ -2048,13 +2051,13 @@ Function : plat_get_power_domain_tree_desc() [mandatory] This function returns a pointer to the byte array containing the power domain topology tree description. The format and method to construct this array are -described in `Power Domain Topology Design`_. The BL31 PSCI initialization code -requires this array to be described by the platform, either statically or -dynamically, to initialize the power domain topology tree. In case the array -is populated dynamically, then plat_core_pos_by_mpidr() and -plat_my_core_pos() should also be implemented suitably so that the topology -tree description matches the CPU indices returned by these APIs. These APIs -together form the platform interface for the PSCI topology framework. +described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI +initialization code requires this array to be described by the platform, either +statically or dynamically, to initialize the power domain topology tree. In case +the array is populated dynamically, then plat_core_pos_by_mpidr() and +plat_my_core_pos() should also be implemented suitably so that the topology tree +description matches the CPU indices returned by these APIs. These APIs together +form the platform interface for the PSCI topology framework. Function : plat_setup_psci_ops() [mandatory] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -2076,10 +2079,10 @@ pointer with a pointer to BL31's private ``plat_psci_ops`` structure. A description of each member of this structure is given below. Please refer to the Arm FVP specific implementation of these handlers in -`plat/arm/board/fvp/fvp_pm.c`_ as an example. For each PSCI function that the +``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the platform wants to support, the associated operation or operations in this structure must be provided and implemented (Refer section 4 of -`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI +:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI function in a platform port, the operation should be removed from this structure instead of providing an empty implementation. @@ -2367,13 +2370,15 @@ region defined by a base address ``base`` and with a size of ``length`` bytes is protected by ``MEM_PROTECT``. If the region is protected then it must return 0, otherwise it must return a negative number. +.. _porting_guide_imf_in_bl31: + Interrupt Management framework (in BL31) ---------------------------------------- BL31 implements an Interrupt Management Framework (IMF) to manage interrupts generated in either security state and targeted to EL1 or EL2 in the non-secure state or EL3/S-EL1 in the secure state. The design of this framework is -described in the `IMF Design Guide`_ +described in the :ref:`Interrupt Management Framework` A platform should export the following APIs to support the IMF. The following text briefly describes each API and its implementation in Arm standard @@ -2383,7 +2388,7 @@ present in the platform. Arm standard platform layer supports both and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the FVP can be configured to use either GICv2 or GICv3 depending on the build flag ``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in -`User Guide`_ for more details). +:ref:`User Guide` for more details). See also: `Interrupt Controller Abstraction APIs`__. @@ -2405,10 +2410,10 @@ the platform IC uses to signal each type of interrupt supported by the framework from a given security state. This API must be invoked at EL3. The first parameter will be one of the ``INTR_TYPE_*`` values (see -`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the -security state of the originating execution context. The return result is the -bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, -FIQ=2. +:ref:`Interrupt Management Framework`) indicating the target type of the +interrupt, the second parameter is the security state of the originating +execution context. The return result is the bit position in the ``SCR_EL3`` +register of the respective interrupt trap: IRQ=1, FIQ=2. In the case of Arm standard platforms using GICv2, S-EL1 interrupts are configured as FIQs and Non-secure interrupts as IRQs from either security @@ -2792,7 +2797,7 @@ storage access is only required by BL1 and BL2 phases and performed inside the It is mandatory to implement at least one storage driver. For the Arm development platforms the Firmware Image Package (FIP) driver is provided as the default means to load data from storage (see the "Firmware Image Package" -section in the `User Guide`_). The storage layer is described in the header file +section in the :ref:`User Guide`). The storage layer is described in the header file ``include/drivers/io/io_storage.h``. The implementation of the common library is in ``drivers/io/io_storage.c`` and the driver files are located in ``drivers/io/``. @@ -2843,22 +2848,7 @@ amount of open resources per driver. *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* -.. _include/plat/common/platform.h: ../include/plat/common/platform.h -.. _include/plat/arm/common/plat_arm.h: ../include/plat/arm/common/plat_arm.h%5D -.. _User Guide: user-guide.rst -.. _include/plat/common/common_def.h: ../include/plat/common/common_def.h -.. _include/plat/arm/common/arm_def.h: ../include/plat/arm/common/arm_def.h -.. _plat/common/aarch64/platform_mp_stack.S: ../plat/common/aarch64/platform_mp_stack.S -.. _plat/common/aarch64/platform_up_stack.S: ../plat/common/aarch64/platform_up_stack.S -.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 -.. _Power Domain Topology Design: ../design/psci-pd-tree.rst -.. _include/common/bl_common.h: ../include/common/bl_common.h -.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h -.. _Firmware Design: ../design/firmware-design.rst .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf -.. _plat/arm/board/fvp/fvp_pm.c: ../plat/arm/board/fvp/fvp_pm.c -.. _Platform compatibility policy: ../process/platform-compatibility-policy.rst -.. _IMF Design Guide: ../design/interrupt-framework-design.rst .. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html .. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html .. _FreeBSD: https://www.freebsd.org diff --git a/docs/getting_started/psci-lib-integration-guide.rst b/docs/getting_started/psci-lib-integration-guide.rst index 25936d900..1351fff00 100644 --- a/docs/getting_started/psci-lib-integration-guide.rst +++ b/docs/getting_started/psci-lib-integration-guide.rst @@ -437,13 +437,13 @@ The mandatory platform macros are: - PLAT_MAX_PWR_LVL_STATES (optional) - PLAT_PCPU_DATA_SIZE (optional) -The details of these APIs/macros can be found in `Porting Guide`_. +The details of these APIs/macros can be found in the :ref:`Porting Guide`. All platform specific operations for power management are done via ``plat_psci_ops_t`` callbacks registered by the platform when ``plat_setup_psci_ops()`` API is called. The description of each of the callbacks in ``plat_psci_ops_t`` can be found in PSCI section of the -`Porting Guide`_. If any these callbacks are not registered, then the +:ref:`Porting Guide`. If any these callbacks are not registered, then the PSCI API associated with that callback will not be supported by PSCI library. @@ -524,12 +524,12 @@ CPU operations ~~~~~~~~~~~~~~ The CPU operations (cpu_ops) framework implement power down sequence specific -to the CPU and the details of which can be found in the -``CPU specific operations framework`` section of `Firmware Design`_. The TF-A -tree implements the ``cpu_ops`` for various supported CPUs and the EL3 Runtime -Software needs to include the required ``cpu_ops`` in its build. The start and -end of the ``cpu_ops`` descriptors must be exported by the EL3 Runtime Software -via the ``__CPU_OPS_START__`` and ``__CPU_OPS_END__`` linker symbols. +to the CPU and the details of which can be found at +:ref:`firmware_design_cpu_ops_fwk`. The TF-A tree implements the ``cpu_ops`` +for various supported CPUs and the EL3 Runtime Software needs to include the +required ``cpu_ops`` in its build. The start and end of the ``cpu_ops`` +descriptors must be exported by the EL3 Runtime Software via the +``__CPU_OPS_START__`` and ``__CPU_OPS_END__`` linker symbols. The ``cpu_ops`` descriptors also include reset sequences and may include errata workarounds for the CPU. The EL3 Runtime Software can choose to call this @@ -538,11 +538,9 @@ workarounds. -------------- -*Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.* .. _PSCI spec: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf .. _SMCCC: https://silver.arm.com/download/ARM_and_AMBA_Architecture/AR570-DA-80002-r0p0-00rel0/ARM_DEN0028A_SMC_Calling_Convention.pdf .. _PSCI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf .. _PSCI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf -.. _Porting Guide: ./porting-guide.rst -.. _Firmware Design: ../design/firmware-design.rst diff --git a/docs/getting_started/rt-svc-writers-guide.rst b/docs/getting_started/rt-svc-writers-guide.rst index 6c17a1fb4..6a06025ef 100644 --- a/docs/getting_started/rt-svc-writers-guide.rst +++ b/docs/getting_started/rt-svc-writers-guide.rst @@ -21,8 +21,8 @@ independent implementation of services for each group, which are then compiled into the BL31 image. This simplifies the integration of common software from Arm to support `PSCI`_, Secure Monitor for a Trusted OS and SoC specific software. The common runtime services framework ensures that SMC Functions are -dispatched to their respective service implementation - the `Firmware Design`_ -provides details of how this is achieved. +dispatched to their respective service implementation - the +:ref:`Firmware Design` document provides details of how this is achieved. The interface and operation of the runtime services depends heavily on the concepts and definitions described in the `SMCCC`_, in particular SMC Function @@ -79,11 +79,11 @@ handler will be responsible for all SMC Functions within a given service type. Getting started --------------- -TF-A has a `services`_ directory in the source tree under which +TF-A has a ``services`` directory in the source tree under which each owning entity can place the implementation of its runtime service. The -`PSCI`_ implementation is located here in the `lib/psci`_ directory. +`PSCI`_ implementation is located here in the ``lib/psci`` directory. -Runtime service sources will need to include the `runtime_svc.h`_ header file. +Runtime service sources will need to include the ``runtime_svc.h`` header file. Registering a runtime service ----------------------------- @@ -100,7 +100,7 @@ initialization and call handler functions. is also used for diagnostic purposes - ``_start`` and ``_end`` values must be based on the ``OEN_*`` values defined in - `smccc.h`_ + ``smccc.h`` - ``_type`` must be one of ``SMC_TYPE_FAST`` or ``SMC_TYPE_YIELD`` @@ -132,7 +132,7 @@ to ensure that the following conditions are met: #. The ``_type`` is one of ``SMC_TYPE_FAST`` or ``SMC_TYPE_YIELD`` #. ``_setup`` and ``_smch`` routines have been specified -`std_svc_setup.c`_ provides an example of registering a runtime service: +``std_svc_setup.c`` provides an example of registering a runtime service: .. code:: c @@ -296,13 +296,7 @@ provide this information.... -------------- -*Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.* .. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf -.. _Firmware Design: ../design/firmware-design.rst -.. _services: ../../services -.. _lib/psci: ../../lib/psci -.. _runtime_svc.h: ../../include/common/runtime_svc.h -.. _smccc.h: ../../include/lib/smccc.h -.. _std_svc_setup.c: ../../services/std_svc/std_svc_setup.c diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index e540fd06a..c7359ada3 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -22,7 +22,7 @@ the different software components required to boot a Linux system: This document also assumes that the user is familiar with the `FVP models`_ and the different command line options available to launch the model. -This document should be used in conjunction with the `Firmware Design`_. +This document should be used in conjunction with the :ref:`Firmware Design`. Host machine requirements ------------------------- @@ -86,8 +86,8 @@ Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the source, for submission to the project, the source must be in compliance with this style guide. -Additional, project-specific guidelines are defined in the `Trusted Firmware-A -Coding Guidelines`_ document. +Additional, project-specific guidelines are defined in the +:ref:`Coding Style & Guidelines` document. To assist with coding style compliance, the project Makefile contains two targets which both utilise the `checkpatch.pl` script that ships with the Linux @@ -196,7 +196,7 @@ Building TF-A an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may include other runtime services, for example Trusted OS services. A guide to integrate PSCI library with AArch32 EL3 Runtime Software can be found - `here`_. + at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32 image, is not compiled in by default. Refer to the @@ -262,11 +262,11 @@ Common build options - ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when compiling TF-A. Its value must be numeric, and defaults to 8 . See also, *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in - `Firmware Design`_. + :ref:`Firmware Design`. - ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when compiling TF-A. Its value must be a numeric, and defaults to 0. See also, - *Armv8 Architecture Extensions* in `Firmware Design`_. + *Armv8 Architecture Extensions* in :ref:`Firmware Design`. - ``BL2``: This is an optional build option which specifies the path to BL2 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be @@ -479,7 +479,7 @@ Common build options is AArch32. - ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM). - Refer to the `Secure Partition Manager Design guide`_ for more details about + Refer to :ref:`Secure Partition Manager` for more details about this feature. Default is 0. - ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension @@ -527,7 +527,7 @@ Common build options - ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` tool to create certificates as per the Chain of Trust described in - `Trusted Board Boot`_. The build system then calls ``fiptool`` to + :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to include the certificates in the FIP and FWU_FIP. Default value is '0'. Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support @@ -745,8 +745,8 @@ Common build options - ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be isolated on separate memory pages. This is a trade-off between security and memory usage. See "Isolating code and read-only data on separate memory - pages" section in `Firmware Design`_. This flag is disabled by default and - affects all BL images. + pages" section in :ref:`Firmware Design`. This flag is disabled by default + and affects all BL images. - ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. This build option is only valid if ``ARCH=aarch64``. The value should be @@ -784,7 +784,7 @@ Common build options - ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or synchronous, (see "Initializing a BL32 Image" section in - `Firmware Design`_). It can take the value 0 (BL32 is initialized using + :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using synchronous method) or 1 (BL32 is initialized using asynchronous method). Default is 0. @@ -808,14 +808,14 @@ Common build options - ``USE_COHERENT_MEM``: This flag determines whether to include the coherent memory region in the BL memory map or not (see "Use of Coherent memory in - TF-A" section in `Firmware Design`_). It can take the value 1 + TF-A" section in :ref:`Firmware Design`). It can take the value 1 (Coherent memory region is included) or 0 (Coherent memory region is excluded). Default is 1. - ``USE_ROMLIB``: This flag determines whether library at ROM will be used. This feature creates a library of functions to be placed in ROM and thus - reduces SRAM usage. Refer to `Library at ROM`_ for further details. Default - is 0. + reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. + Default is 0. - ``USE_SPINLOCK_CAS``: Setting this build flag to 1 selects the spinlock implementation variant using the ARMv8.1-LSE compare-and-swap instruction. @@ -924,7 +924,7 @@ Arm development platform specific build options SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag. For a better understanding of these options, the Arm development platform memory -map is explained in the `Firmware Design`_. +map is explained in the :ref:`Firmware Design`. Arm CSS platform specific build options ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -978,14 +978,14 @@ Arm FVP platform specific build options The default value is 0. - ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled - to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for + to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for details on HW_CONFIG. By default, this is initialized to a sensible DTS file in ``fdts/`` folder depending on other build options. But some cases, like shifted affinity format for MPIDR, cannot be detected at build time and this option is needed to specify the appropriate DTS file. - ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in - FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is + FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the HW_CONFIG blob instead of the DTS file. This option is useful to override the default HW_CONFIG selected by the build system. @@ -1017,7 +1017,7 @@ optimizations by using ``-O0``. .. warning:: Using ``-O0`` could cause output images to be larger and base addresses might need to be recalculated (see the **Memory layout on Arm development - platforms** section in the `Firmware Design`_). + platforms** section in the :ref:`Firmware Design`). Extra debug options can be passed to the build system by setting ``CFLAGS`` or ``LDFLAGS``: @@ -1058,7 +1058,8 @@ Building the Test Secure Payload The TSP is coupled with a companion runtime service in the BL31 firmware, called the TSPD. Therefore, if you intend to use the TSP, the BL31 image must be recompiled as well. For more information on SPs and SPDs, see the -`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_. +:ref:`Secure-EL1 Payloads and Dispatchers ` section +in the :ref:`Firmware Design` document. First clean the TF-A build directory to get rid of any previous BL31 binary. Then to build the TSP image use: @@ -1176,15 +1177,15 @@ remove operations will automatically overwrite it. The unpack operation will fail if the images already exist at the destination. In that case, use -f or --force to continue. -More information about FIP can be found in the `Firmware Design`_ document. +More information about FIP can be found in the :ref:`Firmware Design` document. Building FIP images with support for Trusted Board Boot ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Trusted Board Boot primarily consists of the following two features: -- Image Authentication, described in `Trusted Board Boot`_, and -- Firmware Update, described in `Firmware Update`_ +- Image Authentication, described in :ref:`Trusted Board Boot`, and +- Firmware Update, described in :ref:`Firmware Update (FWU)` The following steps should be followed to build FIP and (optionally) FWU_FIP images with support for these features: @@ -1250,9 +1251,9 @@ images with support for these features: in the output build directory. #. The optional FWU_FIP contains any additional images to be loaded from - Non-Volatile storage during the `Firmware Update`_ process. To build the - FWU_FIP, any FWU images required by the platform must be specified on the - command line. On Arm development platforms like Juno, these are: + Non-Volatile storage during the :ref:`Firmware Update (FWU)` process. To + build the FWU_FIP, any FWU images required by the platform must be specified + on the command line. On Arm development platforms like Juno, these are: - NS_BL2U. The AP non-secure Firmware Updater image. - SCP_BL2U. The SCP Firmware Update Configuration image. @@ -1731,6 +1732,8 @@ The Trusted Firmware must be compiled in a similar way as for FVP explained above. The process to load binaries to memory is the one explained in `Booting an EL3 payload on Juno`_. +.. _user_guide_run_fvp: + Running the software on FVP --------------------------- @@ -1903,7 +1906,7 @@ Notes: - BL1 is loaded at the start of the Trusted ROM. - The Firmware Image Package is loaded at the start of NOR FLASH0. - The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address - is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_. + is specified via the ``hw_config_addr`` property in ``TB_FW_CONFIG`` for FVP. - The default use-case for the Foundation FVP is to use the ``--gicv3`` option and enable the GICv3 device in the model. Note that without this option, the Foundation FVP defaults to legacy (Versatile Express) memory map which @@ -2204,18 +2207,9 @@ wakeup interrupt from RTC. .. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html .. _Linux master tree: https://github.com/torvalds/linux/tree/master/ .. _Dia: https://wiki.gnome.org/Apps/Dia/Download -.. _here: psci-lib-integration-guide.rst -.. _Trusted Board Boot: ../design/trusted-board-boot.rst -.. _TB_FW_CONFIG for FVP: ../../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts -.. _Secure-EL1 Payloads and Dispatchers: ../design/firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers -.. _Firmware Update: ../components/firmware-update.rst -.. _Firmware Design: ../design/firmware-design.rst .. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git .. _mbed TLS Security Center: https://tls.mbed.org/security .. _Arm's website: `FVP models`_ .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms .. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf -.. _Secure Partition Manager Design guide: ../components/secure-partition-manager-design.rst -.. _`Trusted Firmware-A Coding Guidelines`: ../process/coding-guidelines.rst -.. _Library at ROM: ../components/romlib-design.rst diff --git a/docs/index.rst b/docs/index.rst index 2023ceb1d..268ac4720 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -140,8 +140,9 @@ Functionality further support to be added in a future release. For a full description of functionality and implementation details, please -see the `Firmware Design`_ and supporting documentation. The `Change Log`_ -provides details of changes made since the last release. +see :ref:`Firmware Design` and supporting documentation. The +:ref:`Change Log & Release Notes` provides details of changes made since the +last release. Platforms --------- @@ -242,31 +243,32 @@ Still to come - Ongoing security hardening, optimization and quality improvements. -For a full list of detailed issues in the current code, please see the `Change -Log`_ and the `issue tracker`_. +For a full list of detailed issues in the current code, please see the +:ref:`Change Log & Release Notes` and the `issue tracker`_. Getting started --------------- -See the `User Guide`_ for instructions on how to download, install, build and -use TF-A with the Arm `FVP`_\ s. +See the :ref:`User Guide` for instructions on how to download, install, build +and use TF-A with the Arm `FVP`_\ s. -See the `Firmware Design`_ for information on how TF-A works. +See the :ref:`Firmware Design` for information on how TF-A works. -See the `Porting Guide`_ as well for information about how to use this +See the :ref:`Porting Guide` as well for information about how to use this software on another Armv7-A or Armv8-A platform. -See the `Contributing Guidelines`_ for information on how to contribute to this -project and the `Acknowledgments`_ file for a list of contributors to the -project. +See the :ref:`Contributor's Guide` for information on how to contribute to this +project and the :ref:`Contributor Acknowledgements` file for a list of +contributors to the project. -Contact us +Contact Us ~~~~~~~~~~ We welcome any feedback on TF-A. If you think you have found a security vulnerability, please report this using the process defined in the TF-A -`Security Center`_. For all other feedback, you can use either the -`issue tracker`_ or our `mailing list`_. +:ref:`Security Handling` document. + +For all other feedback, please use the `issue tracker`_ or our `mailing list`_. Arm licensees may contact Arm directly via their partner managers. @@ -294,11 +296,3 @@ Arm licensees may contact Arm directly via their partner managers. .. _trustedfirmware.org: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git .. _issue tracker: https://issues.trustedfirmware.org .. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a -.. _Security Center: ./process/security.rst -.. _license: ./license.rst -.. _Contributing Guidelines: ./process/contributing.rst -.. _Acknowledgments: ./acknowledgements.rst -.. _Firmware Design: ./design/firmware-design.rst -.. _Change Log: ./change-log.rst -.. _User Guide: ./getting_started/user-guide.rst -.. _Porting Guide: ./getting_started/porting-guide.rst diff --git a/docs/license.rst b/docs/license.rst index b62286fa9..2f9704335 100644 --- a/docs/license.rst +++ b/docs/license.rst @@ -3,7 +3,7 @@ License The software is provided under a BSD-3-Clause license (below). Contributions to this project are accepted under the same license with developer sign-off as -described in the :ref:`contributor_guide`. +described in the :ref:`Contributor's Guide`. :: @@ -77,4 +77,4 @@ license text is included in those source files. terms of both licenses. .. _FreeBSD: http://www.freebsd.org -.. _SCC: http://www.simple-cc.org/ \ No newline at end of file +.. _SCC: http://www.simple-cc.org/ diff --git a/docs/plat/socionext-uniphier.rst b/docs/plat/socionext-uniphier.rst index 82b9b503a..964dd1db9 100644 --- a/docs/plat/socionext-uniphier.rst +++ b/docs/plat/socionext-uniphier.rst @@ -8,10 +8,11 @@ UniPhier SoC family implements its internal boot ROM, which loads 64KB [1]_ image from a non-volatile storage to the on-chip SRAM, and jumps over to it. TF-A provides a special mode, BL2-AT-EL3, which enables BL2 to execute at EL3. It is useful for platforms with non-TF-A boot ROM, like UniPhier. Here, a -problem is BL2 does not fit in the 64KB limit if `Trusted Board Boot`_ (TBB) -is enabled. To solve this issue, Socionext provides a first stage loader -called `UniPhier BL`_. This loader runs in the on-chip SRAM, initializes the -DRAM, expands BL2 there, and hands the control over to it. Therefore, all images +problem is BL2 does not fit in the 64KB limit if +:ref:`Trusted Board Boot (TBB) ` is enabled. +To solve this issue, Socionext provides a first stage loader called +`UniPhier BL`_. This loader runs in the on-chip SRAM, initializes the DRAM, +expands BL2 there, and hands the control over to it. Therefore, all images of TF-A run in DRAM. The UniPhier platform works with/without TBB. See below for the build process @@ -50,7 +51,7 @@ Boot Flow 4. BL31, BL32, and BL33 - They all run in the DRAM. See `Firmware Design`_ for details. + They all run in the DRAM. See :ref:`Firmware Design` for details. Basic Build @@ -79,7 +80,7 @@ Optional features - Trusted Board Boot `mbed TLS`_ is needed as the cryptographic and image parser modules. - Refer to the `User Guide`_ for the appropriate version of mbed TLS. + Refer to the :ref:`User Guide` for the appropriate version of mbed TLS. To enable TBB, add the following options to the build command:: @@ -109,9 +110,6 @@ Optional features .. [1] Some SoCs can load 80KB, but the software implementation must be aligned to the lowest common denominator. -.. _Trusted Board Boot: ../trusted-board-boot.rst .. _UniPhier BL: https://github.com/uniphier/uniphier-bl -.. _Firmware Design: ../firmware-design.rst .. _U-Boot: https://www.denx.de/wiki/U-Boot .. _mbed TLS: https://tls.mbed.org/ -.. _User Guide: ../user-guide.rst diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst index 66b282c91..fdb702ffe 100644 --- a/docs/process/contributing.rst +++ b/docs/process/contributing.rst @@ -13,8 +13,8 @@ Getting Started raise a separate `issue`_ for this and ensure that the changes that include Third Party IP are made on a separate topic branch. -- Clone `Trusted Firmware-A`_ on your own machine as suggested on the - `User Guide`_. +- Clone `Trusted Firmware-A`_ on your own machine as suggested in the + :ref:`User Guide`. - Create a local topic branch based on the `Trusted Firmware-A`_ ``master`` branch. @@ -23,11 +23,11 @@ Making Changes - Make commits of logical units. See these general `Git guidelines`_ for contributing to a project. -- Follow the `Coding Guidelines`_. +- Follow the :ref:`Coding Style & Guidelines`. - Use the checkpatch.pl script provided with the Linux source tree. A Makefile target is provided for convenience (see the "Checking source code - style" section in the `User Guide`_). + style" section in the :ref:`User Guide`). - Keep the commits on topic. If you need to fix another bug or make another enhancement, please create a separate `issue`_ and address it on a separate @@ -38,12 +38,12 @@ Making Changes an `issue`_, include a reference. - Where appropriate, please update the documentation. - - Consider whether the `User Guide`_, `Porting Guide`_, `Firmware Design`_ - or other in-source documentation needs updating. + - Consider whether the :ref:`User Guide`, :ref:`Porting Guide`, + :ref:`Firmware Design` or other in-source documentation needs updating. - Ensure that each changed file has the correct copyright and license information. Files that entirely consist of contributions to this project should have a copyright notice and BSD-3-Clause SPDX license - identifier of the form as shown in `license.rst`_. Files that contain + identifier of the form as shown in :ref:`license`. Files that contain changes to imported Third Party IP files should retain their original copyright and license notices. For significant contributions you may add your own copyright notice in following format: @@ -57,13 +57,13 @@ Making Changes your company name. - If you are submitting new files that you intend to be the technical sub-maintainer for (for example, a new platform port), then also update - the `Maintainers`_ file. + the :ref:`maintainers` file. - For topics with multiple commits, you should make all documentation changes (and nothing else) in the last commit of the series. Otherwise, include the documentation changes within the single commit. - Please test your changes. As a minimum, ensure that Linux boots on the - Foundation FVP. See `Running the software on FVP`_ for more information. For + Foundation FVP. See :ref:`user_guide_run_fvp` for more information. For more extensive testing, consider running the `TF-A Tests`_ against your patches. @@ -75,13 +75,14 @@ Submitting Changes ``Signed-off-by:`` and ``Author:`` lines must match. If anyone else contributes to the commit, they must also add their own ``Signed-off-by:`` line. By adding this line the contributor certifies the contribution is made - under the terms of the `Developer Certificate of Origin (DCO)`_. + under the terms of the + :download:`Developer Certificate of Origin <../../dco.txt>`. More details may be found in the `Gerrit Signed-off-by Lines guidelines`_. - Ensure that each commit also has a unique ``Change-Id:`` line. If you have cloned the repository with the "`Clone with commit-msg hook`" clone method - (as advised on the `User Guide`_), this should already be the case. + (as advised on the :ref:`User Guide`), this should already be the case. More details may be found in the `Gerrit Change-Ids documentation`_. @@ -89,22 +90,22 @@ Submitting Changes targeting the ``integration`` branch. - The changes will then undergo further review and testing by the - `Maintainers`_. Any review comments will be made directly on your patch. - This may require you to do some rework. + :ref:`maintainers`. Any review comments will be made directly on your + patch. This may require you to do some rework. Refer to the `Gerrit Uploading Changes documentation`_ for more details. -- When the changes are accepted, the `Maintainers`_ will integrate them. +- When the changes are accepted, the :ref:`maintainers` will integrate them. - - Typically, the `Maintainers`_ will merge the changes into the + - Typically, the :ref:`maintainers` will merge the changes into the ``integration`` branch. - If the changes are not based on a sufficiently-recent commit, or if they - cannot be automatically rebased, then the `Maintainers`_ may rebase it on - the ``master`` branch or ask you to do so. + cannot be automatically rebased, then the :ref:`maintainers` may rebase it + on the ``master`` branch or ask you to do so. - After final integration testing, the changes will make their way into the ``master`` branch. If a problem is found during integration, the merge commit will be removed from the ``integration`` branch and the - `Maintainers`_ will ask you to create a new patch set to resolve the + :ref:`maintainers` will ask you to create a new patch set to resolve the problem. Binary Components @@ -132,15 +133,6 @@ Binary Components .. _issue: https://developer.trustedfirmware.org/project/board/1/ .. _Trusted Firmware-A: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git .. _Git guidelines: http://git-scm.com/book/ch5-2.html -.. _Coding Guidelines: ./coding-guidelines.rst -.. _User Guide: ../getting_started/user-guide.rst -.. _Porting Guide: ../getting_started/porting-guide.rst -.. _Firmware Design: ../design/firmware-design.rst -.. _license.rst: ../license.rst -.. _Acknowledgements: ../acknowledgements.rst -.. _Maintainers: ../maintainers.rst -.. _Running the software on FVP: ../getting_started/user-guide.rst#user-content-running-the-software-on-fvp -.. _Developer Certificate of Origin (DCO): ../../dco.txt .. _Gerrit Uploading Changes documentation: https://review.trustedfirmware.org/Documentation/user-upload.html .. _Gerrit Signed-off-by Lines guidelines: https://review.trustedfirmware.org/Documentation/user-signedoffby.html .. _Gerrit Change-Ids documentation: https://review.trustedfirmware.org/Documentation/user-changeid.html diff --git a/docs/process/faq.rst b/docs/process/faq.rst index 6aa04f0a8..2c3658480 100644 --- a/docs/process/faq.rst +++ b/docs/process/faq.rst @@ -37,7 +37,7 @@ This can vary a lot, depending on: conflict between the topics. * If there is a code freeze in place in preparation for the release. Please - refer the `release information`_ for more details. + refer the :ref:`Release Processes` document for more details. * The workload of the TF maintainers. @@ -55,9 +55,9 @@ receiving patches that will not be merged into the release. In this case, the patches will be merged onto ``integration``, which will temporarily diverge from the release branch. The ``integration`` branch will be rebased onto ``master`` after the release, and then ``master`` will be fast-forwarded to ``integration`` -1-2 days later. This whole process could take up 4 weeks. Please refer the -`release information`_ for code freeze dates. The TF maintainers will inform the -patch owner if this is going to happen. +1-2 days later. This whole process could take up 4 weeks. Please refer to the +:ref:`Release Processes` document for code freeze dates. The TF maintainers +will inform the patch owner if this is going to happen. It is OK to create a patch based on commits that are only available in ``integration`` or another patch set, rather than ``master``. There is a risk @@ -73,7 +73,10 @@ but would be after the CI has been transitioned to `trustedfirmware.org`_. Please refer to https://github.com/ARM-software/tf-issues/issues/681 for more details on the timelines. -.. _release information: release-information.rst +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* + .. _Gerrit Upload Patch Set documentation: https://review.trustedfirmware.org/Documentation/intro-user.html#upload-patch-set .. _Gerrit Replace Changes documentation: https://review.trustedfirmware.org/Documentation/user-upload.html#push_replace .. _trustedfirmware.org: https://www.trustedfirmware.org/ diff --git a/docs/process/platform-compatibility-policy.rst b/docs/process/platform-compatibility-policy.rst index a11ba3860..be1f9bac3 100644 --- a/docs/process/platform-compatibility-policy.rst +++ b/docs/process/platform-compatibility-policy.rst @@ -11,7 +11,7 @@ Platform compatibility policy ----------------------------- Platform compatibility is mainly affected by changes to Platform APIs (as -documented in the `Porting Guide`_), driver APIs (like the GICv3 drivers) or +documented in the :ref:`Porting Guide`), driver APIs (like the GICv3 drivers) or library interfaces (like xlat_table library). The project will try to maintain compatibility for upstream platforms. Due to evolving requirements and enhancements, there might be changes affecting platform compatibility which @@ -20,7 +20,7 @@ introduced to replace it. In case the migration to the new interface is trivial, the contributor of the change is expected to make good effort to migrate the upstream platforms to the new interface. -The deprecated interfaces are listed inside `Release information`_ as well as +The deprecated interfaces are listed inside :ref:`Release Processes` as well as the release after which each one will be removed. When an interface is deprecated, the page must be updated to indicate the release after which the interface will be removed. This must be at least 1 full release cycle in future. @@ -33,6 +33,4 @@ the deprecated interface. *Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.* -.. _Porting Guide: ../getting_started/porting-guide.rst -.. _Release information: ./release-information.rst#removal-of-deprecated-interfaces .. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a diff --git a/docs/process/release-information.rst b/docs/process/release-information.rst index b81d42d59..e264e51ad 100644 --- a/docs/process/release-information.rst +++ b/docs/process/release-information.rst @@ -42,9 +42,9 @@ depending on project requirement and partner feedback. Removal of Deprecated Interfaces -------------------------------- -As mentioned in the `Platform compatibility policy`_, this is a live document -cataloging all the deprecated interfaces in TF-A project and the Release version -after which it will be removed. +As mentioned in the :ref:`Platform Compatibility Policy`, this is a live +document cataloging all the deprecated interfaces in TF-A project and the +Release version after which it will be removed. +--------------------------------+-------------+---------+---------------------------------------------------------+ | Interface | Deprecation | Removed | Comments | @@ -54,7 +54,7 @@ after which it will be removed. | Legacy Console API | Jan '18 | v2.1 | Deprecated in favour of ``MULTI_CONSOLE_API`` | +--------------------------------+-------------+---------+---------------------------------------------------------+ | Weak default | Oct '18 | v2.1 | The default implementations are defined in | -| ``plat_crash_console_*`` | | | `crash_console_helpers.S`_. The platforms have to | +| ``plat_crash_console_*`` | | | ``crash_console_helpers.S``. The platforms have to | | APIs | | | define ``plat_crash_console_*``. | +--------------------------------+-------------+---------+---------------------------------------------------------+ | ``finish_console_register`` | Oct '18 | v2.1 | The old version of the macro is deprecated. See commit | @@ -74,9 +74,9 @@ after which it will be removed. | Makefile in ``INCLUDES``. | | | header files. More information in commit 09d40e0e0828_. | +--------------------------------+-------------+---------+---------------------------------------------------------+ +-------------- + *Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.* -.. _Platform compatibility policy: platform-compatibility-policy.rst -.. _crash_console_helpers.S: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/common/aarch64/crash_console_helpers.S .. _cc5859c: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=cc5859ca19ff546c35eb0331000dae090b6eabcf .. _09d40e0e0828: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=09d40e0e08283a249e7dce0e106c07c5141f9b7e diff --git a/docs/process/security-hardening.rst b/docs/process/security-hardening.rst index e2c68b8fe..1a5524fd8 100644 --- a/docs/process/security-hardening.rst +++ b/docs/process/security-hardening.rst @@ -9,7 +9,7 @@ Build options ------------- Several build options can be used to check for security issues. Refer to the -`user guide`_ for detailed information on the specific build options. +:ref:`User Guide` for detailed information on the specific build options. - The ``BRANCH_PROTECTION`` build flag can be used to enable Pointer Authentication and Branch Target Identification. @@ -53,6 +53,6 @@ Several build options can be used to check for security issues. Refer to the NB: The ``Werror`` flag is enabled by default in TF-A and can be disabled by setting the ``E`` build flag to 0. -*Copyright (c) 2019, Arm Limited. All rights reserved.* +-------------- -.. _user guide: ../getting_started/user-guide.rst +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/process/security.rst b/docs/process/security.rst index 94eb9c3bf..c3935daa1 100644 --- a/docs/process/security.rst +++ b/docs/process/security.rst @@ -38,9 +38,11 @@ Please include: - Any additional software or tools required -We recommend using `this PGP/GPG key`_ for encrypting the information. This key -is also available at http://keyserver.pgp.com and LDAP port 389 of the same -server. The fingerprint for this key is: +We recommend using :download:`this PGP/GPG key <./security-reporting.asc>` for +encrypting the information. This key is also available at +http://keyserver.pgp.com and LDAP port 389 of the same server. + +The fingerprint for this key is: :: @@ -59,7 +61,7 @@ code. Attribution ----------- -We will name and thank you in the ``change-log.rst`` distributed with the source +We will name and thank you in the :ref:`Change Log & Release Notes` distributed with the source code and in any published security advisory. Security Advisories @@ -68,38 +70,43 @@ Security Advisories +-----------+------------------------------------------------------------------+ | ID | Title | +===========+==================================================================+ -| `TFV-1`_ | Malformed Firmware Update SMC can result in copy of unexpectedly | +| |TFV-1| | Malformed Firmware Update SMC can result in copy of unexpectedly | | | large data into secure memory | +-----------+------------------------------------------------------------------+ -| `TFV-2`_ | Enabled secure self-hosted invasive debug interface can allow | +| |TFV-2| | Enabled secure self-hosted invasive debug interface can allow | | | normal world to panic secure world | +-----------+------------------------------------------------------------------+ -| `TFV-3`_ | RO memory is always executable at AArch64 Secure EL1 | +| |TFV-3| | RO memory is always executable at AArch64 Secure EL1 | +-----------+------------------------------------------------------------------+ -| `TFV-4`_ | Malformed Firmware Update SMC can result in copy or | +| |TFV-4| | Malformed Firmware Update SMC can result in copy or | | | authentication of unexpected data in secure memory in AArch32 | | | state | +-----------+------------------------------------------------------------------+ -| `TFV-5`_ | Not initializing or saving/restoring PMCR_EL0 can leak secure | +| |TFV-5| | Not initializing or saving/restoring PMCR_EL0 can leak secure | | | world timing information | +-----------+------------------------------------------------------------------+ -| `TFV-6`_ | Trusted Firmware-A exposure to speculative processor | +| |TFV-6| | Trusted Firmware-A exposure to speculative processor | | | vulnerabilities using cache timing side-channels | +-----------+------------------------------------------------------------------+ -| `TFV-7`_ | Trusted Firmware-A exposure to cache speculation vulnerability | +| |TFV-7| | Trusted Firmware-A exposure to cache speculation vulnerability | | | Variant 4 | +-----------+------------------------------------------------------------------+ -| `TFV-8`_ | Not saving x0 to x3 registers can leak information from one | +| |TFV-8| | Not saving x0 to x3 registers can leak information from one | | | Normal World SMC client to another | +-----------+------------------------------------------------------------------+ .. _issue tracker: https://developer.trustedfirmware.org/project/board/1/ .. _this PGP/GPG key: security-reporting.asc -.. _TFV-1: ../security_advisories/security-advisory-tfv-1.rst -.. _TFV-2: ../security_advisories/security-advisory-tfv-2.rst -.. _TFV-3: ../security_advisories/security-advisory-tfv-3.rst -.. _TFV-4: ../security_advisories/security-advisory-tfv-4.rst -.. _TFV-5: ../security_advisories/security-advisory-tfv-5.rst -.. _TFV-6: ../security_advisories/security-advisory-tfv-6.rst -.. _TFV-7: ../security_advisories/security-advisory-tfv-7.rst -.. _TFV-8: ../security_advisories/security-advisory-tfv-8.rst + +.. |TFV-1| replace:: :ref:`Advisory TFV-1 (CVE-2016-10319)` +.. |TFV-2| replace:: :ref:`Advisory TFV-2 (CVE-2017-7564)` +.. |TFV-3| replace:: :ref:`Advisory TFV-3 (CVE-2017-7563)` +.. |TFV-4| replace:: :ref:`Advisory TFV-4 (CVE-2017-9607)` +.. |TFV-5| replace:: :ref:`Advisory TFV-5 (CVE-2017-15031)` +.. |TFV-6| replace:: :ref:`Advisory TFV-6 (CVE-2017-5753, CVE-2017-5715, CVE-2017-5754)` +.. |TFV-7| replace:: :ref:`Advisory TFV-7 (CVE-2018-3639)` +.. |TFV-8| replace:: :ref:`Advisory TFV-8 (CVE-2018-19440)` + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* -- cgit v1.2.3 From 8cc36aec9122305f3537fbaa369d0c72ed324314 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Mon, 23 Sep 2019 15:40:21 +0000 Subject: doc: De-duplicate readme and license files The readme.rst and license.rst files in the project root overlap with the index.rst and license.rst files in the docs/ folder. We need to use the latter when building the documentation, as Sphinx requires all included files to be under a common root. However, the files in the root are currently used by the cgit and Github viewers. Using symlinks in Git presents some difficulties so the best course of action is likely to leave these files but in stub form. The license.rst file in the root will simply tell the reader to refer to docs/license.rst. The readme.rst file will contain a small amount of content that is derived from the docs/index.rst file, so that the Github main page will have something valid to show, but it will also contain a link to the full documentation on ReadTheDocs. Change-Id: I6dc46f08777e8d7ecb32ca7afc07a28486c9f77a Signed-off-by: Paul Beesley --- docs/index.rst | 11 +- license.rst | 39 +------ readme.rst | 341 ++++----------------------------------------------------- 3 files changed, 27 insertions(+), 364 deletions(-) diff --git a/docs/index.rst b/docs/index.rst index 268ac4720..4f0f6ef79 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -43,10 +43,9 @@ states. Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from TF-A. -Arm will continue development in collaboration with interested parties to -provide a full reference implementation of Secure Monitor code and Arm standards -to the benefit of all developers working with Armv7-A and Armv8-A TrustZone -technology. +In collaboration with interested parties, we will continue to enhance |TF-A| +with reference implementations of Arm standards to benefit developers working +with Armv7-A and Armv8-A TrustZone technology. Functionality ------------- @@ -133,8 +132,8 @@ Functionality The use of pointer authentication in the normal world is enabled whenever architectural support is available, without the need for additional build flags. Use of pointer authentication in the secure world remains an - experimental configuration at this time and requires the ``ENABLE_PAUTH`` - build flag to be set. + experimental configuration at this time and requires the + ``BRANCH_PROTECTION`` option to be set to non-zero. - Position-Independent Executable (PIE) support. Initially for BL31 only, with further support to be added in a future release. diff --git a/license.rst b/license.rst index 974313467..3ec3b74f9 100644 --- a/license.rst +++ b/license.rst @@ -1,38 +1 @@ -Copyright (c) [XXXX-]YYYY, . All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -- Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -- Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - -- Neither the name of Arm nor the names of its contributors may be used to - endorse or promote products derived from this software without specific prior - written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - --------------- - -.. note:: - Individual files contain the following tag instead of the full license text. - -:: - - SPDX-License-Identifier: BSD-3-Clause - -This enables machine processing of license information based on the SPDX -License Identifiers that are here available: http://spdx.org/licenses/ +See docs/license.rst diff --git a/readme.rst b/readme.rst index b5038084d..f8f8daf8d 100644 --- a/readme.rst +++ b/readme.rst @@ -1,309 +1,35 @@ -Trusted Firmware-A - version 2.1 -================================ +Trusted Firmware-A +================== -.. section-numbering:: - :suffix: . +Trusted Firmware-A is a reference implementation of secure world software for +`Arm A-Profile architectures`_ (Armv8-A and Armv7-A), including an +Exception Level 3 (EL3)`Secure Monitor`_. It provides a suitable starting point +for productization of secure world boot and runtime firmware, in either the +|AArch32| or |AArch64| execution states. -.. contents:: +|TF-A| implements Arm interface standards, including: -Trusted Firmware-A (TF-A) provides a reference implementation of secure world -software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing -at Exception Level 3 (EL3). It implements various Arm interface standards, -such as: - -- The `Power State Coordination Interface (PSCI)`_ +- `Power State Coordination Interface (PSCI)`_ - `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)`_ - `SMC Calling Convention`_ - `System Control and Management Interface (SCMI)`_ - `Software Delegated Exception Interface (SDEI)`_ -Where possible, the code is designed for reuse or porting to other Armv7-A and -Armv8-A model and hardware platforms. +The code is designed to be portable and reusable across hardware platforms and +software models that are based on the Armv8-A and Armv7-A architectures. -This release provides a suitable starting point for productization of secure -world boot and runtime firmware, in either the AArch32 or AArch64 execution -states. +In collaboration with interested parties, we will continue to enhance |TF-A| +with reference implementations of Arm standards to benefit developers working +with Armv7-A and Armv8-A TrustZone technology. Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from TF-A. -Arm will continue development in collaboration with interested parties to -provide a full reference implementation of Secure Monitor code and Arm standards -to the benefit of all developers working with Armv7-A and Armv8-A TrustZone -technology. - -Documentation contents ----------------------- - -The `Trusted Firmware-A Documentation Contents`_ page contains an overview of -the documentation that is available, with links to facilitate easier browsing. - -License -------- - -The software is provided under a BSD-3-Clause `license`_. Contributions to this -project are accepted under the same license with developer sign-off as -described in the `Contributing Guidelines`_. - -This project contains code from other projects as listed below. The original -license text is included in those source files. - -- The libc source code is derived from `FreeBSD`_ and `SCC`_. FreeBSD uses - various BSD licenses, including BSD-3-Clause and BSD-2-Clause. The SCC code - is used under the BSD-3-Clause license with the author's permission. - -- The libfdt source code is disjunctively dual licensed - (GPL-2.0+ OR BSD-2-Clause). It is used by this project under the terms of - the BSD-2-Clause license. Any contributions to this code must be made under - the terms of both licenses. - -- The LLVM compiler-rt source code is disjunctively dual licensed - (NCSA OR MIT). It is used by this project under the terms of the NCSA - license (also known as the University of Illinois/NCSA Open Source License), - which is a permissive license compatible with BSD-3-Clause. Any - contributions to this code must be made under the terms of both licenses. - -- The zlib source code is licensed under the Zlib license, which is a - permissive license compatible with BSD-3-Clause. - -- Some STMicroelectronics platform source code is disjunctively dual licensed - (GPL-2.0+ OR BSD-3-Clause). It is used by this project under the terms of the - BSD-3-Clause license. Any contributions to this code must be made under the - terms of both licenses. - -Functionality -------------- - -- Initialization of the secure world, for example exception vectors, control - registers and interrupts for the platform. - -- Library support for CPU specific reset and power down sequences. This - includes support for errata workarounds and the latest Arm DynamIQ CPUs. - -- Drivers to enable standard initialization of Arm System IP, for example - Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI), - Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone - Controller (TZC). - -- A generic `SCMI`_ driver to interface with conforming power controllers, for - example the Arm System Control Processor (SCP). - -- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling - Convention`_ using an EL3 runtime services framework. - -- `PSCI`_ library support for CPU, cluster and system power management - use-cases. - This library is pre-integrated with the AArch64 EL3 Runtime Software, and - is also suitable for integration with other AArch32 EL3 Runtime Software, - for example an AArch32 Secure OS. - -- A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate `PSCI`_ library - integration with AArch32 EL3 Runtime Software. - -- Secure Monitor library code such as world switching, EL1 context management - and interrupt routing. - When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the - AArch64 EL3 Runtime Software must be integrated with a Secure Payload - Dispatcher (SPD) component to customize the interaction with the SP. - -- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP - interaction with PSCI. - -- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_ - and `Trusty Secure OS`_. - -- A Trusted Board Boot implementation, conforming to all mandatory TBBR - requirements. This includes image authentication, Firmware Update (or - recovery mode), and packaging of the various firmware images into a - Firmware Image Package (FIP). - -- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of - its hardware Root of Trust and crypto acceleration services. - -- Reliability, Availability, and Serviceability (RAS) functionality, including - - - A Secure Partition Manager (SPM) to manage Secure Partitions in - Secure-EL0, which can be used to implement simple management and - security services. - - - An SDEI dispatcher to route interrupt-based SDEI events. - - - An Exception Handling Framework (EHF) that allows dispatching of EL3 - interrupts to their registered handlers, to facilitate firmware-first - error handling. - -- A dynamic configuration framework that enables each of the firmware images - to be configured at runtime if required by the platform. It also enables - loading of a hardware configuration (for example, a kernel device tree) - as part of the FIP, to be passed through the firmware stages. - -- Support for alternative boot flows, for example to support platforms where - the EL3 Runtime Software is loaded using other firmware or a separate - secure system processor, or where a non-TF-A ROM expects BL2 to be loaded - at EL3. - -- Support for the GCC, LLVM and Arm Compiler 6 toolchains. - -- Support for combining several libraries into a "romlib" image that may be - shared across images to reduce memory footprint. The romlib image is stored - in ROM but is accessed through a jump-table that may be stored - in read-write memory, allowing for the library code to be patched. - -- A prototype implementation of a Secure Partition Manager (SPM) that is based - on the SPCI Alpha 1 and SPRT draft specifications. - -- Support for ARMv8.3 pointer authentication in the normal and secure worlds. - The use of pointer authentication in the normal world is enabled whenever - architectural support is available, without the need for additional build - flags. Use of pointer authentication in the secure world remains an - experimental configuration at this time and requires the - ``BRANCH_PROTECTION`` option to be set to non-zero. - -- Position-Independent Executable (PIE) support. Initially for BL31 only, with - further support to be added in a future release. - -For a full description of functionality and implementation details, please -see the `Firmware Design`_ and supporting documentation. The `Change Log`_ -provides details of changes made since the last release. - -Platforms +Read More --------- -Various AArch32 and AArch64 builds of this release have been tested on r0, r1 -and r2 variants of the `Juno Arm Development Platform`_. - -The latest version of the AArch64 build of TF-A has been tested on the following -Arm FVPs without shifted affinities, and that do not support threaded CPU cores -(64-bit host machine only). - -The FVP models used are Version 11.6 Build 45, unless otherwise stated. - -- ``FVP_Base_AEMv8A-AEMv8A`` -- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` -- ``FVP_Base_RevC-2xAEMv8A`` -- ``FVP_Base_Cortex-A32x4`` -- ``FVP_Base_Cortex-A35x4`` -- ``FVP_Base_Cortex-A53x4`` -- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` -- ``FVP_Base_Cortex-A55x4`` -- ``FVP_Base_Cortex-A57x1-A53x1`` -- ``FVP_Base_Cortex-A57x2-A53x4`` -- ``FVP_Base_Cortex-A57x4-A53x4`` -- ``FVP_Base_Cortex-A57x4`` -- ``FVP_Base_Cortex-A72x4-A53x4`` -- ``FVP_Base_Cortex-A72x4`` -- ``FVP_Base_Cortex-A73x4-A53x4`` -- ``FVP_Base_Cortex-A73x4`` -- ``FVP_Base_Cortex-A75x4`` -- ``FVP_Base_Cortex-A76x4`` -- ``FVP_Base_Cortex-A76AEx4`` -- ``FVP_Base_Cortex-A76AEx8`` -- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) -- ``FVP_Base_Neoverse-N1x4`` -- ``FVP_CSS_SGI-575`` (Version 11.3 build 42) -- ``FVP_CSS_SGM-775`` (Version 11.3 build 42) -- ``FVP_RD_E1Edge`` (Version 11.3 build 42) -- ``FVP_RD_N1Edge`` -- ``Foundation_Platform`` - -The latest version of the AArch32 build of TF-A has been tested on the following -Arm FVPs without shifted affinities, and that do not support threaded CPU cores -(64-bit host machine only). - -- ``FVP_Base_AEMv8A-AEMv8A`` -- ``FVP_Base_Cortex-A32x4`` - -NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities. - -The Foundation FVP can be downloaded free of charge. The Base FVPs can be -licensed from Arm. See the `Arm FVP website`_. - -All the above platforms have been tested with `Linaro Release 18.04`_. - -This release also contains the following platform support: - -- Allwinner sun50i (A64, H5, and H6) SoCs -- Amlogic Meson S905 (GXBB) -- Amlogic Meson S905x (GXL) -- Arm Juno Software Development Platform -- Arm Neoverse N1 System Development Platform (N1SDP) -- Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP -- Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP -- Arm SGI-575 and SGM-775 -- Arm Versatile Express FVP -- HiKey, HiKey960 and Poplar boards -- Intel Stratix 10 SoC FPGA -- Marvell Armada 3700 and 8K -- MediaTek MT6795 and MT8173 SoCs -- NVIDIA T132, T186 and T210 SoCs -- NXP QorIQ LS1043A, i.MX8MM, i.MX8MQ, i.MX8QX, i.MX8QM and i.MX7Solo WaRP7 -- QEMU -- Raspberry Pi 3 -- Renesas R-Car Generation 3 -- RockChip RK3328, RK3368 and RK3399 SoCs -- Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs -- STMicroelectronics STM32MP1 -- Texas Instruments K3 SoCs -- Xilinx Versal and Zynq UltraScale + MPSoC - -Still to come -------------- - -- Support for additional platforms. - -- Refinements to Position Independent Executable (PIE) support. - -- Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT - specifications continue to evolve. - -- Documentation enhancements. - -- Ongoing support for new architectural features, CPUs and System IP. - -- Ongoing support for new Arm system architecture specifications. - -- Ongoing security hardening, optimization and quality improvements. - -For a full list of detailed issues in the current code, please see the `Change -Log`_ and the `issue tracker`_. - -Getting started ---------------- - -See the `User Guide`_ for instructions on how to download, install, build and -use TF-A with the Arm `FVP`_\ s. - -See the `Firmware Design`_ for information on how TF-A works. - -See the `Porting Guide`_ as well for information about how to use this -software on another Armv7-A or Armv8-A platform. - -See the `Contributing Guidelines`_ for information on how to contribute to this -project and the `Acknowledgments`_ file for a list of contributors to the -project. - -Contact us -~~~~~~~~~~ - -We welcome any feedback on TF-A. If you think you have found a security -vulnerability, please report this using the process defined in the TF-A -`Security Center`_. For all other feedback, you can use either the -`issue tracker`_ or our `mailing list`_. - -Arm licensees may contact Arm directly via their partner managers. - -Security advisories -------------------- - -- `Security Advisory TFV-1`_ -- `Security Advisory TFV-2`_ -- `Security Advisory TFV-3`_ -- `Security Advisory TFV-4`_ -- `Security Advisory TFV-5`_ -- `Security Advisory TFV-6`_ -- `Security Advisory TFV-7`_ -- `Security Advisory TFV-8`_ - +To find out more about Trusted Firmware-A, please `view the full documentation`_ +that is available through `trustedfirmware.org`_. -------------- @@ -319,32 +45,7 @@ Security advisories .. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf .. _Software Delegated Exception Interface (SDEI): SDEI_ .. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf -.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php -.. _Arm FVP website: FVP_ -.. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms -.. _Linaro Release 18.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease18.04 -.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os -.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary -.. _Trusty Secure OS: https://source.android.com/security/trusty -.. _trustedfirmware.org: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git -.. _issue tracker: https://developer.trustedfirmware.org/project/board/1/ -.. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a -.. _Security Center: ./docs/process/security.rst -.. _license: ./license.rst -.. _Contributing Guidelines: ./docs/process/contributing.rst -.. _Acknowledgments: ./docs/acknowledgements.rst -.. _Firmware Design: ./docs/design/firmware-design.rst -.. _Change Log: ./docs/change-log.rst -.. _User Guide: ./docs/getting_started/user-guide.rst -.. _Porting Guide: ./docs/getting_started/porting-guide.rst -.. _FreeBSD: http://www.freebsd.org -.. _SCC: http://www.simple-cc.org/ -.. _Security Advisory TFV-1: ./docs/security_advisories/security-advisory-tfv-1.rst -.. _Security Advisory TFV-2: ./docs/security_advisories/security-advisory-tfv-2.rst -.. _Security Advisory TFV-3: ./docs/security_advisories/security-advisory-tfv-3.rst -.. _Security Advisory TFV-4: ./docs/security_advisories/security-advisory-tfv-4.rst -.. _Security Advisory TFV-5: ./docs/security_advisories/security-advisory-tfv-5.rst -.. _Security Advisory TFV-6: ./docs/security_advisories/security-advisory-tfv-6.rst -.. _Security Advisory TFV-7: ./docs/security_advisories/security-advisory-tfv-7.rst -.. _Security Advisory TFV-8: ./docs/security_advisories/security-advisory-tfv-8.rst -.. _Trusted Firmware-A Documentation Contents: ./docs/contents.rst +.. _Arm A-Profile architectures: https://developer.arm.com/architectures/cpu-architecture/a-profile +.. _view the full documentation: https://www.trustedfirmware.org/docs/tf-a +.. _trustedfirmware.org: http://www.trustedfirmware.org + -- cgit v1.2.3 From 862c764ada876aa1be24bdef00656bcc386ebdca Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Mon, 7 Oct 2019 10:04:48 +0000 Subject: doc: Add guide for building the docs locally This new page contains instructions for doing a local build of the documentation, plus information on the environment setup that needs to be done beforehand. Change-Id: If563145ab40639cabbe25d0f62759981a33692c6 Signed-off-by: Paul Beesley --- docs/getting_started/docs-build.rst | 77 +++++++++++++++++++++++++++++++++++++ docs/getting_started/index.rst | 1 + 2 files changed, 78 insertions(+) create mode 100644 docs/getting_started/docs-build.rst diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst new file mode 100644 index 000000000..fa0764266 --- /dev/null +++ b/docs/getting_started/docs-build.rst @@ -0,0 +1,77 @@ +Building Documentation +====================== + +To create a rendered copy of this documentation locally you can use the +`Sphinx`_ tool to build and package the plain-text documents into HTML-formatted +pages. + +If you are building the documentation for the first time then you will need to +check that you have the required software packages, as described in the +*Prerequisites* section that follows. + +.. note:: + An online copy of the documentation is available at + https://www.trustedfirmware.org/docs/tf-a, if you want to view a rendered + copy without doing a local build. + +Prerequisites +------------- + +For building a local copy of the |TF-A| documentation you will need, at minimum: + +- Python 3 (3.5 or later) +- PlantUML (1.2017.15 or later) + +You must also install the Python modules that are specified in the +``requirements.txt`` file in the root of the ``docs`` directory. These modules +can be installed using ``pip3`` (the Python Package Installer). Passing this +requirements file as an argument to ``pip3`` automatically installs the specific +module versions required by |TF-A|. + +An example set of installation commands for Ubuntu 18.04 LTS follows, assuming +that the working directory is ``docs``: + +.. code:: shell + + sudo apt install python3 python3-pip plantuml + pip3 install [--user] -r requirements.txt + +.. note:: + Several other modules will be installed as dependencies. Please review + the list to ensure that there will be no conflicts with other modules already + installed in your environment. + +Passing the optional ``--user`` argument to ``pip3`` will install the Python +packages only for the current user. Omitting this argument will attempt to +install the packages globally and this will likely require the command to be run +as root or using ``sudo``. + +.. note:: + More advanced usage instructions for *pip* are beyond the scope of this + document but you can refer to the `pip homepage`_ for detailed guides. + +Building rendered documentation +------------------------------- + +From the ``docs`` directory of the project, run the following commands. It is +important to note that you will not get the correct result if the commands are +run from the project root directory, as that would invoke the top-level Makefile +for |TF-A| itself. + +.. code:: shell + + make clean + make html + +Output from the build process will be placed in: + +:: + + /docs/build/html/ + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* + +.. _Sphinx: http://www.sphinx-doc.org/en/master/ +.. _pip homepage: https://pip.pypa.io/en/stable/ diff --git a/docs/getting_started/index.rst b/docs/getting_started/index.rst index 23608f860..07e3753ec 100644 --- a/docs/getting_started/index.rst +++ b/docs/getting_started/index.rst @@ -7,6 +7,7 @@ Getting Started :numbered: user-guide + docs-build image-terminology porting-guide psci-lib-integration-guide -- cgit v1.2.3 From 76cf653b8a080029a0376d714b964f4c64da94f7 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Wed, 9 Oct 2019 15:37:59 +0000 Subject: doc: Formatting fixes for readme.rst The readme.rst file in the project root is the front-page that is displayed on Github and if viewing the TF-A repository on git.trustedfirmware.org in the "about" view. It now contains a small amount of stub content, and directs readers to the ReadTheDocs documentation via trustedfirmware.org/docs/tf-a. The Github renderer is displaying the content fine but the cgit viewer displays some "backlink" errors because some content substitutions were left in place (terms surrounded by pipe symbols), e.g. |TF-A|. This patch removes those substitutions, that are not supported by cgit, and also updates one heading to clarify where to find the new docs. Change-Id: I358451df45b8c99975ba0b6db8ea61253a10560d Signed-off-by: Paul Beesley --- readme.rst | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/readme.rst b/readme.rst index f8f8daf8d..148d477a4 100644 --- a/readme.rst +++ b/readme.rst @@ -1,13 +1,13 @@ Trusted Firmware-A ================== -Trusted Firmware-A is a reference implementation of secure world software for -`Arm A-Profile architectures`_ (Armv8-A and Armv7-A), including an -Exception Level 3 (EL3)`Secure Monitor`_. It provides a suitable starting point -for productization of secure world boot and runtime firmware, in either the -|AArch32| or |AArch64| execution states. +Trusted Firmware-A (TF-A) is a reference implementation of secure world software +for `Arm A-Profile architectures`_ (Armv8-A and Armv7-A), including an Exception +Level 3 (EL3) `Secure Monitor`_. It provides a suitable starting point for +productization of secure world boot and runtime firmware, in either the AArch32 +or AArch64 execution states. -|TF-A| implements Arm interface standards, including: +TF-A implements Arm interface standards, including: - `Power State Coordination Interface (PSCI)`_ - `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)`_ @@ -18,15 +18,15 @@ for productization of secure world boot and runtime firmware, in either the The code is designed to be portable and reusable across hardware platforms and software models that are based on the Armv8-A and Armv7-A architectures. -In collaboration with interested parties, we will continue to enhance |TF-A| +In collaboration with interested parties, we will continue to enhance TF-A with reference implementations of Arm standards to benefit developers working with Armv7-A and Armv8-A TrustZone technology. Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from TF-A. -Read More ---------- +More Info and Documentation +--------------------------- To find out more about Trusted Firmware-A, please `view the full documentation`_ that is available through `trustedfirmware.org`_. -- cgit v1.2.3 From 89632e6aeba8414c1901eecb5d885363c73448f0 Mon Sep 17 00:00:00 2001 From: Balint Dobszay Date: Fri, 11 Oct 2019 14:01:43 +0200 Subject: Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__ Change-Id: I497072575231730a216220f84a6d349a48eaf5e3 Signed-off-by: Balint Dobszay --- include/lib/cpus/aarch64/cortex_a53.h | 4 ++-- include/lib/cpus/aarch64/cortex_a73.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index ea7181ed4..6fe67a9f3 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -76,8 +76,8 @@ /******************************************************************************* * Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs ******************************************************************************/ -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1) -#endif +#endif /* __ASSEMBLER__ */ #endif /* CORTEX_A53_H */ diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index fb4f1ec0c..271a33348 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -38,8 +38,8 @@ /******************************************************************************* * Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs ******************************************************************************/ -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1) -#endif +#endif /* __ASSEMBLER__ */ #endif /* CORTEX_A73_H */ -- cgit v1.2.3 From be653a6940b6c7bf3c0c6b7049ae829fa70863c1 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Fri, 4 Oct 2019 16:17:46 +0000 Subject: doc: Misc syntax and spelling fixes Tidying up a few Sphinx warnings that had built-up over time. None of these are critical but it cleans up the Sphinx output. At the same time, fixing some spelling errors that were detected. Change-Id: I38209e235481eed287f8008c6de9dedd6b12ab2e Signed-off-by: Paul Beesley --- docs/components/firmware-update.rst | 2 +- docs/design/firmware-design.rst | 4 ++-- docs/getting_started/image-terminology.rst | 8 ++++---- docs/getting_started/porting-guide.rst | 6 +++--- docs/maintainers.rst | 8 +++++--- docs/perf/psci-performance-juno.rst | 2 +- docs/plat/marvell/porting.rst | 2 +- docs/plat/meson-g12a.rst | 2 +- docs/process/coding-guidelines.rst | 4 ++-- docs/security_advisories/security-advisory-tfv-6.rst | 2 +- 10 files changed, 21 insertions(+), 19 deletions(-) diff --git a/docs/components/firmware-update.rst b/docs/components/firmware-update.rst index 2bff00f51..a59156568 100644 --- a/docs/components/firmware-update.rst +++ b/docs/components/firmware-update.rst @@ -7,7 +7,7 @@ Introduction This document describes the design of the Firmware Update (FWU) feature, which enables authenticated firmware to update firmware images from external interfaces such as USB, UART, SD-eMMC, NAND, NOR or Ethernet to SoC Non-Volatile -memories such as NAND Flash, LPPDR2-NVM or any memory determined by the +memories such as NAND Flash, LPDDR2-NVM or any memory determined by the platform. This feature functions even when the current firmware in the system is corrupt or missing; it therefore may be used as a recovery mode. It may also be complemented by other, higher level firmware update software. diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index 1deacb7f9..4958fc097 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -1672,7 +1672,7 @@ The following list describes the memory layout on the Arm development platforms: point during a cold boot. - On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory - region and transfered to the SCP before being overwritten by EL3 Runtime + region and transferred to the SCP before being overwritten by EL3 Runtime Software. - BL32 (for AArch64) can be loaded in one of the following locations: @@ -2623,7 +2623,7 @@ Cortex-A architecture through ``ARM_CORTEX_A = yes`` in their Cortex-A15 target. Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. -Note that using neon at runtime has constraints on non secure wolrd context. +Note that using neon at runtime has constraints on non secure world context. TF-A does not yet provide VFP context management. Directive ``ARM_CORTEX_A`` and ``ARM_WITH_NEON`` are used to set diff --git a/docs/getting_started/image-terminology.rst b/docs/getting_started/image-terminology.rst index d9e08f76c..5993d6e7a 100644 --- a/docs/getting_started/image-terminology.rst +++ b/docs/getting_started/image-terminology.rst @@ -7,7 +7,7 @@ images referred to in the Trusted Firmware project. General Notes ------------- -- Some of the names and abbreviated names have changed to accomodate new +- Some of the names and abbreviated names have changed to accommodate new requirements. The changed names are as backward compatible as possible to minimize confusion. Where applicable, the previous names are indicated. Some code, documentation and build artefacts may still refer to the previous names; @@ -44,7 +44,7 @@ AP Boot ROM: ``AP_BL1`` ~~~~~~~~~~~~~~~~~~~~~~~ Typically, this is the first code to execute on the AP and cannot be modified. -Its primary purpose is to perform the minimum intialization necessary to load +Its primary purpose is to perform the minimum initialization necessary to load and authenticate an updateable AP firmware image into an executable RAM location, then hand-off control to that image. @@ -96,7 +96,7 @@ SCP Boot ROM: ``SCP_BL1`` (previously ``BL0``) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Typically, this is the first code to execute on the SCP and cannot be modified. -Its primary purpose is to perform the minimum intialization necessary to load +Its primary purpose is to perform the minimum initialization necessary to load and authenticate an updateable SCP firmware image into an executable RAM location, then hand-off control to that image. This may be performed in conjunction with other processor firmware (for example, ``AP_BL1`` and @@ -129,7 +129,7 @@ AP Firmware Update Boot ROM: ``AP_NS_BL1U`` Typically, this is the first normal world code to execute on the AP during a firmware update operation, and cannot be modified. Its primary purpose is to -load subequent firmware update images from an external interface and communicate +load subsequent firmware update images from an external interface and communicate with ``AP_BL1`` to authenticate those images. During firmware update, there are (potentially) multiple transitions between the diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index d7157690d..9cca75e92 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -549,7 +549,7 @@ optionally be defined: - **PLAT_PARTITION_BLOCK_SIZE** The size of partition block. It could be either 512 bytes or 4096 bytes. The default value is 512. - `For example, define the build flag in platform.mk`_: + For example, define the build flag in ``platform.mk``: PLAT_PARTITION_BLOCK_SIZE := 4096 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) @@ -954,7 +954,7 @@ Function : plat_reset_handler() Return : void A platform may need to do additional initialization after reset. This function -allows the platform to do the platform specific intializations. Platform +allows the platform to do the platform specific initializations. Platform specific errata workarounds could also be implemented here. The API should preserve the values of callee saved registers x19 to x29. @@ -2777,7 +2777,7 @@ more functionality is required, the needed library functions will need to be added to the local implementation. Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have -been written specifically for TF-A. Fome implementation files have been obtained +been written specifically for TF-A. Some implementation files have been obtained from `FreeBSD`_, others have been written specifically for TF-A as well. The files can be found in ``include/lib/libc`` and ``lib/libc``. diff --git a/docs/maintainers.rst b/docs/maintainers.rst index d997baace..86e445a76 100644 --- a/docs/maintainers.rst +++ b/docs/maintainers.rst @@ -49,9 +49,9 @@ Amlogic Meson S905x (GXL) platform port :F: plat/amlogic/gxl/ Amlogic Meson S905X2 (G12A) platform port ---------------------------------------- +----------------------------------------- :M: Carlo Caione -:G: `carlo.caione`_ +:G: `carlocaione`_ :F: docs/plat/meson-g12a.rst :F: drivers/amlogic/g12a :F: plat/amlogic/g12a/ @@ -122,7 +122,7 @@ Intel SocFPGA platform ports :M: Tien Hock Loh :G: `thloh85-intel`_ :M: Hadi Asyrafi -:G: `mabdulha`_ +:G: mabdulha :F: plat/intel/soc :F: drivers/intel/soc/ @@ -282,6 +282,7 @@ Xilinx platform port .. _Anson-Huang: https://github.com/Anson-Huang .. _bryanodonoghue: https://github.com/bryanodonoghue .. _b49020: https://github.com/b49020 +.. _carlocaione: https://github.com/carlocaione .. _danh-arm: https://github.com/danh-arm .. _etienne-lms: https://github.com/etienne-lms .. _glneo: https://github.com/glneo @@ -308,6 +309,7 @@ Xilinx platform port .. _sivadur: https://github.com/sivadur .. _smaeul: https://github.com/smaeul .. _soby-mathew: https://github.com/soby-mathew +.. _thloh85-intel: https://github.com/thloh85-intel .. _thomas-arm: https://github.com/thomas-arm .. _TonyXie06: https://github.com/TonyXie06 .. _vwadekar: https://github.com/vwadekar diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst index 4cc430265..c127c1c4a 100644 --- a/docs/perf/psci-performance-juno.rst +++ b/docs/perf/psci-performance-juno.rst @@ -168,7 +168,7 @@ the cache associated with power level 0 is flushed (L1). | 5 | 21 | 17 | 6 | +-------+---------------------+--------------------+--------------------------+ -The ``CLUSH_OVERHEAD`` times for lead CPU 4 and all CPUs in the non-lead cluster +The ``CFLUSH_OVERHEAD`` times for lead CPU 4 and all CPUs in the non-lead cluster are large because all other CPUs in the cluster are powered down during the test. The ``CPU_SUSPEND`` call powers down to the cluster level, requiring a flush of both L1 and L2 caches. diff --git a/docs/plat/marvell/porting.rst b/docs/plat/marvell/porting.rst index 8fc1c1f6d..0a71dbd54 100644 --- a/docs/plat/marvell/porting.rst +++ b/docs/plat/marvell/porting.rst @@ -112,7 +112,7 @@ Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h) .. seealso:: For XFI/SFI comphy type there is procedure "rx_training" which eases - process of suiting some of the parameters. Please see :ref:`uboot_cmd` + process of suiting some of the parameters. Please see *uboot_cmd* section: rx_training. The PHY porting layer simplifies updating static values per board type, diff --git a/docs/plat/meson-g12a.rst b/docs/plat/meson-g12a.rst index 1021da47c..7cd1bf746 100644 --- a/docs/plat/meson-g12a.rst +++ b/docs/plat/meson-g12a.rst @@ -1,5 +1,5 @@ Amlogic Meson S905X2 (G12A) -========================== +=========================== The Amlogic Meson S905X2 is a SoC with a quad core Arm Cortex-A53 running at ~1.8GHz. It also contains a Cortex-M3 used as SCP. diff --git a/docs/process/coding-guidelines.rst b/docs/process/coding-guidelines.rst index a53da77b9..cb8b89245 100644 --- a/docs/process/coding-guidelines.rst +++ b/docs/process/coding-guidelines.rst @@ -23,8 +23,8 @@ include: - ``**WARNING: Use of volatile is usually wrong``: see `Why the “volatile” type class should not be used`_ . Although this document - contains some very useful information, there are several legimate uses of the - volatile keyword within the TF codebase. + contains some very useful information, there are several legitimate uses of + the volatile keyword within the TF codebase. Headers and inclusion --------------------- diff --git a/docs/security_advisories/security-advisory-tfv-6.rst b/docs/security_advisories/security-advisory-tfv-6.rst index 495edddae..9eeaeec57 100644 --- a/docs/security_advisories/security-advisory-tfv-6.rst +++ b/docs/security_advisories/security-advisory-tfv-6.rst @@ -51,7 +51,7 @@ the MMU. For Cortex-A73 and Cortex-A75 CPUs, the PRs in this advisory invalidate the branch predictor when entering EL3 by temporarily dropping into AArch32 Secure-EL1 and executing the ``BPIALL`` instruction. This workaround is -signifiantly more complex than the "MMU disable/enable" workaround. The latter +significantly more complex than the "MMU disable/enable" workaround. The latter is not effective at invalidating the branch predictor on Cortex-A73/Cortex-A75. Note that if other privileged software, for example a Rich OS kernel, implements -- cgit v1.2.3 From 9ec4afc8ddb5d415bd5fac2134b4012b32920bcc Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Tue, 15 Oct 2019 09:08:12 +0000 Subject: doc: Update Linaro release mentioned on index page The version of the Linaro release that is used for testing was updated in 35010bb8 and the user guide was updated with the correct version, however the version is also mentioned on the index page and that was missed. Update the index page with the new version. We can come back and de-duplicate this content later, to ease future maintenance. Change-Id: I3fe83d7a1c59ab8d3ce2b18bcc23e16c93f7af97 Signed-off-by: Paul Beesley --- docs/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/index.rst b/docs/index.rst index 4f0f6ef79..3cdb2b259 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -197,7 +197,7 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from Arm. See the `Arm FVP website`_. -All the above platforms have been tested with `Linaro Release 18.04`_. +All the above platforms have been tested with `Linaro Release 19.06`_. This release also contains the following platform support: @@ -288,7 +288,7 @@ Arm licensees may contact Arm directly via their partner managers. .. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php .. _Arm FVP website: FVP_ .. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms -.. _Linaro Release 18.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease18.04 +.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 .. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os .. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary .. _Trusty Secure OS: https://source.android.com/security/trusty -- cgit v1.2.3 From 2ee6b2bc77b6f967d5e28e030c9447e9c0ea9cac Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Tue, 15 Oct 2019 10:47:09 -0500 Subject: Update TF-A version to 2.2 Signed-off-by: Deepika Bhavnani Change-Id: Ia03701e2e37e3a00a501b144960a4a65aedbfde9 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 18800cb83..721246d51 100644 --- a/Makefile +++ b/Makefile @@ -8,7 +8,7 @@ # Trusted Firmware Version # VERSION_MAJOR := 2 -VERSION_MINOR := 1 +VERSION_MINOR := 2 # Default goal is build all images .DEFAULT_GOAL := all -- cgit v1.2.3 From 434d93d96ae152ae616c73ef58d3f41d07c750ca Mon Sep 17 00:00:00 2001 From: Artsem Artsemenka Date: Tue, 15 Oct 2019 14:59:04 +0100 Subject: Fix documentation User guide: 1. Remove obsolete note saying only FVP is supported with AArch32 2. Switch compiler for Juno AArch32 to arm-eabi 3. Mention SOFTWARE folder in Juno Linaro release Index.rst: 1. Switch default FVP model to Version 11.6 Build 45 Signed-off-by: Artsem Artsemenka Change-Id: Ib47a2ea314e2b8394a20189bf91796de0e17de53 --- docs/getting_started/user-guide.rst | 6 ++---- docs/index.rst | 2 +- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index e540fd06a..a4886c671 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -188,8 +188,6 @@ Building TF-A `Summary of build options`_ for more information on available build options. - - (AArch32 only) Currently only ``PLAT=fvp`` is supported. - - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is provided by TF-A to demonstrate how PSCI Library can be integrated with @@ -1359,7 +1357,7 @@ a single FIP binary. It assumes that a `Linaro Release`_ has been installed. make [DEBUG=1] [V=1] fiptool # Unpack firmware images from Linaro FIP - ./tools/fiptool/fiptool unpack /fip.bin + ./tools/fiptool/fiptool unpack /[SOFTWARE]/fip.bin The unpack operation will result in a set of binary images extracted to the current working directory. The SCP_BL2 image corresponds to @@ -1406,7 +1404,7 @@ a single FIP binary. It assumes that a `Linaro Release`_ has been installed. .. code:: shell - export CROSS_COMPILE=/bin/arm-linux-gnueabihf- + export CROSS_COMPILE=/bin/arm-eabi- - Build BL32 in AArch32. diff --git a/docs/index.rst b/docs/index.rst index 2023ceb1d..bf2b873be 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -154,7 +154,7 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only). .. note:: - The FVP models used are Version 11.5 Build 33, unless otherwise stated. + The FVP models used are Version 11.6 Build 45, unless otherwise stated. - ``FVP_Base_AEMv8A-AEMv8A`` - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` -- cgit v1.2.3 From 206c077b831870463178b016b5b151bcb5baf913 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Thu, 17 Oct 2019 13:39:06 +0000 Subject: doc: Remove version and release variables from conf.py We would need to update this version for the release but, in fact, it is not required for our publishing workflow; the hosted version of the docs uses git commit/tag information in place of these variables anyway. Instead of updating the version, just remove these variables entirely. Change-Id: I424c4e45786e87604e91c7197b7983579afe4806 Signed-off-by: Paul Beesley --- docs/conf.py | 3 --- 1 file changed, 3 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index b267de0e8..a100241c1 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -15,9 +15,6 @@ import os project = 'Trusted Firmware-A' -version = '2.1' -release = version # We don't need these to be distinct - # -- General configuration --------------------------------------------------- # Add any Sphinx extension module names here, as strings. They can be -- cgit v1.2.3 From 0e7a0540d728122913afbc99df4c4b87a19e8048 Mon Sep 17 00:00:00 2001 From: Artsem Artsemenka Date: Thu, 17 Oct 2019 13:51:27 +0100 Subject: xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config The WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during the boot. But the xlat_change_mem_attributes_ctx() API did not do the required cache maintenance after the mmap tables are modified if WARMBOOT_ENABLE_DCACHE_EARLY is enabled. This meant that when the caches are turned off during power down, the tables in memory are accessed as part of cache maintenance for power down, and the tables are not correct at this point which results in a data abort. This patch removes the optimization within xlat_change_mem_attributes_ctx() when WARMBOOT_ENABLE_DCACHE_EARLY is enabled. Signed-off-by: Artsem Artsemenka Change-Id: I82de3decba87dd13e9856b5f3620a1c8571c8d87 --- lib/xlat_tables_v2/xlat_tables_utils.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/xlat_tables_v2/xlat_tables_utils.c b/lib/xlat_tables_v2/xlat_tables_utils.c index 232142e84..30babc63f 100644 --- a/lib/xlat_tables_v2/xlat_tables_utils.c +++ b/lib/xlat_tables_v2/xlat_tables_utils.c @@ -551,7 +551,7 @@ int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, * before writing the new descriptor. */ *entry = INVALID_DESC; -#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) +#if !HW_ASSISTED_COHERENCY dccvac((uintptr_t)entry); #endif /* Invalidate any cached copy of this mapping in the TLBs. */ @@ -562,7 +562,7 @@ int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, /* Write new descriptor */ *entry = xlat_desc(ctx, new_attr, addr_pa, level); -#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) +#if !HW_ASSISTED_COHERENCY dccvac((uintptr_t)entry); #endif base_va += PAGE_SIZE; -- cgit v1.2.3 From 7af195e29a4213eefac0661d84e1c9c20476e166 Mon Sep 17 00:00:00 2001 From: Simon South Date: Sun, 20 Oct 2019 13:54:32 -0400 Subject: Disable stack protection explicitly Explicitly disable stack protection via the "-fno-stack-protector" compiler option when the ENABLE_STACK_PROTECTOR build option is set to "none" (the default). This allows the build to complete without link errors on systems where stack protection is enabled by default in the compiler. Change-Id: I0a676aa672815235894fb2cd05fa2b196fabb972 Signed-off-by: Simon South --- lib/stack_protector/stack_protector.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/stack_protector/stack_protector.mk b/lib/stack_protector/stack_protector.mk index 94e804be9..b5aba1528 100644 --- a/lib/stack_protector/stack_protector.mk +++ b/lib/stack_protector/stack_protector.mk @@ -11,7 +11,9 @@ ifeq (${ENABLE_STACK_PROTECTOR},0) ENABLE_STACK_PROTECTOR := none endif -ifneq (${ENABLE_STACK_PROTECTOR},none) +ifeq (${ENABLE_STACK_PROTECTOR},none) + TF_CFLAGS += -fno-stack-protector +else STACK_PROTECTOR_ENABLED := 1 BL_COMMON_SOURCES += lib/stack_protector/stack_protector.c \ lib/stack_protector/${ARCH}/asm_stack_protector.S -- cgit v1.2.3 From b30646a8f7f8c428faa02f26c01ca383b985afed Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Fri, 18 Oct 2019 11:01:03 +0100 Subject: plat/arm: use Aff3 bits also to validate mpidr There are some platforms which uses MPIDR Affinity level 3 for storing extra affinity information e.g. N1SDP uses it for keeping chip id in a multichip setup, for such platforms MPIDR validation should not fail. This patch adds Aff3 bits also as part of mpidr validation mask, for platforms which does not uses Aff3 will not have any impact as these bits will be all zeros. Change-Id: Ia8273972fa7948fdb11708308d0239d2dc4dfa85 Signed-off-by: Manish Pandey --- plat/arm/common/arm_topology.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/plat/arm/common/arm_topology.c b/plat/arm/common/arm_topology.c index 37047bcf3..c9993a725 100644 --- a/plat/arm/common/arm_topology.c +++ b/plat/arm/common/arm_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,7 +24,8 @@ int arm_check_mpidr(u_register_t mpidr) valid_mask = ~(MPIDR_AFFLVL_MASK | (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | - (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)); + (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | + (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT)); cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; -- cgit v1.2.3 From 8eb9490b61c65288eaacbf229afbbe0f99484c86 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Wed, 16 Oct 2019 13:35:47 +0000 Subject: doc: Move "About" content from index.rst to a new chapter The index.rst page is now the primary landing page for the TF-A documentation. It contains quite a lot of content these days, including: - The project purpose and general intro - A list of functionality - A list of planned functionality - A list of supported platforms - "Getting started" links to other documents - Contact information for raising issues This patch creates an "About" chapter in the table of contents and moves some content there. In order, the above listed content: - Stayed where it is. This is the right place for it. - Moved to About->Features - Moved to About->Features (in subsection) - Stayed where it is. Moved in a later patch. - Was expanded in-place - Moved to About->Contact Change-Id: I254bb87560fd09140b9e485cf15246892aa45943 Signed-off-by: Paul Beesley --- docs/about/acknowledgements.rst | 21 +++ docs/about/contact.rst | 17 ++ docs/about/features.rst | 127 ++++++++++++++ docs/about/index.rst | 13 ++ docs/about/maintainers.rst | 316 +++++++++++++++++++++++++++++++++++ docs/about/release-information.rst | 82 +++++++++ docs/acknowledgements.rst | 17 -- docs/index.rst | 185 ++++---------------- docs/maintainers.rst | 316 ----------------------------------- docs/process/index.rst | 1 - docs/process/release-information.rst | 82 --------- 11 files changed, 608 insertions(+), 569 deletions(-) create mode 100644 docs/about/acknowledgements.rst create mode 100644 docs/about/contact.rst create mode 100644 docs/about/features.rst create mode 100644 docs/about/index.rst create mode 100644 docs/about/maintainers.rst create mode 100644 docs/about/release-information.rst delete mode 100644 docs/acknowledgements.rst delete mode 100644 docs/maintainers.rst delete mode 100644 docs/process/release-information.rst diff --git a/docs/about/acknowledgements.rst b/docs/about/acknowledgements.rst new file mode 100644 index 000000000..a9f64511f --- /dev/null +++ b/docs/about/acknowledgements.rst @@ -0,0 +1,21 @@ +Contributor Acknowledgements +============================ + +.. note:: + This file is only relevant for legacy contributions, to acknowledge the + specific contributors referred to in "Arm Limited and Contributors" copyright + notices. As contributors are now encouraged to put their name or company name + directly into the copyright notices, this file is not relevant for new + contributions. + +- Linaro Limited +- Marvell International Ltd. +- NVIDIA Corporation +- NXP Semiconductors +- Socionext Inc. +- STMicroelectronics +- Xilinx, Inc. + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/about/contact.rst b/docs/about/contact.rst new file mode 100644 index 000000000..af6668dda --- /dev/null +++ b/docs/about/contact.rst @@ -0,0 +1,17 @@ +Support & Contact +----------------- + +We welcome any feedback on TF-A. If you think you have found a security +vulnerability, please report this using the process defined in the TF-A +:ref:`Security Handling` document. + +For all other feedback, please use the `issue tracker`_ or our `mailing list`_. + +Arm licensees may contact Arm directly via their partner managers. + +.. _issue tracker: https://issues.trustedfirmware.org +.. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/about/features.rst b/docs/about/features.rst new file mode 100644 index 000000000..9df289468 --- /dev/null +++ b/docs/about/features.rst @@ -0,0 +1,127 @@ +Feature Overview +================ + +This page provides an overview of the current |TF-A| feature set. For a full +description of these features and their implementation details, please see +:ref:`Firmware Design` and supporting documentation. + +The :ref:`Change Log & Release Notes` provides details of changes made since the +last release. + +Current features +---------------- + +- Initialization of the secure world, for example exception vectors, control + registers and interrupts for the platform. + +- Library support for CPU specific reset and power down sequences. This + includes support for errata workarounds and the latest Arm DynamIQ CPUs. + +- Drivers to enable standard initialization of Arm System IP, for example + Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI), + Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone + Controller (TZC). + +- A generic |SCMI| driver to interface with conforming power controllers, for + example the Arm System Control Processor (SCP). + +- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling + Convention`_ using an EL3 runtime services framework. + +- |PSCI| library support for CPU, cluster and system power management + use-cases. + This library is pre-integrated with the AArch64 EL3 Runtime Software, and + is also suitable for integration with other AArch32 EL3 Runtime Software, + for example an AArch32 Secure OS. + +- A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate |PSCI| library + integration with AArch32 EL3 Runtime Software. + +- Secure Monitor library code such as world switching, EL1 context management + and interrupt routing. + When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the + AArch64 EL3 Runtime Software must be integrated with a Secure Payload + Dispatcher (SPD) component to customize the interaction with the SP. + +- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP + interaction with PSCI. + +- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_ + and `Trusty Secure OS`_. + +- A Trusted Board Boot implementation, conforming to all mandatory TBBR + requirements. This includes image authentication, Firmware Update (or + recovery mode), and packaging of the various firmware images into a + Firmware Image Package (FIP). + +- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of + its hardware Root of Trust and crypto acceleration services. + +- Reliability, Availability, and Serviceability (RAS) functionality, including + + - A Secure Partition Manager (SPM) to manage Secure Partitions in + Secure-EL0, which can be used to implement simple management and + security services. + + - An |SDEI| dispatcher to route interrupt-based |SDEI| events. + + - An Exception Handling Framework (EHF) that allows dispatching of EL3 + interrupts to their registered handlers, to facilitate firmware-first + error handling. + +- A dynamic configuration framework that enables each of the firmware images + to be configured at runtime if required by the platform. It also enables + loading of a hardware configuration (for example, a kernel device tree) + as part of the FIP, to be passed through the firmware stages. + +- Support for alternative boot flows, for example to support platforms where + the EL3 Runtime Software is loaded using other firmware or a separate + secure system processor, or where a non-TF-A ROM expects BL2 to be loaded + at EL3. + +- Support for the GCC, LLVM and Arm Compiler 6 toolchains. + +- Support for combining several libraries into a "romlib" image that may be + shared across images to reduce memory footprint. The romlib image is stored + in ROM but is accessed through a jump-table that may be stored + in read-write memory, allowing for the library code to be patched. + +- A prototype implementation of a Secure Partition Manager (SPM) that is based + on the SPCI Alpha 1 and SPRT draft specifications. + +- Support for ARMv8.3 pointer authentication in the normal and secure worlds. + The use of pointer authentication in the normal world is enabled whenever + architectural support is available, without the need for additional build + flags. Use of pointer authentication in the secure world remains an + experimental configuration at this time and requires the + ``BRANCH_PROTECTION`` option to be set to non-zero. + +- Position-Independent Executable (PIE) support. Initially for BL31 only, with + further support to be added in a future release. + +Still to come +------------- + +- Support for additional platforms. + +- Refinements to Position Independent Executable (PIE) support. + +- Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT + specifications continue to evolve. + +- Documentation enhancements. + +- Ongoing support for new architectural features, CPUs and System IP. + +- Ongoing support for new Arm system architecture specifications. + +- Ongoing security hardening, optimization and quality improvements. + +.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf +.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os +.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary +.. _Trusty Secure OS: https://source.android.com/security/trusty + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/about/index.rst b/docs/about/index.rst new file mode 100644 index 000000000..3a102668c --- /dev/null +++ b/docs/about/index.rst @@ -0,0 +1,13 @@ +About +===== + +.. toctree:: + :maxdepth: 1 + :caption: Contents + :numbered: + + features + release-information + maintainers + contact + acknowledgements diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst new file mode 100644 index 000000000..86e445a76 --- /dev/null +++ b/docs/about/maintainers.rst @@ -0,0 +1,316 @@ +Maintainers +=========== + +Trusted Firmware-A (TF-A) is an Arm maintained project. All contributions are +ultimately merged by the maintainers listed below. Technical ownership of some +parts of the codebase is delegated to the sub-maintainers listed below. An +acknowledgement from these sub-maintainers may be required before the +maintainers merge a contribution. + +Main maintainers +---------------- +:M: Dan Handley +:G: `danh-arm`_ +:M: Soby Mathew +:G: `soby-mathew`_ +:M: Sandrine Bailleux +:G: `sandrine-bailleux-arm`_ +:M: Alexei Fedorov +:G: `AlexeiFedorov`_ +:M: Paul Beesley +:G: `pbeesley-arm`_ +:M: John Tsichritzis +:G: `jts-arm`_ + +Allwinner ARMv8 platform port +----------------------------- +:M: Andre Przywara +:G: `Andre-ARM`_ +:M: Samuel Holland +:G: `smaeul`_ +:F: docs/plat/allwinner.rst +:F: plat/allwinner/ +:F: drivers/allwinner/ + +Amlogic Meson S905 (GXBB) platform port +--------------------------------------- +:M: Andre Przywara +:G: `Andre-ARM`_ +:F: docs/plat/meson-gxbb.rst +:F: drivers/amlogic/ +:F: plat/amlogic/gxbb/ + +Amlogic Meson S905x (GXL) platform port +--------------------------------------- +:M: Remi Pommarel +:G: `remi-triplefault`_ +:F: docs/plat/meson-gxl.rst +:F: drivers/amlogic/gxl +:F: plat/amlogic/gxl/ + +Amlogic Meson S905X2 (G12A) platform port +----------------------------------------- +:M: Carlo Caione +:G: `carlocaione`_ +:F: docs/plat/meson-g12a.rst +:F: drivers/amlogic/g12a +:F: plat/amlogic/g12a/ + +Armv7-A architecture port +------------------------- +:M: Etienne Carriere +:G: `etienne-lms`_ + +Arm System Guidance for Infrastructure / Mobile FVP platforms +------------------------------------------------------------- +:M: Nariman Poushin +:G: `npoushin`_ +:M: Thomas Abraham +:G: `thomas-arm`_ +:F: plat/arm/css/sgi/ +:F: plat/arm/css/sgm/ +:F: plat/arm/board/sgi575/ +:F: plat/arm/board/sgm775/ + +Console API framework +--------------------- +:M: Julius Werner +:G: `jwerner-chromium`_ +:F: drivers/console/ +:F: include/drivers/console.h +:F: plat/common/aarch64/crash_console_helpers.S + +coreboot support libraries +-------------------------- +:M: Julius Werner +:G: `jwerner-chromium`_ +:F: drivers/coreboot/ +:F: include/drivers/coreboot/ +:F: include/lib/coreboot.h +:F: lib/coreboot/ + +eMMC/UFS drivers +---------------- +:M: Haojian Zhuang +:G: `hzhuang1`_ +:F: drivers/partition/ +:F: drivers/synopsys/emmc/ +:F: drivers/synopsys/ufs/ +:F: drivers/ufs/ +:F: include/drivers/dw_ufs.h +:F: include/drivers/ufs.h +:F: include/drivers/synopsys/dw_mmc.h + +HiSilicon HiKey and HiKey960 platform ports +------------------------------------------- +:M: Haojian Zhuang +:G: `hzhuang1`_ +:F: docs/plat/hikey.rst +:F: docs/plat/hikey960.rst +:F: plat/hisilicon/hikey/ +:F: plat/hisilicon/hikey960/ + +HiSilicon Poplar platform port +------------------------------ +:M: Shawn Guo +:G: `shawnguo2`_ +:F: docs/plat/poplar.rst +:F: plat/hisilicon/poplar/ + +Intel SocFPGA platform ports +---------------------------- +:M: Tien Hock Loh +:G: `thloh85-intel`_ +:M: Hadi Asyrafi +:G: mabdulha +:F: plat/intel/soc +:F: drivers/intel/soc/ + +MediaTek platform ports +----------------------- +:M: Yidi Lin (林以廸) +:G: `mtk09422`_ +:F: plat/mediatek/ + +Marvell platform ports and SoC drivers +-------------------------------------- +:M: Konstantin Porotchkin +:G: `kostapr`_ +:F: docs/marvell/ +:F: plat/marvell/ +:F: drivers/marvell/ +:F: tools/marvell/ + +NVidia platform ports +--------------------- +:M: Varun Wadekar +:G: `vwadekar`_ +:F: docs/plat/nvidia-tegra.rst +:F: include/lib/cpus/aarch64/denver.h +:F: lib/cpus/aarch64/denver.S +:F: plat/nvidia/ + +NXP QorIQ Layerscape platform ports +----------------------------------- +:M: Jiafei Pan +:G: `qoriq-open-source`_ +:F: docs/plat/ls1043a.rst +:F: plat/layerscape/ + +NXP i.MX 7 WaRP7 platform port and SoC drivers +---------------------------------------------- +:M: Bryan O'Donoghue +:G: `bryanodonoghue`_ +:M: Jun Nie +:G: `niej`_ +:F: docs/plat/warp7.rst +:F: plat/imx/common/ +:F: plat/imx/imx7/ +:F: drivers/imx/timer/ +:F: drivers/imx/uart/ +:F: drivers/imx/usdhc/ + +NXP i.MX 8 platform port +------------------------ +:M: Anson Huang +:G: `Anson-Huang`_ +:F: docs/plat/imx8.rst +:F: plat/imx/ + +NXP i.MX8M platform port +------------------------ +:M: Jacky Bai +:G: `JackyBai`_ +:F: doc/plat/imx8m.rst +:F: plat/imx/imx8m/ + +OP-TEE dispatcher +----------------- +:M: Jens Wiklander +:G: `jenswi-linaro`_ +:F: docs/spd/optee-dispatcher.rst +:F: services/spd/opteed/ + +QEMU platform port +------------------ +:M: Jens Wiklander +:G: `jenswi-linaro`_ +:F: docs/plat/qemu.rst +:F: plat/qemu/ + +Raspberry Pi 3 platform port +---------------------------- +:M: Ying-Chun Liu (PaulLiu) +:G: `grandpaul`_ +:F: docs/plat/rpi3.rst +:F: plat/rpi3/ +:F: drivers/rpi3/ +:F: include/drivers/rpi3/ + +Renesas rcar-gen3 platform port +------------------------------- +:M: Jorge Ramirez-Ortiz +:G: `ldts`_ +:M: Marek Vasut +:G: `marex`_ +:F: docs/plat/rcar-gen3.rst +:F: plat/renesas/rcar +:F: drivers/renesas/rcar +:F: tools/renesas/rcar_layout_create + +RockChip platform port +---------------------- +:M: Tony Xie +:G: `TonyXie06`_ +:G: `rockchip-linux`_ +:M: Heiko Stuebner +:G: `mmind`_ +:F: plat/rockchip/ + +STM32MP1 platform port +---------------------- +:M: Yann Gautier +:G: `Yann-lms`_ +:F: docs/plat/stm32mp1.rst +:F: drivers/st/ +:F: fdts/stm32\* +:F: include/drivers/st/ +:F: include/dt-bindings/\*/stm32\* +:F: plat/st/ +:F: tools/stm32image/ + +Synquacer platform port +----------------------- +:M: Sumit Garg +:G: `b49020`_ +:F: docs/plat/synquacer.rst +:F: plat/socionext/synquacer/ + +Texas Instruments platform port +------------------------------- +:M: Andrew F. Davis +:G: `glneo`_ +:F: docs/plat/ti-k3.rst +:F: plat/ti/ + +TLK/Trusty secure payloads +-------------------------- +:M: Varun Wadekar +:G: `vwadekar`_ +:F: docs/spd/tlk-dispatcher.rst +:F: docs/spd/trusty-dispatcher.rst +:F: include/bl32/payloads/tlk.h +:F: services/spd/tlkd/ +:F: services/spd/trusty/ + +UniPhier platform port +---------------------- +:M: Masahiro Yamada +:G: `masahir0y`_ +:F: docs/plat/socionext-uniphier.rst +:F: plat/socionext/uniphier/ + +Xilinx platform port +-------------------- +:M: Siva Durga Prasad Paladugu +:G: `sivadur`_ +:F: docs/plat/xilinx-zynqmp.rst +:F: plat/xilinx/ + +.. _AlexeiFedorov: https://github.com/AlexeiFedorov +.. _Andre-ARM: https://github.com/Andre-ARM +.. _Anson-Huang: https://github.com/Anson-Huang +.. _bryanodonoghue: https://github.com/bryanodonoghue +.. _b49020: https://github.com/b49020 +.. _carlocaione: https://github.com/carlocaione +.. _danh-arm: https://github.com/danh-arm +.. _etienne-lms: https://github.com/etienne-lms +.. _glneo: https://github.com/glneo +.. _grandpaul: https://github.com/grandpaul +.. _hzhuang1: https://github.com/hzhuang1 +.. _JackyBai: https://github.com/JackyBai +.. _jenswi-linaro: https://github.com/jenswi-linaro +.. _jts-arm: https://github.com/jts-arm +.. _jwerner-chromium: https://github.com/jwerner-chromium +.. _kostapr: https://github.com/kostapr +.. _ldts: https://github.com/ldts +.. _marex: https://github.com/marex +.. _masahir0y: https://github.com/masahir0y +.. _mmind: https://github.com/mmind +.. _mtk09422: https://github.com/mtk09422 +.. _niej: https://github.com/niej +.. _npoushin: https://github.com/npoushin +.. _pbeesley-arm: https://github.com/pbeesley-arm +.. _qoriq-open-source: https://github.com/qoriq-open-source +.. _remi-triplefault: https://github.com/repk +.. _rockchip-linux: https://github.com/rockchip-linux +.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm +.. _shawnguo2: https://github.com/shawnguo2 +.. _sivadur: https://github.com/sivadur +.. _smaeul: https://github.com/smaeul +.. _soby-mathew: https://github.com/soby-mathew +.. _thloh85-intel: https://github.com/thloh85-intel +.. _thomas-arm: https://github.com/thomas-arm +.. _TonyXie06: https://github.com/TonyXie06 +.. _vwadekar: https://github.com/vwadekar +.. _Yann-lms: https://github.com/Yann-lms diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst new file mode 100644 index 000000000..e264e51ad --- /dev/null +++ b/docs/about/release-information.rst @@ -0,0 +1,82 @@ +Release Processes +================= + +Project Release Cadence +----------------------- + +The project currently aims to do a release once every 6 months which will be +tagged on the master branch. There will be a code freeze (stop merging +non-essential PRs) up to 4 weeks prior to the target release date. The release +candidates will start appearing after this and only bug fixes or updates +required for the release will be merged. The maintainers are free to use their +judgement on what PRs are essential for the release. A release branch may be +created after code freeze if there are significant PRs that need merging onto +the integration branch during the merge window. + +The release testing will be performed on release candidates and depending on +issues found, additional release candidates may be created to fix the issues. + +:: + + |<----------6 months---------->| + |<---4 weeks--->| |<---4 weeks--->| + +-----------------------------------------------------------> time + | | | | + code freeze ver w.x code freeze ver y.z + + +Upcoming Releases +~~~~~~~~~~~~~~~~~ + +These are the estimated dates for the upcoming release. These may change +depending on project requirement and partner feedback. + ++-----------------+---------------------------+------------------------------+ +| Release Version | Target Date | Expected Code Freeze | ++=================+===========================+==============================+ +| v2.0 | 1st week of Oct '18 | 1st week of Sep '18 | ++-----------------+---------------------------+------------------------------+ +| v2.1 | 5th week of Mar '19 | 1st week of Mar '19 | ++-----------------+---------------------------+------------------------------+ + +Removal of Deprecated Interfaces +-------------------------------- + +As mentioned in the :ref:`Platform Compatibility Policy`, this is a live +document cataloging all the deprecated interfaces in TF-A project and the +Release version after which it will be removed. + ++--------------------------------+-------------+---------+---------------------------------------------------------+ +| Interface | Deprecation | Removed | Comments | +| | Date | after | | +| | | Release | | ++================================+=============+=========+=========================================================+ +| Legacy Console API | Jan '18 | v2.1 | Deprecated in favour of ``MULTI_CONSOLE_API`` | ++--------------------------------+-------------+---------+---------------------------------------------------------+ +| Weak default | Oct '18 | v2.1 | The default implementations are defined in | +| ``plat_crash_console_*`` | | | ``crash_console_helpers.S``. The platforms have to | +| APIs | | | define ``plat_crash_console_*``. | ++--------------------------------+-------------+---------+---------------------------------------------------------+ +| ``finish_console_register`` | Oct '18 | v2.1 | The old version of the macro is deprecated. See commit | +| macro in | | | cc5859c_ for more details. | +| ``MULTI_CONSOLE_API`` | | | | ++--------------------------------+-------------+---------+---------------------------------------------------------+ +| Types ``tzc_action_t`` and | Oct '18 | v2.1 | Using logical operations such as OR in enumerations | +| ``tzc_region_attributes_t`` | | | goes against the MISRA guidelines. | ++--------------------------------+-------------+---------+---------------------------------------------------------+ +| Macro ``EL_IMPLEMENTED()`` | Oct '18 | v2.1 | Deprecated in favour of ``el_implemented()``. | ++--------------------------------+-------------+---------+---------------------------------------------------------+ +| ``get_afflvl_shift()``, | Dec '18 | v2.1 | Removed. | +| ``mpidr_mask_lower_afflvls()``,| | | | +| and ``eret()``. | | | | ++--------------------------------+-------------+---------+---------------------------------------------------------+ +| Extra include paths in the | Jan '18 | v2.1 | Now it is needed to use the full path of the common | +| Makefile in ``INCLUDES``. | | | header files. More information in commit 09d40e0e0828_. | ++--------------------------------+-------------+---------+---------------------------------------------------------+ + +-------------- + +*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.* + +.. _cc5859c: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=cc5859ca19ff546c35eb0331000dae090b6eabcf +.. _09d40e0e0828: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=09d40e0e08283a249e7dce0e106c07c5141f9b7e diff --git a/docs/acknowledgements.rst b/docs/acknowledgements.rst deleted file mode 100644 index 74b77ff16..000000000 --- a/docs/acknowledgements.rst +++ /dev/null @@ -1,17 +0,0 @@ -Contributor Acknowledgements -============================ - -.. note:: - This file is only relevant for legacy contributions, to acknowledge the - specific contributors referred to in "Arm Limited and Contributors" copyright - notices. As contributors are now encouraged to put their name or company name - directly into the copyright notices, this file is not relevant for new - contributions. - -- Linaro Limited -- Marvell International Ltd. -- NVIDIA Corporation -- NXP Semiconductors -- Socionext Inc. -- STMicroelectronics -- Xilinx, Inc. diff --git a/docs/index.rst b/docs/index.rst index 4cd17988c..8981072a5 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -6,6 +6,7 @@ Trusted Firmware-A Documentation :hidden: Home + about/index getting_started/index process/index components/index @@ -14,14 +15,9 @@ Trusted Firmware-A Documentation perf/index security_advisories/index change-log - acknowledgements glossary - maintainers license -.. contents:: On This Page - :depth: 3 - Trusted Firmware-A (TF-A) provides a reference implementation of secure world software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing at Exception Level 3 (EL3). It implements various Arm interface standards, @@ -47,101 +43,41 @@ In collaboration with interested parties, we will continue to enhance |TF-A| with reference implementations of Arm standards to benefit developers working with Armv7-A and Armv8-A TrustZone technology. -Functionality -------------- - -- Initialization of the secure world, for example exception vectors, control - registers and interrupts for the platform. - -- Library support for CPU specific reset and power down sequences. This - includes support for errata workarounds and the latest Arm DynamIQ CPUs. - -- Drivers to enable standard initialization of Arm System IP, for example - Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI), - Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone - Controller (TZC). - -- A generic `SCMI`_ driver to interface with conforming power controllers, for - example the Arm System Control Processor (SCP). - -- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling - Convention`_ using an EL3 runtime services framework. - -- `PSCI`_ library support for CPU, cluster and system power management - use-cases. - This library is pre-integrated with the AArch64 EL3 Runtime Software, and - is also suitable for integration with other AArch32 EL3 Runtime Software, - for example an AArch32 Secure OS. - -- A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate `PSCI`_ library - integration with AArch32 EL3 Runtime Software. - -- Secure Monitor library code such as world switching, EL1 context management - and interrupt routing. - When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the - AArch64 EL3 Runtime Software must be integrated with a Secure Payload - Dispatcher (SPD) component to customize the interaction with the SP. - -- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP - interaction with PSCI. - -- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_ - and `Trusty Secure OS`_. - -- A Trusted Board Boot implementation, conforming to all mandatory TBBR - requirements. This includes image authentication, Firmware Update (or - recovery mode), and packaging of the various firmware images into a - Firmware Image Package (FIP). - -- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of - its hardware Root of Trust and crypto acceleration services. - -- Reliability, Availability, and Serviceability (RAS) functionality, including - - - A Secure Partition Manager (SPM) to manage Secure Partitions in - Secure-EL0, which can be used to implement simple management and - security services. - - - An |SDEI| dispatcher to route interrupt-based |SDEI| events. +Getting Started +--------------- - - An Exception Handling Framework (EHF) that allows dispatching of EL3 - interrupts to their registered handlers, to facilitate firmware-first - error handling. +The |TF-A| documentation contains guidance for obtaining and building the +software for existing, supported platforms, as well as supporting information +for porting the software to a new platform. -- A dynamic configuration framework that enables each of the firmware images - to be configured at runtime if required by the platform. It also enables - loading of a hardware configuration (for example, a kernel device tree) - as part of the FIP, to be passed through the firmware stages. +The **About** chapter gives a high-level overview of |TF-A| features as well as +some information on the project and how it is organized. -- Support for alternative boot flows, for example to support platforms where - the EL3 Runtime Software is loaded using other firmware or a separate - secure system processor, or where a non-TF-A ROM expects BL2 to be loaded - at EL3. +Refer to the documents in the **Getting Started** chapter for information about +the prerequisites and requirements for building |TF-A|. -- Support for the GCC, LLVM and Arm Compiler 6 toolchains. +The **Processes & Policies** chapter explains the project's release schedule +and process, how security disclosures are handled, and the guidelines for +contributing to the project (including the coding style). -- Support for combining several libraries into a "romlib" image that may be - shared across images to reduce memory footprint. The romlib image is stored - in ROM but is accessed through a jump-table that may be stored - in read-write memory, allowing for the library code to be patched. +The **Components** chapter holds documents that explain specific components +that make up the |TF-A| software, the :ref:`Exception Handling Framework`, for +example. -- A prototype implementation of a Secure Partition Manager (SPM) that is based - on the SPCI Alpha 1 and SPRT draft specifications. +In the **System Design** chapter you will find documents that explain the +design of portions of the software that involve more than one component, such +as the :ref:`Trusted Board Boot` process. -- Support for ARMv8.3 pointer authentication in the normal and secure worlds. - The use of pointer authentication in the normal world is enabled whenever - architectural support is available, without the need for additional build - flags. Use of pointer authentication in the secure world remains an - experimental configuration at this time and requires the - ``BRANCH_PROTECTION`` option to be set to non-zero. +**Platform Ports** provides a list of the supported hardware and software-model +platforms that are supported upstream in |TF-A|. Most of these platforms also +have additional documentation that has been provided by the maintainers of the +platform. -- Position-Independent Executable (PIE) support. Initially for BL31 only, with - further support to be added in a future release. +The results of any performance evaluations are added to the +**Performance & Testing** chapter. -For a full description of functionality and implementation details, please -see :ref:`Firmware Design` and supporting documentation. The -:ref:`Change Log & Release Notes` provides details of changes made since the -last release. +**Security Advisories** holds a list of documents relating to |CVE| entries that +have previously been raised against the software. Platforms --------- @@ -224,74 +160,17 @@ This release also contains the following platform support: - Texas Instruments K3 SoCs - Xilinx Versal and Zynq UltraScale + MPSoC -Still to come -------------- - -- Support for additional platforms. - -- Refinements to Position Independent Executable (PIE) support. - -- Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT - specifications continue to evolve. - -- Documentation enhancements. - -- Ongoing support for new architectural features, CPUs and System IP. - -- Ongoing support for new Arm system architecture specifications. - -- Ongoing security hardening, optimization and quality improvements. - -For a full list of detailed issues in the current code, please see the -:ref:`Change Log & Release Notes` and the `issue tracker`_. - -Getting started ---------------- - -See the :ref:`User Guide` for instructions on how to download, install, build -and use TF-A with the Arm `FVP`_\ s. - -See the :ref:`Firmware Design` for information on how TF-A works. - -See the :ref:`Porting Guide` as well for information about how to use this -software on another Armv7-A or Armv8-A platform. - -See the :ref:`Contributor's Guide` for information on how to contribute to this -project and the :ref:`Contributor Acknowledgements` file for a list of -contributors to the project. - -Contact Us -~~~~~~~~~~ - -We welcome any feedback on TF-A. If you think you have found a security -vulnerability, please report this using the process defined in the TF-A -:ref:`Security Handling` document. - -For all other feedback, please use the `issue tracker`_ or our `mailing list`_. - -Arm licensees may contact Arm directly via their partner managers. - -------------- *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* .. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile .. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php -.. _Power State Coordination Interface (PSCI): PSCI_ -.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf +.. _Power State Coordination Interface (PSCI): http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf .. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a -.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf -.. _System Control and Management Interface (SCMI): SCMI_ -.. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf -.. _Software Delegated Exception Interface (SDEI): SDEI_ -.. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf +.. _System Control and Management Interface (SCMI): http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf +.. _Software Delegated Exception Interface (SDEI): http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf .. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php -.. _Arm FVP website: FVP_ -.. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms +.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms .. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 -.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os -.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary -.. _Trusty Secure OS: https://source.android.com/security/trusty -.. _trustedfirmware.org: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git -.. _issue tracker: https://issues.trustedfirmware.org -.. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a +.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf diff --git a/docs/maintainers.rst b/docs/maintainers.rst deleted file mode 100644 index 86e445a76..000000000 --- a/docs/maintainers.rst +++ /dev/null @@ -1,316 +0,0 @@ -Maintainers -=========== - -Trusted Firmware-A (TF-A) is an Arm maintained project. All contributions are -ultimately merged by the maintainers listed below. Technical ownership of some -parts of the codebase is delegated to the sub-maintainers listed below. An -acknowledgement from these sub-maintainers may be required before the -maintainers merge a contribution. - -Main maintainers ----------------- -:M: Dan Handley -:G: `danh-arm`_ -:M: Soby Mathew -:G: `soby-mathew`_ -:M: Sandrine Bailleux -:G: `sandrine-bailleux-arm`_ -:M: Alexei Fedorov -:G: `AlexeiFedorov`_ -:M: Paul Beesley -:G: `pbeesley-arm`_ -:M: John Tsichritzis -:G: `jts-arm`_ - -Allwinner ARMv8 platform port ------------------------------ -:M: Andre Przywara -:G: `Andre-ARM`_ -:M: Samuel Holland -:G: `smaeul`_ -:F: docs/plat/allwinner.rst -:F: plat/allwinner/ -:F: drivers/allwinner/ - -Amlogic Meson S905 (GXBB) platform port ---------------------------------------- -:M: Andre Przywara -:G: `Andre-ARM`_ -:F: docs/plat/meson-gxbb.rst -:F: drivers/amlogic/ -:F: plat/amlogic/gxbb/ - -Amlogic Meson S905x (GXL) platform port ---------------------------------------- -:M: Remi Pommarel -:G: `remi-triplefault`_ -:F: docs/plat/meson-gxl.rst -:F: drivers/amlogic/gxl -:F: plat/amlogic/gxl/ - -Amlogic Meson S905X2 (G12A) platform port ------------------------------------------ -:M: Carlo Caione -:G: `carlocaione`_ -:F: docs/plat/meson-g12a.rst -:F: drivers/amlogic/g12a -:F: plat/amlogic/g12a/ - -Armv7-A architecture port -------------------------- -:M: Etienne Carriere -:G: `etienne-lms`_ - -Arm System Guidance for Infrastructure / Mobile FVP platforms -------------------------------------------------------------- -:M: Nariman Poushin -:G: `npoushin`_ -:M: Thomas Abraham -:G: `thomas-arm`_ -:F: plat/arm/css/sgi/ -:F: plat/arm/css/sgm/ -:F: plat/arm/board/sgi575/ -:F: plat/arm/board/sgm775/ - -Console API framework ---------------------- -:M: Julius Werner -:G: `jwerner-chromium`_ -:F: drivers/console/ -:F: include/drivers/console.h -:F: plat/common/aarch64/crash_console_helpers.S - -coreboot support libraries --------------------------- -:M: Julius Werner -:G: `jwerner-chromium`_ -:F: drivers/coreboot/ -:F: include/drivers/coreboot/ -:F: include/lib/coreboot.h -:F: lib/coreboot/ - -eMMC/UFS drivers ----------------- -:M: Haojian Zhuang -:G: `hzhuang1`_ -:F: drivers/partition/ -:F: drivers/synopsys/emmc/ -:F: drivers/synopsys/ufs/ -:F: drivers/ufs/ -:F: include/drivers/dw_ufs.h -:F: include/drivers/ufs.h -:F: include/drivers/synopsys/dw_mmc.h - -HiSilicon HiKey and HiKey960 platform ports -------------------------------------------- -:M: Haojian Zhuang -:G: `hzhuang1`_ -:F: docs/plat/hikey.rst -:F: docs/plat/hikey960.rst -:F: plat/hisilicon/hikey/ -:F: plat/hisilicon/hikey960/ - -HiSilicon Poplar platform port ------------------------------- -:M: Shawn Guo -:G: `shawnguo2`_ -:F: docs/plat/poplar.rst -:F: plat/hisilicon/poplar/ - -Intel SocFPGA platform ports ----------------------------- -:M: Tien Hock Loh -:G: `thloh85-intel`_ -:M: Hadi Asyrafi -:G: mabdulha -:F: plat/intel/soc -:F: drivers/intel/soc/ - -MediaTek platform ports ------------------------ -:M: Yidi Lin (林以廸) -:G: `mtk09422`_ -:F: plat/mediatek/ - -Marvell platform ports and SoC drivers --------------------------------------- -:M: Konstantin Porotchkin -:G: `kostapr`_ -:F: docs/marvell/ -:F: plat/marvell/ -:F: drivers/marvell/ -:F: tools/marvell/ - -NVidia platform ports ---------------------- -:M: Varun Wadekar -:G: `vwadekar`_ -:F: docs/plat/nvidia-tegra.rst -:F: include/lib/cpus/aarch64/denver.h -:F: lib/cpus/aarch64/denver.S -:F: plat/nvidia/ - -NXP QorIQ Layerscape platform ports ------------------------------------ -:M: Jiafei Pan -:G: `qoriq-open-source`_ -:F: docs/plat/ls1043a.rst -:F: plat/layerscape/ - -NXP i.MX 7 WaRP7 platform port and SoC drivers ----------------------------------------------- -:M: Bryan O'Donoghue -:G: `bryanodonoghue`_ -:M: Jun Nie -:G: `niej`_ -:F: docs/plat/warp7.rst -:F: plat/imx/common/ -:F: plat/imx/imx7/ -:F: drivers/imx/timer/ -:F: drivers/imx/uart/ -:F: drivers/imx/usdhc/ - -NXP i.MX 8 platform port ------------------------- -:M: Anson Huang -:G: `Anson-Huang`_ -:F: docs/plat/imx8.rst -:F: plat/imx/ - -NXP i.MX8M platform port ------------------------- -:M: Jacky Bai -:G: `JackyBai`_ -:F: doc/plat/imx8m.rst -:F: plat/imx/imx8m/ - -OP-TEE dispatcher ------------------ -:M: Jens Wiklander -:G: `jenswi-linaro`_ -:F: docs/spd/optee-dispatcher.rst -:F: services/spd/opteed/ - -QEMU platform port ------------------- -:M: Jens Wiklander -:G: `jenswi-linaro`_ -:F: docs/plat/qemu.rst -:F: plat/qemu/ - -Raspberry Pi 3 platform port ----------------------------- -:M: Ying-Chun Liu (PaulLiu) -:G: `grandpaul`_ -:F: docs/plat/rpi3.rst -:F: plat/rpi3/ -:F: drivers/rpi3/ -:F: include/drivers/rpi3/ - -Renesas rcar-gen3 platform port -------------------------------- -:M: Jorge Ramirez-Ortiz -:G: `ldts`_ -:M: Marek Vasut -:G: `marex`_ -:F: docs/plat/rcar-gen3.rst -:F: plat/renesas/rcar -:F: drivers/renesas/rcar -:F: tools/renesas/rcar_layout_create - -RockChip platform port ----------------------- -:M: Tony Xie -:G: `TonyXie06`_ -:G: `rockchip-linux`_ -:M: Heiko Stuebner -:G: `mmind`_ -:F: plat/rockchip/ - -STM32MP1 platform port ----------------------- -:M: Yann Gautier -:G: `Yann-lms`_ -:F: docs/plat/stm32mp1.rst -:F: drivers/st/ -:F: fdts/stm32\* -:F: include/drivers/st/ -:F: include/dt-bindings/\*/stm32\* -:F: plat/st/ -:F: tools/stm32image/ - -Synquacer platform port ------------------------ -:M: Sumit Garg -:G: `b49020`_ -:F: docs/plat/synquacer.rst -:F: plat/socionext/synquacer/ - -Texas Instruments platform port -------------------------------- -:M: Andrew F. Davis -:G: `glneo`_ -:F: docs/plat/ti-k3.rst -:F: plat/ti/ - -TLK/Trusty secure payloads --------------------------- -:M: Varun Wadekar -:G: `vwadekar`_ -:F: docs/spd/tlk-dispatcher.rst -:F: docs/spd/trusty-dispatcher.rst -:F: include/bl32/payloads/tlk.h -:F: services/spd/tlkd/ -:F: services/spd/trusty/ - -UniPhier platform port ----------------------- -:M: Masahiro Yamada -:G: `masahir0y`_ -:F: docs/plat/socionext-uniphier.rst -:F: plat/socionext/uniphier/ - -Xilinx platform port --------------------- -:M: Siva Durga Prasad Paladugu -:G: `sivadur`_ -:F: docs/plat/xilinx-zynqmp.rst -:F: plat/xilinx/ - -.. _AlexeiFedorov: https://github.com/AlexeiFedorov -.. _Andre-ARM: https://github.com/Andre-ARM -.. _Anson-Huang: https://github.com/Anson-Huang -.. _bryanodonoghue: https://github.com/bryanodonoghue -.. _b49020: https://github.com/b49020 -.. _carlocaione: https://github.com/carlocaione -.. _danh-arm: https://github.com/danh-arm -.. _etienne-lms: https://github.com/etienne-lms -.. _glneo: https://github.com/glneo -.. _grandpaul: https://github.com/grandpaul -.. _hzhuang1: https://github.com/hzhuang1 -.. _JackyBai: https://github.com/JackyBai -.. _jenswi-linaro: https://github.com/jenswi-linaro -.. _jts-arm: https://github.com/jts-arm -.. _jwerner-chromium: https://github.com/jwerner-chromium -.. _kostapr: https://github.com/kostapr -.. _ldts: https://github.com/ldts -.. _marex: https://github.com/marex -.. _masahir0y: https://github.com/masahir0y -.. _mmind: https://github.com/mmind -.. _mtk09422: https://github.com/mtk09422 -.. _niej: https://github.com/niej -.. _npoushin: https://github.com/npoushin -.. _pbeesley-arm: https://github.com/pbeesley-arm -.. _qoriq-open-source: https://github.com/qoriq-open-source -.. _remi-triplefault: https://github.com/repk -.. _rockchip-linux: https://github.com/rockchip-linux -.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm -.. _shawnguo2: https://github.com/shawnguo2 -.. _sivadur: https://github.com/sivadur -.. _smaeul: https://github.com/smaeul -.. _soby-mathew: https://github.com/soby-mathew -.. _thloh85-intel: https://github.com/thloh85-intel -.. _thomas-arm: https://github.com/thomas-arm -.. _TonyXie06: https://github.com/TonyXie06 -.. _vwadekar: https://github.com/vwadekar -.. _Yann-lms: https://github.com/Yann-lms diff --git a/docs/process/index.rst b/docs/process/index.rst index a870c8f57..9c12de82f 100644 --- a/docs/process/index.rst +++ b/docs/process/index.rst @@ -6,7 +6,6 @@ Processes & Policies :caption: Contents :numbered: - release-information security platform-compatibility-policy coding-guidelines diff --git a/docs/process/release-information.rst b/docs/process/release-information.rst deleted file mode 100644 index e264e51ad..000000000 --- a/docs/process/release-information.rst +++ /dev/null @@ -1,82 +0,0 @@ -Release Processes -================= - -Project Release Cadence ------------------------ - -The project currently aims to do a release once every 6 months which will be -tagged on the master branch. There will be a code freeze (stop merging -non-essential PRs) up to 4 weeks prior to the target release date. The release -candidates will start appearing after this and only bug fixes or updates -required for the release will be merged. The maintainers are free to use their -judgement on what PRs are essential for the release. A release branch may be -created after code freeze if there are significant PRs that need merging onto -the integration branch during the merge window. - -The release testing will be performed on release candidates and depending on -issues found, additional release candidates may be created to fix the issues. - -:: - - |<----------6 months---------->| - |<---4 weeks--->| |<---4 weeks--->| - +-----------------------------------------------------------> time - | | | | - code freeze ver w.x code freeze ver y.z - - -Upcoming Releases -~~~~~~~~~~~~~~~~~ - -These are the estimated dates for the upcoming release. These may change -depending on project requirement and partner feedback. - -+-----------------+---------------------------+------------------------------+ -| Release Version | Target Date | Expected Code Freeze | -+=================+===========================+==============================+ -| v2.0 | 1st week of Oct '18 | 1st week of Sep '18 | -+-----------------+---------------------------+------------------------------+ -| v2.1 | 5th week of Mar '19 | 1st week of Mar '19 | -+-----------------+---------------------------+------------------------------+ - -Removal of Deprecated Interfaces --------------------------------- - -As mentioned in the :ref:`Platform Compatibility Policy`, this is a live -document cataloging all the deprecated interfaces in TF-A project and the -Release version after which it will be removed. - -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| Interface | Deprecation | Removed | Comments | -| | Date | after | | -| | | Release | | -+================================+=============+=========+=========================================================+ -| Legacy Console API | Jan '18 | v2.1 | Deprecated in favour of ``MULTI_CONSOLE_API`` | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| Weak default | Oct '18 | v2.1 | The default implementations are defined in | -| ``plat_crash_console_*`` | | | ``crash_console_helpers.S``. The platforms have to | -| APIs | | | define ``plat_crash_console_*``. | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| ``finish_console_register`` | Oct '18 | v2.1 | The old version of the macro is deprecated. See commit | -| macro in | | | cc5859c_ for more details. | -| ``MULTI_CONSOLE_API`` | | | | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| Types ``tzc_action_t`` and | Oct '18 | v2.1 | Using logical operations such as OR in enumerations | -| ``tzc_region_attributes_t`` | | | goes against the MISRA guidelines. | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| Macro ``EL_IMPLEMENTED()`` | Oct '18 | v2.1 | Deprecated in favour of ``el_implemented()``. | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| ``get_afflvl_shift()``, | Dec '18 | v2.1 | Removed. | -| ``mpidr_mask_lower_afflvls()``,| | | | -| and ``eret()``. | | | | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| Extra include paths in the | Jan '18 | v2.1 | Now it is needed to use the full path of the common | -| Makefile in ``INCLUDES``. | | | header files. More information in commit 09d40e0e0828_. | -+--------------------------------+-------------+---------+---------------------------------------------------------+ - --------------- - -*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.* - -.. _cc5859c: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=cc5859ca19ff546c35eb0331000dae090b6eabcf -.. _09d40e0e0828: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=09d40e0e08283a249e7dce0e106c07c5141f9b7e -- cgit v1.2.3 From 5e6b4163905563be5dee7303c66188180af33500 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Wed, 16 Oct 2019 13:41:13 +0000 Subject: doc: Move platform list to the Platform Ports index page The list of upstream platforms on the index page is growing quite long, especially with all the FVP variants being listed individually. This patch leverages the "Platform Ports" chapter in the docs table of contents to condense this information. Almost all platform ports now have documentation, so the table of contents serves as the list of upstream platforms by itself. For those upstream platforms that do not have corresponding documentation, the top-level "Platform Ports" page mentions them individually. It also mentions each Arm FVP, just as the index page did before. Note that there is an in-progress patch that creates new platform port documentation for the Arm Juno and Arm FVP platforms, so this list of "other platforms" will soon be reduced further as those platforms become part of the table of contents as well. Change-Id: I6b1eab8cba71a599d85a6e22553a34b07f213268 Signed-off-by: Paul Beesley --- docs/index.rst | 84 ----------------------------------------------------- docs/plat/index.rst | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+), 84 deletions(-) diff --git a/docs/index.rst b/docs/index.rst index 8981072a5..baadd42cf 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -79,87 +79,6 @@ The results of any performance evaluations are added to the **Security Advisories** holds a list of documents relating to |CVE| entries that have previously been raised against the software. -Platforms ---------- - -Various AArch32 and AArch64 builds of this release have been tested on r0, r1 -and r2 variants of the `Juno Arm Development Platform`_. - -The latest version of the AArch64 build of TF-A has been tested on the following -Arm FVPs without shifted affinities, and that do not support threaded CPU cores -(64-bit host machine only). - -.. note:: - The FVP models used are Version 11.6 Build 45, unless otherwise stated. - -- ``FVP_Base_AEMv8A-AEMv8A`` -- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` -- ``FVP_Base_RevC-2xAEMv8A`` -- ``FVP_Base_Cortex-A32x4`` -- ``FVP_Base_Cortex-A35x4`` -- ``FVP_Base_Cortex-A53x4`` -- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` -- ``FVP_Base_Cortex-A55x4`` -- ``FVP_Base_Cortex-A57x1-A53x1`` -- ``FVP_Base_Cortex-A57x2-A53x4`` -- ``FVP_Base_Cortex-A57x4-A53x4`` -- ``FVP_Base_Cortex-A57x4`` -- ``FVP_Base_Cortex-A72x4-A53x4`` -- ``FVP_Base_Cortex-A72x4`` -- ``FVP_Base_Cortex-A73x4-A53x4`` -- ``FVP_Base_Cortex-A73x4`` -- ``FVP_Base_Cortex-A75x4`` -- ``FVP_Base_Cortex-A76x4`` -- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model) -- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model) -- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) -- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model) -- ``FVP_CSS_SGI-575`` (Version 11.3 build 42) -- ``FVP_CSS_SGM-775`` (Version 11.3 build 42) -- ``FVP_RD_E1Edge`` (Version 11.3 build 42) -- ``FVP_RD_N1Edge`` (Version 11.3 build 42) -- ``Foundation_Platform`` - -The latest version of the AArch32 build of TF-A has been tested on the following -Arm FVPs without shifted affinities, and that do not support threaded CPU cores -(64-bit host machine only). - -- ``FVP_Base_AEMv8A-AEMv8A`` -- ``FVP_Base_Cortex-A32x4`` - -.. note:: - The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities. - -The Foundation FVP can be downloaded free of charge. The Base FVPs can be -licensed from Arm. See the `Arm FVP website`_. - -All the above platforms have been tested with `Linaro Release 19.06`_. - -This release also contains the following platform support: - -- Allwinner sun50i_a64 and sun50i_h6 -- Amlogic Meson S905 (GXBB) -- Arm Juno Software Development Platform -- Arm Neoverse N1 System Development Platform (N1SDP) -- Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP -- Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP -- Arm SGI-575 and SGM-775 -- Arm Versatile Express FVP -- HiKey, HiKey960 and Poplar boards -- Intel Stratix 10 SoC FPGA -- Marvell Armada 3700 and 8K -- MediaTek MT6795 and MT8173 SoCs -- NVIDIA T132, T186 and T210 SoCs -- NXP QorIQ LS1043A, i.MX8MM, i.MX8MQ, i.MX8QX, i.MX8QM and i.MX7Solo WaRP7 -- QEMU -- Raspberry Pi 3 -- Renesas R-Car Generation 3 -- RockChip RK3328, RK3368 and RK3399 SoCs -- Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs -- STMicroelectronics STM32MP1 -- Texas Instruments K3 SoCs -- Xilinx Versal and Zynq UltraScale + MPSoC - -------------- *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* @@ -170,7 +89,4 @@ This release also contains the following platform support: .. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a .. _System Control and Management Interface (SCMI): http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf .. _Software Delegated Exception Interface (SDEI): http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf -.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php -.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms -.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 .. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf diff --git a/docs/plat/index.rst b/docs/plat/index.rst index d0b4827bb..572963513 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -5,6 +5,7 @@ Platform Ports :maxdepth: 1 :caption: Contents :numbered: + :hidden: allwinner meson-gxbb @@ -35,3 +36,82 @@ Platform Ports ti-k3 xilinx-versal xilinx-zynqmp + +This section provides a list of supported upstream *platform ports* and the +documentation associated with them. The list of suported Arm |FVP| platforms is +outlined in the following section. + +.. note:: + In addition to the platforms ports listed within the table of contents, there + are several additional platforms that are supported upstream but which do not + currently have associated documentation: + + - Arm Juno Software Development Platform. Various |AArch32| and |AArch64| + builds of this release have been tested on r0, r1 and r2 variants of the + `Juno Arm Development Platform`_. + - Arm Neoverse N1 System Development Platform (N1SDP) + - Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP + - Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP + - Arm SGI-575 and SGM-775 + - MediaTek MT6795 and MT8173 SoCs + +Fixed Virtual Platform (FVP) Support +------------------------------------ + +The latest version of the AArch64 build of TF-A has been tested on the +following Arm FVPs without shifted affinities, and that do not support threaded +CPU cores (64-bit host machine only). + +.. note:: + The FVP models used are Version 11.6 Build 45, unless otherwise stated. + +- ``FVP_Base_AEMv8A-AEMv8A`` +- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` +- ``FVP_Base_RevC-2xAEMv8A`` +- ``FVP_Base_Cortex-A32x4`` +- ``FVP_Base_Cortex-A35x4`` +- ``FVP_Base_Cortex-A53x4`` +- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` +- ``FVP_Base_Cortex-A55x4`` +- ``FVP_Base_Cortex-A57x1-A53x1`` +- ``FVP_Base_Cortex-A57x2-A53x4`` +- ``FVP_Base_Cortex-A57x4-A53x4`` +- ``FVP_Base_Cortex-A57x4`` +- ``FVP_Base_Cortex-A72x4-A53x4`` +- ``FVP_Base_Cortex-A72x4`` +- ``FVP_Base_Cortex-A73x4-A53x4`` +- ``FVP_Base_Cortex-A73x4`` +- ``FVP_Base_Cortex-A75x4`` +- ``FVP_Base_Cortex-A76x4`` +- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model) +- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model) +- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) +- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model) +- ``FVP_CSS_SGI-575`` (Version 11.3 build 42) +- ``FVP_CSS_SGM-775`` (Version 11.3 build 42) +- ``FVP_RD_E1Edge`` (Version 11.3 build 42) +- ``FVP_RD_N1Edge`` (Version 11.3 build 42) +- ``Foundation_Platform`` + +The latest version of the AArch32 build of TF-A has been tested on the +following Arm FVPs without shifted affinities, and that do not support threaded +CPU cores (64-bit host machine only). + +- ``FVP_Base_AEMv8A-AEMv8A`` +- ``FVP_Base_Cortex-A32x4`` + +.. note:: + The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities. + +The *Foundation* FVP can be downloaded free of charge. The *Base* FVPs can be +licensed from Arm. See the `Arm FVP website`_. + +All the above platforms have been tested with `Linaro Release 19.06`_. + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* + +.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php +.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms +.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 -- cgit v1.2.3 From 77caea29607747f9c75c6293f6b12a9c4cbef3a6 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Fri, 11 Oct 2019 14:10:09 -0500 Subject: Update change log for v2.2 Release Signed-off-by: Lauren Wehrmeister Change-Id: I53a7706016539e7de7fdbe87b786d99665bbe1d8 --- docs/change-log.rst | 416 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 416 insertions(+) diff --git a/docs/change-log.rst b/docs/change-log.rst index 0a89aa6f8..a0db2a9bd 100644 --- a/docs/change-log.rst +++ b/docs/change-log.rst @@ -4,6 +4,422 @@ Change Log & Release Notes This document contains a summary of the new features, changes, fixes and known issues in each release of Trusted Firmware-A. +Version 2.2 +----------- + +New Features +^^^^^^^^^^^^ + +- Architecture + - Enable Pointer Authentication (PAuth) support for Secure World + - Adds support for ARMv8.3-PAuth in BL1 SMC calls and + BL2U image for firmware updates. + + - Enable Memory Tagging Extension (MTE) support in both secure and non-secure + worlds + - Adds support for the new Memory Tagging Extension arriving in + ARMv8.5. MTE support is now enabled by default on systems that + support it at EL0. + - To enable it at ELx for both the non-secure and the secure + world, the compiler flag ``CTX_INCLUDE_MTE_REGS`` includes register + saving and restoring when necessary in order to prevent information + leakage between the worlds. + + - Add support for Branch Target Identification (BTI) + +- Build System + - Modify FVP makefile for CPUs that support both AArch64/32 + + - AArch32: Allow compiling with soft-float toolchain + + - Makefile: Add default warning flags + + - Add Makefile check for PAuth and AArch64 + + - Add compile-time errors for HW_ASSISTED_COHERENCY flag + + - Apply compile-time check for AArch64-only CPUs + + - build_macros: Add mechanism to prevent bin generation. + + - Add support for default stack-protector flag + + - spd: opteed: Enable NS_TIMER_SWITCH + + - plat/arm: Skip BL2U if RESET_TO_SP_MIN flag is set + + - Add new build option to let each platform select which implementation of spinlocks + it wants to use + +- CPU Support + - DSU: Workaround for erratum 798953 and 936184 + + - Neoverse N1: Force cacheable atomic to near atomic + - Neoverse N1: Workaround for erratum 1073348, 1130799, 1165347, 1207823, + 1220197, 1257314, 1262606, 1262888, 1275112, 1315703, 1542419 + + - Neoverse Zeus: Apply the MSR SSBS instruction + + - cortex-a76AE: Support added for Cortex-A76AE CPU + - cortex-a76: Workaround for erratum 1257314, 1262606, 1262888, 1275112, + 1286807 + + - cortex-a65/a65AE: Support added for Cortex-A65 and Cortex-A65AE CPUs + - cortex-a65: Enable AMU for Cortex-A65 + + - cortex-a55: Workaround for erratum 1221012 + + - cortex-a35: Workaround for erratum 855472 + + - cortex-a9: Workaround for erratum 794073 + +- Drivers + - console: Allow the console to register multiple times + + - delay: Timeout detection support + + - gicv3: Enabled multi-socket GIC redistributor frame discovery and migrated + ARM platforms to the new API + - Adds ``gicv3_rdistif_probe`` function that delegates the responsibility + of discovering the corresponding redistributor base frame to each CPU + itself. + + - sbsa: Add SBSA watchdog driver + + - st/stm32_hash: Add HASH driver + + - ti/uart: Add an AArch32 variant + +- Library at ROM (romlib) + - Introduce BTI support in Library at ROM (romlib) + +- New Platforms Support + - amlogic: g12a: New platform support added for the S905X2 (G12A) platform + - amlogic: meson/gxl: New platform support added for Amlogic Meson + S905x (GXL) + + - arm/a5ds: New platform support added for A5 DesignStart + + - arm/corstone: New platform support added for Corstone-700 + + - intel: New platform support added for Agilex + + - mediatek: New platform support added for MediaTek mt8183 + + - qemu/qemu_sbsa: New platform support added for QEMU SBSA platform + + - renesas/rcar_gen3: plat: New platform support added for D3 + + - rockchip: New platform support added for px30 + - rockchip: New platform support added for rk3288 + + - rpi: New platform support added for Raspberry Pi 4 + +- Platforms + - arm/common: Introduce wrapper functions to setup secure watchdog + + - arm/fvp: Add Delay Timer driver to BL1 and BL31 and option for defining + platform DRAM2 base + - arm/fvp: Add Linux DTS files for 32 bit threaded FVPs + + - arm/n1sdp: Add code for DDR ECC enablement and BL33 copy to DDR, Initialise CNTFRQ + in Non Secure CNTBaseN + + - arm/juno: Use shared mbedtls heap between BL1 and BL2 and add basic support for + dynamic config + + - imx: Basic support for PicoPi iMX7D, rdc module init, caam module init, + aipstz init, IMX_SIP_GET_SOC_INFO, IMX_SIP_BUILDINFO added + + - intel: Add ncore ccu driver + + - mediatek/mt81*: Use new bl31_params_parse() helper + + - nvidia: tegra: Add support for multi console interface + + - qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1 + - qemu: Added gicv3 support, new console interface in AArch32, and sub-platforms + + - renesas/rcar_gen3: plat: Add R-Car V3M support, new board revision for H3ULCB, DBSC4 + setting before self-refresh mode + + - socionext/uniphier: Support console based on multi-console + + - st: stm32mp1: Add OP-TEE, Avenger96, watchdog, LpDDR3, authentication support + and general SYSCFG management + + - ti/k3: common: Add support for J721E, Use coherent memory for shared data, Trap all + asynchronous bus errors to EL3 + + - xilinx/zynqmp: Add support for multi console interface, Initialize IPI table from + zynqmp_config_setup() + +- PSCI + - Adding new optional PSCI hook ``pwr_domain_on_finish_late`` + - This PSCI hook ``pwr_domain_on_finish_late`` is similar to + ``pwr_domain_on_finish`` but is guaranteed to be invoked when the + respective core and cluster are participating in coherency. + +- Security + - Speculative Store Bypass Safe (SSBS): Further enhance protection against Spectre + variant 4 by disabling speculative loads/stores (SPSR.SSBS bit) by default. + + - UBSAN support and handlers + - Adds support for the Undefined Behaviour sanitizer. There are two types of + support offered - minimalistic trapping support which essentially immediately + crashes on undefined behaviour and full support with full debug messages. + +- Tools + - cert_create: Add support for bigger RSA key sizes (3KB and 4KB), + previously the maximum size was 2KB. + + - fiptool: Add support to build fiptool on Windows. + + +Changed +^^^^^^^ + +- Architecture + - Refactor ARMv8.3 Pointer Authentication support code + + - backtrace: Strip PAC field when PAUTH is enabled + + - Prettify crash reporting output on AArch64. + + - Rework smc_unknown return code path in smc_handler + - Leverage the existing ``el3_exit()`` return routine for smc_unknown return + path rather than a custom set of instructions. + +- BL-Specific + - Invalidate dcache build option for BL2 entry at EL3 + + - Add missing support for BL2_AT_EL3 in XIP memory + +- Boot Flow + - Add helper to parse BL31 parameters (both versions) + + - Factor out cross-BL API into export headers suitable for 3rd party code + + - Introduce lightweight BL platform parameter library + +- Drivers + - auth: Memory optimization for Chain of Trust (CoT) description + + - bsec: Move bsec_mode_is_closed_device() service to platform + + - cryptocell: Move Cryptocell specific API into driver + + - gicv3: Prevent pending G1S interrupt from becoming G0 interrupt + + - mbedtls: Remove weak heap implementation + + - mmc: Increase delay between ACMD41 retries + - mmc: stm32_sdmmc2: Correctly manage block size + - mmc: stm32_sdmmc2: Manage max-frequency property from DT + + - synopsys/emmc: Do not change FIFO TH as this breaks some platforms + - synopsys: Update synopsys drivers to not rely on undefined overflow behaviour + + - ufs: Extend the delay after reset to wait for some slower chips + +- Platforms + - amlogic/meson/gxl: Remove BL2 dependency from BL31 + + - arm/common: Shorten the Firmware Update (FWU) process + + - arm/fvp: Remove GIC initialisation from secondary core cold boot + + - arm/sgm: Temporarily disable shared Mbed TLS heap for SGM + + - hisilicon: Update hisilicon drivers to not rely on undefined overflow behaviour + + - imx: imx8: Replace PLAT_IMX8* with PLAT_imx8*, remove duplicated linker symbols and + deprecated code include, keep only IRQ 32 unmasked, enable all power domain by default + + - marvell: Prevent SError accessing PCIe link, Switch to xlat_tables_v2, do not rely on + argument passed via smc, make sure that comphy init will use correct address + + - mediatek: mt8173: Refactor RTC and PMIC drivers + - mediatek: mt8173: Apply MULTI_CONSOLE framework + + - nvidia: Tegra: memctrl_v2: fix "overflow before widen" coverity issue + + - qemu: Simplify the image size calculation, Move and generalise FDT PSCI fixup, move + gicv2 codes to separate file + + - renesas/rcar_gen3: Convert to multi-console API, update QoS setting, Update IPL and + Secure Monitor Rev2.0.4, Change to restore timer counter value at resume, Update DDR + setting rev.0.35, qos: change subslot cycle, Change periodic write DQ training option. + + - rockchip: Allow SOCs with undefined wfe check bits, Streamline and complete UARTn_BASE + macros, drop rockchip-specific imported linker symbols for bl31, Disable binary generation + for all SOCs, Allow console device to be set by DTB, Use new bl31_params_parse functions + + - rpi/rpi3: Move shared rpi3 files into common directory + + - socionext/uniphier: Set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driver + - socionext/uniphier: Replace DIV_ROUND_UP() with div_round_up() from utils_def.h + + - st/stm32mp: Split stm32mp_io_setup function, move stm32_get_gpio_bank_clock() to private + file, correctly handle Clock Spreading Generator, move oscillator functions to generic file, + realign device tree files with internal devs, enable RTCAPB clock for dual-core chips, use a + common function to check spinlock is available, move check_header() to common code + + - ti/k3: Enable SEPARATE_CODE_AND_RODATA by default, Remove shared RAM space, + Drop _ADDRESS from K3_USART_BASE to match other defines, Remove MSMC port + definitions, Allow USE_COHERENT_MEM for K3, Set L2 latency on A72 cores + +- PSCI + - PSCI: Lookup list of parent nodes to lock only once + +- Secure Partition Manager (SPM): SPCI Prototype + - Fix service UUID lookup + + - Adjust size of virtual address space per partition + + - Refactor xlat context creation + + - Move shim layer to TTBR1_EL1 + + - Ignore empty regions in resource description + +- Security + - Refactor SPSR initialisation code + + - SMMUv3: Abort DMA transactions + - For security DMA should be blocked at the SMMU by default unless explicitly + enabled for a device. SMMU is disabled after reset with all streams bypassing + the SMMU, and abortion of all incoming transactions implements a default deny + policy on reset. + - Moves ``bl1_platform_setup()`` function from arm_bl1_setup.c to FVP platforms' + fvp_bl1_setup.c and fvp_ve_bl1_setup.c files. + +- Tools + - cert_create: Remove RSA PKCS#1 v1.5 support + + +Resolved Issues +^^^^^^^^^^^^^^^ + +- Architecture + - Fix the CAS spinlock implementation by adding a missing DSB in ``spin_unlock()`` + + - AArch64: Fix SCTLR bit definitions + - Removes incorrect ``SCTLR_V_BIT`` definition and adds definitions for + ARMv8.3-Pauth `EnIB`, `EnDA` and `EnDB` bits. + + - Fix restoration of PAuth context + - Replace call to ``pauth_context_save()`` with ``pauth_context_restore()`` in + case of unknown SMC call. + +- BL-Specific Issues + - Fix BL31 crash reporting on AArch64 only platforms + +- Build System + - Remove several warnings reported with W=2 and W=1 + +- Code Quality Issues + - SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64 + - Unify type of "cpu_idx" across PSCI module. + - Assert if power level value greater then PSCI_INVALID_PWR_LVL + - Unsigned long should not be used as per coding guidelines + - Reduce the number of memory leaks in cert_create + - Fix type of cot_desc_ptr + - Use explicit-width data types in AAPCS parameter structs + - Add python configuration for editorconfig + - BL1: Fix type consistency + + - Enable -Wshift-overflow=2 to check for undefined shift behavior + - Updated upstream platforms to not rely on undefined overflow behaviour + +- Coverity Quality Issues + - Remove GGC ignore -Warray-bounds + - Fix Coverity #261967, Infinite loop + - Fix Coverity #343017, Missing unlock + - Fix Coverity #343008, Side affect in assertion + - Fix Coverity #342970, Uninitialized scalar variable + +- CPU Support + - cortex-a12: Fix MIDR mask + +- Drivers + - console: Remove Arm console unregister on suspend + + - gicv3: Fix support for full SPI range + + - scmi: Fix wrong payload length + +- Library Code + - libc: Fix sparse warning for __assert() + + - libc: Fix memchr implementation + +- Platforms + - rpi: rpi3: Fix compilation error when stack protector is enabled + + - socionext/uniphier: Fix compilation fail for SPM support build config + + - st/stm32mp1: Fix TZC400 configuration against non-secure DDR + + - ti/k3: common: Fix RO data area size calculation + +- Security + - AArch32: Disable Secure Cycle Counter + - Changes the implementation for disabling Secure Cycle Counter. + For ARMv8.5 the counter gets disabled by setting ``SDCR.SCCD`` bit on + CPU cold/warm boot. For the earlier architectures PMCR register is + saved/restored on secure world entry/exit from/to Non-secure state, + and cycle counting gets disabled by setting PMCR.DP bit. + - AArch64: Disable Secure Cycle Counter + - For ARMv8.5 the counter gets disabled by setting ``MDCR_El3.SCCD`` bit on + CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is + saved/restored on secure world entry/exit from/to Non-secure state, + and cycle counting gets disabled by setting PMCR_EL0.DP bit. + +Deprecations +^^^^^^^^^^^^ + +- Common Code + - Remove MULTI_CONSOLE_API flag and references to it + + - Remove deprecated `plat_crash_console_*` + + - Remove deprecated interfaces `get_afflvl_shift`, `mpidr_mask_lower_afflvls`, `eret` + + - AARCH32/AARCH64 macros are now deprecated in favor of ``__aarch64__`` + + - ``__ASSEMBLY__`` macro is now deprecated in favor of ``__ASSEMBLER__`` + +- Drivers + - console: Removed legacy console API + - console: Remove deprecated finish_console_register + + - tzc: Remove deprecated types `tzc_action_t` and `tzc_region_attributes_t` + +- Secure Partition Manager (SPM): + - Prototype SPCI-based SPM (services/std_svc/spm) will be replaced with alternative + methods of secure partitioning support. + +Known Issues +^^^^^^^^^^^^ + +- Build System Issues + - dtb: DTB creation not supported when building on a Windows host. + + This step in the build process is skipped when running on a Windows host. A + known issue from the 1.6 release. + +- Platform Issues + - arm/juno: System suspend from Linux does not function as documented in the + user guide + + Following the instructions provided in the user guide document does not + result in the platform entering system suspend state as expected. A message + relating to the hdlcd driver failing to suspend will be emitted on the + Linux terminal. + + - mediatek/mt6795: This platform does not build in this release + Version 2.1 ----------- -- cgit v1.2.3 From 48730856e8b44bc46f8c0e76ec4d984c5f1844f2 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Wed, 16 Oct 2019 13:48:12 +0000 Subject: doc: Expand contact information in About section Giving a bit more background information about the issue tracker and mailing lists. Change-Id: I68921d54e3113d348f1e16c685f74d32df2ca19f Signed-off-by: Paul Beesley --- docs/about/contact.rst | 44 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 37 insertions(+), 7 deletions(-) diff --git a/docs/about/contact.rst b/docs/about/contact.rst index af6668dda..9cb25ef47 100644 --- a/docs/about/contact.rst +++ b/docs/about/contact.rst @@ -1,16 +1,46 @@ Support & Contact ----------------- -We welcome any feedback on TF-A. If you think you have found a security -vulnerability, please report this using the process defined in the TF-A -:ref:`Security Handling` document. +We welcome any feedback on |TF-A| and there are several methods for providing +it or for obtaining support. -For all other feedback, please use the `issue tracker`_ or our `mailing list`_. +.. warning:: + If you think you have found a security vulnerability, please report this using + the process defined in the :ref:`Security Handling` document. -Arm licensees may contact Arm directly via their partner managers. +Mailing Lists +^^^^^^^^^^^^^ -.. _issue tracker: https://issues.trustedfirmware.org -.. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a +Public mailing lists for TF-A and the wider Trusted Firmware project are +hosted on TrustedFirmware.org. The mailing lists can be used for general +enquiries, enhancement requests and issue reports, or to follow and participate +in technical or organizational discussions around the project. These discussions +include design proposals, advance notice of changes and upcoming events. + +The relevant lists for the TF-A project are: + +- `TF-A development`_ +- `TF-A-Tests development`_ + +You can see a `summary of all the lists`_ on the TrustedFirmware.org website. + +Issue Tracker +^^^^^^^^^^^^^ + +Specific issues may be raised using the `issue tracker`_ on the +TrustedFirmware.org website. Using this tracker makes it easy for the +maintainers to prioritise and respond to your ticket. + +Arm Licensees +^^^^^^^^^^^^^ + +Arm licensees have an additional support conduit - they may contact Arm directly +via their partner managers. + +.. _`issue tracker`: https://developer.trustedfirmware.org +.. _`TF-A development`: https://lists.trustedfirmware.org/pipermail/tf-a/ +.. _`TF-A-Tests development`: https://lists.trustedfirmware.org/pipermail/tf-a-tests/ +.. _`summary of all the lists`: https://lists.trustedfirmware.org -------------- -- cgit v1.2.3 From e69f3500381638eca41152589ea78169f48aa191 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Wed, 16 Oct 2019 16:32:16 -0500 Subject: Update release-information for v2.2 Release Removed deprecated interfaces that have been removed from the TF-A project, updated the deprecated list with new deprecations for v2.2 Release, added upcoming release information, remove mentions of PR from github. Signed-off-by: Lauren Wehrmeister Signed-off-by: Paul Beesley Change-Id: I2b59d351cde9860ad0dcb6520a8bd2827ad403cf --- docs/about/release-information.rst | 36 +++++++++++------------------------- 1 file changed, 11 insertions(+), 25 deletions(-) diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst index e264e51ad..c230e605d 100644 --- a/docs/about/release-information.rst +++ b/docs/about/release-information.rst @@ -6,11 +6,11 @@ Project Release Cadence The project currently aims to do a release once every 6 months which will be tagged on the master branch. There will be a code freeze (stop merging -non-essential PRs) up to 4 weeks prior to the target release date. The release +non-essential changes) up to 4 weeks prior to the target release date. The release candidates will start appearing after this and only bug fixes or updates required for the release will be merged. The maintainers are free to use their -judgement on what PRs are essential for the release. A release branch may be -created after code freeze if there are significant PRs that need merging onto +judgement on what changes are essential for the release. A release branch may be +created after code freeze if there are significant changes that need merging onto the integration branch during the merge window. The release testing will be performed on release candidates and depending on @@ -38,6 +38,10 @@ depending on project requirement and partner feedback. +-----------------+---------------------------+------------------------------+ | v2.1 | 5th week of Mar '19 | 1st week of Mar '19 | +-----------------+---------------------------+------------------------------+ +| v2.2 | 4th week of Oct '19 | 1st week of Oct '19 | ++-----------------+---------------------------+------------------------------+ +| v2.3 | 4th week of Mar '20 | 1st week of Mar '20 | ++-----------------+---------------------------+------------------------------+ Removal of Deprecated Interfaces -------------------------------- @@ -51,32 +55,14 @@ Release version after which it will be removed. | | Date | after | | | | | Release | | +================================+=============+=========+=========================================================+ -| Legacy Console API | Jan '18 | v2.1 | Deprecated in favour of ``MULTI_CONSOLE_API`` | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| Weak default | Oct '18 | v2.1 | The default implementations are defined in | -| ``plat_crash_console_*`` | | | ``crash_console_helpers.S``. The platforms have to | -| APIs | | | define ``plat_crash_console_*``. | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| ``finish_console_register`` | Oct '18 | v2.1 | The old version of the macro is deprecated. See commit | -| macro in | | | cc5859c_ for more details. | -| ``MULTI_CONSOLE_API`` | | | | +| ``AARCH32``/``AARCH64`` macros | Oct '19 | v2.3 | Deprecated in favor of ``__aarch64__`` | +--------------------------------+-------------+---------+---------------------------------------------------------+ -| Types ``tzc_action_t`` and | Oct '18 | v2.1 | Using logical operations such as OR in enumerations | -| ``tzc_region_attributes_t`` | | | goes against the MISRA guidelines. | +| ``__ASSEMBLY__`` macro | Oct '19 | v2.3 | Deprecated in favor of ``__ASSEMBLER__`` | +--------------------------------+-------------+---------+---------------------------------------------------------+ -| Macro ``EL_IMPLEMENTED()`` | Oct '18 | v2.1 | Deprecated in favour of ``el_implemented()``. | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| ``get_afflvl_shift()``, | Dec '18 | v2.1 | Removed. | -| ``mpidr_mask_lower_afflvls()``,| | | | -| and ``eret()``. | | | | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| Extra include paths in the | Jan '18 | v2.1 | Now it is needed to use the full path of the common | -| Makefile in ``INCLUDES``. | | | header files. More information in commit 09d40e0e0828_. | +| Prototype SPCI-based SPM | Oct '19 | v2.2 | Based on outdated Alpha 1 spec. Will be replaced with | +| (services/std_svc/spm) | | | alternative methods of secure partitioning support. | +--------------------------------+-------------+---------+---------------------------------------------------------+ -------------- *Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.* - -.. _cc5859c: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=cc5859ca19ff546c35eb0331000dae090b6eabcf -.. _09d40e0e0828: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=09d40e0e08283a249e7dce0e106c07c5141f9b7e -- cgit v1.2.3 From bbf0a1e43479ccfcbb0229cca744d17165749dce Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Mon, 21 Oct 2019 16:37:13 +0000 Subject: doc: Final, pre-release fixes and updates A small set of misc changes to ensure correctness before the v2.2 release tagging. Change-Id: I888840b9483ea1a1633d204fbbc0f9594072101e Signed-off-by: Paul Beesley --- .editorconfig | 7 ++----- docs/about/acknowledgements.rst | 3 ++- docs/about/features.rst | 8 ++++---- docs/about/maintainers.rst | 6 +++--- docs/getting_started/user-guide.rst | 1 + docs/plat/index.rst | 5 +++-- 6 files changed, 15 insertions(+), 15 deletions(-) diff --git a/.editorconfig b/.editorconfig index b14e0253b..f523ca19d 100644 --- a/.editorconfig +++ b/.editorconfig @@ -54,13 +54,10 @@ tab_width = 8 trim_trailing_whitespace = true -# Adjustment for existing .rst files with different format -[*.{rst,md}] +# Adjustment for ReStructuredText (RST) documentation +[*.{rst}] indent_size = 4 indent_style = space -max_line_length = 180 -# 180 only selected to prevent changes to existing text. -tab_width = 4 # Adjustment for python which prefers a different style diff --git a/docs/about/acknowledgements.rst b/docs/about/acknowledgements.rst index a9f64511f..dfc66c8f7 100644 --- a/docs/about/acknowledgements.rst +++ b/docs/about/acknowledgements.rst @@ -6,7 +6,8 @@ Contributor Acknowledgements specific contributors referred to in "Arm Limited and Contributors" copyright notices. As contributors are now encouraged to put their name or company name directly into the copyright notices, this file is not relevant for new - contributions. + contributions. See the :ref:`License` document for the correct template to + use for new contributions. - Linaro Limited - Marvell International Ltd. diff --git a/docs/about/features.rst b/docs/about/features.rst index 9df289468..3441c5ebe 100644 --- a/docs/about/features.rst +++ b/docs/about/features.rst @@ -3,7 +3,7 @@ Feature Overview This page provides an overview of the current |TF-A| feature set. For a full description of these features and their implementation details, please see -:ref:`Firmware Design` and supporting documentation. +the documents that are part of the *Components* and *System Design* chapters. The :ref:`Change Log & Release Notes` provides details of changes made since the last release. @@ -34,7 +34,7 @@ Current features is also suitable for integration with other AArch32 EL3 Runtime Software, for example an AArch32 Secure OS. -- A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate |PSCI| library +- A minimal AArch32 Secure Payload (*SP_MIN*) to demonstrate |PSCI| library integration with AArch32 EL3 Runtime Software. - Secure Monitor library code such as world switching, EL1 context management @@ -106,8 +106,8 @@ Still to come - Refinements to Position Independent Executable (PIE) support. -- Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT - specifications continue to evolve. +- Continued support for the draft SPCI specification, to enable the use of + secure partition management in the secure world. - Documentation enhancements. diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst index 86e445a76..68f84ea57 100644 --- a/docs/about/maintainers.rst +++ b/docs/about/maintainers.rst @@ -19,8 +19,8 @@ Main maintainers :G: `AlexeiFedorov`_ :M: Paul Beesley :G: `pbeesley-arm`_ -:M: John Tsichritzis -:G: `jts-arm`_ +:M: György Szing +:G: `gyuri-szing`_ Allwinner ARMv8 platform port ----------------------------- @@ -287,10 +287,10 @@ Xilinx platform port .. _etienne-lms: https://github.com/etienne-lms .. _glneo: https://github.com/glneo .. _grandpaul: https://github.com/grandpaul +.. _gyuri-szing: https://github.com/gyuri-szing .. _hzhuang1: https://github.com/hzhuang1 .. _JackyBai: https://github.com/JackyBai .. _jenswi-linaro: https://github.com/jenswi-linaro -.. _jts-arm: https://github.com/jts-arm .. _jwerner-chromium: https://github.com/jwerner-chromium .. _kostapr: https://github.com/kostapr .. _ldts: https://github.com/ldts diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 3dd23e5b3..9876531a7 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -1764,6 +1764,7 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores - ``FVP_Base_Cortex-A76AEx8`` - ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) - ``FVP_Base_Neoverse-N1x4`` +- ``FVP_Base_Zeusx4`` - ``FVP_CSS_SGI-575`` (Version 11.3 build 42) - ``FVP_CSS_SGM-775`` (Version 11.3 build 42) - ``FVP_RD_E1Edge`` (Version 11.3 build 42) diff --git a/docs/plat/index.rst b/docs/plat/index.rst index 572963513..5495280aa 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -86,6 +86,7 @@ CPU cores (64-bit host machine only). - ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model) - ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model) - ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) +- ``FVP_Base_Zeusx4`` - ``FVP_Base_Neoverse-N1x4`` (Tested with internal model) - ``FVP_CSS_SGI-575`` (Version 11.3 build 42) - ``FVP_CSS_SGM-775`` (Version 11.3 build 42) @@ -103,8 +104,8 @@ CPU cores (64-bit host machine only). .. note:: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities. -The *Foundation* FVP can be downloaded free of charge. The *Base* FVPs can be -licensed from Arm. See the `Arm FVP website`_. +The *Foundation* and *Base* FVPs can be downloaded free of charge. See the +`Arm FVP website`_. All the above platforms have been tested with `Linaro Release 19.06`_. -- cgit v1.2.3 From 22cab65018487b1ea1838c48c7b6bae768a85e7e Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Fri, 11 Oct 2019 15:45:24 -0500 Subject: Fix white space errors + remove #if defined Fix a few white space errors and remove #if defined in workaround for N1 Errata 1542419. Signed-off-by: Lauren Wehrmeister Change-Id: I07ac5a2fd50cd63de53c06e3d0f8262871b62fad --- lib/cpus/aarch64/neoverse_n1.S | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index c9bb005e3..faf53a848 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -21,9 +21,7 @@ #error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif -#if ERRATA_N1_IC_TRAP .global neoverse_n1_errata_ic_trap_handler -#endif /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1043202. @@ -356,7 +354,7 @@ func errata_n1_1542419_wa bl check_errata_1542419 cbz x0, 1f - /* Apply instruction patching sequence */ + /* Apply instruction patching sequence */ ldr x0, =0x0 msr CPUPSELR_EL3, x0 ldr x0, =0xEE670D35 @@ -536,10 +534,10 @@ func neoverse_n1_errata_ic_trap_handler tlbi vae3is, xzr dsb sy - # Skip the IC instruction itself - mrs x3, elr_el3 - add x3, x3, #4 - msr elr_el3, x3 + # Skip the IC instruction itself + mrs x3, elr_el3 + add x3, x3, #4 + msr elr_el3, x3 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] -- cgit v1.2.3 From cf489bf1184355bb6b2d0ee2e6a1dcc505e008b9 Mon Sep 17 00:00:00 2001 From: Vignesh Radhakrishnan Date: Thu, 25 May 2017 10:31:42 -0700 Subject: Revert "Tegra: Add support for fake system suspend" This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e Fake system suspend relies on software running on EL3 to trigger a warm reset. Revert enabling fake system suspend, as the software running on El3 is not allowed to trigger a warm reset. Change-Id: I6035f2a7bcb0a4ad50a62c5bc5239226c625ee5e Signed-off-by: Vignesh Radhakrishnan --- plat/nvidia/tegra/common/tegra_pm.c | 31 +----------------------------- plat/nvidia/tegra/common/tegra_sip_calls.c | 26 ------------------------- plat/nvidia/tegra/include/tegra_private.h | 2 -- 3 files changed, 1 insertion(+), 58 deletions(-) diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index 8ba02d6f5..a8c70eaa5 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -27,14 +27,6 @@ extern uint64_t tegra_bl31_phys_base; extern uint64_t tegra_sec_entry_point; -/* - * tegra_fake_system_suspend acts as a boolean var controlling whether - * we are going to take fake system suspend code or normal system suspend code - * path. This variable is set inside the sip call handlers,when the kernel - * requests a SIP call to set the suspend debug flags. - */ -uint8_t tegra_fake_system_suspend; - /* * The following platform setup functions are weakly defined. They * provide typical implementations that will be overridden by a SoC. @@ -233,31 +225,10 @@ void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) { - uint8_t pwr_state = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; - uint64_t rmr_el3 = 0; - /* call the chip's power down handler */ (void)tegra_soc_pwr_domain_power_down_wfi(target_state); - /* - * If we are in fake system suspend mode, ensure we start doing - * procedures that help in looping back towards system suspend exit - * instead of calling WFI by requesting a warm reset. - * Else, just call WFI to enter low power state. - */ - if ((tegra_fake_system_suspend != 0U) && - (pwr_state == (uint8_t)PSTATE_ID_SOC_POWERDN)) { - - /* warm reboot */ - rmr_el3 = read_rmr_el3(); - write_rmr_el3(rmr_el3 | RMR_WARM_RESET_CPU); - - } else { - /* enter power down state */ - wfi(); - } - - /* we can never reach here */ + wfi(); panic(); } diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/common/tegra_sip_calls.c index 957300e53..b8ba09562 100644 --- a/plat/nvidia/tegra/common/tegra_sip_calls.c +++ b/plat/nvidia/tegra/common/tegra_sip_calls.c @@ -24,12 +24,6 @@ #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 #define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005 #define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006 -#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2000007 - -/******************************************************************************* - * Fake system suspend mode control var - ******************************************************************************/ -extern uint8_t tegra_fake_system_suspend; /******************************************************************************* * SoC specific SiP handler @@ -162,26 +156,6 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid, SMC_RET0(handle); - case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND: - /* - * System suspend fake mode is set if we are on VDK and we make - * a debug SIP call. This mode ensures that we excercise debug - * path instead of the regular code path to suit the pre-silicon - * platform needs. These include replacing the call to WFI by - * a warm reset request. - */ - if (tegra_platform_is_virt_dev_kit() != false) { - - tegra_fake_system_suspend = 1; - SMC_RET1(handle, 0); - } - - /* - * We return to the external world as if this SIP is not - * implemented in case, we are not running on VDK. - */ - break; - default: ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); break; diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index 34a096cfb..fab0eafc3 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -97,8 +97,6 @@ void tegra_security_setup(void); void tegra_security_setup_videomem(uintptr_t base, uint64_t size); /* Declarations for tegra_pm.c */ -extern uint8_t tegra_fake_system_suspend; - void tegra_pm_system_suspend_entry(void); void tegra_pm_system_suspend_exit(void); int32_t tegra_system_suspended(void); -- cgit v1.2.3 From 416125595367ac426f45093e78f030bb2787ab61 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 9 Apr 2018 17:48:58 -0700 Subject: Tegra194: base commit for the platform This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra_def.h | 235 ++++++++++++++++ .../tegra/soc/t194/drivers/include/mce_private.h | 156 +++++++++++ .../soc/t194/drivers/mce/aarch64/nvg_helpers.S | 31 +++ plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 309 +++++++++++++++++++++ plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 214 ++++++++++++++ plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 306 ++++++++++++++++++++ plat/nvidia/tegra/soc/t194/plat_secondary.c | 65 +++++ plat/nvidia/tegra/soc/t194/plat_setup.c | 253 +++++++++++++++++ plat/nvidia/tegra/soc/t194/plat_sip_calls.c | 112 ++++++++ plat/nvidia/tegra/soc/t194/plat_trampoline.S | 83 ++++++ plat/nvidia/tegra/soc/t194/platform_t194.mk | 62 +++++ 11 files changed, 1826 insertions(+) create mode 100644 plat/nvidia/tegra/include/t194/tegra_def.h create mode 100644 plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h create mode 100644 plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S create mode 100644 plat/nvidia/tegra/soc/t194/drivers/mce/mce.c create mode 100644 plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c create mode 100644 plat/nvidia/tegra/soc/t194/plat_psci_handlers.c create mode 100644 plat/nvidia/tegra/soc/t194/plat_secondary.c create mode 100644 plat/nvidia/tegra/soc/t194/plat_setup.c create mode 100644 plat/nvidia/tegra/soc/t194/plat_sip_calls.c create mode 100644 plat/nvidia/tegra/soc/t194/plat_trampoline.S create mode 100644 plat/nvidia/tegra/soc/t194/platform_t194.mk diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h new file mode 100644 index 000000000..8e7b28cac --- /dev/null +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __TEGRA_DEF_H__ +#define __TEGRA_DEF_H__ + +#include + +/******************************************************************************* + * These values are used by the PSCI implementation during the `CPU_SUSPEND` + * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' + * parameter. + ******************************************************************************/ +#define PSTATE_ID_CORE_IDLE 6 +#define PSTATE_ID_CORE_POWERDN 7 +#define PSTATE_ID_SOC_POWERDN 2 + +/******************************************************************************* + * Platform power states (used by PSCI framework) + * + * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID + * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID + ******************************************************************************/ +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 8 + +/******************************************************************************* + * Implementation defined ACTLR_EL3 bit definitions + ******************************************************************************/ +#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) +#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) +#define ACTLR_EL3_L2CTLR_BIT (1 << 4) +#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) +#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) +#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ + ACTLR_EL3_L2ECTLR_BIT | \ + ACTLR_EL3_L2CTLR_BIT | \ + ACTLR_EL3_CPUECTLR_BIT | \ + ACTLR_EL3_CPUACTLR_BIT) + +/******************************************************************************* + * Secure IRQ definitions + ******************************************************************************/ +#define TEGRA186_MAX_SEC_IRQS 5 +#define TEGRA186_BPMP_WDT_IRQ 46 +#define TEGRA186_SPE_WDT_IRQ 47 +#define TEGRA186_SCE_WDT_IRQ 48 +#define TEGRA186_TOP_WDT_IRQ 49 +#define TEGRA186_AON_WDT_IRQ 50 + +#define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */ + +/******************************************************************************* + * Tegra Miscellanous register constants + ******************************************************************************/ +#define TEGRA_MISC_BASE 0x00100000 +#define HARDWARE_REVISION_OFFSET 0x4 + +#define MISCREG_PFCFG 0x200C + +/******************************************************************************* + * Tegra TSA Controller constants + ******************************************************************************/ +#define TEGRA_TSA_BASE 0x02000000 + +#define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010 +#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034 +#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020 +#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008 +#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008 +#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018 +#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008 +#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028 +#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008 +#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008 +#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008 +#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008 +#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038 +#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018 +#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028 +#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 + +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) + +/******************************************************************************* + * Tegra Memory Controller constants + ******************************************************************************/ +#define TEGRA_MC_STREAMID_BASE 0x02C00000 +#define TEGRA_MC_BASE 0x02C10000 + +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 +#define MC_SECURITY_CFG3_0 0x9BC + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE_HI 0x978 +#define MC_VIDEO_PROTECT_BASE_LO 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + +/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ +#define MC_TZRAM_BASE_LO 0x2194 +#define TZRAM_BASE_LO_SHIFT 12 +#define TZRAM_BASE_LO_MASK 0xFFFFF +#define MC_TZRAM_BASE_HI 0x2198 +#define TZRAM_BASE_HI_SHIFT 0 +#define TZRAM_BASE_HI_MASK 3 +#define MC_TZRAM_SIZE 0x219C +#define TZRAM_SIZE_RANGE_4KB_SHIFT 27 + +#define MC_TZRAM_CARVEOUT_CFG 0x2190 +#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) +#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 +#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25) +#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7) +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 + +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21C0 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21C4 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C8 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21CC +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21D0 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21D4 + +/* Memory Controller Reset Control registers */ +#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27) +#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) +#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) +#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) +#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31) + +/******************************************************************************* + * Tegra UART Controller constants + ******************************************************************************/ +#define TEGRA_UARTA_BASE 0x03100000 +#define TEGRA_UARTB_BASE 0x03110000 +#define TEGRA_UARTC_BASE 0x0C280000 +#define TEGRA_UARTD_BASE 0x03130000 +#define TEGRA_UARTE_BASE 0x03140000 +#define TEGRA_UARTF_BASE 0x03150000 +#define TEGRA_UARTG_BASE 0x0C290000 + +/******************************************************************************* + * Tegra Fuse Controller related constants + ******************************************************************************/ +#define TEGRA_FUSE_BASE 0x03820000 +#define OPT_SUBREVISION 0x248 +#define SUBREVISION_MASK 0xF + +/******************************************************************************* + * GICv2 & interrupt handling related constants + ******************************************************************************/ +#define TEGRA_GICD_BASE 0x03881000 +#define TEGRA_GICC_BASE 0x03882000 + +/******************************************************************************* + * Security Engine related constants + ******************************************************************************/ +#define TEGRA_SE0_BASE 0x03AC0000 +#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C +#define TEGRA_PKA1_BASE 0x03AD0000 +#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 +#define TEGRA_RNG1_BASE 0x03AE0000 +#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 + +/******************************************************************************* + * Tegra micro-seconds timer constants + ******************************************************************************/ +#define TEGRA_TMRUS_BASE 0x0C2E0000 + +/******************************************************************************* + * Tegra Power Mgmt Controller constants + ******************************************************************************/ +#define TEGRA_PMC_BASE 0x0C360000 + +/******************************************************************************* + * Tegra scratch registers constants + ******************************************************************************/ +#define TEGRA_SCRATCH_BASE 0x0C390000 +#define SECURE_SCRATCH_RSV1_LO 0x06C +#define SECURE_SCRATCH_RSV1_HI 0x070 +#define SECURE_SCRATCH_RSV6 0x094 +#define SECURE_SCRATCH_RSV11_LO 0x0BC +#define SECURE_SCRATCH_RSV11_HI 0x0C0 +#define SECURE_SCRATCH_RSV53_LO 0x20C +#define SECURE_SCRATCH_RSV53_HI 0x210 +#define SECURE_SCRATCH_RSV54_HI 0x218 +#define SECURE_SCRATCH_RSV55_LO 0x21C +#define SECURE_SCRATCH_RSV55_HI 0x220 + +/******************************************************************************* + * Tegra Memory Mapped Control Register Access Bus constants + ******************************************************************************/ +#define TEGRA_MMCRAB_BASE 0x0E000000 + +/******************************************************************************* + * Tegra SMMU Controller constants + ******************************************************************************/ +#define TEGRA_SMMU_BASE 0x10000000 + +/******************************************************************************* + * Tegra TZRAM constants + ******************************************************************************/ +#define TEGRA_TZRAM_BASE 0x40000000 +#define TEGRA_TZRAM_SIZE 0x40000 + +/******************************************************************************* + * Tegra Clock and Reset Controller constants + ******************************************************************************/ +#define TEGRA_CAR_RESET_BASE 0x200000000 + +#endif /* __TEGRA_DEF_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h new file mode 100644 index 000000000..473540473 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MCE_PRIVATE_H__ +#define __MCE_PRIVATE_H__ + +#include +#include + +/******************************************************************************* + * Macros to prepare CSTATE info request + ******************************************************************************/ +/* Description of the parameters for UPDATE_CSTATE_INFO request */ +#define CLUSTER_CSTATE_MASK 0x7 +#define CLUSTER_CSTATE_SHIFT 0 +#define CLUSTER_CSTATE_UPDATE_BIT (1 << 7) +#define CCPLEX_CSTATE_MASK 0x3 +#define CCPLEX_CSTATE_SHIFT 8 +#define CCPLEX_CSTATE_UPDATE_BIT (1 << 15) +#define SYSTEM_CSTATE_MASK 0xF +#define SYSTEM_CSTATE_SHIFT 16 +#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22 +#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1 << 22) +#define SYSTEM_CSTATE_UPDATE_BIT (1 << 23) +#define CSTATE_WAKE_MASK_UPDATE_BIT (1 << 31) +#define CSTATE_WAKE_MASK_SHIFT 32 +#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFF + +/******************************************************************************* + * Auto-CC3 control macros + ******************************************************************************/ +#define MCE_AUTO_CC3_FREQ_MASK 0x1FF +#define MCE_AUTO_CC3_FREQ_SHIFT 0 +#define MCE_AUTO_CC3_VTG_MASK 0x7F +#define MCE_AUTO_CC3_VTG_SHIFT 16 +#define MCE_AUTO_CC3_ENABLE_BIT (1 << 31) + +/******************************************************************************* + * Macros for the 'IS_SC7_ALLOWED' command + ******************************************************************************/ +#define MCE_SC7_ALLOWED_MASK 0x7 +#define MCE_SC7_WAKE_TIME_SHIFT 32 + +/******************************************************************************* + * Macros for 'read/write ctats' commands + ******************************************************************************/ +#define MCE_CSTATE_STATS_TYPE_SHIFT 32 +#define MCE_CSTATE_WRITE_DATA_LO_MASK 0xF + +/******************************************************************************* + * Macros for 'update crossover threshold' command + ******************************************************************************/ +#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32 + +/******************************************************************************* + * Timeout value used to powerdown a core + ******************************************************************************/ +#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF + +/******************************************************************************* + * MCA command struct + ******************************************************************************/ +typedef union mca_cmd { + struct command { + uint8_t cmd; + uint8_t idx; + uint8_t subidx; + } command; + struct input { + uint32_t low; + uint32_t high; + } input; + uint64_t data; +} mca_cmd_t; + +/******************************************************************************* + * MCA argument struct + ******************************************************************************/ +typedef union mca_arg { + struct err { + uint64_t error:8; + uint64_t unused:48; + uint64_t finish:8; + } err; + struct arg { + uint32_t low; + uint32_t high; + } arg; + uint64_t data; +} mca_arg_t; + +/******************************************************************************* + * Uncore PERFMON ARI struct + ******************************************************************************/ +typedef union uncore_perfmon_req { + struct perfmon_command { + /* + * Commands: 0 = READ, 1 = WRITE + */ + uint64_t cmd:8; + /* + * The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4 + */ + uint64_t grp:4; + /* + * Unit selector: Selects the unit instance, with 0 = Unit + * = (number of units in group) - 1. + */ + uint64_t unit:4; + /* + * Selects the uncore perfmon register to access + */ + uint64_t reg:8; + /* + * Counter number. Selects which counter to use for + * registers NV_PMEVCNTR and NV_PMEVTYPER. + */ + uint64_t counter:8; + } perfmon_command; + struct perfmon_status { + /* + * Resulting command status + */ + uint64_t val:8; + uint64_t unused:24; + } perfmon_status; + uint64_t data; +} uncore_perfmon_req_t; + +#define UNCORE_PERFMON_CMD_READ 0 +#define UNCORE_PERFMON_CMD_WRITE 1 + +#define UNCORE_PERFMON_CMD_MASK 0xFF +#define UNCORE_PERFMON_UNIT_GRP_MASK 0xF +#define UNCORE_PERFMON_SELECTOR_MASK 0xF +#define UNCORE_PERFMON_REG_MASK 0xFF +#define UNCORE_PERFMON_CTR_MASK 0xFF +#define UNCORE_PERFMON_RESP_STATUS_MASK 0xFF + +/* declarations for NVG handler functions */ +int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); +int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, + uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, + uint8_t update_wake_mask); +int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); +uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state); +int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t val); +int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); +int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); +int nvg_online_core(uint32_t ari_base, uint32_t core); +int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); + +#endif /* __MCE_PRIVATE_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S new file mode 100644 index 000000000..e6a6a9980 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + + .globl nvg_set_request_data + .globl nvg_set_request + .globl nvg_get_result + +/* void nvg_set_request_data(uint64_t req, uint64_t data) */ +func nvg_set_request_data + msr s3_0_c15_c1_2, x0 + msr s3_0_c15_c1_3, x1 + ret +endfunc nvg_set_request_data + +/* void nvg_set_request(uint64_t req) */ +func nvg_set_request + msr s3_0_c15_c1_2, x0 + ret +endfunc nvg_set_request + +/* uint64_t nvg_get_result(void) */ +func nvg_get_result + mrs x0, s3_0_c15_c1_3 + ret +endfunc nvg_get_result diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c new file mode 100644 index 000000000..3a2e262f6 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Common handler for all MCE commands + ******************************************************************************/ +int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, + uint64_t arg2) +{ + uint64_t ret64 = 0, arg3, arg4, arg5; + int ret = 0; + mca_cmd_t mca_cmd; + uncore_perfmon_req_t req; + cpu_context_t *ctx = cm_get_context(NON_SECURE); + gp_regs_t *gp_regs = get_gpregs_ctx(ctx); + + assert(ctx); + assert(gp_regs); + + switch (cmd) { + case MCE_CMD_ENTER_CSTATE: + /* NVG */ + break; + + case MCE_CMD_UPDATE_CSTATE_INFO: + /* + * get the parameters required for the update cstate info + * command + */ + arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4); + arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5); + arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6); + + /* NVG */ + + write_ctx_reg(gp_regs, CTX_GPREG_X4, arg3); + write_ctx_reg(gp_regs, CTX_GPREG_X5, arg4); + write_ctx_reg(gp_regs, CTX_GPREG_X6, arg5); + + break; + + case MCE_CMD_UPDATE_CROSSOVER_TIME: + /* NVG */ + + break; + + case MCE_CMD_READ_CSTATE_STATS: + /* NVG */ + + /* update context to return cstate stats value */ + write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); + write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64); + + break; + + case MCE_CMD_WRITE_CSTATE_STATS: + /* NVG */ + + break; + + case MCE_CMD_IS_CCX_ALLOWED: + /* NVG */ + + /* update context to return CCx status value */ + write_ctx_reg(gp_regs, CTX_GPREG_X1, ret); + + break; + + case MCE_CMD_IS_SC7_ALLOWED: + /* NVG */ + + /* update context to return SC7 status value */ + write_ctx_reg(gp_regs, CTX_GPREG_X1, ret); + write_ctx_reg(gp_regs, CTX_GPREG_X3, ret); + + break; + + case MCE_CMD_ONLINE_CORE: + /* NVG */ + + break; + + case MCE_CMD_CC3_CTRL: + /* NVG */ + + break; + + case MCE_CMD_ECHO_DATA: + /* issue NVG to echo data */ + + /* update context to return if echo'd data matched source */ + write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64 == arg0); + write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64 == arg0); + + break; + + case MCE_CMD_READ_VERSIONS: + /* get the MCE firmware version */ + + /* + * version = minor(63:32) | major(31:0). Update context + * to return major and minor version number. + */ + write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint32_t)ret64); + write_ctx_reg(gp_regs, CTX_GPREG_X2, (uint32_t)(ret64 >> 32)); + + break; + + case MCE_CMD_ENUM_FEATURES: + break; + + case MCE_CMD_ROC_FLUSH_CACHE_TRBITS: + /* NVG */ + + break; + + case MCE_CMD_ROC_FLUSH_CACHE: + /* NVG */ + + break; + + case MCE_CMD_ROC_CLEAN_CACHE: + /* NVG */ + + break; + + case MCE_CMD_ENUM_READ_MCA: + memcpy(&mca_cmd, &arg0, sizeof(arg0)); + + /* NVG */ + + /* update context to return MCA data/error */ + write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); + write_ctx_reg(gp_regs, CTX_GPREG_X2, arg1); + write_ctx_reg(gp_regs, CTX_GPREG_X3, ret64); + + break; + + case MCE_CMD_ENUM_WRITE_MCA: + memcpy(&mca_cmd, &arg0, sizeof(arg0)); + + /* NVG */ + + /* update context to return MCA error */ + write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); + write_ctx_reg(gp_regs, CTX_GPREG_X3, ret64); + + break; + + case MCE_CMD_ENABLE_LATIC: + /* + * This call is not for production use. The constant value, + * 0xFFFF0000, is specific to allowing for enabling LATIC on + * pre-production parts for the chip verification harness. + * + * Enabling LATIC allows S/W to read the MINI ISPs in the + * CCPLEX. The ISMs are used for various measurements relevant + * to particular locations in the Silicon. They are small + * counters which can be polled to determine how fast a + * particular location in the Silicon is. + */ + /* NVG */ + + break; + + case MCE_CMD_UNCORE_PERFMON_REQ: + memcpy(&req, &arg0, sizeof(arg0)); + /* NVG */ + + /* update context to return data */ + write_ctx_reg(gp_regs, CTX_GPREG_X1, arg1); + break; + + case MCE_CMD_MISC_CCPLEX: + /* NVG */ + + break; + + default: + ERROR("unknown MCE command (%lld)\n", cmd); + return EINVAL; + } + + return ret; +} + +/******************************************************************************* + * Handler to update the reset vector for CPUs + ******************************************************************************/ +int mce_update_reset_vector(void) +{ + return 0; +} + +static int mce_update_ccplex_gsc(/* GSC ID */) +{ + return 0; +} + +/******************************************************************************* + * Handler to update carveout values for Video Memory Carveout region + ******************************************************************************/ +int mce_update_gsc_videomem(void) +{ + return mce_update_ccplex_gsc(); +} + +/******************************************************************************* + * Handler to update carveout values for TZDRAM aperture + ******************************************************************************/ +int mce_update_gsc_tzdram(void) +{ + return mce_update_ccplex_gsc(); +} + +/******************************************************************************* + * Handler to update carveout values for TZ SysRAM aperture + ******************************************************************************/ +int mce_update_gsc_tzram(void) +{ + return mce_update_ccplex_gsc(); +} + +/******************************************************************************* + * Handler to shutdown/reset the entire system + ******************************************************************************/ +__dead2 void mce_enter_ccplex_state(uint32_t state_idx) +{ + /* sanity check state value */ + + /* enter ccplex power state */ + + /* wait till the CCPLEX powers down */ + for (;;) + ; + + panic(); +} + +/******************************************************************************* + * Handler to issue the UPDATE_CSTATE_INFO request + ******************************************************************************/ +void mce_update_cstate_info(mce_cstate_info_t *cstate) +{ + /* issue the UPDATE_CSTATE_INFO request */ + /* NVG */ +} + +/******************************************************************************* + * Handler to read the MCE firmware version and check if it is compatible + * with interface header the BL3-1 was compiled against + ******************************************************************************/ +void mce_verify_firmware_version(void) +{ + uint64_t version; + uint32_t major, minor; + + /* + * MCE firmware is not running on simulation platforms. + */ + if (tegra_platform_is_linsim() || tegra_platform_is_virt_dev_kit()) + return; + + /* get a pointer to the CPU's arch_mce_ops_t struct */ + + /* + * Read the MCE firmware version and extract the major and minor + * version fields + */ + version = 0; + major = (uint32_t)version; + minor = (uint32_t)(version >> 32); + + INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor, + 0, 0); + + /* + * Verify that the MCE firmware version and the interface header + * match + */ + if (major != 0) { + ERROR("MCE major version mismatch\n"); + panic(); + } + + if (minor < 0) { + ERROR("MCE minor version mismatch\n"); + panic(); + } +} diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c new file mode 100644 index 000000000..36b3aabbb --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include + +extern void nvg_set_request_data(uint64_t req, uint64_t data); +extern void nvg_set_request(uint64_t req); +extern uint64_t nvg_get_result(void); + +int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) +{ + /* check for allowed power state */ + if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 && + state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) { + ERROR("%s: unknown cstate (%d)\n", __func__, state); + return EINVAL; + } + + /* time (TSC ticks) until the core is expected to get a wake event */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time); + + /* set the core cstate */ + write_actlr_el1(state); + + return 0; +} + +/* + * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and + * SYSTEM_CSTATE values. + */ +int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, + uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, + uint8_t update_wake_mask) +{ + uint64_t val = 0; + + /* update CLUSTER_CSTATE? */ + if (cluster) + val |= (cluster & CLUSTER_CSTATE_MASK) | + CLUSTER_CSTATE_UPDATE_BIT; + + /* update CCPLEX_CSTATE? */ + if (ccplex) + val |= (ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT | + CCPLEX_CSTATE_UPDATE_BIT; + + /* update SYSTEM_CSTATE? */ + if (system) + val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | + ((sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | + SYSTEM_CSTATE_UPDATE_BIT); + + /* update wake mask value? */ + if (update_wake_mask) + val |= CSTATE_WAKE_MASK_UPDATE_BIT; + + /* set the wake mask */ + val &= CSTATE_WAKE_MASK_CLEAR; + val |= ((uint64_t)wake_mask << CSTATE_WAKE_MASK_SHIFT); + + /* set the updated cstate info */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val); + + return 0; +} + +int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) +{ + /* sanity check crossover type */ + if (type > TEGRA_ARI_CROSSOVER_CCP3_SC1) + return EINVAL; + + /* + * The crossover threshold limit types start from + * TEGRA_CROSSOVER_TYPE_C1_C6 to TEGRA_CROSSOVER_TYPE_CCP3_SC7. The + * command indices for updating the threshold can be generated + * by adding the type to the NVG_SET_THRESHOLD_CROSSOVER_C1_C6 + * command index. + */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 + type, + (uint64_t)time); + + return 0; +} + +uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state) +{ + /* sanity check state */ + if (state == 0) + return EINVAL; + + /* + * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES + * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for + * reading the threshold can be generated by adding the type to + * the NVG_CLEAR_CSTATE_STATS command index. + */ + nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + state); + + return (int64_t)nvg_get_result(); +} + +int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) +{ + uint64_t val; + + /* + * The only difference between a CSTATE_STATS_WRITE and + * CSTATE_STATS_READ is the usage of the 63:32 in the request. + * 63:32 are set to '0' for a read, while a write contains the + * actual stats value to be written. + */ + val = ((uint64_t)stats << MCE_CSTATE_STATS_TYPE_SHIFT) | state; + + /* + * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES + * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for + * reading the threshold can be generated by adding the type to + * the NVG_CLEAR_CSTATE_STATS command index. + */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + state, val); + + return 0; +} + +int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) +{ + /* This does not apply to the Denver cluster */ + return 0; +} + +int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) +{ + uint64_t val; + + /* check for allowed power state */ + if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 && + state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) { + ERROR("%s: unknown cstate (%d)\n", __func__, state); + return EINVAL; + } + + /* + * Request format - + * 63:32 = wake time + * 31:0 = C-state for this core + */ + val = ((uint64_t)wake_time << MCE_SC7_WAKE_TIME_SHIFT) | + (state & MCE_SC7_ALLOWED_MASK); + + /* issue command to check if SC7 is allowed */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val); + + /* 1 = SC7 allowed, 0 = SC7 not allowed */ + return !!nvg_get_result(); +} + +int nvg_online_core(uint32_t ari_base, uint32_t core) +{ + int cpu = read_mpidr() & MPIDR_CPU_MASK; + int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + + /* sanity check code id */ + if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) { + ERROR("%s: unsupported core id (%d)\n", __func__, core); + return EINVAL; + } + + /* + * The Denver cluster has 2 CPUs only - 0, 1. + */ + if (impl == DENVER_IMPL && ((core == 2) || (core == 3))) { + ERROR("%s: unknown core id (%d)\n", __func__, core); + return EINVAL; + } + + /* get a core online */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, core & MCE_CORE_ID_MASK); + + return 0; +} + +int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) +{ + int val; + + /* + * If the enable bit is cleared, Auto-CC3 will be disabled by setting + * the SW visible voltage/frequency request registers for all non + * floorswept cores valid independent of StandbyWFI and disabling + * the IDLE voltage/frequency request register. If set, Auto-CC3 + * will be enabled by setting the ARM SW visible voltage/frequency + * request registers for all non floorswept cores to be enabled by + * StandbyWFI or the equivalent signal, and always keeping the IDLE + * voltage/frequency request register enabled. + */ + val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\ + ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\ + (enable ? MCE_AUTO_CC3_ENABLE_BIT : 0)); + + nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val); + + return 0; +} diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c new file mode 100644 index 000000000..fb33c13e1 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -0,0 +1,306 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void prepare_core_pwr_dwn(void); + +#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM +extern void tegra186_cpu_reset_handler(void); +extern uint32_t __tegra186_cpu_reset_handler_data, + __tegra186_cpu_reset_handler_end; + +/* TZDRAM offset for saving SMMU context */ +#define TEGRA186_SMMU_CTX_OFFSET 16 +#endif + +/* state id mask */ +#define TEGRA186_STATE_ID_MASK 0xF +/* constants to get power state's wake time */ +#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 +#define TEGRA186_WAKE_TIME_SHIFT 4 +/* default core wake mask for CPU_SUSPEND */ +#define TEGRA186_CORE_WAKE_MASK 0x180c +/* context size to save during system suspend */ +#define TEGRA186_SE_CONTEXT_SIZE 3 + +static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; +static struct t18x_psci_percpu_data { + unsigned int wake_time; +} __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT]; + +int32_t tegra_soc_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; + int cpu = plat_my_core_pos(); + + /* save the core wake time (in TSC ticks)*/ + percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) + << TEGRA186_WAKE_TIME_SHIFT; + + /* + * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that + * the correct value is read in tegra_soc_pwr_domain_suspend(), which + * is called with caches disabled. It is possible to read a stale value + * from DRAM in that function, because the L2 cache is not flushed + * unless the cluster is entering CC6/CC7. + */ + clean_dcache_range((uint64_t)&percpu_data[cpu], + sizeof(percpu_data[cpu])); + + /* Sanity check the requested state id */ + switch (state_id) { + case PSTATE_ID_CORE_IDLE: + case PSTATE_ID_CORE_POWERDN: + + /* Core powerdown request */ + req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; + req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; + + break; + + default: + ERROR("%s: unsupported state id (%d)\n", __func__, state_id); + return PSCI_E_INVALID_PARAMS; + } + + return PSCI_E_SUCCESS; +} + +int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + const plat_local_state_t *pwr_domain_state; + unsigned int stateid_afflvl0, stateid_afflvl2; +#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM + plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); + uint64_t smmu_ctx_base; +#endif + uint32_t val; + + /* get the state ID */ + pwr_domain_state = target_state->pwr_domain_state; + stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & + TEGRA186_STATE_ID_MASK; + stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & + TEGRA186_STATE_ID_MASK; + + if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || + (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { + + /* Enter CPU idle/powerdown */ + + } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { + + /* save SE registers */ + se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + + SE_MUTEX_WATCHDOG_NS_LIMIT); + se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE + + RNG_MUTEX_WATCHDOG_NS_LIMIT); + se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE + + PKA_MUTEX_WATCHDOG_NS_LIMIT); + + /* save 'Secure Boot' Processor Feature Config Register */ + val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val); + +#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM + /* save SMMU context */ + smmu_ctx_base = params_from_bl2->tzdram_base + + ((uintptr_t)&__tegra186_cpu_reset_handler_data - + (uintptr_t)tegra186_cpu_reset_handler) + + TEGRA186_SMMU_CTX_OFFSET; + tegra_smmu_save_context((uintptr_t)smmu_ctx_base); +#else + tegra_smmu_save_context(0); +#endif + + /* Instruct the MCE to enter system suspend state */ + } + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Platform handler to calculate the proper target power level at the + * specified affinity level + ******************************************************************************/ +plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, + const plat_local_state_t *states, + unsigned int ncpu) +{ + plat_local_state_t target = *states; + int cluster_powerdn = 1; + int core_pos = read_mpidr() & MPIDR_CPU_MASK; + + /* get the current core's power state */ + target = *(states + core_pos); + + /* CPU suspend */ + if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) { + + /* Program default wake mask */ + + /* Check if CCx state is allowed. */ + } + + /* CPU off */ + if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) { + + /* find out the number of ON cpus in the cluster */ + do { + target = *states++; + if (target != PLAT_MAX_OFF_STATE) + cluster_powerdn = 0; + } while (--ncpu); + + /* Enable cluster powerdn from last CPU in the cluster */ + if (cluster_powerdn) { + + /* Enable CC7 state and turn off wake mask */ + + } else { + + /* Turn off wake_mask */ + } + } + + /* System Suspend */ + if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN)) + return PSTATE_ID_SOC_POWERDN; + + /* default state */ + return PSCI_LOCAL_STATE_RUN; +} + +#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM +int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) +{ + const plat_local_state_t *pwr_domain_state = + target_state->pwr_domain_state; + plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); + unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & + TEGRA186_STATE_ID_MASK; + uint32_t val; + + if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { + /* + * The TZRAM loses power when we enter system suspend. To + * allow graceful exit from system suspend, we need to copy + * BL3-1 over to TZDRAM. + */ + val = params_from_bl2->tzdram_base + + ((uintptr_t)&__tegra186_cpu_reset_handler_end - + (uintptr_t)tegra186_cpu_reset_handler); + memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, + (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); + } + + return PSCI_E_SUCCESS; +} +#endif + +int tegra_soc_pwr_domain_on(u_register_t mpidr) +{ + int target_cpu = mpidr & MPIDR_CPU_MASK; + int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> + MPIDR_AFFINITY_BITS; + + if (target_cluster > MPIDR_AFFLVL1) { + ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr); + return PSCI_E_NOT_PRESENT; + } + + /* construct the target CPU # */ + target_cpu |= (target_cluster << 2); + + mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); + + return PSCI_E_SUCCESS; +} + +int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; + + /* + * Reset power state info for CPUs when onlining, we set + * deepest power when offlining a core but that may not be + * requested by non-secure sw which controls idle states. It + * will re-init this info from non-secure software when the + * core come online. + */ + + /* + * Check if we are exiting from deep sleep and restore SE + * context if we are. + */ + if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { + + mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, + se_regs[0]); + mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, + se_regs[1]); + mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT, + se_regs[2]); + + /* Init SMMU */ + + /* + * Reset power state info for the last core doing SC7 + * entry and exit, we set deepest power state as CC7 + * and SC7 for SC7 entry which may not be requested by + * non-secure SW which controls idle states. + */ + } + + return PSCI_E_SUCCESS; +} + +int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) +{ + int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + + /* Disable Denver's DCO operations */ + if (impl == DENVER_IMPL) + denver_disable_dco(); + + /* Turn off CPU */ + + return PSCI_E_SUCCESS; +} + +__dead2 void tegra_soc_prepare_system_off(void) +{ + /* System power off */ + + /* SC8 */ + + wfi(); + + /* wait for the system to power down */ + for (;;) { + ; + } +} + +int tegra_soc_prepare_system_reset(void) +{ + return PSCI_E_SUCCESS; +} diff --git a/plat/nvidia/tegra/soc/t194/plat_secondary.c b/plat/nvidia/tegra/soc/t194/plat_secondary.c new file mode 100644 index 000000000..33c8e1b64 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/plat_secondary.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MISCREG_CPU_RESET_VECTOR 0x2000 +#define MISCREG_AA64_RST_LOW 0x2004 +#define MISCREG_AA64_RST_HIGH 0x2008 + +#define CPU_RESET_MODE_AA64 1 + +extern void tegra_secure_entrypoint(void); + +#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM +extern void tegra186_cpu_reset_handler(void); +extern uint64_t __tegra186_smmu_ctx_start; +#endif + +/******************************************************************************* + * Setup secondary CPU vectors + ******************************************************************************/ +void plat_secondary_setup(void) +{ + uint32_t addr_low, addr_high; +#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM + plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); + uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base; +#else + uint64_t cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint; +#endif + + INFO("Setting up secondary CPU boot\n"); + +#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM + memcpy((void *)((uintptr_t)cpu_reset_handler_base), + (void *)(uintptr_t)tegra186_cpu_reset_handler, + (uintptr_t)&__tegra186_smmu_ctx_start - + (uintptr_t)tegra186_cpu_reset_handler); +#endif + + addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; + addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff); + + /* write lower 32 bits first, then the upper 11 bits */ + mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); + mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); + + /* save reset vector to be used during SYSTEM_SUSPEND exit */ + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_LO, + addr_low); + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI, + addr_high); + + /* update reset vector address to the CCPLEX */ + mce_update_reset_vector(); +} diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c new file mode 100644 index 000000000..aab884e73 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) +extern uint64_t tegra_enable_l2_ecc_parity_prot; + +/******************************************************************************* + * The Tegra power domain tree has a single system level power domain i.e. a + * single root node. The first entry in the power domain descriptor specifies + * the number of power domains at the highest power level. + ******************************************************************************* + */ +const unsigned char tegra_power_domain_tree_desc[] = { + /* No of root nodes */ + 1, + /* No of clusters */ + PLATFORM_CLUSTER_COUNT, + /* No of CPU cores - cluster0 */ + PLATFORM_MAX_CPUS_PER_CLUSTER, + /* No of CPU cores - cluster1 */ + PLATFORM_MAX_CPUS_PER_CLUSTER +}; + +/* + * Table of regions to map using the MMU. + */ +static const mmap_region_t tegra_mmap[] = { + MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + {0} +}; + +/******************************************************************************* + * Set up the pagetables as per the platform memory map & initialize the MMU + ******************************************************************************/ +const mmap_region_t *plat_get_mmio_map(void) +{ + /* MMIO space */ + return tegra_mmap; +} + +/******************************************************************************* + * Handler to get the System Counter Frequency + ******************************************************************************/ +unsigned int plat_get_syscnt_freq2(void) +{ + return 31250000; +} + +/******************************************************************************* + * Maximum supported UART controllers + ******************************************************************************/ +#define TEGRA186_MAX_UART_PORTS 7 + +/******************************************************************************* + * This variable holds the UART port base addresses + ******************************************************************************/ +static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { + 0, /* undefined - treated as an error case */ + TEGRA_UARTA_BASE, + TEGRA_UARTB_BASE, + TEGRA_UARTC_BASE, + TEGRA_UARTD_BASE, + TEGRA_UARTE_BASE, + TEGRA_UARTF_BASE, + TEGRA_UARTG_BASE, +}; + +/******************************************************************************* + * Retrieve the UART controller base to be used as the console + ******************************************************************************/ +uint32_t plat_get_console_from_id(int id) +{ + if (id > TEGRA186_MAX_UART_PORTS) + return 0; + + return tegra186_uart_addresses[id]; +} + +/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ +#define TEGRA186_VER_A02P 0x1201 + +/******************************************************************************* + * Handler for early platform setup + ******************************************************************************/ +void plat_early_platform_setup(void) +{ + int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + uint32_t chip_subrev, val; + + /* sanity check MCE firmware compatibility */ + mce_verify_firmware_version(); + + /* + * Enable ECC and Parity Protection for Cortex-A57 CPUs + * for Tegra A02p SKUs + */ + if (impl != DENVER_IMPL) { + + /* get the major, minor and sub-version values */ + chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & + SUBREVISION_MASK; + + /* prepare chip version number */ + val = (tegra_get_chipid_major() << 12) | + (tegra_get_chipid_minor() << 8) | + chip_subrev; + + /* enable L2 ECC for Tegra186 A02P and beyond */ + if (val >= TEGRA186_VER_A02P) { + + val = read_l2ctlr_el1(); + val |= L2_ECC_PARITY_PROTECTION_BIT; + write_l2ctlr_el1(val); + + /* + * Set the flag to enable ECC/Parity Protection + * when we exit System Suspend or Cluster Powerdn + */ + tegra_enable_l2_ecc_parity_prot = 1; + } + } +} + +/* Secure IRQs for Tegra186 */ +static const irq_sec_cfg_t tegra186_sec_irqs[] = { + [0] = { + TEGRA186_BPMP_WDT_IRQ, + TEGRA186_SEC_IRQ_TARGET_MASK, + INTR_TYPE_EL3, + }, + [1] = { + TEGRA186_BPMP_WDT_IRQ, + TEGRA186_SEC_IRQ_TARGET_MASK, + INTR_TYPE_EL3, + }, + [2] = { + TEGRA186_SPE_WDT_IRQ, + TEGRA186_SEC_IRQ_TARGET_MASK, + INTR_TYPE_EL3, + }, + [3] = { + TEGRA186_SCE_WDT_IRQ, + TEGRA186_SEC_IRQ_TARGET_MASK, + INTR_TYPE_EL3, + }, + [4] = { + TEGRA186_TOP_WDT_IRQ, + TEGRA186_SEC_IRQ_TARGET_MASK, + INTR_TYPE_EL3, + }, + [5] = { + TEGRA186_AON_WDT_IRQ, + TEGRA186_SEC_IRQ_TARGET_MASK, + INTR_TYPE_EL3, + }, +}; + +/******************************************************************************* + * Initialize the GIC and SGIs + ******************************************************************************/ +void plat_gic_setup(void) +{ + tegra_gic_setup(tegra186_sec_irqs, + sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); + + /* + * Initialize the FIQ handler only if the platform supports any + * FIQ interrupt sources. + */ + if (sizeof(tegra186_sec_irqs) > 0) + tegra_fiq_handler_setup(); +} + +/******************************************************************************* + * Return pointer to the BL31 params from previous bootloader + ******************************************************************************/ +struct tegra_bl31_params *plat_get_bl31_params(void) +{ + uint32_t val; + + val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); + + return (struct tegra_bl31_params *)(uintptr_t)val; +} + +/******************************************************************************* + * Return pointer to the BL31 platform params from previous bootloader + ******************************************************************************/ +plat_params_from_bl2_t *plat_get_bl31_plat_params(void) +{ + uint32_t val; + + val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); + + return (plat_params_from_bl2_t *)(uintptr_t)val; +} diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c new file mode 100644 index 000000000..12b4b77da --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern uint32_t tegra186_system_powerdn_state; + +/******************************************************************************* + * Tegra186 SiP SMCs + ******************************************************************************/ +#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 +#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0x82FFFE01 +#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00 +#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01 +#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02 +#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0x82FFFF03 +#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0x82FFFF04 +#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0x82FFFF05 +#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0x82FFFF06 +#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0x82FFFF07 +#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0x82FFFF08 +#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0x82FFFF09 +#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0x82FFFF0A +#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0x82FFFF0B +#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0x82FFFF0C +#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0x82FFFF0D +#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0x82FFFF0E +#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F +#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0x82FFFF10 +#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0x82FFFF11 +#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0x82FFFF12 + +/******************************************************************************* + * This function is responsible for handling all T186 SiP calls + ******************************************************************************/ +int plat_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + int mce_ret; + + switch (smc_fid) { + + /* + * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - + * 0x82FFFFFF SiP SMC space + */ + case TEGRA_SIP_MCE_CMD_ENTER_CSTATE: + case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO: + case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME: + case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS: + case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS: + case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED: + case TEGRA_SIP_MCE_CMD_CC3_CTRL: + case TEGRA_SIP_MCE_CMD_ECHO_DATA: + case TEGRA_SIP_MCE_CMD_READ_VERSIONS: + case TEGRA_SIP_MCE_CMD_ENUM_FEATURES: + case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS: + case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA: + case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA: + case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE: + case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: + case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: + case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: + case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: + + /* clean up the high bits */ + smc_fid &= MCE_CMD_MASK; + + /* execute the command and store the result */ + mce_ret = mce_command_handler(smc_fid, x1, x2, x3); + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret); + + return 0; + + case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE: + + /* clean up the high bits */ + x1 = (uint32_t)x1; + + /* + * SC8 is a special Tegra186 system state where the CPUs and + * DRAM are powered down but the other subsystem is still + * alive. + */ + + return 0; + + default: + break; + } + + return -ENOTSUP; +} diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S new file mode 100644 index 000000000..cf765076a --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#define TEGRA186_SMMU_CTX_SIZE 0x420 + + .align 4 + .globl tegra186_cpu_reset_handler + +/* CPU reset handler routine */ +func tegra186_cpu_reset_handler + /* + * The TZRAM loses state during System Suspend. We use this + * information to decide if the reset handler is running after a + * System Suspend. Resume from system suspend requires restoring + * the entire state from TZDRAM to TZRAM. + */ + mov x0, #BL31_BASE + ldr x0, [x0] + cbnz x0, boot_cpu + + /* resume from system suspend */ + mov x0, #BL31_BASE + adr x1, __tegra186_cpu_reset_handler_end + adr x2, __tegra186_cpu_reset_handler_data + ldr x2, [x2, #8] + + /* memcpy16 */ +m_loop16: + cmp x2, #16 + b.lt m_loop1 + ldp x3, x4, [x1], #16 + stp x3, x4, [x0], #16 + sub x2, x2, #16 + b m_loop16 + /* copy byte per byte */ +m_loop1: + cbz x2, boot_cpu + ldrb w3, [x1], #1 + strb w3, [x0], #1 + subs x2, x2, #1 + b.ne m_loop1 + +boot_cpu: + adr x0, __tegra186_cpu_reset_handler_data + ldr x0, [x0] + br x0 +endfunc tegra186_cpu_reset_handler + + /* + * Tegra186 reset data (offset 0x0 - 0x430) + * + * 0x000: secure world's entrypoint + * 0x008: BL31 size (RO + RW) + * 0x00C: SMMU context start + * 0x42C: SMMU context end + */ + + .align 4 + .type __tegra186_cpu_reset_handler_data, %object + .globl __tegra186_cpu_reset_handler_data +__tegra186_cpu_reset_handler_data: + .quad tegra_secure_entrypoint + .quad __BL31_END__ - BL31_BASE + .globl __tegra186_smmu_ctx_start +__tegra186_smmu_ctx_start: + .rept TEGRA186_SMMU_CTX_SIZE + .quad 0 + .endr + .size __tegra186_cpu_reset_handler_data, \ + . - __tegra186_cpu_reset_handler_data + + .align 4 + .globl __tegra186_cpu_reset_handler_end +__tegra186_cpu_reset_handler_end: diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk new file mode 100644 index 000000000..54bc9419a --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -0,0 +1,62 @@ +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# platform configs +ENABLE_AFI_DEVICE := 0 +$(eval $(call add_define,ENABLE_AFI_DEVICE)) + +ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 0 +$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) + +ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM := 1 +$(eval $(call add_define,ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM)) + +RELOCATE_TO_BL31_BASE := 1 +$(eval $(call add_define,RELOCATE_TO_BL31_BASE)) + +ENABLE_CHIP_VERIFICATION_HARNESS := 0 +$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) + +ENABLE_SMMU_DEVICE := 0 +$(eval $(call add_define,ENABLE_SMMU_DEVICE)) + +RESET_TO_BL31 := 1 + +PROGRAMMABLE_RESET_ADDRESS := 1 + +COLD_BOOT_SINGLE_CPU := 1 + +# platform settings +TZDRAM_BASE := 0x40000000 +$(eval $(call add_define,TZDRAM_BASE)) + +PLATFORM_CLUSTER_COUNT := 2 +$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) + +PLATFORM_MAX_CPUS_PER_CLUSTER := 4 +$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) + +MAX_XLAT_TABLES := 24 +$(eval $(call add_define,MAX_XLAT_TABLES)) + +MAX_MMAP_REGIONS := 24 +$(eval $(call add_define,MAX_MMAP_REGIONS)) + +# platform files +PLAT_INCLUDES += -I${SOC_DIR}/drivers/include + +BL31_SOURCES += lib/cpus/aarch64/denver.S \ + ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ + ${COMMON_DIR}/drivers/smmu/smmu.c \ + ${SOC_DIR}/drivers/mce/mce.c \ + ${SOC_DIR}/plat_psci_handlers.c \ + ${SOC_DIR}/plat_setup.c \ + ${SOC_DIR}/plat_secondary.c \ + ${SOC_DIR}/plat_sip_calls.c + +ifeq (${ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM}, 1) +BL31_SOURCES += ${SOC_DIR}/plat_trampoline.S +endif -- cgit v1.2.3 From d11c793b45e4d859dfd6f2c544bbf09c6e8df7ae Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Fri, 23 Dec 2016 15:51:32 +0800 Subject: Tegra194: psci: support for 64-bit TZDRAM base This patch fixes the variable width to store the TZDRAM base address used to resume from System Suspend. Change-Id: I3c18eb844963f39f91b5ac45e3709f3354bcda0c Signed-off-by: Steven Kao --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index fb33c13e1..b7a6c4f8d 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -197,7 +197,7 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & TEGRA186_STATE_ID_MASK; - uint32_t val; + uint64_t val; if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { /* -- cgit v1.2.3 From 2ac8cb7e4f33c25e164c03b41c78007ef078f8a0 Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Mon, 2 Jan 2017 19:43:45 +0530 Subject: Tegra194: add SMMU and mc_sid support Define mc sid and txn override regs and sec cfgs. Create array for mc sid override regs and sec config that is used to initialize mc. Add smmu ctx regs array to hold register values during suspend. Change-Id: I7b265710a9ec2be7dea050058bce65c614772c78 Signed-off-by: Pritesh Raithatha --- .../soc/t194/drivers/include/memctrl_plat_config.h | 603 +++++++++++++++++++++ .../soc/t194/drivers/include/smmu_plat_config.h | 417 ++++++++++++++ 2 files changed, 1020 insertions(+) create mode 100644 plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h create mode 100644 plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h b/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h new file mode 100644 index 000000000..8a4ed5b05 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h @@ -0,0 +1,603 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MEMCTRL_PLAT_CONFIG_H +#define __MEMCTRL_PLAT_CONFIG_H + +#include + +/******************************************************************************* + * StreamID to indicate no SMMU translations (requests to be steered on the + * SMMU bypass path) + ******************************************************************************/ +#define MC_STREAM_ID_MAX 0x7F + +/******************************************************************************* + * Stream ID Override Config registers + ******************************************************************************/ +#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000 +#define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8 +#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0 +#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0 +#define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8 +#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138 +#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158 +#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8 +#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8 +#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 +#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220 +#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228 +#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230 +#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238 +#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250 +#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258 +#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260 +#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268 +#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0 +#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8 +#define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0 /*TODO: remove it after HW team confirmation */ +#define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8 /*TODO: remove it after HW team confirmation */ +#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300 +#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310 +#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318 +#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320 +#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330 +#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338 +#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360 +#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368 +#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390 +#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0 +#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8 +#define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0 +#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8 +#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0 +#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8 +#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400 +#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408 +#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410 +#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418 +#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420 +#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428 +#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430 +#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438 +#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440 /*TODO: remove it after HW team confirmation */ +#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448 /*TODO: remove it after HW team confirmation */ +#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460 +#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468 +#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470 +#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478 +#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480 +#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488 +#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490 +#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498 +#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0 +#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8 +#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0 +#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8 +#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0 +#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8 +#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0 +#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8 +#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0 +#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8 +#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0 +#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8 +#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500 +#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508 +#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510 +#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518 +#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530 +#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538 +#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540 +#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548 +#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570 +#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578 +#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580 +#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588 +#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5E0 +#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5E8 +#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5F0 +#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5F8 +#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600 +#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608 +#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610 +#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618 +#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620 +#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628 +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630 +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638 +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640 +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648 +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650 +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658 +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660 +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668 +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670 +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678 +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680 +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688 +#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690 +#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698 +#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6A0 +#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6A8 +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6B0 +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6B8 +#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6C0 +#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6C8 +#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6D0 +#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6D8 +#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6E0 +#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6E8 +#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6F0 +#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6F8 +#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700 +#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708 +#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710 +#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718 +#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720 +#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748 +#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750 +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758 +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760 +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768 +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770 +#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778 +#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780 +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788 +#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790 +#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798 +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7C8 +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7D0 +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7D8 + +/******************************************************************************* + * Macro to calculate Security cfg register addr from StreamID Override register + ******************************************************************************/ +#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t)) + +/******************************************************************************* + * Memory Controller transaction override config registers + ******************************************************************************/ +#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8 +#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0 +#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000 +#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490 +#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478 +#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8 +#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220 +#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360 +#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8 +#define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0 +#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460 +#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0 +#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330 +#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470 +#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8 +#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0 +#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318 +#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510 +#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8 +#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390 +#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468 +#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260 +#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480 +#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8 +#define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8 +#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8 +#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258 +#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438 +#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440 +#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8 +#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448 +#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0 +#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500 +#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0 +#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0 +#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420 +#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408 +#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0 +#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0 +#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430 +#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0 +#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0 +#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518 +#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250 +#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230 +#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400 +#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8 +#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8 +#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138 +#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320 +#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8 +#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8 +#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488 +#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8 +#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8 +#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428 +#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368 +#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158 +#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338 +#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300 +#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508 +#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238 +#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498 +#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8 +#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310 +#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268 +#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0 +#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0 +#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530 +#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538 +#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540 +#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548 +#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570 +#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578 +#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580 +#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158C +#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15E4 +#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15EC +#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15F4 +#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15FC +#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604 +#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160C +#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614 +#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161C +#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624 +#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162C +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634 +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163C +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644 +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164C +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654 +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165C +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664 +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166C +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674 +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167C +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684 +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168C +#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694 +#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169C +#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16A4 +#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16AC +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16B4 +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16BC +#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16C4 +#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16CC +#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16D4 +#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16DC +#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16E4 +#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16EC +#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16F4 +#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16FC +#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704 +#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170C +#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714 +#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171C +#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724 +#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174C +#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754 +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175C +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764 +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176C +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774 +#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177C +#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784 +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178C +#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794 +#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179C +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17CC +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4 +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC + +/******************************************************************************* + * Array to hold stream_id override config register offsets + ******************************************************************************/ +const static uint32_t mc_streamid_override_regs[] = { + MC_STREAMID_OVERRIDE_CFG_PTCR, + MC_STREAMID_OVERRIDE_CFG_HDAR, + MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, + MC_STREAMID_OVERRIDE_CFG_NVENCSRD, + MC_STREAMID_OVERRIDE_CFG_SATAR, + MC_STREAMID_OVERRIDE_CFG_MPCORER, + MC_STREAMID_OVERRIDE_CFG_NVENCSWR, + MC_STREAMID_OVERRIDE_CFG_HDAW, + MC_STREAMID_OVERRIDE_CFG_MPCOREW, + MC_STREAMID_OVERRIDE_CFG_SATAW, + MC_STREAMID_OVERRIDE_CFG_ISPRA, + MC_STREAMID_OVERRIDE_CFG_ISPFALR, + MC_STREAMID_OVERRIDE_CFG_ISPWA, + MC_STREAMID_OVERRIDE_CFG_ISPWB, + MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, + MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, + MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, + MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, + MC_STREAMID_OVERRIDE_CFG_TSECSRD, + MC_STREAMID_OVERRIDE_CFG_TSECSWR, + MC_STREAMID_OVERRIDE_CFG_GPUSRD, + MC_STREAMID_OVERRIDE_CFG_GPUSWR, + MC_STREAMID_OVERRIDE_CFG_SDMMCRA, + MC_STREAMID_OVERRIDE_CFG_SDMMCR, + MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, + MC_STREAMID_OVERRIDE_CFG_SDMMCWA, + MC_STREAMID_OVERRIDE_CFG_SDMMCW, + MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, + MC_STREAMID_OVERRIDE_CFG_VICSRD, + MC_STREAMID_OVERRIDE_CFG_VICSWR, + MC_STREAMID_OVERRIDE_CFG_VIW, + MC_STREAMID_OVERRIDE_CFG_NVDECSRD, + MC_STREAMID_OVERRIDE_CFG_NVDECSWR, + MC_STREAMID_OVERRIDE_CFG_APER, + MC_STREAMID_OVERRIDE_CFG_APEW, + MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, + MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, + MC_STREAMID_OVERRIDE_CFG_SESRD, + MC_STREAMID_OVERRIDE_CFG_SESWR, + MC_STREAMID_OVERRIDE_CFG_AXIAPR, + MC_STREAMID_OVERRIDE_CFG_AXIAPW, + MC_STREAMID_OVERRIDE_CFG_ETRR, + MC_STREAMID_OVERRIDE_CFG_ETRW, + MC_STREAMID_OVERRIDE_CFG_TSECSRDB, + MC_STREAMID_OVERRIDE_CFG_TSECSWRB, + MC_STREAMID_OVERRIDE_CFG_GPUSRD2, + MC_STREAMID_OVERRIDE_CFG_GPUSWR2, + MC_STREAMID_OVERRIDE_CFG_AXISR, + MC_STREAMID_OVERRIDE_CFG_AXISW, + MC_STREAMID_OVERRIDE_CFG_EQOSR, + MC_STREAMID_OVERRIDE_CFG_EQOSW, + MC_STREAMID_OVERRIDE_CFG_UFSHCR, + MC_STREAMID_OVERRIDE_CFG_UFSHCW, + MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, + MC_STREAMID_OVERRIDE_CFG_BPMPR, + MC_STREAMID_OVERRIDE_CFG_BPMPW, + MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, + MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, + MC_STREAMID_OVERRIDE_CFG_AONR, + MC_STREAMID_OVERRIDE_CFG_AONW, + MC_STREAMID_OVERRIDE_CFG_AONDMAR, + MC_STREAMID_OVERRIDE_CFG_AONDMAW, + MC_STREAMID_OVERRIDE_CFG_SCER, + MC_STREAMID_OVERRIDE_CFG_SCEW, + MC_STREAMID_OVERRIDE_CFG_SCEDMAR, + MC_STREAMID_OVERRIDE_CFG_SCEDMAW, + MC_STREAMID_OVERRIDE_CFG_APEDMAR, + MC_STREAMID_OVERRIDE_CFG_APEDMAW, + MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, + MC_STREAMID_OVERRIDE_CFG_VICSRD1, + MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, + MC_STREAMID_OVERRIDE_CFG_VIFALR, + MC_STREAMID_OVERRIDE_CFG_VIFALW, + MC_STREAMID_OVERRIDE_CFG_DLA0RDA, + MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, + MC_STREAMID_OVERRIDE_CFG_DLA0WRA, + MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, + MC_STREAMID_OVERRIDE_CFG_DLA1RDA, + MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, + MC_STREAMID_OVERRIDE_CFG_DLA1WRA, + MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, + MC_STREAMID_OVERRIDE_CFG_PVA0RDA, + MC_STREAMID_OVERRIDE_CFG_PVA0RDB, + MC_STREAMID_OVERRIDE_CFG_PVA0RDC, + MC_STREAMID_OVERRIDE_CFG_PVA0WRA, + MC_STREAMID_OVERRIDE_CFG_PVA0WRB, + MC_STREAMID_OVERRIDE_CFG_PVA0WRC, + MC_STREAMID_OVERRIDE_CFG_PVA1RDA, + MC_STREAMID_OVERRIDE_CFG_PVA1RDB, + MC_STREAMID_OVERRIDE_CFG_PVA1RDC, + MC_STREAMID_OVERRIDE_CFG_PVA1WRA, + MC_STREAMID_OVERRIDE_CFG_PVA1WRB, + MC_STREAMID_OVERRIDE_CFG_PVA1WRC, + MC_STREAMID_OVERRIDE_CFG_RCER, + MC_STREAMID_OVERRIDE_CFG_RCEW, + MC_STREAMID_OVERRIDE_CFG_RCEDMAR, + MC_STREAMID_OVERRIDE_CFG_RCEDMAW, + MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, + MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, + MC_STREAMID_OVERRIDE_CFG_PCIE0R, + MC_STREAMID_OVERRIDE_CFG_PCIE0W, + MC_STREAMID_OVERRIDE_CFG_PCIE1R, + MC_STREAMID_OVERRIDE_CFG_PCIE1W, + MC_STREAMID_OVERRIDE_CFG_PCIE2AR, + MC_STREAMID_OVERRIDE_CFG_PCIE2AW, + MC_STREAMID_OVERRIDE_CFG_PCIE3R, + MC_STREAMID_OVERRIDE_CFG_PCIE3W, + MC_STREAMID_OVERRIDE_CFG_PCIE4R, + MC_STREAMID_OVERRIDE_CFG_PCIE4W, + MC_STREAMID_OVERRIDE_CFG_PCIE5R, + MC_STREAMID_OVERRIDE_CFG_PCIE5W, + MC_STREAMID_OVERRIDE_CFG_ISPFALW, + MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, + MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, + MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, + MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, + MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, + MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, + MC_STREAMID_OVERRIDE_CFG_PCIE5R1, + MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, + MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, + MC_STREAMID_OVERRIDE_CFG_ISPRA1, + MC_STREAMID_OVERRIDE_CFG_MIU0R, + MC_STREAMID_OVERRIDE_CFG_MIU0W, + MC_STREAMID_OVERRIDE_CFG_MIU1R, + MC_STREAMID_OVERRIDE_CFG_MIU1W, + MC_STREAMID_OVERRIDE_CFG_MIU2R, + MC_STREAMID_OVERRIDE_CFG_MIU2W, + MC_STREAMID_OVERRIDE_CFG_MIU3R, + MC_STREAMID_OVERRIDE_CFG_MIU3W +}; + +/******************************************************************************* + * Array to hold the security configs for stream IDs + ******************************************************************************/ +const static mc_streamid_security_cfg_t mc_streamid_sec_cfgs[] = { + mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE), + mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE), + mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE), + mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE), + mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), + mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), + mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE), +}; + +/******************************************************************************* + * Array to hold the transaction override configs + ******************************************************************************/ +const static mc_txn_override_cfg_t mc_txn_override_cfgs[] = { + mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR), + mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR), + mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR), + mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR), + mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR), + mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR), + mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR), + mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR), + mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR), + mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(APEW, CGID_TAG_ADR), + mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR), + mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR), + mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR), + mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR), + mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR), + mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR), + mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR), + mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR), + mc_make_txn_override_cfg(AONW, CGID_TAG_ADR), + mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR), + mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR), + mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR), +}; + +#endif //__MEMCTRL_PLAT_CONFIG_H diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h b/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h new file mode 100644 index 000000000..f955e5366 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h @@ -0,0 +1,417 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SMMU_PLAT_CONFIG_H +#define __SMMU_PLAT_CONFIG_H + +#include +#include +#include + +static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = { + _START_OF_TABLE_, + mc_make_sid_security_cfg(PTCR), + mc_make_sid_security_cfg(HDAR), + mc_make_sid_security_cfg(HOST1XDMAR), + mc_make_sid_security_cfg(NVENCSRD), + mc_make_sid_security_cfg(SATAR), + mc_make_sid_security_cfg(MPCORER), + mc_make_sid_security_cfg(NVENCSWR), + mc_make_sid_security_cfg(HDAW), + mc_make_sid_security_cfg(MPCOREW), + mc_make_sid_security_cfg(SATAW), + mc_make_sid_security_cfg(ISPRA), + mc_make_sid_security_cfg(ISPFALR), + mc_make_sid_security_cfg(ISPWA), + mc_make_sid_security_cfg(ISPWB), + mc_make_sid_security_cfg(XUSB_HOSTR), + mc_make_sid_security_cfg(XUSB_HOSTW), + mc_make_sid_security_cfg(XUSB_DEVR), + mc_make_sid_security_cfg(XUSB_DEVW), + mc_make_sid_security_cfg(TSECSRD), + mc_make_sid_security_cfg(TSECSWR), + mc_make_sid_security_cfg(GPUSRD), + mc_make_sid_security_cfg(GPUSWR), + mc_make_sid_security_cfg(SDMMCRA), + mc_make_sid_security_cfg(SDMMCR), + mc_make_sid_security_cfg(SDMMCRAB), + mc_make_sid_security_cfg(SDMMCWA), + mc_make_sid_security_cfg(SDMMCW), + mc_make_sid_security_cfg(SDMMCWAB), + mc_make_sid_security_cfg(VICSRD), + mc_make_sid_security_cfg(VICSWR), + mc_make_sid_security_cfg(VIW), + mc_make_sid_security_cfg(NVDECSRD), + mc_make_sid_security_cfg(NVDECSWR), + mc_make_sid_security_cfg(APER), + mc_make_sid_security_cfg(APEW), + mc_make_sid_security_cfg(NVJPGSRD), + mc_make_sid_security_cfg(NVJPGSWR), + mc_make_sid_security_cfg(SESRD), + mc_make_sid_security_cfg(SESWR), + mc_make_sid_security_cfg(AXIAPR), + mc_make_sid_security_cfg(AXIAPW), + mc_make_sid_security_cfg(ETRR), + mc_make_sid_security_cfg(ETRW), + mc_make_sid_security_cfg(TSECSRDB), + mc_make_sid_security_cfg(TSECSWRB), + mc_make_sid_security_cfg(GPUSRD2), + mc_make_sid_security_cfg(GPUSWR2), + mc_make_sid_security_cfg(AXISR), + mc_make_sid_security_cfg(AXISW), + mc_make_sid_security_cfg(EQOSR), + mc_make_sid_security_cfg(EQOSW), + mc_make_sid_security_cfg(UFSHCR), + mc_make_sid_security_cfg(UFSHCW), + mc_make_sid_security_cfg(NVDISPLAYR), + mc_make_sid_security_cfg(BPMPR), + mc_make_sid_security_cfg(BPMPW), + mc_make_sid_security_cfg(BPMPDMAR), + mc_make_sid_security_cfg(BPMPDMAW), + mc_make_sid_security_cfg(AONR), + mc_make_sid_security_cfg(AONW), + mc_make_sid_security_cfg(AONDMAR), + mc_make_sid_security_cfg(AONDMAW), + mc_make_sid_security_cfg(SCER), + mc_make_sid_security_cfg(SCEW), + mc_make_sid_security_cfg(SCEDMAR), + mc_make_sid_security_cfg(SCEDMAW), + mc_make_sid_security_cfg(APEDMAR), + mc_make_sid_security_cfg(APEDMAW), + mc_make_sid_security_cfg(NVDISPLAYR1), + mc_make_sid_security_cfg(VICSRD1), + mc_make_sid_security_cfg(NVDECSRD1), + mc_make_sid_security_cfg(VIFALR), + mc_make_sid_security_cfg(VIFALW), + mc_make_sid_security_cfg(DLA0RDA), + mc_make_sid_security_cfg(DLA0FALRDB), + mc_make_sid_security_cfg(DLA0WRA), + mc_make_sid_security_cfg(DLA0FALWRB), + mc_make_sid_security_cfg(DLA1RDA), + mc_make_sid_security_cfg(DLA1FALRDB), + mc_make_sid_security_cfg(DLA1WRA), + mc_make_sid_security_cfg(DLA1FALWRB), + mc_make_sid_security_cfg(PVA0RDA), + mc_make_sid_security_cfg(PVA0RDB), + mc_make_sid_security_cfg(PVA0RDC), + mc_make_sid_security_cfg(PVA0WRA), + mc_make_sid_security_cfg(PVA0WRB), + mc_make_sid_security_cfg(PVA0WRC), + mc_make_sid_security_cfg(PVA1RDA), + mc_make_sid_security_cfg(PVA1RDB), + mc_make_sid_security_cfg(PVA1RDC), + mc_make_sid_security_cfg(PVA1WRA), + mc_make_sid_security_cfg(PVA1WRB), + mc_make_sid_security_cfg(PVA1WRC), + mc_make_sid_security_cfg(RCER), + mc_make_sid_security_cfg(RCEW), + mc_make_sid_security_cfg(RCEDMAR), + mc_make_sid_security_cfg(RCEDMAW), + mc_make_sid_security_cfg(NVENC1SRD), + mc_make_sid_security_cfg(NVENC1SWR), + mc_make_sid_security_cfg(PCIE0R), + mc_make_sid_security_cfg(PCIE0W), + mc_make_sid_security_cfg(PCIE1R), + mc_make_sid_security_cfg(PCIE1W), + mc_make_sid_security_cfg(PCIE2AR), + mc_make_sid_security_cfg(PCIE2AW), + mc_make_sid_security_cfg(PCIE3R), + mc_make_sid_security_cfg(PCIE3W), + mc_make_sid_security_cfg(PCIE4R), + mc_make_sid_security_cfg(PCIE4W), + mc_make_sid_security_cfg(PCIE5R), + mc_make_sid_security_cfg(PCIE5W), + mc_make_sid_security_cfg(ISPFALW), + mc_make_sid_security_cfg(DLA0RDA1), + mc_make_sid_security_cfg(DLA1RDA1), + mc_make_sid_security_cfg(PVA0RDA1), + mc_make_sid_security_cfg(PVA0RDB1), + mc_make_sid_security_cfg(PVA1RDA1), + mc_make_sid_security_cfg(PVA1RDB1), + mc_make_sid_security_cfg(PCIE5R1), + mc_make_sid_security_cfg(NVENCSRD1), + mc_make_sid_security_cfg(NVENC1SRD1), + mc_make_sid_security_cfg(ISPRA1), + mc_make_sid_security_cfg(MIU0R), + mc_make_sid_security_cfg(MIU0W), + mc_make_sid_security_cfg(MIU1R), + mc_make_sid_security_cfg(MIU1W), + mc_make_sid_security_cfg(MIU2R), + mc_make_sid_security_cfg(MIU2W), + mc_make_sid_security_cfg(MIU3R), + mc_make_sid_security_cfg(MIU3W), + mc_make_sid_override_cfg(PTCR), + mc_make_sid_override_cfg(HDAR), + mc_make_sid_override_cfg(HOST1XDMAR), + mc_make_sid_override_cfg(NVENCSRD), + mc_make_sid_override_cfg(SATAR), + mc_make_sid_override_cfg(MPCORER), + mc_make_sid_override_cfg(NVENCSWR), + mc_make_sid_override_cfg(HDAW), + mc_make_sid_override_cfg(MPCOREW), + mc_make_sid_override_cfg(SATAW), + mc_make_sid_override_cfg(ISPRA), + mc_make_sid_override_cfg(ISPFALR), + mc_make_sid_override_cfg(ISPWA), + mc_make_sid_override_cfg(ISPWB), + mc_make_sid_override_cfg(XUSB_HOSTR), + mc_make_sid_override_cfg(XUSB_HOSTW), + mc_make_sid_override_cfg(XUSB_DEVR), + mc_make_sid_override_cfg(XUSB_DEVW), + mc_make_sid_override_cfg(TSECSRD), + mc_make_sid_override_cfg(TSECSWR), + mc_make_sid_override_cfg(GPUSRD), + mc_make_sid_override_cfg(GPUSWR), + mc_make_sid_override_cfg(SDMMCRA), + mc_make_sid_override_cfg(SDMMCR), + mc_make_sid_override_cfg(SDMMCRAB), + mc_make_sid_override_cfg(SDMMCWA), + mc_make_sid_override_cfg(SDMMCW), + mc_make_sid_override_cfg(SDMMCWAB), + mc_make_sid_override_cfg(VICSRD), + mc_make_sid_override_cfg(VICSWR), + mc_make_sid_override_cfg(VIW), + mc_make_sid_override_cfg(NVDECSRD), + mc_make_sid_override_cfg(NVDECSWR), + mc_make_sid_override_cfg(APER), + mc_make_sid_override_cfg(APEW), + mc_make_sid_override_cfg(NVJPGSRD), + mc_make_sid_override_cfg(NVJPGSWR), + mc_make_sid_override_cfg(SESRD), + mc_make_sid_override_cfg(SESWR), + mc_make_sid_override_cfg(AXIAPR), + mc_make_sid_override_cfg(AXIAPW), + mc_make_sid_override_cfg(ETRR), + mc_make_sid_override_cfg(ETRW), + mc_make_sid_override_cfg(TSECSRDB), + mc_make_sid_override_cfg(TSECSWRB), + mc_make_sid_override_cfg(GPUSRD2), + mc_make_sid_override_cfg(GPUSWR2), + mc_make_sid_override_cfg(AXISR), + mc_make_sid_override_cfg(AXISW), + mc_make_sid_override_cfg(EQOSR), + mc_make_sid_override_cfg(EQOSW), + mc_make_sid_override_cfg(UFSHCR), + mc_make_sid_override_cfg(UFSHCW), + mc_make_sid_override_cfg(NVDISPLAYR), + mc_make_sid_override_cfg(BPMPR), + mc_make_sid_override_cfg(BPMPW), + mc_make_sid_override_cfg(BPMPDMAR), + mc_make_sid_override_cfg(BPMPDMAW), + mc_make_sid_override_cfg(AONR), + mc_make_sid_override_cfg(AONW), + mc_make_sid_override_cfg(AONDMAR), + mc_make_sid_override_cfg(AONDMAW), + mc_make_sid_override_cfg(SCER), + mc_make_sid_override_cfg(SCEW), + mc_make_sid_override_cfg(SCEDMAR), + mc_make_sid_override_cfg(SCEDMAW), + mc_make_sid_override_cfg(APEDMAR), + mc_make_sid_override_cfg(APEDMAW), + mc_make_sid_override_cfg(NVDISPLAYR1), + mc_make_sid_override_cfg(VICSRD1), + mc_make_sid_override_cfg(NVDECSRD1), + mc_make_sid_override_cfg(VIFALR), + mc_make_sid_override_cfg(VIFALW), + mc_make_sid_override_cfg(DLA0RDA), + mc_make_sid_override_cfg(DLA0FALRDB), + mc_make_sid_override_cfg(DLA0WRA), + mc_make_sid_override_cfg(DLA0FALWRB), + mc_make_sid_override_cfg(DLA1RDA), + mc_make_sid_override_cfg(DLA1FALRDB), + mc_make_sid_override_cfg(DLA1WRA), + mc_make_sid_override_cfg(DLA1FALWRB), + mc_make_sid_override_cfg(PVA0RDA), + mc_make_sid_override_cfg(PVA0RDB), + mc_make_sid_override_cfg(PVA0RDC), + mc_make_sid_override_cfg(PVA0WRA), + mc_make_sid_override_cfg(PVA0WRB), + mc_make_sid_override_cfg(PVA0WRC), + mc_make_sid_override_cfg(PVA1RDA), + mc_make_sid_override_cfg(PVA1RDB), + mc_make_sid_override_cfg(PVA1RDC), + mc_make_sid_override_cfg(PVA1WRA), + mc_make_sid_override_cfg(PVA1WRB), + mc_make_sid_override_cfg(PVA1WRC), + mc_make_sid_override_cfg(RCER), + mc_make_sid_override_cfg(RCEW), + mc_make_sid_override_cfg(RCEDMAR), + mc_make_sid_override_cfg(RCEDMAW), + mc_make_sid_override_cfg(NVENC1SRD), + mc_make_sid_override_cfg(NVENC1SWR), + mc_make_sid_override_cfg(PCIE0R), + mc_make_sid_override_cfg(PCIE0W), + mc_make_sid_override_cfg(PCIE1R), + mc_make_sid_override_cfg(PCIE1W), + mc_make_sid_override_cfg(PCIE2AR), + mc_make_sid_override_cfg(PCIE2AW), + mc_make_sid_override_cfg(PCIE3R), + mc_make_sid_override_cfg(PCIE3W), + mc_make_sid_override_cfg(PCIE4R), + mc_make_sid_override_cfg(PCIE4W), + mc_make_sid_override_cfg(PCIE5R), + mc_make_sid_override_cfg(PCIE5W), + mc_make_sid_override_cfg(ISPFALW), + mc_make_sid_override_cfg(DLA0RDA1), + mc_make_sid_override_cfg(DLA1RDA1), + mc_make_sid_override_cfg(PVA0RDA1), + mc_make_sid_override_cfg(PVA0RDB1), + mc_make_sid_override_cfg(PVA1RDA1), + mc_make_sid_override_cfg(PVA1RDB1), + mc_make_sid_override_cfg(PCIE5R1), + mc_make_sid_override_cfg(NVENCSRD1), + mc_make_sid_override_cfg(NVENC1SRD1), + mc_make_sid_override_cfg(ISPRA1), + mc_make_sid_override_cfg(MIU0R), + mc_make_sid_override_cfg(MIU0W), + mc_make_sid_override_cfg(MIU1R), + mc_make_sid_override_cfg(MIU1W), + mc_make_sid_override_cfg(MIU2R), + mc_make_sid_override_cfg(MIU2W), + mc_make_sid_override_cfg(MIU3R), + mc_make_sid_override_cfg(MIU3W), + smmu_make_gnsr0_nsec_cfg(CR0), + smmu_make_gnsr0_sec_cfg(IDR0), + smmu_make_gnsr0_sec_cfg(IDR1), + smmu_make_gnsr0_sec_cfg(IDR2), + smmu_make_gnsr0_nsec_cfg(GFSR), + smmu_make_gnsr0_nsec_cfg(GFSYNR0), + smmu_make_gnsr0_nsec_cfg(GFSYNR1), + smmu_make_gnsr0_nsec_cfg(TLBGSTATUS), + smmu_make_gnsr0_nsec_cfg(PIDR2), + smmu_make_smrg_group(0), + smmu_make_smrg_group(1), + smmu_make_smrg_group(2), + smmu_make_smrg_group(3), + smmu_make_smrg_group(4), + smmu_make_smrg_group(5), + smmu_make_smrg_group(6), + smmu_make_smrg_group(7), + smmu_make_smrg_group(8), + smmu_make_smrg_group(9), + smmu_make_smrg_group(10), + smmu_make_smrg_group(11), + smmu_make_smrg_group(12), + smmu_make_smrg_group(13), + smmu_make_smrg_group(14), + smmu_make_smrg_group(15), + smmu_make_smrg_group(16), + smmu_make_smrg_group(17), + smmu_make_smrg_group(18), + smmu_make_smrg_group(19), + smmu_make_smrg_group(20), + smmu_make_smrg_group(21), + smmu_make_smrg_group(22), + smmu_make_smrg_group(23), + smmu_make_smrg_group(24), + smmu_make_smrg_group(25), + smmu_make_smrg_group(26), + smmu_make_smrg_group(27), + smmu_make_smrg_group(28), + smmu_make_smrg_group(29), + smmu_make_smrg_group(30), + smmu_make_smrg_group(31), + smmu_make_smrg_group(32), + smmu_make_smrg_group(33), + smmu_make_smrg_group(34), + smmu_make_smrg_group(35), + smmu_make_smrg_group(36), + smmu_make_smrg_group(37), + smmu_make_smrg_group(38), + smmu_make_smrg_group(39), + smmu_make_smrg_group(40), + smmu_make_smrg_group(41), + smmu_make_smrg_group(42), + smmu_make_smrg_group(43), + smmu_make_smrg_group(44), + smmu_make_smrg_group(45), + smmu_make_smrg_group(46), + smmu_make_smrg_group(47), + smmu_make_smrg_group(48), + smmu_make_smrg_group(49), + smmu_make_smrg_group(50), + smmu_make_smrg_group(51), + smmu_make_smrg_group(52), + smmu_make_smrg_group(53), + smmu_make_smrg_group(54), + smmu_make_smrg_group(55), + smmu_make_smrg_group(56), + smmu_make_smrg_group(57), + smmu_make_smrg_group(58), + smmu_make_smrg_group(59), + smmu_make_smrg_group(60), + smmu_make_smrg_group(61), + smmu_make_smrg_group(62), + smmu_make_smrg_group(63), + smmu_make_cb_group(0), + smmu_make_cb_group(1), + smmu_make_cb_group(2), + smmu_make_cb_group(3), + smmu_make_cb_group(4), + smmu_make_cb_group(5), + smmu_make_cb_group(6), + smmu_make_cb_group(7), + smmu_make_cb_group(8), + smmu_make_cb_group(9), + smmu_make_cb_group(10), + smmu_make_cb_group(11), + smmu_make_cb_group(12), + smmu_make_cb_group(13), + smmu_make_cb_group(14), + smmu_make_cb_group(15), + smmu_make_cb_group(16), + smmu_make_cb_group(17), + smmu_make_cb_group(18), + smmu_make_cb_group(19), + smmu_make_cb_group(20), + smmu_make_cb_group(21), + smmu_make_cb_group(22), + smmu_make_cb_group(23), + smmu_make_cb_group(24), + smmu_make_cb_group(25), + smmu_make_cb_group(26), + smmu_make_cb_group(27), + smmu_make_cb_group(28), + smmu_make_cb_group(29), + smmu_make_cb_group(30), + smmu_make_cb_group(31), + smmu_make_cb_group(32), + smmu_make_cb_group(33), + smmu_make_cb_group(34), + smmu_make_cb_group(35), + smmu_make_cb_group(36), + smmu_make_cb_group(37), + smmu_make_cb_group(38), + smmu_make_cb_group(39), + smmu_make_cb_group(40), + smmu_make_cb_group(41), + smmu_make_cb_group(42), + smmu_make_cb_group(43), + smmu_make_cb_group(44), + smmu_make_cb_group(45), + smmu_make_cb_group(46), + smmu_make_cb_group(47), + smmu_make_cb_group(48), + smmu_make_cb_group(49), + smmu_make_cb_group(50), + smmu_make_cb_group(51), + smmu_make_cb_group(52), + smmu_make_cb_group(53), + smmu_make_cb_group(54), + smmu_make_cb_group(55), + smmu_make_cb_group(56), + smmu_make_cb_group(57), + smmu_make_cb_group(58), + smmu_make_cb_group(59), + smmu_make_cb_group(60), + smmu_make_cb_group(61), + smmu_make_cb_group(62), + smmu_make_cb_group(63), + smmu_bypass_cfg, /* TBU settings */ + _END_OF_TABLE_, +}; + +#endif //__SMMU_PLAT_CONFIG_H -- cgit v1.2.3 From 0ea8881ea3c776491ab9b1326798b1283f0cec1f Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Tue, 24 Jan 2017 14:16:07 +0530 Subject: Tegra194: add support for multiple SMMU devices This patch adds support for all three SMMU devices present on the SoC. The following changes have been done: Add SMMU devices to the memory map Update register read and write functions Change-Id: I0007b496d2ae7264f4fa9f605d4b0a15fa747a0f Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/include/t194/tegra_def.h | 4 +++- .../soc/t194/drivers/include/smmu_plat_config.h | 25 ++++++++++++++++++++++ plat/nvidia/tegra/soc/t194/plat_setup.c | 6 +++++- plat/nvidia/tegra/soc/t194/platform_t194.mk | 3 +++ 4 files changed, 36 insertions(+), 2 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 8e7b28cac..7bdd975fc 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -219,7 +219,9 @@ /******************************************************************************* * Tegra SMMU Controller constants ******************************************************************************/ -#define TEGRA_SMMU_BASE 0x10000000 +#define TEGRA_SMMU0_BASE 0x12000000 +#define TEGRA_SMMU1_BASE 0x11000000 +#define TEGRA_SMMU2_BASE 0x10000000 /******************************************************************************* * Tegra TZRAM constants diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h b/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h index f955e5366..72547110e 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h @@ -414,4 +414,29 @@ static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = { _END_OF_TABLE_, }; +static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off) +{ + if (smmu_id == 0) + return mmio_read_32(TEGRA_SMMU0_BASE + off); + else if (smmu_id == 1) + return mmio_read_32(TEGRA_SMMU1_BASE + off); + else if (smmu_id == 2) + return mmio_read_32(TEGRA_SMMU2_BASE + off); + else + panic(); +} + +static inline void tegra_smmu_write_32(uint32_t smmu_id, + uint32_t off, uint32_t val) +{ + if (smmu_id == 0) + mmio_write_32(TEGRA_SMMU0_BASE + off, val); + else if (smmu_id == 1) + mmio_write_32(TEGRA_SMMU1_BASE + off, val); + else if (smmu_id == 2) + mmio_write_32(TEGRA_SMMU2_BASE + off, val); + else + panic(); +} + #endif //__SMMU_PLAT_CONFIG_H diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index aab884e73..3424d1928 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -81,7 +81,11 @@ static const mmap_region_t tegra_mmap[] = { MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ + MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */ MT_DEVICE | MT_RW | MT_SECURE), {0} }; diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 54bc9419a..cb31bdd18 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -23,6 +23,9 @@ $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) ENABLE_SMMU_DEVICE := 0 $(eval $(call add_define,ENABLE_SMMU_DEVICE)) +NUM_SMMU_DEVICES := 3 +$(eval $(call add_define,NUM_SMMU_DEVICES)) + RESET_TO_BL31 := 1 PROGRAMMABLE_RESET_ADDRESS := 1 -- cgit v1.2.3 From 5660eebf39d55e6da2a91080ee468887d264854c Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Tue, 24 Jan 2017 14:44:57 +0530 Subject: Tegra194: enable SMMU Enable smmu by setting ENABLE_SMMU_DEVICE to 1. Change-Id: I9135071b257a166fa6082b7fe409bcd315cf6838 Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/soc/t194/platform_t194.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index cb31bdd18..8a61759b3 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -20,7 +20,7 @@ $(eval $(call add_define,RELOCATE_TO_BL31_BASE)) ENABLE_CHIP_VERIFICATION_HARNESS := 0 $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) -ENABLE_SMMU_DEVICE := 0 +ENABLE_SMMU_DEVICE := 1 $(eval $(call add_define,ENABLE_SMMU_DEVICE)) NUM_SMMU_DEVICES := 3 -- cgit v1.2.3 From 9808032cd9dba9c46ceb0cea1e90a3ae80b0c00d Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Thu, 5 Jan 2017 17:04:40 +0800 Subject: Tegra194: Enable MCE driver This patch enable MCE driver for T19x SoC. The MCE driver takes care of the communication with the MCE firmware to achieve: - Cold boot - Warm boot - Core/Cluster/System Power management - Custom MCE requests Change-Id: I75854c0b649a691e9b244d9ed9fc1c19743e3e8d Signed-off-by: Steven Kao --- .../tegra/soc/t194/drivers/include/mce_private.h | 170 +++------ .../tegra/soc/t194/drivers/include/t194_nvg.h | 275 ++++++++++++++ plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 228 +++++------- plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 409 ++++++++++++++------- plat/nvidia/tegra/soc/t194/plat_secondary.c | 3 - plat/nvidia/tegra/soc/t194/platform_t194.mk | 2 + 6 files changed, 683 insertions(+), 404 deletions(-) create mode 100644 plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 473540473..cc32ec416 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -14,143 +14,61 @@ * Macros to prepare CSTATE info request ******************************************************************************/ /* Description of the parameters for UPDATE_CSTATE_INFO request */ -#define CLUSTER_CSTATE_MASK 0x7 -#define CLUSTER_CSTATE_SHIFT 0 -#define CLUSTER_CSTATE_UPDATE_BIT (1 << 7) -#define CCPLEX_CSTATE_MASK 0x3 -#define CCPLEX_CSTATE_SHIFT 8 -#define CCPLEX_CSTATE_UPDATE_BIT (1 << 15) -#define SYSTEM_CSTATE_MASK 0xF -#define SYSTEM_CSTATE_SHIFT 16 -#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22 -#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1 << 22) -#define SYSTEM_CSTATE_UPDATE_BIT (1 << 23) -#define CSTATE_WAKE_MASK_UPDATE_BIT (1 << 31) -#define CSTATE_WAKE_MASK_SHIFT 32 -#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFF +#define CLUSTER_CSTATE_MASK 0x7UL +#define CLUSTER_CSTATE_SHIFT 0X0UL +#define CLUSTER_CSTATE_UPDATE_BIT (1UL << 7) +#define CCPLEX_CSTATE_MASK 0x3UL +#define CCPLEX_CSTATE_SHIFT 8UL +#define CCPLEX_CSTATE_UPDATE_BIT (1UL << 15) +#define SYSTEM_CSTATE_MASK 0xFUL +#define SYSTEM_CSTATE_SHIFT 16UL +#define SYSTEM_CSTATE_UPDATE_BIT (1UL << 23) +#define CSTATE_WAKE_MASK_UPDATE_BIT (1UL << 31) +#define CSTATE_WAKE_MASK_SHIFT 32UL +#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFUL /******************************************************************************* * Auto-CC3 control macros ******************************************************************************/ -#define MCE_AUTO_CC3_FREQ_MASK 0x1FF -#define MCE_AUTO_CC3_FREQ_SHIFT 0 -#define MCE_AUTO_CC3_VTG_MASK 0x7F -#define MCE_AUTO_CC3_VTG_SHIFT 16 -#define MCE_AUTO_CC3_ENABLE_BIT (1 << 31) +#define MCE_AUTO_CC3_FREQ_MASK 0xFFUL +#define MCE_AUTO_CC3_FREQ_SHIFT 0UL +#define MCE_AUTO_CC3_ENABLE_BIT (1UL << 31) /******************************************************************************* - * Macros for the 'IS_SC7_ALLOWED' command + * Core ID mask (bits 3:0 in the online request) ******************************************************************************/ -#define MCE_SC7_ALLOWED_MASK 0x7 -#define MCE_SC7_WAKE_TIME_SHIFT 32 +#define MCE_CORE_ID_MASK 0xFUL /******************************************************************************* - * Macros for 'read/write ctats' commands + * Cache control macros ******************************************************************************/ -#define MCE_CSTATE_STATS_TYPE_SHIFT 32 -#define MCE_CSTATE_WRITE_DATA_LO_MASK 0xF - -/******************************************************************************* - * Macros for 'update crossover threshold' command - ******************************************************************************/ -#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32 - -/******************************************************************************* - * Timeout value used to powerdown a core - ******************************************************************************/ -#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF - -/******************************************************************************* - * MCA command struct - ******************************************************************************/ -typedef union mca_cmd { - struct command { - uint8_t cmd; - uint8_t idx; - uint8_t subidx; - } command; - struct input { - uint32_t low; - uint32_t high; - } input; - uint64_t data; -} mca_cmd_t; - -/******************************************************************************* - * MCA argument struct - ******************************************************************************/ -typedef union mca_arg { - struct err { - uint64_t error:8; - uint64_t unused:48; - uint64_t finish:8; - } err; - struct arg { - uint32_t low; - uint32_t high; - } arg; - uint64_t data; -} mca_arg_t; - -/******************************************************************************* - * Uncore PERFMON ARI struct - ******************************************************************************/ -typedef union uncore_perfmon_req { - struct perfmon_command { - /* - * Commands: 0 = READ, 1 = WRITE - */ - uint64_t cmd:8; - /* - * The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4 - */ - uint64_t grp:4; - /* - * Unit selector: Selects the unit instance, with 0 = Unit - * = (number of units in group) - 1. - */ - uint64_t unit:4; - /* - * Selects the uncore perfmon register to access - */ - uint64_t reg:8; - /* - * Counter number. Selects which counter to use for - * registers NV_PMEVCNTR and NV_PMEVTYPER. - */ - uint64_t counter:8; - } perfmon_command; - struct perfmon_status { - /* - * Resulting command status - */ - uint64_t val:8; - uint64_t unused:24; - } perfmon_status; - uint64_t data; -} uncore_perfmon_req_t; - -#define UNCORE_PERFMON_CMD_READ 0 -#define UNCORE_PERFMON_CMD_WRITE 1 - -#define UNCORE_PERFMON_CMD_MASK 0xFF -#define UNCORE_PERFMON_UNIT_GRP_MASK 0xF -#define UNCORE_PERFMON_SELECTOR_MASK 0xF -#define UNCORE_PERFMON_REG_MASK 0xFF -#define UNCORE_PERFMON_CTR_MASK 0xFF -#define UNCORE_PERFMON_RESP_STATUS_MASK 0xFF +#define CACHE_CLEAN_SET (1UL << 0) +#define CACHE_CLEAN_INVAL_SET (1UL << 1) +#define CACHE_CLEAN_INVAL_TR_SET (1UL << 2) /* declarations for NVG handler functions */ -int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); -int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, - uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, - uint8_t update_wake_mask); -int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); -uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state); -int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t val); -int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); -int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); -int nvg_online_core(uint32_t ari_base, uint32_t core); -int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); +uint64_t nvg_get_version(void); +int32_t nvg_enable_power_perf_mode(void); +int32_t nvg_disable_power_perf_mode(void); +int32_t nvg_enable_power_saver_modes(void); +int32_t nvg_disable_power_saver_modes(void); +void nvg_set_wake_time(uint32_t wake_time); +void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, + uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask); +int32_t nvg_update_crossover_time(uint32_t type, uint32_t time); +int32_t nvg_set_cstate_stat_query_value(uint64_t data); +uint64_t nvg_get_cstate_stat_query_value(void); +int32_t nvg_is_sc7_allowed(void); +int32_t nvg_online_core(uint32_t core); +int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable); +int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); +int32_t nvg_roc_flush_cache(void); +int32_t nvg_roc_clean_cache(void); +int32_t nvg_roc_clean_cache_trbits(void); +int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); + +void nvg_set_request_data(uint64_t req, uint64_t data); +void nvg_set_request(uint64_t req); +uint64_t nvg_get_result(void); #endif /* __MCE_PRIVATE_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h new file mode 100644 index 000000000..1fe462032 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef T194_NVG_H +#define T194_NVG_H + +/** + * t194_nvg.h - Header for the NVIDIA Generic interface (NVG). + * Official documentation for this interface is included as part + * of the T194 TRM. + */ + +/** + * Current version - Major version increments may break backwards + * compatiblity and binary compatibility. Minor version increments + * occur when there is only new functionality. + */ +enum { + TEGRA_NVG_VERSION_MAJOR = 6, + TEGRA_NVG_VERSION_MINOR = 0, +}; + +typedef enum { + TEGRA_NVG_CHANNEL_VERSION = 0, + TEGRA_NVG_CHANNEL_POWER_PERF = 1, + TEGRA_NVG_CHANNEL_POWER_MODES = 2, + TEGRA_NVG_CHANNEL_WAKE_TIME = 3, + TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, + TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, + TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, + // Value 7 reserved + TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, + // Value 9 reserved + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, + // Values 12-42 reserved + TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, + TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, + TEGRA_NVG_CHANNEL_CC3_CTRL = 45, + TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, + TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL = 51, + // 52 FREQ FEEDBACK + TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, + TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, + TEGRA_NVG_CHANNEL_LAST_INDEX, +} tegra_nvg_channel_id_t; + + +typedef enum { + // Value 0 reserved + NVG_STAT_QUERY_SC7_ENTRIES = 1, + // Values 2-5 reserved + NVG_STAT_QUERY_CC6_ENTRIES = 6, + NVG_STAT_QUERY_CG7_ENTRIES = 7, + // Values 8-9 reserved + NVG_STAT_QUERY_C6_ENTRIES = 10, + // Values 11-13 reserved + NVG_STAT_QUERY_C7_ENTRIES = 14, + // Values 15-31 reserved + NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, + NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, + NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, + NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, + NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56, +} tegra_nvg_stat_query_t; + + +typedef enum { + TEGRA_NVG_CORE_C0 = 0, + TEGRA_NVG_CORE_C1 = 1, + TEGRA_NVG_CORE_C6 = 6, + TEGRA_NVG_CORE_C7 = 7, + TEGRA_NVG_CORE_WARMRSTREQ = 8, +} tegra_nvg_core_sleep_state_t; + +typedef enum { + TEGRA_NVG_CLUSTER_CC0 = 0, + TEGRA_NVG_CLUSTER_CC6 = 6, +} tegra_nvg_cluster_sleep_state_t; + +typedef enum { + TEGRA_NVG_CCPLEX_CG0 = 0, + TEGRA_NVG_CCPLEX_CG7 = 1, + +} tegra_nvg_cluster_group_sleep_state_t; + +typedef enum { + TEGRA_NVG_SYSTEM_SC0 = 0, + TEGRA_NVG_SYSTEM_SC7 = 7, + TEGRA_NVG_SYSTEM_SC8 = 8, +} tegra_nvg_system_sleep_state_t; + +// --------------------------------------------------------------------------- +// NVG Data subformats +// --------------------------------------------------------------------------- + +typedef union +{ + uint64_t flat; + struct nvg_version_channel_t { + uint64_t minor_version : 32; + uint64_t major_version : 32; + } bits; +} nvg_version_data_t; + +typedef union nvg_channel_1_data_u +{ + uint64_t flat; + struct nvg_channel_1_data_s + { + uint64_t perf_per_watt_mode : 1; + uint64_t reserved_63_1 : 63; + } bits; +} nvg_channel_1_data_t; + +typedef union nvg_channel_2_data_u +{ + uint64_t flat; + struct nvg_channel_2_data_s + { + uint64_t reserved_1_0 : 2; + uint64_t battery_saver_mode : 1; + uint64_t reserved_63_3 : 61; + } bits; +} nvg_channel_2_data_t; + +typedef union +{ + uint64_t flat; + struct nvg_wake_time_channel_t { + uint64_t wake_time : 32; + uint64_t reserved_63_32 : 32; + } bits; +} nvg_wake_time_channel_t; + +typedef union +{ + uint64_t flat; + struct nvg_cstate_info_channel_t { + uint64_t cluster_state : 3; + uint64_t reserved_6_3 : 4; + uint64_t update_cluster : 1; + uint64_t cg_cstate : 3; + uint64_t reserved_14_11 : 4; + uint64_t update_cg : 1; + uint64_t system_cstate : 4; + uint64_t reserved_22_20 : 3; + uint64_t update_system : 1; + uint64_t reserved_30_24 : 7; + uint64_t update_wake_mask : 1; + uint64_t wake_mask : 32; + } bits; +} nvg_cstate_info_channel_t; + +typedef union +{ + uint64_t flat; + struct nvg_lower_bound_channel_t { + uint64_t crossover_value : 32; + uint64_t reserved_63_32 : 32; + } bits; +} nvg_lower_bound_channel_t; + + +typedef union +{ + uint64_t flat; + struct nvg_cstate_stat_query_channel_t { + uint64_t unit_id : 4; + uint64_t reserved_15_4 : 12; + uint64_t stat_id : 16; + uint64_t reserved_63_32 : 32; + } bits; +} nvg_cstate_stat_query_channel_t; + +typedef union +{ + uint64_t flat; + struct nvg_is_sc7_allowed_channel_t { + uint64_t is_sc7_allowed : 1; + uint64_t reserved_63_32 : 63; + } bits; +} nvg_is_sc7_allowed_channel_t; + + +typedef union +{ + uint64_t flat; + struct nvg_core_online_channel_t { + uint64_t core_id : 4; + uint64_t reserved_63_4 : 60; + } bits; +} nvg_core_online_channel_t; + + +typedef union +{ + uint64_t flat; + struct nvg_cc3_control_channel_t { + uint64_t freq_req : 8; + uint64_t reserved_30_8 : 23; + uint64_t enable : 1; + uint64_t reserved_63_32 : 32; + } bits; +} nvg_cc3_control_channel_t; + + +typedef union +{ + uint64_t flat; + struct nvg_update_gsc_channel_t { + uint64_t gsc_enum : 16; + uint64_t reserved_63_16 : 48; + } bits; +} nvg_update_gsc_channel_t; + + +typedef union +{ + uint64_t flat; + struct nvg_cache_inval_channel_t { + uint64_t cache_clean : 1; + uint64_t cache_clean_inval : 1; + uint64_t cache_clean_inval_tr : 1; + uint64_t reserved_63_3 : 61; + } bits; +} nvg_cache_inval_channel_t; + + +/* GSC type define */ +typedef enum { + TEGRA_NVG_GSC_ALL=0, + TEGRA_NVG_GSC_NVDEC=1, + TEGRA_NVG_GSC_WPR1=2, + TEGRA_NVG_GSC_WPR2=3, + TEGRA_NVG_GSC_TSECA=4, + TEGRA_NVG_GSC_TSECB=5, + + TEGRA_NVG_GSC_BPMP=6, + TEGRA_NVG_GSC_APE=7, + TEGRA_NVG_GSC_SPE=8, + TEGRA_NVG_GSC_SCE=9, + TEGRA_NVG_GSC_APR=10, + TEGRA_NVG_GSC_TZRAM=11, + TEGRA_NVG_GSC_SE=12, + + TEGRA_NVG_GSC_DMCE=13, + TEGRA_NVG_GSC_BPMP_TO_DMCE=14, + TEGRA_NVG_GSC_BPMP_TO_SPE=16, + TEGRA_NVG_GSC_CPU_TZ_TO_BPMP=18, + TEGRA_NVG_GSC_CPU_NS_TO_BPMP=20, + TEGRA_NVG_GSC_IPC_SE_SPE_SCE_BPMP=22, + TEGRA_NVG_GSC_SC7_RESUME_FW=23, + + TEGRA_NVG_GSC_VPR_RESIZE=24, + TEGRA_NVG_GSC_RCE=25, + TEGRA_NVG_GSC_CV=26, + + TEGRA_NVG_GSC_BO_MTS_PACKAGE=28, + TEGRA_NVG_GSC_BO_MCE_PREBOOT=29, + + TEGRA_NVG_GSC_TZ_DRAM_IDX=34, + TEGRA_NVG_GSC_VPR_IDX=35, +} tegra_nvg_gsc_index_t; + +typedef enum { + TEGRA_NVG_CROSSOVER_C6 = 0, + TEGRA_NVG_CROSSOVER_CC6 = 1, + TEGRA_NVG_CROSSOVER_CG7 = 2, +} tegra_nvg_crossover_index_t; + +#endif // T194_NVG_H diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index 3a2e262f6..4754b77c5 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -15,21 +15,21 @@ #include #include #include +#include #include #include +#include #include #include /******************************************************************************* * Common handler for all MCE commands ******************************************************************************/ -int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, +int32_t mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, uint64_t arg2) { uint64_t ret64 = 0, arg3, arg4, arg5; - int ret = 0; - mca_cmd_t mca_cmd; - uncore_perfmon_req_t req; + int32_t ret = 0; cpu_context_t *ctx = cm_get_context(NON_SECURE); gp_regs_t *gp_regs = get_gpregs_ctx(ctx); @@ -38,7 +38,11 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, switch (cmd) { case MCE_CMD_ENTER_CSTATE: - /* NVG */ + ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1); + if (ret < 0) { + ERROR("%s: enter_cstate failed(%d)\n", __func__, ret); + } + break; case MCE_CMD_UPDATE_CSTATE_INFO: @@ -46,214 +50,147 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, * get the parameters required for the update cstate info * command */ - arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4); - arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5); - arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6); - - /* NVG */ + arg3 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4)); + arg4 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5)); + arg5 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6)); + + /* arg0 cluster + * arg1 ccplex + * arg2 system + * arg3 sys_state_force => T19x not support + * arg4 wake_mask + * arg5 update_wake_mask + */ + nvg_update_cstate_info((uint32_t)arg0, (uint32_t)arg1, + (uint32_t)arg2, (uint32_t)arg4, (uint8_t)arg5); - write_ctx_reg(gp_regs, CTX_GPREG_X4, arg3); - write_ctx_reg(gp_regs, CTX_GPREG_X5, arg4); - write_ctx_reg(gp_regs, CTX_GPREG_X6, arg5); + write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4), (arg3)); + write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5), (arg4)); + write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6), (arg5)); break; case MCE_CMD_UPDATE_CROSSOVER_TIME: - /* NVG */ + ret = nvg_update_crossover_time((uint32_t)arg0, (uint32_t)arg1); + if (ret < 0) { + ERROR("%s: update_crossover_time failed(%d)\n", + __func__, ret); + } break; case MCE_CMD_READ_CSTATE_STATS: - /* NVG */ + ret64 = nvg_get_cstate_stat_query_value(); /* update context to return cstate stats value */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); - write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64); + write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64)); + write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64)); break; case MCE_CMD_WRITE_CSTATE_STATS: - /* NVG */ - - break; - - case MCE_CMD_IS_CCX_ALLOWED: - /* NVG */ - - /* update context to return CCx status value */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret); + ret = nvg_set_cstate_stat_query_value(arg0); break; case MCE_CMD_IS_SC7_ALLOWED: - /* NVG */ + ret = nvg_is_sc7_allowed(); + if (ret < 0) { + ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret); + break; + } /* update context to return SC7 status value */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret); - write_ctx_reg(gp_regs, CTX_GPREG_X3, ret); + write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), ((uint64_t)ret)); + write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X3), ((uint64_t)ret)); break; case MCE_CMD_ONLINE_CORE: - /* NVG */ + ret = nvg_online_core((uint32_t)arg0); + if (ret < 0) { + ERROR("%s: online_core failed(%d)\n", __func__, ret); + } break; case MCE_CMD_CC3_CTRL: - /* NVG */ - - break; - - case MCE_CMD_ECHO_DATA: - /* issue NVG to echo data */ - - /* update context to return if echo'd data matched source */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64 == arg0); - write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64 == arg0); + ret = nvg_cc3_ctrl((uint32_t)arg0, (uint8_t)arg2); + if (ret < 0) { + ERROR("%s: cc3_ctrl failed(%d)\n", __func__, ret); + } break; case MCE_CMD_READ_VERSIONS: /* get the MCE firmware version */ + ret64 = nvg_get_version(); /* * version = minor(63:32) | major(31:0). Update context * to return major and minor version number. */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint32_t)ret64); - write_ctx_reg(gp_regs, CTX_GPREG_X2, (uint32_t)(ret64 >> 32)); + write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64 & (uint64_t)0xFFFF)); + write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64 >> 32)); break; - case MCE_CMD_ENUM_FEATURES: - break; - case MCE_CMD_ROC_FLUSH_CACHE_TRBITS: - /* NVG */ + ret = nvg_roc_clean_cache_trbits(); + if (ret < 0) { + ERROR("%s: flush cache_trbits failed(%d)\n", __func__, + ret); + } break; case MCE_CMD_ROC_FLUSH_CACHE: - /* NVG */ + ret = nvg_roc_flush_cache(); + if (ret < 0) { + ERROR("%s: flush cache failed(%d)\n", __func__, ret); + } break; case MCE_CMD_ROC_CLEAN_CACHE: - /* NVG */ - - break; - - case MCE_CMD_ENUM_READ_MCA: - memcpy(&mca_cmd, &arg0, sizeof(arg0)); - - /* NVG */ - - /* update context to return MCA data/error */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); - write_ctx_reg(gp_regs, CTX_GPREG_X2, arg1); - write_ctx_reg(gp_regs, CTX_GPREG_X3, ret64); - - break; - - case MCE_CMD_ENUM_WRITE_MCA: - memcpy(&mca_cmd, &arg0, sizeof(arg0)); - - /* NVG */ - - /* update context to return MCA error */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); - write_ctx_reg(gp_regs, CTX_GPREG_X3, ret64); - - break; - - case MCE_CMD_ENABLE_LATIC: - /* - * This call is not for production use. The constant value, - * 0xFFFF0000, is specific to allowing for enabling LATIC on - * pre-production parts for the chip verification harness. - * - * Enabling LATIC allows S/W to read the MINI ISPs in the - * CCPLEX. The ISMs are used for various measurements relevant - * to particular locations in the Silicon. They are small - * counters which can be polled to determine how fast a - * particular location in the Silicon is. - */ - /* NVG */ - - break; - - case MCE_CMD_UNCORE_PERFMON_REQ: - memcpy(&req, &arg0, sizeof(arg0)); - /* NVG */ - - /* update context to return data */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, arg1); - break; - - case MCE_CMD_MISC_CCPLEX: - /* NVG */ + ret = nvg_roc_clean_cache(); + if (ret < 0) { + ERROR("%s: clean cache failed(%d)\n", __func__, ret); + } break; default: ERROR("unknown MCE command (%lld)\n", cmd); - return EINVAL; + ret = EINVAL; + break; } return ret; } -/******************************************************************************* - * Handler to update the reset vector for CPUs - ******************************************************************************/ -int mce_update_reset_vector(void) -{ - return 0; -} - -static int mce_update_ccplex_gsc(/* GSC ID */) -{ - return 0; -} - /******************************************************************************* * Handler to update carveout values for Video Memory Carveout region ******************************************************************************/ -int mce_update_gsc_videomem(void) +int32_t mce_update_gsc_videomem(void) { - return mce_update_ccplex_gsc(); + return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_VPR_IDX); } /******************************************************************************* * Handler to update carveout values for TZDRAM aperture ******************************************************************************/ -int mce_update_gsc_tzdram(void) +int32_t mce_update_gsc_tzdram(void) { - return mce_update_ccplex_gsc(); + return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZ_DRAM_IDX); } /******************************************************************************* * Handler to update carveout values for TZ SysRAM aperture ******************************************************************************/ -int mce_update_gsc_tzram(void) +int32_t mce_update_gsc_tzram(void) { - return mce_update_ccplex_gsc(); -} - -/******************************************************************************* - * Handler to shutdown/reset the entire system - ******************************************************************************/ -__dead2 void mce_enter_ccplex_state(uint32_t state_idx) -{ - /* sanity check state value */ - - /* enter ccplex power state */ - - /* wait till the CCPLEX powers down */ - for (;;) - ; - - panic(); + return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZRAM); } /******************************************************************************* @@ -262,7 +199,8 @@ __dead2 void mce_enter_ccplex_state(uint32_t state_idx) void mce_update_cstate_info(mce_cstate_info_t *cstate) { /* issue the UPDATE_CSTATE_INFO request */ - /* NVG */ + nvg_update_cstate_info(cstate->cluster, cstate->ccplex, cstate->system, + cstate->wake_mask, cstate->update_wake_mask); } /******************************************************************************* @@ -277,18 +215,18 @@ void mce_verify_firmware_version(void) /* * MCE firmware is not running on simulation platforms. */ - if (tegra_platform_is_linsim() || tegra_platform_is_virt_dev_kit()) + if ((tegra_platform_is_linsim() == 1U) || + (tegra_platform_is_virt_dev_kit() == 1U)) { return; - - /* get a pointer to the CPU's arch_mce_ops_t struct */ + } /* * Read the MCE firmware version and extract the major and minor * version fields */ - version = 0; - major = (uint32_t)version; - minor = (uint32_t)(version >> 32); + version = nvg_get_version(); + minor = (uint32_t)version; + major = (uint32_t)(version >> 32); INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor, 0, 0); @@ -297,12 +235,12 @@ void mce_verify_firmware_version(void) * Verify that the MCE firmware version and the interface header * match */ - if (major != 0) { + if (major != (uint32_t)TEGRA_NVG_VERSION_MAJOR) { ERROR("MCE major version mismatch\n"); panic(); } - if (minor < 0) { + if (minor < (uint32_t)TEGRA_NVG_VERSION_MINOR) { ERROR("MCE minor version mismatch\n"); panic(); } diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index 36b3aabbb..12dd6cb09 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -8,207 +8,356 @@ #include #include #include +#include #include #include -#include +#include +#include extern void nvg_set_request_data(uint64_t req, uint64_t data); extern void nvg_set_request(uint64_t req); extern uint64_t nvg_get_result(void); -int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) +/* + * Reports the major and minor version of this interface. + * + * NVGDATA[0:31]: SW(R) Minor Version + * NVGDATA[32:63]: SW(R) Major Version + */ +uint64_t nvg_get_version(void) { - /* check for allowed power state */ - if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 && - state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) { - ERROR("%s: unknown cstate (%d)\n", __func__, state); - return EINVAL; - } + nvg_set_request(TEGRA_NVG_CHANNEL_VERSION); - /* time (TSC ticks) until the core is expected to get a wake event */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time); + return (uint64_t)nvg_get_result(); +} - /* set the core cstate */ - write_actlr_el1(state); +/* + * Enable the perf per watt mode. + * + * NVGDATA[0]: SW(RW), 1 = enable perf per watt mode + */ +int32_t nvg_enable_power_perf_mode(void) +{ + nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 1U); + + return 0; +} + +/* + * Disable the perf per watt mode. + * + * NVGDATA[0]: SW(RW), 0 = disable perf per watt mode + */ +int32_t nvg_disable_power_perf_mode(void) +{ + nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 0U); + + return 0; +} + +/* + * Enable the battery saver mode. + * + * NVGDATA[2]: SW(RW), 1 = enable battery saver mode + */ +int32_t nvg_enable_power_saver_modes(void) +{ + nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 1U); + + return 0; +} + +/* + * Disable the battery saver mode. + * + * NVGDATA[2]: SW(RW), 0 = disable battery saver mode + */ +int32_t nvg_disable_power_saver_modes(void) +{ + nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 0U); return 0; } +/* + * Set the expected wake time in TSC ticks for the next low-power state the + * core enters. + * + * NVGDATA[0:31]: SW(RW), WAKE_TIME + */ +void nvg_set_wake_time(uint32_t wake_time) +{ + /* time (TSC ticks) until the core is expected to get a wake event */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); +} + /* * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and * SYSTEM_CSTATE values. + * + * NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE + * NVGDATA[7]: SW(W), update cluster flag + * NVGDATA[8:9]: SW(RW), CG_CSTATE + * NVGDATA[15]: SW(W), update ccplex flag + * NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE + * NVGDATA[23]: SW(W), update system flag + * NVGDATA[31]: SW(W), update wake mask flag + * NVGDATA[32:63]: SW(RW), WAKE_MASK */ -int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, - uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, - uint8_t update_wake_mask) +void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, + uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask) { uint64_t val = 0; /* update CLUSTER_CSTATE? */ - if (cluster) - val |= (cluster & CLUSTER_CSTATE_MASK) | - CLUSTER_CSTATE_UPDATE_BIT; + if (cluster != 0U) { + val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | + CLUSTER_CSTATE_UPDATE_BIT; + } /* update CCPLEX_CSTATE? */ - if (ccplex) - val |= (ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT | - CCPLEX_CSTATE_UPDATE_BIT; + if (ccplex != 0U) { + val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | + CCPLEX_CSTATE_UPDATE_BIT; + } /* update SYSTEM_CSTATE? */ - if (system) - val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | - ((sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | - SYSTEM_CSTATE_UPDATE_BIT); + if (system != 0U) { + val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | + SYSTEM_CSTATE_UPDATE_BIT; + } /* update wake mask value? */ - if (update_wake_mask) + if (update_wake_mask != 0U) { val |= CSTATE_WAKE_MASK_UPDATE_BIT; + } /* set the wake mask */ - val &= CSTATE_WAKE_MASK_CLEAR; - val |= ((uint64_t)wake_mask << CSTATE_WAKE_MASK_SHIFT); + val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT; /* set the updated cstate info */ nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val); - - return 0; } -int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) +/* + * Indices gives MTS the crossover point in TSC ticks for when it becomes + * no longer viable to enter the named state + * + * Type 0 : NVGDATA[0:31]: C6 Lower bound + * Type 1 : NVGDATA[0:31]: CC6 Lower bound + * Type 2 : NVGDATA[0:31]: CG7 Lower bound + */ +int32_t nvg_update_crossover_time(uint32_t type, uint32_t time) { - /* sanity check crossover type */ - if (type > TEGRA_ARI_CROSSOVER_CCP3_SC1) - return EINVAL; - - /* - * The crossover threshold limit types start from - * TEGRA_CROSSOVER_TYPE_C1_C6 to TEGRA_CROSSOVER_TYPE_CCP3_SC7. The - * command indices for updating the threshold can be generated - * by adding the type to the NVG_SET_THRESHOLD_CROSSOVER_C1_C6 - * command index. - */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 + type, - (uint64_t)time); + int32_t ret = 0; + + switch (type) { + case TEGRA_NVG_CROSSOVER_C6: + nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND, + (uint64_t)time); + break; + + case TEGRA_NVG_CROSSOVER_CC6: + nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND, + (uint64_t)time); + break; + + case TEGRA_NVG_CROSSOVER_CG7: + nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND, + (uint64_t)time); + break; + + default: + ERROR("%s: unknown crossover type (%d)\n", __func__, type); + ret = EINVAL; + break; + } - return 0; + return ret; } -uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state) +/* + * These NVG calls allow ARM SW to access CSTATE statistical information + * + * NVGDATA[0:3]: SW(RW) Core/cluster/cg id + * NVGDATA[16:31]: SW(RW) Stat id + */ +int32_t nvg_set_cstate_stat_query_value(uint64_t data) { - /* sanity check state */ - if (state == 0) - return EINVAL; - - /* - * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES - * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for - * reading the threshold can be generated by adding the type to - * the NVG_CLEAR_CSTATE_STATS command index. - */ - nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + state); + int32_t ret = 0; + + /* sanity check stat id */ + if (data > (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) { + ERROR("%s: unknown stat id (%d)\n", __func__, (uint32_t)data); + ret = EINVAL; + } else { + nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data); + } - return (int64_t)nvg_get_result(); + return ret; } -int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) +/* + * The read-only value associated with the CSTATE_STAT_QUERY_REQUEST + * + * NVGDATA[0:63]: SW(R) Stat count + */ +uint64_t nvg_get_cstate_stat_query_value(void) { - uint64_t val; - - /* - * The only difference between a CSTATE_STATS_WRITE and - * CSTATE_STATS_READ is the usage of the 63:32 in the request. - * 63:32 are set to '0' for a read, while a write contains the - * actual stats value to be written. - */ - val = ((uint64_t)stats << MCE_CSTATE_STATS_TYPE_SHIFT) | state; - - /* - * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES - * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for - * reading the threshold can be generated by adding the type to - * the NVG_CLEAR_CSTATE_STATS command index. - */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + state, val); + nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE); - return 0; + return (uint64_t)nvg_get_result(); } -int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) +/* + * Return a non-zero value if the CCPLEX is able to enter SC7 + * + * NVGDATA[0]: SW(R), Is allowed result + */ +int32_t nvg_is_sc7_allowed(void) { - /* This does not apply to the Denver cluster */ - return 0; + /* issue command to check if SC7 is allowed */ + nvg_set_request(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED); + + /* 1 = SC7 allowed, 0 = SC7 not allowed */ + return (int32_t)nvg_get_result(); } -int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) +/* + * Wake an offlined logical core. Note that a core is offlined by entering + * a C-state where the WAKE_MASK is all 0. + * + * NVGDATA[0:3]: SW(W) logical core to online + */ +int32_t nvg_online_core(uint32_t core) { - uint64_t val; + int32_t ret = 0; - /* check for allowed power state */ - if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 && - state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) { - ERROR("%s: unknown cstate (%d)\n", __func__, state); - return EINVAL; + /* sanity check the core ID value */ + if (core > (uint32_t)PLATFORM_CORE_COUNT) { + ERROR("%s: unknown core id (%d)\n", __func__, core); + ret = EINVAL; + } else { + /* get a core online */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, + (uint64_t)core & MCE_CORE_ID_MASK); } + return ret; +} + +/* + * Enables and controls the voltage/frequency hint for CC3. CC3 is disabled + * by default. + * + * NVGDATA[7:0] SW(RW) frequency request + * NVGDATA[31:31] SW(RW) enable bit + */ +int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable) +{ + uint64_t val = 0; + /* - * Request format - - * 63:32 = wake time - * 31:0 = C-state for this core + * If the enable bit is cleared, Auto-CC3 will be disabled by setting + * the SW visible frequency request registers for all non + * floorswept cores valid independent of StandbyWFI and disabling + * the IDLE frequency request register. If set, Auto-CC3 + * will be enabled by setting the ARM SW visible frequency + * request registers for all non floorswept cores to be enabled by + * StandbyWFI or the equivalent signal, and always keeping the IDLE + * frequency request register enabled. */ - val = ((uint64_t)wake_time << MCE_SC7_WAKE_TIME_SHIFT) | - (state & MCE_SC7_ALLOWED_MASK); - - /* issue command to check if SC7 is allowed */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val); + if (enable != 0U) { + val = ((uint64_t)freq & MCE_AUTO_CC3_FREQ_MASK) | MCE_AUTO_CC3_ENABLE_BIT; + } + nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val); - /* 1 = SC7 allowed, 0 = SC7 not allowed */ - return !!nvg_get_result(); + return 0; } -int nvg_online_core(uint32_t ari_base, uint32_t core) +/* + * MC GSC (General Security Carveout) register values are expected to be + * changed by TrustZone ARM code after boot. + * + * NVGDATA[0:15] SW(R) GSC enun + */ +int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) { - int cpu = read_mpidr() & MPIDR_CPU_MASK; - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; - - /* sanity check code id */ - if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) { - ERROR("%s: unsupported core id (%d)\n", __func__, core); - return EINVAL; + int32_t ret = 0; + + /* sanity check GSC ID */ + if (gsc_idx > (uint32_t)TEGRA_NVG_GSC_VPR_IDX) { + ERROR("%s: unknown gsc_idx (%d)\n", __func__, gsc_idx); + ret = EINVAL; + } else { + nvg_set_request_data(TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, + (uint64_t)gsc_idx); } - /* - * The Denver cluster has 2 CPUs only - 0, 1. - */ - if (impl == DENVER_IMPL && ((core == 2) || (core == 3))) { - ERROR("%s: unknown core id (%d)\n", __func__, core); - return EINVAL; - } + return ret; +} - /* get a core online */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, core & MCE_CORE_ID_MASK); +/* + * Cache clean operation for all CCPLEX caches. + * + * NVGDATA[0] cache_clean + */ +int32_t nvg_roc_clean_cache(void) +{ + nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL, + (uint64_t)CACHE_CLEAN_SET); return 0; } -int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) +/* + * Cache clean and invalidate operation for all CCPLEX caches. + * + * NVGDATA[1] cache_clean_inval + */ +int32_t nvg_roc_flush_cache(void) { - int val; + nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL, + (uint64_t)CACHE_CLEAN_INVAL_SET); - /* - * If the enable bit is cleared, Auto-CC3 will be disabled by setting - * the SW visible voltage/frequency request registers for all non - * floorswept cores valid independent of StandbyWFI and disabling - * the IDLE voltage/frequency request register. If set, Auto-CC3 - * will be enabled by setting the ARM SW visible voltage/frequency - * request registers for all non floorswept cores to be enabled by - * StandbyWFI or the equivalent signal, and always keeping the IDLE - * voltage/frequency request register enabled. - */ - val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\ - ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\ - (enable ? MCE_AUTO_CC3_ENABLE_BIT : 0)); + return 0; +} - nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val); +/* + * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches. + * + * NVGDATA[2] cache_clean_inval_tr + */ +int32_t nvg_roc_clean_cache_trbits(void) +{ + nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL, + (uint64_t)CACHE_CLEAN_INVAL_TR_SET); return 0; } + +/* + * Set the power state for a core + */ +int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) +{ + int32_t ret = 0; + + /* check for allowed power state */ + if ((state != (uint32_t)TEGRA_NVG_CORE_C0) && + (state != (uint32_t)TEGRA_NVG_CORE_C1) && + (state != (uint32_t)TEGRA_NVG_CORE_C6) && + (state != (uint32_t)TEGRA_NVG_CORE_C7)) + { + ERROR("%s: unknown cstate (%d)\n", __func__, state); + ret = EINVAL; + } else { + /* time (TSC ticks) until the core is expected to get a wake event */ + nvg_set_wake_time(wake_time); + + /* set the core cstate */ + write_actlr_el1(state); + } + + return ret; +} diff --git a/plat/nvidia/tegra/soc/t194/plat_secondary.c b/plat/nvidia/tegra/soc/t194/plat_secondary.c index 33c8e1b64..f5e56b9b0 100644 --- a/plat/nvidia/tegra/soc/t194/plat_secondary.c +++ b/plat/nvidia/tegra/soc/t194/plat_secondary.c @@ -59,7 +59,4 @@ void plat_secondary_setup(void) addr_low); mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI, addr_high); - - /* update reset vector address to the CCPLEX */ - mce_update_reset_vector(); } diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 8a61759b3..b6bc44214 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -55,6 +55,8 @@ BL31_SOURCES += lib/cpus/aarch64/denver.S \ ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ ${COMMON_DIR}/drivers/smmu/smmu.c \ ${SOC_DIR}/drivers/mce/mce.c \ + ${SOC_DIR}/drivers/mce/nvg.c \ + ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ ${SOC_DIR}/plat_psci_handlers.c \ ${SOC_DIR}/plat_setup.c \ ${SOC_DIR}/plat_secondary.c \ -- cgit v1.2.3 From 7e4ffcd9256f1b1c11341002b8c2567aad317794 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 22 Feb 2017 11:57:15 -0800 Subject: Tegra194: Support SMC64 encoding for MCE calls This patch uses SMC64 encoding for all MCE SMC calls originating from the linux kernel. Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_sip_calls.c | 48 ++++++++++++++++------------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index 12b4b77da..cb57c9b61 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -21,27 +21,27 @@ extern uint32_t tegra186_system_powerdn_state; /******************************************************************************* * Tegra186 SiP SMCs ******************************************************************************/ -#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 -#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0x82FFFE01 -#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00 -#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01 -#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02 -#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0x82FFFF03 -#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0x82FFFF04 -#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0x82FFFF05 -#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0x82FFFF06 -#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0x82FFFF07 -#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0x82FFFF08 -#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0x82FFFF09 -#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0x82FFFF0A -#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0x82FFFF0B -#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0x82FFFF0C -#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0x82FFFF0D -#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0x82FFFF0E -#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F -#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0x82FFFF10 -#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0x82FFFF11 -#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0x82FFFF12 +#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01 +#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02 +#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00 +#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01 +#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02 +#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03 +#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04 +#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05 +#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06 +#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07 +#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08 +#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09 +#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A +#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B +#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C +#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D +#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E +#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F +#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10 +#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11 +#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12 /******************************************************************************* * This function is responsible for handling all T186 SiP calls @@ -57,6 +57,12 @@ int plat_sip_handler(uint32_t smc_fid, { int mce_ret; + /* + * Convert SMC FID to SMC64 until the linux driver uses + * SMC64 encoding. + */ + smc_fid |= (SMC_64 << FUNCID_CC_SHIFT); + switch (smc_fid) { /* -- cgit v1.2.3 From e9bb627d11dd3e7c8d65a0ee912a019a7ea4bbec Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Mon, 13 Feb 2017 17:22:57 +0530 Subject: Tegra194: remove GPU, MPCORE and PTC registers from streamid list GPU, MPCORE and PTC clients are changed and not going through SMMU. Removing it from streamid list. Change-Id: I14b450a11f02ad6c1a97e67e487d6d624911d019 Signed-off-by: Pritesh Raithatha --- .../soc/t194/drivers/include/memctrl_plat_config.h | 17 ----------------- .../tegra/soc/t194/drivers/include/smmu_plat_config.h | 14 -------------- 2 files changed, 31 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h b/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h index 8a4ed5b05..8eaae678a 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h @@ -297,15 +297,12 @@ * Array to hold stream_id override config register offsets ******************************************************************************/ const static uint32_t mc_streamid_override_regs[] = { - MC_STREAMID_OVERRIDE_CFG_PTCR, MC_STREAMID_OVERRIDE_CFG_HDAR, MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, MC_STREAMID_OVERRIDE_CFG_NVENCSRD, MC_STREAMID_OVERRIDE_CFG_SATAR, - MC_STREAMID_OVERRIDE_CFG_MPCORER, MC_STREAMID_OVERRIDE_CFG_NVENCSWR, MC_STREAMID_OVERRIDE_CFG_HDAW, - MC_STREAMID_OVERRIDE_CFG_MPCOREW, MC_STREAMID_OVERRIDE_CFG_SATAW, MC_STREAMID_OVERRIDE_CFG_ISPRA, MC_STREAMID_OVERRIDE_CFG_ISPFALR, @@ -317,8 +314,6 @@ const static uint32_t mc_streamid_override_regs[] = { MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, MC_STREAMID_OVERRIDE_CFG_TSECSRD, MC_STREAMID_OVERRIDE_CFG_TSECSWR, - MC_STREAMID_OVERRIDE_CFG_GPUSRD, - MC_STREAMID_OVERRIDE_CFG_GPUSWR, MC_STREAMID_OVERRIDE_CFG_SDMMCRA, MC_STREAMID_OVERRIDE_CFG_SDMMCR, MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, @@ -342,8 +337,6 @@ const static uint32_t mc_streamid_override_regs[] = { MC_STREAMID_OVERRIDE_CFG_ETRW, MC_STREAMID_OVERRIDE_CFG_TSECSRDB, MC_STREAMID_OVERRIDE_CFG_TSECSWRB, - MC_STREAMID_OVERRIDE_CFG_GPUSRD2, - MC_STREAMID_OVERRIDE_CFG_GPUSWR2, MC_STREAMID_OVERRIDE_CFG_AXISR, MC_STREAMID_OVERRIDE_CFG_AXISW, MC_STREAMID_OVERRIDE_CFG_EQOSR, @@ -433,15 +426,12 @@ const static uint32_t mc_streamid_override_regs[] = { * Array to hold the security configs for stream IDs ******************************************************************************/ const static mc_streamid_security_cfg_t mc_streamid_sec_cfgs[] = { - mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), @@ -453,8 +443,6 @@ const static mc_streamid_security_cfg_t mc_streamid_sec_cfgs[] = { mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE), - mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), @@ -478,8 +466,6 @@ const static mc_streamid_security_cfg_t mc_streamid_sec_cfgs[] = { mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE), - mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), @@ -571,13 +557,11 @@ const static mc_streamid_security_cfg_t mc_streamid_sec_cfgs[] = { const static mc_txn_override_cfg_t mc_txn_override_cfgs[] = { mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR), mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR), mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR), mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR), mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR), mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR), mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR), mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR), mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR), mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR), @@ -588,7 +572,6 @@ const static mc_txn_override_cfg_t mc_txn_override_cfgs[] = { mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR), mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR), mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR), - mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR), mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR), mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR), mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR), diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h b/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h index 72547110e..fc8669a0d 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h @@ -13,15 +13,12 @@ static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = { _START_OF_TABLE_, - mc_make_sid_security_cfg(PTCR), mc_make_sid_security_cfg(HDAR), mc_make_sid_security_cfg(HOST1XDMAR), mc_make_sid_security_cfg(NVENCSRD), mc_make_sid_security_cfg(SATAR), - mc_make_sid_security_cfg(MPCORER), mc_make_sid_security_cfg(NVENCSWR), mc_make_sid_security_cfg(HDAW), - mc_make_sid_security_cfg(MPCOREW), mc_make_sid_security_cfg(SATAW), mc_make_sid_security_cfg(ISPRA), mc_make_sid_security_cfg(ISPFALR), @@ -33,8 +30,6 @@ static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = { mc_make_sid_security_cfg(XUSB_DEVW), mc_make_sid_security_cfg(TSECSRD), mc_make_sid_security_cfg(TSECSWR), - mc_make_sid_security_cfg(GPUSRD), - mc_make_sid_security_cfg(GPUSWR), mc_make_sid_security_cfg(SDMMCRA), mc_make_sid_security_cfg(SDMMCR), mc_make_sid_security_cfg(SDMMCRAB), @@ -58,8 +53,6 @@ static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = { mc_make_sid_security_cfg(ETRW), mc_make_sid_security_cfg(TSECSRDB), mc_make_sid_security_cfg(TSECSWRB), - mc_make_sid_security_cfg(GPUSRD2), - mc_make_sid_security_cfg(GPUSWR2), mc_make_sid_security_cfg(AXISR), mc_make_sid_security_cfg(AXISW), mc_make_sid_security_cfg(EQOSR), @@ -143,15 +136,12 @@ static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = { mc_make_sid_security_cfg(MIU2W), mc_make_sid_security_cfg(MIU3R), mc_make_sid_security_cfg(MIU3W), - mc_make_sid_override_cfg(PTCR), mc_make_sid_override_cfg(HDAR), mc_make_sid_override_cfg(HOST1XDMAR), mc_make_sid_override_cfg(NVENCSRD), mc_make_sid_override_cfg(SATAR), - mc_make_sid_override_cfg(MPCORER), mc_make_sid_override_cfg(NVENCSWR), mc_make_sid_override_cfg(HDAW), - mc_make_sid_override_cfg(MPCOREW), mc_make_sid_override_cfg(SATAW), mc_make_sid_override_cfg(ISPRA), mc_make_sid_override_cfg(ISPFALR), @@ -163,8 +153,6 @@ static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = { mc_make_sid_override_cfg(XUSB_DEVW), mc_make_sid_override_cfg(TSECSRD), mc_make_sid_override_cfg(TSECSWR), - mc_make_sid_override_cfg(GPUSRD), - mc_make_sid_override_cfg(GPUSWR), mc_make_sid_override_cfg(SDMMCRA), mc_make_sid_override_cfg(SDMMCR), mc_make_sid_override_cfg(SDMMCRAB), @@ -188,8 +176,6 @@ static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = { mc_make_sid_override_cfg(ETRW), mc_make_sid_override_cfg(TSECSRDB), mc_make_sid_override_cfg(TSECSWRB), - mc_make_sid_override_cfg(GPUSRD2), - mc_make_sid_override_cfg(GPUSWR2), mc_make_sid_override_cfg(AXISR), mc_make_sid_override_cfg(AXISW), mc_make_sid_override_cfg(EQOSR), -- cgit v1.2.3 From 4fb71eae31a5a0c66c173facb2fdc145098b5d6e Mon Sep 17 00:00:00 2001 From: Rohit Khanna Date: Fri, 3 Mar 2017 11:33:32 -0800 Subject: Tegra194: Dont run MCE firmware on Emulation Dont run MCE firmware on pre-silicon emulation platforms Change-Id: I2a8d653e46f494621580ca92271a18e62f648859 Signed-off-by: Rohit Khanna --- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index 4754b77c5..f13643fc0 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -216,7 +216,8 @@ void mce_verify_firmware_version(void) * MCE firmware is not running on simulation platforms. */ if ((tegra_platform_is_linsim() == 1U) || - (tegra_platform_is_virt_dev_kit() == 1U)) { + (tegra_platform_is_virt_dev_kit() == 1U) || + (tegra_platform_is_qt() == 1U)) { return; } -- cgit v1.2.3 From ddbf946f7b5251bf9106dcbd1166801dffd290e7 Mon Sep 17 00:00:00 2001 From: Stefan Kristiansson Date: Mon, 20 Mar 2017 14:19:46 +0200 Subject: Tegra194: Fix TEGRA186_SMMU_CTX_SIZE TEGRA186_SMMU_CTX_SIZE should match the numbe of elements in smmu_ctx_regs, which is defined in smmu_plat_config.h. The current number of elements are 0x490. Change-Id: If0614ea8ef8b6a8f5da1a3279abaf9255eb76420 Signed-off-by: Stefan Kristiansson --- plat/nvidia/tegra/soc/t194/plat_trampoline.S | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S index cf765076a..e3ee5e5a5 100644 --- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S @@ -10,7 +10,7 @@ #include #include -#define TEGRA186_SMMU_CTX_SIZE 0x420 +#define TEGRA186_SMMU_CTX_SIZE 0x490 .align 4 .globl tegra186_cpu_reset_handler @@ -56,12 +56,12 @@ boot_cpu: endfunc tegra186_cpu_reset_handler /* - * Tegra186 reset data (offset 0x0 - 0x430) + * Tegra186 reset data (offset 0x0 - 0x2490) * - * 0x000: secure world's entrypoint - * 0x008: BL31 size (RO + RW) - * 0x00C: SMMU context start - * 0x42C: SMMU context end + * 0x0000: secure world's entrypoint + * 0x0008: BL31 size (RO + RW) + * 0x0010: SMMU context start + * 0x2490: SMMU context end */ .align 4 -- cgit v1.2.3 From d82f5a36f7bcff88a3eeab849ff13ee54df25932 Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Tue, 7 Mar 2017 13:13:27 +0800 Subject: Tegra194: add 'TEGRA_TMRUS_SIZE' macro This patch defines the macro for the TEGRA_TMRUS aperture size. Change-Id: I33fb674c6a7be8d02971667e7bf8650b7adc62ef Signed-off-by: Steven Kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 1 + 1 file changed, 1 insertion(+) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 7bdd975fc..6d198392a 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -190,6 +190,7 @@ * Tegra micro-seconds timer constants ******************************************************************************/ #define TEGRA_TMRUS_BASE 0x0C2E0000 +#define TEGRA_TMRUS_SIZE 0x10000 /******************************************************************************* * Tegra Power Mgmt Controller constants -- cgit v1.2.3 From 3b2b3375f10088aabfe4b519a49c7db294379579 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 13 Feb 2017 09:00:04 -0800 Subject: Tegra194: add macros for security carveout configuration registers This patch adds macros defining the generalised security carveout registers. These macros help us program the TZRAM carveout access and the Video Protect Clear carveout access. Change-Id: I8f7b24b653fdb702fb57a4097801cb3eae050294 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra_def.h | 46 ++++++++++++++---------------- 1 file changed, 22 insertions(+), 24 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 6d198392a..a1b70db9f 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -106,6 +106,16 @@ #define TEGRA_MC_STREAMID_BASE 0x02C00000 #define TEGRA_MC_BASE 0x02C10000 +/* General Security Carveout register macros */ +#define MC_GSC_CONFIG_REGS_SIZE 0x40 +#define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1) +#define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0) +#define MC_GSC_SIZE_RANGE_4KB_SHIFT 27 +#define MC_GSC_BASE_LO_SHIFT 12 +#define MC_GSC_BASE_LO_MASK 0xFFFFF +#define MC_GSC_BASE_HI_SHIFT 0 +#define MC_GSC_BASE_HI_MASK 3 + /* TZDRAM carveout configuration registers */ #define MC_SECURITY_CFG0_0 0x70 #define MC_SECURITY_CFG1_0 0x74 @@ -116,34 +126,22 @@ #define MC_VIDEO_PROTECT_BASE_LO 0x648 #define MC_VIDEO_PROTECT_SIZE_MB 0x64c +/* + * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the + * non-overlapping Video memory region + */ +#define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 +#define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 +#define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 +#define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC +#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 + /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ +#define MC_TZRAM_CARVEOUT_CFG 0x2190 #define MC_TZRAM_BASE_LO 0x2194 -#define TZRAM_BASE_LO_SHIFT 12 -#define TZRAM_BASE_LO_MASK 0xFFFFF #define MC_TZRAM_BASE_HI 0x2198 -#define TZRAM_BASE_HI_SHIFT 0 -#define TZRAM_BASE_HI_MASK 3 #define MC_TZRAM_SIZE 0x219C -#define TZRAM_SIZE_RANGE_4KB_SHIFT 27 - -#define MC_TZRAM_CARVEOUT_CFG 0x2190 -#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) -#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 -#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25) -#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7) -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 - -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21C0 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21C4 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C8 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21CC -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21D0 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21D4 +#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 /* Memory Controller Reset Control registers */ #define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27) -- cgit v1.2.3 From ec477e7da9dee6eadddec3686f5c19c3f673c125 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Mon, 28 Oct 2019 14:02:51 +0100 Subject: doc: Fix syntax erros in I/O storage layer plantuml diagrams Some of the plantuml diagrams in the I/O storage abstraction layer documentation are absent from the rendered version of the porting guide. The build log (see [1] for example) reports a syntax error in these files. This is due to the usage of the 'order' keyword on the participants list, which does not seem to be supported by the version of plantuml installed on the ReadTheDocs server. Fix these syntax errors by removing the 'order' keyword altogether. We simply rely on the participants being declared in the desired order, which will be the order of display, according to the plantuml documentation. [1] https://readthedocs.org/api/v2/build/9870345.txt Change-Id: Ife35c74cb2f1dac28bda07df395244639a8d6a2b Signed-off-by: Sandrine Bailleux --- docs/resources/diagrams/plantuml/io_dev_init_and_check.puml | 4 ++-- docs/resources/diagrams/plantuml/io_dev_registration.puml | 8 ++++---- docs/resources/diagrams/plantuml/io_framework_usage_overview.puml | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/docs/resources/diagrams/plantuml/io_dev_init_and_check.puml b/docs/resources/diagrams/plantuml/io_dev_init_and_check.puml index 2752b3326..b7289a246 100644 --- a/docs/resources/diagrams/plantuml/io_dev_init_and_check.puml +++ b/docs/resources/diagrams/plantuml/io_dev_init_and_check.puml @@ -1,7 +1,7 @@ @startuml -participant arm_io_storage order 1 -participant io_storage order 2 +participant arm_io_storage +participant io_storage -> arm_io_storage : plat_get_image_source(image_id, &dev_handle, &image_spec) diff --git a/docs/resources/diagrams/plantuml/io_dev_registration.puml b/docs/resources/diagrams/plantuml/io_dev_registration.puml index 114c3b778..c6f330e6a 100644 --- a/docs/resources/diagrams/plantuml/io_dev_registration.puml +++ b/docs/resources/diagrams/plantuml/io_dev_registration.puml @@ -1,9 +1,9 @@ @startuml -participant arm_io_storage order 1 -participant io_storage order 2 -participant io_fip order 3 -participant io_memmap order 4 +participant arm_io_storage +participant io_storage +participant io_fip +participant io_memmap -> arm_io_storage : arm_io_setup() diff --git a/docs/resources/diagrams/plantuml/io_framework_usage_overview.puml b/docs/resources/diagrams/plantuml/io_framework_usage_overview.puml index eb3e2b4c7..b21a0ae5d 100644 --- a/docs/resources/diagrams/plantuml/io_framework_usage_overview.puml +++ b/docs/resources/diagrams/plantuml/io_framework_usage_overview.puml @@ -1,8 +1,8 @@ @startuml -participant bl_common order 1 -participant arm_io_storage order 2 -participant io_storage order 3 +participant bl_common +participant arm_io_storage +participant io_storage == Platform Setup == -- cgit v1.2.3 From ff835a9a9dca698d7c003979aa668e8bfae6f6e7 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 4 Jan 2019 16:04:01 -0600 Subject: ti: k3: common: Add PIE support Running TF-A from non-standard location such as DRAM is useful for some SRAM heavy use-cases. Allow the TF-A binary to be executed from an arbitrary memory location. Signed-off-by: Andrew F. Davis Change-Id: Icd97926e4d97f37d7cde4a92758a52f57d569111 --- plat/ti/k3/common/plat_common.mk | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk index 20a94ef9e..7956497ae 100644 --- a/plat/ti/k3/common/plat_common.mk +++ b/plat/ti/k3/common/plat_common.mk @@ -31,6 +31,9 @@ HANDLE_EA_EL3_FIRST := 1 # Split out RO data into a non-executable section SEPARATE_CODE_AND_RODATA := 1 +# Generate a Position Independent Executable +ENABLE_PIE := 1 + TI_16550_MDR_QUIRK := 1 $(eval $(call add_define,TI_16550_MDR_QUIRK)) -- cgit v1.2.3 From 34c7af41df3a19889edb2592a4a9d42663839d8f Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Mon, 7 Oct 2019 17:47:46 +0100 Subject: n1sdp: introduce platform information SDS region Platform information structure holds information about platform's DDR size(local/remote) which will be used to zero out the memory before enabling the ECC capability as well as information about multichip setup. Multichip and remote DDR information can only be probed in SCP, SDS region will be used by TF-A to get this information at boot up. This patch introduces a new SDS to store platform information, which is populated dynamically by SCP Firmware.previously used mem_info SDS is also made part of this structure itself. The platform information is also passed to BL33 by copying it to Non- Secure SRAM. Change-Id: I4781dc6a7232c3c0a3219b164d943ce9e3e469ee Signed-off-by: Manish Pandey --- plat/arm/board/n1sdp/n1sdp_bl31_setup.c | 63 +++++++++++++++++++++------------ plat/arm/board/n1sdp/n1sdp_def.h | 14 ++++---- 2 files changed, 48 insertions(+), 29 deletions(-) diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c index 632af7b40..5445f246a 100644 --- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c +++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,14 +17,22 @@ #include "n1sdp_def.h" /* - * Memory information structure stored in SDS. - * This structure holds the total DDR memory size which will be - * used when zeroing out the entire DDR memory before enabling - * the ECC capability in DMCs. + * Platform information structure stored in SDS. + * This structure holds information about platform's DDR + * size which will be used to zero out the memory before + * enabling the ECC capability as well as information + * about multichip setup + * - multichip mode + * - slave_count + * - Local DDR size in GB, DDR memory in master board + * - Remote DDR size in GB, DDR memory in slave board */ -struct n1sdp_mem_info { - uint32_t ddr_size_gb; -}; +struct n1sdp_plat_info { + bool multichip_mode; + uint8_t slave_count; + uint8_t local_ddr_size; + uint8_t remote_ddr_size; +} __packed; /* * BL33 image information structure stored in SDS. @@ -38,11 +46,11 @@ struct n1sdp_bl33_info { }; static scmi_channel_plat_info_t n1sdp_scmi_plat_info = { - .scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE, - .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, - .db_preserve_mask = 0xfffffffe, - .db_modify_mask = 0x1, - .ring_doorbell = &mhu_ring_doorbell, + .scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE, + .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, + .db_preserve_mask = 0xfffffffe, + .db_modify_mask = 0x1, + .ring_doorbell = &mhu_ring_doorbell }; scmi_channel_plat_info_t *plat_css_get_scmi_info() @@ -112,7 +120,7 @@ void copy_bl33(uint32_t src, uint32_t dst, uint32_t size) void bl31_platform_setup(void) { int ret; - struct n1sdp_mem_info mem_info; + struct n1sdp_plat_info plat_info; struct n1sdp_bl33_info bl33_info; arm_bl31_platform_setup(); @@ -123,16 +131,25 @@ void bl31_platform_setup(void) panic(); } - ret = sds_struct_read(N1SDP_SDS_MEM_INFO_STRUCT_ID, - N1SDP_SDS_MEM_INFO_OFFSET, - &mem_info, - N1SDP_SDS_MEM_INFO_SIZE, + ret = sds_struct_read(N1SDP_SDS_PLATFORM_INFO_STRUCT_ID, + N1SDP_SDS_PLATFORM_INFO_OFFSET, + &plat_info, + N1SDP_SDS_PLATFORM_INFO_SIZE, SDS_ACCESS_MODE_NON_CACHED); if (ret != SDS_OK) { - ERROR("Error getting memory info from SDS\n"); + ERROR("Error getting platform info from SDS\n"); + panic(); + } + /* Validate plat_info SDS */ + if ((plat_info.local_ddr_size == 0) + || (plat_info.local_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) + || (plat_info.remote_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) + || (plat_info.slave_count > N1SDP_MAX_SLAVE_COUNT)) { + ERROR("platform info SDS is corrupted\n"); panic(); } - dmc_ecc_setup(mem_info.ddr_size_gb); + + dmc_ecc_setup(plat_info.local_ddr_size); ret = sds_struct_read(N1SDP_SDS_BL33_INFO_STRUCT_ID, N1SDP_SDS_BL33_INFO_OFFSET, @@ -147,11 +164,11 @@ void bl31_platform_setup(void) bl33_info.bl33_dst_addr, bl33_info.bl33_size); /* - * Pass DDR memory size info to BL33. This method is followed as + * Pass platform information to BL33. This method is followed as * currently there is no BL1/BL2 involved in boot flow of N1SDP. * When TBBR is implemented for N1SDP, this method should be removed - * and DDR memory size shoule be passed to BL33 using NT_FW_CONFIG + * and platform information should be passed to BL33 using NT_FW_CONFIG * passing mechanism. */ - mmio_write_32(N1SDP_DDR_MEM_INFO_BASE, mem_info.ddr_size_gb); + mmio_write_32(N1SDP_PLATFORM_INFO_BASE, *(uint32_t *)&plat_info); } diff --git a/plat/arm/board/n1sdp/n1sdp_def.h b/plat/arm/board/n1sdp/n1sdp_def.h index d43c5a47b..574cdc9e3 100644 --- a/plat/arm/board/n1sdp/n1sdp_def.h +++ b/plat/arm/board/n1sdp/n1sdp_def.h @@ -15,10 +15,12 @@ N1SDP_NS_SRAM_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -/* SDS memory information defines */ -#define N1SDP_SDS_MEM_INFO_STRUCT_ID 8 -#define N1SDP_SDS_MEM_INFO_OFFSET 0 -#define N1SDP_SDS_MEM_INFO_SIZE 4 +/* SDS Platform information defines */ +#define N1SDP_SDS_PLATFORM_INFO_STRUCT_ID 8 +#define N1SDP_SDS_PLATFORM_INFO_OFFSET 0 +#define N1SDP_SDS_PLATFORM_INFO_SIZE 4 +#define N1SDP_MAX_DDR_CAPACITY_GB 64 +#define N1SDP_MAX_SLAVE_COUNT 16 /* SDS BL33 image information defines */ #define N1SDP_SDS_BL33_INFO_STRUCT_ID 9 @@ -40,7 +42,7 @@ /* DMC ECC enable bit in ERR0CTLR0 register */ #define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1 -/* Base address of non-secure SRAM where DDR memory size will be filled */ -#define N1SDP_DDR_MEM_INFO_BASE 0x06008000 +/* Base address of non-secure SRAM where Platform information will be filled */ +#define N1SDP_PLATFORM_INFO_BASE 0x06008000 #endif /* N1SDP_DEF_H */ -- cgit v1.2.3 From f91a8e4c2c5e9312b257fd241f2114b9532edd15 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Wed, 11 Sep 2019 17:07:40 +0100 Subject: n1sdp: update platform macros for dual-chip setup N1SDP supports multichip configuration wherein n1sdp boards are connected over high speed coherent CCIX link for now only dual-chip is supported. A single instance of TF-A runs on master chip which should be aware of slave chip's CPU and memory topology. This patch updates platform macros to include remote chip's information and also ensures that a single version of firmware works for both single and dual-chip setup. Change-Id: I75799fd46dc10527aa99585226099d836c21da70 Signed-off-by: Manish Pandey --- plat/arm/board/n1sdp/aarch64/n1sdp_helper.S | 26 +++++---- plat/arm/board/n1sdp/include/platform_def.h | 84 ++++++++++++++++++++--------- plat/arm/board/n1sdp/n1sdp_bl31_setup.c | 38 ++++++++++++- plat/arm/board/n1sdp/n1sdp_def.h | 12 +++++ plat/arm/board/n1sdp/n1sdp_plat.c | 5 +- plat/arm/board/n1sdp/n1sdp_topology.c | 8 ++- 6 files changed, 132 insertions(+), 41 deletions(-) diff --git a/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S b/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S index c03185aea..3da55b66f 100644 --- a/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S +++ b/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S @@ -17,19 +17,20 @@ * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) * * Helper function to calculate the core position. - * (ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) + - * (CPUId * N1SDP_MAX_PE_PER_CPU) + - * ThreadId + * ((ChipId * N1SDP_MAX_CLUSTERS_PER_CHIP + ClusterId) * + * N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) + + * (CPUId * N1SDP_MAX_PE_PER_CPU) + ThreadId * * which can be simplified as: * - * ((ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) * - * N1SDP_MAX_PE_PER_CPU) + ThreadId + * (((ChipId * N1SDP_MAX_CLUSTERS_PER_CHIP + ClusterId) * + * N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) * N1SDP_MAX_PE_PER_CPU) + + * ThreadId * ------------------------------------------------------ */ func plat_arm_calc_core_pos - mov x3, x0 + mov x4, x0 /* * The MT bit in MPIDR is always set for n1sdp and the @@ -37,15 +38,18 @@ func plat_arm_calc_core_pos */ /* Extract individual affinity fields from MPIDR */ - ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS - ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS - ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS + ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS + ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS + ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS + ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS /* Compute linear position */ + mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP + madd x2, x3, x4, x2 mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER madd x1, x2, x4, x1 - mov x5, #N1SDP_MAX_PE_PER_CPU - madd x0, x1, x5, x0 + mov x4, #N1SDP_MAX_PE_PER_CPU + madd x0, x1, x4, x0 ret endfunc plat_arm_calc_core_pos diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h index 7348bf5e4..6a309e8e1 100644 --- a/plat/arm/board/n1sdp/include/platform_def.h +++ b/plat/arm/board/n1sdp/include/platform_def.h @@ -27,16 +27,27 @@ #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) +/* N1SDP remote chip at 4 TB offset */ +#define PLAT_ARM_REMOTE_CHIP_OFFSET (ULL(1) << 42) + +#define N1SDP_REMOTE_DRAM1_BASE ARM_DRAM1_BASE + \ + PLAT_ARM_REMOTE_CHIP_OFFSET +#define N1SDP_REMOTE_DRAM1_SIZE ARM_DRAM1_SIZE + +#define N1SDP_REMOTE_DRAM2_BASE PLAT_ARM_DRAM2_BASE + \ + PLAT_ARM_REMOTE_CHIP_OFFSET +#define N1SDP_REMOTE_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE + /* * N1SDP platform supports RDIMMs with ECC capability. To use the ECC * capability, the entire DDR memory space has to be zeroed out before - * enabling the ECC bits in DMC620. The access the complete DDR memory - * space the physical & virtual address space limits are extended to - * 40-bits. + * enabling the ECC bits in DMC620. To access the complete DDR memory + * along with remote chip's DDR memory, which is at 4 TB offset, physical + * and virtual address space limits are extended to 43-bits. */ #ifdef __aarch64__ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) #else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) @@ -51,34 +62,36 @@ #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ #define PLAT_ARM_MAX_BL31_SIZE 0X20000 - /******************************************************************************* * N1SDP topology related constants ******************************************************************************/ -#define N1SDP_MAX_CPUS_PER_CLUSTER 2 -#define PLAT_ARM_CLUSTER_COUNT 2 -#define N1SDP_MAX_PE_PER_CPU 1 - -#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ +#define N1SDP_MAX_CPUS_PER_CLUSTER U(2) +#define PLAT_ARM_CLUSTER_COUNT U(2) +#define PLAT_N1SDP_CHIP_COUNT U(2) +#define N1SDP_MAX_CLUSTERS_PER_CHIP U(2) +#define N1SDP_MAX_PE_PER_CPU U(1) + +#define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \ + PLAT_ARM_CLUSTER_COUNT * \ N1SDP_MAX_CPUS_PER_CLUSTER * \ N1SDP_MAX_PE_PER_CPU) /* System power domain level */ -#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 +#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 /* * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the * plat_arm_mmap array defined for each BL stage. */ -#define PLAT_ARM_MMAP_ENTRIES 6 -#define MAX_XLAT_TABLES 7 +#define PLAT_ARM_MMAP_ENTRIES 9 +#define MAX_XLAT_TABLES 10 #define PLATFORM_STACK_SIZE 0x400 #define PLAT_ARM_NSTIMER_FRAME_ID 0 #define PLAT_CSS_MHU_BASE 0x45000000 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE -#define PLAT_MAX_PWR_LVL 1 +#define PLAT_MAX_PWR_LVL 2 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ CSS_IRQ_MHU @@ -88,17 +101,36 @@ #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) -#define N1SDP_DEVICE_BASE (0x08000000) -#define N1SDP_DEVICE_SIZE (0x48000000) -#define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ - N1SDP_DEVICE_BASE, \ - N1SDP_DEVICE_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ - ARM_DRAM1_BASE, \ - ARM_DRAM1_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) +#define N1SDP_DEVICE_BASE ULL(0x08000000) +#define N1SDP_DEVICE_SIZE ULL(0x48000000) +#define N1SDP_REMOTE_DEVICE_BASE N1SDP_DEVICE_BASE + \ + PLAT_ARM_REMOTE_CHIP_OFFSET +#define N1SDP_REMOTE_DEVICE_SIZE N1SDP_DEVICE_SIZE + +#define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ + N1SDP_DEVICE_BASE, \ + N1SDP_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ + ARM_DRAM1_BASE, \ + ARM_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define N1SDP_MAP_REMOTE_DEVICE MAP_REGION_FLAT( \ + N1SDP_REMOTE_DEVICE_BASE, \ + N1SDP_REMOTE_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define N1SDP_MAP_REMOTE_DRAM1 MAP_REGION_FLAT( \ + N1SDP_REMOTE_DRAM1_BASE, \ + N1SDP_REMOTE_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define N1SDP_MAP_REMOTE_DRAM2 MAP_REGION_FLAT( \ + N1SDP_REMOTE_DRAM2_BASE, \ + N1SDP_REMOTE_DRAM2_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) /* GIC related constants */ #define PLAT_ARM_GICD_BASE 0x30000000 diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c index 5445f246a..79a0a7997 100644 --- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c +++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c @@ -74,7 +74,7 @@ const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) * from IOFPGA-DDR3 memory to main DDR4 memory. */ -void dmc_ecc_setup(uint32_t ddr_size_gb) +void dmc_ecc_setup(uint8_t ddr_size_gb) { uint64_t dram2_size; @@ -101,6 +101,38 @@ void dmc_ecc_setup(uint32_t ddr_size_gb) mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); } +void remote_dmc_ecc_setup(uint8_t remote_ddr_size) +{ + uint64_t remote_dram2_size; + + remote_dram2_size = (remote_ddr_size * 1024UL * 1024UL * 1024UL) - + N1SDP_REMOTE_DRAM1_SIZE; + /* multichip setup */ + INFO("Zeroing remote DDR memories\n"); + zero_normalmem((void *)N1SDP_REMOTE_DRAM1_BASE, + N1SDP_REMOTE_DRAM1_SIZE); + flush_dcache_range(N1SDP_REMOTE_DRAM1_BASE, N1SDP_REMOTE_DRAM1_SIZE); + zero_normalmem((void *)N1SDP_REMOTE_DRAM2_BASE, remote_dram2_size); + flush_dcache_range(N1SDP_REMOTE_DRAM2_BASE, remote_dram2_size); + + INFO("Enabling ECC on remote DMCs\n"); + /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */ + mmio_write_32(N1SDP_REMOTE_DMC0_MEMC_CMD_REG, + N1SDP_DMC_MEMC_CMD_CONFIG); + mmio_write_32(N1SDP_REMOTE_DMC1_MEMC_CMD_REG, + N1SDP_DMC_MEMC_CMD_CONFIG); + + /* Enable ECC in DMCs */ + mmio_setbits_32(N1SDP_REMOTE_DMC0_ERR0CTLR0_REG, + N1SDP_DMC_ERR0CTLR0_ECC_EN); + mmio_setbits_32(N1SDP_REMOTE_DMC1_ERR0CTLR0_REG, + N1SDP_DMC_ERR0CTLR0_ECC_EN); + + /* Set DMCs to READY state */ + mmio_write_32(N1SDP_REMOTE_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); + mmio_write_32(N1SDP_REMOTE_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); +} + void copy_bl33(uint32_t src, uint32_t dst, uint32_t size) { uint32_t i; @@ -151,6 +183,10 @@ void bl31_platform_setup(void) dmc_ecc_setup(plat_info.local_ddr_size); + /* Check if remote memory is present */ + if ((plat_info.multichip_mode) && (plat_info.remote_ddr_size != 0)) + remote_dmc_ecc_setup(plat_info.remote_ddr_size); + ret = sds_struct_read(N1SDP_SDS_BL33_INFO_STRUCT_ID, N1SDP_SDS_BL33_INFO_OFFSET, &bl33_info, diff --git a/plat/arm/board/n1sdp/n1sdp_def.h b/plat/arm/board/n1sdp/n1sdp_def.h index 574cdc9e3..30e29a758 100644 --- a/plat/arm/board/n1sdp/n1sdp_def.h +++ b/plat/arm/board/n1sdp/n1sdp_def.h @@ -35,6 +35,18 @@ #define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708 #define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708 +/* Remote DMC memory command registers */ +#define N1SDP_REMOTE_DMC0_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ + N1SDP_DMC0_MEMC_CMD_REG +#define N1SDP_REMOTE_DMC1_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ + N1SDP_DMC1_MEMC_CMD_REG + +/* Remote DMC ERR0CTLR0 registers */ +#define N1SDP_REMOTE_DMC0_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ + N1SDP_DMC0_ERR0CTLR0_REG +#define N1SDP_REMOTE_DMC1_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ + N1SDP_DMC1_ERR0CTLR0_REG + /* DMC memory commands */ #define N1SDP_DMC_MEMC_CMD_CONFIG 0 #define N1SDP_DMC_MEMC_CMD_READY 3 diff --git a/plat/arm/board/n1sdp/n1sdp_plat.c b/plat/arm/board/n1sdp/n1sdp_plat.c index a32ca7251..951a562f2 100644 --- a/plat/arm/board/n1sdp/n1sdp_plat.c +++ b/plat/arm/board/n1sdp/n1sdp_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,6 +25,9 @@ const mmap_region_t plat_arm_mmap[] = { N1SDP_MAP_NS_SRAM, ARM_MAP_DRAM1, ARM_MAP_DRAM2, + N1SDP_MAP_REMOTE_DEVICE, + N1SDP_MAP_REMOTE_DRAM1, + N1SDP_MAP_REMOTE_DRAM2, {0} }; diff --git a/plat/arm/board/n1sdp/n1sdp_topology.c b/plat/arm/board/n1sdp/n1sdp_topology.c index edf117099..5c2db71b7 100644 --- a/plat/arm/board/n1sdp/n1sdp_topology.c +++ b/plat/arm/board/n1sdp/n1sdp_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,7 +19,11 @@ typedef struct n1sdp_topology { * indices returned by plat_core_pos_by_mpidr(). */ const unsigned char n1sdp_pd_tree_desc[] = { + PLAT_N1SDP_CHIP_COUNT, PLAT_ARM_CLUSTER_COUNT, + PLAT_ARM_CLUSTER_COUNT, + N1SDP_MAX_CPUS_PER_CLUSTER, + N1SDP_MAX_CPUS_PER_CLUSTER, N1SDP_MAX_CPUS_PER_CLUSTER, N1SDP_MAX_CPUS_PER_CLUSTER }; @@ -52,4 +56,4 @@ unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) * to the SCMI power domain ID implemented by SCP. ******************************************************************************/ const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = { - 0, 1, 2, 3}; + 0, 1, 2, 3, 4, 5, 6, 7}; -- cgit v1.2.3 From 620dd58b811efdb22e40d3ec4ddba0883a676b70 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Thu, 31 Oct 2019 14:09:52 -0600 Subject: SMMUv3:Changed retry loop to delay timer(GENFW-3329) Instead of retry polling, timer of 1ms is used to poll Signed-off-by: Deepika Bhavnani Change-Id: I7e028dc68138d2888e3cf0cbed744f5e6bc6ff42 --- drivers/arm/smmu/smmu_v3.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/arm/smmu/smmu_v3.c b/drivers/arm/smmu/smmu_v3.c index 5493b850a..a082a8107 100644 --- a/drivers/arm/smmu/smmu_v3.c +++ b/drivers/arm/smmu/smmu_v3.c @@ -7,23 +7,27 @@ #include #include #include +#include #include /* SMMU poll number of retries */ -#define SMMU_POLL_RETRY 1000000 +#define SMMU_POLL_TIMEOUT_US U(1000) static int __init smmuv3_poll(uintptr_t smmu_reg, uint32_t mask, uint32_t value) { - uint32_t reg_val, retries = SMMU_POLL_RETRY; + uint32_t reg_val; + uint64_t timeout; + /* Set 1ms timeout value */ + timeout = timeout_init_us(SMMU_POLL_TIMEOUT_US); do { reg_val = mmio_read_32(smmu_reg); if ((reg_val & mask) == value) return 0; - } while (--retries != 0U); + } while (!timeout_elapsed(timeout)); - ERROR("Failed to poll SMMUv3 register @%p\n", (void *)smmu_reg); + ERROR("Timeout polling SMMUv3 register @%p\n", (void *)smmu_reg); ERROR("Read value 0x%x, expected 0x%x\n", reg_val, value == 0U ? reg_val & ~mask : reg_val | mask); return -1; -- cgit v1.2.3 From c605ecd1a13f1ffb3a64369ec61169058f08122c Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Wed, 30 Oct 2019 10:24:55 +0000 Subject: TF-A Documentation: Update Security Advisory TFV-5 (CVE-2017-15031) This patch updates description of Security Advisory TFV-5. Change-Id: Ieaee0b51a79843345b1aca5d0e20c4964beb3c95 Signed-off-by: Alexei Fedorov --- .../security_advisories/security-advisory-tfv-5.rst | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/docs/security_advisories/security-advisory-tfv-5.rst b/docs/security_advisories/security-advisory-tfv-5.rst index 2214f2d50..97f7cd98c 100644 --- a/docs/security_advisories/security-advisory-tfv-5.rst +++ b/docs/security_advisories/security-advisory-tfv-5.rst @@ -7,9 +7,9 @@ Advisory TFV-5 (CVE-2017-15031) +================+=============================================================+ | CVE ID | `CVE-2017-15031`_ | +----------------+-------------------------------------------------------------+ -| Date | 02 Oct 2017 | +| Date | 02 Oct 2017, updated on 04 Nov 2019 | +----------------+-------------------------------------------------------------+ -| Versions | All, up to and including v1.4 | +| Versions | All, up to and including v2.1 | | Affected | | +----------------+-------------------------------------------------------------+ | Configurations | All | @@ -18,8 +18,12 @@ Advisory TFV-5 (CVE-2017-15031) | Impact | Leakage of sensitive secure world timing information | +----------------+-------------------------------------------------------------+ | Fix Version | `Pull Request #1127`_ (merged on 18 October 2017) | +| | | +| | `Commit e290a8fcbc`_ (merged on 23 August 2019) | +| | | +| | `Commit c3e8b0be9b`_ (merged on 27 September 2019) | +----------------+-------------------------------------------------------------+ -| Credit | Arm | +| Credit | Arm, Marek Bykowski | +----------------+-------------------------------------------------------------+ The ``PMCR_EL0`` (Performance Monitors Control Register) provides details of the @@ -28,10 +32,11 @@ implemented, and configures and controls the counters. If the ``PMCR_EL0.DP`` bit is set to zero, the cycle counter (when enabled) counts during secure world execution, even when prohibited by the debug signals. -Since Arm TF does not save and restore ``PMCR_EL0`` when switching between the +Since TF-A does not save and restore ``PMCR_EL0`` when switching between the normal and secure worlds, normal world code can set ``PMCR_EL0.DP`` to zero to cause leakage of secure world timing information. This register should be added -to the list of saved/restored registers. +to the list of saved/restored registers both when entering EL3 and also +transitioning to S-EL1. Furthermore, ``PMCR_EL0.DP`` has an architecturally ``UNKNOWN`` reset value. Since Arm TF does not initialize this register, it's possible that on at least @@ -42,5 +47,11 @@ sensible default values in the secure context. The same issue exists for the equivalent AArch32 register, ``PMCR``, except that here ``PMCR_EL0.DP`` architecturally resets to zero. +NOTE: The original pull request referenced above only fixed the issue for S-EL1 +whereas the EL3 was fixed in the later commits. + .. _CVE-2017-15031: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-15031 .. _Pull Request #1127: https://github.com/ARM-software/arm-trusted-firmware/pull/1127 +.. _Commit e290a8fcbc: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=e290a8fcbc +.. _Commit c3e8b0be9b: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=c3e8b0be9b + -- cgit v1.2.3 From 74c21244005f639812b0cc68f71e501f831d8f70 Mon Sep 17 00:00:00 2001 From: Vijayenthiran Subramaniam Date: Fri, 11 Oct 2019 14:01:25 +0530 Subject: plat/arm/gicv3: add support for probing multiple GIC Redistributor frames ARM platform can have a non-contiguous GICR frames. For instance, a multi socket platform can have two or more GIC Redistributor frames which are 4TB apart. Hence it is necessary for the `gicv3_rdistif_probe` function to probe all the GICR frames available in the platform. Introduce `plat_arm_override_gicr_frames` function which platforms can use to override the default gicr_frames which holds the GICR base address of the primary cpu. Change-Id: I1f537b0d871a679cb256092944737f2e55ab866e Signed-off-by: Vijayenthiran Subramaniam --- include/plat/arm/common/plat_arm.h | 5 +++++ plat/arm/common/arm_gicv3.c | 38 ++++++++++++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 4 deletions(-) diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 07a46c518..c00a04126 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -254,6 +254,11 @@ void plat_arm_program_trusted_mailbox(uintptr_t address); int plat_arm_bl1_fwu_needed(void); __dead2 void plat_arm_error_handler(int err); +/* + * Optional function in ARM standard platforms + */ +void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); + #if ARM_PLAT_MT unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); #endif diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index fef53761c..cfc535939 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -28,6 +28,15 @@ /* The GICv3 driver only needs to be initialized in EL3 */ static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; +/* Default GICR base address to be used for GICR probe. */ +static const uintptr_t gicr_base_addrs[2] = { + PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */ + 0U /* Zero Termination */ +}; + +/* List of zero terminated GICR frame addresses which CPUs will probe */ +static const uintptr_t *gicr_frames = gicr_base_addrs; + static const interrupt_prop_t arm_interrupt_props[] = { PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0) @@ -76,6 +85,18 @@ static const gicv3_driver_data_t arm_gic_data __unused = { .mpidr_to_core_pos = arm_gicv3_mpidr_hash }; +/* + * By default, gicr_frames will be pointing to gicr_base_addrs. If + * the platform supports a non-contiguous GICR frames (GICR frames located + * at uneven offset), plat_arm_override_gicr_frames function can be used by + * such platform to override the gicr_frames. + */ +void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames) +{ + assert(plat_gicr_frames != NULL); + gicr_frames = plat_gicr_frames; +} + void __init plat_arm_gic_driver_init(void) { /* @@ -88,7 +109,7 @@ void __init plat_arm_gic_driver_init(void) (defined(__aarch64__) && defined(IMAGE_BL31)) gicv3_driver_init(&arm_gic_data); - if (gicv3_rdistif_probe(PLAT_ARM_GICR_BASE) == -1) { + if (gicv3_rdistif_probe(gicr_base_addrs[0]) == -1) { ERROR("No GICR base frame found for Primary CPU\n"); panic(); } @@ -124,14 +145,23 @@ void plat_arm_gic_cpuif_disable(void) /****************************************************************************** * ARM common helper function to iterate over all GICR frames and discover the * corresponding per-cpu redistributor frame as well as initialize the - * corresponding interface in GICv3. At the moment, Arm platforms do not have - * non-contiguous GICR frames. + * corresponding interface in GICv3. *****************************************************************************/ void plat_arm_gic_pcpu_init(void) { int result; + const uintptr_t *plat_gicr_frames = gicr_frames; + + do { + result = gicv3_rdistif_probe(*plat_gicr_frames); + + /* If the probe is successful, no need to proceed further */ + if (result == 0) + break; + + plat_gicr_frames++; + } while (*plat_gicr_frames != 0U); - result = gicv3_rdistif_probe(PLAT_ARM_GICR_BASE); if (result == -1) { ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); panic(); -- cgit v1.2.3 From abb6fee665a303c21f40a26f1466e5273464e290 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Thu, 18 Jul 2019 13:34:09 +0800 Subject: plat: imx8mm: Add the support for opteed spd on imx8mq/imx8mm Add the basic support for opteed SPD on imx8mq & imx8mm. Signed-off-by: Jacky Bai Change-Id: I6c4855c89dea78d13d172c3d86cf047f829e51ce --- plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c | 12 ++++++++++++ plat/imx/imx8m/imx8mm/include/platform_def.h | 1 - plat/imx/imx8m/imx8mm/platform.mk | 6 ++++++ plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c | 12 ++++++++++++ plat/imx/imx8m/imx8mq/include/platform_def.h | 1 - plat/imx/imx8m/imx8mq/platform.mk | 6 ++++++ 6 files changed, 36 insertions(+), 2 deletions(-) diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c index c3cd0d0cb..4c5f4f0d1 100644 --- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c @@ -124,6 +124,18 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); +#ifdef SPD_opteed + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = 0; + + /* Pass TEE base and size to bl33 */ + bl33_image_ep_info.args.arg1 = BL32_BASE; + bl33_image_ep_info.args.arg2 = BL32_SIZE; +#endif + bl31_tzc380_setup(); } diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index de9e3b5c8..fc35dac14 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -31,7 +31,6 @@ #define BL31_BASE U(0x920000) #define BL31_LIMIT U(0x940000) -#define BL32_BASE U(0xbe000000) /* non-secure uboot base */ #define PLAT_NS_IMAGE_OFFSET U(0x40200000) diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk index 6d32dbba3..c0cb6c2a5 100644 --- a/plat/imx/imx8m/imx8mm/platform.mk +++ b/plat/imx/imx8m/imx8mm/platform.mk @@ -45,3 +45,9 @@ A53_DISABLE_NON_TEMPORAL_HINT := 0 ERRATA_A53_835769 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 + +BL32_BASE ?= 0xbe000000 +$(eval $(call add_define,BL32_BASE)) + +BL32_SIZE ?= 0x2000000 +$(eval $(call add_define,BL32_SIZE)) diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c index 26a3b364e..a347389a2 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c @@ -146,6 +146,18 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); +#ifdef SPD_opteed + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = 0; + + /* Pass TEE base and size to bl33 */ + bl33_image_ep_info.args.arg1 = BL32_BASE; + bl33_image_ep_info.args.arg2 = BL32_SIZE; +#endif + bl31_tz380_setup(); } diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h index 3c212e378..9aa759fd3 100644 --- a/plat/imx/imx8m/imx8mq/include/platform_def.h +++ b/plat/imx/imx8m/imx8mq/include/platform_def.h @@ -32,7 +32,6 @@ #define BL31_BASE U(0x910000) #define BL31_LIMIT U(0x920000) -#define BL32_BASE U(0xfe000000) /* non-secure uboot base */ #define PLAT_NS_IMAGE_OFFSET U(0x40200000) diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk index 44ce55587..80ebe4062 100644 --- a/plat/imx/imx8m/imx8mq/platform.mk +++ b/plat/imx/imx8m/imx8mq/platform.mk @@ -44,3 +44,9 @@ A53_DISABLE_NON_TEMPORAL_HINT := 0 ERRATA_A53_835769 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 + +BL32_BASE ?= 0xfe000000 +$(eval $(call add_define,BL32_BASE)) + +BL32_SIZE ?= 0x2000000 +$(eval $(call add_define,BL32_SIZE)) -- cgit v1.2.3 From 658cb0725f6afa5838736137fec0d6171fbc23b8 Mon Sep 17 00:00:00 2001 From: Roger Lu Date: Mon, 28 Oct 2019 21:11:48 +0800 Subject: mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM 1. Switch ARMPLL_LL/CCIPLL/MAINPLL/MPLL control to SPM 2. Switch CLKSQ1/TDCLKSQ control to SPM 3. Switch ck_off/axi_26m control to SPM BUG=b:136980838 TEST=system suspend/resume passed Change-Id: I5c8506f7cf16d5cdaeb5ef8caa60a2992a361e18 Signed-off-by: Roger Lu --- plat/mediatek/mt8183/drivers/spm/spm.c | 24 ++++++++++++++++++++++++ plat/mediatek/mt8183/include/platform_def.h | 7 +++++++ 2 files changed, 31 insertions(+) diff --git a/plat/mediatek/mt8183/drivers/spm/spm.c b/plat/mediatek/mt8183/drivers/spm/spm.c index dcafd55fd..547af5781 100644 --- a/plat/mediatek/mt8183/drivers/spm/spm.c +++ b/plat/mediatek/mt8183/drivers/spm/spm.c @@ -12,6 +12,21 @@ DEFINE_BAKERY_LOCK(spm_lock); +/* CLK_SCP_CFG_0 */ +#define SPM_CK_OFF_CONTROL (0x3FF) + +/* CLK_SCP_CFG_1 */ +#define SPM_AXI_26M_SEL (0x1) + +/* AP_PLL_CON3 */ +#define SPM_PLL_CONTROL (0x7FAAAAF) + +/* AP_PLL_CON4 */ +#define SPM_PLL_OUT_OFF_CONTROL (0xFA0A) + +/* AP_PLL_CON6 */ +#define PLL_DLY (0x20000) + const char *wakeup_src_str[32] = { [0] = "R12_PCM_TIMER", [1] = "R12_SSPM_WDT_EVENT_B", @@ -324,5 +339,14 @@ void spm_boot_init(void) spm_lock_init(); mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); + /* switch ck_off/axi_26m control to SPM */ + mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL); + mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL); + + /* switch PLL/CLKSQ control to SPM */ + mmio_clrbits_32(AP_PLL_CON3, SPM_PLL_CONTROL); + mmio_clrbits_32(AP_PLL_CON4, SPM_PLL_OUT_OFF_CONTROL); + mmio_clrbits_32(AP_PLL_CON6, PLL_DLY); + NOTICE("%s() end\n", __func__); } diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h index 0a1e038b3..ad81a3331 100644 --- a/plat/mediatek/mt8183/include/platform_def.h +++ b/plat/mediatek/mt8183/include/platform_def.h @@ -39,7 +39,14 @@ #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) +#define TOPCKGEN_BASE (IO_PHYS + 0x0) +#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200) +#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x204) + #define APMIXEDSYS (IO_PHYS + 0xC000) +#define AP_PLL_CON3 (APMIXEDSYS + 0xC) +#define AP_PLL_CON4 (APMIXEDSYS + 0x10) +#define AP_PLL_CON6 (APMIXEDSYS + 0x18) #define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200) #define ARMPLL_L_CON0 (APMIXEDSYS + 0x210) #define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c) -- cgit v1.2.3 From 67f629e87e4c5b4eec6c32b37cdac635964ef1cf Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 5 Nov 2019 15:50:26 +0800 Subject: plat: imx: Correct the SGIs that used for secure interrupt Normally, SGI6 & SGI7 is used by non-secure world, these two SGIs should not be reserved for secure interrupt purpose. On i.MX8M platform, SGI8 is used for secure group0 IPI for DDR DVFS, So update the code to reserve SGI8 for secure world. Change-Id: Ib1ed9786e0a79bb729b120a0d4d791d13b6f048a Signed-off-by: Jacky Bai --- plat/imx/common/plat_imx8_gic.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/plat/imx/common/plat_imx8_gic.c b/plat/imx/common/plat_imx8_gic.c index 3a7dcfec6..afb9d1f1a 100644 --- a/plat/imx/common/plat_imx8_gic.c +++ b/plat/imx/common/plat_imx8_gic.c @@ -20,9 +20,7 @@ uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; static const interrupt_prop_t g01s_interrupt_props[] = { - INTR_PROP_DESC(6, GIC_HIGHEST_SEC_PRIORITY, - INTR_GROUP1S, GIC_INTR_CFG_LEVEL), - INTR_PROP_DESC(7, GIC_HIGHEST_SEC_PRIORITY, + INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, GIC_INTR_CFG_LEVEL), }; -- cgit v1.2.3 From 133a5c680243a282b78b94834e5f09cb17100866 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Wed, 6 Nov 2019 13:17:46 +0000 Subject: plat/arm: Re-enable PIE when RESET_TO_BL31=1 Earlier PIE support was enabled for all arm platforms when RESET_TO_BL31=1, but later on it was restricted only to FVP with patch SHA d4580d17 because of n1sdp platform. Now it has been verified that PIE does work for n1sdp platform also, so enabling it again for all arm platforms. Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5 Signed-off-by: Manish Pandey --- include/plat/arm/common/arm_def.h | 13 ++++--------- plat/arm/board/fvp/platform.mk | 9 ++------- plat/arm/common/arm_common.mk | 5 +++++ 3 files changed, 11 insertions(+), 16 deletions(-) diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 53bd13fc0..941190fdc 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -403,21 +403,16 @@ #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ PLAT_ARM_MAX_BL31_SIZE) #elif (RESET_TO_BL31) - -# if ENABLE_PIE +/* Ensure Position Independent support (PIE) is enabled for this config.*/ +# if !ENABLE_PIE +# error "BL31 must be a PIE if RESET_TO_BL31=1." +#endif /* * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely * used for building BL31 and not used for loading BL31. */ # define BL31_BASE 0x0 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE -# else -/* Put BL31_BASE in the middle of the Trusted SRAM.*/ -# define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \ - (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1)) -# define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) -# endif /* ENABLE_PIE */ - #else /* Put BL31 below BL2 in the Trusted SRAM.*/ #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 317f0bada..3a9972bb4 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -244,15 +244,10 @@ ENABLE_AMU := 1 # Enable dynamic mitigation support by default DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 +# Enable reclaiming of BL31 initialisation code for secondary cores +# stacks for FVP. ifneq (${RESET_TO_BL31},1) -# Enable reclaiming of BL31 initialisation code for secondary cores stacks for -# FVP. We cannot enable PIE for this case because the overlayed init section -# creates some dynamic relocations which cannot be handled by the fixup -# logic currently. RECLAIM_INIT_CODE := 1 -else -# Enable PIE support when RESET_TO_BL31=1 -ENABLE_PIE := 1 endif ifeq (${ENABLE_AMU},1) diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index a4a29bf74..acc379797 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -130,6 +130,11 @@ ARM_CRYPTOCELL_INTEG := 0 $(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG)) $(eval $(call add_define,ARM_CRYPTOCELL_INTEG)) +# Enable PIE support for RESET_TO_BL31 case +ifeq (${RESET_TO_BL31},1) + ENABLE_PIE := 1 +endif + # CryptoCell integration relies on coherent buffers for passing data from # the AP CPU to the CryptoCell ifeq (${ARM_CRYPTOCELL_INTEG},1) -- cgit v1.2.3 From fcc337cf49e8b3d5f08d905bf24265ca82711bd8 Mon Sep 17 00:00:00 2001 From: Vijayenthiran Subramaniam Date: Mon, 16 Sep 2019 17:05:08 +0530 Subject: gic/gic600: add support for multichip configuration Add support to configure GIC-600's multichip routing table registers. Introduce a new gic600 multichip structure in order to support platforms to pass their GIC-600 multichip information such as routing table owner, SPI blocks ownership. This driver is currently experimental and the driver api may change in the future. Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d Signed-off-by: Vijayenthiran Subramaniam --- drivers/arm/gic/v3/gic600_multichip.c | 240 ++++++++++++++++++++++++++ drivers/arm/gic/v3/gic600_multichip_private.h | 97 +++++++++++ include/drivers/arm/gic600_multichip.h | 55 ++++++ 3 files changed, 392 insertions(+) create mode 100644 drivers/arm/gic/v3/gic600_multichip.c create mode 100644 drivers/arm/gic/v3/gic600_multichip_private.h create mode 100644 include/drivers/arm/gic600_multichip.h diff --git a/drivers/arm/gic/v3/gic600_multichip.c b/drivers/arm/gic/v3/gic600_multichip.c new file mode 100644 index 000000000..c62c3f5dd --- /dev/null +++ b/drivers/arm/gic/v3/gic600_multichip.c @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * GIC-600 driver extension for multichip setup + */ + +#include +#include + +#include +#include + +#include "gic600_multichip_private.h" +#include "../common/gic_common_private.h" + +#warning "GIC-600 Multichip driver is currently experimental and the API may change in future." + +/******************************************************************************* + * GIC-600 multichip operation related helper functions + ******************************************************************************/ +static void gicd_dchipr_wait_for_power_update_progress(uintptr_t base) +{ + unsigned int retry = GICD_PUP_UPDATE_RETRIES; + + while ((read_gicd_dchipr(base) & GICD_DCHIPR_PUP_BIT) != 0U) { + if (retry-- == 0) { + ERROR("GIC-600 connection to Routing Table Owner timed " + "out\n"); + panic(); + } + } +} + +/******************************************************************************* + * Sets up the routing table owner. + ******************************************************************************/ +static void set_gicd_dchipr_rt_owner(uintptr_t base, unsigned int rt_owner) +{ + /* + * Ensure that Group enables in GICD_CTLR are disabled and no pending + * register writes to GICD_CTLR. + */ + if ((gicd_read_ctlr(base) & + (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | + CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { + ERROR("GICD_CTLR group interrupts are either enabled or have " + "pending writes. Cannot set RT owner.\n"); + panic(); + } + + /* Poll till PUP is zero before intiating write */ + gicd_dchipr_wait_for_power_update_progress(base); + + write_gicd_dchipr(base, read_gicd_dchipr(base) | + (rt_owner << GICD_DCHIPR_RT_OWNER_SHIFT)); + + /* Poll till PUP is zero to ensure write is complete */ + gicd_dchipr_wait_for_power_update_progress(base); +} + +/******************************************************************************* + * Configures the Chip Register to make connections to GICDs on + * a multichip platform. + ******************************************************************************/ +static void set_gicd_chipr_n(uintptr_t base, + unsigned int chip_id, + uint64_t chip_addr, + unsigned int spi_id_min, + unsigned int spi_id_max) +{ + unsigned int spi_block_min, spi_blocks; + uint64_t chipr_n_val; + + /* + * Ensure that group enables in GICD_CTLR are disabled and no pending + * register writes to GICD_CTLR. + */ + if ((gicd_read_ctlr(base) & + (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | + CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { + ERROR("GICD_CTLR group interrupts are either enabled or have " + "pending writes. Cannot set CHIPR register.\n"); + panic(); + } + + /* + * spi_id_min and spi_id_max of value 0 is used to intidicate that the + * chip doesn't own any SPI block. Re-assign min and max values as SPI + * id starts from 32. + */ + if (spi_id_min == 0 && spi_id_max == 0) { + spi_id_min = GIC600_SPI_ID_MIN; + spi_id_max = GIC600_SPI_ID_MIN; + } + + spi_block_min = SPI_BLOCK_MIN_VALUE(spi_id_min); + spi_blocks = SPI_BLOCKS_VALUE(spi_id_min, spi_id_max); + + chipr_n_val = (GICD_CHIPR_VALUE(chip_addr, spi_block_min, spi_blocks)) | + GICD_CHIPRx_SOCKET_STATE; + + /* + * Wait for DCHIPR.PUP to be zero before commencing writes to + * GICD_CHIPRx. + */ + gicd_dchipr_wait_for_power_update_progress(base); + + /* + * Assign chip addr, spi min block, number of spi blocks and bring chip + * online by setting SocketState. + */ + write_gicd_chipr_n(base, chip_id, chipr_n_val); + + /* + * Poll until DCHIP.PUP is zero to verify connection to rt_owner chip + * is complete. + */ + gicd_dchipr_wait_for_power_update_progress(base); + + /* + * Ensure that write to GICD_CHIPRx is successful and the chip_n came + * online. + */ + if (read_gicd_chipr_n(base, chip_id) != chipr_n_val) { + ERROR("GICD_CHIPR%u write failed\n", chip_id); + panic(); + } + + /* Ensure that chip is in consistent state */ + if (((read_gicd_chipsr(base) & GICD_CHIPSR_RTS_MASK) >> + GICD_CHIPSR_RTS_SHIFT) != + GICD_CHIPSR_RTS_STATE_CONSISTENT) { + ERROR("Chip %u routing table is not in consistent state\n", + chip_id); + panic(); + } +} + +/******************************************************************************* + * Validates the GIC-600 Multichip data structure passed by the platform. + ******************************************************************************/ +static void gic600_multichip_validate_data( + struct gic600_multichip_data *multichip_data) +{ + unsigned int i, spi_id_min, spi_id_max, blocks_of_32; + unsigned int multichip_spi_blocks = 0; + + assert(multichip_data != NULL); + + if (multichip_data->chip_count > GIC600_MAX_MULTICHIP) { + ERROR("GIC-600 Multichip count should not exceed %d\n", + GIC600_MAX_MULTICHIP); + panic(); + } + + for (i = 0; i < multichip_data->chip_count; i++) { + spi_id_min = multichip_data->spi_ids[i][SPI_MIN_INDEX]; + spi_id_max = multichip_data->spi_ids[i][SPI_MAX_INDEX]; + + if ((spi_id_min != 0) || (spi_id_max != 0)) { + + /* SPI IDs range check */ + if (!(spi_id_min >= GIC600_SPI_ID_MIN) || + !(spi_id_max < GIC600_SPI_ID_MAX) || + !(spi_id_min <= spi_id_max) || + !((spi_id_max - spi_id_min + 1) % 32 == 0)) { + ERROR("Invalid SPI IDs {%u, %u} passed for " + "Chip %u\n", spi_id_min, + spi_id_max, i); + panic(); + } + + /* SPI IDs overlap check */ + blocks_of_32 = BLOCKS_OF_32(spi_id_min, spi_id_max); + if ((multichip_spi_blocks & blocks_of_32) != 0) { + ERROR("SPI IDs of Chip %u overlapping\n", i); + panic(); + } + multichip_spi_blocks |= blocks_of_32; + } + } +} + +/******************************************************************************* + * Intialize GIC-600 Multichip operation. + ******************************************************************************/ +void gic600_multichip_init(struct gic600_multichip_data *multichip_data) +{ + unsigned int i; + + gic600_multichip_validate_data(multichip_data); + + INFO("GIC-600 Multichip driver is experimental\n"); + + /* + * Ensure that G0/G1S/G1NS interrupts are disabled. This also ensures + * that GIC-600 Multichip configuration is done first. + */ + if ((gicd_read_ctlr(multichip_data->rt_owner_base) & + (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | + CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { + ERROR("GICD_CTLR group interrupts are either enabled or have " + "pending writes.\n"); + panic(); + } + + /* Ensure that the routing table owner is in disconnected state */ + if (((read_gicd_chipsr(multichip_data->rt_owner_base) & + GICD_CHIPSR_RTS_MASK) >> GICD_CHIPSR_RTS_SHIFT) != + GICD_CHIPSR_RTS_STATE_DISCONNECTED) { + ERROR("GIC-600 routing table owner is not in disconnected " + "state to begin multichip configuration\n"); + panic(); + } + + /* Initialize the GICD which is marked as routing table owner first */ + set_gicd_dchipr_rt_owner(multichip_data->rt_owner_base, + multichip_data->rt_owner); + + set_gicd_chipr_n(multichip_data->rt_owner_base, multichip_data->rt_owner, + multichip_data->chip_addrs[multichip_data->rt_owner], + multichip_data-> + spi_ids[multichip_data->rt_owner][SPI_MIN_INDEX], + multichip_data-> + spi_ids[multichip_data->rt_owner][SPI_MAX_INDEX]); + + for (i = 0; i < multichip_data->chip_count; i++) { + if (i == multichip_data->rt_owner) + continue; + + set_gicd_chipr_n(multichip_data->rt_owner_base, i, + multichip_data->chip_addrs[i], + multichip_data->spi_ids[i][SPI_MIN_INDEX], + multichip_data->spi_ids[i][SPI_MAX_INDEX]); + } +} diff --git a/drivers/arm/gic/v3/gic600_multichip_private.h b/drivers/arm/gic/v3/gic600_multichip_private.h new file mode 100644 index 000000000..b0217b6d4 --- /dev/null +++ b/drivers/arm/gic/v3/gic600_multichip_private.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GIC600_MULTICHIP_PRIVATE_H +#define GIC600_MULTICHIP_PRIVATE_H + +#include + +#include "gicv3_private.h" + +/* GIC600 GICD multichip related offsets */ +#define GICD_CHIPSR U(0xC000) +#define GICD_DCHIPR U(0xC004) +#define GICD_CHIPR U(0xC008) + +/* GIC600 GICD multichip related masks */ +#define GICD_CHIPRx_PUP_BIT BIT_64(1) +#define GICD_CHIPRx_SOCKET_STATE BIT_64(0) +#define GICD_DCHIPR_PUP_BIT BIT_32(0) +#define GICD_CHIPSR_RTS_MASK (BIT_32(4) | BIT_32(5)) + +/* GIC600 GICD multichip related shifts */ +#define GICD_CHIPRx_ADDR_SHIFT 16 +#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10 +#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5 +#define GICD_CHIPSR_RTS_SHIFT 4 +#define GICD_DCHIPR_RT_OWNER_SHIFT 4 + +#define GICD_CHIPSR_RTS_STATE_DISCONNECTED U(0) +#define GICD_CHIPSR_RTS_STATE_UPDATING U(1) +#define GICD_CHIPSR_RTS_STATE_CONSISTENT U(2) + +/* SPI interrupt id minimum and maximum range */ +#define GIC600_SPI_ID_MIN 32 +#define GIC600_SPI_ID_MAX 960 + +/* Number of retries for PUP update */ +#define GICD_PUP_UPDATE_RETRIES 10000 + +#define SPI_MIN_INDEX 0 +#define SPI_MAX_INDEX 1 + +#define SPI_BLOCK_MIN_VALUE(spi_id_min) \ + (((spi_id_min) - GIC600_SPI_ID_MIN) / \ + GIC600_SPI_ID_MIN) +#define SPI_BLOCKS_VALUE(spi_id_min, spi_id_max) \ + (((spi_id_max) - (spi_id_min) + 1) / \ + GIC600_SPI_ID_MIN) +#define GICD_CHIPR_VALUE(chip_addr, spi_block_min, spi_blocks) \ + (((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \ + ((spi_block_min) << GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT) | \ + ((spi_blocks) << GICD_CHIPRx_SPI_BLOCKS_SHIFT)) + +/* + * Multichip data assertion macros + */ +/* Set bits from 0 to ((spi_id_max + 1) / 32) */ +#define SPI_BLOCKS_TILL_MAX(spi_id_max) ((1 << (((spi_id_max) + 1) >> 5)) - 1) +/* Set bits from 0 to (spi_id_min / 32) */ +#define SPI_BLOCKS_TILL_MIN(spi_id_min) ((1 << ((spi_id_min) >> 5)) - 1) +/* Set bits from (spi_id_min / 32) to ((spi_id_max + 1) / 32) */ +#define BLOCKS_OF_32(spi_id_min, spi_id_max) \ + SPI_BLOCKS_TILL_MAX(spi_id_max) ^ \ + SPI_BLOCKS_TILL_MIN(spi_id_min) + +/******************************************************************************* + * GIC-600 multichip operation related helper functions + ******************************************************************************/ +static inline uint32_t read_gicd_dchipr(uintptr_t base) +{ + return mmio_read_32(base + GICD_DCHIPR); +} + +static inline uint64_t read_gicd_chipr_n(uintptr_t base, uint8_t n) +{ + return mmio_read_64(base + (GICD_CHIPR + (8U * n))); +} + +static inline uint32_t read_gicd_chipsr(uintptr_t base) +{ + return mmio_read_32(base + GICD_CHIPSR); +} + +static inline void write_gicd_dchipr(uintptr_t base, uint32_t val) +{ + mmio_write_32(base + GICD_DCHIPR, val); +} + +static inline void write_gicd_chipr_n(uintptr_t base, uint8_t n, uint64_t val) +{ + mmio_write_64(base + (GICD_CHIPR + (8U * n)), val); +} + +#endif /* GIC600_MULTICHIP_PRIVATE_H */ diff --git a/include/drivers/arm/gic600_multichip.h b/include/drivers/arm/gic600_multichip.h new file mode 100644 index 000000000..bda406bba --- /dev/null +++ b/include/drivers/arm/gic600_multichip.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GIC600_MULTICHIP_H +#define GIC600_MULTICHIP_H + +#include + +/* + * GIC-600 microarchitecture supports coherent multichip environments containing + * up to 16 chips. + */ +#define GIC600_MAX_MULTICHIP 16 + +/* SPI IDs array consist of min and max ids */ +#define GIC600_SPI_IDS_SIZE 2 + +/******************************************************************************* + * GIC-600 multichip data structure describes platform specific attributes + * related to GIC-600 multichip. Platform port is expected to define these + * attributes to initialize the multichip related registers and create + * successful connections between the GIC-600s in a multichip system. + * + * The 'rt_owner_base' field contains the base address of the GIC Distributor + * which owns the routing table. + * + * The 'rt_owner' field contains the chip number which owns the routing table. + * Chip number or chip_id starts from 0. + * + * The 'chip_count' field contains the total number of chips in a multichip + * system. This should match the number of entries in 'chip_addrs' and 'spi_ids' + * fields. + * + * The 'chip_addrs' field contains array of chip addresses. These addresses are + * implementation specific values. + * + * The 'spi_ids' field contains array of minimum and maximum SPI interrupt ids + * that each chip owns. Note that SPI interrupt ids can range from 32 to 960 and + * it should be group of 32 (i.e., SPI minimum and (SPI maximum + 1) should be + * a multiple of 32). If a chip doesn't own any SPI interrupts a value of {0, 0} + * should be passed. + ******************************************************************************/ +struct gic600_multichip_data { + uintptr_t rt_owner_base; + unsigned int rt_owner; + unsigned int chip_count; + uint64_t chip_addrs[GIC600_MAX_MULTICHIP]; + unsigned int spi_ids[GIC600_MAX_MULTICHIP][GIC600_SPI_IDS_SIZE]; +}; + +void gic600_multichip_init(struct gic600_multichip_data *multichip_data); +#endif /* GIC600_MULTICHIP_H */ -- cgit v1.2.3 From 6799a370e2b9e61b997410044044a8d3fb308806 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Mon, 14 Oct 2019 17:37:38 +0100 Subject: n1sdp: setup multichip gic routing table N1SDP supports multichip configuration wherein n1sdp boards are connected over high speed coherent CCIX link, for now only dual-chip is supported. Whether or not multiple chips are present is dynamically probed by SCP firmware and passed on to TF-A, routing table will be set up only if multiple chips are present. Initialize GIC-600 multichip operation by overriding the default GICR frames with array of GICR frames and setting the chip 0 as routing table owner. Change-Id: Ida35672be4bbf4c517469a5b330548d75e593ff2 Signed-off-by: Manish Pandey --- plat/arm/board/n1sdp/n1sdp_bl31_setup.c | 35 +++++++++++++++++++++++++++++++-- plat/arm/board/n1sdp/platform.mk | 1 + 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c index 79a0a7997..4f158ee4d 100644 --- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c +++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -53,6 +54,26 @@ static scmi_channel_plat_info_t n1sdp_scmi_plat_info = { .ring_doorbell = &mhu_ring_doorbell }; +static struct gic600_multichip_data n1sdp_multichip_data __init = { + .rt_owner_base = PLAT_ARM_GICD_BASE, + .rt_owner = 0, + .chip_count = 1, + .chip_addrs = { + PLAT_ARM_GICD_BASE >> 16, + PLAT_ARM_GICD_BASE >> 16 + }, + .spi_ids = { + {32, 255}, + {0, 0} + } +}; + +static uintptr_t n1sdp_multichip_gicr_frames[3] = { + PLAT_ARM_GICR_BASE, + PLAT_ARM_GICR_BASE + PLAT_ARM_REMOTE_CHIP_OFFSET, + 0 +}; + scmi_channel_plat_info_t *plat_css_get_scmi_info() { return &n1sdp_scmi_plat_info; @@ -149,14 +170,18 @@ void copy_bl33(uint32_t src, uint32_t dst, uint32_t size) } } +void n1sdp_bl31_multichip_setup(void) +{ + plat_arm_override_gicr_frames(n1sdp_multichip_gicr_frames); + gic600_multichip_init(&n1sdp_multichip_data); +} + void bl31_platform_setup(void) { int ret; struct n1sdp_plat_info plat_info; struct n1sdp_bl33_info bl33_info; - arm_bl31_platform_setup(); - ret = sds_init(); if (ret != SDS_OK) { ERROR("SDS initialization failed\n"); @@ -181,6 +206,12 @@ void bl31_platform_setup(void) panic(); } + if (plat_info.multichip_mode) { + n1sdp_multichip_data.chip_count = plat_info.slave_count + 1; + n1sdp_bl31_multichip_setup(); + } + arm_bl31_platform_setup(); + dmc_ecc_setup(plat_info.local_ddr_size); /* Check if remote memory is present */ diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk index 986bd70a5..8816670dc 100644 --- a/plat/arm/board/n1sdp/platform.mk +++ b/plat/arm/board/n1sdp/platform.mk @@ -18,6 +18,7 @@ N1SDP_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S N1SDP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v3/gicv3_main.c \ drivers/arm/gic/v3/gicv3_helpers.c \ + drivers/arm/gic/v3/gic600_multichip.c \ plat/common/plat_gicv3.c \ plat/arm/common/arm_gicv3.c \ drivers/arm/gic/v3/gic600.c -- cgit v1.2.3 From 9afe8cdc06c8e82b83d327978b937e51ade4925a Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Tue, 3 Sep 2019 21:06:17 +0300 Subject: Coding guideline suggest not to use unsigned long `unsigned long` should be replaced to 1. `unsigned int` or `unsigned long long` - If fixed, based on the architecture AArch32 or AArch64 2. `u_register_t` - If it is supposed to be 32-bit wide in AArch32 and 64-bit wide in AArch64. Translation descriptors are always 32-bit wide, here `uint32_t` is used to describe the `exact size` of translation descriptors instead of `unsigned int` which guarantees minimum 32-bits Signed-off-by: Deepika Bhavnani Change-Id: I6a2af2e8b3c71170e2634044e0b887f07a41677e --- lib/xlat_tables/aarch32/nonlpae_tables.c | 22 +++++++++++----------- lib/xlat_tables_v2/xlat_tables_core.c | 3 ++- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/lib/xlat_tables/aarch32/nonlpae_tables.c b/lib/xlat_tables/aarch32/nonlpae_tables.c index bd6b152ef..b8c268665 100644 --- a/lib/xlat_tables/aarch32/nonlpae_tables.c +++ b/lib/xlat_tables/aarch32/nonlpae_tables.c @@ -284,10 +284,10 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, } /* map all memory as shared/global/domain0/no-usr access */ -static unsigned long mmap_desc(unsigned attr, unsigned long addr_pa, - unsigned int level) +static uint32_t mmap_desc(unsigned attr, unsigned int addr_pa, + unsigned int level) { - unsigned long desc; + uint32_t desc; switch (level) { case 1: @@ -380,14 +380,14 @@ static unsigned int mmap_region_attr(const mmap_region_t *mm, uintptr_t base_va, } static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm, - unsigned long base_va, - unsigned long *table, + unsigned int base_va, + uint32_t *table, unsigned int level) { unsigned int level_size_shift = (level == 1) ? ONE_MB_SHIFT : FOUR_KB_SHIFT; unsigned int level_size = 1 << level_size_shift; - unsigned long level_index_mask = (level == 1) ? + unsigned int level_index_mask = (level == 1) ? (NUM_1MB_IN_4GB - 1) << ONE_MB_SHIFT : (NUM_4K_IN_1MB - 1) << FOUR_KB_SHIFT; @@ -396,7 +396,7 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm, VERBOSE("init xlat table at %p (level%1d)\n", (void *)table, level); do { - unsigned long desc = MMU32B_UNSET_DESC; + uint32_t desc = MMU32B_UNSET_DESC; if (mm->base_va + mm->size <= base_va) { /* Area now after the region so skip it */ @@ -427,7 +427,7 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm, } if (desc == MMU32B_UNSET_DESC) { - unsigned long xlat_table; + uintptr_t xlat_table; /* * Area not covered by a region so need finer table @@ -443,7 +443,7 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm, ~(MMU32B_L1_TABLE_ALIGN - 1); desc = *table; } else { - xlat_table = (unsigned long)mmu_l2_base + + xlat_table = (uintptr_t)mmu_l2_base + next_xlat * MMU32B_L2_TABLE_SIZE; next_xlat++; assert(next_xlat <= MAX_XLAT_TABLES); @@ -456,7 +456,7 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm, } /* Recurse to fill in new table */ mm = init_xlation_table_inner(mm, base_va, - (unsigned long *)xlat_table, + (uint32_t *)xlat_table, level + 1); } #if LOG_LEVEL >= LOG_LEVEL_VERBOSE @@ -480,7 +480,7 @@ void init_xlat_tables(void) memset(mmu_l1_base, 0, MMU32B_L1_TABLE_SIZE); - init_xlation_table_inner(mmap, 0, (unsigned long *)mmu_l1_base, 1); + init_xlation_table_inner(mmap, 0, (uint32_t *)mmu_l1_base, 1); VERBOSE("init xlat - max_va=%p, max_pa=%llx\n", (void *)xlat_max_va, xlat_max_pa); diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c index 4f62f469f..3c0865b81 100644 --- a/lib/xlat_tables_v2/xlat_tables_core.c +++ b/lib/xlat_tables_v2/xlat_tables_core.c @@ -607,7 +607,8 @@ static uintptr_t xlat_tables_map_region(xlat_ctx_t *ctx, mmap_region_t *mm, } /* Point to new subtable from this one. */ - table_base[table_idx] = TABLE_DESC | (unsigned long)subtable; + table_base[table_idx] = + TABLE_DESC | (uintptr_t)subtable; /* Recurse to write into subtable */ end_va = xlat_tables_map_region(ctx, mm, table_idx_va, -- cgit v1.2.3 From 38c078e05c4eebc4c25c9cec5201197ec461bd70 Mon Sep 17 00:00:00 2001 From: Imre Kis Date: Fri, 25 Oct 2019 14:29:51 +0200 Subject: Add multithreaded DynamIQ dts file The new dts file overrides the MPIDR values of the processing elements which were defined in the common dtsi file. The new dts file defines four cores in a single cluster, each core having two threads. Signed-off-by: Imre Kis Change-Id: I0f8d8d250289077aee11eede4508871bb61dbc88 --- fdts/fvp-base-gicv3-psci-dynamiq-2t.dts | 41 +++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 fdts/fvp-base-gicv3-psci-dynamiq-2t.dts diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts new file mode 100644 index 000000000..f35eaf482 --- /dev/null +++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +/include/ "fvp-base-gicv3-psci-common.dtsi" + +&CPU0 { + reg = <0x0 0x0>; +}; + +&CPU1 { + reg = <0x0 0x1>; +}; + +&CPU2 { + reg = <0x0 0x100>; +}; + +&CPU3 { + reg = <0x0 0x101>; +}; + +&CPU4 { + reg = <0x0 0x200>; +}; + +&CPU5 { + reg = <0x0 0x201>; +}; + +&CPU6 { + reg = <0x0 0x300>; +}; + +&CPU7 { + reg = <0x0 0x301>; +}; -- cgit v1.2.3 From 39009031eb19b7df1275b99d728ae77775e9b0eb Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Wed, 23 Oct 2019 15:39:31 -0500 Subject: docs: Add Cortex-Hercules/HerculesAE CPU support Signed-off-by: Lauren Wehrmeister Change-Id: Ia1ff13be1308e63c2854d2b6e5f6651750186abe --- docs/change-log.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/change-log.rst b/docs/change-log.rst index a0db2a9bd..cf5b57ac6 100644 --- a/docs/change-log.rst +++ b/docs/change-log.rst @@ -60,6 +60,10 @@ New Features - Neoverse Zeus: Apply the MSR SSBS instruction + - cortex-Hercules/HerculesAE: Support added for Cortex-Hercules and + Cortex-HerculesAE CPUs + - cortex-Hercules/HerculesAE: Enable AMU for Cortex-Hercules and Cortex-HerculesAE + - cortex-a76AE: Support added for Cortex-A76AE CPU - cortex-a76: Workaround for erratum 1257314, 1262606, 1262888, 1275112, 1286807 -- cgit v1.2.3 From 12f06f1c0e1962a5d6a0239581574ce8ea456a62 Mon Sep 17 00:00:00 2001 From: Tejal Kudav Date: Tue, 14 Feb 2017 18:02:04 -0800 Subject: Tegra194: Enable system suspend This patch does the following: 1. Populate the cstate info corresponding to system suspend and communicate it to the MCE 2. Ask for MCE's acknowledgement for entering system suspend and instruct MCE to get inside system suspend once permitted Change-Id: I51e1910e24a7e61e36ac2d12ce271290e433e506 Signed-off-by: Tejal Kudav Signed-off-by: Vignesh Radhakrishnan --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index b7a6c4f8d..495a2c40d 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -18,6 +18,7 @@ #include #include #include +#include extern void prepare_core_pwr_dwn(void); @@ -93,6 +94,7 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) uint64_t smmu_ctx_base; #endif uint32_t val; + mce_cstate_info_t cstate_info = { 0 }; /* get the state ID */ pwr_domain_state = target_state->pwr_domain_state; @@ -131,7 +133,24 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) tegra_smmu_save_context(0); #endif - /* Instruct the MCE to enter system suspend state */ + /* Prepare for system suspend */ + cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6; + cstate_info.system = TEGRA_NVG_SYSTEM_SC7; + cstate_info.system_state_force = 1; + cstate_info.update_wake_mask = 1; + mce_update_cstate_info(&cstate_info); + + do { + val = mce_command_handler( + MCE_CMD_IS_SC7_ALLOWED, + TEGRA_NVG_CORE_C7, + MCE_CORE_SLEEP_TIME_INFINITE, + 0); + } while (val == 0); + + /* Instruct the MCE to enter system suspend state */ + (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, + TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); } return PSCI_E_SUCCESS; -- cgit v1.2.3 From 5da8ec562ecee9d70c13e0d62d17da6780be01e2 Mon Sep 17 00:00:00 2001 From: Vignesh Radhakrishnan Date: Mon, 10 Apr 2017 15:07:39 -0700 Subject: Tegra194: skip notifying MCE in fake system suspend - In pre-silicon platforms, MCE might not be ready to support system suspend(SC7) - Thus, in fake system suspend mode, bypass waiting for MCE's acknowledgment to enter system suspend Change-Id: Ia3c010ce080c4283ab1233ba82e3e577adca34f6 Signed-off-by: Vignesh Radhakrishnan --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 40 ++++++++++++++----------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 495a2c40d..e53d5946e 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -22,6 +22,8 @@ extern void prepare_core_pwr_dwn(void); +extern uint8_t tegra_fake_system_suspend; + #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM extern void tegra186_cpu_reset_handler(void); extern uint32_t __tegra186_cpu_reset_handler_data, @@ -133,24 +135,28 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) tegra_smmu_save_context(0); #endif - /* Prepare for system suspend */ - cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6; - cstate_info.system = TEGRA_NVG_SYSTEM_SC7; - cstate_info.system_state_force = 1; - cstate_info.update_wake_mask = 1; - mce_update_cstate_info(&cstate_info); + if (tegra_fake_system_suspend == 0U) { - do { - val = mce_command_handler( - MCE_CMD_IS_SC7_ALLOWED, - TEGRA_NVG_CORE_C7, - MCE_CORE_SLEEP_TIME_INFINITE, - 0); - } while (val == 0); - - /* Instruct the MCE to enter system suspend state */ - (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, - TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); + /* Prepare for system suspend */ + cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6; + cstate_info.system = TEGRA_NVG_SYSTEM_SC7; + cstate_info.system_state_force = 1; + cstate_info.update_wake_mask = 1; + + mce_update_cstate_info(&cstate_info); + + do { + val = mce_command_handler( + MCE_CMD_IS_SC7_ALLOWED, + TEGRA_NVG_CORE_C7, + MCE_CORE_SLEEP_TIME_INFINITE, + 0); + } while (val == 0); + + /* Instruct the MCE to enter system suspend state */ + (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, + TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); + } } return PSCI_E_SUCCESS; -- cgit v1.2.3 From 2fdd9ae6c7b79b2e667a743eb3d781ea0e7f1da0 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 26 Apr 2017 08:57:27 -0700 Subject: Tegra194: add macros to read GPU reset status This patch adds macros to check the GPU reset status bit, before resizing the VideoMem region. Change-Id: I4377c1ce1ac6d3bd14c7db83526b99d72bdb41ed Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra_def.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index a1b70db9f..79d776f55 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -232,5 +232,7 @@ * Tegra Clock and Reset Controller constants ******************************************************************************/ #define TEGRA_CAR_RESET_BASE 0x200000000 +#define TEGRA_GPU_RESET_REG_OFFSET 0x18UL +#define GPU_RESET_BIT (1UL << 0) #endif /* __TEGRA_DEF_H__ */ -- cgit v1.2.3 From 73dad7f9c70eb1a867791efefc077e80cef279e5 Mon Sep 17 00:00:00 2001 From: Anthony Zhou Date: Fri, 28 Apr 2017 13:52:58 +0800 Subject: Tegra194: mce: fix function declaration conflicts To fix MISRA defects, remove union in t186 MCE drivers this driver should compatible with that. Change-Id: I09e96a1874dd86626c7e41c92a1484a84e387402 Signed-off-by: Anthony Zhou --- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index f13643fc0..0a6515e1c 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -25,7 +25,7 @@ /******************************************************************************* * Common handler for all MCE commands ******************************************************************************/ -int32_t mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, +int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, uint64_t arg2) { uint64_t ret64 = 0, arg3, arg4, arg5; @@ -161,7 +161,7 @@ int32_t mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, break; default: - ERROR("unknown MCE command (%lld)\n", cmd); + ERROR("unknown MCE command (%llu)\n", cmd); ret = EINVAL; break; } @@ -196,7 +196,7 @@ int32_t mce_update_gsc_tzram(void) /******************************************************************************* * Handler to issue the UPDATE_CSTATE_INFO request ******************************************************************************/ -void mce_update_cstate_info(mce_cstate_info_t *cstate) +void mce_update_cstate_info(const mce_cstate_info_t *cstate) { /* issue the UPDATE_CSTATE_INFO request */ nvg_update_cstate_info(cstate->cluster, cstate->ccplex, cstate->system, -- cgit v1.2.3 From 42de03848f61c79f4f1aeb2ce91df1eac59fa3fb Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 28 Apr 2017 08:45:53 -0700 Subject: Tegra194: implement handler to retrieve power domain tree This patch implements the platform handler to return the pointer to the power domain tree. Change-Id: I74ea7002c7a461a028b4a252bbd354256fdc0647 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_setup.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 3424d1928..7ca65dd06 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -45,6 +45,14 @@ const unsigned char tegra_power_domain_tree_desc[] = { PLATFORM_MAX_CPUS_PER_CLUSTER }; +/******************************************************************************* + * This function returns the Tegra default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return tegra_power_domain_tree_desc; +} + /* * Table of regions to map using the MMU. */ -- cgit v1.2.3 From 2e446f50bde561913276ef6d930a20dfeadf416d Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 28 Apr 2017 18:15:09 -0700 Subject: Tegra194: sip_calls: mark unused parameter as const This patch marks the unused parameter 'cookie', to the plat_sip_handler() function, as const to fix an issue flagged by the MISRA scan. Change-Id: I53fdd2caadf43fef17fbc3a50a18bf7fdbd42d39 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_sip_calls.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index cb57c9b61..eaad73a40 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -51,7 +51,7 @@ int plat_sip_handler(uint32_t smc_fid, uint64_t x2, uint64_t x3, uint64_t x4, - void *cookie, + const void *cookie, void *handle, uint64_t flags) { -- cgit v1.2.3 From d191573e6ae616adb3b6ce2404a4cff9bf4c0052 Mon Sep 17 00:00:00 2001 From: Harvey Hsieh Date: Wed, 23 Nov 2016 19:15:02 +0800 Subject: Tegra194: remove L2 ECC parity protection setting This patch removes the code to enable L2 ECC parity protection bit, as Tegra194 does not have any Cortex-A57 CPUs. Change-Id: I4b56595fea2652e8bb8ab4a7ae7567278ecff9af Signed-off-by: Harvey Hsieh --- plat/nvidia/tegra/soc/t194/plat_setup.c | 37 --------------------------------- 1 file changed, 37 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 7ca65dd06..a3a2515ca 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -25,9 +25,6 @@ #include #include -DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) -extern uint64_t tegra_enable_l2_ecc_parity_prot; - /******************************************************************************* * The Tegra power domain tree has a single system level power domain i.e. a * single root node. The first entry in the power domain descriptor specifies @@ -145,49 +142,15 @@ uint32_t plat_get_console_from_id(int id) return tegra186_uart_addresses[id]; } -/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ -#define TEGRA186_VER_A02P 0x1201 - /******************************************************************************* * Handler for early platform setup ******************************************************************************/ void plat_early_platform_setup(void) { - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; - uint32_t chip_subrev, val; /* sanity check MCE firmware compatibility */ mce_verify_firmware_version(); - /* - * Enable ECC and Parity Protection for Cortex-A57 CPUs - * for Tegra A02p SKUs - */ - if (impl != DENVER_IMPL) { - - /* get the major, minor and sub-version values */ - chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & - SUBREVISION_MASK; - - /* prepare chip version number */ - val = (tegra_get_chipid_major() << 12) | - (tegra_get_chipid_minor() << 8) | - chip_subrev; - - /* enable L2 ECC for Tegra186 A02P and beyond */ - if (val >= TEGRA186_VER_A02P) { - - val = read_l2ctlr_el1(); - val |= L2_ECC_PARITY_PROTECTION_BIT; - write_l2ctlr_el1(val); - - /* - * Set the flag to enable ECC/Parity Protection - * when we exit System Suspend or Cluster Powerdn - */ - tegra_enable_l2_ecc_parity_prot = 1; - } - } } /* Secure IRQs for Tegra186 */ -- cgit v1.2.3 From 9e7d66314ac2094094be930e3d36a815de47e500 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Mon, 14 Oct 2019 13:47:21 +0200 Subject: Refactor load_auth_image_internal(). The pre-processor directives make it hard to read the non-TBB version of this function. Refactor the code to improve readability. No functional change introduced. In particular, introduce a new helper function load_image_flush(), that simply loads an image and flushes it out to main memory. This is the only thing load_auth_image_internal() needs to do when TBB is disabled or when authentication is dynamically disabled. In other cases, we need to recursively authenticate the parent images up to the root of trust. To make this clearer, this code gets moved to a TBB-specific helper function called load_auth_image_recursive(). As a result, load_auth_image_internal() now boils down to calling the right helper function (depending on TBB enablement and dynamic authentication status). Change-Id: I20a39a3b833810b97ecf4219358e7d2cac263890 Signed-off-by: Sandrine Bailleux --- common/bl_common.c | 92 ++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 59 insertions(+), 33 deletions(-) diff --git a/common/bl_common.c b/common/bl_common.c index e6f98029e..b74225b13 100644 --- a/common/bl_common.c +++ b/common/bl_common.c @@ -143,26 +143,45 @@ exit: return io_result; } -static int load_auth_image_internal(unsigned int image_id, +/* + * Load an image and flush it out to main memory so that it can be executed + * later by any CPU, regardless of cache and MMU state. + */ +static int load_image_flush(unsigned int image_id, + image_info_t *image_data) +{ + int rc; + + rc = load_image(image_id, image_data); + if (rc == 0) { + flush_dcache_range(image_data->image_base, + image_data->image_size); + } + + return rc; +} + + +#if TRUSTED_BOARD_BOOT +/* + * This function uses recursion to authenticate the parent images up to the root + * of trust. + */ +static int load_auth_image_recursive(unsigned int image_id, image_info_t *image_data, int is_parent_image) { int rc; + unsigned int parent_id; -#if TRUSTED_BOARD_BOOT - if (dyn_is_auth_disabled() == 0) { - unsigned int parent_id; - - /* Use recursion to authenticate parent images */ - rc = auth_mod_get_parent_id(image_id, &parent_id); - if (rc == 0) { - rc = load_auth_image_internal(parent_id, image_data, 1); - if (rc != 0) { - return rc; - } + /* Use recursion to authenticate parent images */ + rc = auth_mod_get_parent_id(image_id, &parent_id); + if (rc == 0) { + rc = load_auth_image_recursive(parent_id, image_data, 1); + if (rc != 0) { + return rc; } } -#endif /* TRUSTED_BOARD_BOOT */ /* Load the image */ rc = load_image(image_id, image_data); @@ -170,51 +189,58 @@ static int load_auth_image_internal(unsigned int image_id, return rc; } -#if TRUSTED_BOARD_BOOT - if (dyn_is_auth_disabled() == 0) { - /* Authenticate it */ - rc = auth_mod_verify_img(image_id, - (void *)image_data->image_base, - image_data->image_size); - if (rc != 0) { - /* Authentication error, zero memory and flush it right away. */ - zero_normalmem((void *)image_data->image_base, + /* Authenticate it */ + rc = auth_mod_verify_img(image_id, + (void *)image_data->image_base, + image_data->image_size); + if (rc != 0) { + /* Authentication error, zero memory and flush it right away. */ + zero_normalmem((void *)image_data->image_base, image_data->image_size); - flush_dcache_range(image_data->image_base, - image_data->image_size); - return -EAUTH; - } + flush_dcache_range(image_data->image_base, + image_data->image_size); + return -EAUTH; } -#endif /* TRUSTED_BOARD_BOOT */ /* * Flush the image to main memory so that it can be executed later by - * any CPU, regardless of cache and MMU state. If TBB is enabled, then - * the file has been successfully loaded and authenticated and flush - * only for child images, not for the parents (certificates). + * any CPU, regardless of cache and MMU state. This is only needed for + * child images, not for the parents (certificates). */ if (is_parent_image == 0) { flush_dcache_range(image_data->image_base, image_data->image_size); } - return 0; } +#endif /* TRUSTED_BOARD_BOOT */ + +static int load_auth_image_internal(unsigned int image_id, + image_info_t *image_data) +{ +#if TRUSTED_BOARD_BOOT + if (dyn_is_auth_disabled() == 0) { + return load_auth_image_recursive(image_id, image_data, 0); + } +#endif + + return load_image_flush(image_id, image_data); +} /******************************************************************************* * Generic function to load and authenticate an image. The image is actually * loaded by calling the 'load_image()' function. Therefore, it returns the * same error codes if the loading operation failed, or -EAUTH if the * authentication failed. In addition, this function uses recursion to - * authenticate the parent images up to the root of trust. + * authenticate the parent images up to the root of trust (if TBB is enabled). ******************************************************************************/ int load_auth_image(unsigned int image_id, image_info_t *image_data) { int err; do { - err = load_auth_image_internal(image_id, image_data, 0); + err = load_auth_image_internal(image_id, image_data); } while ((err != 0) && (plat_try_next_boot_source() != 0)); return err; -- cgit v1.2.3 From f2976bdda89d466c35d66fb480e1b355703c9810 Mon Sep 17 00:00:00 2001 From: Max Shvetsov Date: Thu, 31 Oct 2019 08:35:02 +0000 Subject: TF-A: Fix non-standard frequency issue in udelay Previous implementation of timers assumed that clk_div has pretty representation in MHz (10MHz, 100MHz, etc). Unusual frequencies (99.99MHz) were causing assertion error and made udelay unusable. Signed-off-by: Max Shvetsov Change-Id: Ic915fff224369d113fd9f8edbcfff169fca8beac --- drivers/delay_timer/delay_timer.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/delay_timer/delay_timer.c b/drivers/delay_timer/delay_timer.c index 8c2996ec3..a3fd7bfeb 100644 --- a/drivers/delay_timer/delay_timer.c +++ b/drivers/delay_timer/delay_timer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,23 +27,32 @@ void udelay(uint32_t usec) (timer_ops->clk_div != 0U) && (timer_ops->get_timer_value != NULL)); - uint32_t start, delta, total_delta; + uint32_t start, delta; + uint64_t total_delta; - assert(usec < (UINT32_MAX / timer_ops->clk_div)); + assert(usec < (UINT64_MAX / timer_ops->clk_div)); start = timer_ops->get_timer_value(); /* Add an extra tick to avoid delaying less than requested. */ total_delta = - div_round_up(usec * timer_ops->clk_div, + div_round_up((uint64_t)usec * timer_ops->clk_div, timer_ops->clk_mult) + 1U; + /* + * Precaution for the total_delta ~ UINT32_MAX and the fact that we + * cannot catch every tick of the timer. + * For example 100MHz timer over 25MHz APB will miss at least 4 ticks. + * 1000U is an arbitrary big number which is believed to be sufficient. + */ + assert(total_delta < (UINT32_MAX - 1000U)); do { /* * If the timer value wraps around, the subtraction will * overflow and it will still give the correct result. + * delta is decreasing counter */ - delta = start - timer_ops->get_timer_value(); /* Decreasing counter */ + delta = start - timer_ops->get_timer_value(); } while (delta < total_delta); } @@ -54,6 +63,7 @@ void udelay(uint32_t usec) ***********************************************************/ void mdelay(uint32_t msec) { + assert((msec * 1000UL) < UINT32_MAX); udelay(msec * 1000U); } -- cgit v1.2.3 From ff2d38c2dd7a02ebf458dd82913e0a2e4f30c151 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Thu, 17 Oct 2019 13:19:02 +0000 Subject: doc: Add missing terms to the glossary Change-Id: Ibca94eae1a9a89c98b4d7cb5b4fd8943bf854030 Signed-off-by: Paul Beesley --- docs/global_substitutions.txt | 8 +++++++- docs/glossary.rst | 24 +++++++++++++++++++++++- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/docs/global_substitutions.txt b/docs/global_substitutions.txt index fdca9c3f4..491b160e6 100644 --- a/docs/global_substitutions.txt +++ b/docs/global_substitutions.txt @@ -1,11 +1,13 @@ .. |AArch32| replace:: :term:`AArch32` .. |AArch64| replace:: :term:`AArch64` .. |API| replace:: :term:`API` +.. |BTI| replace:: :term:`BTI` .. |CoT| replace:: :term:`CoT` .. |COT| replace:: :term:`COT` .. |CSS| replace:: :term:`CSS` .. |CVE| replace:: :term:`CVE` .. |DS-5| replace:: :term:`DS-5` +.. |DSU| replace:: :term:`DSU` .. |DT| replace:: :term:`DT` .. |EL| replace:: :term:`EL` .. |EHF| replace:: :term:`EHF` @@ -19,10 +21,12 @@ .. |MMU| replace:: :term:`MMU` .. |MPAM| replace:: :term:`MPAM` .. |MPIDR| replace:: :term:`MPIDR` +.. |MTE| replace:: :term:`MTE` .. |OEN| replace:: :term:`OEN` .. |OP-TEE| replace:: :term:`OP-TEE` .. |OTE| replace:: :term:`OTE` .. |PDD| replace:: :term:`PDD` +.. |PAUTH| replace:: :term:`PAUTH` .. |PMF| replace:: :term:`PMF` .. |PSCI| replace:: :term:`PSCI` .. |RAS| replace:: :term:`RAS` @@ -41,6 +45,7 @@ .. |SPCI| replace:: :term:`SPCI` .. |SPD| replace:: :term:`SPD` .. |SPM| replace:: :term:`SPM` +.. |SSBS| replace:: :term:`SSBS` .. |SVE| replace:: :term:`SVE` .. |TBB| replace:: :term:`TBB` .. |TBBR| replace:: :term:`TBBR` @@ -51,6 +56,7 @@ .. |TLK| replace:: :term:`TLK` .. |TSP| replace:: :term:`TSP` .. |TZC| replace:: :term:`TZC` +.. |UBSAN| replace:: :term:`UBSAN` .. |UEFI| replace:: :term:`UEFI` .. |WDOG| replace:: :term:`WDOG` -.. |XLAT| replace:: :term:`XLAT` \ No newline at end of file +.. |XLAT| replace:: :term:`XLAT` diff --git a/docs/glossary.rst b/docs/glossary.rst index 45caf4629..2f19df59c 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -18,6 +18,10 @@ You can find additional definitions in the `Arm Glossary`_. API Application Programming Interface + BTI + Branch Target Identification. An Armv8.5 extension providing additional + control flow integrity around indirect branches and their targets. + CoT COT Chain of Trust @@ -32,6 +36,9 @@ You can find additional definitions in the `Arm Glossary`_. DS-5 Arm Development Studio 5 + DSU + DynamIQ Shared Unit + DT Device Tree @@ -72,6 +79,10 @@ You can find additional definitions in the `Arm Glossary`_. MPIDR Multiprocessor Affinity Register + MTE + Memory Tagging Extension. An optional Armv8.5 extension that enables + hardware-assisted memory tagging. + OEN Owning Entity Number @@ -84,6 +95,9 @@ You can find additional definitions in the `Arm Glossary`_. PDD Platform Design Document + PAUTH + Pointer Authentication. An optional extension introduced in Armv8.3. + PMF Performance Measurement Framework @@ -138,6 +152,11 @@ You can find additional definitions in the `Arm Glossary`_. SPM Secure Partition Manager + SSBS + Speculative Store Bypass Safe. Introduced in Armv8.5, this configuration + bit can be set by software to allow or prevent the hardware from + performing speculative operations. + SVE Scalable Vector Extension @@ -168,6 +187,9 @@ You can find additional definitions in the `Arm Glossary`_. TZC TrustZone Controller + UBSAN + Undefined Behavior Sanitizer + UEFI Unified Extensible Firmware Interface @@ -177,4 +199,4 @@ You can find additional definitions in the `Arm Glossary`_. XLAT Translation (abbr.). For example, "XLAT table". -.. _`Arm Glossary`: https://developer.arm.com/support/arm-glossary \ No newline at end of file +.. _`Arm Glossary`: https://developer.arm.com/support/arm-glossary -- cgit v1.2.3 From 7a7fbb122ee3f66be81f34d58895939ef411e3f6 Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Wed, 31 Jul 2019 13:24:22 +0100 Subject: GIC-600: Fix power up sequence Arm's GIC-600 features a Power Register (GICR_PWRR), which needs to be programmed to enable redistributor operation. Section 3.6.1 in the GIC-600 TRM describes the power-up and power-down sequence in pseudo code, which deviates from the current TF-A implementation in drivers/arm/gic/v3/gic600.c. For powering on a redistributor, the pseudo code suggests to loop over the whole sequence (check for transition, write request bit) instead of just looping over the ready bit read as TF-A does in gic600_pwr_on(). This patch fixes GIC-600 power up sequence according to the TRM. Change-Id: I445c480e96ba356b69a2d8e5308ffe6c0a97f45b Signed-off-by: Alexei Fedorov --- drivers/arm/gic/v3/gic600.c | 65 +++++++++++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 26 deletions(-) diff --git a/drivers/arm/gic/v3/gic600.c b/drivers/arm/gic/v3/gic600.c index 9cb2ab25e..59652da63 100644 --- a/drivers/arm/gic/v3/gic600.c +++ b/drivers/arm/gic/v3/gic600.c @@ -1,14 +1,14 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /* - * Driver for GIC600-specific features. This driver only overrides APIs that are - * different to those generic ones in GICv3 driver. + * Driver for GIC-600 specific features. This driver only overrides + * APIs that are different to those generic ones in GICv3 driver. * - * GIC600 supports independently power-gating redistributor interface. + * GIC-600 supports independently power-gating redistributor interface. */ #include @@ -18,22 +18,28 @@ #include "gicv3_private.h" -/* GIC600-specific register offsets */ +/* GIC-600 specific register offsets */ #define GICR_PWRR 0x24 /* GICR_PWRR fields */ #define PWRR_RDPD_SHIFT 0 +#define PWRR_RDAG_SHIFT 1 #define PWRR_RDGPD_SHIFT 2 #define PWRR_RDGPO_SHIFT 3 +#define PWRR_RDPD (1 << PWRR_RDPD_SHIFT) +#define PWRR_RDAG (1 << PWRR_RDAG_SHIFT) #define PWRR_RDGPD (1 << PWRR_RDGPD_SHIFT) #define PWRR_RDGPO (1 << PWRR_RDGPO_SHIFT) -/* Values to write to GICR_PWRR register to power redistributor */ +/* + * Values to write to GICR_PWRR register to power redistributor + * for operating through the core (GICR_PWRR.RDAG = 0) + */ #define PWRR_ON (0 << PWRR_RDPD_SHIFT) #define PWRR_OFF (1 << PWRR_RDPD_SHIFT) -/* GIC600-specific accessor functions */ +/* GIC-600 specific accessor functions */ static void gicr_write_pwrr(uintptr_t base, unsigned int val) { mmio_write_32(base + GICR_PWRR, val); @@ -44,39 +50,46 @@ static uint32_t gicr_read_pwrr(uintptr_t base) return mmio_read_32(base + GICR_PWRR); } -static int gicr_group_powering_down(uint32_t pwrr) +static void gicr_wait_group_not_in_transit(uintptr_t base) { - /* - * Whether the redistributor group power down operation is in transit: - * i.e. it's intending to, but not finished yet. - */ - return ((pwrr & PWRR_RDGPD) && !(pwrr & PWRR_RDGPO)); + /* Check group not transitioning: RDGPD == RDGPO */ + while (((gicr_read_pwrr(base) & PWRR_RDGPD) >> PWRR_RDGPD_SHIFT) != + ((gicr_read_pwrr(base) & PWRR_RDGPO) >> PWRR_RDGPO_SHIFT)) + ; } static void gic600_pwr_on(uintptr_t base) { - /* Power on redistributor */ - gicr_write_pwrr(base, PWRR_ON); + do { /* Wait until group not transitioning */ + gicr_wait_group_not_in_transit(base); - /* Wait until the power on state is reflected */ - while (gicr_read_pwrr(base) & PWRR_RDGPO) - ; + /* Power on redistributor */ + gicr_write_pwrr(base, PWRR_ON); + + /* + * Wait until the power on state is reflected. + * If RDPD == 0 then powered on. + */ + } while ((gicr_read_pwrr(base) & PWRR_RDPD) != PWRR_ON); } static void gic600_pwr_off(uintptr_t base) { + /* Wait until group not transitioning */ + gicr_wait_group_not_in_transit(base); + /* Power off redistributor */ gicr_write_pwrr(base, PWRR_OFF); /* * If this is the last man, turning this redistributor frame off will - * result in the group itself being powered off. In that case, wait as - * long as it's in transition, or has aborted the transition altogether - * for any reason. + * result in the group itself being powered off and RDGPD = 1. + * In that case, wait as long as it's in transition, or has aborted + * the transition altogether for any reason. */ - if (gicr_read_pwrr(base) & PWRR_RDGPD) { - while (gicr_group_powering_down(gicr_read_pwrr(base))) - ; + if ((gicr_read_pwrr(base) & PWRR_RDGPD) != 0) { + /* Wait until group not transitioning */ + gicr_wait_group_not_in_transit(base); } } @@ -91,7 +104,7 @@ void gicv3_distif_post_restore(unsigned int proc_num) } /* - * Power off GIC600 redistributor + * Power off GIC-600 redistributor */ void gicv3_rdistif_off(unsigned int proc_num) { @@ -109,7 +122,7 @@ void gicv3_rdistif_off(unsigned int proc_num) } /* - * Power on GIC600 redistributor + * Power on GIC-600 redistributor */ void gicv3_rdistif_on(unsigned int proc_num) { -- cgit v1.2.3 From e2b6a9ced9be909306ecf445aee621e5113ac1fd Mon Sep 17 00:00:00 2001 From: Imre Kis Date: Fri, 15 Nov 2019 09:50:06 +0000 Subject: Fix multithreaded FVP power domain tree The number of levels in the topology has not changed but the count of processing elements on the lowest layer is now multiplied by the value of FVP_MAX_PE_PER_CPU. Signed-off-by: Imre Kis Change-Id: Ia1568a40ea33dbbbcdfab6c8ab6d19f4db0b8eb4 --- plat/arm/board/fvp/fvp_topology.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/plat/arm/board/fvp/fvp_topology.c b/plat/arm/board/fvp/fvp_topology.c index 9823fb3b3..24e79b4d4 100644 --- a/plat/arm/board/fvp/fvp_topology.c +++ b/plat/arm/board/fvp/fvp_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -36,7 +36,8 @@ const unsigned char *plat_get_power_domain_tree_desc(void) fvp_power_domain_tree_desc[1] = FVP_CLUSTER_COUNT; for (i = 0; i < FVP_CLUSTER_COUNT; i++) - fvp_power_domain_tree_desc[i + 2] = FVP_MAX_CPUS_PER_CLUSTER; + fvp_power_domain_tree_desc[i + 2] = + FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU; return fvp_power_domain_tree_desc; -- cgit v1.2.3 From d52331d01e0efae36e837af90887a8aed33ff604 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Fri, 15 Nov 2019 08:25:02 -0800 Subject: plat/rockchip: initialize reset and poweroff GPIOs with known invalid value And return NULL if we didn't get them in bl aux params otherwise reset and poweroff will be broken on platforms that do not have reset and poweroff GPIOs. Fixes: c1185ffde17c ("plat/rockchip: Switch to use new common BL aux parameter library") Signed-off-by: Vasily Khoruzhick Change-Id: Ic6cf6383d8f05d745e2c5d5e1b1df38514ea8429 --- plat/rockchip/common/params_setup.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c index 8c2e5e911..b2fd2011e 100644 --- a/plat/rockchip/common/params_setup.c +++ b/plat/rockchip/common/params_setup.c @@ -6,6 +6,7 @@ #include #include +#include #include #include @@ -21,8 +22,8 @@ #include #include -static struct bl_aux_gpio_info rst_gpio; -static struct bl_aux_gpio_info poweroff_gpio; +static struct bl_aux_gpio_info rst_gpio = { .index = UINT_MAX } ; +static struct bl_aux_gpio_info poweroff_gpio = { .index = UINT_MAX }; static struct bl_aux_gpio_info suspend_gpio[10]; uint32_t suspend_gpio_cnt; static struct bl_aux_rk_apio_info suspend_apio; @@ -174,11 +175,17 @@ uint32_t rockchip_get_uart_clock(void) struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void) { + if (rst_gpio.index == UINT_MAX) + return NULL; + return &rst_gpio; } struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void) { + if (poweroff_gpio.index == UINT_MAX) + return NULL; + return &poweroff_gpio; } -- cgit v1.2.3 From e7b390892d5d9ad4b1cf0dc127d72cbe81193c54 Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Fri, 11 Oct 2019 14:31:13 +0100 Subject: ROMLIB: Optimize memory layout when ROMLIB is used ROMLIB extract functions code from BL images to put them inside ROM. This has for effect to reduce the size of the BL images. This patch take this size reduction into consideration to optimize the memory layout of BL2. A new "PLAT_ARM_BL2_ROMLIB_OPTIMIZATION" macro is defined and used to reduce "PLAT_ARM_MAX_BL2_SIZE". This allows to remove the gap between BL1 and BL2 when ROMLIB is used and provides more room for BL31. The current memory gain is 0x6000 for fvp and 0x8000 for juno. Change-Id: I71c2c2c63b57bce5b22a125efaefc486ff3e87be Signed-off-by: Louis Mayencourt --- plat/arm/board/fvp/include/platform_def.h | 6 ++++-- plat/arm/board/juno/include/platform_def.h | 10 ++++++---- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 4f2627704..98dd0a97f 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -94,9 +94,11 @@ #if USE_ROMLIB #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) +#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000) #else #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) +#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) #endif /* @@ -104,9 +106,9 @@ * little space for growth. */ #if TRUSTED_BOARD_BOOT -# define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) #else -# define PLAT_ARM_MAX_BL2_SIZE UL(0x11000) +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION) #endif /* diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 83aeeb4bd..16bb33d7e 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -60,9 +60,11 @@ #if USE_ROMLIB #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) +#define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) #else #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) +#define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) #endif /* @@ -127,14 +129,14 @@ */ #if TRUSTED_BOARD_BOOT #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA -# define PLAT_ARM_MAX_BL2_SIZE UL(0x1F000) +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION) #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA -# define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) #else -# define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) #endif #else -# define PLAT_ARM_MAX_BL2_SIZE UL(0xF000) +# define PLAT_ARM_MAX_BL2_SIZE (UL(0xF000) - JUNO_BL2_ROMLIB_OPTIMIZATION) #endif /* -- cgit v1.2.3 From 4685b64fc34b3fd23c5d942aeac87fe1ece744e1 Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Fri, 11 Oct 2019 15:27:01 +0100 Subject: DOC: Update ROMLIB page with memory impact info Complete the Library at ROM documentation with information regarding the memory impact of the feature. Change-Id: I5a10620a8e94f123021bb19523a36d558b330deb Signed-off-by: Louis Mayencourt --- docs/components/romlib-design.rst | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/docs/components/romlib-design.rst b/docs/components/romlib-design.rst index d8bc89cea..e0a028e46 100644 --- a/docs/components/romlib-design.rst +++ b/docs/components/romlib-design.rst @@ -111,6 +111,21 @@ The calling sequence for a patched function is as follows: BL image --> function +Memory impact +~~~~~~~~~~~~~ + +Using library at ROM will modify the memory layout of the BL images: +- The ROM library needs a page aligned RAM section to hold the RW data. This + section is defined by the ROMLIB_RW_BASE and ROMLIB_RW_END macros. + On Arm platforms a section of 1 page (0x1000) is allocated at the top of SRAM. + This will have for effect to shift down all the BL images by 1 page. +- Depending on the functions moved to the ROM library, the size of the BL images + will be reduced. + For example: moving MbedTLS function into the ROM library reduces BL1 and + BL2, but not BL31. +- This change in BL images size can be taken into consideration to optimize the + memory layout when defining the BLx_BASE macros. + Build library at ROM ~~~~~~~~~~~~~~~~~~~~~ -- cgit v1.2.3 From ac42635123b5efd89f4bb04f67ea43c7d2926d82 Mon Sep 17 00:00:00 2001 From: Max Shvetsov Date: Tue, 19 Nov 2019 11:01:26 +0000 Subject: GIC-600: Fix include ordering according to the coding style Change-Id: Ia120bcaacea3a462ab78db13f84ed23493033601 Signed-off-by: Max Shvetsov --- drivers/arm/gic/v3/gic600_multichip.c | 6 +++--- plat/arm/board/n1sdp/n1sdp_bl31_setup.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/arm/gic/v3/gic600_multichip.c b/drivers/arm/gic/v3/gic600_multichip.c index c62c3f5dd..ca7c43bf9 100644 --- a/drivers/arm/gic/v3/gic600_multichip.c +++ b/drivers/arm/gic/v3/gic600_multichip.c @@ -9,13 +9,13 @@ */ #include -#include -#include +#include #include +#include -#include "gic600_multichip_private.h" #include "../common/gic_common_private.h" +#include "gic600_multichip_private.h" #warning "GIC-600 Multichip driver is currently experimental and the API may change in future." diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c index 4f158ee4d..b150b8959 100644 --- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c +++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c @@ -6,11 +6,11 @@ #include +#include #include #include #include #include -#include #include #include #include -- cgit v1.2.3 From 9ab81b5ea9811b673668c43289bb48c85c4f9659 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Wed, 31 Jul 2019 11:36:41 +0100 Subject: Refactor the warning flags This patch keeps the same warnings, and simply reorders them to keep all the warning options together in one place. Change-Id: Ibb655dcabc84f3af01a0d7f71f5af7e0479c2521 Signed-off-by: Justin Chadwell --- Makefile | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index 721246d51..534896a79 100644 --- a/Makefile +++ b/Makefile @@ -228,6 +228,13 @@ endif ASFLAGS_aarch32 = $(march32-directive) ASFLAGS_aarch64 = $(march64-directive) +# General warnings +WARNINGS := -Wall -Wmissing-include-dirs -Wunused \ + -Wdisabled-optimization -Wvla \ + -Wno-unused-parameter + +# Additional warnings +# Level 1 WARNING1 := -Wextra WARNING1 += -Wmissing-declarations WARNING1 += -Wmissing-format-attribute @@ -253,17 +260,14 @@ WARNING3 += -Wredundant-decls WARNING3 += -Wswitch-default ifeq (${W},1) -WARNINGS := $(WARNING1) +WARNINGS += $(WARNING1) else ifeq (${W},2) -WARNINGS := $(WARNING1) $(WARNING2) +WARNINGS += $(WARNING1) $(WARNING2) else ifeq (${W},3) -WARNINGS := $(WARNING1) $(WARNING2) $(WARNING3) +WARNINGS += $(WARNING1) $(WARNING2) $(WARNING3) endif -WARNINGS += -Wunused -Wno-unused-parameter \ - -Wdisabled-optimization \ - -Wvla - +# Compiler specific warnings ifeq ($(findstring clang,$(notdir $(CC))),) # not using clang WARNINGS += -Wunused-but-set-variable \ @@ -279,12 +283,12 @@ ifneq (${E},0) ERRORS := -Werror endif -CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \ - -Wmissing-include-dirs $(ERRORS) $(WARNINGS) +CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \ + $(ERRORS) $(WARNINGS) ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \ -ffreestanding -Wa,--fatal-warnings TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ - -ffreestanding -fno-builtin -Wall -std=gnu99 \ + -ffreestanding -fno-builtin -std=gnu99 \ -Os -ffunction-sections -fdata-sections ifeq (${SANITIZE_UB},on) -- cgit v1.2.3 From b8baa9346aaad24f8da48e408e0dbd5e65619905 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Wed, 31 Jul 2019 11:44:42 +0100 Subject: Remove unnecessary warning options Both -Wmissing-field-initializers and -Wsign-compare are both covered by -Wextra which is enabled at W=1 anyway. Therefore, the explicit options are not required. Change-Id: I2e7d95b5fc14af7c70895859a7ebbeac5bc0d2a4 Signed-off-by: Justin Chadwell --- Makefile | 2 -- docs/process/security-hardening.rst | 3 +-- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 534896a79..65d46293e 100644 --- a/Makefile +++ b/Makefile @@ -247,8 +247,6 @@ WARNING2 += -Wcast-align WARNING2 += -Wnested-externs WARNING2 += -Wshadow WARNING2 += -Wlogical-op -WARNING2 += -Wmissing-field-initializers -WARNING2 += -Wsign-compare WARNING3 := -Wbad-function-cast WARNING3 += -Wcast-qual diff --git a/docs/process/security-hardening.rst b/docs/process/security-hardening.rst index 1a5524fd8..646b7a117 100644 --- a/docs/process/security-hardening.rst +++ b/docs/process/security-hardening.rst @@ -37,8 +37,7 @@ Several build options can be used to check for security issues. Refer to the - W=2 Adds ``Waggregate-return``, ``Wcast-align``, ``Wnested-externs``, - ``Wshadow``, ``Wlogical-op``, ``Wmissing-field-initializers`` and - ``Wsign-compare``. + ``Wshadow``, ``Wlogical-op``. - W=3 -- cgit v1.2.3 From b7f6525db642d533327403ff8130eb91190f2e98 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Tue, 17 Sep 2019 15:21:50 +0100 Subject: Enable -Wshadow always Variable shadowing is, according to the C standard, permitted and valid behaviour. However, allowing a local variable to take the same name as a global one can cause confusion and can make refactoring and bug hunting more difficult. This patch moves -Wshadow from WARNING2 into the general warning group so it is always used. It also fixes all warnings that this introduces by simply renaming the local variable to a new name Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e Signed-off-by: Justin Chadwell --- Makefile | 4 ++-- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 24 +++++++++---------- plat/layerscape/common/ns_access.c | 12 +++++----- plat/mediatek/mt8173/drivers/spm/spm_suspend.c | 6 ++--- plat/renesas/rcar/bl2_plat_setup.c | 28 +++++++++++----------- plat/rockchip/rk3399/drivers/dram/dfs.c | 6 ++--- services/std_svc/spm_mm/spm_main.c | 10 ++++---- 7 files changed, 45 insertions(+), 45 deletions(-) diff --git a/Makefile b/Makefile index 65d46293e..05820619e 100644 --- a/Makefile +++ b/Makefile @@ -230,7 +230,7 @@ ASFLAGS_aarch64 = $(march64-directive) # General warnings WARNINGS := -Wall -Wmissing-include-dirs -Wunused \ - -Wdisabled-optimization -Wvla \ + -Wdisabled-optimization -Wvla -Wshadow \ -Wno-unused-parameter # Additional warnings @@ -242,10 +242,10 @@ WARNING1 += -Wmissing-prototypes WARNING1 += -Wold-style-definition WARNING1 += -Wunused-const-variable +# Level 2 WARNING2 := -Waggregate-return WARNING2 += -Wcast-align WARNING2 += -Wnested-externs -WARNING2 += -Wshadow WARNING2 += -Wlogical-op WARNING3 := -Wbad-function-cast diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index 9f7c95490..1d6e83a2c 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -254,10 +254,10 @@ static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); static uint32_t ddrphy_regif_chk(void); static inline void ddrphy_regif_idle(void); -static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps, +static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, uint16_t cyc); -static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, - uint16_t *js2); +static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, + uint16_t *_js2); static int16_t _f_scale_adj(int16_t ps); static void ddrtbl_load(void); static void ddr_config_sub(void); @@ -991,15 +991,15 @@ static uint16_t js2[JS2_CNT]; static uint8_t RL; static uint8_t WL; -static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps, +static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, uint16_t cyc) { uint32_t tmp; uint32_t div; - tmp = (((uint32_t)(ps) + 9) / 10) * ddr_mbps; - div = tmp / (200000 * ddr_mbpsdiv); - if (tmp != (div * 200000 * ddr_mbpsdiv)) + tmp = (((uint32_t)(ps) + 9) / 10) * _ddr_mbps; + div = tmp / (200000 * _ddr_mbpsdiv); + if (tmp != (div * 200000 * _ddr_mbpsdiv)) div = div + 1; if (div > cyc) @@ -1007,19 +1007,19 @@ static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps, return cyc; } -static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, - uint16_t *js2) +static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, + uint16_t *_js2) { int i; for (i = 0; i < JS2_TBLCNT; i++) { - js2[i] = _f_scale(ddr_mbps, ddr_mbpsdiv, + _js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv, 1UL * jedec_spec2[JS2_DERATE][i].ps, jedec_spec2[JS2_DERATE][i].cyc); } - js2[js2_trcpb] = js2[js2_tras] + js2[js2_trppb]; - js2[js2_trcab] = js2[js2_tras] + js2[js2_trpab]; + _js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb]; + _js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab]; } /* scaler for DELAY value */ diff --git a/plat/layerscape/common/ns_access.c b/plat/layerscape/common/ns_access.c index b84fdbd7e..9717c7281 100644 --- a/plat/layerscape/common/ns_access.c +++ b/plat/layerscape/common/ns_access.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,7 @@ #include "ns_access.h" -static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +static void enable_devices_ns_access(struct csu_ns_dev *_ns_dev, uint32_t num) { uint32_t *base = (uint32_t *)CONFIG_SYS_FSL_CSU_ADDR; uint32_t *reg; @@ -21,14 +21,14 @@ static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) int i; for (i = 0; i < num; i++) { - reg = base + ns_dev[i].ind / 2; + reg = base + _ns_dev[i].ind / 2; val = be32toh(mmio_read_32((uintptr_t)reg)); - if (ns_dev[i].ind % 2 == 0) { + if (_ns_dev[i].ind % 2 == 0) { val &= 0x0000ffff; - val |= ns_dev[i].val << 16; + val |= _ns_dev[i].val << 16; } else { val &= 0xffff0000; - val |= ns_dev[i].val; + val |= _ns_dev[i].val; } mmio_write_32((uintptr_t)reg, htobe32(val)); } diff --git a/plat/mediatek/mt8173/drivers/spm/spm_suspend.c b/plat/mediatek/mt8173/drivers/spm/spm_suspend.c index 5021695db..838455d8c 100644 --- a/plat/mediatek/mt8173/drivers/spm/spm_suspend.c +++ b/plat/mediatek/mt8173/drivers/spm/spm_suspend.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -239,13 +239,13 @@ static struct pwr_ctrl spm_ctrl = { /* * go_to_sleep_before_wfi() - trigger SPM to enter suspend scenario */ -static void go_to_sleep_before_wfi(const unsigned int spm_flags) +static void go_to_sleep_before_wfi(const unsigned int flags_spm) { struct pwr_ctrl *pwrctrl; pwrctrl = &spm_ctrl; - set_pwrctrl_pcm_flags(pwrctrl, spm_flags); + set_pwrctrl_pcm_flags(pwrctrl, flags_spm); spm_set_sysclk_settle(); diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index ebe6dddc9..b4762f330 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -408,7 +408,7 @@ struct meminfo *bl2_plat_sec_mem_layout(void) return &bl2_tzram_layout; } -static void bl2_populate_compatible_string(void *fdt) +static void bl2_populate_compatible_string(void *dt) { uint32_t board_type; uint32_t board_rev; @@ -419,32 +419,32 @@ static void bl2_populate_compatible_string(void *fdt) rcar_get_board_type(&board_type, &board_rev); switch (board_type) { case BOARD_SALVATOR_X: - ret = fdt_setprop_string(fdt, 0, "compatible", + ret = fdt_setprop_string(dt, 0, "compatible", "renesas,salvator-x"); break; case BOARD_SALVATOR_XS: - ret = fdt_setprop_string(fdt, 0, "compatible", + ret = fdt_setprop_string(dt, 0, "compatible", "renesas,salvator-xs"); break; case BOARD_STARTER_KIT: - ret = fdt_setprop_string(fdt, 0, "compatible", + ret = fdt_setprop_string(dt, 0, "compatible", "renesas,m3ulcb"); break; case BOARD_STARTER_KIT_PRE: - ret = fdt_setprop_string(fdt, 0, "compatible", + ret = fdt_setprop_string(dt, 0, "compatible", "renesas,h3ulcb"); break; case BOARD_EAGLE: - ret = fdt_setprop_string(fdt, 0, "compatible", + ret = fdt_setprop_string(dt, 0, "compatible", "renesas,eagle"); break; case BOARD_EBISU: case BOARD_EBISU_4D: - ret = fdt_setprop_string(fdt, 0, "compatible", + ret = fdt_setprop_string(dt, 0, "compatible", "renesas,ebisu"); break; case BOARD_DRAAK: - ret = fdt_setprop_string(fdt, 0, "compatible", + ret = fdt_setprop_string(dt, 0, "compatible", "renesas,draak"); break; default: @@ -460,27 +460,27 @@ static void bl2_populate_compatible_string(void *fdt) reg = mmio_read_32(RCAR_PRR); switch (reg & PRR_PRODUCT_MASK) { case PRR_PRODUCT_H3: - ret = fdt_appendprop_string(fdt, 0, "compatible", + ret = fdt_appendprop_string(dt, 0, "compatible", "renesas,r8a7795"); break; case PRR_PRODUCT_M3: - ret = fdt_appendprop_string(fdt, 0, "compatible", + ret = fdt_appendprop_string(dt, 0, "compatible", "renesas,r8a7796"); break; case PRR_PRODUCT_M3N: - ret = fdt_appendprop_string(fdt, 0, "compatible", + ret = fdt_appendprop_string(dt, 0, "compatible", "renesas,r8a77965"); break; case PRR_PRODUCT_V3M: - ret = fdt_appendprop_string(fdt, 0, "compatible", + ret = fdt_appendprop_string(dt, 0, "compatible", "renesas,r8a77970"); break; case PRR_PRODUCT_E3: - ret = fdt_appendprop_string(fdt, 0, "compatible", + ret = fdt_appendprop_string(dt, 0, "compatible", "renesas,r8a77990"); break; case PRR_PRODUCT_D3: - ret = fdt_appendprop_string(fdt, 0, "compatible", + ret = fdt_appendprop_string(dt, 0, "compatible", "renesas,r8a77995"); break; default: diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c index 3b627d287..816372bfc 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.c +++ b/plat/rockchip/rk3399/drivers/dram/dfs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -78,10 +78,10 @@ static struct rk3399_sdram_default_config lpddr4_default_config = { .zqcsi = 0 }; -static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, +static uint32_t get_cs_die_capability(struct rk3399_sdram_params *ram_config, uint8_t channel, uint8_t cs) { - struct rk3399_sdram_channel *ch = &sdram_config->ch[channel]; + struct rk3399_sdram_channel *ch = &ram_config->ch[channel]; uint32_t bandwidth; uint32_t die_bandwidth; uint32_t die; diff --git a/services/std_svc/spm_mm/spm_main.c b/services/std_svc/spm_mm/spm_main.c index 7525763b1..706b69d9f 100644 --- a/services/std_svc/spm_mm/spm_main.c +++ b/services/std_svc/spm_mm/spm_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -86,14 +86,14 @@ int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to) * This function takes an SP context pointer and performs a synchronous entry * into it. ******************************************************************************/ -static uint64_t spm_sp_synchronous_entry(sp_context_t *sp_ctx) +static uint64_t spm_sp_synchronous_entry(sp_context_t *ctx) { uint64_t rc; - assert(sp_ctx != NULL); + assert(ctx != NULL); /* Assign the context of the SP to this CPU */ - cm_set_context(&(sp_ctx->cpu_ctx), SECURE); + cm_set_context(&(ctx->cpu_ctx), SECURE); /* Restore the context assigned above */ cm_el1_sysregs_context_restore(SECURE); @@ -104,7 +104,7 @@ static uint64_t spm_sp_synchronous_entry(sp_context_t *sp_ctx) dsbish(); /* Enter Secure Partition */ - rc = spm_secure_partition_enter(&sp_ctx->c_rt_ctx); + rc = spm_secure_partition_enter(&ctx->c_rt_ctx); /* Save secure state */ cm_el1_sysregs_context_save(SECURE); -- cgit v1.2.3 From d7b4cd4111ab4cfde60f693a789a290870c02035 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Wed, 18 Sep 2019 14:13:42 +0100 Subject: Enable -Wlogical-op always -Wlogical-op prevents common errors with using numerical constants where a boolean one is expected as well as when the operands of a logical operator are the same. While these are perfectly valid behavior, they can be a sign that something is slightly off. This patch adds this warning to gcc and it's closest equivalent to clang, while also fixing any warnings that enabling them causes. Change-Id: Iabadfc1e6ee0c44eef6685a23b0aed8abef8ce89 Signed-off-by: Justin Chadwell --- Makefile | 11 +++++------ drivers/mentor/i2c/mi2cv.c | 4 ++-- plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c | 2 +- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index 05820619e..d634b336b 100644 --- a/Makefile +++ b/Makefile @@ -246,7 +246,6 @@ WARNING1 += -Wunused-const-variable WARNING2 := -Waggregate-return WARNING2 += -Wcast-align WARNING2 += -Wnested-externs -WARNING2 += -Wlogical-op WARNING3 := -Wbad-function-cast WARNING3 += -Wcast-qual @@ -268,13 +267,13 @@ endif # Compiler specific warnings ifeq ($(findstring clang,$(notdir $(CC))),) # not using clang -WARNINGS += -Wunused-but-set-variable \ - -Wmaybe-uninitialized \ - -Wpacked-bitfield-compat \ - -Wshift-overflow=2 +WARNINGS += -Wunused-but-set-variable -Wmaybe-uninitialized \ + -Wpacked-bitfield-compat -Wshift-overflow=2 \ + -Wlogical-op else # using clang -WARNINGS += -Wshift-overflow -Wshift-sign-overflow +WARNINGS += -Wshift-overflow -Wshift-sign-overflow \ + -Wlogical-op-parentheses endif ifneq (${E},0) diff --git a/drivers/mentor/i2c/mi2cv.c b/drivers/mentor/i2c/mi2cv.c index 1cdcf7478..b0270c955 100644 --- a/drivers/mentor/i2c/mi2cv.c +++ b/drivers/mentor/i2c/mi2cv.c @@ -81,14 +81,14 @@ static void mentor_i2c_interrupt_clear(void) udelay(1); } -static int mentor_i2c_interrupt_get(void) +static bool mentor_i2c_interrupt_get(void) { uint32_t reg; /* get the interrupt flag bit */ reg = mmio_read_32((uintptr_t)&base->control); reg &= I2C_CONTROL_IFLG; - return reg && I2C_CONTROL_IFLG; + return (reg != 0U); } static int mentor_i2c_wait_interrupt(void) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c index 44acb4bd5..60e80d907 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c @@ -58,7 +58,7 @@ static enum pm_ret_status pm_ioctl_set_rpu_oper_mode(unsigned int mode) { unsigned int val; - if (mmio_read_32(CRL_APB_RST_LPD_TOP) && CRL_APB_RPU_AMBA_RESET) + if (mmio_read_32(CRL_APB_RST_LPD_TOP) & CRL_APB_RPU_AMBA_RESET) return PM_RET_ERROR_ACCESS; val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL); -- cgit v1.2.3 From 4450a5189435202a35ae77904f200a94457cdeb4 Mon Sep 17 00:00:00 2001 From: kenny liang Date: Fri, 4 Oct 2019 10:47:11 +0800 Subject: mediatek: mt8183: refine GIC driver for low power scenarios Implement rdist save/resore functions to support low power scenarios. Signed-off-by: kenny liang Change-Id: I9ddc077a04f843275fbe2e868cdd0bd00d622de7 --- plat/mediatek/mt8183/include/mt_gic_v3.h | 10 +++- plat/mediatek/mt8183/plat_mt_gic.c | 98 ++++++++++++++++++++++++-------- plat/mediatek/mt8183/plat_pm.c | 32 +++++++++-- 3 files changed, 106 insertions(+), 34 deletions(-) diff --git a/plat/mediatek/mt8183/include/mt_gic_v3.h b/plat/mediatek/mt8183/include/mt_gic_v3.h index 9d78ddb10..b6fc29bbd 100644 --- a/plat/mediatek/mt8183/include/mt_gic_v3.h +++ b/plat/mediatek/mt8183/include/mt_gic_v3.h @@ -15,15 +15,19 @@ #define GIC500_ACTIVE_CPU_SHIFT 16 #define GIC500_ACTIVE_CPU_MASK (0xff << GIC500_ACTIVE_CPU_SHIFT) +#define NR_INT_POL_CTL 20 + void mt_gic_driver_init(void); void mt_gic_init(void); void mt_gic_set_pending(uint32_t irq); uint32_t mt_gic_get_pending(uint32_t irq); void mt_gic_cpuif_enable(void); void mt_gic_cpuif_disable(void); -void mt_gic_pcpu_init(void); -void mt_gic_irq_save(void); -void mt_gic_irq_restore(void); +void mt_gic_rdistif_init(void); +void mt_gic_distif_save(void); +void mt_gic_distif_restore(void); +void mt_gic_rdistif_save(void); +void mt_gic_rdistif_restore(void); void mt_gic_sync_dcm_enable(void); void mt_gic_sync_dcm_disable(void); diff --git a/plat/mediatek/mt8183/plat_mt_gic.c b/plat/mediatek/mt8183/plat_mt_gic.c index ccb72be42..35792b2e1 100644 --- a/plat/mediatek/mt8183/plat_mt_gic.c +++ b/plat/mediatek/mt8183/plat_mt_gic.c @@ -11,18 +11,17 @@ #include #include #include +#include "../drivers/arm/gic/v3/gicv3_private.h" #include "plat_private.h" #include #include #include #include -#define NR_INT_POL_CTL 20 - uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; +static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT]; /* we save and restore the GICv3 context on system suspend */ -gicv3_redist_ctx_t rdist_ctx; gicv3_dist_ctx_t dist_ctx; static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr) @@ -38,6 +37,16 @@ gicv3_driver_data_t mt_gicv3_data = { .mpidr_to_core_pos = mt_mpidr_to_core_pos, }; +struct gic_chip_data { + unsigned int saved_group; + unsigned int saved_enable; + unsigned int saved_conf0; + unsigned int saved_conf1; + unsigned int saved_grpmod; +}; + +static struct gic_chip_data gic_data; + void clear_sec_pol_ctl_en(void) { unsigned int i; @@ -54,15 +63,6 @@ void mt_gic_driver_init(void) gicv3_driver_init(&mt_gicv3_data); } -void mt_gic_init(void) -{ - gicv3_distif_init(); - gicv3_rdistif_init(plat_my_core_pos()); - gicv3_cpuif_enable(plat_my_core_pos()); - - clear_sec_pol_ctl_en(); -} - void mt_gic_set_pending(uint32_t irq) { gicv3_set_interrupt_pending(irq, plat_my_core_pos()); @@ -78,35 +78,83 @@ void mt_gic_cpuif_disable(void) gicv3_cpuif_disable(plat_my_core_pos()); } -void mt_gic_pcpu_init(void) +void mt_gic_rdistif_init(void) { - gicv3_rdistif_init(plat_my_core_pos()); + unsigned int proc_num; + unsigned int index; + uintptr_t gicr_base; + + proc_num = plat_my_core_pos(); + gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + + /* set all SGI/PPI as non-secure GROUP1 by default */ + mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U); + mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0); + + /* setup the default PPI/SGI priorities */ + for (index = 0; index < TOTAL_PCPU_INTR_NUM; index += 4U) + gicr_write_ipriorityr(gicr_base, index, + GICD_IPRIORITYR_DEF_VAL); } -void mt_gic_irq_save(void) +void mt_gic_distif_save(void) { - gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx); gicv3_distif_save(&dist_ctx); } -void mt_gic_irq_restore(void) +void mt_gic_distif_restore(void) { gicv3_distif_init_restore(&dist_ctx); - gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx); } -void mt_gic_sync_dcm_enable(void) +void mt_gic_rdistif_save(void) { - unsigned int val = mmio_read_32(GIC_SYNC_DCM); + unsigned int proc_num; + uintptr_t gicr_base; + + proc_num = plat_my_core_pos(); + gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; - val &= ~GIC_SYNC_DCM_MASK; - mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_ON); + gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0); + gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0); + gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0); + gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1); + gic_data.saved_grpmod = mmio_read_32(gicr_base + GICR_IGRPMODR0); + + rdist_has_saved[proc_num] = 1; +} + +void mt_gic_rdistif_restore(void) +{ + unsigned int proc_num; + uintptr_t gicr_base; + + proc_num = plat_my_core_pos(); + if (rdist_has_saved[proc_num] == 1) { + gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group); + mmio_write_32(gicr_base + GICR_ISENABLER0, gic_data.saved_enable); + mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0); + mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1); + mmio_write_32(gicr_base + GICR_IGRPMODR0, gic_data.saved_grpmod); + } +} + +void mt_gic_sync_dcm_enable(void) +{ + mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_ON); } void mt_gic_sync_dcm_disable(void) { - unsigned int val = mmio_read_32(GIC_SYNC_DCM); + mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_OFF); +} + +void mt_gic_init(void) +{ + gicv3_distif_init(); + gicv3_cpuif_enable(plat_my_core_pos()); + mt_gic_rdistif_init(); - val &= ~GIC_SYNC_DCM_MASK; - mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_OFF); + clear_sec_pol_ctl_en(); } diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c index 555b3895c..efa30f611 100644 --- a/plat/mediatek/mt8183/plat_pm.c +++ b/plat/mediatek/mt8183/plat_pm.c @@ -152,6 +152,21 @@ static bool clst_single_on(int cluster, int cpu) return !(on_stat & (cpu_mask[cluster] & ~BIT(my_idx))); } +static void plat_cpu_pwrdwn_common(void) +{ + /* Prevent interrupts from spuriously waking up this cpu */ + mt_gic_rdistif_save(); + mt_gic_cpuif_disable(); +} + +static void plat_cpu_pwron_common(void) +{ + /* Enable the gic cpu interface */ + mt_gic_cpuif_enable(); + mt_gic_rdistif_init(); + mt_gic_rdistif_restore(); +} + static void plat_cluster_pwrdwn_common(uint64_t mpidr, int cluster) { if (cluster > 0) @@ -312,7 +327,7 @@ static void plat_mtk_power_domain_off(const psci_power_state_t *state) bool cluster_off = (HP_CLUSTER_OFF && afflvl1 && clst_single_on(cluster, cpu)); - mt_gic_cpuif_disable(); + plat_cpu_pwrdwn_common(); if (cluster_off) plat_cluster_pwrdwn_common(mpidr, cluster); @@ -332,8 +347,7 @@ static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state) if (afflvl1) plat_cluster_pwron_common(mpidr, cluster); - mt_gic_pcpu_init(); - mt_gic_cpuif_enable(); + plat_cpu_pwron_common(); hotplug_ctrl_cpu_on_finish(cluster, cpu); } @@ -352,8 +366,8 @@ static void plat_mtk_power_domain_suspend(const psci_power_state_t *state) mcucfg_init_archstate(cluster, cpu, 1); mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); - mt_gic_cpuif_disable(); - mt_gic_irq_save(); + plat_cpu_pwrdwn_common(); + plat_dcm_mcsi_a_backup(); if (cluster_off || afflvl2) @@ -376,6 +390,8 @@ static void plat_mtk_power_domain_suspend(const psci_power_state_t *state) if (MCDI_SSPM) while (sspm_ipi_recv_non_blocking(IPI_ID_SUSPEND, d, l)) ; + + mt_gic_distif_save(); } else { mcdi_ctrl_cluster_cpu_off(cluster, cpu, cluster_off); } @@ -394,7 +410,9 @@ static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state uint32_t l = sizeof(spm_d) / sizeof(uint32_t); mt_gic_init(); - mt_gic_irq_restore(); + mt_gic_distif_restore(); + mt_gic_rdistif_restore(); + mmio_write_32(EMI_WFIFO, 0xf); if (MCDI_SSPM) @@ -407,6 +425,8 @@ static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state ; mcdi_ctrl_resume(); + } else { + plat_cpu_pwron_common(); } plat_cluster_pwron_common(mpidr, cluster); -- cgit v1.2.3 From c6e0a64d83bed2bb7b9a2adefabc54402b460aa8 Mon Sep 17 00:00:00 2001 From: James Liao Date: Thu, 31 Oct 2019 14:19:44 +0800 Subject: mediatek: mt8183: Fix AARCH64 init fail on CPU0 CPU0 is default on, so it doesn't need to run pwr_domain_on() at boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may encounter race condition with other CPUs. Now AARCH64 will be set with cluster on in pwr_domain_on(), and all CPUs on this cluster will be set together. It doesn't need to set AARCH64 again in pwr_domain_suspend(), so the race condition can be avoided. Change-Id: I5693ad56e4901f82badb0fc0d8d13e4c9acfe648 Signed-off-by: James Liao --- plat/mediatek/mt8183/plat_pm.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c index efa30f611..2358ec6c4 100644 --- a/plat/mediatek/mt8183/plat_pm.c +++ b/plat/mediatek/mt8183/plat_pm.c @@ -304,13 +304,19 @@ static int plat_mtk_power_domain_on(unsigned long mpidr) { int cpu = MPIDR_AFFLVL0_VAL(mpidr); int cluster = MPIDR_AFFLVL1_VAL(mpidr); + int clst_pwr = spm_get_cluster_powerstate(cluster); + unsigned int i; mcdi_ctrl_before_hotplug_on(cluster, cpu); hotplug_ctrl_cluster_on(cluster, cpu); - /* init cpu reset arch as AARCH64 */ - mcucfg_init_archstate(cluster, cpu, 1); - mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); + if (clst_pwr == 0) { + /* init cpu reset arch as AARCH64 of cluster */ + for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) { + mcucfg_init_archstate(cluster, i, 1); + mcucfg_set_bootaddr(cluster, i, secure_entrypoint); + } + } hotplug_ctrl_cpu_on(cluster, cpu); @@ -362,10 +368,6 @@ static void plat_mtk_power_domain_suspend(const psci_power_state_t *state) bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF); bool cluster_off = MCDI_C2 && afflvl1 && clst_single_pwr(cluster, cpu); - /* init cpu reset arch as AARCH64 */ - mcucfg_init_archstate(cluster, cpu, 1); - mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); - plat_cpu_pwrdwn_common(); plat_dcm_mcsi_a_backup(); @@ -561,15 +563,23 @@ static const plat_psci_ops_t plat_plat_pm_ops = { .system_off = plat_mtk_system_off, .system_reset = plat_mtk_system_reset, .validate_power_state = plat_mtk_validate_power_state, - .get_sys_suspend_power_state = plat_mtk_get_sys_suspend_power_state, + .get_sys_suspend_power_state = plat_mtk_get_sys_suspend_power_state }; int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { + unsigned int i; + *psci_ops = &plat_plat_pm_ops; secure_entrypoint = sec_entrypoint; + /* Init cpu reset arch as AARCH64 of cluster 0 */ + for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) { + mcucfg_init_archstate(0, i, 1); + mcucfg_set_bootaddr(0, i, secure_entrypoint); + } + if (!check_mcdi_ctl_stat()) { HP_SSPM_CTRL = false; MCDI_SSPM = false; -- cgit v1.2.3 From ea698c1ea4395d0d4a225bb7159442b5d0aa5328 Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Mon, 14 Oct 2019 14:09:40 +0100 Subject: tools: Add show_memory script show_memory is a simple tools that parse the blx.map files and print a representation of the memory layout for the latest build. This representation is based on standard symbols present on the map files as: __TEXT_START/END__, __RODATA_START/END__, __STACKS_START/END__ , etc.. Change-Id: Iba3e301a1a9fee9a35abf1afdb69093617d33929 Signed-off-by: Louis Mayencourt --- tools/memory/print_memory_map.py | 68 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100755 tools/memory/print_memory_map.py diff --git a/tools/memory/print_memory_map.py b/tools/memory/print_memory_map.py new file mode 100755 index 000000000..35cccd38c --- /dev/null +++ b/tools/memory/print_memory_map.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python3 +# +# Copyright (c) 2019, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +import re +import os +import sys +import operator + +# List of folder/map to parse +bl_images = ['bl1', 'bl2', 'bl31'] + +# List of symbols to search for +blx_symbols = ['__BL1_RAM_START__', '__BL1_RAM_END__', + '__BL2_END__', + '__BL31_END__', + '__TEXT_START__', '__TEXT_END__', + '__RODATA_START__', '__RODATA_END__', + '__DATA_START__', '__DATA_END__', + '__STACKS_START__', '__STACKS_END__', + '__BSS_END', + ] + +# Regex to extract address from map file +address_pattern = re.compile(r"\b0x\w*") + +# List of found element: [address, symbol, file] +address_list = [] + +# Get the directory from command line or use a default one +if len(sys.argv) >= 2: + build_dir = sys.argv[1] +else: + build_dir = 'build/fvp/debug' + +# Extract all the required symbols from the map files +for image in bl_images: + file_path = os.path.join(build_dir, image, '{}.map'.format(image)) + if os.path.isfile(file_path): + with open (file_path, 'rt') as mapfile: + for line in mapfile: + for symbol in blx_symbols: + if line.find(symbol) > 0 and line.find("ASSERT") < 0: + # Extract address from line + match = address_pattern.search(line) + if match: + address_list.append([match.group(0), symbol, image]) + +# Sort by address +address_list.sort(key=operator.itemgetter(0)) + +# Generate memory view +print('{:-^87}'.format('Memory Map from: ' + build_dir)) +for address in reversed(address_list): + if "bl1" in address[2]: + print(address[0], '+{:-^20}+ |{:^20}| |{:^20}|'.format(address[1], '', '')) + elif "bl2" in address[2]: + print(address[0], '|{:^20}| +{:-^20}+ |{:^20}|'.format('', address[1], '')) + elif "bl31" in address[2]: + print(address[0], '|{:^20}| |{:^20}| +{:-^20}+'.format('', '', address[1])) + else: + print(address[0], '|{:^20}| |{:^20}| +{:-^20}+'.format('', '', address[1])) + +print('{:^20}{:_^20} {:_^20} {:_^20}'.format('', '', '', '')) +print('{:^20}{:^20} {:^20} {:^20}'.format('address', 'bl1', 'bl2', 'bl31')) -- cgit v1.2.3 From cfe83910f1d783a04c8d9e704d087413edf29724 Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Wed, 16 Oct 2019 14:30:51 +0100 Subject: Add memory_map tools as a target for Make Create a new "memmap" target for the Makefile, which prints a representation of the memory map for the build. The information are extracted from the .map files by the "print_memory_map.py" tools. Change-Id: Id5ebc7ce8a3a571c7ac4848be14657cf2fd711f4 Signed-off-by: Louis Mayencourt --- Makefile | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 721246d51..bcb2af182 100644 --- a/Makefile +++ b/Makefile @@ -623,6 +623,13 @@ SPTOOL ?= ${SPTOOLPATH}/sptool${BIN_EXT} # Variables for use with ROMLIB ROMLIBPATH ?= lib/romlib +# Variable for use with Python +PYTHON ?= python3 + +# Variables for use with PRINT_MEMORY_MAP +PRINT_MEMORY_MAP_PATH ?= tools/memory +PRINT_MEMORY_MAP ?= ${PRINT_MEMORY_MAP_PATH}/print_memory_map.py + ################################################################################ # Include BL specific makefiles ################################################################################ @@ -795,7 +802,7 @@ endif # Build targets ################################################################################ -.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip fwu_fip certtool dtbs +.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip fwu_fip certtool dtbs memmap .SUFFIXES: all: msg_start @@ -989,6 +996,10 @@ ${SPTOOL}: romlib.bin: libraries ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all +# Call print_memory_map tool +memmap: all + ${Q}${PYTHON} $(PRINT_MEMORY_MAP) $(BUILD_PLAT) + cscope: @echo " CSCOPE" ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files @@ -1028,6 +1039,7 @@ help: @echo " fiptool Build the Firmware Image Package (FIP) creation tool" @echo " sptool Build the Secure Partition Package creation tool" @echo " dtbs Build the Device Tree Blobs (if required for the platform)" + @echo " memmap Print the memory map of the built binaries" @echo "" @echo "Note: most build targets require PLAT to be set to a specific platform." @echo "" -- cgit v1.2.3 From c6dc85046c7beed1a8fe799125635f4db46945c9 Mon Sep 17 00:00:00 2001 From: Stefan Mavrodiev Date: Tue, 26 Nov 2019 09:29:04 +0200 Subject: allwinner: power: Add DLDO4 power rail A64-OLinuXino family boards (maybe others too) uses PG for USB vbus enable/disable. However PG is supplied by DLDO4, which is not present in the list of known regulators. This patch adds DLD04 to it. Signed-off-by: Stefan Mavrodiev Change-Id: I31d3bb3e0004ccf5b282d08b530ee44979da0466 --- plat/allwinner/sun50i_a64/sunxi_power.c | 1 + 1 file changed, 1 insertion(+) diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index 07a37167f..d48ff56dc 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -191,6 +191,7 @@ static const struct axp_regulator { {"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3}, {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4}, {"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5}, + {"dldo4", 700, 3300, 100, NO_SPLIT, 0x18, 0x12, 6}, {"fldo1", 700, 1450, 50, NO_SPLIT, 0x1c, 0x13, 2}, {} }; -- cgit v1.2.3 From ab4df50c23b92cd344fe1e36cdd0e6e9c3d9aff6 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Tue, 15 Oct 2019 15:44:45 +0530 Subject: adding support to enable different personality of the same soc. Same SoC has different personality by creating different number of: - cores - clusters. As a result, the platform specific power domain tree will be created after identify the personality of the SoC. Hence, platform specific power domain tree may not be same for all the personality of the soc. Thus, psci library code will deduce the 'plat_core_count', while populating the power domain tree topology and return the number of cores. PLATFORM_CORE_COUNT will still be valid for a SoC, such that psci_plat_core_count <= PLATFORM_CORE_COUNT. PLATFORM_CORE_COUNT will continued to be defined by platform to create the data structures. Signed-off-by: Pankaj Gupta Change-Id: I1f5c47647631cae2dcdad540d64cf09757db7185 --- lib/psci/psci_common.c | 17 +++++++++-------- lib/psci/psci_private.h | 1 + lib/psci/psci_setup.c | 13 ++++++++----- 3 files changed, 18 insertions(+), 13 deletions(-) diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 7c42be7e5..ea1a01de9 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -43,6 +43,7 @@ const spd_pm_ops_t *psci_spd_pm; static plat_local_state_t psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT]; +unsigned int psci_plat_core_count; /******************************************************************************* * Arrays that hold the platform's power domain tree information for state @@ -161,7 +162,7 @@ unsigned int psci_is_last_on_cpu(void) { unsigned int cpu_idx, my_idx = plat_my_core_pos(); - for (cpu_idx = 0; cpu_idx < (unsigned int)PLATFORM_CORE_COUNT; + for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { if (cpu_idx == my_idx) { assert(psci_get_aff_info_state() == AFF_STATE_ON); @@ -208,7 +209,7 @@ static void psci_set_req_local_pwr_state(unsigned int pwrlvl, { assert(pwrlvl > PSCI_CPU_PWR_LVL); if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && - (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) { + (cpu_idx < psci_plat_core_count)) { psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state; } } @@ -220,10 +221,10 @@ void __init psci_init_req_local_pwr_states(void) { /* Initialize the requested state of all non CPU power domains as OFF */ unsigned int pwrlvl; - int core; + unsigned int core; for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) { - for (core = 0; core < PLATFORM_CORE_COUNT; core++) { + for (core = 0; core < psci_plat_core_count; core++) { psci_req_local_pwr_states[pwrlvl][core] = PLAT_MAX_OFF_STATE; } @@ -244,7 +245,7 @@ static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, assert(pwrlvl > PSCI_CPU_PWR_LVL); if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && - (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) { + (cpu_idx < psci_plat_core_count)) { return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx]; } else return NULL; @@ -888,7 +889,7 @@ int psci_spd_migrate_info(u_register_t *mpidr) void psci_print_power_domain_map(void) { #if LOG_LEVEL >= LOG_LEVEL_INFO - int idx; + unsigned int idx; plat_local_state_t state; plat_local_state_type_t state_type; @@ -900,7 +901,7 @@ void psci_print_power_domain_map(void) }; INFO("PSCI Power Domain Map:\n"); - for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT); + for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - psci_plat_core_count); idx++) { state_type = find_local_state_type( psci_non_cpu_pd_nodes[idx].local_state); @@ -912,7 +913,7 @@ void psci_print_power_domain_map(void) psci_non_cpu_pd_nodes[idx].local_state); } - for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) { + for (idx = 0; idx < psci_plat_core_count; idx++) { state = psci_get_cpu_local_state_by_idx(idx); state_type = find_local_state_type(state); INFO(" CPU Node : MPID 0x%llx, parent_node %d," diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h index b49847c95..0f25e6563 100644 --- a/lib/psci/psci_private.h +++ b/lib/psci/psci_private.h @@ -251,6 +251,7 @@ extern const plat_psci_ops_t *psci_plat_pm_ops; extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; extern unsigned int psci_caps; +extern unsigned int psci_plat_core_count; /******************************************************************************* * SPD's power management hooks registered with PSCI diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c index 853f9157c..becb54709 100644 --- a/lib/psci/psci_setup.c +++ b/lib/psci/psci_setup.c @@ -84,11 +84,12 @@ static void __init psci_init_pwr_domain_node(unsigned char node_idx, *******************************************************************************/ static void __init psci_update_pwrlvl_limits(void) { - int j, cpu_idx; + unsigned int cpu_idx; + int j; unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; unsigned int temp_index[PLAT_MAX_PWR_LVL]; - for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { + for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { psci_get_parent_pwr_domain_nodes(cpu_idx, (unsigned int)PLAT_MAX_PWR_LVL, temp_index); @@ -109,7 +110,8 @@ static void __init psci_update_pwrlvl_limits(void) * informs the number of root power domains. The parent nodes of the root nodes * will point to an invalid entry(-1). ******************************************************************************/ -static void __init populate_power_domain_tree(const unsigned char *topology) +static unsigned int __init populate_power_domain_tree(const unsigned char + *topology) { unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl; unsigned int node_index = 0U, num_children; @@ -160,7 +162,8 @@ static void __init populate_power_domain_tree(const unsigned char *topology) } /* Validate the sanity of array exported by the platform */ - assert((int) j == PLATFORM_CORE_COUNT); + assert(j <= (unsigned int)PLATFORM_CORE_COUNT); + return j; } /******************************************************************************* @@ -199,7 +202,7 @@ int __init psci_setup(const psci_lib_args_t *lib_args) topology_tree = plat_get_power_domain_tree_desc(); /* Populate the power domain arrays using the platform topology map */ - populate_power_domain_tree(topology_tree); + psci_plat_core_count = populate_power_domain_tree(topology_tree); /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */ psci_update_pwrlvl_limits(); -- cgit v1.2.3 From e34cc0cedca6e229847c232fe58d37fad2610ce9 Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Sat, 9 Nov 2019 23:28:08 -0600 Subject: Changes to support updated register usage in SMCCC v1.2 From AArch64 state, arguments are passed in registers W0-W7(X0-X7) and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls. From AArch32 state, arguments are passed in registers R0-R7 and results are returned in registers R0-R7 for SMC32 calls. Most of the functions and macros already existed to support using upto 8 registers for passing/returning parameters/results. Added few helper macros for SMC calls from AArch32 state. Link to the specification: https://developer.arm.com/docs/den0028/c Change-Id: I87976b42454dc3fc45c8343e9640aa78210e9741 Signed-off-by: Madhukar Pappireddy --- docs/design/firmware-design.rst | 4 ++-- docs/getting_started/rt-svc-writers-guide.rst | 26 ++++++++++++++++++++++---- include/arch/aarch32/smccc_helpers.h | 18 +++++++++++++++++- include/lib/smccc.h | 8 +++++++- 4 files changed, 48 insertions(+), 8 deletions(-) diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index 4958fc097..4e380bfe1 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -978,8 +978,8 @@ manipulation; and with ``flags`` indicating the security state of the caller. Th framework finally sets up the execution stack for the handler, and invokes the services ``handle()`` function. -On return from the handler the result registers are populated in X0-X3 before -restoring the stack and CPU state and returning from the original SMC. +On return from the handler the result registers are populated in X0-X7 as needed +before restoring the stack and CPU state and returning from the original SMC. Exception Handling Framework ---------------------------- diff --git a/docs/getting_started/rt-svc-writers-guide.rst b/docs/getting_started/rt-svc-writers-guide.rst index 6a06025ef..5375b659d 100644 --- a/docs/getting_started/rt-svc-writers-guide.rst +++ b/docs/getting_started/rt-svc-writers-guide.rst @@ -244,17 +244,35 @@ The handler is responsible for: TF-A expects owning entities to follow this recommendation. -#. Returning the result to the caller. The `SMCCC`_ allows for up to 256 bits - of return value in SMC64 using X0-X3 and 128 bits in SMC32 using W0-W3. The - framework provides a family of macros to set the multi-register return - value and complete the handler: +#. Returning the result to the caller. Based on `SMCCC`_ spec, results are + returned in W0-W7(X0-X7) registers for SMC32(SMC64) calls from AArch64 + state. Results are returned in R0-R7 registers for SMC32 calls from AArch32 + state. The framework provides a family of macros to set the multi-register + return value and complete the handler: .. code:: c + AArch64 state: + SMC_RET1(handle, x0); SMC_RET2(handle, x0, x1); SMC_RET3(handle, x0, x1, x2); SMC_RET4(handle, x0, x1, x2, x3); + SMC_RET5(handle, x0, x1, x2, x3, x4); + SMC_RET6(handle, x0, x1, x2, x3, x4, x5); + SMC_RET7(handle, x0, x1, x2, x3, x4, x5, x6); + SMC_RET8(handle, x0, x1, x2, x3, x4, x5, x6, x7); + + AArch32 state: + + SMC_RET1(handle, r0); + SMC_RET2(handle, r0, r1); + SMC_RET3(handle, r0, r1, r2); + SMC_RET4(handle, r0, r1, r2, r3); + SMC_RET5(handle, r0, r1, r2, r3, r4); + SMC_RET6(handle, r0, r1, r2, r3, r4, r5); + SMC_RET7(handle, r0, r1, r2, r3, r4, r5, r6); + SMC_RET8(handle, r0, r1, r2, r3, r4, r5, r6, r7); The ``cookie`` parameter to the handler is reserved for future use and can be ignored. The ``handle`` is returned by the SMC handler - completion of the diff --git a/include/arch/aarch32/smccc_helpers.h b/include/arch/aarch32/smccc_helpers.h index b2ee3cfe0..2ce7874ef 100644 --- a/include/arch/aarch32/smccc_helpers.h +++ b/include/arch/aarch32/smccc_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -130,6 +130,22 @@ CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch); ((smc_ctx_t *)(_h))->r3 = (_r3); \ SMC_RET3(_h, (_r0), (_r1), (_r2)); \ } +#define SMC_RET5(_h, _r0, _r1, _r2, _r3, _r4) { \ + ((smc_ctx_t *)(_h))->r4 = (_r4); \ + SMC_RET4(_h, (_r0), (_r1), (_r2), (_r3)); \ +} +#define SMC_RET6(_h, _r0, _r1, _r2, _r3, _r4, _r5) { \ + ((smc_ctx_t *)(_h))->r5 = (_r5); \ + SMC_RET5(_h, (_r0), (_r1), (_r2), (_r3), (_r4)); \ +} +#define SMC_RET7(_h, _r0, _r1, _r2, _r3, _r4, _r5, _r6) { \ + ((smc_ctx_t *)(_h))->r6 = (_r6); \ + SMC_RET6(_h, (_r0), (_r1), (_r2), (_r3), (_r4), (_r5)); \ +} +#define SMC_RET8(_h, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) { \ + ((smc_ctx_t *)(_h))->r7 = (_r7); \ + SMC_RET7(_h, (_r0), (_r1), (_r2), (_r3), (_r4), (_r5), (_r6)); \ +} /* * Helper macro to retrieve the SMC parameters from smc_ctx_t. diff --git a/include/lib/smccc.h b/include/lib/smccc.h index 76e60231f..dd3c578dc 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h @@ -20,7 +20,7 @@ SMCCC_VERSION_MINOR_SHIFT)) #define SMCCC_MAJOR_VERSION U(1) -#define SMCCC_MINOR_VERSION U(1) +#define SMCCC_MINOR_VERSION U(2) /******************************************************************************* * Bit definitions inside the function id as per the SMC calling convention @@ -83,6 +83,12 @@ #define SMC_UNK -1 #define SMC_PREEMPTED -2 /* Not defined by the SMCCC */ +/* Return codes for Arm Architecture Service SMC calls */ +#define SMC_ARCH_CALL_SUCCESS 0 +#define SMC_ARCH_CALL_NOT_SUPPORTED -1 +#define SMC_ARCH_CALL_NOT_REQUIRED -2 +#define SMC_ARCH_CALL_INVAL_PARAM -3 + /* Various flags passed to SMC handlers */ #define SMC_FROM_SECURE (U(0) << 0) #define SMC_FROM_NON_SECURE (U(1) << 0) -- cgit v1.2.3 From 697d18ae1a73c5e2d874b36760618b9f6534baa9 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Mon, 18 Nov 2019 15:52:13 +0100 Subject: plat/st: Fix incorrect return value Change the return code in boot_api.h which impacts the authentication result. Signed-off-by: Lionel Debieve Change-Id: I2c3aadb98dd261ae5ad73978fc74a8a8cfa59b82 Reviewed-by: Yann GAUTIER --- plat/st/stm32mp1/include/boot_api.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/st/stm32mp1/include/boot_api.h b/plat/st/stm32mp1/include/boot_api.h index 2284970fa..c80aef6dd 100644 --- a/plat/st/stm32mp1/include/boot_api.h +++ b/plat/st/stm32mp1/include/boot_api.h @@ -124,7 +124,7 @@ /* Closed = OTP_CFG0[6] */ #define BOOT_API_OTP_MODE_CLOSED_BIT_POS 6 -#define BOOT_API_RETURN_OK 0x66U +#define BOOT_API_RETURN_OK 0x77U /* * Boot Context related definitions -- cgit v1.2.3 From 43f35ef516b899c82e11bad760c704c44ced5440 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Wed, 29 May 2019 13:59:40 +0100 Subject: doc: Split the User Guide into multiple files The User Guide document has grown organically over time and now covers a wide range of topics, making it difficult to skim read and extract information from. Currently, it covers these topics and maybe a couple more: - Requirements (hardware, tools, libs) - Checking out the repo - Basic build instructions - A comprehensive list of build flags - FIP packaging - Building specifically for Juno - Firmware update images - EL3 payloads - Preloaded BL33 boot flow - Running on FVPs - Running on Juno I have separated these out into a few groups that become new documents. Broadly speaking, build instructions for the tools, for TF-A generally, and for specific scenarios are separated. Content relating to specific platforms (Juno and the FVPs are Arm-specific platforms, essentially) has been moved into the documentation that is specific to those platforms, under docs/plat/arm. Change-Id: Ica87c52d8cd4f577332be0b0738998ea3ba3bbec Signed-off-by: Paul Beesley --- docs/components/romlib-design.rst | 22 +- docs/design/alt-boot-flows.rst | 84 ++ docs/design/firmware-design.rst | 11 +- docs/design/index.rst | 6 + docs/design/reset-design.rst | 4 +- docs/design/trusted-board-boot-build.rst | 114 ++ docs/design/trusted-board-boot.rst | 13 +- docs/getting_started/build-options.rst | 623 +++++++++ docs/getting_started/docs-build.rst | 6 +- docs/getting_started/index.rst | 9 +- docs/getting_started/initial-build.rst | 117 ++ docs/getting_started/porting-guide.rst | 14 +- docs/getting_started/prerequisites.rst | 136 ++ docs/getting_started/tools-build.rst | 140 ++ docs/getting_started/user-guide.rst | 2214 ------------------------------ docs/perf/index.rst | 5 + docs/perf/tsp.rst | 27 + docs/plat/arm/arm-build-options.rst | 114 ++ docs/plat/arm/fvp-ve/index.rst | 84 ++ docs/plat/arm/fvp/index.rst | 637 +++++++++ docs/plat/arm/index.rst | 19 + docs/plat/arm/juno/index.rst | 246 ++++ docs/plat/fvp_ve.rst | 80 -- docs/plat/index.rst | 66 +- docs/plat/marvell/build.rst | 5 +- docs/plat/socionext-uniphier.rst | 3 +- docs/process/contributing.rst | 21 +- docs/process/security-hardening.rst | 2 +- 28 files changed, 2417 insertions(+), 2405 deletions(-) create mode 100644 docs/design/alt-boot-flows.rst create mode 100644 docs/design/trusted-board-boot-build.rst create mode 100644 docs/getting_started/build-options.rst create mode 100644 docs/getting_started/initial-build.rst create mode 100644 docs/getting_started/prerequisites.rst create mode 100644 docs/getting_started/tools-build.rst delete mode 100644 docs/getting_started/user-guide.rst create mode 100644 docs/perf/tsp.rst create mode 100644 docs/plat/arm/arm-build-options.rst create mode 100644 docs/plat/arm/fvp-ve/index.rst create mode 100644 docs/plat/arm/fvp/index.rst create mode 100644 docs/plat/arm/index.rst create mode 100644 docs/plat/arm/juno/index.rst delete mode 100644 docs/plat/fvp_ve.rst diff --git a/docs/components/romlib-design.rst b/docs/components/romlib-design.rst index e0a028e46..d34b3cc58 100644 --- a/docs/components/romlib-design.rst +++ b/docs/components/romlib-design.rst @@ -115,21 +115,27 @@ Memory impact ~~~~~~~~~~~~~ Using library at ROM will modify the memory layout of the BL images: + - The ROM library needs a page aligned RAM section to hold the RW data. This - section is defined by the ROMLIB_RW_BASE and ROMLIB_RW_END macros. - On Arm platforms a section of 1 page (0x1000) is allocated at the top of SRAM. - This will have for effect to shift down all the BL images by 1 page. + section is defined by the ROMLIB_RW_BASE and ROMLIB_RW_END macros. + On Arm platforms a section of 1 page (0x1000) is allocated at the top of SRAM. + This will have for effect to shift down all the BL images by 1 page. + - Depending on the functions moved to the ROM library, the size of the BL images - will be reduced. - For example: moving MbedTLS function into the ROM library reduces BL1 and - BL2, but not BL31. + will be reduced. + For example: moving MbedTLS function into the ROM library reduces BL1 and + BL2, but not BL31. + - This change in BL images size can be taken into consideration to optimize the - memory layout when defining the BLx_BASE macros. + memory layout when defining the BLx_BASE macros. Build library at ROM ~~~~~~~~~~~~~~~~~~~~~ -The environment variable ``CROSS_COMPILE`` must be set as per the user guide. +The environment variable ``CROSS_COMPILE`` must be set appropriately. Refer to +:ref:`Performing an Initial Build` for more information about setting this +variable. + In the below example the usage of ROMLIB together with mbed TLS is demonstrated to showcase the benefits of library at ROM - it's not mandatory. diff --git a/docs/design/alt-boot-flows.rst b/docs/design/alt-boot-flows.rst new file mode 100644 index 000000000..b44c061d4 --- /dev/null +++ b/docs/design/alt-boot-flows.rst @@ -0,0 +1,84 @@ +Alternative Boot Flows +====================== + +EL3 payloads alternative boot flow +---------------------------------- + +On a pre-production system, the ability to execute arbitrary, bare-metal code at +the highest exception level is required. It allows full, direct access to the +hardware, for example to run silicon soak tests. + +Although it is possible to implement some baremetal secure firmware from +scratch, this is a complex task on some platforms, depending on the level of +configuration required to put the system in the expected state. + +Rather than booting a baremetal application, a possible compromise is to boot +``EL3 payloads`` through TF-A instead. This is implemented as an alternative +boot flow, where a modified BL2 boots an EL3 payload, instead of loading the +other BL images and passing control to BL31. It reduces the complexity of +developing EL3 baremetal code by: + +- putting the system into a known architectural state; +- taking care of platform secure world initialization; +- loading the SCP_BL2 image if required by the platform. + +When booting an EL3 payload on Arm standard platforms, the configuration of the +TrustZone controller is simplified such that only region 0 is enabled and is +configured to permit secure access only. This gives full access to the whole +DRAM to the EL3 payload. + +The system is left in the same state as when entering BL31 in the default boot +flow. In particular: + +- Running in EL3; +- Current state is AArch64; +- Little-endian data access; +- All exceptions disabled; +- MMU disabled; +- Caches disabled. + +.. _alt_boot_flows_el3_payload: + +Booting an EL3 payload +~~~~~~~~~~~~~~~~~~~~~~ + +The EL3 payload image is a standalone image and is not part of the FIP. It is +not loaded by TF-A. Therefore, there are 2 possible scenarios: + +- The EL3 payload may reside in non-volatile memory (NVM) and execute in + place. In this case, booting it is just a matter of specifying the right + address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A. + +- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at + run-time. + +To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be +used. The infinite loop that it introduces in BL1 stops execution at the right +moment for a debugger to take control of the target and load the payload (for +example, over JTAG). + +It is expected that this loading method will work in most cases, as a debugger +connection is usually available in a pre-production system. The user is free to +use any other platform-specific mechanism to load the EL3 payload, though. + + +Preloaded BL33 alternative boot flow +------------------------------------ + +Some platforms have the ability to preload BL33 into memory instead of relying +on TF-A to load it. This may simplify packaging of the normal world code and +improve performance in a development environment. When secure world cold boot +is complete, TF-A simply jumps to a BL33 base address provided at build time. + +For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be +used when compiling TF-A. For example, the following command will create a FIP +without a BL33 and prepare to jump to a BL33 image loaded at address +0x80000000: + +.. code:: shell + + make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index 4958fc097..eb0a366d1 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -597,7 +597,7 @@ registered function to initialize BL32 before running BL33. This initialization is not necessary for AArch32 SPs. Details on BL32 initialization and the SPD's role are described in the -"Secure-EL1 Payloads and Dispatchers" section below. +:ref:`firmware_design_sel1_spd` section below. BL33 (Non-trusted Firmware) execution ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -868,7 +868,7 @@ not all been instantiated in the current implementation. TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher (TSPD). Details of SPD design and TSP/TSPD operation are described in the - "Secure-EL1 Payloads and Dispatchers" section below. + :ref:`firmware_design_sel1_spd` section below. #. CPU implementation service @@ -1875,10 +1875,7 @@ BL image during boot. | MHU | 0x04000000 +----------+ -Library at ROM ---------------- - -Please refer to the :ref:`Library at ROM` document. +.. _firmware_design_fip: Firmware Image Package (FIP) ---------------------------- @@ -2543,7 +2540,7 @@ Architecture Extension-specific code is included in the build. Otherwise, TF-A targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values. -See also the *Summary of build options* in :ref:`User Guide`. +.. seealso:: :ref:`Build Options` For details on the Architecture Extension and available features, please refer to the respective Architecture Extension Supplement. diff --git a/docs/design/index.rst b/docs/design/index.rst index a51a4eb47..e3b8f7429 100644 --- a/docs/design/index.rst +++ b/docs/design/index.rst @@ -6,6 +6,7 @@ System Design :caption: Contents :numbered: + alt-boot-flows auth-framework cpu-specific-build-macros firmware-design @@ -13,3 +14,8 @@ System Design psci-pd-tree reset-design trusted-board-boot + trusted-board-boot-build + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/design/reset-design.rst b/docs/design/reset-design.rst index a92ceeba7..7b10c956c 100644 --- a/docs/design/reset-design.rst +++ b/docs/design/reset-design.rst @@ -115,8 +115,8 @@ only. It allows the Arm FVP port to support the ``RESET_TO_BL31`` configuration, in which case the ``bl31.bin`` image must be loaded to its run address in Trusted SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run -address. See the :ref:`User Guide` for details of running the FVP models in this -way. +address. See the :ref:`Arm Fixed Virtual Platforms (FVP)` for details of running +the FVP models in this way. Although technically it would be possible to program the reset base address with the right support in the SCP firmware, this is currently not implemented so the diff --git a/docs/design/trusted-board-boot-build.rst b/docs/design/trusted-board-boot-build.rst new file mode 100644 index 000000000..202524316 --- /dev/null +++ b/docs/design/trusted-board-boot-build.rst @@ -0,0 +1,114 @@ +Building FIP images with support for Trusted Board Boot +======================================================= + +Trusted Board Boot primarily consists of the following two features: + +- Image Authentication, described in :ref:`Trusted Board Boot`, and +- Firmware Update, described in :ref:`Firmware Update (FWU)` + +The following steps should be followed to build FIP and (optionally) FWU_FIP +images with support for these features: + +#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser + modules by checking out a recent version of the `mbed TLS Repository`_. It + is important to use a version that is compatible with TF-A and fixes any + known security vulnerabilities. See `mbed TLS Security Center`_ for more + information. See the :ref:`Prerequisites` document for the appropriate + version of mbed TLS to use. + + The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS + source files the modules depend upon. + ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration + options required to build the mbed TLS sources. + + Note that the mbed TLS library is licensed under the Apache version 2.0 + license. Using mbed TLS source code will affect the licensing of TF-A + binaries that are built using this library. + +#. To build the FIP image, ensure the following command line variables are set + while invoking ``make`` to build TF-A: + + - ``MBEDTLS_DIR=`` + - ``TRUSTED_BOARD_BOOT=1`` + - ``GENERATE_COT=1`` + + In the case of Arm platforms, the location of the ROTPK hash must also be + specified at build time. Two locations are currently supported (see + ``ARM_ROTPK_LOCATION`` build option): + + - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted + root-key storage registers present in the platform. On Juno, this + registers are read-only. On FVP Base and Cortex models, the registers + are read-only, but the value can be specified using the command line + option ``bp.trusted_key_storage.public_key`` when launching the model. + On both Juno and FVP models, the default value corresponds to an + ECDSA-SECP256R1 public key hash, whose private part is not currently + available. + + - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded + in the Arm platform port. The private/public RSA key pair may be + found in ``plat/arm/board/common/rotpk``. + + - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded + in the Arm platform port. The private/public ECDSA key pair may be + found in ``plat/arm/board/common/rotpk``. + + Example of command line using RSA development keys: + + .. code:: shell + + MBEDTLS_DIR= \ + make PLAT= TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ + ARM_ROTPK_LOCATION=devel_rsa \ + ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ + BL33=/ \ + all fip + + The result of this build will be the bl1.bin and the fip.bin binaries. This + FIP will include the certificates corresponding to the Chain of Trust + described in the TBBR-client document. These certificates can also be found + in the output build directory. + +#. The optional FWU_FIP contains any additional images to be loaded from + Non-Volatile storage during the :ref:`Firmware Update (FWU)` process. To build the + FWU_FIP, any FWU images required by the platform must be specified on the + command line. On Arm development platforms like Juno, these are: + + - NS_BL2U. The AP non-secure Firmware Updater image. + - SCP_BL2U. The SCP Firmware Update Configuration image. + + Example of Juno command line for generating both ``fwu`` and ``fwu_fip`` + targets using RSA development: + + :: + + MBEDTLS_DIR= \ + make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ + ARM_ROTPK_LOCATION=devel_rsa \ + ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ + BL33=/ \ + SCP_BL2=/ \ + SCP_BL2U=/ \ + NS_BL2U=/ \ + all fip fwu_fip + + .. note:: + The BL2U image will be built by default and added to the FWU_FIP. + The user may override this by adding ``BL2U=/`` + to the command line above. + + .. note:: + Building and installing the non-secure and SCP FWU images (NS_BL1U, + NS_BL2U and SCP_BL2U) is outside the scope of this document. + + The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries. + Both the FIP and FWU_FIP will include the certificates corresponding to the + Chain of Trust described in the TBBR-client document. These certificates + can also be found in the output build directory. + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* + +.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git +.. _mbed TLS Security Center: https://tls.mbed.org/security diff --git a/docs/design/trusted-board-boot.rst b/docs/design/trusted-board-boot.rst index f3b1c3644..49e8adb98 100644 --- a/docs/design/trusted-board-boot.rst +++ b/docs/design/trusted-board-boot.rst @@ -187,8 +187,8 @@ The next step is executed for all the boot loader images. The Trusted Board Boot implementation spans both generic and platform-specific BL1 and BL2 code, and in tool code on the host build machine. The feature is -enabled through use of specific build flags as described in the -:ref:`User Guide`. +enabled through use of specific build flags as described in +:ref:`Build Options`. On the host machine, a tool generates the certificates, which are included in the FIP along with the boot loader images. These certificates are loaded in @@ -222,9 +222,12 @@ passed as inputs to the ``fiptool`` utility for creating the FIP. The certificates are also stored individually in the in the output build directory. -The tool resides in the ``tools/cert_create`` directory. It uses OpenSSL SSL -library version 1.0.1 or later to generate the X.509 certificates. Instructions -for building and using the tool can be found in the :ref:`User Guide`. +The tool resides in the ``tools/cert_create`` directory. It uses the OpenSSL SSL +library version to generate the X.509 certificates. The specific version of the +library that is required is given in the :ref:`Prerequisites` document. + +Instructions for building and using the tool can be found at +:ref:`tools_build_cert_create`. -------------- diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst new file mode 100644 index 000000000..fded1e0c9 --- /dev/null +++ b/docs/getting_started/build-options.rst @@ -0,0 +1,623 @@ +Build Options +============= + +The TF-A build system supports the following build options. Unless mentioned +otherwise, these options are expected to be specified at the build command +line and are not to be modified in any component makefiles. Note that the +build system doesn't track dependency for build options. Therefore, if any of +the build options are changed from a previous build, a clean build must be +performed. + +.. _build_options_common: + +Common build options +-------------------- + +- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the + compiler should use. Valid values are T32 and A32. It defaults to T32 due to + code having a smaller resulting size. + +- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as + as the BL32 image when ``ARCH=aarch32``. The value should be the path to the + directory containing the SP source, relative to the ``bl32/``; the directory + is expected to contain a makefile called ``.mk``. + +- ``ARCH`` : Choose the target build architecture for TF-A. It can take either + ``aarch64`` or ``aarch32`` as values. By default, it is defined to + ``aarch64``. + +- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when + compiling TF-A. Its value must be numeric, and defaults to 8 . See also, + *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in + :ref:`Firmware Design`. + +- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when + compiling TF-A. Its value must be a numeric, and defaults to 0. See also, + *Armv8 Architecture Extensions* in :ref:`Firmware Design`. + +- ``BL2``: This is an optional build option which specifies the path to BL2 + image for the ``fip`` target. In this case, the BL2 in the TF-A will not be + built. + +- ``BL2U``: This is an optional build option which specifies the path to + BL2U image. In this case, the BL2U in TF-A will not be built. + +- ``BL2_AT_EL3``: This is an optional build option that enables the use of + BL2 at EL3 execution level. + +- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place + (XIP) memory, like BL1. In these use-cases, it is necessary to initialize + the RW sections in RAM, while leaving the RO sections in place. This option + enable this use-case. For now, this option is only supported when BL2_AT_EL3 + is set to '1'. + +- ``BL31``: This is an optional build option which specifies the path to + BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not + be built. + +- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the + file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, + this file name will be used to save the key. + +- ``BL32``: This is an optional build option which specifies the path to + BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not + be built. + +- ``BL32_EXTRA1``: This is an optional build option which specifies the path to + Trusted OS Extra1 image for the ``fip`` target. + +- ``BL32_EXTRA2``: This is an optional build option which specifies the path to + Trusted OS Extra2 image for the ``fip`` target. + +- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the + file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, + this file name will be used to save the key. + +- ``BL33``: Path to BL33 image in the host file system. This is mandatory for + ``fip`` target in case TF-A BL2 is used. + +- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the + file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, + this file name will be used to save the key. + +- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication + and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. + If enabled, it is needed to use a compiler that supports the option + ``-mbranch-protection``. Selects the branch protection features to use: +- 0: Default value turns off all types of branch protection +- 1: Enables all types of branch protection features +- 2: Return address signing to its standard level +- 3: Extend the signing to include leaf functions + + The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options + and resulting PAuth/BTI features. + + +-------+--------------+-------+-----+ + | Value | GCC option | PAuth | BTI | + +=======+==============+=======+=====+ + | 0 | none | N | N | + +-------+--------------+-------+-----+ + | 1 | standard | Y | Y | + +-------+--------------+-------+-----+ + | 2 | pac-ret | Y | N | + +-------+--------------+-------+-----+ + | 3 | pac-ret+leaf | Y | N | + +-------+--------------+-------+-----+ + + This option defaults to 0 and this is an experimental feature. + Note that Pointer Authentication is enabled for Non-secure world + irrespective of the value of this option if the CPU supports it. + +- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the + compilation of each build. It must be set to a C string (including quotes + where applicable). Defaults to a string that contains the time and date of + the compilation. + +- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A + build to be uniquely identified. Defaults to the current git commit id. + +- ``CFLAGS``: Extra user options appended on the compiler's command line in + addition to the options set by the build system. + +- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may + release several CPUs out of reset. It can take either 0 (several CPUs may be + brought up) or 1 (only one CPU will ever be brought up during cold reset). + Default is 0. If the platform always brings up a single CPU, there is no + need to distinguish between primary and secondary CPUs and the boot path can + be optimised. The ``plat_is_my_cpu_primary()`` and + ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need + to be implemented in this case. + +- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor + register state when an unexpected exception occurs during execution of + BL31. This option defaults to the value of ``DEBUG`` - i.e. by default + this is only enabled for a debug build of the firmware. + +- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the + certificate generation tool to create new keys in case no valid keys are + present or specified. Allowed options are '0' or '1'. Default is '1'. + +- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause + the AArch32 system registers to be included when saving and restoring the + CPU context. The option must be set to 0 for AArch64-only platforms (that + is on hardware that does not implement AArch32, or at least not at EL1 and + higher ELs). Default value is 1. + +- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP + registers to be included when saving and restoring the CPU context. Default + is 0. + +- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables + Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth + registers to be included when saving and restoring the CPU context as + part of world switch. Default value is 0 and this is an experimental feature. + Note that Pointer Authentication is enabled for Non-secure world irrespective + of the value of this flag if the CPU supports it. + +- ``DEBUG``: Chooses between a debug and release build. It can take either 0 + (release) or 1 (debug) as values. 0 is the default. + +- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation + of the binary image. If set to 1, then only the ELF image is built. + 0 is the default. + +- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted + Board Boot authentication at runtime. This option is meant to be enabled only + for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this + flag has to be enabled. 0 is the default. + +- ``E``: Boolean option to make warnings into errors. Default is 1. + +- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of + the normal boot flow. It must specify the entry point address of the EL3 + payload. Please refer to the "Booting an EL3 payload" section for more + details. + +- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. + This is an optional architectural feature available on v8.4 onwards. Some + v8.2 implementations also implement an AMU and this option can be used to + enable this feature on those systems as well. Default is 0. + +- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` + are compiled out. For debug builds, this option defaults to 1, and calls to + ``assert()`` are left in place. For release builds, this option defaults to 0 + and calls to ``assert()`` function are compiled out. This option can be set + independently of ``DEBUG``. It can also be used to hide any auxiliary code + that is only required for the assertion and does not fit in the assertion + itself. + +- ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace + dumps or not. It is supported in both AArch64 and AArch32. However, in + AArch32 the format of the frame records are not defined in the AAPCS and they + are defined by the implementation. This implementation of backtrace only + supports the format used by GCC when T32 interworking is disabled. For this + reason enabling this option in AArch32 will force the compiler to only + generate A32 code. This option is enabled by default only in AArch64 debug + builds, but this behaviour can be overridden in each platform's Makefile or + in the build command line. + +- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM + feature. MPAM is an optional Armv8.4 extension that enables various memory + system components and resources to define partitions; software running at + various ELs can assign themselves to desired partition to control their + performance aspects. + + When this option is set to ``1``, EL3 allows lower ELs to access their own + MPAM registers without trapping into EL3. This option doesn't make use of + partitioning in EL3, however. Platform initialisation code should configure + and use partitions in EL3 as required. This option defaults to ``0``. + +- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) + support within generic code in TF-A. This option is currently only supported + in BL31. Default is 0. + +- ``ENABLE_PMF``: Boolean option to enable support for optional Performance + Measurement Framework(PMF). Default is 0. + +- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI + functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. + In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must + be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in + software. + +- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime + instrumentation which injects timestamp collection points into TF-A to + allow runtime performance to be measured. Currently, only PSCI is + instrumented. Enabling this option enables the ``ENABLE_PMF`` build option + as well. Default is 0. + +- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling + extensions. This is an optional architectural feature for AArch64. + The default is 1 but is automatically disabled when the target architecture + is AArch32. + +- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM). + Refer to :ref:`Secure Partition Manager` for more details about + this feature. Default is 0. + +- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension + (SVE) for the Non-secure world only. SVE is an optional architectural feature + for AArch64. Note that when SVE is enabled for the Non-secure world, access + to SIMD and floating-point functionality from the Secure world is disabled. + This is to avoid corruption of the Non-secure world data in the Z-registers + which are aliased by the SIMD and FP registers. The build option is not + compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an + assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to + 1. The default is 1 but is automatically disabled when the target + architecture is AArch32. + +- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection + checks in GCC. Allowed values are "all", "strong", "default" and "none". The + default value is set to "none". "strong" is the recommended stack protection + level if this feature is desired. "none" disables the stack protection. For + all values other than "none", the ``plat_get_stack_protector_canary()`` + platform hook needs to be implemented. The value is passed as the last + component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. + +- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of + deprecated platform APIs, helper functions or drivers within Trusted + Firmware as error. It can take the value 1 (flag the use of deprecated + APIs as error) or 0. The default is 0. + +- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions + targeted at EL3. When set ``0`` (default), no exceptions are expected or + handled at EL3, and a panic will result. This is supported only for AArch64 + builds. + +- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault + injection from lower ELs, and this build option enables lower ELs to use + Error Records accessed via System Registers to inject faults. This is + applicable only to AArch64 builds. + + This feature is intended for testing purposes only, and is advisable to keep + disabled for production images. + +- ``FIP_NAME``: This is an optional build option which specifies the FIP + filename for the ``fip`` target. Default is ``fip.bin``. + +- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU + FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. + +- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` + tool to create certificates as per the Chain of Trust described in + :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to + include the certificates in the FIP and FWU_FIP. Default value is '0'. + + Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support + for the Trusted Board Boot feature in the BL1 and BL2 images, to generate + the corresponding certificates, and to include those certificates in the + FIP and FWU_FIP. + + Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 + images will not include support for Trusted Board Boot. The FIP will still + include the corresponding certificates. This FIP can be used to verify the + Chain of Trust on the host machine through other mechanisms. + + Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 + images will include support for Trusted Board Boot, but the FIP and FWU_FIP + will not include the corresponding certificates, causing a boot failure. + +- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have + inherent support for specific EL3 type interrupts. Setting this build option + to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both + by `platform abstraction layer`__ and `Interrupt Management Framework`__. + This allows GICv2 platforms to enable features requiring EL3 interrupt type. + This also means that all GICv2 Group 0 interrupts are delivered to EL3, and + the Secure Payload interrupts needs to be synchronously handed over to Secure + EL1 for handling. The default value of this option is ``0``, which means the + Group 0 interrupts are assumed to be handled by Secure EL1. + + .. __: `platform-interrupt-controller-API.rst` + .. __: `interrupt-framework-design.rst` + +- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError + Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to + ``0`` (default), these exceptions will be trapped in the current exception + level (or in EL1 if the current exception level is EL0). + +- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific + software operations are required for CPUs to enter and exit coherency. + However, newer systems exist where CPUs' entry to and exit from coherency + is managed in hardware. Such systems require software to only initiate these + operations, and the rest is managed in hardware, minimizing active software + management. In such systems, this boolean option enables TF-A to carry out + build and run-time optimizations during boot and power management operations. + This option defaults to 0 and if it is enabled, then it implies + ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. + + If this flag is disabled while the platform which TF-A is compiled for + includes cores that manage coherency in hardware, then a compilation error is + generated. This is based on the fact that a system cannot have, at the same + time, cores that manage coherency in hardware and cores that don't. In other + words, a platform cannot have, at the same time, cores that require + ``HW_ASSISTED_COHERENCY=1`` and cores that require + ``HW_ASSISTED_COHERENCY=0``. + + Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of + translation library (xlat tables v2) must be used; version 1 of translation + library is not supported. + +- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 + runtime software in AArch32 mode, which is required to run AArch32 on Juno. + By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in + AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable + images. + +- ``KEY_ALG``: This build flag enables the user to select the algorithm to be + used for generating the PKCS keys and subsequent signing of the certificate. + It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option + ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR + compliant and is retained only for compatibility. The default value of this + flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. + +- ``HASH_ALG``: This build flag enables the user to select the secure hash + algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. + The default value of this flag is ``sha256``. + +- ``LDFLAGS``: Extra user options appended to the linkers' command line in + addition to the one set by the build system. + +- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log + output compiled into the build. This should be one of the following: + + :: + + 0 (LOG_LEVEL_NONE) + 10 (LOG_LEVEL_ERROR) + 20 (LOG_LEVEL_NOTICE) + 30 (LOG_LEVEL_WARNING) + 40 (LOG_LEVEL_INFO) + 50 (LOG_LEVEL_VERBOSE) + + All log output up to and including the selected log level is compiled into + the build. The default value is 40 in debug builds and 20 in release builds. + +- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It + specifies the file that contains the Non-Trusted World private key in PEM + format. If ``SAVE_KEYS=1``, this file name will be used to save the key. + +- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is + optional. It is only needed if the platform makefile specifies that it + is required in order to build the ``fwu_fip`` target. + +- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register + contents upon world switch. It can take either 0 (don't save and restore) or + 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it + wants the timer registers to be saved and restored. + +- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc + for the BL image. It can be either 0 (include) or 1 (remove). The default + value is 0. + +- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that + the underlying hardware is not a full PL011 UART but a minimally compliant + generic UART, which is a subset of the PL011. The driver will not access + any register that is not part of the SBSA generic UART specification. + Default value is 0 (a full PL011 compliant UART is present). + +- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name + must be subdirectory of any depth under ``plat/``, and must contain a + platform makefile named ``platform.mk``. For example, to build TF-A for the + Arm Juno board, select PLAT=juno. + +- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image + instead of the normal boot flow. When defined, it must specify the entry + point address for the preloaded BL33 image. This option is incompatible with + ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority + over ``PRELOADED_BL33_BASE``. + +- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset + vector address can be programmed or is fixed on the platform. It can take + either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a + programmable reset address, it is expected that a CPU will start executing + code directly at the right address, both on a cold and warm reset. In this + case, there is no need to identify the entrypoint on boot and the boot path + can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface + does not need to be implemented in this case. + +- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats + possible for the PSCI power-state parameter: original and extended State-ID + formats. This flag if set to 1, configures the generic PSCI layer to use the + extended format. The default value of this flag is 0, which means by default + the original power-state format is used by the PSCI implementation. This flag + should be specified by the platform makefile and it governs the return value + of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is + enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be + set to 1 as well. + +- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features + are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 + or later CPUs. + + When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be + set to ``1``. + + This option is disabled by default. + +- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead + of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 + entrypoint) or 1 (CPU reset to BL31 entrypoint). + The default value is 0. + +- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided + in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector + instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 + entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. + +- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the + file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this + file name will be used to save the key. + +- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the + certificate generation tool to save the keys used to establish the Chain of + Trust. Allowed options are '0' or '1'. Default is '0' (do not save). + +- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. + If a SCP_BL2 image is present then this option must be passed for the ``fip`` + target. + +- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the + file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, + this file name will be used to save the key. + +- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is + optional. It is only needed if the platform makefile specifies that it + is required in order to build the ``fwu_fip`` target. + +- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software + Delegated Exception Interface to BL31 image. This defaults to ``0``. + + When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be + set to ``1``. + +- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be + isolated on separate memory pages. This is a trade-off between security and + memory usage. See "Isolating code and read-only data on separate memory + pages" section in :ref:`Firmware Design`. This flag is disabled by default and + affects all BL images. + +- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. + This build option is only valid if ``ARCH=aarch64``. The value should be + the path to the directory containing the SPD source, relative to + ``services/spd/``; the directory is expected to contain a makefile called + ``.mk``. + +- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can + take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops + execution in BL1 just before handing over to BL31. At this point, all + firmware images have been loaded in memory, and the MMU and caches are + turned off. Refer to the "Debugging options" section for more details. + +- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles + secure interrupts (caught through the FIQ line). Platforms can enable + this directive if they need to handle such interruption. When enabled, + the FIQ are handled in monitor mode and non secure world is not allowed + to mask these events. Platforms that enable FIQ handling in SP_MIN shall + implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. + +- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board + Boot feature. When set to '1', BL1 and BL2 images include support to load + and verify the certificates and images in a FIP, and BL1 includes support + for the Firmware Update. The default value is '0'. Generation and inclusion + of certificates in the FIP and FWU_FIP depends upon the value of the + ``GENERATE_COT`` option. + + .. warning:: + This option depends on ``CREATE_KEYS`` to be enabled. If the keys + already exist in disk, they will be overwritten without further notice. + +- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It + specifies the file that contains the Trusted World private key in PEM + format. If ``SAVE_KEYS=1``, this file name will be used to save the key. + +- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or + synchronous, (see "Initializing a BL32 Image" section in + :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using + synchronous method) or 1 (BL32 is initialized using asynchronous method). + Default is 0. + +- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt + routing model which routes non-secure interrupts asynchronously from TSP + to EL3 causing immediate preemption of TSP. The EL3 is responsible + for saving and restoring the TSP context in this routing model. The + default routing model (when the value is 0) is to route non-secure + interrupts to TSP allowing it to save its context and hand over + synchronously to EL3 via an SMC. + + .. note:: + When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` + must also be set to ``1``. + +- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM + linker. When the ``LINKER`` build variable points to the armlink linker, + this flag is enabled automatically. To enable support for armlink, platforms + will have to provide a scatter file for the BL image. Currently, Tegra + platforms use the armlink support to compile BL3-1 images. + +- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent + memory region in the BL memory map or not (see "Use of Coherent memory in + TF-A" section in :ref:`Firmware Design`). It can take the value 1 + (Coherent memory region is included) or 0 (Coherent memory region is + excluded). Default is 1. + +- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. + This feature creates a library of functions to be placed in ROM and thus + reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default + is 0. + +- ``V``: Verbose build. If assigned anything other than 0, the build commands + are printed. Default is 0. + +- ``VERSION_STRING``: String used in the log output for each TF-A image. + Defaults to a string formed by concatenating the version number, build type + and build string. + +- ``W``: Warning level. Some compiler warning options of interest have been + regrouped and put in the root Makefile. This flag can take the values 0 to 3, + each level enabling more warning options. Default is 0. + +- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on + the CPU after warm boot. This is applicable for platforms which do not + require interconnect programming to enable cache coherency (eg: single + cluster platforms). If this option is enabled, then warm boot path + enables D-caches immediately after enabling MMU. This option defaults to 0. + +Debugging options +----------------- + +To compile a debug version and make the build more verbose use + +.. code:: shell + + make PLAT= DEBUG=1 V=1 all + +AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for +example DS-5) might not support this and may need an older version of DWARF +symbols to be emitted by GCC. This can be achieved by using the +``-gdwarf-`` flag, with the version being set to 2 or 3. Setting the +version to 2 is recommended for DS-5 versions older than 5.16. + +When debugging logic problems it might also be useful to disable all compiler +optimizations by using ``-O0``. + +.. warning:: + Using ``-O0`` could cause output images to be larger and base addresses + might need to be recalculated (see the **Memory layout on Arm development + platforms** section in the :ref:`Firmware Design`). + +Extra debug options can be passed to the build system by setting ``CFLAGS`` or +``LDFLAGS``: + +.. code:: shell + + CFLAGS='-O0 -gdwarf-2' \ + make PLAT= DEBUG=1 V=1 all + +Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be +ignored as the linker is called directly. + +It is also possible to introduce an infinite loop to help in debugging the +post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the +``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` +section. In this case, the developer may take control of the target using a +debugger when indicated by the console output. When using DS-5, the following +commands can be used: + +:: + + # Stop target execution + interrupt + + # + # Prepare your debugging environment, e.g. set breakpoints + # + + # Jump over the debug loop + set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 + + # Resume execution + continue + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst index fa0764266..c5625e98d 100644 --- a/docs/getting_started/docs-build.rst +++ b/docs/getting_started/docs-build.rst @@ -22,6 +22,9 @@ For building a local copy of the |TF-A| documentation you will need, at minimum: - Python 3 (3.5 or later) - PlantUML (1.2017.15 or later) +Optionally, the `Dia`_ application can be installed if you need to edit +existing ``.dia`` diagram files, or create new ones. + You must also install the Python modules that are specified in the ``requirements.txt`` file in the root of the ``docs`` directory. These modules can be installed using ``pip3`` (the Python Package Installer). Passing this @@ -33,7 +36,7 @@ that the working directory is ``docs``: .. code:: shell - sudo apt install python3 python3-pip plantuml + sudo apt install python3 python3-pip plantuml [dia] pip3 install [--user] -r requirements.txt .. note:: @@ -75,3 +78,4 @@ Output from the build process will be placed in: .. _Sphinx: http://www.sphinx-doc.org/en/master/ .. _pip homepage: https://pip.pypa.io/en/stable/ +.. _Dia: https://wiki.gnome.org/Apps/Dia diff --git a/docs/getting_started/index.rst b/docs/getting_started/index.rst index 07e3753ec..817beaf8e 100644 --- a/docs/getting_started/index.rst +++ b/docs/getting_started/index.rst @@ -6,9 +6,16 @@ Getting Started :caption: Contents :numbered: - user-guide + prerequisites docs-build + tools-build + initial-build + build-options image-terminology porting-guide psci-lib-integration-guide rt-svc-writers-guide + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/getting_started/initial-build.rst b/docs/getting_started/initial-build.rst new file mode 100644 index 000000000..41cd4d1c9 --- /dev/null +++ b/docs/getting_started/initial-build.rst @@ -0,0 +1,117 @@ +Performing an Initial Build +=========================== + +- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point + to the Linaro cross compiler. + + For AArch64: + + .. code:: shell + + export CROSS_COMPILE=/bin/aarch64-linux-gnu- + + For AArch32: + + .. code:: shell + + export CROSS_COMPILE=/bin/arm-eabi- + + It is possible to build TF-A using Clang or Arm Compiler 6. To do so + ``CC`` needs to point to the clang or armclang binary, which will + also select the clang or armclang assembler. Be aware that the + GNU linker is used by default. In case of being needed the linker + can be overridden using the ``LD`` variable. Clang linker version 6 is + known to work with TF-A. + + In both cases ``CROSS_COMPILE`` should be set as described above. + + Arm Compiler 6 will be selected when the base name of the path assigned + to ``CC`` matches the string 'armclang'. + + For AArch64 using Arm Compiler 6: + + .. code:: shell + + export CROSS_COMPILE=/bin/aarch64-linux-gnu- + make CC=/bin/armclang PLAT= all + + Clang will be selected when the base name of the path assigned to ``CC`` + contains the string 'clang'. This is to allow both clang and clang-X.Y + to work. + + For AArch64 using clang: + + .. code:: shell + + export CROSS_COMPILE=/bin/aarch64-linux-gnu- + make CC=/bin/clang PLAT= all + +- Change to the root directory of the TF-A source tree and build. + + For AArch64: + + .. code:: shell + + make PLAT= all + + For AArch32: + + .. code:: shell + + make PLAT= ARCH=aarch32 AARCH32_SP=sp_min all + + Notes: + + - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the + :ref:`Build Options` document for more information on available build + options. + + - (AArch32 only) Currently only ``PLAT=fvp`` is supported. + + - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it + corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is + provided by TF-A to demonstrate how PSCI Library can be integrated with + an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may + include other runtime services, for example Trusted OS services. A guide + to integrate PSCI library with AArch32 EL3 Runtime Software can be found + at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. + + - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32 + image, is not compiled in by default. Refer to the + :ref:`Test Secure Payload (TSP) and Dispatcher (TSPD)` document for + details on building the TSP. + + - By default this produces a release version of the build. To produce a + debug version instead, refer to the "Debugging options" section below. + + - The build process creates products in a ``build`` directory tree, building + the objects and binaries for each boot loader stage in separate + sub-directories. The following boot loader binary files are created + from the corresponding ELF files: + + - ``build///bl1.bin`` + - ``build///bl2.bin`` + - ``build///bl31.bin`` (AArch64 only) + - ``build///bl32.bin`` (mandatory for AArch32) + + where ```` is the name of the chosen platform and ```` + is either ``debug`` or ``release``. The actual number of images might differ + depending on the platform. + +- Build products for a specific build variant can be removed using: + + .. code:: shell + + make DEBUG= PLAT= clean + + ... where ```` is ``0`` or ``1``, as specified when building. + + The build tree can be removed completely using: + + .. code:: shell + + make realclean + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index 9cca75e92..17fd54662 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -23,8 +23,6 @@ Some modifications are common to all Boot Loader (BL) stages. Section 2 discusses these in detail. The subsequent sections discuss the remaining modifications for each BL stage in detail. -This document should be read in conjunction with the TF-A :ref:`User Guide`. - Please refer to the :ref:`Platform Compatibility Policy` for the policy regarding compatibility and deprecation of these porting interfaces. @@ -2387,8 +2385,8 @@ present in the platform. Arm standard platform layer supports both `Arm Generic Interrupt Controller version 2.0 (GICv2)`_ and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the FVP can be configured to use either GICv2 or GICv3 depending on the build flag -``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in -:ref:`User Guide` for more details). +``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more +details). See also: `Interrupt Controller Abstraction APIs`__. @@ -2796,10 +2794,10 @@ storage access is only required by BL1 and BL2 phases and performed inside the It is mandatory to implement at least one storage driver. For the Arm development platforms the Firmware Image Package (FIP) driver is provided as -the default means to load data from storage (see the "Firmware Image Package" -section in the :ref:`User Guide`). The storage layer is described in the header file -``include/drivers/io/io_storage.h``. The implementation of the common library -is in ``drivers/io/io_storage.c`` and the driver files are located in +the default means to load data from storage (see :ref:`firmware_design_fip`). +The storage layer is described in the header file +``include/drivers/io/io_storage.h``. The implementation of the common library is +in ``drivers/io/io_storage.c`` and the driver files are located in ``drivers/io/``. .. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst new file mode 100644 index 000000000..27ad0ed5f --- /dev/null +++ b/docs/getting_started/prerequisites.rst @@ -0,0 +1,136 @@ +Prerequisites +============= + +This document describes the software requirements for building |TF-A| for +AArch32 and AArch64 target platforms. + +It may possible to build |TF-A| with combinations of software packages that are +different from those listed below, however only the software described in this +document can be officially supported. + +Build Host +---------- + +|TF-A| can be built using either a Linux or a Windows machine as the build host. + +A relatively recent Linux distribution is recommended for building |TF-A|. We +have performed tests using Ubuntu 16.04 LTS (64-bit) but other distributions +should also work fine as a base, provided that the necessary tools and libraries +can be installed. + +.. _prerequisites_toolchain: + +Toolchain +--------- + +|TF-A| can be built with any of the following *cross-compiler* toolchains that +target the Armv7-A or Armv8-A architectures: + +- GCC >= 8.3-2019.03 (from the `Arm Developer website`_) +- Clang >= 4.0 +- Arm Compiler >= 6.0 + +In addition, a native compiler is required to build the supporting tools. + +.. note:: + The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE, + Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain. + +.. note:: + For instructions on how to select the cross compiler refer to + :ref:`Performing an Initial Build`. + +.. _prerequisites_software_and_libraries: + +Software and Libraries +---------------------- + +The following tools are required to obtain and build |TF-A|: + +- An appropriate toolchain (see :ref:`prerequisites_toolchain`) +- GNU Make +- Git + +The following libraries must be available to build one or more components or +supporting tools: + +- OpenSSL >= 1.0.1 + + Required to build the cert_create tool. + +The following libraries are required for Trusted Board Boot support: + +- mbed TLS == 2.16.2 (tag: ``mbedtls-2.16.2``) + +These tools are optional: + +- Device Tree Compiler (DTC) >= 1.4.6 + + Needed if you want to rebuild the provided Flattened Device Tree (FDT) + source files (``.dts`` files). DTC is available for Linux through the package + repositories of most distributions. + +- Arm `Development Studio 5 (DS-5)`_ + + The standard software package used for debugging software on Arm development + platforms and |FVP| models. + +Package Installation (Linux) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +If you are using the recommended Ubuntu distribution then you can install the +required packages with the following command: + +.. code:: shell + + sudo apt install build-essential git libssl-dev + +The optional packages can be installed using: + +.. code:: shell + + sudo apt install device-tree-compiler + +Supporting Files +---------------- + +TF-A has been tested with pre-built binaries and file systems from `Linaro +Release 19.06`_. Alternatively, you can build the binaries from source using +instructions in :ref:`Performing an Initial Build`. + +.. _prerequisites_get_source: + +Getting the TF-A Source +----------------------- + +Source code for |TF-A| is maintained in a Git repository hosted on +TrustedFirmware.org. To clone this repository from the server, run the following +in your shell: + +.. code:: shell + + git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a" && (cd "trusted-firmware-a" && mkdir -p .git/hooks && curl -Lo `git rev-parse --git-dir`/hooks/commit-msg https://review.trustedfirmware.org/tools/hooks/commit-msg; chmod +x `git rev-parse --git-dir`/hooks/commit-msg) + +This will clone the Git repository also install a *commit hook* that +automatically inserts appropriate *Change-Id:* lines at the end of your +commit messages. These change IDs are required when committing changes that you +intend to push for review via our Gerrit system. + +You can read more about Git hooks in the *githooks* page of the Git documentation, +available at: https://git-scm.com/docs/githooks + +Alternatively, you can clone without the commit hook using: + +.. code:: shell + + git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a" + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* + +.. _Arm Developer website: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads +.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes +.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables +.. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio +.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 diff --git a/docs/getting_started/tools-build.rst b/docs/getting_started/tools-build.rst new file mode 100644 index 000000000..bb707cb7c --- /dev/null +++ b/docs/getting_started/tools-build.rst @@ -0,0 +1,140 @@ +Building Supporting Tools +========================= + +Building and using the FIP tool +------------------------------- + +Firmware Image Package (FIP) is a packaging format used by TF-A to package +firmware images in a single binary. The number and type of images that should +be packed in a FIP is platform specific and may include TF-A images and other +firmware images required by the platform. For example, most platforms require +a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or +U-Boot). + +The TF-A build system provides the make target ``fip`` to create a FIP file +for the specified platform using the FIP creation tool included in the TF-A +project. Examples below show how to build a FIP file for FVP, packaging TF-A +and BL33 images. + +For AArch64: + +.. code:: shell + + make PLAT=fvp BL33=/bl33.bin fip + +For AArch32: + +.. code:: shell + + make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=/bl33.bin fip + +The resulting FIP may be found in: + +:: + + build/fvp//fip.bin + +For advanced operations on FIP files, it is also possible to independently build +the tool and create or modify FIPs using this tool. To do this, follow these +steps: + +It is recommended to remove old artifacts before building the tool: + +.. code:: shell + + make -C tools/fiptool clean + +Build the tool: + +.. code:: shell + + make [DEBUG=1] [V=1] fiptool + +The tool binary can be located in: + +:: + + ./tools/fiptool/fiptool + +Invoking the tool with ``help`` will print a help message with all available +options. + +Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31: + +.. code:: shell + + ./tools/fiptool/fiptool create \ + --tb-fw build///bl2.bin \ + --soc-fw build///bl31.bin \ + fip.bin + +Example 2: view the contents of an existing Firmware package: + +.. code:: shell + + ./tools/fiptool/fiptool info /fip.bin + +Example 3: update the entries of an existing Firmware package: + +.. code:: shell + + # Change the BL2 from Debug to Release version + ./tools/fiptool/fiptool update \ + --tb-fw build//release/bl2.bin \ + build//debug/fip.bin + +Example 4: unpack all entries from an existing Firmware package: + +.. code:: shell + + # Images will be unpacked to the working directory + ./tools/fiptool/fiptool unpack /fip.bin + +Example 5: remove an entry from an existing Firmware package: + +.. code:: shell + + ./tools/fiptool/fiptool remove \ + --tb-fw build//debug/fip.bin + +Note that if the destination FIP file exists, the create, update and +remove operations will automatically overwrite it. + +The unpack operation will fail if the images already exist at the +destination. In that case, use -f or --force to continue. + +More information about FIP can be found in the :ref:`Firmware Design` document. + +.. _tools_build_cert_create: + +Building the Certificate Generation Tool +---------------------------------------- + +The ``cert_create`` tool is built as part of the TF-A build process when the +``fip`` make target is specified and TBB is enabled (as described in the +previous section), but it can also be built separately with the following +command: + +.. code:: shell + + make PLAT= [DEBUG=1] [V=1] certtool + +For platforms that require their own IDs in certificate files, the generic +'cert_create' tool can be built with the following command. Note that the target +platform must define its IDs within a ``platform_oid.h`` header file for the +build to succeed. + +.. code:: shell + + make PLAT= USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool + +``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more +verbose. The following command should be used to obtain help about the tool: + +.. code:: shell + + ./tools/cert_create/cert_create -h + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst deleted file mode 100644 index 9876531a7..000000000 --- a/docs/getting_started/user-guide.rst +++ /dev/null @@ -1,2214 +0,0 @@ -User Guide -========== - -This document describes how to build Trusted Firmware-A (TF-A) and run it with a -tested set of other software components using defined configurations on the Juno -Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is -possible to use other software components, configurations and platforms but that -is outside the scope of this document. - -This document assumes that the reader has previous experience running a fully -bootable Linux software stack on Juno or FVP using the prebuilt binaries and -filesystems provided by Linaro. Further information may be found in the -`Linaro instructions`_. It also assumes that the user understands the role of -the different software components required to boot a Linux system: - -- Specific firmware images required by the platform (e.g. SCP firmware on Juno) -- Normal world bootloader (e.g. UEFI or U-Boot) -- Device tree -- Linux kernel image -- Root filesystem - -This document also assumes that the user is familiar with the `FVP models`_ and -the different command line options available to launch the model. - -This document should be used in conjunction with the :ref:`Firmware Design`. - -Host machine requirements -------------------------- - -The minimum recommended machine specification for building the software and -running the FVP models is a dual-core processor running at 2GHz with 12GB of -RAM. For best performance, use a machine with a quad-core processor running at -2.6GHz with 16GB of RAM. - -The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for -building the software were installed from that distribution unless otherwise -specified. - -The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE, -Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain. - -Tools ------ - -Install the required packages to build TF-A with the following command: - -.. code:: shell - - sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev - -Download and install the AArch32 (arm-eabi) or AArch64 little-endian -(aarch64-linux-gnu) GCC 8.3-2019.03 cross compiler from `Arm Developer page`_. - -Optionally, TF-A can be built using clang version 4.0 or newer or Arm -Compiler 6. See instructions below on how to switch the default compiler. - -In addition, the following optional packages and tools may be needed: - -- ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device - Tree (FDT) source files (``.dts`` files) provided with this software. The - version of dtc must be 1.4.6 or above. - -- For debugging, Arm `Development Studio 5 (DS-5)`_. - -- To create and modify the diagram files included in the documentation, `Dia`_. - This tool can be found in most Linux distributions. Inkscape is needed to - generate the actual \*.png files. - -TF-A has been tested with pre-built binaries and file systems from -`Linaro Release 19.06`_. Alternatively, you can build the binaries from -source using instructions provided at the `Arm Platforms User guide`_. - -Getting the TF-A source code ----------------------------- - -Clone the repository from the Gerrit server. The project details may be found -on the `arm-trusted-firmware-a project page`_. We recommend the "`Clone with -commit-msg hook`" clone method, which will setup the git commit hook that -automatically generates and inserts appropriate `Change-Id:` lines in your -commit messages. - -Checking source code style -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the -source, for submission to the project, the source must be in compliance with -this style guide. - -Additional, project-specific guidelines are defined in the -:ref:`Coding Style & Guidelines` document. - -To assist with coding style compliance, the project Makefile contains two -targets which both utilise the `checkpatch.pl` script that ships with the Linux -source tree. The project also defines certain *checkpatch* options in the -``.checkpatch.conf`` file in the top-level directory. - -.. note:: - Checkpatch errors will gate upstream merging of pull requests. - Checkpatch warnings will not gate merging but should be reviewed and fixed if - possible. - -To check the entire source tree, you must first download copies of -``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available -in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH`` -environment variable to point to ``checkpatch.pl`` (with the other 2 files in -the same directory) and build the `checkcodebase` target: - -.. code:: shell - - make CHECKPATCH=/linux/scripts/checkpatch.pl checkcodebase - -To just check the style on the files that differ between your local branch and -the remote master, use: - -.. code:: shell - - make CHECKPATCH=/linux/scripts/checkpatch.pl checkpatch - -If you wish to check your patch against something other than the remote master, -set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT`` -is set to ``origin/master``. - -Building TF-A -------------- - -- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point - to the cross compiler. - - For AArch64: - - .. code:: shell - - export CROSS_COMPILE=/bin/aarch64-linux-gnu- - - For AArch32: - - .. code:: shell - - export CROSS_COMPILE=/bin/arm-eabi- - - It is possible to build TF-A using Clang or Arm Compiler 6. To do so - ``CC`` needs to point to the clang or armclang binary, which will - also select the clang or armclang assembler. Be aware that the - GNU linker is used by default. In case of being needed the linker - can be overridden using the ``LD`` variable. Clang linker version 6 is - known to work with TF-A. - - In both cases ``CROSS_COMPILE`` should be set as described above. - - Arm Compiler 6 will be selected when the base name of the path assigned - to ``CC`` matches the string 'armclang'. - - For AArch64 using Arm Compiler 6: - - .. code:: shell - - export CROSS_COMPILE=/bin/aarch64-linux-gnu- - make CC=/bin/armclang PLAT= all - - Clang will be selected when the base name of the path assigned to ``CC`` - contains the string 'clang'. This is to allow both clang and clang-X.Y - to work. - - For AArch64 using clang: - - .. code:: shell - - export CROSS_COMPILE=/bin/aarch64-linux-gnu- - make CC=/bin/clang PLAT= all - -- Change to the root directory of the TF-A source tree and build. - - For AArch64: - - .. code:: shell - - make PLAT= all - - For AArch32: - - .. code:: shell - - make PLAT= ARCH=aarch32 AARCH32_SP=sp_min all - - Notes: - - - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the - `Summary of build options`_ for more information on available build - options. - - - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it - corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is - provided by TF-A to demonstrate how PSCI Library can be integrated with - an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may - include other runtime services, for example Trusted OS services. A guide - to integrate PSCI library with AArch32 EL3 Runtime Software can be found - at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. - - - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32 - image, is not compiled in by default. Refer to the - `Building the Test Secure Payload`_ section below. - - - By default this produces a release version of the build. To produce a - debug version instead, refer to the "Debugging options" section below. - - - The build process creates products in a ``build`` directory tree, building - the objects and binaries for each boot loader stage in separate - sub-directories. The following boot loader binary files are created - from the corresponding ELF files: - - - ``build///bl1.bin`` - - ``build///bl2.bin`` - - ``build///bl31.bin`` (AArch64 only) - - ``build///bl32.bin`` (mandatory for AArch32) - - where ```` is the name of the chosen platform and ```` - is either ``debug`` or ``release``. The actual number of images might differ - depending on the platform. - -- Build products for a specific build variant can be removed using: - - .. code:: shell - - make DEBUG= PLAT= clean - - ... where ```` is ``0`` or ``1``, as specified when building. - - The build tree can be removed completely using: - - .. code:: shell - - make realclean - -Summary of build options -~~~~~~~~~~~~~~~~~~~~~~~~ - -The TF-A build system supports the following build options. Unless mentioned -otherwise, these options are expected to be specified at the build command -line and are not to be modified in any component makefiles. Note that the -build system doesn't track dependency for build options. Therefore, if any of -the build options are changed from a previous build, a clean build must be -performed. - -Common build options -^^^^^^^^^^^^^^^^^^^^ - -- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the - compiler should use. Valid values are T32 and A32. It defaults to T32 due to - code having a smaller resulting size. - -- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as - as the BL32 image when ``ARCH=aarch32``. The value should be the path to the - directory containing the SP source, relative to the ``bl32/``; the directory - is expected to contain a makefile called ``.mk``. - -- ``ARCH`` : Choose the target build architecture for TF-A. It can take either - ``aarch64`` or ``aarch32`` as values. By default, it is defined to - ``aarch64``. - -- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when - compiling TF-A. Its value must be numeric, and defaults to 8 . See also, - *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in - :ref:`Firmware Design`. - -- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when - compiling TF-A. Its value must be a numeric, and defaults to 0. See also, - *Armv8 Architecture Extensions* in :ref:`Firmware Design`. - -- ``BL2``: This is an optional build option which specifies the path to BL2 - image for the ``fip`` target. In this case, the BL2 in the TF-A will not be - built. - -- ``BL2U``: This is an optional build option which specifies the path to - BL2U image. In this case, the BL2U in TF-A will not be built. - -- ``BL2_AT_EL3``: This is an optional build option that enables the use of - BL2 at EL3 execution level. - -- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place - (XIP) memory, like BL1. In these use-cases, it is necessary to initialize - the RW sections in RAM, while leaving the RO sections in place. This option - enable this use-case. For now, this option is only supported when BL2_AT_EL3 - is set to '1'. - -- ``BL2_INV_DCACHE``: This is an optional build option which control dcache - invalidation upon BL2 entry. Some platform cannot handle cache operations - during entry as the coherency unit is not yet initialized. This may cause - crashing. Leaving this option to '1' (default) will allow the operation. - This option is only relevant when BL2_AT_EL3 is set to '1'. - -- ``BL31``: This is an optional build option which specifies the path to - BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not - be built. - -- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the - file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, - this file name will be used to save the key. - -- ``BL32``: This is an optional build option which specifies the path to - BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not - be built. - -- ``BL32_EXTRA1``: This is an optional build option which specifies the path to - Trusted OS Extra1 image for the ``fip`` target. - -- ``BL32_EXTRA2``: This is an optional build option which specifies the path to - Trusted OS Extra2 image for the ``fip`` target. - -- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the - file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, - this file name will be used to save the key. - -- ``BL33``: Path to BL33 image in the host file system. This is mandatory for - ``fip`` target in case TF-A BL2 is used. - -- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the - file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, - this file name will be used to save the key. - -- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication - and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. - If enabled, it is needed to use a compiler (e.g GCC 9.1 and later versions) that - supports the option ``-mbranch-protection``. - Selects the branch protection features to use: -- 0: Default value turns off all types of branch protection -- 1: Enables all types of branch protection features -- 2: Return address signing to its standard level -- 3: Extend the signing to include leaf functions - - The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options - and resulting PAuth/BTI features. - - +-------+--------------+-------+-----+ - | Value | GCC option | PAuth | BTI | - +=======+==============+=======+=====+ - | 0 | none | N | N | - +-------+--------------+-------+-----+ - | 1 | standard | Y | Y | - +-------+--------------+-------+-----+ - | 2 | pac-ret | Y | N | - +-------+--------------+-------+-----+ - | 3 | pac-ret+leaf | Y | N | - +-------+--------------+-------+-----+ - - This option defaults to 0 and this is an experimental feature. - Note that Pointer Authentication is enabled for Non-secure world - irrespective of the value of this option if the CPU supports it. - -- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the - compilation of each build. It must be set to a C string (including quotes - where applicable). Defaults to a string that contains the time and date of - the compilation. - -- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A - build to be uniquely identified. Defaults to the current git commit id. - -- ``CFLAGS``: Extra user options appended on the compiler's command line in - addition to the options set by the build system. - -- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may - release several CPUs out of reset. It can take either 0 (several CPUs may be - brought up) or 1 (only one CPU will ever be brought up during cold reset). - Default is 0. If the platform always brings up a single CPU, there is no - need to distinguish between primary and secondary CPUs and the boot path can - be optimised. The ``plat_is_my_cpu_primary()`` and - ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need - to be implemented in this case. - -- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor - register state when an unexpected exception occurs during execution of - BL31. This option defaults to the value of ``DEBUG`` - i.e. by default - this is only enabled for a debug build of the firmware. - -- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the - certificate generation tool to create new keys in case no valid keys are - present or specified. Allowed options are '0' or '1'. Default is '1'. - -- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause - the AArch32 system registers to be included when saving and restoring the - CPU context. The option must be set to 0 for AArch64-only platforms (that - is on hardware that does not implement AArch32, or at least not at EL1 and - higher ELs). Default value is 1. - -- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP - registers to be included when saving and restoring the CPU context. Default - is 0. - -- ``CTX_INCLUDE_MTE_REGS``: Enables register saving/reloading support for - ARMv8.5 Memory Tagging Extension. A value of 0 will disable - saving/reloading and restrict the use of MTE to the normal world if the - CPU has support, while a value of 1 enables the saving/reloading, allowing - the use of MTE in both the secure and non-secure worlds. Default is 0 - (disabled) and this feature is experimental. - -- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables - Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth - registers to be included when saving and restoring the CPU context as - part of world switch. Default value is 0 and this is an experimental feature. - Note that Pointer Authentication is enabled for Non-secure world irrespective - of the value of this flag if the CPU supports it. - -- ``DEBUG``: Chooses between a debug and release build. It can take either 0 - (release) or 1 (debug) as values. 0 is the default. - -- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation - of the binary image. If set to 1, then only the ELF image is built. - 0 is the default. - -- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted - Board Boot authentication at runtime. This option is meant to be enabled only - for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this - flag has to be enabled. 0 is the default. - -- ``E``: Boolean option to make warnings into errors. Default is 1. - -- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of - the normal boot flow. It must specify the entry point address of the EL3 - payload. Please refer to the "Booting an EL3 payload" section for more - details. - -- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. - This is an optional architectural feature available on v8.4 onwards. Some - v8.2 implementations also implement an AMU and this option can be used to - enable this feature on those systems as well. Default is 0. - -- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` - are compiled out. For debug builds, this option defaults to 1, and calls to - ``assert()`` are left in place. For release builds, this option defaults to 0 - and calls to ``assert()`` function are compiled out. This option can be set - independently of ``DEBUG``. It can also be used to hide any auxiliary code - that is only required for the assertion and does not fit in the assertion - itself. - -- ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace - dumps or not. It is supported in both AArch64 and AArch32. However, in - AArch32 the format of the frame records are not defined in the AAPCS and they - are defined by the implementation. This implementation of backtrace only - supports the format used by GCC when T32 interworking is disabled. For this - reason enabling this option in AArch32 will force the compiler to only - generate A32 code. This option is enabled by default only in AArch64 debug - builds, but this behaviour can be overridden in each platform's Makefile or - in the build command line. - -- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM - feature. MPAM is an optional Armv8.4 extension that enables various memory - system components and resources to define partitions; software running at - various ELs can assign themselves to desired partition to control their - performance aspects. - - When this option is set to ``1``, EL3 allows lower ELs to access their own - MPAM registers without trapping into EL3. This option doesn't make use of - partitioning in EL3, however. Platform initialisation code should configure - and use partitions in EL3 as required. This option defaults to ``0``. - -- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) - support within generic code in TF-A. This option is currently only supported - in BL31. Default is 0. - -- ``ENABLE_PMF``: Boolean option to enable support for optional Performance - Measurement Framework(PMF). Default is 0. - -- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI - functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. - In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must - be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in - software. - -- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime - instrumentation which injects timestamp collection points into TF-A to - allow runtime performance to be measured. Currently, only PSCI is - instrumented. Enabling this option enables the ``ENABLE_PMF`` build option - as well. Default is 0. - -- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling - extensions. This is an optional architectural feature for AArch64. - The default is 1 but is automatically disabled when the target architecture - is AArch32. - -- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM). - Refer to :ref:`Secure Partition Manager` for more details about - this feature. Default is 0. - -- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension - (SVE) for the Non-secure world only. SVE is an optional architectural feature - for AArch64. Note that when SVE is enabled for the Non-secure world, access - to SIMD and floating-point functionality from the Secure world is disabled. - This is to avoid corruption of the Non-secure world data in the Z-registers - which are aliased by the SIMD and FP registers. The build option is not - compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an - assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to - 1. The default is 1 but is automatically disabled when the target - architecture is AArch32. - -- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection - checks in GCC. Allowed values are "all", "strong", "default" and "none". The - default value is set to "none". "strong" is the recommended stack protection - level if this feature is desired. "none" disables the stack protection. For - all values other than "none", the ``plat_get_stack_protector_canary()`` - platform hook needs to be implemented. The value is passed as the last - component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. - -- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of - deprecated platform APIs, helper functions or drivers within Trusted - Firmware as error. It can take the value 1 (flag the use of deprecated - APIs as error) or 0. The default is 0. - -- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions - targeted at EL3. When set ``0`` (default), no exceptions are expected or - handled at EL3, and a panic will result. This is supported only for AArch64 - builds. - -- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault - injection from lower ELs, and this build option enables lower ELs to use - Error Records accessed via System Registers to inject faults. This is - applicable only to AArch64 builds. - - This feature is intended for testing purposes only, and is advisable to keep - disabled for production images. - -- ``FIP_NAME``: This is an optional build option which specifies the FIP - filename for the ``fip`` target. Default is ``fip.bin``. - -- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU - FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. - -- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` - tool to create certificates as per the Chain of Trust described in - :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to - include the certificates in the FIP and FWU_FIP. Default value is '0'. - - Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support - for the Trusted Board Boot feature in the BL1 and BL2 images, to generate - the corresponding certificates, and to include those certificates in the - FIP and FWU_FIP. - - Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 - images will not include support for Trusted Board Boot. The FIP will still - include the corresponding certificates. This FIP can be used to verify the - Chain of Trust on the host machine through other mechanisms. - - Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 - images will include support for Trusted Board Boot, but the FIP and FWU_FIP - will not include the corresponding certificates, causing a boot failure. - -- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have - inherent support for specific EL3 type interrupts. Setting this build option - to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both - by `platform abstraction layer`__ and `Interrupt Management Framework`__. - This allows GICv2 platforms to enable features requiring EL3 interrupt type. - This also means that all GICv2 Group 0 interrupts are delivered to EL3, and - the Secure Payload interrupts needs to be synchronously handed over to Secure - EL1 for handling. The default value of this option is ``0``, which means the - Group 0 interrupts are assumed to be handled by Secure EL1. - - .. __: `platform-interrupt-controller-API.rst` - .. __: `interrupt-framework-design.rst` - -- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError - Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to - ``0`` (default), these exceptions will be trapped in the current exception - level (or in EL1 if the current exception level is EL0). - -- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific - software operations are required for CPUs to enter and exit coherency. - However, newer systems exist where CPUs' entry to and exit from coherency - is managed in hardware. Such systems require software to only initiate these - operations, and the rest is managed in hardware, minimizing active software - management. In such systems, this boolean option enables TF-A to carry out - build and run-time optimizations during boot and power management operations. - This option defaults to 0 and if it is enabled, then it implies - ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. - - If this flag is disabled while the platform which TF-A is compiled for - includes cores that manage coherency in hardware, then a compilation error is - generated. This is based on the fact that a system cannot have, at the same - time, cores that manage coherency in hardware and cores that don't. In other - words, a platform cannot have, at the same time, cores that require - ``HW_ASSISTED_COHERENCY=1`` and cores that require - ``HW_ASSISTED_COHERENCY=0``. - - Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of - translation library (xlat tables v2) must be used; version 1 of translation - library is not supported. - -- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 - runtime software in AArch32 mode, which is required to run AArch32 on Juno. - By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in - AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable - images. - -- ``KEY_ALG``: This build flag enables the user to select the algorithm to be - used for generating the PKCS keys and subsequent signing of the certificate. - It accepts 2 values: ``rsa`` and ``ecdsa``. The default value of this flag - is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. - -- ``KEY_SIZE``: This build flag enables the user to select the key size for - the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` - depend on the chosen algorithm. - - +-----------+------------------------------------+ - | KEY_ALG | Possible key sizes | - +===========+====================================+ - | rsa | 1024, 2048 (default), 3072, 4096 | - +-----------+------------------------------------+ - | ecdsa | unavailable | - +-----------+------------------------------------+ - -- ``HASH_ALG``: This build flag enables the user to select the secure hash - algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. - The default value of this flag is ``sha256``. - -- ``LDFLAGS``: Extra user options appended to the linkers' command line in - addition to the one set by the build system. - -- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log - output compiled into the build. This should be one of the following: - - :: - - 0 (LOG_LEVEL_NONE) - 10 (LOG_LEVEL_ERROR) - 20 (LOG_LEVEL_NOTICE) - 30 (LOG_LEVEL_WARNING) - 40 (LOG_LEVEL_INFO) - 50 (LOG_LEVEL_VERBOSE) - - All log output up to and including the selected log level is compiled into - the build. The default value is 40 in debug builds and 20 in release builds. - -- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It - specifies the file that contains the Non-Trusted World private key in PEM - format. If ``SAVE_KEYS=1``, this file name will be used to save the key. - -- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is - optional. It is only needed if the platform makefile specifies that it - is required in order to build the ``fwu_fip`` target. - -- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register - contents upon world switch. It can take either 0 (don't save and restore) or - 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it - wants the timer registers to be saved and restored. - -- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc - for the BL image. It can be either 0 (include) or 1 (remove). The default - value is 0. - -- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that - the underlying hardware is not a full PL011 UART but a minimally compliant - generic UART, which is a subset of the PL011. The driver will not access - any register that is not part of the SBSA generic UART specification. - Default value is 0 (a full PL011 compliant UART is present). - -- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name - must be subdirectory of any depth under ``plat/``, and must contain a - platform makefile named ``platform.mk``. For example, to build TF-A for the - Arm Juno board, select PLAT=juno. - -- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image - instead of the normal boot flow. When defined, it must specify the entry - point address for the preloaded BL33 image. This option is incompatible with - ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority - over ``PRELOADED_BL33_BASE``. - -- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset - vector address can be programmed or is fixed on the platform. It can take - either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a - programmable reset address, it is expected that a CPU will start executing - code directly at the right address, both on a cold and warm reset. In this - case, there is no need to identify the entrypoint on boot and the boot path - can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface - does not need to be implemented in this case. - -- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats - possible for the PSCI power-state parameter: original and extended State-ID - formats. This flag if set to 1, configures the generic PSCI layer to use the - extended format. The default value of this flag is 0, which means by default - the original power-state format is used by the PSCI implementation. This flag - should be specified by the platform makefile and it governs the return value - of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is - enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be - set to 1 as well. - -- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features - are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 - or later CPUs. - - When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be - set to ``1``. - - This option is disabled by default. - -- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead - of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 - entrypoint) or 1 (CPU reset to BL31 entrypoint). - The default value is 0. - -- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided - in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector - instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 - entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. - -- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the - file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this - file name will be used to save the key. - -- ``SANITIZE_UB``: This option enables the Undefined Behaviour sanitizer. It - can take 3 values: 'off' (default), 'on' and 'trap'. When using 'trap', - gcc and clang will insert calls to ``__builtin_trap`` on detected - undefined behaviour, which defaults to a ``brk`` instruction. When using - 'on', undefined behaviour is translated to a call to special handlers which - prints the exact location of the problem and its cause and then panics. - - .. note:: - Because of the space penalty of the Undefined Behaviour sanitizer, - this option will increase the size of the binary. Depending on the - memory constraints of the target platform, it may not be possible to - enable the sanitizer for all images (BL1 and BL2 are especially - likely to be memory constrained). We recommend that the - sanitizer is enabled only in debug builds. - -- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the - certificate generation tool to save the keys used to establish the Chain of - Trust. Allowed options are '0' or '1'. Default is '0' (do not save). - -- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. - If a SCP_BL2 image is present then this option must be passed for the ``fip`` - target. - -- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the - file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, - this file name will be used to save the key. - -- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is - optional. It is only needed if the platform makefile specifies that it - is required in order to build the ``fwu_fip`` target. - -- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software - Delegated Exception Interface to BL31 image. This defaults to ``0``. - - When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be - set to ``1``. - -- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be - isolated on separate memory pages. This is a trade-off between security and - memory usage. See "Isolating code and read-only data on separate memory - pages" section in :ref:`Firmware Design`. This flag is disabled by default - and affects all BL images. - -- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. - This build option is only valid if ``ARCH=aarch64``. The value should be - the path to the directory containing the SPD source, relative to - ``services/spd/``; the directory is expected to contain a makefile called - ``.mk``. - -- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can - take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops - execution in BL1 just before handing over to BL31. At this point, all - firmware images have been loaded in memory, and the MMU and caches are - turned off. Refer to the "Debugging options" section for more details. - -- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles - secure interrupts (caught through the FIQ line). Platforms can enable - this directive if they need to handle such interruption. When enabled, - the FIQ are handled in monitor mode and non secure world is not allowed - to mask these events. Platforms that enable FIQ handling in SP_MIN shall - implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. - -- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board - Boot feature. When set to '1', BL1 and BL2 images include support to load - and verify the certificates and images in a FIP, and BL1 includes support - for the Firmware Update. The default value is '0'. Generation and inclusion - of certificates in the FIP and FWU_FIP depends upon the value of the - ``GENERATE_COT`` option. - - .. warning:: - This option depends on ``CREATE_KEYS`` to be enabled. If the keys - already exist in disk, they will be overwritten without further notice. - -- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It - specifies the file that contains the Trusted World private key in PEM - format. If ``SAVE_KEYS=1``, this file name will be used to save the key. - -- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or - synchronous, (see "Initializing a BL32 Image" section in - :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using - synchronous method) or 1 (BL32 is initialized using asynchronous method). - Default is 0. - -- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt - routing model which routes non-secure interrupts asynchronously from TSP - to EL3 causing immediate preemption of TSP. The EL3 is responsible - for saving and restoring the TSP context in this routing model. The - default routing model (when the value is 0) is to route non-secure - interrupts to TSP allowing it to save its context and hand over - synchronously to EL3 via an SMC. - - .. note:: - When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` - must also be set to ``1``. - -- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM - linker. When the ``LINKER`` build variable points to the armlink linker, - this flag is enabled automatically. To enable support for armlink, platforms - will have to provide a scatter file for the BL image. Currently, Tegra - platforms use the armlink support to compile BL3-1 images. - -- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent - memory region in the BL memory map or not (see "Use of Coherent memory in - TF-A" section in :ref:`Firmware Design`). It can take the value 1 - (Coherent memory region is included) or 0 (Coherent memory region is - excluded). Default is 1. - -- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. - This feature creates a library of functions to be placed in ROM and thus - reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. - Default is 0. - -- ``USE_SPINLOCK_CAS``: Setting this build flag to 1 selects the spinlock - implementation variant using the ARMv8.1-LSE compare-and-swap instruction. - Notice this option is experimental and only available to AArch64 builds. - -- ``V``: Verbose build. If assigned anything other than 0, the build commands - are printed. Default is 0. - -- ``VERSION_STRING``: String used in the log output for each TF-A image. - Defaults to a string formed by concatenating the version number, build type - and build string. - -- ``W``: Warning level. Some compiler warning options of interest have been - regrouped and put in the root Makefile. This flag can take the values 0 to 3, - each level enabling more warning options. Default is 0. - -- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on - the CPU after warm boot. This is applicable for platforms which do not - require interconnect programming to enable cache coherency (eg: single - cluster platforms). If this option is enabled, then warm boot path - enables D-caches immediately after enabling MMU. This option defaults to 0. - -Arm development platform specific build options -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured - DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load - BL31 in TZC secured DRAM. If TSP is present, then setting this option also - sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build - flag. - -- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase`` - frame registers by setting the ``CNTCTLBase.CNTACR`` register bits. The - frame number ```` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should - match the frame used by the Non-Secure image (normally the Linux kernel). - Default is true (access to the frame is allowed). - -- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog. - By default, Arm platforms use a watchdog to trigger a system reset in case - an error is encountered during the boot process (for example, when an image - could not be loaded or authenticated). The watchdog is enabled in the early - platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The - Trusted Watchdog may be disabled at build time for testing or development - purposes. - -- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to - have specific values at boot. This boolean option allows the Trusted Firmware - to have a Linux kernel image as BL33 by preparing the registers to these - values before jumping to BL33. This option defaults to 0 (disabled). For - AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when - using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set - to the location of a device tree blob (DTB) already loaded in memory. The - Linux Image address must be specified using the ``PRELOADED_BL33_BASE`` - option. - -- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to - cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag - is set, the functions which deal with MPIDR assume that the ``MT`` bit in - MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of - this flag is 0. Note that this option is not used on FVP platforms. - -- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding - for the construction of composite state-ID in the power-state parameter. - The existing PSCI clients currently do not support this encoding of - State-ID yet. Hence this flag is used to configure whether to use the - recommended State-ID encoding or not. The default value of this flag is 0, - in which case the platform is configured to expect NULL in the State-ID - field of power-state parameter. - -- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the - location of the ROTPK hash returned by the function ``plat_get_rotpk_info()`` - for Arm platforms. Depending on the selected option, the proper private key - must be specified using the ``ROT_KEY`` option when building the Trusted - Firmware. This private key will be used by the certificate generation tool - to sign the BL2 and Trusted Key certificates. Available options for - ``ARM_ROTPK_LOCATION`` are: - - - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage - registers. The private key corresponding to this ROTPK hash is not - currently available. - - ``devel_rsa`` : return a development public key hash embedded in the BL1 - and BL2 binaries. This hash has been obtained from the RSA public key - ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use - this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when - creating the certificates. - - ``devel_ecdsa`` : return a development public key hash embedded in the BL1 - and BL2 binaries. This hash has been obtained from the ECDSA public key - ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use - this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY`` - when creating the certificates. - -- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options: - - - ``tsram`` : Trusted SRAM (default option when TBB is not enabled) - - ``tdram`` : Trusted DRAM (if available) - - ``dram`` : Secure region in DRAM (default option when TBB is enabled, - configured by the TrustZone controller) - -- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1 - of the translation tables library instead of version 2. It is set to 0 by - default, which selects version 2. - -- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm® - TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm - platforms. If this option is specified, then the path to the CryptoCell - SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag. - -For a better understanding of these options, the Arm development platform memory -map is explained in the :ref:`Firmware Design`. - -Arm CSS platform specific build options -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version - incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards - compatible change to the MTL protocol, used for AP/SCP communication. - TF-A no longer supports earlier SCP versions. If this option is set to 1 - then TF-A will detect if an earlier version is in use. Default is 1. - -- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and - SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded - during boot. Default is 1. - -- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers - instead of SCPI/BOM driver for communicating with the SCP during power - management operations and for SCP RAM Firmware transfer. If this option - is set to 1, then SCMI/SDS drivers will be used. Default is 0. - -Arm FVP platform specific build options -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to - build the topology tree within TF-A. By default TF-A is configured for dual - cluster topology and this option can be used to override the default value. - -- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The - default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as - explained in the options below: - - - ``FVP_CCI`` : The CCI driver is selected. This is the default - if 0 < ``FVP_CLUSTER_COUNT`` <= 2. - - ``FVP_CCN`` : The CCN driver is selected. This is the default - if ``FVP_CLUSTER_COUNT`` > 2. - -- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in - a single cluster. This option defaults to 4. - -- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU - in the system. This option defaults to 1. Note that the build option - ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. - -- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: - - - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected - - ``FVP_GICV2`` : The GICv2 only driver is selected - - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) - -- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer - for functions that wait for an arbitrary time length (udelay and mdelay). - The default value is 0. - -- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled - to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for - details on HW_CONFIG. By default, this is initialized to a sensible DTS - file in ``fdts/`` folder depending on other build options. But some cases, - like shifted affinity format for MPIDR, cannot be detected at build time - and this option is needed to specify the appropriate DTS file. - -- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in - FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is - similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the - HW_CONFIG blob instead of the DTS file. This option is useful to override - the default HW_CONFIG selected by the build system. - -ARM JUNO platform specific build options -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone - Media Protection (TZ-MP1). Default value of this flag is 0. - -Debugging options -~~~~~~~~~~~~~~~~~ - -To compile a debug version and make the build more verbose use - -.. code:: shell - - make PLAT= DEBUG=1 V=1 all - -AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for -example DS-5) might not support this and may need an older version of DWARF -symbols to be emitted by GCC. This can be achieved by using the -``-gdwarf-`` flag, with the version being set to 2 or 3. Setting the -version to 2 is recommended for DS-5 versions older than 5.16. - -When debugging logic problems it might also be useful to disable all compiler -optimizations by using ``-O0``. - -.. warning:: - Using ``-O0`` could cause output images to be larger and base addresses - might need to be recalculated (see the **Memory layout on Arm development - platforms** section in the :ref:`Firmware Design`). - -Extra debug options can be passed to the build system by setting ``CFLAGS`` or -``LDFLAGS``: - -.. code:: shell - - CFLAGS='-O0 -gdwarf-2' \ - make PLAT= DEBUG=1 V=1 all - -Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be -ignored as the linker is called directly. - -It is also possible to introduce an infinite loop to help in debugging the -post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the -``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_ -section. In this case, the developer may take control of the target using a -debugger when indicated by the console output. When using DS-5, the following -commands can be used: - -:: - - # Stop target execution - interrupt - - # - # Prepare your debugging environment, e.g. set breakpoints - # - - # Jump over the debug loop - set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 - - # Resume execution - continue - -Building the Test Secure Payload -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The TSP is coupled with a companion runtime service in the BL31 firmware, -called the TSPD. Therefore, if you intend to use the TSP, the BL31 image -must be recompiled as well. For more information on SPs and SPDs, see the -:ref:`Secure-EL1 Payloads and Dispatchers ` section -in the :ref:`Firmware Design` document. - -First clean the TF-A build directory to get rid of any previous BL31 binary. -Then to build the TSP image use: - -.. code:: shell - - make PLAT= SPD=tspd all - -An additional boot loader binary file is created in the ``build`` directory: - -:: - - build///bl32.bin - - -Building and using the FIP tool -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Firmware Image Package (FIP) is a packaging format used by TF-A to package -firmware images in a single binary. The number and type of images that should -be packed in a FIP is platform specific and may include TF-A images and other -firmware images required by the platform. For example, most platforms require -a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or -U-Boot). - -The TF-A build system provides the make target ``fip`` to create a FIP file -for the specified platform using the FIP creation tool included in the TF-A -project. Examples below show how to build a FIP file for FVP, packaging TF-A -and BL33 images. - -For AArch64: - -.. code:: shell - - make PLAT=fvp BL33=/bl33.bin fip - -For AArch32: - -.. code:: shell - - make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=/bl33.bin fip - -The resulting FIP may be found in: - -:: - - build/fvp//fip.bin - -For advanced operations on FIP files, it is also possible to independently build -the tool and create or modify FIPs using this tool. To do this, follow these -steps: - -It is recommended to remove old artifacts before building the tool: - -.. code:: shell - - make -C tools/fiptool clean - -Build the tool: - -.. code:: shell - - make [DEBUG=1] [V=1] fiptool - -The tool binary can be located in: - -:: - - ./tools/fiptool/fiptool - -Invoking the tool with ``help`` will print a help message with all available -options. - -Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31: - -.. code:: shell - - ./tools/fiptool/fiptool create \ - --tb-fw build///bl2.bin \ - --soc-fw build///bl31.bin \ - fip.bin - -Example 2: view the contents of an existing Firmware package: - -.. code:: shell - - ./tools/fiptool/fiptool info /fip.bin - -Example 3: update the entries of an existing Firmware package: - -.. code:: shell - - # Change the BL2 from Debug to Release version - ./tools/fiptool/fiptool update \ - --tb-fw build//release/bl2.bin \ - build//debug/fip.bin - -Example 4: unpack all entries from an existing Firmware package: - -.. code:: shell - - # Images will be unpacked to the working directory - ./tools/fiptool/fiptool unpack /fip.bin - -Example 5: remove an entry from an existing Firmware package: - -.. code:: shell - - ./tools/fiptool/fiptool remove \ - --tb-fw build//debug/fip.bin - -Note that if the destination FIP file exists, the create, update and -remove operations will automatically overwrite it. - -The unpack operation will fail if the images already exist at the -destination. In that case, use -f or --force to continue. - -More information about FIP can be found in the :ref:`Firmware Design` document. - -Building FIP images with support for Trusted Board Boot -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Trusted Board Boot primarily consists of the following two features: - -- Image Authentication, described in :ref:`Trusted Board Boot`, and -- Firmware Update, described in :ref:`Firmware Update (FWU)` - -The following steps should be followed to build FIP and (optionally) FWU_FIP -images with support for these features: - -#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser - modules by checking out a recent version of the `mbed TLS Repository`_. It - is important to use a version that is compatible with TF-A and fixes any - known security vulnerabilities. See `mbed TLS Security Center`_ for more - information. The latest version of TF-A is tested with tag - ``mbedtls-2.16.2``. - - The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS - source files the modules depend upon. - ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration - options required to build the mbed TLS sources. - - Note that the mbed TLS library is licensed under the Apache version 2.0 - license. Using mbed TLS source code will affect the licensing of TF-A - binaries that are built using this library. - -#. To build the FIP image, ensure the following command line variables are set - while invoking ``make`` to build TF-A: - - - ``MBEDTLS_DIR=`` - - ``TRUSTED_BOARD_BOOT=1`` - - ``GENERATE_COT=1`` - - In the case of Arm platforms, the location of the ROTPK hash must also be - specified at build time. Two locations are currently supported (see - ``ARM_ROTPK_LOCATION`` build option): - - - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted - root-key storage registers present in the platform. On Juno, this - registers are read-only. On FVP Base and Cortex models, the registers - are read-only, but the value can be specified using the command line - option ``bp.trusted_key_storage.public_key`` when launching the model. - On both Juno and FVP models, the default value corresponds to an - ECDSA-SECP256R1 public key hash, whose private part is not currently - available. - - - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded - in the Arm platform port. The private/public RSA key pair may be - found in ``plat/arm/board/common/rotpk``. - - - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded - in the Arm platform port. The private/public ECDSA key pair may be - found in ``plat/arm/board/common/rotpk``. - - Example of command line using RSA development keys: - - .. code:: shell - - MBEDTLS_DIR= \ - make PLAT= TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ - ARM_ROTPK_LOCATION=devel_rsa \ - ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ - BL33=/ \ - all fip - - The result of this build will be the bl1.bin and the fip.bin binaries. This - FIP will include the certificates corresponding to the Chain of Trust - described in the TBBR-client document. These certificates can also be found - in the output build directory. - -#. The optional FWU_FIP contains any additional images to be loaded from - Non-Volatile storage during the :ref:`Firmware Update (FWU)` process. To - build the FWU_FIP, any FWU images required by the platform must be specified - on the command line. On Arm development platforms like Juno, these are: - - - NS_BL2U. The AP non-secure Firmware Updater image. - - SCP_BL2U. The SCP Firmware Update Configuration image. - - Example of Juno command line for generating both ``fwu`` and ``fwu_fip`` - targets using RSA development: - - :: - - MBEDTLS_DIR= \ - make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ - ARM_ROTPK_LOCATION=devel_rsa \ - ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ - BL33=/ \ - SCP_BL2=/ \ - SCP_BL2U=/ \ - NS_BL2U=/ \ - all fip fwu_fip - - .. note:: - The BL2U image will be built by default and added to the FWU_FIP. - The user may override this by adding ``BL2U=/`` - to the command line above. - - .. note:: - Building and installing the non-secure and SCP FWU images (NS_BL1U, - NS_BL2U and SCP_BL2U) is outside the scope of this document. - - The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries. - Both the FIP and FWU_FIP will include the certificates corresponding to the - Chain of Trust described in the TBBR-client document. These certificates - can also be found in the output build directory. - -Building the Certificate Generation Tool -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The ``cert_create`` tool is built as part of the TF-A build process when the -``fip`` make target is specified and TBB is enabled (as described in the -previous section), but it can also be built separately with the following -command: - -.. code:: shell - - make PLAT= [DEBUG=1] [V=1] certtool - -For platforms that require their own IDs in certificate files, the generic -'cert_create' tool can be built with the following command. Note that the target -platform must define its IDs within a ``platform_oid.h`` header file for the -build to succeed. - -.. code:: shell - - make PLAT= USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool - -``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more -verbose. The following command should be used to obtain help about the tool: - -.. code:: shell - - ./tools/cert_create/cert_create -h - -Building a FIP for Juno and FVP -------------------------------- - -This section provides Juno and FVP specific instructions to build Trusted -Firmware, obtain the additional required firmware, and pack it all together in -a single FIP binary. It assumes that a `Linaro Release`_ has been installed. - -.. note:: - Pre-built binaries for AArch32 are available from Linaro Release 16.12 - onwards. Before that release, pre-built binaries are only available for - AArch64. - -.. warning:: - Follow the full instructions for one platform before switching to a - different one. Mixing instructions for different platforms may result in - corrupted binaries. - -.. warning:: - The uboot image downloaded by the Linaro workspace script does not always - match the uboot image packaged as BL33 in the corresponding fip file. It is - recommended to use the version that is packaged in the fip file using the - instructions below. - -.. note:: - For the FVP, the kernel FDT is packaged in FIP during build and loaded - by the firmware at runtime. See `Obtaining the Flattened Device Trees`_ - section for more info on selecting the right FDT to use. - -#. Clean the working directory - - .. code:: shell - - make realclean - -#. Obtain SCP_BL2 (Juno) and BL33 (all platforms) - - Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP - package included in the Linaro release: - - .. code:: shell - - # Build the fiptool - make [DEBUG=1] [V=1] fiptool - - # Unpack firmware images from Linaro FIP - ./tools/fiptool/fiptool unpack /[SOFTWARE]/fip.bin - - The unpack operation will result in a set of binary images extracted to the - current working directory. The SCP_BL2 image corresponds to - ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``. - - .. note:: - The fiptool will complain if the images to be unpacked already - exist in the current directory. If that is the case, either delete those - files or use the ``--force`` option to overwrite. - - .. note:: - For AArch32, the instructions below assume that nt-fw.bin is a - normal world boot loader that supports AArch32. - -#. Build TF-A images and create a new FIP for FVP - - .. code:: shell - - # AArch64 - make PLAT=fvp BL33=nt-fw.bin all fip - - # AArch32 - make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip - -#. Build TF-A images and create a new FIP for Juno - - For AArch64: - - Building for AArch64 on Juno simply requires the addition of ``SCP_BL2`` - as a build parameter. - - .. code:: shell - - make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip - - For AArch32: - - Hardware restrictions on Juno prevent cold reset into AArch32 execution mode, - therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled - separately for AArch32. - - - Before building BL32, the environment variable ``CROSS_COMPILE`` must point - to the AArch32 cross compiler. - - .. code:: shell - - export CROSS_COMPILE=/bin/arm-eabi- - - - Build BL32 in AArch32. - - .. code:: shell - - make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \ - RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32 - - - Save ``bl32.bin`` to a temporary location and clean the build products. - - :: - - cp /bl32.bin - make realclean - - - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE`` - must point to the AArch64 cross compiler. - - .. code:: shell - - export CROSS_COMPILE=/bin/aarch64-linux-gnu- - - - The following parameters should be used to build BL1 and BL2 in AArch64 - and point to the BL32 file. - - .. code:: shell - - make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \ - BL33=nt-fw.bin SCP_BL2=scp-fw.bin \ - BL32=/bl32.bin all fip - -The resulting BL1 and FIP images may be found in: - -:: - - # Juno - ./build/juno/release/bl1.bin - ./build/juno/release/fip.bin - - # FVP - ./build/fvp/release/bl1.bin - ./build/fvp/release/fip.bin - - -Booting Firmware Update images -------------------------------------- - -When Firmware Update (FWU) is enabled there are at least 2 new images -that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the -FWU FIP. - -Juno -~~~~ - -The new images must be programmed in flash memory by adding -an entry in the ``SITE1/HBI0262x/images.txt`` configuration file -on the Juno SD card (where ``x`` depends on the revision of the Juno board). -Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory -programming" for more information. User should ensure these do not -overlap with any other entries in the file. - -:: - - NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE - NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address] - NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name - NOR10LOAD: 00000000 ;Image Load Address - NOR10ENTRY: 00000000 ;Image Entry Point - - NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE - NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address] - NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name - NOR11LOAD: 00000000 ;Image Load Address - -The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000. -In the same way, the address ns_bl2u_base_address is the value of -NS_BL2U_BASE - 0x8000000. - -FVP -~~~ - -The additional fip images must be loaded with: - -:: - - --data cluster0.cpu0="/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] - --data cluster0.cpu0="/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] - -The address ns_bl1u_base_address is the value of NS_BL1U_BASE. -In the same way, the address ns_bl2u_base_address is the value of -NS_BL2U_BASE. - - -EL3 payloads alternative boot flow ----------------------------------- - -On a pre-production system, the ability to execute arbitrary, bare-metal code at -the highest exception level is required. It allows full, direct access to the -hardware, for example to run silicon soak tests. - -Although it is possible to implement some baremetal secure firmware from -scratch, this is a complex task on some platforms, depending on the level of -configuration required to put the system in the expected state. - -Rather than booting a baremetal application, a possible compromise is to boot -``EL3 payloads`` through TF-A instead. This is implemented as an alternative -boot flow, where a modified BL2 boots an EL3 payload, instead of loading the -other BL images and passing control to BL31. It reduces the complexity of -developing EL3 baremetal code by: - -- putting the system into a known architectural state; -- taking care of platform secure world initialization; -- loading the SCP_BL2 image if required by the platform. - -When booting an EL3 payload on Arm standard platforms, the configuration of the -TrustZone controller is simplified such that only region 0 is enabled and is -configured to permit secure access only. This gives full access to the whole -DRAM to the EL3 payload. - -The system is left in the same state as when entering BL31 in the default boot -flow. In particular: - -- Running in EL3; -- Current state is AArch64; -- Little-endian data access; -- All exceptions disabled; -- MMU disabled; -- Caches disabled. - -Booting an EL3 payload -~~~~~~~~~~~~~~~~~~~~~~ - -The EL3 payload image is a standalone image and is not part of the FIP. It is -not loaded by TF-A. Therefore, there are 2 possible scenarios: - -- The EL3 payload may reside in non-volatile memory (NVM) and execute in - place. In this case, booting it is just a matter of specifying the right - address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A. - -- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at - run-time. - -To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be -used. The infinite loop that it introduces in BL1 stops execution at the right -moment for a debugger to take control of the target and load the payload (for -example, over JTAG). - -It is expected that this loading method will work in most cases, as a debugger -connection is usually available in a pre-production system. The user is free to -use any other platform-specific mechanism to load the EL3 payload, though. - -Booting an EL3 payload on FVP -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for -the secondary CPUs holding pen to work properly. Unfortunately, its reset value -is undefined on the FVP platform and the FVP platform code doesn't clear it. -Therefore, one must modify the way the model is normally invoked in order to -clear the mailbox at start-up. - -One way to do that is to create an 8-byte file containing all zero bytes using -the following command: - -.. code:: shell - - dd if=/dev/zero of=mailbox.dat bs=1 count=8 - -and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) -using the following model parameters: - -:: - - --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] - --data=mailbox.dat@0x04000000 [Foundation FVP] - -To provide the model with the EL3 payload image, the following methods may be -used: - -#. If the EL3 payload is able to execute in place, it may be programmed into - flash memory. On Base Cortex and AEM FVPs, the following model parameter - loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already - used for the FIP): - - :: - - -C bp.flashloader1.fname="/" - - On Foundation FVP, there is no flash loader component and the EL3 payload - may be programmed anywhere in flash using method 3 below. - -#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 - command may be used to load the EL3 payload ELF image over JTAG: - - :: - - load /el3-payload.elf - -#. The EL3 payload may be pre-loaded in volatile memory using the following - model parameters: - - :: - - --data cluster0.cpu0="/el3-payload>"@address [Base FVPs] - --data="/"@address [Foundation FVP] - - The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address - used when building TF-A. - -Booting an EL3 payload on Juno -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -If the EL3 payload is able to execute in place, it may be programmed in flash -memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file -on the Juno SD card (where ``x`` depends on the revision of the Juno board). -Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory -programming" for more information. - -Alternatively, the same DS-5 command mentioned in the FVP section above can -be used to load the EL3 payload's ELF file over JTAG on Juno. - -Preloaded BL33 alternative boot flow ------------------------------------- - -Some platforms have the ability to preload BL33 into memory instead of relying -on TF-A to load it. This may simplify packaging of the normal world code and -improve performance in a development environment. When secure world cold boot -is complete, TF-A simply jumps to a BL33 base address provided at build time. - -For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be -used when compiling TF-A. For example, the following command will create a FIP -without a BL33 and prepare to jump to a BL33 image loaded at address -0x80000000: - -.. code:: shell - - make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip - -Boot of a preloaded kernel image on Base FVP -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The following example uses a simplified boot flow by directly jumping from the -TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be -useful if both the kernel and the device tree blob (DTB) are already present in -memory (like in FVP). - -For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at -address ``0x82000000``, the firmware can be built like this: - -.. code:: shell - - CROSS_COMPILE=aarch64-linux-gnu- \ - make PLAT=fvp DEBUG=1 \ - RESET_TO_BL31=1 \ - ARM_LINUX_KERNEL_AS_BL33=1 \ - PRELOADED_BL33_BASE=0x80080000 \ - ARM_PRELOADED_DTB_BASE=0x82000000 \ - all fip - -Now, it is needed to modify the DTB so that the kernel knows the address of the -ramdisk. The following script generates a patched DTB from the provided one, -assuming that the ramdisk is loaded at address ``0x84000000``. Note that this -script assumes that the user is using a ramdisk image prepared for U-Boot, like -the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` -offset in ``INITRD_START`` has to be removed. - -.. code:: bash - - #!/bin/bash - - # Path to the input DTB - KERNEL_DTB=/ - # Path to the output DTB - PATCHED_KERNEL_DTB=/ - # Base address of the ramdisk - INITRD_BASE=0x84000000 - # Path to the ramdisk - INITRD=/ - - # Skip uboot header (64 bytes) - INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) - INITRD_SIZE=$(stat -Lc %s ${INITRD}) - INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) - - CHOSEN_NODE=$(echo \ - "/ { \ - chosen { \ - linux,initrd-start = <${INITRD_START}>; \ - linux,initrd-end = <${INITRD_END}>; \ - }; \ - };") - - echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ - dtc -O dtb -o ${PATCHED_KERNEL_DTB} - - -And the FVP binary can be run with the following command: - -.. code:: shell - - /FVP_Base_AEMv8A-AEMv8A \ - -C pctl.startup=0.0.0.0 \ - -C bp.secure_memory=1 \ - -C cluster0.NUM_CORES=4 \ - -C cluster1.NUM_CORES=4 \ - -C cache_state_modelled=1 \ - -C cluster0.cpu0.RVBAR=0x04020000 \ - -C cluster0.cpu1.RVBAR=0x04020000 \ - -C cluster0.cpu2.RVBAR=0x04020000 \ - -C cluster0.cpu3.RVBAR=0x04020000 \ - -C cluster1.cpu0.RVBAR=0x04020000 \ - -C cluster1.cpu1.RVBAR=0x04020000 \ - -C cluster1.cpu2.RVBAR=0x04020000 \ - -C cluster1.cpu3.RVBAR=0x04020000 \ - --data cluster0.cpu0="/bl31.bin"@0x04020000 \ - --data cluster0.cpu0="/"@0x82000000 \ - --data cluster0.cpu0="/"@0x80080000 \ - --data cluster0.cpu0="/"@0x84000000 - -Boot of a preloaded kernel image on Juno -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The Trusted Firmware must be compiled in a similar way as for FVP explained -above. The process to load binaries to memory is the one explained in -`Booting an EL3 payload on Juno`_. - -.. _user_guide_run_fvp: - -Running the software on FVP ---------------------------- - -The latest version of the AArch64 build of TF-A has been tested on the following -Arm FVPs without shifted affinities, and that do not support threaded CPU cores -(64-bit host machine only). - -.. note:: - The FVP models used are Version 11.6 Build 45, unless otherwise stated. - -- ``FVP_Base_AEMv8A-AEMv8A`` -- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` -- ``FVP_Base_RevC-2xAEMv8A`` -- ``FVP_Base_Cortex-A32x4`` -- ``FVP_Base_Cortex-A35x4`` -- ``FVP_Base_Cortex-A53x4`` -- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` -- ``FVP_Base_Cortex-A55x4`` -- ``FVP_Base_Cortex-A57x1-A53x1`` -- ``FVP_Base_Cortex-A57x2-A53x4`` -- ``FVP_Base_Cortex-A57x4-A53x4`` -- ``FVP_Base_Cortex-A57x4`` -- ``FVP_Base_Cortex-A72x4-A53x4`` -- ``FVP_Base_Cortex-A72x4`` -- ``FVP_Base_Cortex-A73x4-A53x4`` -- ``FVP_Base_Cortex-A73x4`` -- ``FVP_Base_Cortex-A75x4`` -- ``FVP_Base_Cortex-A76x4`` -- ``FVP_Base_Cortex-A76AEx4`` -- ``FVP_Base_Cortex-A76AEx8`` -- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) -- ``FVP_Base_Neoverse-N1x4`` -- ``FVP_Base_Zeusx4`` -- ``FVP_CSS_SGI-575`` (Version 11.3 build 42) -- ``FVP_CSS_SGM-775`` (Version 11.3 build 42) -- ``FVP_RD_E1Edge`` (Version 11.3 build 42) -- ``FVP_RD_N1Edge`` -- ``Foundation_Platform`` - -The latest version of the AArch32 build of TF-A has been tested on the following -Arm FVPs without shifted affinities, and that do not support threaded CPU cores -(64-bit host machine only). - -- ``FVP_Base_AEMv8A-AEMv8A`` -- ``FVP_Base_Cortex-A32x4`` - -.. note:: - The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which - is not compatible with legacy GIC configurations. Therefore this FVP does not - support these legacy GIC configurations. - -.. note:: - The build numbers quoted above are those reported by launching the FVP - with the ``--version`` parameter. - -.. note:: - Linaro provides a ramdisk image in prebuilt FVP configurations and full - file systems that can be downloaded separately. To run an FVP with a virtio - file system image an additional FVP configuration option - ``-C bp.virtioblockdevice.image_path="/`` can be - used. - -.. note:: - The software will not work on Version 1.0 of the Foundation FVP. - The commands below would report an ``unhandled argument`` error in this case. - -.. note:: - FVPs can be launched with ``--cadi-server`` option such that a - CADI-compliant debugger (for example, Arm DS-5) can connect to and control - its execution. - -.. warning:: - Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 - the internal synchronisation timings changed compared to older versions of - the models. The models can be launched with ``-Q 100`` option if they are - required to match the run time characteristics of the older versions. - -The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be -downloaded for free from `Arm's website`_. - -The Cortex-A models listed above are also available to download from -`Arm's website`_. - -Please refer to the FVP documentation for a detailed description of the model -parameter options. A brief description of the important ones that affect TF-A -and normal world software behavior is provided below. - -Obtaining the Flattened Device Trees -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Depending on the FVP configuration and Linux configuration used, different -FDT files are required. FDT source files for the Foundation and Base FVPs can -be found in the TF-A source directory under ``fdts/``. The Foundation FVP has -a subset of the Base FVP components. For example, the Foundation FVP lacks -CLCD and MMC support, and has only one CPU cluster. - -.. note:: - It is not recommended to use the FDTs built along the kernel because not - all FDTs are available from there. - -The dynamic configuration capability is enabled in the firmware for FVPs. -This means that the firmware can authenticate and load the FDT if present in -FIP. A default FDT is packaged into FIP during the build based on -the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` -or ``FVP_HW_CONFIG_DTS`` build options (refer to the -`Arm FVP platform specific build options`_ section for detail on the options). - -- ``fvp-base-gicv2-psci.dts`` - - For use with models such as the Cortex-A57-A53 Base FVPs without shifted - affinities and with Base memory map configuration. - -- ``fvp-base-gicv2-psci-aarch32.dts`` - - For use with models such as the Cortex-A32 Base FVPs without shifted - affinities and running Linux in AArch32 state with Base memory map - configuration. - -- ``fvp-base-gicv3-psci.dts`` - - For use with models such as the Cortex-A57-A53 Base FVPs without shifted - affinities and with Base memory map configuration and Linux GICv3 support. - -- ``fvp-base-gicv3-psci-1t.dts`` - - For use with models such as the AEMv8-RevC Base FVP with shifted affinities, - single threaded CPUs, Base memory map configuration and Linux GICv3 support. - -- ``fvp-base-gicv3-psci-dynamiq.dts`` - - For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, - single cluster, single threaded CPUs, Base memory map configuration and Linux - GICv3 support. - -- ``fvp-base-gicv3-psci-aarch32.dts`` - - For use with models such as the Cortex-A32 Base FVPs without shifted - affinities and running Linux in AArch32 state with Base memory map - configuration and Linux GICv3 support. - -- ``fvp-foundation-gicv2-psci.dts`` - - For use with Foundation FVP with Base memory map configuration. - -- ``fvp-foundation-gicv3-psci.dts`` - - (Default) For use with Foundation FVP with Base memory map configuration - and Linux GICv3 support. - -Running on the Foundation FVP with reset to BL1 entrypoint -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The following ``Foundation_Platform`` parameters should be used to boot Linux with -4 CPUs using the AArch64 build of TF-A. - -.. code:: shell - - /Foundation_Platform \ - --cores=4 \ - --arm-v8.0 \ - --secure-memory \ - --visualization \ - --gicv3 \ - --data="/"@0x0 \ - --data="/"@0x08000000 \ - --data="/"@0x80080000 \ - --data="/"@0x84000000 - -Notes: - -- BL1 is loaded at the start of the Trusted ROM. -- The Firmware Image Package is loaded at the start of NOR FLASH0. -- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address - is specified via the ``hw_config_addr`` property in ``TB_FW_CONFIG`` for FVP. -- The default use-case for the Foundation FVP is to use the ``--gicv3`` option - and enable the GICv3 device in the model. Note that without this option, - the Foundation FVP defaults to legacy (Versatile Express) memory map which - is not supported by TF-A. -- In order for TF-A to run correctly on the Foundation FVP, the architecture - versions must match. The Foundation FVP defaults to the highest v8.x - version it supports but the default build for TF-A is for v8.0. To avoid - issues either start the Foundation FVP to use v8.0 architecture using the - ``--arm-v8.0`` option, or build TF-A with an appropriate value for - ``ARM_ARCH_MINOR``. - -Running on the AEMv8 Base FVP with reset to BL1 entrypoint -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux -with 8 CPUs using the AArch64 build of TF-A. - -.. code:: shell - - /FVP_Base_RevC-2xAEMv8A \ - -C pctl.startup=0.0.0.0 \ - -C bp.secure_memory=1 \ - -C bp.tzc_400.diagnostics=1 \ - -C cluster0.NUM_CORES=4 \ - -C cluster1.NUM_CORES=4 \ - -C cache_state_modelled=1 \ - -C bp.secureflashloader.fname="/" \ - -C bp.flashloader0.fname="/" \ - --data cluster0.cpu0="/"@0x80080000 \ - --data cluster0.cpu0="/"@0x84000000 - -.. note:: - The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires - a specific DTS for all the CPUs to be loaded. - -Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux -with 8 CPUs using the AArch32 build of TF-A. - -.. code:: shell - - /FVP_Base_AEMv8A-AEMv8A \ - -C pctl.startup=0.0.0.0 \ - -C bp.secure_memory=1 \ - -C bp.tzc_400.diagnostics=1 \ - -C cluster0.NUM_CORES=4 \ - -C cluster1.NUM_CORES=4 \ - -C cache_state_modelled=1 \ - -C cluster0.cpu0.CONFIG64=0 \ - -C cluster0.cpu1.CONFIG64=0 \ - -C cluster0.cpu2.CONFIG64=0 \ - -C cluster0.cpu3.CONFIG64=0 \ - -C cluster1.cpu0.CONFIG64=0 \ - -C cluster1.cpu1.CONFIG64=0 \ - -C cluster1.cpu2.CONFIG64=0 \ - -C cluster1.cpu3.CONFIG64=0 \ - -C bp.secureflashloader.fname="/" \ - -C bp.flashloader0.fname="/" \ - --data cluster0.cpu0="/"@0x80080000 \ - --data cluster0.cpu0="/"@0x84000000 - -Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to -boot Linux with 8 CPUs using the AArch64 build of TF-A. - -.. code:: shell - - /FVP_Base_Cortex-A57x4-A53x4 \ - -C pctl.startup=0.0.0.0 \ - -C bp.secure_memory=1 \ - -C bp.tzc_400.diagnostics=1 \ - -C cache_state_modelled=1 \ - -C bp.secureflashloader.fname="/" \ - -C bp.flashloader0.fname="/" \ - --data cluster0.cpu0="/"@0x80080000 \ - --data cluster0.cpu0="/"@0x84000000 - -Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to -boot Linux with 4 CPUs using the AArch32 build of TF-A. - -.. code:: shell - - /FVP_Base_Cortex-A32x4 \ - -C pctl.startup=0.0.0.0 \ - -C bp.secure_memory=1 \ - -C bp.tzc_400.diagnostics=1 \ - -C cache_state_modelled=1 \ - -C bp.secureflashloader.fname="/" \ - -C bp.flashloader0.fname="/" \ - --data cluster0.cpu0="/"@0x80080000 \ - --data cluster0.cpu0="/"@0x84000000 - -Running on the AEMv8 Base FVP with reset to BL31 entrypoint -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux -with 8 CPUs using the AArch64 build of TF-A. - -.. code:: shell - - /FVP_Base_RevC-2xAEMv8A \ - -C pctl.startup=0.0.0.0 \ - -C bp.secure_memory=1 \ - -C bp.tzc_400.diagnostics=1 \ - -C cluster0.NUM_CORES=4 \ - -C cluster1.NUM_CORES=4 \ - -C cache_state_modelled=1 \ - -C cluster0.cpu0.RVBAR=0x04010000 \ - -C cluster0.cpu1.RVBAR=0x04010000 \ - -C cluster0.cpu2.RVBAR=0x04010000 \ - -C cluster0.cpu3.RVBAR=0x04010000 \ - -C cluster1.cpu0.RVBAR=0x04010000 \ - -C cluster1.cpu1.RVBAR=0x04010000 \ - -C cluster1.cpu2.RVBAR=0x04010000 \ - -C cluster1.cpu3.RVBAR=0x04010000 \ - --data cluster0.cpu0="/"@0x04010000 \ - --data cluster0.cpu0="/"@0xff000000 \ - --data cluster0.cpu0="/"@0x88000000 \ - --data cluster0.cpu0="/"@0x82000000 \ - --data cluster0.cpu0="/"@0x80080000 \ - --data cluster0.cpu0="/"@0x84000000 - -Notes: - -- If Position Independent Executable (PIE) support is enabled for BL31 - in this config, it can be loaded at any valid address for execution. - -- Since a FIP is not loaded when using BL31 as reset entrypoint, the - ``--data=""@`` - parameter is needed to load the individual bootloader images in memory. - BL32 image is only needed if BL31 has been built to expect a Secure-EL1 - Payload. For the same reason, the FDT needs to be compiled from the DT source - and loaded via the ``--data cluster0.cpu0="/"@0x82000000`` - parameter. - -- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a - specific DTS for all the CPUs to be loaded. - -- The ``-C cluster.cpu.RVBAR=@`` parameter, where - X and Y are the cluster and CPU numbers respectively, is used to set the - reset vector for each core. - -- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require - changing the value of - ``--data=""@`` to the new value of - ``BL32_BASE``. - -Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux -with 8 CPUs using the AArch32 build of TF-A. - -.. code:: shell - - /FVP_Base_AEMv8A-AEMv8A \ - -C pctl.startup=0.0.0.0 \ - -C bp.secure_memory=1 \ - -C bp.tzc_400.diagnostics=1 \ - -C cluster0.NUM_CORES=4 \ - -C cluster1.NUM_CORES=4 \ - -C cache_state_modelled=1 \ - -C cluster0.cpu0.CONFIG64=0 \ - -C cluster0.cpu1.CONFIG64=0 \ - -C cluster0.cpu2.CONFIG64=0 \ - -C cluster0.cpu3.CONFIG64=0 \ - -C cluster1.cpu0.CONFIG64=0 \ - -C cluster1.cpu1.CONFIG64=0 \ - -C cluster1.cpu2.CONFIG64=0 \ - -C cluster1.cpu3.CONFIG64=0 \ - -C cluster0.cpu0.RVBAR=0x04002000 \ - -C cluster0.cpu1.RVBAR=0x04002000 \ - -C cluster0.cpu2.RVBAR=0x04002000 \ - -C cluster0.cpu3.RVBAR=0x04002000 \ - -C cluster1.cpu0.RVBAR=0x04002000 \ - -C cluster1.cpu1.RVBAR=0x04002000 \ - -C cluster1.cpu2.RVBAR=0x04002000 \ - -C cluster1.cpu3.RVBAR=0x04002000 \ - --data cluster0.cpu0="/"@0x04002000 \ - --data cluster0.cpu0="/"@0x88000000 \ - --data cluster0.cpu0="/"@0x82000000 \ - --data cluster0.cpu0="/"@0x80080000 \ - --data cluster0.cpu0="/"@0x84000000 - -.. note:: - The load address of ```` depends on the value ``BL32_BASE``. - It should match the address programmed into the RVBAR register as well. - -Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to -boot Linux with 8 CPUs using the AArch64 build of TF-A. - -.. code:: shell - - /FVP_Base_Cortex-A57x4-A53x4 \ - -C pctl.startup=0.0.0.0 \ - -C bp.secure_memory=1 \ - -C bp.tzc_400.diagnostics=1 \ - -C cache_state_modelled=1 \ - -C cluster0.cpu0.RVBARADDR=0x04010000 \ - -C cluster0.cpu1.RVBARADDR=0x04010000 \ - -C cluster0.cpu2.RVBARADDR=0x04010000 \ - -C cluster0.cpu3.RVBARADDR=0x04010000 \ - -C cluster1.cpu0.RVBARADDR=0x04010000 \ - -C cluster1.cpu1.RVBARADDR=0x04010000 \ - -C cluster1.cpu2.RVBARADDR=0x04010000 \ - -C cluster1.cpu3.RVBARADDR=0x04010000 \ - --data cluster0.cpu0="/"@0x04010000 \ - --data cluster0.cpu0="/"@0xff000000 \ - --data cluster0.cpu0="/"@0x88000000 \ - --data cluster0.cpu0="/"@0x82000000 \ - --data cluster0.cpu0="/"@0x80080000 \ - --data cluster0.cpu0="/"@0x84000000 - -Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to -boot Linux with 4 CPUs using the AArch32 build of TF-A. - -.. code:: shell - - /FVP_Base_Cortex-A32x4 \ - -C pctl.startup=0.0.0.0 \ - -C bp.secure_memory=1 \ - -C bp.tzc_400.diagnostics=1 \ - -C cache_state_modelled=1 \ - -C cluster0.cpu0.RVBARADDR=0x04002000 \ - -C cluster0.cpu1.RVBARADDR=0x04002000 \ - -C cluster0.cpu2.RVBARADDR=0x04002000 \ - -C cluster0.cpu3.RVBARADDR=0x04002000 \ - --data cluster0.cpu0="/"@0x04002000 \ - --data cluster0.cpu0="/"@0x88000000 \ - --data cluster0.cpu0="/"@0x82000000 \ - --data cluster0.cpu0="/"@0x80080000 \ - --data cluster0.cpu0="/"@0x84000000 - -Running the software on Juno ----------------------------- - -This version of TF-A has been tested on variants r0, r1 and r2 of Juno. - -To execute the software stack on Juno, installing the latest Arm Platforms -software deliverables is recommended. Please install the deliverables by -following the `Instructions for using Linaro's deliverables on Juno`_. - -Preparing TF-A images -~~~~~~~~~~~~~~~~~~~~~ - -After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the -``SOFTWARE/`` directory of the Juno SD card. - -Other Juno software information -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno -software information. Please also refer to the `Juno Getting Started Guide`_ to -get more detailed information about the Juno Arm development platform and how to -configure it. - -Testing SYSTEM SUSPEND on Juno -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend -to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend -on Juno, at the linux shell prompt, issue the following command: - -.. code:: shell - - echo +10 > /sys/class/rtc/rtc0/wakealarm - echo -n mem > /sys/power/state - -The Juno board should suspend to RAM and then wakeup after 10 seconds due to -wakeup interrupt from RTC. - --------------- - -*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* - -.. _Arm Developer page: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads -.. _Linaro Release: http://releases.linaro.org/members/arm/platforms -.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 -.. _Linaro instructions: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about -.. _Arm Platforms User guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/user-guide.rst -.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno -.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/ -.. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio -.. _arm-trusted-firmware-a project page: https://review.trustedfirmware.org/admin/projects/TF-A/trusted-firmware-a -.. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html -.. _Linux master tree: https://github.com/torvalds/linux/tree/master/ -.. _Dia: https://wiki.gnome.org/Apps/Dia/Download -.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git -.. _mbed TLS Security Center: https://tls.mbed.org/security -.. _Arm's website: `FVP models`_ -.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms -.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf -.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf diff --git a/docs/perf/index.rst b/docs/perf/index.rst index 50833b8c8..0f49b4810 100644 --- a/docs/perf/index.rst +++ b/docs/perf/index.rst @@ -7,3 +7,8 @@ Performance & Testing :numbered: psci-performance-juno + tsp + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/perf/tsp.rst b/docs/perf/tsp.rst new file mode 100644 index 000000000..f8b0048bf --- /dev/null +++ b/docs/perf/tsp.rst @@ -0,0 +1,27 @@ +Test Secure Payload (TSP) and Dispatcher (TSPD) +=============================================== + +Building the Test Secure Payload +-------------------------------- + +The TSP is coupled with a companion runtime service in the BL31 firmware, +called the TSPD. Therefore, if you intend to use the TSP, the BL31 image +must be recompiled as well. For more information on SPs and SPDs, see the +:ref:`firmware_design_sel1_spd` section in the :ref:`Firmware Design`. + +First clean the TF-A build directory to get rid of any previous BL31 binary. +Then to build the TSP image use: + +.. code:: shell + + make PLAT= SPD=tspd all + +An additional boot loader binary file is created in the ``build`` directory: + +:: + + build///bl32.bin + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst new file mode 100644 index 000000000..d24ad231d --- /dev/null +++ b/docs/plat/arm/arm-build-options.rst @@ -0,0 +1,114 @@ +Arm Development Platform Build Options +====================================== + +Arm Platform Build Options +-------------------------- + +- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured + DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load + BL31 in TZC secured DRAM. If TSP is present, then setting this option also + sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build + flag. + +- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase`` + frame registers by setting the ``CNTCTLBase.CNTACR`` register bits. The + frame number ```` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which + should match the frame used by the Non-Secure image (normally the Linux + kernel). Default is true (access to the frame is allowed). + +- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog. + By default, Arm platforms use a watchdog to trigger a system reset in case + an error is encountered during the boot process (for example, when an image + could not be loaded or authenticated). The watchdog is enabled in the early + platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The + Trusted Watchdog may be disabled at build time for testing or development + purposes. + +- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to + have specific values at boot. This boolean option allows the Trusted Firmware + to have a Linux kernel image as BL33 by preparing the registers to these + values before jumping to BL33. This option defaults to 0 (disabled). For + AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when + using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set + to the location of a device tree blob (DTB) already loaded in memory. The + Linux Image address must be specified using the ``PRELOADED_BL33_BASE`` + option. + +- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to + cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag + is set, the functions which deal with MPIDR assume that the ``MT`` bit in + MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of + this flag is 0. Note that this option is not used on FVP platforms. + +- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding + for the construction of composite state-ID in the power-state parameter. + The existing PSCI clients currently do not support this encoding of + State-ID yet. Hence this flag is used to configure whether to use the + recommended State-ID encoding or not. The default value of this flag is 0, + in which case the platform is configured to expect NULL in the State-ID + field of power-state parameter. + +- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the + location of the ROTPK hash returned by the function ``plat_get_rotpk_info()`` + for Arm platforms. Depending on the selected option, the proper private key + must be specified using the ``ROT_KEY`` option when building the Trusted + Firmware. This private key will be used by the certificate generation tool + to sign the BL2 and Trusted Key certificates. Available options for + ``ARM_ROTPK_LOCATION`` are: + + - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage + registers. The private key corresponding to this ROTPK hash is not + currently available. + - ``devel_rsa`` : return a development public key hash embedded in the BL1 + and BL2 binaries. This hash has been obtained from the RSA public key + ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use + this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` + when creating the certificates. + - ``devel_ecdsa`` : return a development public key hash embedded in the BL1 + and BL2 binaries. This hash has been obtained from the ECDSA public key + ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To + use this option, ``arm_rotprivk_ecdsa.pem`` must be specified as + ``ROT_KEY`` when creating the certificates. + +- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options: + + - ``tsram`` : Trusted SRAM (default option when TBB is not enabled) + - ``tdram`` : Trusted DRAM (if available) + - ``dram`` : Secure region in DRAM (default option when TBB is enabled, + configured by the TrustZone controller) + +- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1 + of the translation tables library instead of version 2. It is set to 0 by + default, which selects version 2. + +- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm® + TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm + platforms. If this option is specified, then the path to the CryptoCell + SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag. + +For a better understanding of these options, the Arm development platform memory +map is explained in the :ref:`Firmware Design`. + +.. _build_options_arm_css_platform: + +Arm CSS Platform-Specific Build Options +--------------------------------------- + +- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version + incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards + compatible change to the MTL protocol, used for AP/SCP communication. + TF-A no longer supports earlier SCP versions. If this option is set to 1 + then TF-A will detect if an earlier version is in use. Default is 1. + +- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and + SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded + during boot. Default is 1. + +- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers + instead of SCPI/BOM driver for communicating with the SCP during power + management operations and for SCP RAM Firmware transfer. If this option + is set to 1, then SCMI/SDS drivers will be used. Default is 0. + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/plat/arm/fvp-ve/index.rst b/docs/plat/arm/fvp-ve/index.rst new file mode 100644 index 000000000..8ac07418a --- /dev/null +++ b/docs/plat/arm/fvp-ve/index.rst @@ -0,0 +1,84 @@ +Arm Versatile Express +===================== + +Versatile Express (VE) family development platform provides an ultra fast +environment for prototyping Armv7 System-on-Chip designs. VE Fixed Virtual +Platforms (FVP) are simulations of Versatile Express boards. The platform in +Trusted Firmware-A has been verified with Arm Cortex-A5 and Cortex-A7 VE FVP's. +This platform is tested on and only expected to work with single core models. + +Boot Sequence +------------- + +BL1 --> BL2 --> BL32(sp_min) --> BL33(u-boot) --> Linux kernel + +How to build +------------ + +Code Locations +~~~~~~~~~~~~~~ +- `U-boot `__ + +- `Trusted Firmware-A `__ + +Build Procedure +~~~~~~~~~~~~~~~ + +- Obtain arm toolchain. The software stack has been verified with linaro 6.2 + `arm-linux-gnueabihf `__. + Set the CROSS_COMPILE environment variable to point to the toolchain folder. + +- Fetch and build u-boot. + Make the .config file using the command: + + .. code:: shell + + make ARCH=arm vexpress_aemv8a_aarch32_config + + Make the u-boot binary for Cortex-A5 using the command: + + .. code:: shell + + make ARCH=arm SUPPORT_ARCH_TIMER=no + + Make the u-boot binary for Cortex-A7 using the command: + + .. code:: shell + + make ARCH=arm + + +- Build TF-A: + + The make command for Cortex-A5 is: + + .. code:: shell + + make PLAT=fvp_ve ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes \ + AARCH32_SP=sp_min FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts \ + ARM_XLAT_TABLES_LIB_V1=1 BL33= all fip + + The make command for Cortex-A7 is: + + .. code:: shell + + make PLAT=fvp_ve ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \ + AARCH32_SP=sp_min FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A7x1.dts \ + BL33= all fip + +Run Procedure +~~~~~~~~~~~~~ + +The following model parameters should be used to boot Linux using the build of +Trusted Firmware-A made using the above make commands: + + .. code:: shell + + ./ \ + -C motherboard.flashloader1.fname= \ + --data cluster.cpu0=@0x80080000 \ + --data cluster.cpu0=@0x84000000 + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst new file mode 100644 index 000000000..b6396b97c --- /dev/null +++ b/docs/plat/arm/fvp/index.rst @@ -0,0 +1,637 @@ +Arm Fixed Virtual Platforms (FVP) +================================= + +Fixed Virtual Platform (FVP) Support +------------------------------------ + +This section lists the supported Arm |FVP| platforms. Please refer to the FVP +documentation for a detailed description of the model parameter options. + +The latest version of the AArch64 build of TF-A has been tested on the following +Arm FVPs without shifted affinities, and that do not support threaded CPU cores +(64-bit host machine only). + +.. note:: + The FVP models used are Version 11.6 Build 45, unless otherwise stated. + +- ``FVP_Base_AEMv8A-AEMv8A`` +- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` +- ``FVP_Base_RevC-2xAEMv8A`` +- ``FVP_Base_Cortex-A32x4`` +- ``FVP_Base_Cortex-A35x4`` +- ``FVP_Base_Cortex-A53x4`` +- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` +- ``FVP_Base_Cortex-A55x4`` +- ``FVP_Base_Cortex-A57x1-A53x1`` +- ``FVP_Base_Cortex-A57x2-A53x4`` +- ``FVP_Base_Cortex-A57x4-A53x4`` +- ``FVP_Base_Cortex-A57x4`` +- ``FVP_Base_Cortex-A72x4-A53x4`` +- ``FVP_Base_Cortex-A72x4`` +- ``FVP_Base_Cortex-A73x4-A53x4`` +- ``FVP_Base_Cortex-A73x4`` +- ``FVP_Base_Cortex-A75x4`` +- ``FVP_Base_Cortex-A76x4`` +- ``FVP_Base_Cortex-A76AEx4`` +- ``FVP_Base_Cortex-A76AEx8`` +- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) +- ``FVP_Base_Neoverse-N1x4`` +- ``FVP_Base_Zeusx4`` +- ``FVP_CSS_SGI-575`` (Version 11.3 build 42) +- ``FVP_CSS_SGM-775`` (Version 11.3 build 42) +- ``FVP_RD_E1Edge`` (Version 11.3 build 42) +- ``FVP_RD_N1Edge`` +- ``Foundation_Platform`` + +The latest version of the AArch32 build of TF-A has been tested on the +following Arm FVPs without shifted affinities, and that do not support threaded +CPU cores (64-bit host machine only). + +- ``FVP_Base_AEMv8A-AEMv8A`` +- ``FVP_Base_Cortex-A32x4`` + +.. note:: + The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which + is not compatible with legacy GIC configurations. Therefore this FVP does not + support these legacy GIC configurations. + +The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm +FVP website`_. The Cortex-A models listed above are also available to download +from `Arm's website`_. + +.. note:: + The build numbers quoted above are those reported by launching the FVP + with the ``--version`` parameter. + +.. note:: + Linaro provides a ramdisk image in prebuilt FVP configurations and full + file systems that can be downloaded separately. To run an FVP with a virtio + file system image an additional FVP configuration option + ``-C bp.virtioblockdevice.image_path="/`` can be + used. + +.. note:: + The software will not work on Version 1.0 of the Foundation FVP. + The commands below would report an ``unhandled argument`` error in this case. + +.. note:: + FVPs can be launched with ``--cadi-server`` option such that a + CADI-compliant debugger (for example, Arm DS-5) can connect to and control + its execution. + +.. warning:: + Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 + the internal synchronisation timings changed compared to older versions of + the models. The models can be launched with ``-Q 100`` option if they are + required to match the run time characteristics of the older versions. + +All the above platforms have been tested with `Linaro Release 19.06`_. + +.. _build_options_arm_fvp_platform: + +Arm FVP Platform Specific Build Options +--------------------------------------- + +- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to + build the topology tree within TF-A. By default TF-A is configured for dual + cluster topology and this option can be used to override the default value. + +- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The + default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as + explained in the options below: + + - ``FVP_CCI`` : The CCI driver is selected. This is the default + if 0 < ``FVP_CLUSTER_COUNT`` <= 2. + - ``FVP_CCN`` : The CCN driver is selected. This is the default + if ``FVP_CLUSTER_COUNT`` > 2. + +- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in + a single cluster. This option defaults to 4. + +- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU + in the system. This option defaults to 1. Note that the build option + ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. + +- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: + + - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected + - ``FVP_GICV2`` : The GICv2 only driver is selected + - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) + +- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer + for functions that wait for an arbitrary time length (udelay and mdelay). + The default value is 0. + +- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled + to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for + details on HW_CONFIG. By default, this is initialized to a sensible DTS + file in ``fdts/`` folder depending on other build options. But some cases, + like shifted affinity format for MPIDR, cannot be detected at build time + and this option is needed to specify the appropriate DTS file. + +- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in + FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is + similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the + HW_CONFIG blob instead of the DTS file. This option is useful to override + the default HW_CONFIG selected by the build system. + +Booting Firmware Update images +------------------------------ + +When Firmware Update (FWU) is enabled there are at least 2 new images +that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the +FWU FIP. + +The additional fip images must be loaded with: + +:: + + --data cluster0.cpu0="/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] + --data cluster0.cpu0="/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] + +The address ns_bl1u_base_address is the value of NS_BL1U_BASE. +In the same way, the address ns_bl2u_base_address is the value of +NS_BL2U_BASE. + +Booting an EL3 payload +---------------------- + +The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for +the secondary CPUs holding pen to work properly. Unfortunately, its reset value +is undefined on the FVP platform and the FVP platform code doesn't clear it. +Therefore, one must modify the way the model is normally invoked in order to +clear the mailbox at start-up. + +One way to do that is to create an 8-byte file containing all zero bytes using +the following command: + +.. code:: shell + + dd if=/dev/zero of=mailbox.dat bs=1 count=8 + +and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) +using the following model parameters: + +:: + + --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] + --data=mailbox.dat@0x04000000 [Foundation FVP] + +To provide the model with the EL3 payload image, the following methods may be +used: + +#. If the EL3 payload is able to execute in place, it may be programmed into + flash memory. On Base Cortex and AEM FVPs, the following model parameter + loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already + used for the FIP): + + :: + + -C bp.flashloader1.fname="/" + + On Foundation FVP, there is no flash loader component and the EL3 payload + may be programmed anywhere in flash using method 3 below. + +#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 + command may be used to load the EL3 payload ELF image over JTAG: + + :: + + load /el3-payload.elf + +#. The EL3 payload may be pre-loaded in volatile memory using the following + model parameters: + + :: + + --data cluster0.cpu0="/el3-payload>"@address [Base FVPs] + --data="/"@address [Foundation FVP] + + The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address + used when building TF-A. + +Booting a preloaded kernel image (Base FVP) +------------------------------------------- + +The following example uses a simplified boot flow by directly jumping from the +TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be +useful if both the kernel and the device tree blob (DTB) are already present in +memory (like in FVP). + +For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at +address ``0x82000000``, the firmware can be built like this: + +.. code:: shell + + CROSS_COMPILE=aarch64-linux-gnu- \ + make PLAT=fvp DEBUG=1 \ + RESET_TO_BL31=1 \ + ARM_LINUX_KERNEL_AS_BL33=1 \ + PRELOADED_BL33_BASE=0x80080000 \ + ARM_PRELOADED_DTB_BASE=0x82000000 \ + all fip + +Now, it is needed to modify the DTB so that the kernel knows the address of the +ramdisk. The following script generates a patched DTB from the provided one, +assuming that the ramdisk is loaded at address ``0x84000000``. Note that this +script assumes that the user is using a ramdisk image prepared for U-Boot, like +the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` +offset in ``INITRD_START`` has to be removed. + +.. code:: bash + + #!/bin/bash + + # Path to the input DTB + KERNEL_DTB=/ + # Path to the output DTB + PATCHED_KERNEL_DTB=/ + # Base address of the ramdisk + INITRD_BASE=0x84000000 + # Path to the ramdisk + INITRD=/ + + # Skip uboot header (64 bytes) + INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) + INITRD_SIZE=$(stat -Lc %s ${INITRD}) + INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) + + CHOSEN_NODE=$(echo \ + "/ { \ + chosen { \ + linux,initrd-start = <${INITRD_START}>; \ + linux,initrd-end = <${INITRD_END}>; \ + }; \ + };") + + echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ + dtc -O dtb -o ${PATCHED_KERNEL_DTB} - + +And the FVP binary can be run with the following command: + +.. code:: shell + + /FVP_Base_AEMv8A-AEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.RVBAR=0x04020000 \ + -C cluster0.cpu1.RVBAR=0x04020000 \ + -C cluster0.cpu2.RVBAR=0x04020000 \ + -C cluster0.cpu3.RVBAR=0x04020000 \ + -C cluster1.cpu0.RVBAR=0x04020000 \ + -C cluster1.cpu1.RVBAR=0x04020000 \ + -C cluster1.cpu2.RVBAR=0x04020000 \ + -C cluster1.cpu3.RVBAR=0x04020000 \ + --data cluster0.cpu0="/bl31.bin"@0x04020000 \ + --data cluster0.cpu0="/"@0x82000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + --data cluster0.cpu0="/"@0x84000000 + +Obtaining the Flattened Device Trees +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Depending on the FVP configuration and Linux configuration used, different +FDT files are required. FDT source files for the Foundation and Base FVPs can +be found in the TF-A source directory under ``fdts/``. The Foundation FVP has +a subset of the Base FVP components. For example, the Foundation FVP lacks +CLCD and MMC support, and has only one CPU cluster. + +.. note:: + It is not recommended to use the FDTs built along the kernel because not + all FDTs are available from there. + +The dynamic configuration capability is enabled in the firmware for FVPs. +This means that the firmware can authenticate and load the FDT if present in +FIP. A default FDT is packaged into FIP during the build based on +the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` +or ``FVP_HW_CONFIG_DTS`` build options (refer to +:ref:`build_options_arm_fvp_platform` for details on the options). + +- ``fvp-base-gicv2-psci.dts`` + + For use with models such as the Cortex-A57-A53 Base FVPs without shifted + affinities and with Base memory map configuration. + +- ``fvp-base-gicv2-psci-aarch32.dts`` + + For use with models such as the Cortex-A32 Base FVPs without shifted + affinities and running Linux in AArch32 state with Base memory map + configuration. + +- ``fvp-base-gicv3-psci.dts`` + + For use with models such as the Cortex-A57-A53 Base FVPs without shifted + affinities and with Base memory map configuration and Linux GICv3 support. + +- ``fvp-base-gicv3-psci-1t.dts`` + + For use with models such as the AEMv8-RevC Base FVP with shifted affinities, + single threaded CPUs, Base memory map configuration and Linux GICv3 support. + +- ``fvp-base-gicv3-psci-dynamiq.dts`` + + For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, + single cluster, single threaded CPUs, Base memory map configuration and Linux + GICv3 support. + +- ``fvp-base-gicv3-psci-aarch32.dts`` + + For use with models such as the Cortex-A32 Base FVPs without shifted + affinities and running Linux in AArch32 state with Base memory map + configuration and Linux GICv3 support. + +- ``fvp-foundation-gicv2-psci.dts`` + + For use with Foundation FVP with Base memory map configuration. + +- ``fvp-foundation-gicv3-psci.dts`` + + (Default) For use with Foundation FVP with Base memory map configuration + and Linux GICv3 support. + + +Running on the Foundation FVP with reset to BL1 entrypoint +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following ``Foundation_Platform`` parameters should be used to boot Linux with +4 CPUs using the AArch64 build of TF-A. + +.. code:: shell + + /Foundation_Platform \ + --cores=4 \ + --arm-v8.0 \ + --secure-memory \ + --visualization \ + --gicv3 \ + --data="/"@0x0 \ + --data="/"@0x08000000 \ + --data="/"@0x80080000 \ + --data="/"@0x84000000 + +Notes: + +- BL1 is loaded at the start of the Trusted ROM. +- The Firmware Image Package is loaded at the start of NOR FLASH0. +- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address + is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_. +- The default use-case for the Foundation FVP is to use the ``--gicv3`` option + and enable the GICv3 device in the model. Note that without this option, + the Foundation FVP defaults to legacy (Versatile Express) memory map which + is not supported by TF-A. +- In order for TF-A to run correctly on the Foundation FVP, the architecture + versions must match. The Foundation FVP defaults to the highest v8.x + version it supports but the default build for TF-A is for v8.0. To avoid + issues either start the Foundation FVP to use v8.0 architecture using the + ``--arm-v8.0`` option, or build TF-A with an appropriate value for + ``ARM_ARCH_MINOR``. + +Running on the AEMv8 Base FVP with reset to BL1 entrypoint +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux +with 8 CPUs using the AArch64 build of TF-A. + +.. code:: shell + + /FVP_Base_RevC-2xAEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x80080000 \ + --data cluster0.cpu0="/"@0x84000000 + +.. note:: + The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires + a specific DTS for all the CPUs to be loaded. + +Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux +with 8 CPUs using the AArch32 build of TF-A. + +.. code:: shell + + /FVP_Base_AEMv8A-AEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.CONFIG64=0 \ + -C cluster0.cpu1.CONFIG64=0 \ + -C cluster0.cpu2.CONFIG64=0 \ + -C cluster0.cpu3.CONFIG64=0 \ + -C cluster1.cpu0.CONFIG64=0 \ + -C cluster1.cpu1.CONFIG64=0 \ + -C cluster1.cpu2.CONFIG64=0 \ + -C cluster1.cpu3.CONFIG64=0 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x80080000 \ + --data cluster0.cpu0="/"@0x84000000 + +Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to +boot Linux with 8 CPUs using the AArch64 build of TF-A. + +.. code:: shell + + /FVP_Base_Cortex-A57x4-A53x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x80080000 \ + --data cluster0.cpu0="/"@0x84000000 + +Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to +boot Linux with 4 CPUs using the AArch32 build of TF-A. + +.. code:: shell + + /FVP_Base_Cortex-A32x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x80080000 \ + --data cluster0.cpu0="/"@0x84000000 + + +Running on the AEMv8 Base FVP with reset to BL31 entrypoint +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux +with 8 CPUs using the AArch64 build of TF-A. + +.. code:: shell + + /FVP_Base_RevC-2xAEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.RVBAR=0x04010000 \ + -C cluster0.cpu1.RVBAR=0x04010000 \ + -C cluster0.cpu2.RVBAR=0x04010000 \ + -C cluster0.cpu3.RVBAR=0x04010000 \ + -C cluster1.cpu0.RVBAR=0x04010000 \ + -C cluster1.cpu1.RVBAR=0x04010000 \ + -C cluster1.cpu2.RVBAR=0x04010000 \ + -C cluster1.cpu3.RVBAR=0x04010000 \ + --data cluster0.cpu0="/"@0x04010000 \ + --data cluster0.cpu0="/"@0xff000000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x82000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + --data cluster0.cpu0="/"@0x84000000 + +Notes: + +- If Position Independent Executable (PIE) support is enabled for BL31 + in this config, it can be loaded at any valid address for execution. + +- Since a FIP is not loaded when using BL31 as reset entrypoint, the + ``--data=""@`` + parameter is needed to load the individual bootloader images in memory. + BL32 image is only needed if BL31 has been built to expect a Secure-EL1 + Payload. For the same reason, the FDT needs to be compiled from the DT source + and loaded via the ``--data cluster0.cpu0="/"@0x82000000`` + parameter. + +- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a + specific DTS for all the CPUs to be loaded. + +- The ``-C cluster.cpu.RVBAR=@`` parameter, where + X and Y are the cluster and CPU numbers respectively, is used to set the + reset vector for each core. + +- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require + changing the value of + ``--data=""@`` to the new value of + ``BL32_BASE``. + + +Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux +with 8 CPUs using the AArch32 build of TF-A. + +.. code:: shell + + /FVP_Base_AEMv8A-AEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.CONFIG64=0 \ + -C cluster0.cpu1.CONFIG64=0 \ + -C cluster0.cpu2.CONFIG64=0 \ + -C cluster0.cpu3.CONFIG64=0 \ + -C cluster1.cpu0.CONFIG64=0 \ + -C cluster1.cpu1.CONFIG64=0 \ + -C cluster1.cpu2.CONFIG64=0 \ + -C cluster1.cpu3.CONFIG64=0 \ + -C cluster0.cpu0.RVBAR=0x04002000 \ + -C cluster0.cpu1.RVBAR=0x04002000 \ + -C cluster0.cpu2.RVBAR=0x04002000 \ + -C cluster0.cpu3.RVBAR=0x04002000 \ + -C cluster1.cpu0.RVBAR=0x04002000 \ + -C cluster1.cpu1.RVBAR=0x04002000 \ + -C cluster1.cpu2.RVBAR=0x04002000 \ + -C cluster1.cpu3.RVBAR=0x04002000 \ + --data cluster0.cpu0="/"@0x04002000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x82000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + --data cluster0.cpu0="/"@0x84000000 + +.. note:: + The load address of ```` depends on the value ``BL32_BASE``. + It should match the address programmed into the RVBAR register as well. + +Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to +boot Linux with 8 CPUs using the AArch64 build of TF-A. + +.. code:: shell + + /FVP_Base_Cortex-A57x4-A53x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.RVBARADDR=0x04010000 \ + -C cluster0.cpu1.RVBARADDR=0x04010000 \ + -C cluster0.cpu2.RVBARADDR=0x04010000 \ + -C cluster0.cpu3.RVBARADDR=0x04010000 \ + -C cluster1.cpu0.RVBARADDR=0x04010000 \ + -C cluster1.cpu1.RVBARADDR=0x04010000 \ + -C cluster1.cpu2.RVBARADDR=0x04010000 \ + -C cluster1.cpu3.RVBARADDR=0x04010000 \ + --data cluster0.cpu0="/"@0x04010000 \ + --data cluster0.cpu0="/"@0xff000000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x82000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + --data cluster0.cpu0="/"@0x84000000 + +Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to +boot Linux with 4 CPUs using the AArch32 build of TF-A. + +.. code:: shell + + /FVP_Base_Cortex-A32x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.RVBARADDR=0x04002000 \ + -C cluster0.cpu1.RVBARADDR=0x04002000 \ + -C cluster0.cpu2.RVBARADDR=0x04002000 \ + -C cluster0.cpu3.RVBARADDR=0x04002000 \ + --data cluster0.cpu0="/"@0x04002000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x82000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + --data cluster0.cpu0="/"@0x84000000 + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* + +.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts +.. _Arm's website: `FVP models`_ +.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms +.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 +.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst new file mode 100644 index 000000000..e26f75e56 --- /dev/null +++ b/docs/plat/arm/index.rst @@ -0,0 +1,19 @@ +Arm Development Platforms +========================= + +.. toctree:: + :maxdepth: 1 + :caption: Contents + + juno/index + fvp/index + fvp-ve/index + arm-build-options + +This chapter holds documentation related to Arm's development platforms, +including both software models (FVPs) and hardware development boards +such as Juno. + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst new file mode 100644 index 000000000..6429ede7a --- /dev/null +++ b/docs/plat/arm/juno/index.rst @@ -0,0 +1,246 @@ +Arm Juno Development Platform +============================= + +Platform-specific build options +------------------------------- + +- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone + Media Protection (TZ-MP1). Default value of this flag is 0. + +Running software on Juno +------------------------ + +This version of TF-A has been tested on variants r0, r1 and r2 of Juno. + +To execute the software stack on Juno, the version of the Juno board recovery +image indicated in the `Linaro Release Notes`_ must be installed. If you have an +earlier version installed or are unsure which version is installed, please +re-install the recovery image by following the +`Instructions for using Linaro's deliverables on Juno`_. + +Preparing TF-A images +--------------------- + +After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the +``SOFTWARE/`` directory of the Juno SD card. + +Creating a Firmware Image Package (FIP) +--------------------------------------- + +This section provides Juno and FVP specific instructions to build Trusted +Firmware, obtain the additional required firmware, and pack it all together in +a single FIP binary. It assumes that a Linaro release has been installed. + +.. note:: + Pre-built binaries for AArch32 are available from Linaro Release 16.12 + onwards. Before that release, pre-built binaries are only available for + AArch64. + +.. warning:: + Follow the full instructions for one platform before switching to a + different one. Mixing instructions for different platforms may result in + corrupted binaries. + +.. warning:: + The uboot image downloaded by the Linaro workspace script does not always + match the uboot image packaged as BL33 in the corresponding fip file. It is + recommended to use the version that is packaged in the fip file using the + instructions below. + +.. note:: + For the FVP, the kernel FDT is packaged in FIP during build and loaded + by the firmware at runtime. + +#. Clean the working directory + + .. code:: shell + + make realclean + +#. Obtain SCP_BL2 (Juno) and BL33 (all platforms) + + Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP + package included in the Linaro release: + + .. code:: shell + + # Build the fiptool + make [DEBUG=1] [V=1] fiptool + + # Unpack firmware images from Linaro FIP + ./tools/fiptool/fiptool unpack /[SOFTWARE]/fip.bin + + The unpack operation will result in a set of binary images extracted to the + current working directory. The SCP_BL2 image corresponds to + ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``. + + .. note:: + The fiptool will complain if the images to be unpacked already + exist in the current directory. If that is the case, either delete those + files or use the ``--force`` option to overwrite. + + .. note:: + For AArch32, the instructions below assume that nt-fw.bin is a + normal world boot loader that supports AArch32. + +#. Build TF-A images and create a new FIP for FVP + + .. code:: shell + + # AArch64 + make PLAT=fvp BL33=nt-fw.bin all fip + + # AArch32 + make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip + +#. Build TF-A images and create a new FIP for Juno + + For AArch64: + + Building for AArch64 on Juno simply requires the addition of ``SCP_BL2`` + as a build parameter. + + .. code:: shell + + make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip + + For AArch32: + + Hardware restrictions on Juno prevent cold reset into AArch32 execution mode, + therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled + separately for AArch32. + + - Before building BL32, the environment variable ``CROSS_COMPILE`` must point + to the AArch32 Linaro cross compiler. + + .. code:: shell + + export CROSS_COMPILE=/bin/arm-linux-gnueabihf- + + - Build BL32 in AArch32. + + .. code:: shell + + make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \ + RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32 + + - Save ``bl32.bin`` to a temporary location and clean the build products. + + :: + + cp /bl32.bin + make realclean + + - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE`` + must point to the AArch64 Linaro cross compiler. + + .. code:: shell + + export CROSS_COMPILE=/bin/aarch64-linux-gnu- + + - The following parameters should be used to build BL1 and BL2 in AArch64 + and point to the BL32 file. + + .. code:: shell + + make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \ + BL33=nt-fw.bin SCP_BL2=scp-fw.bin \ + BL32=/bl32.bin all fip + +The resulting BL1 and FIP images may be found in: + +:: + + # Juno + ./build/juno/release/bl1.bin + ./build/juno/release/fip.bin + + # FVP + ./build/fvp/release/bl1.bin + ./build/fvp/release/fip.bin + + +Booting Firmware Update images +------------------------------ + +The new images must be programmed in flash memory by adding +an entry in the ``SITE1/HBI0262x/images.txt`` configuration file +on the Juno SD card (where ``x`` depends on the revision of the Juno board). +Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory +programming" for more information. User should ensure these do not +overlap with any other entries in the file. + +:: + + NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE + NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address] + NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name + NOR10LOAD: 00000000 ;Image Load Address + NOR10ENTRY: 00000000 ;Image Entry Point + + NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE + NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address] + NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name + NOR11LOAD: 00000000 ;Image Load Address + +The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000. +In the same way, the address ns_bl2u_base_address is the value of +NS_BL2U_BASE - 0x8000000. + +.. _plat_juno_booting_el3_payload: + +Booting an EL3 payload +---------------------- + +If the EL3 payload is able to execute in place, it may be programmed in flash +memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file +on the Juno SD card (where ``x`` depends on the revision of the Juno board). +Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory +programming" for more information. + +Alternatively, the same DS-5 command mentioned in the FVP section above can +be used to load the EL3 payload's ELF file over JTAG on Juno. + +For more information on EL3 payloads in general, see +:ref:`alt_boot_flows_el3_payload`. + +Booting a preloaded kernel image +-------------------------------- + +The Trusted Firmware must be compiled in a similar way as for FVP explained +above. The process to load binaries to memory is the one explained in +`plat_juno_booting_el3_payload`_. + +Testing System Suspend +---------------------- + +The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend +to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend +on Juno, at the linux shell prompt, issue the following command: + +.. code:: shell + + echo +10 > /sys/class/rtc/rtc0/wakealarm + echo -n mem > /sys/power/state + +The Juno board should suspend to RAM and then wakeup after 10 seconds due to +wakeup interrupt from RTC. + +Additional Resources +-------------------- + +Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno +software information. Please also refer to the `Juno Getting Started Guide`_ to +get more detailed information about the Juno Arm development platform and how to +configure it. + +-------------- + +*Copyright (c) 2019, Arm Limited. All rights reserved.* + +.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes +.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno +.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/ +.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf +.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf +.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php diff --git a/docs/plat/fvp_ve.rst b/docs/plat/fvp_ve.rst deleted file mode 100644 index 6abf9e5f7..000000000 --- a/docs/plat/fvp_ve.rst +++ /dev/null @@ -1,80 +0,0 @@ -Arm Versatile Express -===================== - -Versatile Express (VE) family development platform provides an ultra fast -environment for prototyping Armv7 System-on-Chip designs. VE Fixed Virtual -Platforms (FVP) are simulations of Versatile Express boards. The platform in -Trusted Firmware-A has been verified with Arm Cortex-A5 and Cortex-A7 VE FVP's. -This platform is tested on and only expected to work with single core models. - -Boot Sequence -------------- - -BL1 --> BL2 --> BL32(sp_min) --> BL33(u-boot) --> Linux kernel - -How to build ------------- - -Code Locations -~~~~~~~~~~~~~~ -- `U-boot `__ - -- `Trusted Firmware-A `__ - -Build Procedure -~~~~~~~~~~~~~~~ - -- Obtain arm toolchain. The software stack has been verified with linaro 6.2 - `arm-linux-gnueabihf `__. - Set the CROSS_COMPILE environment variable to point to the toolchain folder. - -- Fetch and build u-boot. - Make the .config file using the command: - - .. code:: shell - - make ARCH=arm vexpress_aemv8a_aarch32_config - - Make the u-boot binary for Cortex-A5 using the command: - - .. code:: shell - - make ARCH=arm SUPPORT_ARCH_TIMER=no - - Make the u-boot binary for Cortex-A7 using the command: - - .. code:: shell - - make ARCH=arm - - -- Build TF-A: - - The make command for Cortex-A5 is: - - .. code:: shell - - make PLAT=fvp_ve ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes \ - AARCH32_SP=sp_min FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts \ - ARM_XLAT_TABLES_LIB_V1=1 BL33= all fip - - The make command for Cortex-A7 is: - - .. code:: shell - - make PLAT=fvp_ve ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \ - AARCH32_SP=sp_min FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A7x1.dts \ - BL33= all fip - -Run Procedure -~~~~~~~~~~~~~ - -The following model parameters should be used to boot Linux using the build of -Trusted Firmware-A made using the above make commands: - - .. code:: shell - - ./ \ - -C motherboard.flashloader1.fname= \ - --data cluster.cpu0=@0x80080000 \ - --data cluster.cpu0=@0x84000000 diff --git a/docs/plat/index.rst b/docs/plat/index.rst index 5495280aa..63d29a9be 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -8,10 +8,10 @@ Platform Ports :hidden: allwinner + arm/index meson-gxbb meson-gxl meson-g12a - fvp_ve hikey hikey960 intel-agilex @@ -38,81 +38,19 @@ Platform Ports xilinx-zynqmp This section provides a list of supported upstream *platform ports* and the -documentation associated with them. The list of suported Arm |FVP| platforms is -outlined in the following section. +documentation associated with them. .. note:: In addition to the platforms ports listed within the table of contents, there are several additional platforms that are supported upstream but which do not currently have associated documentation: - - Arm Juno Software Development Platform. Various |AArch32| and |AArch64| - builds of this release have been tested on r0, r1 and r2 variants of the - `Juno Arm Development Platform`_. - Arm Neoverse N1 System Development Platform (N1SDP) - Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP - Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP - Arm SGI-575 and SGM-775 - MediaTek MT6795 and MT8173 SoCs -Fixed Virtual Platform (FVP) Support ------------------------------------- - -The latest version of the AArch64 build of TF-A has been tested on the -following Arm FVPs without shifted affinities, and that do not support threaded -CPU cores (64-bit host machine only). - -.. note:: - The FVP models used are Version 11.6 Build 45, unless otherwise stated. - -- ``FVP_Base_AEMv8A-AEMv8A`` -- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` -- ``FVP_Base_RevC-2xAEMv8A`` -- ``FVP_Base_Cortex-A32x4`` -- ``FVP_Base_Cortex-A35x4`` -- ``FVP_Base_Cortex-A53x4`` -- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` -- ``FVP_Base_Cortex-A55x4`` -- ``FVP_Base_Cortex-A57x1-A53x1`` -- ``FVP_Base_Cortex-A57x2-A53x4`` -- ``FVP_Base_Cortex-A57x4-A53x4`` -- ``FVP_Base_Cortex-A57x4`` -- ``FVP_Base_Cortex-A72x4-A53x4`` -- ``FVP_Base_Cortex-A72x4`` -- ``FVP_Base_Cortex-A73x4-A53x4`` -- ``FVP_Base_Cortex-A73x4`` -- ``FVP_Base_Cortex-A75x4`` -- ``FVP_Base_Cortex-A76x4`` -- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model) -- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model) -- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) -- ``FVP_Base_Zeusx4`` -- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model) -- ``FVP_CSS_SGI-575`` (Version 11.3 build 42) -- ``FVP_CSS_SGM-775`` (Version 11.3 build 42) -- ``FVP_RD_E1Edge`` (Version 11.3 build 42) -- ``FVP_RD_N1Edge`` (Version 11.3 build 42) -- ``Foundation_Platform`` - -The latest version of the AArch32 build of TF-A has been tested on the -following Arm FVPs without shifted affinities, and that do not support threaded -CPU cores (64-bit host machine only). - -- ``FVP_Base_AEMv8A-AEMv8A`` -- ``FVP_Base_Cortex-A32x4`` - -.. note:: - The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities. - -The *Foundation* and *Base* FVPs can be downloaded free of charge. See the -`Arm FVP website`_. - -All the above platforms have been tested with `Linaro Release 19.06`_. - -------------- *Copyright (c) 2019, Arm Limited. All rights reserved.* - -.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php -.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms -.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 diff --git a/docs/plat/marvell/build.rst b/docs/plat/marvell/build.rst index c8923e43a..c10bcff79 100644 --- a/docs/plat/marvell/build.rst +++ b/docs/plat/marvell/build.rst @@ -194,8 +194,8 @@ Special Build Flags can interrupt UART recovery process). This MACRO definition is set in ``plat/marvell/a8k/common/include/platform_def.h`` file. -For more information about build options, please refer to section -'Summary of build options' in the :ref:`User Guide`. +For more information about build options, please refer to the +:ref:`Build Options` document. Build output @@ -251,4 +251,3 @@ Armada70x0 and Armada80x0 Builds require installation of an additional component (use the "mv_ddr-armada-atf-mainline" branch): https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git - diff --git a/docs/plat/socionext-uniphier.rst b/docs/plat/socionext-uniphier.rst index 964dd1db9..92881932c 100644 --- a/docs/plat/socionext-uniphier.rst +++ b/docs/plat/socionext-uniphier.rst @@ -80,7 +80,8 @@ Optional features - Trusted Board Boot `mbed TLS`_ is needed as the cryptographic and image parser modules. - Refer to the :ref:`User Guide` for the appropriate version of mbed TLS. + Refer to the :ref:`Prerequisites` document for the appropriate version of + mbed TLS. To enable TBB, add the following options to the build command:: diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst index fdb702ffe..f569fcbe7 100644 --- a/docs/process/contributing.rst +++ b/docs/process/contributing.rst @@ -13,8 +13,8 @@ Getting Started raise a separate `issue`_ for this and ensure that the changes that include Third Party IP are made on a separate topic branch. -- Clone `Trusted Firmware-A`_ on your own machine as suggested in the - :ref:`User Guide`. +- Clone `Trusted Firmware-A`_ on your own machine as described in + :ref:`prerequisites_get_source`. - Create a local topic branch based on the `Trusted Firmware-A`_ ``master`` branch. @@ -26,8 +26,7 @@ Making Changes - Follow the :ref:`Coding Style & Guidelines`. - Use the checkpatch.pl script provided with the Linux source tree. A - Makefile target is provided for convenience (see the "Checking source code - style" section in the :ref:`User Guide`). + Makefile target is provided for convenience. - Keep the commits on topic. If you need to fix another bug or make another enhancement, please create a separate `issue`_ and address it on a separate @@ -38,8 +37,9 @@ Making Changes an `issue`_, include a reference. - Where appropriate, please update the documentation. - - Consider whether the :ref:`User Guide`, :ref:`Porting Guide`, - :ref:`Firmware Design` or other in-source documentation needs updating. + - Consider whether the :ref:`Porting Guide`, + :ref:`Firmware Design` document or other in-source documentation needs + updating. - Ensure that each changed file has the correct copyright and license information. Files that entirely consist of contributions to this project should have a copyright notice and BSD-3-Clause SPDX license @@ -63,9 +63,9 @@ Making Changes include the documentation changes within the single commit. - Please test your changes. As a minimum, ensure that Linux boots on the - Foundation FVP. See :ref:`user_guide_run_fvp` for more information. For - more extensive testing, consider running the `TF-A Tests`_ against your - patches. + Foundation FVP. See :ref:`Arm Fixed Virtual Platforms (FVP)` for more + information. For more extensive testing, consider running the `TF-A Tests`_ + against your patches. Submitting Changes ------------------ @@ -82,7 +82,8 @@ Submitting Changes - Ensure that each commit also has a unique ``Change-Id:`` line. If you have cloned the repository with the "`Clone with commit-msg hook`" clone method - (as advised on the :ref:`User Guide`), this should already be the case. + (following the :ref:`Prerequisites` document), this should already be the + case. More details may be found in the `Gerrit Change-Ids documentation`_. diff --git a/docs/process/security-hardening.rst b/docs/process/security-hardening.rst index 1a5524fd8..86aeb739d 100644 --- a/docs/process/security-hardening.rst +++ b/docs/process/security-hardening.rst @@ -9,7 +9,7 @@ Build options ------------- Several build options can be used to check for security issues. Refer to the -:ref:`User Guide` for detailed information on the specific build options. +:ref:`Build Options` for detailed information on these. - The ``BRANCH_PROTECTION`` build flag can be used to enable Pointer Authentication and Branch Target Identification. -- cgit v1.2.3 From 48393e30c330e42cdd7b547cb0b7e2d745015afb Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 27 Nov 2019 14:59:36 +0100 Subject: rockchip: px30: Add support for UART3 as serial output Add the UART3 base definition for serial output, which is used on some PX30 SoM boards. Signed-off-by: Paul Kocialkowski Change-Id: I8490b15c9f129a33c01cb78bd78675014bc7b015 --- plat/rockchip/px30/px30_def.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plat/rockchip/px30/px30_def.h b/plat/rockchip/px30/px30_def.h index 9b8ccfca6..283b60641 100644 --- a/plat/rockchip/px30/px30_def.h +++ b/plat/rockchip/px30/px30_def.h @@ -54,6 +54,9 @@ #define UART2_BASE 0xff160000 #define UART2_SIZE SIZE_K(64) +#define UART3_BASE 0xff168000 +#define UART3_SIZE SIZE_K(64) + #define UART5_BASE 0xff178000 #define UART5_SIZE SIZE_K(64) -- cgit v1.2.3 From 328718f2545a9aa2e731e141deb965baf8b6c6e6 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Wed, 23 Oct 2019 16:26:53 +0800 Subject: intel: Refactor common platform code [1/5] Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by: Hadi Asyrafi Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d --- plat/intel/soc/agilex/bl2_plat_setup.c | 4 +- plat/intel/soc/agilex/bl31_plat_setup.c | 8 +- .../soc/agilex/include/agilex_clock_manager.h | 2 +- plat/intel/soc/agilex/include/agilex_handoff.h | 96 ---------- plat/intel/soc/agilex/include/agilex_pinmux.h | 2 +- plat/intel/soc/agilex/include/platform_def.h | 196 -------------------- plat/intel/soc/agilex/include/socfpga_plat_def.h | 23 +++ plat/intel/soc/agilex/platform.mk | 3 +- plat/intel/soc/agilex/soc/agilex_clock_manager.c | 2 +- plat/intel/soc/agilex/soc/agilex_handoff.c | 40 ----- plat/intel/soc/common/include/platform_def.h | 198 +++++++++++++++++++++ plat/intel/soc/common/include/socfpga_handoff.h | 136 ++++++++++++++ plat/intel/soc/common/soc/socfpga_handoff.c | 39 ++++ plat/intel/soc/stratix10/bl2_plat_setup.c | 4 +- plat/intel/soc/stratix10/bl31_plat_setup.c | 9 +- plat/intel/soc/stratix10/include/platform_def.h | 198 --------------------- .../soc/stratix10/include/s10_clock_manager.h | 2 +- plat/intel/soc/stratix10/include/s10_handoff.h | 98 ---------- plat/intel/soc/stratix10/include/s10_pinmux.h | 2 +- .../intel/soc/stratix10/include/socfpga_plat_def.h | 22 +++ plat/intel/soc/stratix10/platform.mk | 3 +- plat/intel/soc/stratix10/soc/s10_clock_manager.c | 2 +- plat/intel/soc/stratix10/soc/s10_handoff.c | 47 ----- 23 files changed, 438 insertions(+), 698 deletions(-) delete mode 100644 plat/intel/soc/agilex/include/agilex_handoff.h delete mode 100644 plat/intel/soc/agilex/include/platform_def.h create mode 100644 plat/intel/soc/agilex/include/socfpga_plat_def.h delete mode 100644 plat/intel/soc/agilex/soc/agilex_handoff.c create mode 100644 plat/intel/soc/common/include/platform_def.h create mode 100644 plat/intel/soc/common/include/socfpga_handoff.h create mode 100644 plat/intel/soc/common/soc/socfpga_handoff.c delete mode 100644 plat/intel/soc/stratix10/include/platform_def.h delete mode 100644 plat/intel/soc/stratix10/include/s10_handoff.h create mode 100644 plat/intel/soc/stratix10/include/socfpga_plat_def.h delete mode 100644 plat/intel/soc/stratix10/soc/s10_handoff.c diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index e9ab92850..fa9a6a54e 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -18,7 +18,6 @@ #include #include "agilex_clock_manager.h" -#include "agilex_handoff.h" #include "agilex_mailbox.h" #include "agilex_memory_controller.h" #include "agilex_pinmux.h" @@ -28,6 +27,7 @@ #include "ccu/ncore_ccu.h" #include "qspi/cadence_qspi.h" +#include "socfpga_handoff.h" #include "wdt/watchdog.h" @@ -59,7 +59,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, generic_delay_timer_init(); - if (agilex_get_handoff(&reverse_handoff_ptr)) + if (socfpga_get_handoff(&reverse_handoff_ptr)) return; config_pinmux(&reverse_handoff_ptr); boot_source = reverse_handoff_ptr.boot_source; diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c index c8765e857..e7852cfab 100644 --- a/plat/intel/soc/agilex/bl31_plat_setup.c +++ b/plat/intel/soc/agilex/bl31_plat_setup.c @@ -67,15 +67,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, } static const interrupt_prop_t s10_interrupt_props[] = { - PLAT_INTEL_AGX_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), - PLAT_INTEL_AGX_G0_IRQ_PROPS(GICV2_INTR_GROUP0) + PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), + PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) }; static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; static const gicv2_driver_data_t plat_gicv2_gic_data = { - .gicd_base = PLAT_INTEL_AGX_GICD_BASE, - .gicc_base = PLAT_INTEL_AGX_GICC_BASE, + .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, + .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, .interrupt_props = s10_interrupt_props, .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), .target_masks = target_mask_array, diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h index 0822290aa..8af6a60bc 100644 --- a/plat/intel/soc/agilex/include/agilex_clock_manager.h +++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h @@ -7,7 +7,7 @@ #ifndef CLOCKMANAGER_H #define CLOCKMANAGER_H -#include "agilex_handoff.h" +#include "socfpga_handoff.h" /* Clock Manager Registers */ #define CLKMGR_OFFSET 0xffd10000 diff --git a/plat/intel/soc/agilex/include/agilex_handoff.h b/plat/intel/soc/agilex/include/agilex_handoff.h deleted file mode 100644 index 201640611..000000000 --- a/plat/intel/soc/agilex/include/agilex_handoff.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef HANDOFF_H -#define HANDOFF_H - -#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */ -#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */ -#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */ -#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */ -#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */ -#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ -#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ - -typedef struct handoff_t { - /* header */ - uint32_t header_magic; - uint32_t header_device; - uint32_t _pad_0x08_0x10[2]; - - /* pinmux configuration - select */ - uint32_t pinmux_sel_magic; - uint32_t pinmux_sel_length; - uint32_t _pad_0x18_0x20[2]; - uint32_t pinmux_sel_array[96]; /* offset, value */ - - /* pinmux configuration - io control */ - uint32_t pinmux_io_magic; - uint32_t pinmux_io_length; - uint32_t _pad_0x1a8_0x1b0[2]; - uint32_t pinmux_io_array[96]; /* offset, value */ - - /* pinmux configuration - use fpga switch */ - uint32_t pinmux_fpga_magic; - uint32_t pinmux_fpga_length; - uint32_t _pad_0x338_0x340[2]; - uint32_t pinmux_fpga_array[42]; /* offset, value */ - uint32_t _pad_0x3e8_0x3f0[2]; - - /* pinmux configuration - io delay */ - uint32_t pinmux_delay_magic; - uint32_t pinmux_delay_length; - uint32_t _pad_0x3f8_0x400[2]; - uint32_t pinmux_iodelay_array[96]; /* offset, value */ - - /* clock configuration */ - uint32_t clock_magic; - uint32_t clock_length; - uint32_t _pad_0x588_0x590[2]; - uint32_t main_pll_mpuclk; - uint32_t main_pll_nocclk; - uint32_t main_pll_nocdiv; - uint32_t main_pll_pllglob; - uint32_t main_pll_fdbck; - uint32_t main_pll_pllc0; - uint32_t main_pll_pllc1; - uint32_t main_pll_pllc2; - uint32_t main_pll_pllc3; - uint32_t main_pll_pllm; - uint32_t per_pll_emacctl; - uint32_t per_pll_gpiodiv; - uint32_t per_pll_pllglob; - uint32_t per_pll_fdbck; - uint32_t per_pll_pllc0; - uint32_t per_pll_pllc1; - uint32_t per_pll_pllc2; - uint32_t per_pll_pllc3; - uint32_t per_pll_pllm; - uint32_t alt_emacactr; - uint32_t alt_emacbctr; - uint32_t alt_emacptpctr; - uint32_t alt_gpiodbctr; - uint32_t alt_sdmmcctr; - uint32_t alt_s2fuser0ctr; - uint32_t alt_s2fuser1ctr; - uint32_t alt_psirefctr; - uint32_t hps_osc_clk_h; - uint32_t fpga_clk_hz; - uint32_t _pad_0x604_0x610[3]; - - /* misc configuration */ - uint32_t misc_magic; - uint32_t misc_length; - uint32_t _pad_0x618_0x620[2]; - uint32_t boot_source; -} handoff; - -int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); -int agilex_get_handoff(handoff *hoff_ptr); - -#endif - - diff --git a/plat/intel/soc/agilex/include/agilex_pinmux.h b/plat/intel/soc/agilex/include/agilex_pinmux.h index e6a7b341d..fe01062c0 100644 --- a/plat/intel/soc/agilex/include/agilex_pinmux.h +++ b/plat/intel/soc/agilex/include/agilex_pinmux.h @@ -12,7 +12,7 @@ #define AGX_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300 #define AGX_PINMUX_IO0_DELAY 0xffd13400 -#include "agilex_handoff.h" +#include "socfpga_handoff.h" void config_pinmux(handoff *handoff); diff --git a/plat/intel/soc/agilex/include/platform_def.h b/plat/intel/soc/agilex/include/platform_def.h deleted file mode 100644 index 277862a30..000000000 --- a/plat/intel/soc/agilex/include/platform_def.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLATFORM_DEF_H -#define PLATFORM_DEF_H - -#include -#include -#include -#include - - -#define PLAT_CPUID_RELEASE 0xffe1b000 -#define PLAT_SEC_ENTRY 0xffe1b008 - -/* Define next boot image name and offset */ -#define PLAT_NS_IMAGE_OFFSET 0x50000 -#define PLAT_HANDOFF_OFFSET 0xFFE3F000 - -/******************************************************************************* - * Platform binary types for linking - ******************************************************************************/ -#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" -#define PLATFORM_LINKER_ARCH aarch64 - -/* Agilex supports up to 124GB RAM */ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) - - -/******************************************************************************* - * Generic platform constants - ******************************************************************************/ -#define PLAT_PRIMARY_CPU 0 -#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 - -/* Size of cacheable stacks */ -#define PLATFORM_STACK_SIZE 0x2000 - -/* PSCI related constant */ -#define PLAT_NUM_POWER_DOMAINS 5 -#define PLAT_MAX_PWR_LVL 1 -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 -#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ - PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 - -/* Interrupt related constant */ - -#define INTEL_AGX_IRQ_SEC_PHY_TIMER 29 - -#define INTEL_AGX_IRQ_SEC_SGI_0 8 -#define INTEL_AGX_IRQ_SEC_SGI_1 9 -#define INTEL_AGX_IRQ_SEC_SGI_2 10 -#define INTEL_AGX_IRQ_SEC_SGI_3 11 -#define INTEL_AGX_IRQ_SEC_SGI_4 12 -#define INTEL_AGX_IRQ_SEC_SGI_5 13 -#define INTEL_AGX_IRQ_SEC_SGI_6 14 -#define INTEL_AGX_IRQ_SEC_SGI_7 15 - -#define TSP_IRQ_SEC_PHY_TIMER INTEL_AGX_IRQ_SEC_PHY_TIMER -#define TSP_SEC_MEM_BASE BL32_BASE -#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) -/******************************************************************************* - * Platform memory map related constants - ******************************************************************************/ -#define DRAM_BASE (0x0) -#define DRAM_SIZE (0x80000000) - -#define OCRAM_BASE (0xFFE00000) -#define OCRAM_SIZE (0x00040000) - -#define MEM64_BASE (0x0100000000) -#define MEM64_SIZE (0x1F00000000) - -#define DEVICE1_BASE (0x80000000) -#define DEVICE1_SIZE (0x60000000) - -#define DEVICE2_BASE (0xF7000000) -#define DEVICE2_SIZE (0x08E00000) - -#define DEVICE3_BASE (0xFFFC0000) -#define DEVICE3_SIZE (0x00008000) - -#define DEVICE4_BASE (0x2000000000) -#define DEVICE4_SIZE (0x0100000000) - -/******************************************************************************* - * BL31 specific defines. - ******************************************************************************/ -/* - * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if - * present). BL31_BASE is calculated using the current BL3-1 debug size plus a - * little space for growth. - */ - - -#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" - -#define BL1_RO_BASE (0xffe00000) -#define BL1_RO_LIMIT (0xffe0f000) -#define BL1_RW_BASE (0xffe10000) -#define BL1_RW_LIMIT (0xffe1ffff) -#define BL1_RW_SIZE (0x14000) - -#define BL2_BASE (0xffe00000) -#define BL2_LIMIT (0xffe1b000) - -#define BL31_BASE (0xffe1c000) -#define BL31_LIMIT (0xffe3bfff) - -/******************************************************************************* - * Platform specific page table and MMU setup constants - ******************************************************************************/ -#define MAX_XLAT_TABLES 8 -#define MAX_MMAP_REGIONS 16 - -/******************************************************************************* - * Declarations and constants to access the mailboxes safely. Each mailbox is - * aligned on the biggest cache line size in the platform. This is known only - * to the platform as it might have a combination of integrated and external - * caches. Such alignment ensures that two maiboxes do not sit on the same cache - * line at any cache level. They could belong to different cpus/clusters & - * get written while being protected by different locks causing corruption of - * a valid mailbox address. - ******************************************************************************/ -#define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) - -#define PLAT_GIC_BASE (0xFFFC0000) -#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) -#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) -#define PLAT_GICR_BASE 0 - -/******************************************************************************* - * UART related constants - ******************************************************************************/ -#define PLAT_UART0_BASE (0xFFC02000) -#define PLAT_UART1_BASE (0xFFC02100) - -#define CRASH_CONSOLE_BASE PLAT_UART0_BASE - -#define PLAT_BAUDRATE (115200) -#define PLAT_UART_CLOCK (100000000) - -/******************************************************************************* - * System counter frequency related constants - ******************************************************************************/ -#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) -#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400) - -#define PLAT_INTEL_AGX_GICD_BASE PLAT_GICD_BASE -#define PLAT_INTEL_AGX_GICC_BASE PLAT_GICC_BASE - -/* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define PLAT_INTEL_AGX_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE) - -#define PLAT_INTEL_AGX_G0_IRQ_PROPS(grp) - -#define MAX_IO_HANDLES 4 -#define MAX_IO_DEVICES 4 -#define MAX_IO_BLOCK_DEVICES 2 - -#endif /* PLATFORM_DEF_H */ - diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h new file mode 100644 index 000000000..a346cb5f8 --- /dev/null +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_SOCFPGA_DEF_H +#define PLAT_SOCFPGA_DEF_H + +#include + +/* Platform Setting */ +#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX + +/* Register Mapping */ +#define SOCFPGA_MMC_REG_BASE 0xff808000 + +#define SOCFPGA_RSTMGR_OFST 0xffd11000 +#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020 + +#endif /* PLAT_SOCFPGA_DEF_H */ + diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index d1ea62915..f21e84268 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -40,10 +40,10 @@ BL2_SOURCES += \ plat/intel/soc/agilex/socfpga_storage.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/agilex/soc/agilex_reset_manager.c \ - plat/intel/soc/agilex/soc/agilex_handoff.c \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ plat/intel/soc/agilex/soc/agilex_memory_controller.c \ + plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/agilex/soc/agilex_system_manager.c \ @@ -65,7 +65,6 @@ BL31_SOURCES += \ plat/intel/soc/agilex/soc/agilex_reset_manager.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ - plat/intel/soc/agilex/soc/agilex_handoff.c \ plat/intel/soc/agilex/soc/agilex_mailbox.c PROGRAMMABLE_RESET_ADDRESS := 0 diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c index 06891ff93..96b669cfd 100644 --- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c +++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c @@ -11,8 +11,8 @@ #include #include "agilex_clock_manager.h" -#include "agilex_handoff.h" #include "agilex_system_manager.h" +#include "socfpga_handoff.h" uint32_t wait_pll_lock(void) diff --git a/plat/intel/soc/agilex/soc/agilex_handoff.c b/plat/intel/soc/agilex/soc/agilex_handoff.c deleted file mode 100644 index a458686f1..000000000 --- a/plat/intel/soc/agilex/soc/agilex_handoff.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include "agilex_handoff.h" - -#define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) | \ - (((x) & 0x0000FF00) << 8) | ((x) << 24)) - -int agilex_get_handoff(handoff *reverse_hoff_ptr) -{ - int i; - uint32_t *buffer; - handoff *handoff_ptr = (handoff *) PLAT_HANDOFF_OFFSET; - - memcpy(reverse_hoff_ptr, handoff_ptr, sizeof(handoff)); - buffer = (uint32_t *)reverse_hoff_ptr; - - /* convert big endian to little endian */ - for (i = 0; i < sizeof(handoff) / 4; i++) - buffer[i] = SWAP_UINT32(buffer[i]); - - if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER) - return -1; - if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL) - return -1; - if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR) - return -1; - if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA) - return -1; - if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY) - return -1; - - return 0; -} diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h new file mode 100644 index 000000000..e57aafb6a --- /dev/null +++ b/plat/intel/soc/common/include/platform_def.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include +#include +#include + +#define PLAT_SOCFPGA_STRATIX10 1 +#define PLAT_SOCFPGA_AGILEX 2 + +#define PLAT_CPUID_RELEASE 0xffe1b000 +#define PLAT_SEC_ENTRY 0xffe1b008 + +/* Define next boot image name and offset */ +#define PLAT_NS_IMAGE_OFFSET 0x50000 +#define PLAT_HANDOFF_OFFSET 0xFFE3F000 + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/* SoCFPGA supports up to 124GB RAM */ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) + + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ +#define PLAT_PRIMARY_CPU 0 +#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 + +/* Size of cacheable stacks */ +#define PLATFORM_STACK_SIZE 0x2000 + +/* PSCI related constant */ +#define PLAT_NUM_POWER_DOMAINS 5 +#define PLAT_MAX_PWR_LVL 1 +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 2 +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 + +/* Interrupt related constant */ + +#define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 + +#define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 + +#define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER +#define TSP_SEC_MEM_BASE BL32_BASE +#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define DRAM_BASE (0x0) +#define DRAM_SIZE (0x80000000) + +#define OCRAM_BASE (0xFFE00000) +#define OCRAM_SIZE (0x00040000) + +#define MEM64_BASE (0x0100000000) +#define MEM64_SIZE (0x1F00000000) + +#define DEVICE1_BASE (0x80000000) +#define DEVICE1_SIZE (0x60000000) + +#define DEVICE2_BASE (0xF7000000) +#define DEVICE2_SIZE (0x08E00000) + +#define DEVICE3_BASE (0xFFFC0000) +#define DEVICE3_SIZE (0x00008000) + +#define DEVICE4_BASE (0x2000000000) +#define DEVICE4_SIZE (0x0100000000) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL3-1 debug size plus a + * little space for growth. + */ + + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define BL1_RO_BASE (0xffe00000) +#define BL1_RO_LIMIT (0xffe0f000) +#define BL1_RW_BASE (0xffe10000) +#define BL1_RW_LIMIT (0xffe1ffff) +#define BL1_RW_SIZE (0x14000) + +#define BL2_BASE (0xffe00000) +#define BL2_LIMIT (0xffe1b000) + +#define BL31_BASE (0xffe1c000) +#define BL31_LIMIT (0xffe3bfff) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define MAX_XLAT_TABLES 8 +#define MAX_MMAP_REGIONS 16 + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#define PLAT_GIC_BASE (0xFFFC0000) +#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) +#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) +#define PLAT_GICR_BASE 0 + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define PLAT_UART0_BASE (0xFFC02000) +#define PLAT_UART1_BASE (0xFFC02100) + +#define CRASH_CONSOLE_BASE PLAT_UART0_BASE + +#define PLAT_BAUDRATE (115200) +#define PLAT_UART_CLOCK (100000000) + +/******************************************************************************* + * System counter frequency related constants + ******************************************************************************/ +#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) +#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400) + +#define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE +#define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) + +#define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) + +#define MAX_IO_HANDLES 4 +#define MAX_IO_DEVICES 4 +#define MAX_IO_BLOCK_DEVICES 2 + +#endif /* PLATFORM_DEF_H */ + diff --git a/plat/intel/soc/common/include/socfpga_handoff.h b/plat/intel/soc/common/include/socfpga_handoff.h new file mode 100644 index 000000000..889d13767 --- /dev/null +++ b/plat/intel/soc/common/include/socfpga_handoff.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef HANDOFF_H +#define HANDOFF_H + +#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */ +#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */ +#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */ +#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */ +#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */ +#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ +#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ + +#include + +typedef struct handoff_t { + /* header */ + uint32_t header_magic; + uint32_t header_device; + uint32_t _pad_0x08_0x10[2]; + + /* pinmux configuration - select */ + uint32_t pinmux_sel_magic; + uint32_t pinmux_sel_length; + uint32_t _pad_0x18_0x20[2]; + uint32_t pinmux_sel_array[96]; /* offset, value */ + + /* pinmux configuration - io control */ + uint32_t pinmux_io_magic; + uint32_t pinmux_io_length; + uint32_t _pad_0x1a8_0x1b0[2]; + uint32_t pinmux_io_array[96]; /* offset, value */ + + /* pinmux configuration - use fpga switch */ + uint32_t pinmux_fpga_magic; + uint32_t pinmux_fpga_length; + uint32_t _pad_0x338_0x340[2]; + uint32_t pinmux_fpga_array[42]; /* offset, value */ + uint32_t _pad_0x3e8_0x3f0[2]; + + /* pinmux configuration - io delay */ + uint32_t pinmux_delay_magic; + uint32_t pinmux_delay_length; + uint32_t _pad_0x3f8_0x400[2]; + uint32_t pinmux_iodelay_array[96]; /* offset, value */ + + /* clock configuration */ + +#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 + uint32_t clock_magic; + uint32_t clock_length; + uint32_t _pad_0x588_0x590[2]; + uint32_t main_pll_mpuclk; + uint32_t main_pll_nocclk; + uint32_t main_pll_cntr2clk; + uint32_t main_pll_cntr3clk; + uint32_t main_pll_cntr4clk; + uint32_t main_pll_cntr5clk; + uint32_t main_pll_cntr6clk; + uint32_t main_pll_cntr7clk; + uint32_t main_pll_cntr8clk; + uint32_t main_pll_cntr9clk; + uint32_t main_pll_nocdiv; + uint32_t main_pll_pllglob; + uint32_t main_pll_fdbck; + uint32_t main_pll_pllc0; + uint32_t main_pll_pllc1; + uint32_t _pad_0x5cc_0x5d0[1]; + uint32_t per_pll_cntr2clk; + uint32_t per_pll_cntr3clk; + uint32_t per_pll_cntr4clk; + uint32_t per_pll_cntr5clk; + uint32_t per_pll_cntr6clk; + uint32_t per_pll_cntr7clk; + uint32_t per_pll_cntr8clk; + uint32_t per_pll_cntr9clk; + uint32_t per_pll_emacctl; + uint32_t per_pll_gpiodiv; + uint32_t per_pll_pllglob; + uint32_t per_pll_fdbck; + uint32_t per_pll_pllc0; + uint32_t per_pll_pllc1; + uint32_t hps_osc_clk_h; + uint32_t fpga_clk_hz; +#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX + uint32_t clock_magic; + uint32_t clock_length; + uint32_t _pad_0x588_0x590[2]; + uint32_t main_pll_mpuclk; + uint32_t main_pll_nocclk; + uint32_t main_pll_nocdiv; + uint32_t main_pll_pllglob; + uint32_t main_pll_fdbck; + uint32_t main_pll_pllc0; + uint32_t main_pll_pllc1; + uint32_t main_pll_pllc2; + uint32_t main_pll_pllc3; + uint32_t main_pll_pllm; + uint32_t per_pll_emacctl; + uint32_t per_pll_gpiodiv; + uint32_t per_pll_pllglob; + uint32_t per_pll_fdbck; + uint32_t per_pll_pllc0; + uint32_t per_pll_pllc1; + uint32_t per_pll_pllc2; + uint32_t per_pll_pllc3; + uint32_t per_pll_pllm; + uint32_t alt_emacactr; + uint32_t alt_emacbctr; + uint32_t alt_emacptpctr; + uint32_t alt_gpiodbctr; + uint32_t alt_sdmmcctr; + uint32_t alt_s2fuser0ctr; + uint32_t alt_s2fuser1ctr; + uint32_t alt_psirefctr; + uint32_t hps_osc_clk_h; + uint32_t fpga_clk_hz; + uint32_t _pad_0x604_0x610[3]; +#endif + /* misc configuration */ + uint32_t misc_magic; + uint32_t misc_length; + uint32_t _pad_0x618_0x620[2]; + uint32_t boot_source; +} handoff; + +int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); +int socfpga_get_handoff(handoff *hoff_ptr); + +#endif + + diff --git a/plat/intel/soc/common/soc/socfpga_handoff.c b/plat/intel/soc/common/soc/socfpga_handoff.c new file mode 100644 index 000000000..4bb3a9619 --- /dev/null +++ b/plat/intel/soc/common/soc/socfpga_handoff.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "socfpga_handoff.h" + +#define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) | \ + (((x) & 0x0000FF00) << 8) | ((x) << 24)) + +int socfpga_get_handoff(handoff *reverse_hoff_ptr) +{ + int i; + uint32_t *buffer; + handoff *handoff_ptr = (handoff *) PLAT_HANDOFF_OFFSET; + + memcpy(reverse_hoff_ptr, handoff_ptr, sizeof(handoff)); + buffer = (uint32_t *)reverse_hoff_ptr; + + /* convert big endian to little endian */ + for (i = 0; i < sizeof(handoff) / 4; i++) + buffer[i] = SWAP_UINT32(buffer[i]); + + if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER) + return -1; + if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL) + return -1; + if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR) + return -1; + if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA) + return -1; + if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY) + return -1; + + return 0; +} diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index f24bbdec4..cc6b4a7c2 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -27,11 +27,11 @@ #include "s10_memory_controller.h" #include "s10_reset_manager.h" #include "s10_clock_manager.h" -#include "s10_handoff.h" #include "s10_pinmux.h" #include "stratix10_private.h" #include "include/s10_mailbox.h" #include "qspi/cadence_qspi.h" +#include "socfpga_handoff.h" #include "wdt/watchdog.h" @@ -63,7 +63,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, generic_delay_timer_init(); - if (s10_get_handoff(&reverse_handoff_ptr)) + if (socfpga_get_handoff(&reverse_handoff_ptr)) return; config_pinmux(&reverse_handoff_ptr); boot_source = reverse_handoff_ptr.boot_source; diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 7c9833b33..46ef7cbf0 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -23,7 +23,6 @@ #include #include "stratix10_private.h" -#include "s10_handoff.h" #include "s10_reset_manager.h" #include "s10_memory_controller.h" #include "s10_pinmux.h" @@ -82,15 +81,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, } static const interrupt_prop_t s10_interrupt_props[] = { - PLAT_INTEL_S10_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), - PLAT_INTEL_S10_G0_IRQ_PROPS(GICV2_INTR_GROUP0) + PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), + PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) }; static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; static const gicv2_driver_data_t plat_gicv2_gic_data = { - .gicd_base = PLAT_INTEL_S10_GICD_BASE, - .gicc_base = PLAT_INTEL_S10_GICC_BASE, + .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, + .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, .interrupt_props = s10_interrupt_props, .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), .target_masks = target_mask_array, diff --git a/plat/intel/soc/stratix10/include/platform_def.h b/plat/intel/soc/stratix10/include/platform_def.h deleted file mode 100644 index a753acd20..000000000 --- a/plat/intel/soc/stratix10/include/platform_def.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ - -#include -#include -#include -#include -#include -#include - - -#define PLAT_CPUID_RELEASE 0xffe1b000 -#define PLAT_SEC_ENTRY 0xffe1b008 - -/* Define next boot image name and offset */ -#define PLAT_NS_IMAGE_OFFSET 0x50000 -#define PLAT_HANDOFF_OFFSET 0xFFE3F000 - -/******************************************************************************* - * Platform binary types for linking - ******************************************************************************/ -#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" -#define PLATFORM_LINKER_ARCH aarch64 - -/* Stratix 10 supports up to 124GB RAM */ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) - - -/******************************************************************************* - * Generic platform constants - ******************************************************************************/ -#define PLAT_PRIMARY_CPU 0 -#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 - -/* Size of cacheable stacks */ -#define PLATFORM_STACK_SIZE 0x2000 - -/* PSCI related constant */ -#define PLAT_NUM_POWER_DOMAINS 5 -#define PLAT_MAX_PWR_LVL 1 -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 -#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ - PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 - -/* Interrupt related constant */ - -#define INTEL_S10_IRQ_SEC_PHY_TIMER 29 - -#define INTEL_S10_IRQ_SEC_SGI_0 8 -#define INTEL_S10_IRQ_SEC_SGI_1 9 -#define INTEL_S10_IRQ_SEC_SGI_2 10 -#define INTEL_S10_IRQ_SEC_SGI_3 11 -#define INTEL_S10_IRQ_SEC_SGI_4 12 -#define INTEL_S10_IRQ_SEC_SGI_5 13 -#define INTEL_S10_IRQ_SEC_SGI_6 14 -#define INTEL_S10_IRQ_SEC_SGI_7 15 - -#define TSP_IRQ_SEC_PHY_TIMER INTEL_S10_IRQ_SEC_PHY_TIMER -#define TSP_SEC_MEM_BASE BL32_BASE -#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) -/******************************************************************************* - * Platform memory map related constants - ******************************************************************************/ -#define DRAM_BASE (0x0) -#define DRAM_SIZE (0x80000000) - -#define OCRAM_BASE (0xFFE00000) -#define OCRAM_SIZE (0x00040000) - -#define MEM64_BASE (0x0100000000) -#define MEM64_SIZE (0x1F00000000) - -#define DEVICE1_BASE (0x80000000) -#define DEVICE1_SIZE (0x60000000) - -#define DEVICE2_BASE (0xF7000000) -#define DEVICE2_SIZE (0x08E00000) - -#define DEVICE3_BASE (0xFFFC0000) -#define DEVICE3_SIZE (0x00008000) - -#define DEVICE4_BASE (0x2000000000) -#define DEVICE4_SIZE (0x0100000000) - -/******************************************************************************* - * BL31 specific defines. - ******************************************************************************/ -/* - * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if - * present). BL31_BASE is calculated using the current BL3-1 debug size plus a - * little space for growth. - */ - - -#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" - -#define BL1_RO_BASE (0xffe00000) -#define BL1_RO_LIMIT (0xffe0f000) -#define BL1_RW_BASE (0xffe10000) -#define BL1_RW_LIMIT (0xffe1ffff) -#define BL1_RW_SIZE (0x14000) - -#define BL2_BASE (0xffe00000) -#define BL2_LIMIT (0xffe1b000) - -#define BL31_BASE (0xffe1c000) -#define BL31_LIMIT (0xffe3bfff) - -/******************************************************************************* - * Platform specific page table and MMU setup constants - ******************************************************************************/ -#define MAX_XLAT_TABLES 8 -#define MAX_MMAP_REGIONS 16 - -/******************************************************************************* - * Declarations and constants to access the mailboxes safely. Each mailbox is - * aligned on the biggest cache line size in the platform. This is known only - * to the platform as it might have a combination of integrated and external - * caches. Such alignment ensures that two maiboxes do not sit on the same cache - * line at any cache level. They could belong to different cpus/clusters & - * get written while being protected by different locks causing corruption of - * a valid mailbox address. - ******************************************************************************/ -#define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) - -#define PLAT_GIC_BASE (0xFFFC0000) -#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) -#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) -#define PLAT_GICR_BASE 0 - -/******************************************************************************* - * UART related constants - ******************************************************************************/ -#define PLAT_UART0_BASE (0xFFC02000) -#define PLAT_UART1_BASE (0xFFC02100) - -#define CRASH_CONSOLE_BASE PLAT_UART0_BASE - -#define PLAT_BAUDRATE (115200) -#define PLAT_UART_CLOCK (100000000) - -/******************************************************************************* - * System counter frequency related constants - ******************************************************************************/ -#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) -#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400) - -#define PLAT_INTEL_S10_GICD_BASE PLAT_GICD_BASE -#define PLAT_INTEL_S10_GICC_BASE PLAT_GICC_BASE - -/* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define PLAT_INTEL_S10_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE) - -#define PLAT_INTEL_S10_G0_IRQ_PROPS(grp) - -#define MAX_IO_HANDLES 4 -#define MAX_IO_DEVICES 4 -#define MAX_IO_BLOCK_DEVICES 2 - - -#endif /* __PLATFORM_DEF_H__ */ - diff --git a/plat/intel/soc/stratix10/include/s10_clock_manager.h b/plat/intel/soc/stratix10/include/s10_clock_manager.h index c800b9cf7..acc700a07 100644 --- a/plat/intel/soc/stratix10/include/s10_clock_manager.h +++ b/plat/intel/soc/stratix10/include/s10_clock_manager.h @@ -7,7 +7,7 @@ #ifndef __CLOCKMANAGER_H__ #define __CLOCKMANAGER_H__ -#include "s10_handoff.h" +#include "socfpga_handoff.h" #define ALT_CLKMGR 0xffd10000 diff --git a/plat/intel/soc/stratix10/include/s10_handoff.h b/plat/intel/soc/stratix10/include/s10_handoff.h deleted file mode 100644 index 1cc8d09d2..000000000 --- a/plat/intel/soc/stratix10/include/s10_handoff.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HANDOFF_H_ -#define _HANDOFF_H_ - -#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */ -#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */ -#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */ -#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */ -#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */ -#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ -#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ - -typedef struct handoff_t { - /* header */ - uint32_t header_magic; - uint32_t header_device; - uint32_t _pad_0x08_0x10[2]; - - /* pinmux configuration - select */ - uint32_t pinmux_sel_magic; - uint32_t pinmux_sel_length; - uint32_t _pad_0x18_0x20[2]; - uint32_t pinmux_sel_array[96]; /* offset, value */ - - /* pinmux configuration - io control */ - uint32_t pinmux_io_magic; - uint32_t pinmux_io_length; - uint32_t _pad_0x1a8_0x1b0[2]; - uint32_t pinmux_io_array[96]; /* offset, value */ - - /* pinmux configuration - use fpga switch */ - uint32_t pinmux_fpga_magic; - uint32_t pinmux_fpga_length; - uint32_t _pad_0x338_0x340[2]; - uint32_t pinmux_fpga_array[42]; /* offset, value */ - uint32_t _pad_0x3e8_0x3f0[2]; - - /* pinmux configuration - io delay */ - uint32_t pinmux_delay_magic; - uint32_t pinmux_delay_length; - uint32_t _pad_0x3f8_0x400[2]; - uint32_t pinmux_iodelay_array[96]; /* offset, value */ - - /* clock configuration */ - uint32_t clock_magic; - uint32_t clock_length; - uint32_t _pad_0x588_0x590[2]; - uint32_t main_pll_mpuclk; - uint32_t main_pll_nocclk; - uint32_t main_pll_cntr2clk; - uint32_t main_pll_cntr3clk; - uint32_t main_pll_cntr4clk; - uint32_t main_pll_cntr5clk; - uint32_t main_pll_cntr6clk; - uint32_t main_pll_cntr7clk; - uint32_t main_pll_cntr8clk; - uint32_t main_pll_cntr9clk; - uint32_t main_pll_nocdiv; - uint32_t main_pll_pllglob; - uint32_t main_pll_fdbck; - uint32_t main_pll_pllc0; - uint32_t main_pll_pllc1; - uint32_t _pad_0x5cc_0x5d0[1]; - uint32_t per_pll_cntr2clk; - uint32_t per_pll_cntr3clk; - uint32_t per_pll_cntr4clk; - uint32_t per_pll_cntr5clk; - uint32_t per_pll_cntr6clk; - uint32_t per_pll_cntr7clk; - uint32_t per_pll_cntr8clk; - uint32_t per_pll_cntr9clk; - uint32_t per_pll_emacctl; - uint32_t per_pll_gpiodiv; - uint32_t per_pll_pllglob; - uint32_t per_pll_fdbck; - uint32_t per_pll_pllc0; - uint32_t per_pll_pllc1; - uint32_t hps_osc_clk_h; - uint32_t fpga_clk_hz; - - /* misc configuration */ - uint32_t misc_magic; - uint32_t misc_length; - uint32_t _pad_0x618_0x620[2]; - uint32_t boot_source; -} handoff; - -int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); -int s10_get_handoff(handoff *hoff_ptr); - -#endif - - diff --git a/plat/intel/soc/stratix10/include/s10_pinmux.h b/plat/intel/soc/stratix10/include/s10_pinmux.h index a1ba29ef9..82367d74f 100644 --- a/plat/intel/soc/stratix10/include/s10_pinmux.h +++ b/plat/intel/soc/stratix10/include/s10_pinmux.h @@ -12,7 +12,7 @@ #define S10_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300 #define S10_PINMUX_IO0_DELAY 0xffd13400 -#include "s10_handoff.h" +#include "socfpga_handoff.h" void config_pinmux(handoff *handoff); diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h new file mode 100644 index 000000000..ab723f79d --- /dev/null +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_SOCFPGA_DEF_H +#define PLAT_SOCFPGA_DEF_H + +#include + +/* Platform Setting */ +#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 + +/* Register Mapping */ +#define SOCFPGA_MMC_REG_BASE 0xff808000 + +#define SOCFPGA_RSTMGR_OFST 0xffd11000 +#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020 + +#endif /* PLATSOCFPGA_DEF_H */ + diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 34674b0cd..b7c70ff87 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -37,7 +37,7 @@ BL2_SOURCES += \ plat/intel/soc/stratix10/plat_storage.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/stratix10/soc/s10_reset_manager.c \ - plat/intel/soc/stratix10/soc/s10_handoff.c \ + plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/stratix10/soc/s10_clock_manager.c \ plat/intel/soc/stratix10/soc/s10_pinmux.c \ plat/intel/soc/stratix10/soc/s10_memory_controller.c \ @@ -63,7 +63,6 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ plat/intel/soc/stratix10/soc/s10_reset_manager.c\ plat/intel/soc/stratix10/soc/s10_pinmux.c \ plat/intel/soc/stratix10/soc/s10_clock_manager.c\ - plat/intel/soc/stratix10/soc/s10_handoff.c \ plat/intel/soc/stratix10/soc/s10_mailbox.c PROGRAMMABLE_RESET_ADDRESS := 0 diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c index ed65c2ba8..e4ff7acf2 100644 --- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c @@ -12,8 +12,8 @@ #include #include "s10_clock_manager.h" -#include "s10_handoff.h" #include "s10_system_manager.h" +#include "socfpga_handoff.h" void wait_pll_lock(void) diff --git a/plat/intel/soc/stratix10/soc/s10_handoff.c b/plat/intel/soc/stratix10/soc/s10_handoff.c deleted file mode 100644 index 1a4d5c326..000000000 --- a/plat/intel/soc/stratix10/soc/s10_handoff.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "s10_handoff.h" - -#define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) | \ - (((x) & 0x0000FF00) << 8) | ((x) << 24)) - -int s10_get_handoff(handoff *reverse_hoff_ptr) -{ - int i; - uint32_t *buffer; - handoff *handoff_ptr = (handoff *) PLAT_HANDOFF_OFFSET; - - memcpy(reverse_hoff_ptr, handoff_ptr, sizeof(handoff)); - buffer = (uint32_t *)reverse_hoff_ptr; - - /* convert big indian to little indian */ - for (i = 0; i < sizeof(handoff) / 4; i++) - buffer[i] = SWAP_UINT32(buffer[i]); - - if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER) - return -1; - if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL) - return -1; - if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR) - return -1; - if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA) - return -1; - if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY) - return -1; - - return 0; -} -- cgit v1.2.3 From e9b5e360de9e43e6dd4d17bc53622f5a5606ff8d Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Wed, 23 Oct 2019 17:02:55 +0800 Subject: intel: Refactor common platform code [2/5] Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: Hadi Asyrafi Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5 --- plat/intel/soc/agilex/bl2_plat_setup.c | 3 +- plat/intel/soc/agilex/include/agilex_private.h | 34 ---- plat/intel/soc/agilex/platform.mk | 2 +- plat/intel/soc/agilex/socfpga_storage.c | 193 -------------------- plat/intel/soc/common/aarch64/platform_common.c | 3 +- plat/intel/soc/common/include/socfpga_private.h | 32 +++- plat/intel/soc/common/socfpga_storage.c | 193 ++++++++++++++++++++ plat/intel/soc/stratix10/bl2_plat_setup.c | 7 +- plat/intel/soc/stratix10/bl31_plat_setup.c | 2 +- .../soc/stratix10/include/stratix10_private.h | 34 ---- plat/intel/soc/stratix10/plat_storage.c | 195 --------------------- plat/intel/soc/stratix10/platform.mk | 2 +- 12 files changed, 231 insertions(+), 469 deletions(-) delete mode 100644 plat/intel/soc/agilex/include/agilex_private.h delete mode 100644 plat/intel/soc/agilex/socfpga_storage.c create mode 100644 plat/intel/soc/common/socfpga_storage.c delete mode 100644 plat/intel/soc/stratix10/include/stratix10_private.h delete mode 100644 plat/intel/soc/stratix10/plat_storage.c diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index fa9a6a54e..d65049d1b 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -15,19 +15,18 @@ #include #include #include -#include #include "agilex_clock_manager.h" #include "agilex_mailbox.h" #include "agilex_memory_controller.h" #include "agilex_pinmux.h" -#include "agilex_private.h" #include "agilex_reset_manager.h" #include "agilex_system_manager.h" #include "ccu/ncore_ccu.h" #include "qspi/cadence_qspi.h" #include "socfpga_handoff.h" +#include "socfpga_private.h" #include "wdt/watchdog.h" diff --git a/plat/intel/soc/agilex/include/agilex_private.h b/plat/intel/soc/agilex/include/agilex_private.h deleted file mode 100644 index fc0e9fddf..000000000 --- a/plat/intel/soc/agilex/include/agilex_private.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef AGX_PRIVATE_H -#define AGX_PRIVATE_H - -#define AGX_MMC_REG_BASE 0xff808000 - -#define EMMC_DESC_SIZE (1<<20) -#define EMMC_INIT_PARAMS(base, clk) \ - { .bus_width = MMC_BUS_WIDTH_4, \ - .clk_rate = (clk), \ - .desc_base = (base), \ - .desc_size = EMMC_DESC_SIZE, \ - .flags = 0, \ - .reg_base = AGX_MMC_REG_BASE \ - } - -typedef enum { - BOOT_SOURCE_FPGA = 0, - BOOT_SOURCE_SDMMC, - BOOT_SOURCE_NAND, - BOOT_SOURCE_RSVD, - BOOT_SOURCE_QSPI -} boot_source_type; - -void enable_nonsecure_access(void); -void socfpga_io_setup(int boot_source); - -#endif diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index f21e84268..b523d9ccf 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -37,7 +37,7 @@ BL2_SOURCES += \ drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ lib/cpus/aarch64/cortex_a53.S \ plat/intel/soc/agilex/bl2_plat_setup.c \ - plat/intel/soc/agilex/socfpga_storage.c \ + plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/agilex/soc/agilex_reset_manager.c \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ diff --git a/plat/intel/soc/agilex/socfpga_storage.c b/plat/intel/soc/agilex/socfpga_storage.c deleted file mode 100644 index 76dd81f75..000000000 --- a/plat/intel/soc/agilex/socfpga_storage.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "agilex_private.h" - -#define PLAT_FIP_BASE (0) -#define PLAT_FIP_MAX_SIZE (0x1000000) -#define PLAT_MMC_DATA_BASE (0xffe3c000) -#define PLAT_MMC_DATA_SIZE (0x2000) -#define PLAT_QSPI_DATA_BASE (0x3C00000) -#define PLAT_QSPI_DATA_SIZE (0x1000000) - - -static const io_dev_connector_t *fip_dev_con; -static const io_dev_connector_t *boot_dev_con; - -static uintptr_t fip_dev_handle; -static uintptr_t boot_dev_handle; - -static const io_uuid_spec_t bl2_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, -}; - -static const io_uuid_spec_t bl31_uuid_spec = { - .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, -}; - -static const io_uuid_spec_t bl33_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, -}; - -uintptr_t a2_lba_offset; -const char a2[] = {0xa2, 0x0}; - -static const io_block_spec_t gpt_block_spec = { - .offset = 0, - .length = MMC_BLOCK_SIZE -}; - -static int check_fip(const uintptr_t spec); -static int check_dev(const uintptr_t spec); - -static io_block_dev_spec_t boot_dev_spec; -static int (*register_io_dev)(const io_dev_connector_t **); - -static io_block_spec_t fip_spec = { - .offset = PLAT_FIP_BASE, - .length = PLAT_FIP_MAX_SIZE, -}; - -struct plat_io_policy { - uintptr_t *dev_handle; - uintptr_t image_spec; - int (*check)(const uintptr_t spec); -}; - -static const struct plat_io_policy policies[] = { - [FIP_IMAGE_ID] = { - &boot_dev_handle, - (uintptr_t)&fip_spec, - check_dev - }, - [BL2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl2_uuid_spec, - check_fip - }, - [BL31_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl31_uuid_spec, - check_fip - }, - [BL33_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t) &bl33_uuid_spec, - check_fip - }, - [GPT_IMAGE_ID] = { - &boot_dev_handle, - (uintptr_t) &gpt_block_spec, - check_dev - }, -}; - -static int check_dev(const uintptr_t spec) -{ - int result; - uintptr_t local_handle; - - result = io_dev_init(boot_dev_handle, (uintptr_t)NULL); - if (result == 0) { - result = io_open(boot_dev_handle, spec, &local_handle); - if (result == 0) - io_close(local_handle); - } - return result; -} - -static int check_fip(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); - if (result == 0) { - result = io_open(fip_dev_handle, spec, &local_image_handle); - if (result == 0) - io_close(local_image_handle); - } - return result; -} - -void socfpga_io_setup(int boot_source) -{ - int result; - - switch (boot_source) { - case BOOT_SOURCE_SDMMC: - register_io_dev = ®ister_io_dev_block; - boot_dev_spec.buffer.offset = PLAT_MMC_DATA_BASE; - boot_dev_spec.buffer.length = MMC_BLOCK_SIZE; - boot_dev_spec.ops.read = mmc_read_blocks; - boot_dev_spec.ops.write = mmc_write_blocks; - boot_dev_spec.block_size = MMC_BLOCK_SIZE; - break; - - case BOOT_SOURCE_QSPI: - register_io_dev = ®ister_io_dev_memmap; - fip_spec.offset = fip_spec.offset + PLAT_QSPI_DATA_BASE; - break; - - default: - ERROR("Unsupported boot source\n"); - panic(); - break; - } - - result = (*register_io_dev)(&boot_dev_con); - assert(result == 0); - - result = register_io_dev_fip(&fip_dev_con); - assert(result == 0); - - result = io_dev_open(boot_dev_con, (uintptr_t)&boot_dev_spec, - &boot_dev_handle); - assert(result == 0); - - result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle); - assert(result == 0); - - if (boot_source == BOOT_SOURCE_SDMMC) { - partition_init(GPT_IMAGE_ID); - fip_spec.offset = get_partition_entry(a2)->start; - } - - (void)result; -} - -int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int result; - const struct plat_io_policy *policy; - - assert(image_id < ARRAY_SIZE(policies)); - - policy = &policies[image_id]; - result = policy->check(policy->image_spec); - assert(result == 0); - - *image_spec = policy->image_spec; - *dev_handle = *(policy->dev_handle); - - return result; -} diff --git a/plat/intel/soc/common/aarch64/platform_common.c b/plat/intel/soc/common/aarch64/platform_common.c index 6d3d817d6..b79a63c86 100644 --- a/plat/intel/soc/common/aarch64/platform_common.c +++ b/plat/intel/soc/common/aarch64/platform_common.c @@ -8,7 +8,8 @@ #include #include #include -#include + +#include "socfpga_private.h" unsigned int plat_get_syscnt_freq2(void) diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h index 6ab14090f..375484443 100644 --- a/plat/intel/soc/common/include/socfpga_private.h +++ b/plat/intel/soc/common/include/socfpga_private.h @@ -4,12 +4,38 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef PLATFORM_PRIVATE_H -#define PLATFORM_PRIVATE_H +#ifndef SOCFPGA_PRIVATE_H +#define SOCFPGA_PRIVATE_H + +#include "socfpga_plat_def.h" + +#define EMMC_DESC_SIZE (1<<20) + +#define EMMC_INIT_PARAMS(base, clk) \ + { .bus_width = MMC_BUS_WIDTH_4, \ + .clk_rate = (clk), \ + .desc_base = (base), \ + .desc_size = EMMC_DESC_SIZE, \ + .flags = 0, \ + .reg_base = SOCFPGA_MMC_REG_BASE \ + } + +typedef enum { + BOOT_SOURCE_FPGA = 0, + BOOT_SOURCE_SDMMC, + BOOT_SOURCE_NAND, + BOOT_SOURCE_RSVD, + BOOT_SOURCE_QSPI +} boot_source_type; /******************************************************************************* * Function and variable prototypes ******************************************************************************/ + +void enable_nonsecure_access(void); + +void socfpga_io_setup(int boot_source); + void socfgpa_configure_mmu_el3(unsigned long total_base, unsigned long total_size, unsigned long ro_start, @@ -36,4 +62,4 @@ uint32_t socfpga_get_spsr_for_bl33_entry(void); unsigned long socfpga_get_ns_image_entrypoint(void); -#endif /* PLATFORM_PRIVATE_H */ +#endif /* SOCFPGA_PRIVATE_H */ diff --git a/plat/intel/soc/common/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c new file mode 100644 index 000000000..a2f2c184c --- /dev/null +++ b/plat/intel/soc/common/socfpga_storage.c @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "socfpga_private.h" + +#define PLAT_FIP_BASE (0) +#define PLAT_FIP_MAX_SIZE (0x1000000) +#define PLAT_MMC_DATA_BASE (0xffe3c000) +#define PLAT_MMC_DATA_SIZE (0x2000) +#define PLAT_QSPI_DATA_BASE (0x3C00000) +#define PLAT_QSPI_DATA_SIZE (0x1000000) + + +static const io_dev_connector_t *fip_dev_con; +static const io_dev_connector_t *boot_dev_con; + +static uintptr_t fip_dev_handle; +static uintptr_t boot_dev_handle; + +static const io_uuid_spec_t bl2_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, +}; + +static const io_uuid_spec_t bl31_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, +}; + +static const io_uuid_spec_t bl33_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +uintptr_t a2_lba_offset; +const char a2[] = {0xa2, 0x0}; + +static const io_block_spec_t gpt_block_spec = { + .offset = 0, + .length = MMC_BLOCK_SIZE +}; + +static int check_fip(const uintptr_t spec); +static int check_dev(const uintptr_t spec); + +static io_block_dev_spec_t boot_dev_spec; +static int (*register_io_dev)(const io_dev_connector_t **); + +static io_block_spec_t fip_spec = { + .offset = PLAT_FIP_BASE, + .length = PLAT_FIP_MAX_SIZE, +}; + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +static const struct plat_io_policy policies[] = { + [FIP_IMAGE_ID] = { + &boot_dev_handle, + (uintptr_t)&fip_spec, + check_dev + }, + [BL2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl2_uuid_spec, + check_fip + }, + [BL31_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_uuid_spec, + check_fip + }, + [BL33_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t) &bl33_uuid_spec, + check_fip + }, + [GPT_IMAGE_ID] = { + &boot_dev_handle, + (uintptr_t) &gpt_block_spec, + check_dev + }, +}; + +static int check_dev(const uintptr_t spec) +{ + int result; + uintptr_t local_handle; + + result = io_dev_init(boot_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(boot_dev_handle, spec, &local_handle); + if (result == 0) + io_close(local_handle); + } + return result; +} + +static int check_fip(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); + if (result == 0) { + result = io_open(fip_dev_handle, spec, &local_image_handle); + if (result == 0) + io_close(local_image_handle); + } + return result; +} + +void socfpga_io_setup(int boot_source) +{ + int result; + + switch (boot_source) { + case BOOT_SOURCE_SDMMC: + register_io_dev = ®ister_io_dev_block; + boot_dev_spec.buffer.offset = PLAT_MMC_DATA_BASE; + boot_dev_spec.buffer.length = MMC_BLOCK_SIZE; + boot_dev_spec.ops.read = mmc_read_blocks; + boot_dev_spec.ops.write = mmc_write_blocks; + boot_dev_spec.block_size = MMC_BLOCK_SIZE; + break; + + case BOOT_SOURCE_QSPI: + register_io_dev = ®ister_io_dev_memmap; + fip_spec.offset = fip_spec.offset + PLAT_QSPI_DATA_BASE; + break; + + default: + ERROR("Unsupported boot source\n"); + panic(); + break; + } + + result = (*register_io_dev)(&boot_dev_con); + assert(result == 0); + + result = register_io_dev_fip(&fip_dev_con); + assert(result == 0); + + result = io_dev_open(boot_dev_con, (uintptr_t)&boot_dev_spec, + &boot_dev_handle); + assert(result == 0); + + result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle); + assert(result == 0); + + if (boot_source == BOOT_SOURCE_SDMMC) { + partition_init(GPT_IMAGE_ID); + fip_spec.offset = get_partition_entry(a2)->start; + } + + (void)result; +} + +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + assert(result == 0); + + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + + return result; +} diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index cc6b4a7c2..1cb9c250c 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -28,10 +27,10 @@ #include "s10_reset_manager.h" #include "s10_clock_manager.h" #include "s10_pinmux.h" -#include "stratix10_private.h" #include "include/s10_mailbox.h" #include "qspi/cadence_qspi.h" #include "socfpga_handoff.h" +#include "socfpga_private.h" #include "wdt/watchdog.h" @@ -115,7 +114,7 @@ void bl2_el3_plat_arch_setup(void) switch (boot_source) { case BOOT_SOURCE_SDMMC: dw_mmc_init(¶ms, &info); - stratix10_io_setup(boot_source); + socfpga_io_setup(boot_source); break; case BOOT_SOURCE_QSPI: @@ -124,7 +123,7 @@ void bl2_el3_plat_arch_setup(void) cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); - stratix10_io_setup(boot_source); + socfpga_io_setup(boot_source); break; default: diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 46ef7cbf0..0a7f21873 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -22,7 +22,7 @@ #include #include -#include "stratix10_private.h" +#include "socfpga_private.h" #include "s10_reset_manager.h" #include "s10_memory_controller.h" #include "s10_pinmux.h" diff --git a/plat/intel/soc/stratix10/include/stratix10_private.h b/plat/intel/soc/stratix10/include/stratix10_private.h deleted file mode 100644 index 85aff3aa7..000000000 --- a/plat/intel/soc/stratix10/include/stratix10_private.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __S10_PRIVATE_H__ -#define __S10_PRIVATE_H__ - -#define S10_MMC_REG_BASE 0xff808000 - -#define EMMC_DESC_SIZE (1<<20) -#define EMMC_INIT_PARAMS(base, clk) \ - { .bus_width = MMC_BUS_WIDTH_4, \ - .clk_rate = (clk), \ - .desc_base = (base), \ - .desc_size = EMMC_DESC_SIZE, \ - .flags = 0, \ - .reg_base = S10_MMC_REG_BASE, \ - \ - } - -typedef enum { - BOOT_SOURCE_FPGA = 0, - BOOT_SOURCE_SDMMC, - BOOT_SOURCE_NAND, - BOOT_SOURCE_RSVD, - BOOT_SOURCE_QSPI, -} boot_source_type; - -void enable_nonsecure_access(void); -void stratix10_io_setup(int boot_source); - -#endif diff --git a/plat/intel/soc/stratix10/plat_storage.c b/plat/intel/soc/stratix10/plat_storage.c deleted file mode 100644 index 0b8b9cd2a..000000000 --- a/plat/intel/soc/stratix10/plat_storage.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "platform_def.h" -#include "stratix10_private.h" - -#define STRATIX10_FIP_BASE (0) -#define STRATIX10_FIP_MAX_SIZE (0x1000000) -#define STRATIX10_MMC_DATA_BASE (0xffe3c000) -#define STRATIX10_MMC_DATA_SIZE (0x2000) -#define STRATIX10_QSPI_DATA_BASE (0x3C00000) -#define STRATIX10_QSPI_DATA_SIZE (0x1000000) - - -static const io_dev_connector_t *fip_dev_con; -static const io_dev_connector_t *boot_dev_con; - -static uintptr_t fip_dev_handle; -static uintptr_t boot_dev_handle; - -static const io_uuid_spec_t bl2_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, -}; - -static const io_uuid_spec_t bl31_uuid_spec = { - .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, -}; - -static const io_uuid_spec_t bl33_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, -}; - -uintptr_t a2_lba_offset; -const char a2[] = {0xa2, 0x0}; - -static const io_block_spec_t gpt_block_spec = { - .offset = 0, - .length = MMC_BLOCK_SIZE -}; - -static int check_fip(const uintptr_t spec); -static int check_dev(const uintptr_t spec); - -static io_block_dev_spec_t boot_dev_spec; -static int (*register_io_dev)(const io_dev_connector_t **); - -static io_block_spec_t fip_spec = { - .offset = STRATIX10_FIP_BASE, - .length = STRATIX10_FIP_MAX_SIZE, -}; - -struct plat_io_policy { - uintptr_t *dev_handle; - uintptr_t image_spec; - int (*check)(const uintptr_t spec); -}; - -static const struct plat_io_policy policies[] = { - [FIP_IMAGE_ID] = { - &boot_dev_handle, - (uintptr_t)&fip_spec, - check_dev - }, - [BL2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl2_uuid_spec, - check_fip - }, - [BL31_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl31_uuid_spec, - check_fip - }, - [BL33_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t) &bl33_uuid_spec, - check_fip - }, - [GPT_IMAGE_ID] = { - &boot_dev_handle, - (uintptr_t) &gpt_block_spec, - check_dev - }, -}; - -static int check_dev(const uintptr_t spec) -{ - int result; - uintptr_t local_handle; - - result = io_dev_init(boot_dev_handle, (uintptr_t)NULL); - if (result == 0) { - result = io_open(boot_dev_handle, spec, &local_handle); - if (result == 0) - io_close(local_handle); - } - return result; -} - -static int check_fip(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); - if (result == 0) { - result = io_open(fip_dev_handle, spec, &local_image_handle); - if (result == 0) - io_close(local_image_handle); - } - return result; -} - -void stratix10_io_setup(int boot_source) -{ - int result; - - switch (boot_source) { - case BOOT_SOURCE_SDMMC: - register_io_dev = ®ister_io_dev_block; - boot_dev_spec.buffer.offset = STRATIX10_MMC_DATA_BASE; - boot_dev_spec.buffer.length = MMC_BLOCK_SIZE; - boot_dev_spec.ops.read = mmc_read_blocks; - boot_dev_spec.ops.write = mmc_write_blocks; - boot_dev_spec.block_size = MMC_BLOCK_SIZE; - break; - - case BOOT_SOURCE_QSPI: - register_io_dev = ®ister_io_dev_memmap; - fip_spec.offset = fip_spec.offset + STRATIX10_QSPI_DATA_BASE; - break; - - default: - ERROR("Unsupported boot source\n"); - panic(); - break; - } - - result = (*register_io_dev)(&boot_dev_con); - assert(result == 0); - - result = register_io_dev_fip(&fip_dev_con); - assert(result == 0); - - result = io_dev_open(boot_dev_con, (uintptr_t)&boot_dev_spec, - &boot_dev_handle); - assert(result == 0); - - result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle); - assert(result == 0); - - if (boot_source == BOOT_SOURCE_SDMMC) { - partition_init(GPT_IMAGE_ID); - fip_spec.offset = get_partition_entry(a2)->start; - } - - (void)result; -} - -int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int result; - const struct plat_io_policy *policy; - - assert(image_id < ARRAY_SIZE(policies)); - - policy = &policies[image_id]; - result = policy->check(policy->image_spec); - assert(result == 0); - - *image_spec = policy->image_spec; - *dev_handle = *(policy->dev_handle); - - return result; -} diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index b7c70ff87..d1ff07761 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -34,7 +34,7 @@ BL2_SOURCES += \ drivers/gpio/gpio.c \ drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ plat/intel/soc/stratix10/bl2_plat_setup.c \ - plat/intel/soc/stratix10/plat_storage.c \ + plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/stratix10/soc/s10_reset_manager.c \ plat/intel/soc/common/soc/socfpga_handoff.c \ -- cgit v1.2.3 From d09adcbaf2c443ef7dde66fda5e9c568ff02e7a1 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Wed, 23 Oct 2019 18:34:14 +0800 Subject: intel: Refactor common platform code [3/5] Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: Hadi Asyrafi Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716 --- plat/intel/soc/agilex/bl2_plat_setup.c | 2 +- plat/intel/soc/agilex/include/agilex_mailbox.h | 127 ----------- plat/intel/soc/agilex/platform.mk | 4 +- plat/intel/soc/agilex/soc/agilex_mailbox.c | 280 ------------------------ plat/intel/soc/agilex/socfpga_psci.c | 2 +- plat/intel/soc/agilex/socfpga_sip_svc.c | 2 +- plat/intel/soc/common/include/socfpga_mailbox.h | 127 +++++++++++ plat/intel/soc/common/soc/socfpga_mailbox.c | 280 ++++++++++++++++++++++++ plat/intel/soc/stratix10/bl2_plat_setup.c | 2 +- plat/intel/soc/stratix10/bl31_plat_setup.c | 1 - plat/intel/soc/stratix10/include/s10_mailbox.h | 125 ----------- plat/intel/soc/stratix10/plat_psci.c | 2 +- plat/intel/soc/stratix10/plat_sip_svc.c | 2 +- plat/intel/soc/stratix10/platform.mk | 4 +- plat/intel/soc/stratix10/soc/s10_mailbox.c | 275 ----------------------- 15 files changed, 417 insertions(+), 818 deletions(-) delete mode 100644 plat/intel/soc/agilex/include/agilex_mailbox.h delete mode 100644 plat/intel/soc/agilex/soc/agilex_mailbox.c create mode 100644 plat/intel/soc/common/include/socfpga_mailbox.h create mode 100644 plat/intel/soc/common/soc/socfpga_mailbox.c delete mode 100644 plat/intel/soc/stratix10/include/s10_mailbox.h delete mode 100644 plat/intel/soc/stratix10/soc/s10_mailbox.c diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index d65049d1b..ece7b9c70 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -17,7 +17,6 @@ #include #include "agilex_clock_manager.h" -#include "agilex_mailbox.h" #include "agilex_memory_controller.h" #include "agilex_pinmux.h" #include "agilex_reset_manager.h" @@ -26,6 +25,7 @@ #include "ccu/ncore_ccu.h" #include "qspi/cadence_qspi.h" #include "socfpga_handoff.h" +#include "socfpga_mailbox.h" #include "socfpga_private.h" #include "wdt/watchdog.h" diff --git a/plat/intel/soc/agilex/include/agilex_mailbox.h b/plat/intel/soc/agilex/include/agilex_mailbox.h deleted file mode 100644 index cd8be2894..000000000 --- a/plat/intel/soc/agilex/include/agilex_mailbox.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef AGX_MBOX_H -#define AGX_MBOX_H - -#include - -#define MBOX_OFFSET 0xffa30000 - -#define MBOX_ATF_CLIENT_ID 0x1 -#define MBOX_JOB_ID 0x1 - -/* Mailbox interrupt flags and masks */ -#define MBOX_INT_FLAG_COE 0x1 -#define MBOX_INT_FLAG_RIE 0x2 -#define MBOX_INT_FLAG_UAE 0x100 -#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) -#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8))) - -/* Mailbox response and status */ -#define MBOX_RESP_BUFFER_SIZE 16 -#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff) -#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) -#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) -#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) -#define MBOX_STATUS_UA_MASK (1<<8) - -/* Mailbox command and response */ -#define MBOX_CMD_FREE_OFFSET 0x14 -#define MBOX_CMD_BUFFER_SIZE 32 -#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) -#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) -#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) -#define MBOX_INDIRECT (1 << 11) -#define MBOX_INSUFFICIENT_BUFFER -2 -#define MBOX_CIN 0x00 -#define MBOX_ROUT 0x04 -#define MBOX_URG 0x08 -#define MBOX_INT 0x0C -#define MBOX_COUT 0x20 -#define MBOX_RIN 0x24 -#define MBOX_STATUS 0x2C -#define MBOX_CMD_BUFFER 0x40 -#define MBOX_RESP_BUFFER 0xC0 - -#define MBOX_RESP_BUFFER_SIZE 16 -#define MBOX_RESP_OK 0 -#define MBOX_RESP_INVALID_CMD 1 -#define MBOX_RESP_UNKNOWN_BR 2 -#define MBOX_RESP_UNKNOWN 3 -#define MBOX_RESP_NOT_CONFIGURED 256 - -/* Mailbox SDM doorbell */ -#define MBOX_DOORBELL_TO_SDM 0x400 -#define MBOX_DOORBELL_FROM_SDM 0x480 - -/* Mailbox QSPI commands */ -#define MBOX_CMD_RESTART 2 -#define MBOX_CMD_QSPI_OPEN 50 -#define MBOX_CMD_QSPI_CLOSE 51 -#define MBOX_CMD_QSPI_DIRECT 59 -#define MBOX_CMD_GET_IDCODE 16 -#define MBOX_CMD_QSPI_SET_CS 52 - -/* Mailbox REBOOT commands */ -#define MBOX_CMD_REBOOT_HPS 71 - -/* Generic error handling */ -#define MBOX_TIMEOUT -2047 -#define MBOX_NO_RESPONSE -2 -#define MBOX_WRONG_ID -3 - -/* Mailbox status */ -#define RECONFIG_STATUS_STATE 0 -#define RECONFIG_STATUS_PIN_STATUS 2 -#define RECONFIG_STATUS_SOFTFUNC_STATUS 3 -#define PIN_STATUS_NSTATUS (U(1) << 31) -#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) -#define SOFTFUNC_STATUS_INIT_DONE (1 << 1) -#define SOFTFUNC_STATUS_CONF_DONE (1 << 0) -#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 - -/* SMC function IDs for SiP Service queries */ -#define SIP_SVC_CALL_COUNT 0x8200ff00 -#define SIP_SVC_UID 0x8200ff01 -#define SIP_SVC_VERSION 0x8200ff03 - -/* SiP Service Calls version numbers */ -#define SIP_SVC_VERSION_MAJOR 0 -#define SIP_SVC_VERSION_MINOR 1 - -/* Mailbox reconfiguration commands */ -#define MBOX_RECONFIG 6 -#define MBOX_RECONFIG_DATA 8 -#define MBOX_RECONFIG_STATUS 9 - -/* Sip get memory */ -#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 -#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 -#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 -#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 -#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 -#define INTEL_SIP_SMC_STATUS_OK 0 -#define INTEL_SIP_SMC_STATUS_ERROR 0x4 -#define INTEL_SIP_SMC_STATUS_BUSY 0x1 -#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 -#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x1000 -#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216 - -void mailbox_set_int(int interrupt_input); -int mailbox_init(void); -void mailbox_set_qspi_close(void); -void mailbox_set_qspi_open(void); -void mailbox_set_qspi_direct(void); -int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response); -void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent); -int mailbox_read_response(int job_id, uint32_t *response); -int mailbox_get_qspi_clock(void); -void mailbox_reset_cold(void); - -#endif diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index b523d9ccf..bf8fc36b2 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -47,7 +47,7 @@ BL2_SOURCES += \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/agilex/soc/agilex_system_manager.c \ - plat/intel/soc/agilex/soc/agilex_mailbox.c \ + plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c \ plat/intel/soc/common/drivers/ccu/ncore_ccu.c @@ -65,7 +65,7 @@ BL31_SOURCES += \ plat/intel/soc/agilex/soc/agilex_reset_manager.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ - plat/intel/soc/agilex/soc/agilex_mailbox.c + plat/intel/soc/common/soc/socfpga_mailbox.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/agilex/soc/agilex_mailbox.c b/plat/intel/soc/agilex/soc/agilex_mailbox.c deleted file mode 100644 index ebfea6148..000000000 --- a/plat/intel/soc/agilex/soc/agilex_mailbox.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include "agilex_mailbox.h" - -static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, - int len) -{ - uint32_t cmd_free_offset; - int i; - - cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN); - - if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) { - INFO("Insufficient buffer in mailbox\n"); - return MBOX_INSUFFICIENT_BUFFER; - } - - - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + (cmd_free_offset++ * 4), - header_cmd); - - - for (i = 0; i < len; i++) { - cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + - (cmd_free_offset++ * 4), args[i]); - } - - cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_CIN, cmd_free_offset); - - return 0; -} - -int mailbox_read_response(int job_id, uint32_t *response) -{ - int rin = 0; - int rout = 0; - int response_length = 0; - int resp = 0; - int total_resp_len = 0; - int timeout = 100000; - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - - while (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { - if (timeout-- < 0) - return MBOX_NO_RESPONSE; - } - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - - rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); - rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); - - while (rout != rin) { - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4)); - - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - - if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || - MBOX_RESP_JOB_ID(resp) != job_id) { - return MBOX_WRONG_ID; - } - - if (MBOX_RESP_ERR(resp) > 0) { - INFO("Error in response: %x\n", resp); - return -resp; - } - response_length = MBOX_RESP_LEN(resp); - - while (response_length) { - - response_length--; - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + - (rout)*4); - if (response) { - *(response + total_resp_len) = resp; - total_resp_len++; - } - rout++; - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - } - return total_resp_len; - } - - return MBOX_NO_RESPONSE; -} - - -int mailbox_poll_response(int job_id, int urgent, uint32_t *response) -{ - int timeout = 80000; - int rin = 0; - int rout = 0; - int response_length = 0; - int resp = 0; - int total_resp_len = 0; - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - - while (1) { - while (timeout > 0 && - mmio_read_32(MBOX_OFFSET + - MBOX_DOORBELL_FROM_SDM) != 1) { - timeout--; - } - - if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { - INFO("Timed out waiting for SDM"); - return MBOX_TIMEOUT; - } - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - - if (urgent & 1) { - if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & - MBOX_STATUS_UA_MASK) ^ - (urgent & MBOX_STATUS_UA_MASK)) { - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - return 0; - } - - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - INFO("Error: Mailbox did not get UA"); - return -1; - } - - rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); - rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); - - while (rout != rin) { - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4)); - - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - - if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || - MBOX_RESP_JOB_ID(resp) != job_id) - continue; - - if (MBOX_RESP_ERR(resp) > 0) { - INFO("Error in response: %x\n", resp); - return -MBOX_RESP_ERR(resp); - } - response_length = MBOX_RESP_LEN(resp); - - while (response_length) { - - response_length--; - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + - (rout)*4); - if (response) { - *(response + total_resp_len) = resp; - total_resp_len++; - } - rout++; - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - } - return total_resp_len; - } - } -} - -void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent) -{ - if (urgent) - mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); - - fill_mailbox_circular_buffer(MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | - MBOX_JOB_ID_CMD(job_id) | - MBOX_CMD_LEN_CMD(len) | - MBOX_INDIRECT | - cmd, args, len); -} - -int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response) -{ - int status; - - if (urgent) { - urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & - MBOX_STATUS_UA_MASK; - mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd); - status = 0; - } else { - status = fill_mailbox_circular_buffer( - MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | - MBOX_JOB_ID_CMD(job_id) | - cmd, args, len); - } - - if (status) - return status; - - return mailbox_poll_response(job_id, urgent, response); -} - -void mailbox_set_int(int interrupt) -{ - - mmio_write_32(MBOX_OFFSET+MBOX_INT, MBOX_COE_BIT(interrupt) | - MBOX_UAE_BIT(interrupt)); -} - - -void mailbox_set_qspi_open(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, 0); -} - -void mailbox_set_qspi_direct(void) -{ - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); -} - -void mailbox_set_qspi_close(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, 0); -} - -int mailbox_get_qspi_clock(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); -} - -void mailbox_qspi_set_cs(int device_select) -{ - uint32_t cs_setting = device_select; - - /* QSPI device select settings at 31:28 */ - cs_setting = (cs_setting << 28); - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting, - 1, 0, 0); -} - -void mailbox_reset_cold(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, 0); -} - -int mailbox_init(void) -{ - int status = 0; - - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE | - MBOX_INT_FLAG_UAE); - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, 0); - - if (status) - return status; - - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - - return 0; -} - diff --git a/plat/intel/soc/agilex/socfpga_psci.c b/plat/intel/soc/agilex/socfpga_psci.c index 12060ef08..4b29159bd 100644 --- a/plat/intel/soc/agilex/socfpga_psci.c +++ b/plat/intel/soc/agilex/socfpga_psci.c @@ -12,7 +12,7 @@ #include #include "agilex_reset_manager.h" -#include "agilex_mailbox.h" +#include "socfpga_mailbox.h" #define AGX_RSTMGR_OFST 0xffd11000 #define AGX_RSTMGR_MPUMODRST_OFST 0x20 diff --git a/plat/intel/soc/agilex/socfpga_sip_svc.c b/plat/intel/soc/agilex/socfpga_sip_svc.c index 6a1c957c3..16e3c0393 100644 --- a/plat/intel/soc/agilex/socfpga_sip_svc.c +++ b/plat/intel/soc/agilex/socfpga_sip_svc.c @@ -9,7 +9,7 @@ #include #include -#include "agilex_mailbox.h" +#include "socfpga_mailbox.h" /* Number of SiP Calls implemented */ #define SIP_NUM_CALLS 0x3 diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h new file mode 100644 index 000000000..db4c84104 --- /dev/null +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOCFPGA_MBOX_H +#define SOCFPGA_MBOX_H + +#include + +#define MBOX_OFFSET 0xffa30000 + +#define MBOX_ATF_CLIENT_ID 0x1 +#define MBOX_JOB_ID 0x1 + +/* Mailbox interrupt flags and masks */ +#define MBOX_INT_FLAG_COE 0x1 +#define MBOX_INT_FLAG_RIE 0x2 +#define MBOX_INT_FLAG_UAE 0x100 +#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) +#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8))) + +/* Mailbox response and status */ +#define MBOX_RESP_BUFFER_SIZE 16 +#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff) +#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) +#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) +#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) +#define MBOX_STATUS_UA_MASK (1<<8) + +/* Mailbox command and response */ +#define MBOX_CMD_FREE_OFFSET 0x14 +#define MBOX_CMD_BUFFER_SIZE 32 +#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) +#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) +#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) +#define MBOX_INDIRECT (1 << 11) +#define MBOX_INSUFFICIENT_BUFFER -2 +#define MBOX_CIN 0x00 +#define MBOX_ROUT 0x04 +#define MBOX_URG 0x08 +#define MBOX_INT 0x0C +#define MBOX_COUT 0x20 +#define MBOX_RIN 0x24 +#define MBOX_STATUS 0x2C +#define MBOX_CMD_BUFFER 0x40 +#define MBOX_RESP_BUFFER 0xC0 + +#define MBOX_RESP_BUFFER_SIZE 16 +#define MBOX_RESP_OK 0 +#define MBOX_RESP_INVALID_CMD 1 +#define MBOX_RESP_UNKNOWN_BR 2 +#define MBOX_RESP_UNKNOWN 3 +#define MBOX_RESP_NOT_CONFIGURED 256 + +/* Mailbox SDM doorbell */ +#define MBOX_DOORBELL_TO_SDM 0x400 +#define MBOX_DOORBELL_FROM_SDM 0x480 + +/* Mailbox QSPI commands */ +#define MBOX_CMD_RESTART 2 +#define MBOX_CMD_QSPI_OPEN 50 +#define MBOX_CMD_QSPI_CLOSE 51 +#define MBOX_CMD_QSPI_DIRECT 59 +#define MBOX_CMD_GET_IDCODE 16 +#define MBOX_CMD_QSPI_SET_CS 52 + +/* Mailbox REBOOT commands */ +#define MBOX_CMD_REBOOT_HPS 71 + +/* Generic error handling */ +#define MBOX_TIMEOUT -2047 +#define MBOX_NO_RESPONSE -2 +#define MBOX_WRONG_ID -3 + +/* Mailbox status */ +#define RECONFIG_STATUS_STATE 0 +#define RECONFIG_STATUS_PIN_STATUS 2 +#define RECONFIG_STATUS_SOFTFUNC_STATUS 3 +#define PIN_STATUS_NSTATUS (U(1) << 31) +#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) +#define SOFTFUNC_STATUS_INIT_DONE (1 << 1) +#define SOFTFUNC_STATUS_CONF_DONE (1 << 0) +#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 + +/* SMC function IDs for SiP Service queries */ +#define SIP_SVC_CALL_COUNT 0x8200ff00 +#define SIP_SVC_UID 0x8200ff01 +#define SIP_SVC_VERSION 0x8200ff03 + +/* SiP Service Calls version numbers */ +#define SIP_SVC_VERSION_MAJOR 0 +#define SIP_SVC_VERSION_MINOR 1 + +/* Mailbox reconfiguration commands */ +#define MBOX_RECONFIG 6 +#define MBOX_RECONFIG_DATA 8 +#define MBOX_RECONFIG_STATUS 9 + +/* Sip get memory */ +#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 +#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 +#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 +#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 +#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 +#define INTEL_SIP_SMC_STATUS_OK 0 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x1000 +#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216 + +void mailbox_set_int(int interrupt_input); +int mailbox_init(void); +void mailbox_set_qspi_close(void); +void mailbox_set_qspi_open(void); +void mailbox_set_qspi_direct(void); +int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, + int len, int urgent, uint32_t *response); +void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, + int len, int urgent); +int mailbox_read_response(int job_id, uint32_t *response); +int mailbox_get_qspi_clock(void); +void mailbox_reset_cold(void); + +#endif /* SOCFPGA_MBOX_H */ diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c new file mode 100644 index 000000000..27838bfe7 --- /dev/null +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include "socfpga_mailbox.h" + +static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, + int len) +{ + uint32_t cmd_free_offset; + int i; + + cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN); + + if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) { + INFO("Insufficient buffer in mailbox\n"); + return MBOX_INSUFFICIENT_BUFFER; + } + + + mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + (cmd_free_offset++ * 4), + header_cmd); + + + for (i = 0; i < len; i++) { + cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; + mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + + (cmd_free_offset++ * 4), args[i]); + } + + cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; + mmio_write_32(MBOX_OFFSET + MBOX_CIN, cmd_free_offset); + + return 0; +} + +int mailbox_read_response(int job_id, uint32_t *response) +{ + int rin = 0; + int rout = 0; + int response_length = 0; + int resp = 0; + int total_resp_len = 0; + int timeout = 100000; + + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); + + while (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { + if (timeout-- < 0) + return MBOX_NO_RESPONSE; + } + + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); + + rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); + rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); + + while (rout != rin) { + resp = mmio_read_32(MBOX_OFFSET + + MBOX_RESP_BUFFER + ((rout++)*4)); + + rout %= MBOX_RESP_BUFFER_SIZE; + mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); + + if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || + MBOX_RESP_JOB_ID(resp) != job_id) { + return MBOX_WRONG_ID; + } + + if (MBOX_RESP_ERR(resp) > 0) { + INFO("Error in response: %x\n", resp); + return -resp; + } + response_length = MBOX_RESP_LEN(resp); + + while (response_length) { + + response_length--; + resp = mmio_read_32(MBOX_OFFSET + + MBOX_RESP_BUFFER + + (rout)*4); + if (response) { + *(response + total_resp_len) = resp; + total_resp_len++; + } + rout++; + rout %= MBOX_RESP_BUFFER_SIZE; + mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); + } + return total_resp_len; + } + + return MBOX_NO_RESPONSE; +} + + +int mailbox_poll_response(int job_id, int urgent, uint32_t *response) +{ + int timeout = 80000; + int rin = 0; + int rout = 0; + int response_length = 0; + int resp = 0; + int total_resp_len = 0; + + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); + + while (1) { + while (timeout > 0 && + mmio_read_32(MBOX_OFFSET + + MBOX_DOORBELL_FROM_SDM) != 1) { + timeout--; + } + + if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { + INFO("Timed out waiting for SDM"); + return MBOX_TIMEOUT; + } + + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); + + if (urgent & 1) { + if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & + MBOX_STATUS_UA_MASK) ^ + (urgent & MBOX_STATUS_UA_MASK)) { + mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); + return 0; + } + + mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); + INFO("Error: Mailbox did not get UA"); + return -1; + } + + rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); + rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); + + while (rout != rin) { + resp = mmio_read_32(MBOX_OFFSET + + MBOX_RESP_BUFFER + ((rout++)*4)); + + rout %= MBOX_RESP_BUFFER_SIZE; + mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); + + if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || + MBOX_RESP_JOB_ID(resp) != job_id) + continue; + + if (MBOX_RESP_ERR(resp) > 0) { + INFO("Error in response: %x\n", resp); + return -MBOX_RESP_ERR(resp); + } + response_length = MBOX_RESP_LEN(resp); + + while (response_length) { + + response_length--; + resp = mmio_read_32(MBOX_OFFSET + + MBOX_RESP_BUFFER + + (rout)*4); + if (response) { + *(response + total_resp_len) = resp; + total_resp_len++; + } + rout++; + rout %= MBOX_RESP_BUFFER_SIZE; + mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); + } + return total_resp_len; + } + } +} + +void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, + int len, int urgent) +{ + if (urgent) + mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); + + fill_mailbox_circular_buffer(MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | + MBOX_JOB_ID_CMD(job_id) | + MBOX_CMD_LEN_CMD(len) | + MBOX_INDIRECT | + cmd, args, len); +} + +int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, + int len, int urgent, uint32_t *response) +{ + int status; + + if (urgent) { + urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & + MBOX_STATUS_UA_MASK; + mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd); + status = 0; + } else { + status = fill_mailbox_circular_buffer( + MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | + MBOX_JOB_ID_CMD(job_id) | + cmd, args, len); + } + + if (status) + return status; + + return mailbox_poll_response(job_id, urgent, response); +} + +void mailbox_set_int(int interrupt) +{ + + mmio_write_32(MBOX_OFFSET+MBOX_INT, MBOX_COE_BIT(interrupt) | + MBOX_UAE_BIT(interrupt)); +} + + +void mailbox_set_qspi_open(void) +{ + mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, 0); +} + +void mailbox_set_qspi_direct(void) +{ + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); +} + +void mailbox_set_qspi_close(void) +{ + mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, 0); +} + +int mailbox_get_qspi_clock(void) +{ + mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); + return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); +} + +void mailbox_qspi_set_cs(int device_select) +{ + uint32_t cs_setting = device_select; + + /* QSPI device select settings at 31:28 */ + cs_setting = (cs_setting << 28); + mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting, + 1, 0, 0); +} + +void mailbox_reset_cold(void) +{ + mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, 0); +} + +int mailbox_init(void) +{ + int status = 0; + + mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE | + MBOX_INT_FLAG_UAE); + mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); + status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, 0); + + if (status) + return status; + + mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); + + return 0; +} + diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 1cb9c250c..7376b4143 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -27,9 +27,9 @@ #include "s10_reset_manager.h" #include "s10_clock_manager.h" #include "s10_pinmux.h" -#include "include/s10_mailbox.h" #include "qspi/cadence_qspi.h" #include "socfpga_handoff.h" +#include "socfpga_mailbox.h" #include "socfpga_private.h" #include "wdt/watchdog.h" diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 0a7f21873..9887cb1d5 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/plat/intel/soc/stratix10/include/s10_mailbox.h b/plat/intel/soc/stratix10/include/s10_mailbox.h deleted file mode 100644 index 554c26566..000000000 --- a/plat/intel/soc/stratix10/include/s10_mailbox.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __S10_MBOX__ -#define __S10_MBOX__ - -#define MBOX_OFFSET 0xffa30000 - -#define MBOX_ATF_CLIENT_ID 0x1 -#define MBOX_JOB_ID 0x1 - -/* Mailbox interrupt flags and masks */ -#define MBOX_INT_FLAG_COE 0x1 -#define MBOX_INT_FLAG_RIE 0x2 -#define MBOX_INT_FLAG_UAE 0x100 -#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) -#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<4))) - -/* Mailbox response and status */ -#define MBOX_RESP_BUFFER_SIZE 16 -#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff) -#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) -#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) -#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) -#define MBOX_STATUS_UA_MASK (1<<8) - -/* Mailbox command and response */ -#define MBOX_CMD_FREE_OFFSET 0x14 -#define MBOX_CMD_BUFFER_SIZE 32 -#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) -#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) -#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) -#define MBOX_INDIRECT (1 << 11) -#define MBOX_INSUFFICIENT_BUFFER -2 -#define MBOX_CIN 0x00 -#define MBOX_ROUT 0x04 -#define MBOX_URG 0x08 -#define MBOX_INT 0x0C -#define MBOX_COUT 0x20 -#define MBOX_RIN 0x24 -#define MBOX_STATUS 0x2C -#define MBOX_CMD_BUFFER 0x40 -#define MBOX_RESP_BUFFER 0xC0 - -#define MBOX_RESP_BUFFER_SIZE 16 -#define MBOX_RESP_OK 0 -#define MBOX_RESP_INVALID_CMD 1 -#define MBOX_RESP_UNKNOWN_BR 2 -#define MBOX_RESP_UNKNOWN 3 -#define MBOX_RESP_NOT_CONFIGURED 256 - -/* Mailbox SDM doorbell */ -#define MBOX_DOORBELL_TO_SDM 0x400 -#define MBOX_DOORBELL_FROM_SDM 0x480 - -/* Mailbox QSPI commands */ -#define MBOX_CMD_RESTART 2 -#define MBOX_CMD_QSPI_OPEN 50 -#define MBOX_CMD_QSPI_CLOSE 51 -#define MBOX_CMD_QSPI_DIRECT 59 -#define MBOX_CMD_GET_IDCODE 16 -#define MBOX_CMD_QSPI_SET_CS 52 - -/* Mailbox REBOOT commands */ -#define MBOX_CMD_REBOOT_HPS 71 - -/* Generic error handling */ -#define MBOX_TIMEOUT -2047 -#define MBOX_NO_RESPONSE -2 -#define MBOX_WRONG_ID -3 - -/* Mailbox status */ -#define RECONFIG_STATUS_STATE 0 -#define RECONFIG_STATUS_PIN_STATUS 2 -#define RECONFIG_STATUS_SOFTFUNC_STATUS 3 -#define PIN_STATUS_NSTATUS (1U << 31) -#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) -#define SOFTFUNC_STATUS_INIT_DONE (1 << 1) -#define SOFTFUNC_STATUS_CONF_DONE (1 << 0) -#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 - -/* SMC function IDs for SiP Service queries */ -#define SIP_SVC_CALL_COUNT 0x8200ff00 -#define SIP_SVC_UID 0x8200ff01 -#define SIP_SVC_VERSION 0x8200ff03 - -/* SiP Service Calls version numbers */ -#define SIP_SVC_VERSION_MAJOR 0 -#define SIP_SVC_VERSION_MINOR 1 - -/* Mailbox reconfiguration commands */ -#define MBOX_RECONFIG 6 -#define MBOX_RECONFIG_DATA 8 -#define MBOX_RECONFIG_STATUS 9 - -/* Sip get memory */ -#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 -#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 -#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 -#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 -#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 -#define INTEL_SIP_SMC_STATUS_OK 0 -#define INTEL_SIP_SMC_STATUS_ERROR 0x4 -#define INTEL_SIP_SMC_STATUS_BUSY 0x1 -#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 -#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x1000 -#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216 - -void mailbox_set_int(int interrupt_input); -int mailbox_init(void); -void mailbox_set_qspi_close(void); -void mailbox_set_qspi_open(void); -void mailbox_set_qspi_direct(void); -int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response); -void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent); -int mailbox_read_response(int job_id, uint32_t *response); -int mailbox_get_qspi_clock(void); -void mailbox_reset_cold(void); - -#endif diff --git a/plat/intel/soc/stratix10/plat_psci.c b/plat/intel/soc/stratix10/plat_psci.c index f4a970e75..73389c95d 100644 --- a/plat/intel/soc/stratix10/plat_psci.c +++ b/plat/intel/soc/stratix10/plat_psci.c @@ -16,7 +16,7 @@ #include "platform_def.h" #include "s10_reset_manager.h" -#include "s10_mailbox.h" +#include "socfpga_mailbox.h" #define S10_RSTMGR_OFST 0xffd11000 #define S10_RSTMGR_MPUMODRST_OFST 0x20 diff --git a/plat/intel/soc/stratix10/plat_sip_svc.c b/plat/intel/soc/stratix10/plat_sip_svc.c index 2c2332ba9..23a009d12 100644 --- a/plat/intel/soc/stratix10/plat_sip_svc.c +++ b/plat/intel/soc/stratix10/plat_sip_svc.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include /* Number of SiP Calls implemented */ diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index d1ff07761..2ed1cb442 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -46,7 +46,7 @@ BL2_SOURCES += \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/stratix10/soc/s10_system_manager.c \ common/desc_image_load.c \ - plat/intel/soc/stratix10/soc/s10_mailbox.c \ + plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c @@ -63,7 +63,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ plat/intel/soc/stratix10/soc/s10_reset_manager.c\ plat/intel/soc/stratix10/soc/s10_pinmux.c \ plat/intel/soc/stratix10/soc/s10_clock_manager.c\ - plat/intel/soc/stratix10/soc/s10_mailbox.c + plat/intel/soc/common/soc/socfpga_mailbox.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/stratix10/soc/s10_mailbox.c b/plat/intel/soc/stratix10/soc/s10_mailbox.c deleted file mode 100644 index 00a07f33a..000000000 --- a/plat/intel/soc/stratix10/soc/s10_mailbox.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include "s10_mailbox.h" - -static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, - int len) -{ - uint32_t cmd_free_offset; - int i; - - cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN); - - if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) { - INFO("Insufficient buffer in mailbox\n"); - return MBOX_INSUFFICIENT_BUFFER; - } - - - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + (cmd_free_offset++ * 4), - header_cmd); - - - for (i = 0; i < len; i++) { - cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + - (cmd_free_offset++ * 4), args[i]); - } - - cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_CIN, cmd_free_offset); - - return 0; -} - -int mailbox_read_response(int job_id, uint32_t *response) -{ - int rin = 0; - int rout = 0; - int response_length = 0; - int resp = 0; - int total_resp_len = 0; - int timeout = 100000; - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - - while (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { - if (timeout-- < 0) - return MBOX_NO_RESPONSE; - } - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - - rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); - rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); - - while (rout != rin) { - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4)); - - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - - if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || - MBOX_RESP_JOB_ID(resp) != job_id) { - return MBOX_WRONG_ID; - } - - if (MBOX_RESP_ERR(resp) > 0) { - INFO("Error in response: %x\n", resp); - return -resp; - } - response_length = MBOX_RESP_LEN(resp); - - while (response_length) { - - response_length--; - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + - (rout)*4); - if (response) { - *(response + total_resp_len) = resp; - total_resp_len++; - } - rout++; - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - } - return total_resp_len; - } - - return MBOX_NO_RESPONSE; -} - - -int mailbox_poll_response(int job_id, int urgent, uint32_t *response) -{ - int timeout = 80000; - int rin = 0; - int rout = 0; - int response_length = 0; - int resp = 0; - int total_resp_len = 0; - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - - while (1) { - while (timeout > 0 && - mmio_read_32(MBOX_OFFSET + - MBOX_DOORBELL_FROM_SDM) != 1) { - timeout--; - } - - if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { - INFO("Timed out waiting for SDM"); - return MBOX_TIMEOUT; - } - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - - if (urgent & 1) { - if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & - MBOX_STATUS_UA_MASK) ^ - (urgent & MBOX_STATUS_UA_MASK)) { - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - return 0; - } - - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - INFO("Error: Mailbox did not get UA"); - return -1; - } - - rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); - rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); - - while (rout != rin) { - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4)); - - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - - if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || - MBOX_RESP_JOB_ID(resp) != job_id) - continue; - - if (MBOX_RESP_ERR(resp) > 0) { - INFO("Error in response: %x\n", resp); - return -MBOX_RESP_ERR(resp); - } - response_length = MBOX_RESP_LEN(resp); - - while (response_length) { - - response_length--; - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + - (rout)*4); - if (response) { - *(response + total_resp_len) = resp; - total_resp_len++; - } - rout++; - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - } - return total_resp_len; - } - } -} - -void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent) -{ - if (urgent) - mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); - - fill_mailbox_circular_buffer(MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | - MBOX_JOB_ID_CMD(job_id) | - MBOX_CMD_LEN_CMD(len) | - MBOX_INDIRECT | - cmd, args, len); -} - -int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response) -{ - int status; - - if (urgent) { - urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & - MBOX_STATUS_UA_MASK; - mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); - } - - status = fill_mailbox_circular_buffer( - MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | - MBOX_JOB_ID_CMD(job_id) | - cmd, args, len); - - if (status) - return status; - - return mailbox_poll_response(job_id, urgent, response); -} - -void mailbox_set_int(int interrupt) -{ - - mmio_write_32(MBOX_OFFSET+MBOX_INT, MBOX_COE_BIT(interrupt) | - MBOX_UAE_BIT(interrupt)); -} - - -void mailbox_set_qspi_open(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, 0); -} - -void mailbox_set_qspi_direct(void) -{ - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); -} - -void mailbox_set_qspi_close(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, 0); -} - -int mailbox_get_qspi_clock(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); -} - -void mailbox_qspi_set_cs(int device_select) -{ - uint32_t cs_setting = device_select; - - /* QSPI device select settings at 31:28 */ - cs_setting = (cs_setting << 28); - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting, - 1, 0, 0); -} - -void mailbox_reset_cold(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, 0); -} - -int mailbox_init(void) -{ - int status = 0; - - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, 0); - - if (status) - return status; - - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - - return 0; -} - -- cgit v1.2.3 From c76d42398990044ea84b6348d77a5f34bd7e9a8e Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Wed, 23 Oct 2019 17:35:32 +0800 Subject: intel: Refactor common platform code [4/5] Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: Hadi Asyrafi Change-Id: I1a0390fca6db4c89919a2a038de2a9d96c3ae4fd --- plat/intel/soc/agilex/platform.mk | 4 +- plat/intel/soc/agilex/socfpga_psci.c | 198 ----------------- plat/intel/soc/agilex/socfpga_sip_svc.c | 378 -------------------------------- plat/intel/soc/common/socfpga_psci.c | 190 ++++++++++++++++ plat/intel/soc/common/socfpga_sip_svc.c | 378 ++++++++++++++++++++++++++++++++ plat/intel/soc/stratix10/platform.mk | 4 +- 6 files changed, 572 insertions(+), 580 deletions(-) delete mode 100644 plat/intel/soc/agilex/socfpga_psci.c delete mode 100644 plat/intel/soc/agilex/socfpga_sip_svc.c create mode 100644 plat/intel/soc/common/socfpga_psci.c create mode 100644 plat/intel/soc/common/socfpga_sip_svc.c diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index bf8fc36b2..dc56ac8ba 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -57,9 +57,9 @@ BL31_SOURCES += \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/aem_generic.S \ plat/common/plat_psci_common.c \ - plat/intel/soc/agilex/socfpga_sip_svc.c \ + plat/intel/soc/common/socfpga_sip_svc.c \ plat/intel/soc/agilex/bl31_plat_setup.c \ - plat/intel/soc/agilex/socfpga_psci.c \ + plat/intel/soc/common/socfpga_psci.c \ plat/intel/soc/common/socfpga_topology.c \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/agilex/soc/agilex_reset_manager.c \ diff --git a/plat/intel/soc/agilex/socfpga_psci.c b/plat/intel/soc/agilex/socfpga_psci.c deleted file mode 100644 index 4b29159bd..000000000 --- a/plat/intel/soc/agilex/socfpga_psci.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -#include "agilex_reset_manager.h" -#include "socfpga_mailbox.h" - -#define AGX_RSTMGR_OFST 0xffd11000 -#define AGX_RSTMGR_MPUMODRST_OFST 0x20 - -uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; -uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE; - -/******************************************************************************* - * plat handler called when a CPU is about to enter standby. - ******************************************************************************/ -void socfpga_cpu_standby(plat_local_state_t cpu_state) -{ - /* - * Enter standby state - * dsb is good practice before using wfi to enter low power states - */ - VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state); - dsb(); - wfi(); -} - -/******************************************************************************* - * plat handler called when a power domain is about to be turned on. The - * mpidr determines the CPU to be turned on. - ******************************************************************************/ -int socfpga_pwr_domain_on(u_register_t mpidr) -{ - unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); - - VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); - - if (cpu_id == -1) - return PSCI_E_INTERN_FAIL; - - *cpuid_release = cpu_id; - - /* release core reset */ - mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); - return PSCI_E_SUCCESS; -} - -/******************************************************************************* - * plat handler called when a power domain is about to be turned off. The - * target_state encodes the power state that each level should transition to. - ******************************************************************************/ -void socfpga_pwr_domain_off(const psci_power_state_t *target_state) -{ - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - - /* Prevent interrupts from spuriously waking up this cpu */ - gicv2_cpuif_disable(); -} - -/******************************************************************************* - * plat handler called when a power domain is about to be suspended. The - * target_state encodes the power state that each level should transition to. - ******************************************************************************/ -void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state) -{ - unsigned int cpu_id = plat_my_core_pos(); - - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - /* assert core reset */ - mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); - -} - -/******************************************************************************* - * plat handler called when a power domain has just been powered on after - * being turned off earlier. The target_state encodes the low power state that - * each level has woken up from. - ******************************************************************************/ -void socfpga_pwr_domain_on_finish(const psci_power_state_t *target_state) -{ - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - - /* Program the gic per-cpu distributor or re-distributor interface */ - gicv2_pcpu_distif_init(); - gicv2_set_pe_target_mask(plat_my_core_pos()); - - /* Enable the gic cpu interface */ - gicv2_cpuif_enable(); -} - -/******************************************************************************* - * plat handler called when a power domain has just been powered on after - * having been suspended earlier. The target_state encodes the low power state - * that each level has woken up from. - * TODO: At the moment we reuse the on finisher and reinitialize the secure - * context. Need to implement a separate suspend finisher. - ******************************************************************************/ -void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state) -{ - unsigned int cpu_id = plat_my_core_pos(); - - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - - /* release core reset */ - mmio_clrbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); -} - -/******************************************************************************* - * plat handlers to shutdown/reboot the system - ******************************************************************************/ -static void __dead2 socfpga_system_off(void) -{ - wfi(); - ERROR("System Off: operation not handled.\n"); - panic(); -} - -static void __dead2 socfpga_system_reset(void) -{ - INFO("assert Peripheral from Reset\r\n"); - - deassert_peripheral_reset(); - mailbox_reset_cold(); - - while (1) - wfi(); -} - -int socfpga_validate_power_state(unsigned int power_state, - psci_power_state_t *req_state) -{ - VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); - - return PSCI_E_SUCCESS; -} - -int socfpga_validate_ns_entrypoint(unsigned long ns_entrypoint) -{ - VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint); - return PSCI_E_SUCCESS; -} - -void socfpga_get_sys_suspend_power_state(psci_power_state_t *req_state) -{ - req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; - req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; -} - -/******************************************************************************* - * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard - * platform layer will take care of registering the handlers with PSCI. - ******************************************************************************/ -const plat_psci_ops_t socfpga_psci_pm_ops = { - .cpu_standby = socfpga_cpu_standby, - .pwr_domain_on = socfpga_pwr_domain_on, - .pwr_domain_off = socfpga_pwr_domain_off, - .pwr_domain_suspend = socfpga_pwr_domain_suspend, - .pwr_domain_on_finish = socfpga_pwr_domain_on_finish, - .pwr_domain_suspend_finish = socfpga_pwr_domain_suspend_finish, - .system_off = socfpga_system_off, - .system_reset = socfpga_system_reset, - .validate_power_state = socfpga_validate_power_state, - .validate_ns_entrypoint = socfpga_validate_ns_entrypoint, - .get_sys_suspend_power_state = socfpga_get_sys_suspend_power_state -}; - -/******************************************************************************* - * Export the platform specific power ops. - ******************************************************************************/ -int plat_setup_psci_ops(uintptr_t sec_entrypoint, - const struct plat_psci_ops **psci_ops) -{ - /* Save warm boot entrypoint.*/ - *agilex_sec_entry = sec_entrypoint; - - *psci_ops = &socfpga_psci_pm_ops; - return 0; -} diff --git a/plat/intel/soc/agilex/socfpga_sip_svc.c b/plat/intel/soc/agilex/socfpga_sip_svc.c deleted file mode 100644 index 16e3c0393..000000000 --- a/plat/intel/soc/agilex/socfpga_sip_svc.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -#include "socfpga_mailbox.h" - -/* Number of SiP Calls implemented */ -#define SIP_NUM_CALLS 0x3 - -/* Total buffer the driver can hold */ -#define FPGA_CONFIG_BUFFER_SIZE 4 - -int current_block; -int current_buffer; -int current_id = 1; -int max_blocks; -uint32_t bytes_per_block; -uint32_t blocks_submitted; -uint32_t blocks_completed; - -struct fpga_config_info { - uint32_t addr; - int size; - int size_written; - uint32_t write_requested; - int subblocks_sent; - int block_number; -}; - -/* SiP Service UUID */ -DEFINE_SVC_UUID2(intl_svc_uid, - 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, - 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); - -uint64_t socfpga_sip_handler(uint32_t smc_fid, - uint64_t x1, - uint64_t x2, - uint64_t x3, - uint64_t x4, - void *cookie, - void *handle, - uint64_t flags) -{ - ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); - SMC_RET1(handle, SMC_UNK); -} - -struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; - -static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) -{ - uint32_t args[3]; - - while (max_blocks > 0 && buffer->size > buffer->size_written) { - if (buffer->size - buffer->size_written <= - bytes_per_block) { - args[0] = (1<<8); - args[1] = buffer->addr + buffer->size_written; - args[2] = buffer->size - buffer->size_written; - buffer->size_written += - buffer->size - buffer->size_written; - buffer->subblocks_sent++; - mailbox_send_cmd_async(0x4, - MBOX_RECONFIG_DATA, - args, 3, 0); - current_buffer++; - current_buffer %= FPGA_CONFIG_BUFFER_SIZE; - } else { - args[0] = (1<<8); - args[1] = buffer->addr + buffer->size_written; - args[2] = bytes_per_block; - buffer->size_written += bytes_per_block; - mailbox_send_cmd_async(0x4, - MBOX_RECONFIG_DATA, - args, 3, 0); - buffer->subblocks_sent++; - } - max_blocks--; - } -} - -static int intel_fpga_sdm_write_all(void) -{ - int i; - - for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) - intel_fpga_sdm_write_buffer( - &fpga_config_buffers[current_buffer]); - - return 0; -} - -uint32_t intel_mailbox_fpga_config_isdone(void) -{ - uint32_t args[2]; - uint32_t response[6]; - int status; - - status = mailbox_send_cmd(1, MBOX_RECONFIG_STATUS, args, 0, 0, - response); - - if (status < 0) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (response[RECONFIG_STATUS_STATE] && - response[RECONFIG_STATUS_STATE] != MBOX_CFGSTAT_STATE_CONFIG) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (!(response[RECONFIG_STATUS_PIN_STATUS] & PIN_STATUS_NSTATUS)) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_SEU_ERROR) - return INTEL_SIP_SMC_STATUS_ERROR; - - if ((response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_CONF_DONE) && - (response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_INIT_DONE)) - return INTEL_SIP_SMC_STATUS_OK; - - return INTEL_SIP_SMC_STATUS_ERROR; -} - -static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) -{ - int i; - - for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - if (fpga_config_buffers[i].block_number == current_block) { - fpga_config_buffers[i].subblocks_sent--; - if (fpga_config_buffers[i].subblocks_sent == 0 - && fpga_config_buffers[i].size <= - fpga_config_buffers[i].size_written) { - fpga_config_buffers[i].write_requested = 0; - current_block++; - *buffer_addr_completed = - fpga_config_buffers[i].addr; - return 0; - } - } - } - - return -1; -} - -unsigned int address_in_ddr(uint32_t *addr) -{ - if (((unsigned long long)addr > DRAM_BASE) && - ((unsigned long long)addr < DRAM_BASE + DRAM_SIZE)) - return 0; - - return -1; -} - -int intel_fpga_config_completed_write(uint32_t *completed_addr, - uint32_t *count) -{ - uint32_t status = INTEL_SIP_SMC_STATUS_OK; - *count = 0; - int resp_len = 0; - uint32_t resp[5]; - int all_completed = 1; - int count_check = 0; - - if (address_in_ddr(completed_addr) != 0 || address_in_ddr(count) != 0) - return INTEL_SIP_SMC_STATUS_ERROR; - - for (count_check = 0; count_check < 3; count_check++) - if (address_in_ddr(&completed_addr[*count + count_check]) != 0) - return INTEL_SIP_SMC_STATUS_ERROR; - - resp_len = mailbox_read_response(0x4, resp); - - while (resp_len >= 0 && *count < 3) { - max_blocks++; - if (mark_last_buffer_xfer_completed( - &completed_addr[*count]) == 0) - *count = *count + 1; - else - break; - resp_len = mailbox_read_response(0x4, resp); - } - - if (*count <= 0) { - if (resp_len != MBOX_NO_RESPONSE && - resp_len != MBOX_TIMEOUT && resp_len != 0) { - return INTEL_SIP_SMC_STATUS_ERROR; - } - - *count = 0; - } - - intel_fpga_sdm_write_all(); - - if (*count > 0) - status = INTEL_SIP_SMC_STATUS_OK; - else if (*count == 0) - status = INTEL_SIP_SMC_STATUS_BUSY; - - for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - if (fpga_config_buffers[i].write_requested != 0) { - all_completed = 0; - break; - } - } - - if (all_completed == 1) - return INTEL_SIP_SMC_STATUS_OK; - - return status; -} - -int intel_fpga_config_start(uint32_t config_type) -{ - uint32_t response[3]; - int status = 0; - - status = mailbox_send_cmd(2, MBOX_RECONFIG, 0, 0, 0, - response); - - if (status < 0) - return status; - - max_blocks = response[0]; - bytes_per_block = response[1]; - - for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - fpga_config_buffers[i].size = 0; - fpga_config_buffers[i].size_written = 0; - fpga_config_buffers[i].addr = 0; - fpga_config_buffers[i].write_requested = 0; - fpga_config_buffers[i].block_number = 0; - fpga_config_buffers[i].subblocks_sent = 0; - } - - blocks_submitted = 0; - current_block = 0; - current_buffer = 0; - - return 0; -} - - -uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) -{ - int i = 0; - uint32_t status = INTEL_SIP_SMC_STATUS_OK; - - if (mem < DRAM_BASE || mem > DRAM_BASE + DRAM_SIZE) - status = INTEL_SIP_SMC_STATUS_REJECTED; - - if (mem + size > DRAM_BASE + DRAM_SIZE) - status = INTEL_SIP_SMC_STATUS_REJECTED; - - for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - if (!fpga_config_buffers[i].write_requested) { - fpga_config_buffers[i].addr = mem; - fpga_config_buffers[i].size = size; - fpga_config_buffers[i].size_written = 0; - fpga_config_buffers[i].write_requested = 1; - fpga_config_buffers[i].block_number = - blocks_submitted++; - fpga_config_buffers[i].subblocks_sent = 0; - break; - } - } - - - if (i == FPGA_CONFIG_BUFFER_SIZE) { - status = INTEL_SIP_SMC_STATUS_REJECTED; - return status; - } else if (i == FPGA_CONFIG_BUFFER_SIZE - 1) { - status = INTEL_SIP_SMC_STATUS_BUSY; - } - - intel_fpga_sdm_write_all(); - - return status; -} - -/* - * This function is responsible for handling all SiP calls from the NS world - */ - -uintptr_t sip_smc_handler(uint32_t smc_fid, - u_register_t x1, - u_register_t x2, - u_register_t x3, - u_register_t x4, - void *cookie, - void *handle, - u_register_t flags) -{ - uint32_t status = INTEL_SIP_SMC_STATUS_OK; - uint32_t completed_addr[3]; - uint32_t count = 0; - - switch (smc_fid) { - case SIP_SVC_UID: - /* Return UID to the caller */ - SMC_UUID_RET(handle, intl_svc_uid); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: - status = intel_mailbox_fpga_config_isdone(); - SMC_RET4(handle, status, 0, 0, 0); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: - SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, - INTEL_SIP_SMC_FPGA_CONFIG_ADDR, - INTEL_SIP_SMC_FPGA_CONFIG_SIZE - - INTEL_SIP_SMC_FPGA_CONFIG_ADDR); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_START: - status = intel_fpga_config_start(x1); - SMC_RET4(handle, status, 0, 0, 0); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: - status = intel_fpga_config_write(x1, x2); - SMC_RET4(handle, status, 0, 0, 0); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: - status = intel_fpga_config_completed_write(completed_addr, - &count); - switch (count) { - case 1: - SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, - completed_addr[0], 0, 0); - break; - case 2: - SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, - completed_addr[0], - completed_addr[1], 0); - break; - case 3: - SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, - completed_addr[0], - completed_addr[1], - completed_addr[2]); - break; - case 0: - SMC_RET4(handle, status, 0, 0, 0); - break; - default: - SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); - } - break; - - default: - return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, - cookie, handle, flags); - } -} - -DECLARE_RT_SVC( - agilex_sip_svc, - OEN_SIP_START, - OEN_SIP_END, - SMC_TYPE_FAST, - NULL, - sip_smc_handler -); - -DECLARE_RT_SVC( - agilex_sip_svc_std, - OEN_SIP_START, - OEN_SIP_END, - SMC_TYPE_YIELD, - NULL, - sip_smc_handler -); diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c new file mode 100644 index 000000000..e29836173 --- /dev/null +++ b/plat/intel/soc/common/socfpga_psci.c @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +#include "socfpga_mailbox.h" +#include "socfpga_plat_def.h" + + +uintptr_t *socfpga_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; +uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE; + +/******************************************************************************* + * plat handler called when a CPU is about to enter standby. + ******************************************************************************/ +void socfpga_cpu_standby(plat_local_state_t cpu_state) +{ + /* + * Enter standby state + * dsb is good practice before using wfi to enter low power states + */ + VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state); + dsb(); + wfi(); +} + +/******************************************************************************* + * plat handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +int socfpga_pwr_domain_on(u_register_t mpidr) +{ + unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); + + VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); + + if (cpu_id == -1) + return PSCI_E_INTERN_FAIL; + + *cpuid_release = cpu_id; + + /* release core reset */ + mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * plat handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void socfpga_pwr_domain_off(const psci_power_state_t *target_state) +{ + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* Prevent interrupts from spuriously waking up this cpu */ + gicv2_cpuif_disable(); +} + +/******************************************************************************* + * plat handler called when a power domain is about to be suspended. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + unsigned int cpu_id = plat_my_core_pos(); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + /* assert core reset */ + mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); + +} + +/******************************************************************************* + * plat handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +void socfpga_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* Program the gic per-cpu distributor or re-distributor interface */ + gicv2_pcpu_distif_init(); + gicv2_set_pe_target_mask(plat_my_core_pos()); + + /* Enable the gic cpu interface */ + gicv2_cpuif_enable(); +} + +/******************************************************************************* + * plat handler called when a power domain has just been powered on after + * having been suspended earlier. The target_state encodes the low power state + * that each level has woken up from. + * TODO: At the moment we reuse the on finisher and reinitialize the secure + * context. Need to implement a separate suspend finisher. + ******************************************************************************/ +void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + unsigned int cpu_id = plat_my_core_pos(); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* release core reset */ + mmio_clrbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); +} + +/******************************************************************************* + * plat handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 socfpga_system_off(void) +{ + wfi(); + ERROR("System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 socfpga_system_reset(void) +{ + mailbox_reset_cold(); + + while (1) + wfi(); +} + +int socfpga_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); + + return PSCI_E_SUCCESS; +} + +int socfpga_validate_ns_entrypoint(unsigned long ns_entrypoint) +{ + VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint); + return PSCI_E_SUCCESS; +} + +void socfpga_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; + req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; +} + +/******************************************************************************* + * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard + * platform layer will take care of registering the handlers with PSCI. + ******************************************************************************/ +const plat_psci_ops_t socfpga_psci_pm_ops = { + .cpu_standby = socfpga_cpu_standby, + .pwr_domain_on = socfpga_pwr_domain_on, + .pwr_domain_off = socfpga_pwr_domain_off, + .pwr_domain_suspend = socfpga_pwr_domain_suspend, + .pwr_domain_on_finish = socfpga_pwr_domain_on_finish, + .pwr_domain_suspend_finish = socfpga_pwr_domain_suspend_finish, + .system_off = socfpga_system_off, + .system_reset = socfpga_system_reset, + .validate_power_state = socfpga_validate_power_state, + .validate_ns_entrypoint = socfpga_validate_ns_entrypoint, + .get_sys_suspend_power_state = socfpga_get_sys_suspend_power_state +}; + +/******************************************************************************* + * Export the platform specific power ops. + ******************************************************************************/ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const struct plat_psci_ops **psci_ops) +{ + /* Save warm boot entrypoint.*/ + *socfpga_sec_entry = sec_entrypoint; + + *psci_ops = &socfpga_psci_pm_ops; + return 0; +} diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c new file mode 100644 index 000000000..88750d771 --- /dev/null +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include "socfpga_mailbox.h" + +/* Number of SiP Calls implemented */ +#define SIP_NUM_CALLS 0x3 + +/* Total buffer the driver can hold */ +#define FPGA_CONFIG_BUFFER_SIZE 4 + +int current_block; +int current_buffer; +int current_id = 1; +int max_blocks; +uint32_t bytes_per_block; +uint32_t blocks_submitted; +uint32_t blocks_completed; + +struct fpga_config_info { + uint32_t addr; + int size; + int size_written; + uint32_t write_requested; + int subblocks_sent; + int block_number; +}; + +/* SiP Service UUID */ +DEFINE_SVC_UUID2(intl_svc_uid, + 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, + 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); + +uint64_t socfpga_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + SMC_RET1(handle, SMC_UNK); +} + +struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; + +static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) +{ + uint32_t args[3]; + + while (max_blocks > 0 && buffer->size > buffer->size_written) { + if (buffer->size - buffer->size_written <= + bytes_per_block) { + args[0] = (1<<8); + args[1] = buffer->addr + buffer->size_written; + args[2] = buffer->size - buffer->size_written; + buffer->size_written += + buffer->size - buffer->size_written; + buffer->subblocks_sent++; + mailbox_send_cmd_async(0x4, + MBOX_RECONFIG_DATA, + args, 3, 0); + current_buffer++; + current_buffer %= FPGA_CONFIG_BUFFER_SIZE; + } else { + args[0] = (1<<8); + args[1] = buffer->addr + buffer->size_written; + args[2] = bytes_per_block; + buffer->size_written += bytes_per_block; + mailbox_send_cmd_async(0x4, + MBOX_RECONFIG_DATA, + args, 3, 0); + buffer->subblocks_sent++; + } + max_blocks--; + } +} + +static int intel_fpga_sdm_write_all(void) +{ + int i; + + for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) + intel_fpga_sdm_write_buffer( + &fpga_config_buffers[current_buffer]); + + return 0; +} + +uint32_t intel_mailbox_fpga_config_isdone(void) +{ + uint32_t args[2]; + uint32_t response[6]; + int status; + + status = mailbox_send_cmd(1, MBOX_RECONFIG_STATUS, args, 0, 0, + response); + + if (status < 0) + return INTEL_SIP_SMC_STATUS_ERROR; + + if (response[RECONFIG_STATUS_STATE] && + response[RECONFIG_STATUS_STATE] != MBOX_CFGSTAT_STATE_CONFIG) + return INTEL_SIP_SMC_STATUS_ERROR; + + if (!(response[RECONFIG_STATUS_PIN_STATUS] & PIN_STATUS_NSTATUS)) + return INTEL_SIP_SMC_STATUS_ERROR; + + if (response[RECONFIG_STATUS_SOFTFUNC_STATUS] & + SOFTFUNC_STATUS_SEU_ERROR) + return INTEL_SIP_SMC_STATUS_ERROR; + + if ((response[RECONFIG_STATUS_SOFTFUNC_STATUS] & + SOFTFUNC_STATUS_CONF_DONE) && + (response[RECONFIG_STATUS_SOFTFUNC_STATUS] & + SOFTFUNC_STATUS_INIT_DONE)) + return INTEL_SIP_SMC_STATUS_OK; + + return INTEL_SIP_SMC_STATUS_ERROR; +} + +static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) +{ + int i; + + for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { + if (fpga_config_buffers[i].block_number == current_block) { + fpga_config_buffers[i].subblocks_sent--; + if (fpga_config_buffers[i].subblocks_sent == 0 + && fpga_config_buffers[i].size <= + fpga_config_buffers[i].size_written) { + fpga_config_buffers[i].write_requested = 0; + current_block++; + *buffer_addr_completed = + fpga_config_buffers[i].addr; + return 0; + } + } + } + + return -1; +} + +unsigned int address_in_ddr(uint32_t *addr) +{ + if (((unsigned long long)addr > DRAM_BASE) && + ((unsigned long long)addr < DRAM_BASE + DRAM_SIZE)) + return 0; + + return -1; +} + +int intel_fpga_config_completed_write(uint32_t *completed_addr, + uint32_t *count) +{ + uint32_t status = INTEL_SIP_SMC_STATUS_OK; + *count = 0; + int resp_len = 0; + uint32_t resp[5]; + int all_completed = 1; + int count_check = 0; + + if (address_in_ddr(completed_addr) != 0 || address_in_ddr(count) != 0) + return INTEL_SIP_SMC_STATUS_ERROR; + + for (count_check = 0; count_check < 3; count_check++) + if (address_in_ddr(&completed_addr[*count + count_check]) != 0) + return INTEL_SIP_SMC_STATUS_ERROR; + + resp_len = mailbox_read_response(0x4, resp); + + while (resp_len >= 0 && *count < 3) { + max_blocks++; + if (mark_last_buffer_xfer_completed( + &completed_addr[*count]) == 0) + *count = *count + 1; + else + break; + resp_len = mailbox_read_response(0x4, resp); + } + + if (*count <= 0) { + if (resp_len != MBOX_NO_RESPONSE && + resp_len != MBOX_TIMEOUT && resp_len != 0) { + return INTEL_SIP_SMC_STATUS_ERROR; + } + + *count = 0; + } + + intel_fpga_sdm_write_all(); + + if (*count > 0) + status = INTEL_SIP_SMC_STATUS_OK; + else if (*count == 0) + status = INTEL_SIP_SMC_STATUS_BUSY; + + for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { + if (fpga_config_buffers[i].write_requested != 0) { + all_completed = 0; + break; + } + } + + if (all_completed == 1) + return INTEL_SIP_SMC_STATUS_OK; + + return status; +} + +int intel_fpga_config_start(uint32_t config_type) +{ + uint32_t response[3]; + int status = 0; + + status = mailbox_send_cmd(2, MBOX_RECONFIG, 0, 0, 0, + response); + + if (status < 0) + return status; + + max_blocks = response[0]; + bytes_per_block = response[1]; + + for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { + fpga_config_buffers[i].size = 0; + fpga_config_buffers[i].size_written = 0; + fpga_config_buffers[i].addr = 0; + fpga_config_buffers[i].write_requested = 0; + fpga_config_buffers[i].block_number = 0; + fpga_config_buffers[i].subblocks_sent = 0; + } + + blocks_submitted = 0; + current_block = 0; + current_buffer = 0; + + return 0; +} + + +uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) +{ + int i = 0; + uint32_t status = INTEL_SIP_SMC_STATUS_OK; + + if (mem < DRAM_BASE || mem > DRAM_BASE + DRAM_SIZE) + status = INTEL_SIP_SMC_STATUS_REJECTED; + + if (mem + size > DRAM_BASE + DRAM_SIZE) + status = INTEL_SIP_SMC_STATUS_REJECTED; + + for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { + if (!fpga_config_buffers[i].write_requested) { + fpga_config_buffers[i].addr = mem; + fpga_config_buffers[i].size = size; + fpga_config_buffers[i].size_written = 0; + fpga_config_buffers[i].write_requested = 1; + fpga_config_buffers[i].block_number = + blocks_submitted++; + fpga_config_buffers[i].subblocks_sent = 0; + break; + } + } + + + if (i == FPGA_CONFIG_BUFFER_SIZE) { + status = INTEL_SIP_SMC_STATUS_REJECTED; + return status; + } else if (i == FPGA_CONFIG_BUFFER_SIZE - 1) { + status = INTEL_SIP_SMC_STATUS_BUSY; + } + + intel_fpga_sdm_write_all(); + + return status; +} + +/* + * This function is responsible for handling all SiP calls from the NS world + */ + +uintptr_t sip_smc_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + uint32_t status = INTEL_SIP_SMC_STATUS_OK; + uint32_t completed_addr[3]; + uint32_t count = 0; + + switch (smc_fid) { + case SIP_SVC_UID: + /* Return UID to the caller */ + SMC_UUID_RET(handle, intl_svc_uid); + break; + case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: + status = intel_mailbox_fpga_config_isdone(); + SMC_RET4(handle, status, 0, 0, 0); + break; + case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: + SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, + INTEL_SIP_SMC_FPGA_CONFIG_ADDR, + INTEL_SIP_SMC_FPGA_CONFIG_SIZE - + INTEL_SIP_SMC_FPGA_CONFIG_ADDR); + break; + case INTEL_SIP_SMC_FPGA_CONFIG_START: + status = intel_fpga_config_start(x1); + SMC_RET4(handle, status, 0, 0, 0); + break; + case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: + status = intel_fpga_config_write(x1, x2); + SMC_RET4(handle, status, 0, 0, 0); + break; + case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: + status = intel_fpga_config_completed_write(completed_addr, + &count); + switch (count) { + case 1: + SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, + completed_addr[0], 0, 0); + break; + case 2: + SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, + completed_addr[0], + completed_addr[1], 0); + break; + case 3: + SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, + completed_addr[0], + completed_addr[1], + completed_addr[2]); + break; + case 0: + SMC_RET4(handle, status, 0, 0, 0); + break; + default: + SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); + } + break; + + default: + return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, + cookie, handle, flags); + } +} + +DECLARE_RT_SVC( + socfpga_sip_svc, + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + sip_smc_handler +); + +DECLARE_RT_SVC( + socfpga_sip_svc_std, + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_YIELD, + NULL, + sip_smc_handler +); diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 2ed1cb442..5bf8f6555 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -55,9 +55,9 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ - plat/intel/soc/stratix10/plat_sip_svc.c \ + plat/intel/soc/common/socfpga_sip_svc.c \ plat/intel/soc/stratix10/bl31_plat_setup.c \ - plat/intel/soc/stratix10/plat_psci.c \ + plat/intel/soc/common/socfpga_psci.c \ plat/intel/soc/common/socfpga_topology.c \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/stratix10/soc/s10_reset_manager.c\ -- cgit v1.2.3 From 1520b5d6888c470692c73fa1bb6fcf09aa96869b Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Wed, 23 Oct 2019 17:58:06 +0800 Subject: intel: Refactor common platform code [5/5] Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: Hadi Asyrafi Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd --- plat/intel/soc/agilex/bl2_plat_setup.c | 2 - plat/intel/soc/agilex/bl31_plat_setup.c | 5 +-- plat/intel/soc/agilex/platform.mk | 34 ++++++-------- plat/intel/soc/common/drivers/ccu/ncore_ccu.c | 1 - plat/intel/soc/common/drivers/qspi/cadence_qspi.c | 1 - plat/intel/soc/common/drivers/wdt/watchdog.c | 1 - plat/intel/soc/stratix10/bl2_plat_setup.c | 23 ++++------ plat/intel/soc/stratix10/bl31_plat_setup.c | 9 +--- plat/intel/soc/stratix10/platform.mk | 55 +++++++++++------------ 9 files changed, 51 insertions(+), 80 deletions(-) diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index ece7b9c70..86b7ab88f 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -14,14 +14,12 @@ #include #include #include -#include #include "agilex_clock_manager.h" #include "agilex_memory_controller.h" #include "agilex_pinmux.h" #include "agilex_reset_manager.h" #include "agilex_system_manager.h" - #include "ccu/ncore_ccu.h" #include "qspi/cadence_qspi.h" #include "socfpga_handoff.h" diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c index e7852cfab..375483dd4 100644 --- a/plat/intel/soc/agilex/bl31_plat_setup.c +++ b/plat/intel/soc/agilex/bl31_plat_setup.c @@ -12,7 +12,6 @@ #include #include #include -#include static entry_point_info_t bl32_image_ep_info; @@ -104,7 +103,7 @@ const mmap_region_t plat_agilex_mmap[] = { MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS), - {0}, + {0} }; /******************************************************************************* @@ -126,7 +125,7 @@ void bl31_plat_arch_setup(void) BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE), #endif - {0}, + {0} }; setup_page_tables(bl_regions, plat_agilex_mmap); diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index dc56ac8ba..ef02a8dfb 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -4,7 +4,7 @@ # # SPDX-License-Identifier: BSD-3-Clause # -# + PLAT_INCLUDES := \ -Iplat/intel/soc/agilex/include/ \ -Iplat/intel/soc/common/drivers/ \ @@ -25,28 +25,26 @@ PLAT_BL_COMMON_SOURCES := \ BL2_SOURCES += \ common/desc_image_load.c \ - drivers/partition/partition.c \ - drivers/partition/gpt.c \ - drivers/arm/pl061/pl061_gpio.c \ drivers/mmc/mmc.c \ - drivers/synopsys/emmc/dw_mmc.c \ + drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ drivers/io/io_storage.c \ drivers/io/io_block.c \ drivers/io/io_fip.c \ - drivers/gpio/gpio.c \ - drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ + drivers/partition/partition.c \ + drivers/partition/gpt.c \ + drivers/synopsys/emmc/dw_mmc.c \ lib/cpus/aarch64/cortex_a53.S \ plat/intel/soc/agilex/bl2_plat_setup.c \ - plat/intel/soc/common/socfpga_storage.c \ - plat/intel/soc/common/bl2_plat_mem_params_desc.c \ - plat/intel/soc/agilex/soc/agilex_reset_manager.c \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ - plat/intel/soc/agilex/soc/agilex_pinmux.c \ plat/intel/soc/agilex/soc/agilex_memory_controller.c \ - plat/intel/soc/common/soc/socfpga_handoff.c \ + plat/intel/soc/agilex/soc/agilex_pinmux.c \ + plat/intel/soc/agilex/soc/agilex_reset_manager.c \ + plat/intel/soc/agilex/soc/agilex_system_manager.c \ + plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/socfpga_image_load.c \ - plat/intel/soc/agilex/soc/agilex_system_manager.c \ + plat/intel/soc/common/socfpga_storage.c \ + plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c \ @@ -54,18 +52,14 @@ BL2_SOURCES += \ BL31_SOURCES += \ drivers/arm/cci/cci.c \ - lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ - plat/intel/soc/common/socfpga_sip_svc.c \ plat/intel/soc/agilex/bl31_plat_setup.c \ plat/intel/soc/common/socfpga_psci.c \ + plat/intel/soc/common/socfpga_sip_svc.c \ plat/intel/soc/common/socfpga_topology.c \ - plat/intel/soc/common/socfpga_delay_timer.c \ - plat/intel/soc/agilex/soc/agilex_reset_manager.c \ - plat/intel/soc/agilex/soc/agilex_pinmux.c \ - plat/intel/soc/agilex/soc/agilex_clock_manager.c \ - plat/intel/soc/common/soc/socfpga_mailbox.c + plat/intel/soc/common/soc/socfpga_mailbox.c \ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c index ac8218ecd..fce816b65 100644 --- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c +++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c @@ -10,7 +10,6 @@ #include #include "ncore_ccu.h" -#include uint32_t poll_active_bit(uint32_t dir); diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c index 0fd11ec78..d7cd71bec 100644 --- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c +++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c @@ -13,7 +13,6 @@ #include #include "cadence_qspi.h" -#include #define LESS(a, b) (((a) < (b)) ? (a) : (b)) #define MORE(a, b) (((a) > (b)) ? (a) : (b)) diff --git a/plat/intel/soc/common/drivers/wdt/watchdog.c b/plat/intel/soc/common/drivers/wdt/watchdog.c index 0f89b4fd3..651189b12 100644 --- a/plat/intel/soc/common/drivers/wdt/watchdog.c +++ b/plat/intel/soc/common/drivers/wdt/watchdog.c @@ -6,7 +6,6 @@ #include #include -#include #include "watchdog.h" diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 7376b4143..85a60d651 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -1,36 +1,29 @@ /* * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include #include -#include - -#include -#include -#include #include #include #include -#include -#include -#include -#include -#include +#include #include -#include +#include #include -#include "s10_memory_controller.h" -#include "s10_reset_manager.h" -#include "s10_clock_manager.h" -#include "s10_pinmux.h" #include "qspi/cadence_qspi.h" #include "socfpga_handoff.h" #include "socfpga_mailbox.h" #include "socfpga_private.h" +#include "s10_clock_manager.h" +#include "s10_memory_controller.h" +#include "s10_pinmux.h" +#include "s10_reset_manager.h" +#include "s10_system_manager.h" #include "wdt/watchdog.h" diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 9887cb1d5..a133f82cb 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -1,21 +1,16 @@ /* * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#include #include #include +#include #include -#include -#include -#include -#include #include #include -#include -#include #include #include #include diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 5bf8f6555..e7251c428 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -1,5 +1,6 @@ # # Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2019, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -10,60 +11,54 @@ PLAT_INCLUDES := \ -Iplat/intel/soc/common/include/ PLAT_BL_COMMON_SOURCES := \ - lib/xlat_tables/xlat_tables_common.c \ - lib/xlat_tables/aarch64/xlat_tables.c \ drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/v2/gicv2_helpers.c \ - plat/common/plat_gicv2.c \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ drivers/ti/uart/aarch64/16550_console.S \ + lib/xlat_tables/aarch64/xlat_tables.c \ + lib/xlat_tables/xlat_tables_common.c \ + plat/common/plat_gicv2.c \ plat/intel/soc/common/aarch64/platform_common.c \ plat/intel/soc/common/aarch64/plat_helpers.S BL2_SOURCES += \ - drivers/partition/partition.c \ - drivers/partition/gpt.c \ - drivers/arm/pl061/pl061_gpio.c \ + common/desc_image_load.c \ drivers/mmc/mmc.c \ - drivers/synopsys/emmc/dw_mmc.c \ + drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ drivers/io/io_storage.c \ drivers/io/io_block.c \ drivers/io/io_fip.c \ - drivers/gpio/gpio.c \ - drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ + drivers/partition/partition.c \ + drivers/partition/gpt.c \ + drivers/synopsys/emmc/dw_mmc.c \ + lib/cpus/aarch64/cortex_a53.S \ plat/intel/soc/stratix10/bl2_plat_setup.c \ - plat/intel/soc/common/socfpga_storage.c \ - plat/intel/soc/common/bl2_plat_mem_params_desc.c \ - plat/intel/soc/stratix10/soc/s10_reset_manager.c \ - plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/stratix10/soc/s10_clock_manager.c \ - plat/intel/soc/stratix10/soc/s10_pinmux.c \ plat/intel/soc/stratix10/soc/s10_memory_controller.c \ + plat/intel/soc/stratix10/soc/s10_pinmux.c \ + plat/intel/soc/stratix10/soc/s10_reset_manager.c \ + plat/intel/soc/stratix10/soc/s10_system_manager.c \ + plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/common/socfpga_delay_timer.c \ - lib/cpus/aarch64/cortex_a53.S \ plat/intel/soc/common/socfpga_image_load.c \ - plat/intel/soc/stratix10/soc/s10_system_manager.c \ - common/desc_image_load.c \ + plat/intel/soc/common/socfpga_storage.c \ + plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c -BL31_SOURCES += drivers/arm/cci/cci.c \ +BL31_SOURCES += \ + drivers/arm/cci/cci.c \ + lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ - lib/cpus/aarch64/aem_generic.S \ - lib/cpus/aarch64/cortex_a53.S \ - plat/common/plat_psci_common.c \ - plat/intel/soc/common/socfpga_sip_svc.c \ - plat/intel/soc/stratix10/bl31_plat_setup.c \ - plat/intel/soc/common/socfpga_psci.c \ - plat/intel/soc/common/socfpga_topology.c \ - plat/intel/soc/common/socfpga_delay_timer.c \ - plat/intel/soc/stratix10/soc/s10_reset_manager.c\ - plat/intel/soc/stratix10/soc/s10_pinmux.c \ - plat/intel/soc/stratix10/soc/s10_clock_manager.c\ - plat/intel/soc/common/soc/socfpga_mailbox.c + plat/common/plat_psci_common.c \ + plat/intel/soc/stratix10/bl31_plat_setup.c \ + plat/intel/soc/common/socfpga_psci.c \ + plat/intel/soc/common/socfpga_sip_svc.c \ + plat/intel/soc/common/socfpga_topology.c \ + plat/intel/soc/common/soc/socfpga_mailbox.c \ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 -- cgit v1.2.3 From 14105374e5afa1af6e94396bc337ade0b926afe8 Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Mon, 23 Jan 2017 16:15:44 -0800 Subject: Tegra194: Support for cpu suspend This patch adds support for cpu suspend in T19x soc. Change-Id: I8ef1d3e03ee9c528dec34eaff6dcbbfa43941484 Signed-off-by: Krishna Sitaraman --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index e53d5946e..59131b3d2 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -39,7 +39,7 @@ extern uint32_t __tegra186_cpu_reset_handler_data, #define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 #define TEGRA186_WAKE_TIME_SHIFT 4 /* default core wake mask for CPU_SUSPEND */ -#define TEGRA186_CORE_WAKE_MASK 0x180c +#define TEGRA194_CORE_WAKE_MASK 0x180c /* context size to save during system suspend */ #define TEGRA186_SE_CONTEXT_SIZE 3 @@ -97,6 +97,7 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) #endif uint32_t val; mce_cstate_info_t cstate_info = { 0 }; + int cpu = plat_my_core_pos(); /* get the state ID */ pwr_domain_state = target_state->pwr_domain_state; @@ -109,6 +110,10 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { /* Enter CPU idle/powerdown */ + val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? + TEGRA_NVG_CORE_C6 : TEGRA_NVG_CORE_C7; + (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val, + percpu_data[cpu].wake_time, 0); } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { @@ -173,6 +178,7 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, plat_local_state_t target = *states; int cluster_powerdn = 1; int core_pos = read_mpidr() & MPIDR_CPU_MASK; + mce_cstate_info_t cstate_info = { 0 }; /* get the current core's power state */ target = *(states + core_pos); @@ -181,8 +187,9 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) { /* Program default wake mask */ - - /* Check if CCx state is allowed. */ + cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; + cstate_info.update_wake_mask = 1; + mce_update_cstate_info(&cstate_info); } /* CPU off */ -- cgit v1.2.3 From 719fdb6efc009e8ffdb65d507ed44d7bae28cd88 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 31 May 2017 11:41:00 -0700 Subject: Tegra194: platform support for memctrl/smmu drivers This patch adds platform support for the Memory Controller and SMMU drivers, for the Tegra194 SoC. Change-Id: Id8b482de70f1f93bedbca8d124575c39b469927f Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra_def.h | 137 +++++ .../soc/t194/drivers/include/memctrl_plat_config.h | 586 --------------------- .../soc/t194/drivers/include/smmu_plat_config.h | 428 --------------- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 318 +++++++++++ plat/nvidia/tegra/soc/t194/plat_smmu.c | 413 +++++++++++++++ plat/nvidia/tegra/soc/t194/platform_t194.mk | 4 +- 6 files changed, 871 insertions(+), 1015 deletions(-) delete mode 100644 plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h delete mode 100644 plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h create mode 100644 plat/nvidia/tegra/soc/t194/plat_memctrl.c create mode 100644 plat/nvidia/tegra/soc/t194/plat_smmu.c diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 79d776f55..300db8135 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -235,4 +235,141 @@ #define TEGRA_GPU_RESET_REG_OFFSET 0x18UL #define GPU_RESET_BIT (1UL << 0) +/******************************************************************************* + * Stream ID Override Config registers + ******************************************************************************/ +#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U +#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U +#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U +#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U +#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U +#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U +#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U +#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U +#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U +#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U +#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U +#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5E0U +#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5E8U +#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5F0U +#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5F8U +#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U +#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U +#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U +#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U +#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U +#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U +#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U +#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U +#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6A0U +#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6A8U +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6B0U +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6B8U +#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6C0U +#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6C8U +#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6D0U +#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6D8U +#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6E0U +#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6E8U +#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6F0U +#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6F8U +#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U +#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U +#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U +#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U +#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U +#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U +#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U +#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U +#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U +#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U +#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7C8U +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7D0U +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7D8U + +/******************************************************************************* + * Memory Controller transaction override config registers + ******************************************************************************/ +#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530 +#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538 +#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540 +#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548 +#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570 +#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578 +#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580 +#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158C +#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15E4 +#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15EC +#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15F4 +#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15FC +#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604 +#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160C +#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614 +#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161C +#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624 +#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162C +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634 +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163C +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644 +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164C +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654 +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165C +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664 +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166C +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674 +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167C +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684 +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168C +#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694 +#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169C +#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16A4 +#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16AC +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16B4 +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16BC +#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16C4 +#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16CC +#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16D4 +#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16DC +#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16E4 +#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16EC +#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16F4 +#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16FC +#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704 +#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170C +#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714 +#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171C +#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724 +#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174C +#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754 +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175C +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764 +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176C +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774 +#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177C +#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784 +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178C +#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794 +#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179C +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17CC +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4 +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC + #endif /* __TEGRA_DEF_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h b/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h deleted file mode 100644 index 8eaae678a..000000000 --- a/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h +++ /dev/null @@ -1,586 +0,0 @@ -/* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __MEMCTRL_PLAT_CONFIG_H -#define __MEMCTRL_PLAT_CONFIG_H - -#include - -/******************************************************************************* - * StreamID to indicate no SMMU translations (requests to be steered on the - * SMMU bypass path) - ******************************************************************************/ -#define MC_STREAM_ID_MAX 0x7F - -/******************************************************************************* - * Stream ID Override Config registers - ******************************************************************************/ -#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000 -#define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8 -#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0 -#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0 -#define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8 -#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138 -#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158 -#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8 -#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8 -#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 -#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220 -#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228 -#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230 -#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238 -#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250 -#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258 -#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260 -#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268 -#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0 -#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8 -#define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0 /*TODO: remove it after HW team confirmation */ -#define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8 /*TODO: remove it after HW team confirmation */ -#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300 -#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310 -#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318 -#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320 -#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330 -#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338 -#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360 -#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368 -#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390 -#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0 -#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8 -#define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0 -#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8 -#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0 -#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8 -#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400 -#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408 -#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410 -#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418 -#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420 -#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428 -#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430 -#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438 -#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440 /*TODO: remove it after HW team confirmation */ -#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448 /*TODO: remove it after HW team confirmation */ -#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460 -#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468 -#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470 -#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478 -#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480 -#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488 -#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490 -#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498 -#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0 -#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8 -#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0 -#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8 -#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0 -#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8 -#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0 -#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8 -#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0 -#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8 -#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0 -#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8 -#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500 -#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508 -#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510 -#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518 -#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530 -#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538 -#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540 -#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548 -#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570 -#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578 -#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580 -#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588 -#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5E0 -#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5E8 -#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5F0 -#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5F8 -#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600 -#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608 -#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610 -#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618 -#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620 -#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628 -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630 -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638 -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640 -#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648 -#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650 -#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658 -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660 -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668 -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670 -#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678 -#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680 -#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688 -#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690 -#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698 -#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6A0 -#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6A8 -#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6B0 -#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6B8 -#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6C0 -#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6C8 -#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6D0 -#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6D8 -#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6E0 -#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6E8 -#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6F0 -#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6F8 -#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700 -#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708 -#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710 -#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718 -#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720 -#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748 -#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750 -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758 -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760 -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768 -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770 -#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778 -#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780 -#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788 -#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790 -#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798 -#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7C8 -#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7D0 -#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7D8 - -/******************************************************************************* - * Macro to calculate Security cfg register addr from StreamID Override register - ******************************************************************************/ -#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t)) - -/******************************************************************************* - * Memory Controller transaction override config registers - ******************************************************************************/ -#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8 -#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0 -#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000 -#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490 -#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478 -#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8 -#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220 -#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360 -#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8 -#define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0 -#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460 -#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0 -#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330 -#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470 -#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8 -#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0 -#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318 -#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510 -#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8 -#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390 -#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468 -#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260 -#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480 -#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8 -#define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8 -#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8 -#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258 -#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438 -#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440 -#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8 -#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448 -#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0 -#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500 -#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0 -#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0 -#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420 -#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408 -#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0 -#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0 -#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430 -#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0 -#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0 -#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518 -#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250 -#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230 -#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400 -#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8 -#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8 -#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138 -#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320 -#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8 -#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8 -#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488 -#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8 -#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8 -#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428 -#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368 -#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158 -#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338 -#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300 -#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508 -#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238 -#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498 -#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8 -#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310 -#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268 -#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0 -#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0 -#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530 -#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538 -#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540 -#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548 -#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570 -#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578 -#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580 -#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158C -#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15E4 -#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15EC -#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15F4 -#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15FC -#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604 -#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160C -#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614 -#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161C -#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624 -#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162C -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634 -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163C -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644 -#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164C -#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654 -#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165C -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664 -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166C -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674 -#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167C -#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684 -#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168C -#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694 -#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169C -#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16A4 -#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16AC -#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16B4 -#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16BC -#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16C4 -#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16CC -#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16D4 -#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16DC -#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16E4 -#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16EC -#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16F4 -#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16FC -#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704 -#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170C -#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714 -#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171C -#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724 -#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174C -#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754 -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175C -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764 -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176C -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774 -#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177C -#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784 -#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178C -#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794 -#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179C -#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17CC -#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4 -#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC - -/******************************************************************************* - * Array to hold stream_id override config register offsets - ******************************************************************************/ -const static uint32_t mc_streamid_override_regs[] = { - MC_STREAMID_OVERRIDE_CFG_HDAR, - MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, - MC_STREAMID_OVERRIDE_CFG_NVENCSRD, - MC_STREAMID_OVERRIDE_CFG_SATAR, - MC_STREAMID_OVERRIDE_CFG_NVENCSWR, - MC_STREAMID_OVERRIDE_CFG_HDAW, - MC_STREAMID_OVERRIDE_CFG_SATAW, - MC_STREAMID_OVERRIDE_CFG_ISPRA, - MC_STREAMID_OVERRIDE_CFG_ISPFALR, - MC_STREAMID_OVERRIDE_CFG_ISPWA, - MC_STREAMID_OVERRIDE_CFG_ISPWB, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, - MC_STREAMID_OVERRIDE_CFG_TSECSRD, - MC_STREAMID_OVERRIDE_CFG_TSECSWR, - MC_STREAMID_OVERRIDE_CFG_SDMMCRA, - MC_STREAMID_OVERRIDE_CFG_SDMMCR, - MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, - MC_STREAMID_OVERRIDE_CFG_SDMMCWA, - MC_STREAMID_OVERRIDE_CFG_SDMMCW, - MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, - MC_STREAMID_OVERRIDE_CFG_VICSRD, - MC_STREAMID_OVERRIDE_CFG_VICSWR, - MC_STREAMID_OVERRIDE_CFG_VIW, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD, - MC_STREAMID_OVERRIDE_CFG_NVDECSWR, - MC_STREAMID_OVERRIDE_CFG_APER, - MC_STREAMID_OVERRIDE_CFG_APEW, - MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, - MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, - MC_STREAMID_OVERRIDE_CFG_SESRD, - MC_STREAMID_OVERRIDE_CFG_SESWR, - MC_STREAMID_OVERRIDE_CFG_AXIAPR, - MC_STREAMID_OVERRIDE_CFG_AXIAPW, - MC_STREAMID_OVERRIDE_CFG_ETRR, - MC_STREAMID_OVERRIDE_CFG_ETRW, - MC_STREAMID_OVERRIDE_CFG_TSECSRDB, - MC_STREAMID_OVERRIDE_CFG_TSECSWRB, - MC_STREAMID_OVERRIDE_CFG_AXISR, - MC_STREAMID_OVERRIDE_CFG_AXISW, - MC_STREAMID_OVERRIDE_CFG_EQOSR, - MC_STREAMID_OVERRIDE_CFG_EQOSW, - MC_STREAMID_OVERRIDE_CFG_UFSHCR, - MC_STREAMID_OVERRIDE_CFG_UFSHCW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, - MC_STREAMID_OVERRIDE_CFG_BPMPR, - MC_STREAMID_OVERRIDE_CFG_BPMPW, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, - MC_STREAMID_OVERRIDE_CFG_AONR, - MC_STREAMID_OVERRIDE_CFG_AONW, - MC_STREAMID_OVERRIDE_CFG_AONDMAR, - MC_STREAMID_OVERRIDE_CFG_AONDMAW, - MC_STREAMID_OVERRIDE_CFG_SCER, - MC_STREAMID_OVERRIDE_CFG_SCEW, - MC_STREAMID_OVERRIDE_CFG_SCEDMAR, - MC_STREAMID_OVERRIDE_CFG_SCEDMAW, - MC_STREAMID_OVERRIDE_CFG_APEDMAR, - MC_STREAMID_OVERRIDE_CFG_APEDMAW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, - MC_STREAMID_OVERRIDE_CFG_VICSRD1, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, - MC_STREAMID_OVERRIDE_CFG_VIFALR, - MC_STREAMID_OVERRIDE_CFG_VIFALW, - MC_STREAMID_OVERRIDE_CFG_DLA0RDA, - MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, - MC_STREAMID_OVERRIDE_CFG_DLA0WRA, - MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, - MC_STREAMID_OVERRIDE_CFG_DLA1RDA, - MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, - MC_STREAMID_OVERRIDE_CFG_DLA1WRA, - MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, - MC_STREAMID_OVERRIDE_CFG_PVA0RDA, - MC_STREAMID_OVERRIDE_CFG_PVA0RDB, - MC_STREAMID_OVERRIDE_CFG_PVA0RDC, - MC_STREAMID_OVERRIDE_CFG_PVA0WRA, - MC_STREAMID_OVERRIDE_CFG_PVA0WRB, - MC_STREAMID_OVERRIDE_CFG_PVA0WRC, - MC_STREAMID_OVERRIDE_CFG_PVA1RDA, - MC_STREAMID_OVERRIDE_CFG_PVA1RDB, - MC_STREAMID_OVERRIDE_CFG_PVA1RDC, - MC_STREAMID_OVERRIDE_CFG_PVA1WRA, - MC_STREAMID_OVERRIDE_CFG_PVA1WRB, - MC_STREAMID_OVERRIDE_CFG_PVA1WRC, - MC_STREAMID_OVERRIDE_CFG_RCER, - MC_STREAMID_OVERRIDE_CFG_RCEW, - MC_STREAMID_OVERRIDE_CFG_RCEDMAR, - MC_STREAMID_OVERRIDE_CFG_RCEDMAW, - MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, - MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, - MC_STREAMID_OVERRIDE_CFG_PCIE0R, - MC_STREAMID_OVERRIDE_CFG_PCIE0W, - MC_STREAMID_OVERRIDE_CFG_PCIE1R, - MC_STREAMID_OVERRIDE_CFG_PCIE1W, - MC_STREAMID_OVERRIDE_CFG_PCIE2AR, - MC_STREAMID_OVERRIDE_CFG_PCIE2AW, - MC_STREAMID_OVERRIDE_CFG_PCIE3R, - MC_STREAMID_OVERRIDE_CFG_PCIE3W, - MC_STREAMID_OVERRIDE_CFG_PCIE4R, - MC_STREAMID_OVERRIDE_CFG_PCIE4W, - MC_STREAMID_OVERRIDE_CFG_PCIE5R, - MC_STREAMID_OVERRIDE_CFG_PCIE5W, - MC_STREAMID_OVERRIDE_CFG_ISPFALW, - MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, - MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, - MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, - MC_STREAMID_OVERRIDE_CFG_PCIE5R1, - MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, - MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, - MC_STREAMID_OVERRIDE_CFG_ISPRA1, - MC_STREAMID_OVERRIDE_CFG_MIU0R, - MC_STREAMID_OVERRIDE_CFG_MIU0W, - MC_STREAMID_OVERRIDE_CFG_MIU1R, - MC_STREAMID_OVERRIDE_CFG_MIU1W, - MC_STREAMID_OVERRIDE_CFG_MIU2R, - MC_STREAMID_OVERRIDE_CFG_MIU2W, - MC_STREAMID_OVERRIDE_CFG_MIU3R, - MC_STREAMID_OVERRIDE_CFG_MIU3W -}; - -/******************************************************************************* - * Array to hold the security configs for stream IDs - ******************************************************************************/ -const static mc_streamid_security_cfg_t mc_streamid_sec_cfgs[] = { - mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), - mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), - mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE), -}; - -/******************************************************************************* - * Array to hold the transaction override configs - ******************************************************************************/ -const static mc_txn_override_cfg_t mc_txn_override_cfgs[] = { - mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR), - mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR), - mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR), - mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR), - mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR), - mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(APEW, CGID_TAG_ADR), - mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR), - mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR), - mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR), - mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR), - mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR), - mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR), - mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(AONW, CGID_TAG_ADR), - mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR), -}; - -#endif //__MEMCTRL_PLAT_CONFIG_H diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h b/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h deleted file mode 100644 index fc8669a0d..000000000 --- a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h +++ /dev/null @@ -1,428 +0,0 @@ -/* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __SMMU_PLAT_CONFIG_H -#define __SMMU_PLAT_CONFIG_H - -#include -#include -#include - -static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = { - _START_OF_TABLE_, - mc_make_sid_security_cfg(HDAR), - mc_make_sid_security_cfg(HOST1XDMAR), - mc_make_sid_security_cfg(NVENCSRD), - mc_make_sid_security_cfg(SATAR), - mc_make_sid_security_cfg(NVENCSWR), - mc_make_sid_security_cfg(HDAW), - mc_make_sid_security_cfg(SATAW), - mc_make_sid_security_cfg(ISPRA), - mc_make_sid_security_cfg(ISPFALR), - mc_make_sid_security_cfg(ISPWA), - mc_make_sid_security_cfg(ISPWB), - mc_make_sid_security_cfg(XUSB_HOSTR), - mc_make_sid_security_cfg(XUSB_HOSTW), - mc_make_sid_security_cfg(XUSB_DEVR), - mc_make_sid_security_cfg(XUSB_DEVW), - mc_make_sid_security_cfg(TSECSRD), - mc_make_sid_security_cfg(TSECSWR), - mc_make_sid_security_cfg(SDMMCRA), - mc_make_sid_security_cfg(SDMMCR), - mc_make_sid_security_cfg(SDMMCRAB), - mc_make_sid_security_cfg(SDMMCWA), - mc_make_sid_security_cfg(SDMMCW), - mc_make_sid_security_cfg(SDMMCWAB), - mc_make_sid_security_cfg(VICSRD), - mc_make_sid_security_cfg(VICSWR), - mc_make_sid_security_cfg(VIW), - mc_make_sid_security_cfg(NVDECSRD), - mc_make_sid_security_cfg(NVDECSWR), - mc_make_sid_security_cfg(APER), - mc_make_sid_security_cfg(APEW), - mc_make_sid_security_cfg(NVJPGSRD), - mc_make_sid_security_cfg(NVJPGSWR), - mc_make_sid_security_cfg(SESRD), - mc_make_sid_security_cfg(SESWR), - mc_make_sid_security_cfg(AXIAPR), - mc_make_sid_security_cfg(AXIAPW), - mc_make_sid_security_cfg(ETRR), - mc_make_sid_security_cfg(ETRW), - mc_make_sid_security_cfg(TSECSRDB), - mc_make_sid_security_cfg(TSECSWRB), - mc_make_sid_security_cfg(AXISR), - mc_make_sid_security_cfg(AXISW), - mc_make_sid_security_cfg(EQOSR), - mc_make_sid_security_cfg(EQOSW), - mc_make_sid_security_cfg(UFSHCR), - mc_make_sid_security_cfg(UFSHCW), - mc_make_sid_security_cfg(NVDISPLAYR), - mc_make_sid_security_cfg(BPMPR), - mc_make_sid_security_cfg(BPMPW), - mc_make_sid_security_cfg(BPMPDMAR), - mc_make_sid_security_cfg(BPMPDMAW), - mc_make_sid_security_cfg(AONR), - mc_make_sid_security_cfg(AONW), - mc_make_sid_security_cfg(AONDMAR), - mc_make_sid_security_cfg(AONDMAW), - mc_make_sid_security_cfg(SCER), - mc_make_sid_security_cfg(SCEW), - mc_make_sid_security_cfg(SCEDMAR), - mc_make_sid_security_cfg(SCEDMAW), - mc_make_sid_security_cfg(APEDMAR), - mc_make_sid_security_cfg(APEDMAW), - mc_make_sid_security_cfg(NVDISPLAYR1), - mc_make_sid_security_cfg(VICSRD1), - mc_make_sid_security_cfg(NVDECSRD1), - mc_make_sid_security_cfg(VIFALR), - mc_make_sid_security_cfg(VIFALW), - mc_make_sid_security_cfg(DLA0RDA), - mc_make_sid_security_cfg(DLA0FALRDB), - mc_make_sid_security_cfg(DLA0WRA), - mc_make_sid_security_cfg(DLA0FALWRB), - mc_make_sid_security_cfg(DLA1RDA), - mc_make_sid_security_cfg(DLA1FALRDB), - mc_make_sid_security_cfg(DLA1WRA), - mc_make_sid_security_cfg(DLA1FALWRB), - mc_make_sid_security_cfg(PVA0RDA), - mc_make_sid_security_cfg(PVA0RDB), - mc_make_sid_security_cfg(PVA0RDC), - mc_make_sid_security_cfg(PVA0WRA), - mc_make_sid_security_cfg(PVA0WRB), - mc_make_sid_security_cfg(PVA0WRC), - mc_make_sid_security_cfg(PVA1RDA), - mc_make_sid_security_cfg(PVA1RDB), - mc_make_sid_security_cfg(PVA1RDC), - mc_make_sid_security_cfg(PVA1WRA), - mc_make_sid_security_cfg(PVA1WRB), - mc_make_sid_security_cfg(PVA1WRC), - mc_make_sid_security_cfg(RCER), - mc_make_sid_security_cfg(RCEW), - mc_make_sid_security_cfg(RCEDMAR), - mc_make_sid_security_cfg(RCEDMAW), - mc_make_sid_security_cfg(NVENC1SRD), - mc_make_sid_security_cfg(NVENC1SWR), - mc_make_sid_security_cfg(PCIE0R), - mc_make_sid_security_cfg(PCIE0W), - mc_make_sid_security_cfg(PCIE1R), - mc_make_sid_security_cfg(PCIE1W), - mc_make_sid_security_cfg(PCIE2AR), - mc_make_sid_security_cfg(PCIE2AW), - mc_make_sid_security_cfg(PCIE3R), - mc_make_sid_security_cfg(PCIE3W), - mc_make_sid_security_cfg(PCIE4R), - mc_make_sid_security_cfg(PCIE4W), - mc_make_sid_security_cfg(PCIE5R), - mc_make_sid_security_cfg(PCIE5W), - mc_make_sid_security_cfg(ISPFALW), - mc_make_sid_security_cfg(DLA0RDA1), - mc_make_sid_security_cfg(DLA1RDA1), - mc_make_sid_security_cfg(PVA0RDA1), - mc_make_sid_security_cfg(PVA0RDB1), - mc_make_sid_security_cfg(PVA1RDA1), - mc_make_sid_security_cfg(PVA1RDB1), - mc_make_sid_security_cfg(PCIE5R1), - mc_make_sid_security_cfg(NVENCSRD1), - mc_make_sid_security_cfg(NVENC1SRD1), - mc_make_sid_security_cfg(ISPRA1), - mc_make_sid_security_cfg(MIU0R), - mc_make_sid_security_cfg(MIU0W), - mc_make_sid_security_cfg(MIU1R), - mc_make_sid_security_cfg(MIU1W), - mc_make_sid_security_cfg(MIU2R), - mc_make_sid_security_cfg(MIU2W), - mc_make_sid_security_cfg(MIU3R), - mc_make_sid_security_cfg(MIU3W), - mc_make_sid_override_cfg(HDAR), - mc_make_sid_override_cfg(HOST1XDMAR), - mc_make_sid_override_cfg(NVENCSRD), - mc_make_sid_override_cfg(SATAR), - mc_make_sid_override_cfg(NVENCSWR), - mc_make_sid_override_cfg(HDAW), - mc_make_sid_override_cfg(SATAW), - mc_make_sid_override_cfg(ISPRA), - mc_make_sid_override_cfg(ISPFALR), - mc_make_sid_override_cfg(ISPWA), - mc_make_sid_override_cfg(ISPWB), - mc_make_sid_override_cfg(XUSB_HOSTR), - mc_make_sid_override_cfg(XUSB_HOSTW), - mc_make_sid_override_cfg(XUSB_DEVR), - mc_make_sid_override_cfg(XUSB_DEVW), - mc_make_sid_override_cfg(TSECSRD), - mc_make_sid_override_cfg(TSECSWR), - mc_make_sid_override_cfg(SDMMCRA), - mc_make_sid_override_cfg(SDMMCR), - mc_make_sid_override_cfg(SDMMCRAB), - mc_make_sid_override_cfg(SDMMCWA), - mc_make_sid_override_cfg(SDMMCW), - mc_make_sid_override_cfg(SDMMCWAB), - mc_make_sid_override_cfg(VICSRD), - mc_make_sid_override_cfg(VICSWR), - mc_make_sid_override_cfg(VIW), - mc_make_sid_override_cfg(NVDECSRD), - mc_make_sid_override_cfg(NVDECSWR), - mc_make_sid_override_cfg(APER), - mc_make_sid_override_cfg(APEW), - mc_make_sid_override_cfg(NVJPGSRD), - mc_make_sid_override_cfg(NVJPGSWR), - mc_make_sid_override_cfg(SESRD), - mc_make_sid_override_cfg(SESWR), - mc_make_sid_override_cfg(AXIAPR), - mc_make_sid_override_cfg(AXIAPW), - mc_make_sid_override_cfg(ETRR), - mc_make_sid_override_cfg(ETRW), - mc_make_sid_override_cfg(TSECSRDB), - mc_make_sid_override_cfg(TSECSWRB), - mc_make_sid_override_cfg(AXISR), - mc_make_sid_override_cfg(AXISW), - mc_make_sid_override_cfg(EQOSR), - mc_make_sid_override_cfg(EQOSW), - mc_make_sid_override_cfg(UFSHCR), - mc_make_sid_override_cfg(UFSHCW), - mc_make_sid_override_cfg(NVDISPLAYR), - mc_make_sid_override_cfg(BPMPR), - mc_make_sid_override_cfg(BPMPW), - mc_make_sid_override_cfg(BPMPDMAR), - mc_make_sid_override_cfg(BPMPDMAW), - mc_make_sid_override_cfg(AONR), - mc_make_sid_override_cfg(AONW), - mc_make_sid_override_cfg(AONDMAR), - mc_make_sid_override_cfg(AONDMAW), - mc_make_sid_override_cfg(SCER), - mc_make_sid_override_cfg(SCEW), - mc_make_sid_override_cfg(SCEDMAR), - mc_make_sid_override_cfg(SCEDMAW), - mc_make_sid_override_cfg(APEDMAR), - mc_make_sid_override_cfg(APEDMAW), - mc_make_sid_override_cfg(NVDISPLAYR1), - mc_make_sid_override_cfg(VICSRD1), - mc_make_sid_override_cfg(NVDECSRD1), - mc_make_sid_override_cfg(VIFALR), - mc_make_sid_override_cfg(VIFALW), - mc_make_sid_override_cfg(DLA0RDA), - mc_make_sid_override_cfg(DLA0FALRDB), - mc_make_sid_override_cfg(DLA0WRA), - mc_make_sid_override_cfg(DLA0FALWRB), - mc_make_sid_override_cfg(DLA1RDA), - mc_make_sid_override_cfg(DLA1FALRDB), - mc_make_sid_override_cfg(DLA1WRA), - mc_make_sid_override_cfg(DLA1FALWRB), - mc_make_sid_override_cfg(PVA0RDA), - mc_make_sid_override_cfg(PVA0RDB), - mc_make_sid_override_cfg(PVA0RDC), - mc_make_sid_override_cfg(PVA0WRA), - mc_make_sid_override_cfg(PVA0WRB), - mc_make_sid_override_cfg(PVA0WRC), - mc_make_sid_override_cfg(PVA1RDA), - mc_make_sid_override_cfg(PVA1RDB), - mc_make_sid_override_cfg(PVA1RDC), - mc_make_sid_override_cfg(PVA1WRA), - mc_make_sid_override_cfg(PVA1WRB), - mc_make_sid_override_cfg(PVA1WRC), - mc_make_sid_override_cfg(RCER), - mc_make_sid_override_cfg(RCEW), - mc_make_sid_override_cfg(RCEDMAR), - mc_make_sid_override_cfg(RCEDMAW), - mc_make_sid_override_cfg(NVENC1SRD), - mc_make_sid_override_cfg(NVENC1SWR), - mc_make_sid_override_cfg(PCIE0R), - mc_make_sid_override_cfg(PCIE0W), - mc_make_sid_override_cfg(PCIE1R), - mc_make_sid_override_cfg(PCIE1W), - mc_make_sid_override_cfg(PCIE2AR), - mc_make_sid_override_cfg(PCIE2AW), - mc_make_sid_override_cfg(PCIE3R), - mc_make_sid_override_cfg(PCIE3W), - mc_make_sid_override_cfg(PCIE4R), - mc_make_sid_override_cfg(PCIE4W), - mc_make_sid_override_cfg(PCIE5R), - mc_make_sid_override_cfg(PCIE5W), - mc_make_sid_override_cfg(ISPFALW), - mc_make_sid_override_cfg(DLA0RDA1), - mc_make_sid_override_cfg(DLA1RDA1), - mc_make_sid_override_cfg(PVA0RDA1), - mc_make_sid_override_cfg(PVA0RDB1), - mc_make_sid_override_cfg(PVA1RDA1), - mc_make_sid_override_cfg(PVA1RDB1), - mc_make_sid_override_cfg(PCIE5R1), - mc_make_sid_override_cfg(NVENCSRD1), - mc_make_sid_override_cfg(NVENC1SRD1), - mc_make_sid_override_cfg(ISPRA1), - mc_make_sid_override_cfg(MIU0R), - mc_make_sid_override_cfg(MIU0W), - mc_make_sid_override_cfg(MIU1R), - mc_make_sid_override_cfg(MIU1W), - mc_make_sid_override_cfg(MIU2R), - mc_make_sid_override_cfg(MIU2W), - mc_make_sid_override_cfg(MIU3R), - mc_make_sid_override_cfg(MIU3W), - smmu_make_gnsr0_nsec_cfg(CR0), - smmu_make_gnsr0_sec_cfg(IDR0), - smmu_make_gnsr0_sec_cfg(IDR1), - smmu_make_gnsr0_sec_cfg(IDR2), - smmu_make_gnsr0_nsec_cfg(GFSR), - smmu_make_gnsr0_nsec_cfg(GFSYNR0), - smmu_make_gnsr0_nsec_cfg(GFSYNR1), - smmu_make_gnsr0_nsec_cfg(TLBGSTATUS), - smmu_make_gnsr0_nsec_cfg(PIDR2), - smmu_make_smrg_group(0), - smmu_make_smrg_group(1), - smmu_make_smrg_group(2), - smmu_make_smrg_group(3), - smmu_make_smrg_group(4), - smmu_make_smrg_group(5), - smmu_make_smrg_group(6), - smmu_make_smrg_group(7), - smmu_make_smrg_group(8), - smmu_make_smrg_group(9), - smmu_make_smrg_group(10), - smmu_make_smrg_group(11), - smmu_make_smrg_group(12), - smmu_make_smrg_group(13), - smmu_make_smrg_group(14), - smmu_make_smrg_group(15), - smmu_make_smrg_group(16), - smmu_make_smrg_group(17), - smmu_make_smrg_group(18), - smmu_make_smrg_group(19), - smmu_make_smrg_group(20), - smmu_make_smrg_group(21), - smmu_make_smrg_group(22), - smmu_make_smrg_group(23), - smmu_make_smrg_group(24), - smmu_make_smrg_group(25), - smmu_make_smrg_group(26), - smmu_make_smrg_group(27), - smmu_make_smrg_group(28), - smmu_make_smrg_group(29), - smmu_make_smrg_group(30), - smmu_make_smrg_group(31), - smmu_make_smrg_group(32), - smmu_make_smrg_group(33), - smmu_make_smrg_group(34), - smmu_make_smrg_group(35), - smmu_make_smrg_group(36), - smmu_make_smrg_group(37), - smmu_make_smrg_group(38), - smmu_make_smrg_group(39), - smmu_make_smrg_group(40), - smmu_make_smrg_group(41), - smmu_make_smrg_group(42), - smmu_make_smrg_group(43), - smmu_make_smrg_group(44), - smmu_make_smrg_group(45), - smmu_make_smrg_group(46), - smmu_make_smrg_group(47), - smmu_make_smrg_group(48), - smmu_make_smrg_group(49), - smmu_make_smrg_group(50), - smmu_make_smrg_group(51), - smmu_make_smrg_group(52), - smmu_make_smrg_group(53), - smmu_make_smrg_group(54), - smmu_make_smrg_group(55), - smmu_make_smrg_group(56), - smmu_make_smrg_group(57), - smmu_make_smrg_group(58), - smmu_make_smrg_group(59), - smmu_make_smrg_group(60), - smmu_make_smrg_group(61), - smmu_make_smrg_group(62), - smmu_make_smrg_group(63), - smmu_make_cb_group(0), - smmu_make_cb_group(1), - smmu_make_cb_group(2), - smmu_make_cb_group(3), - smmu_make_cb_group(4), - smmu_make_cb_group(5), - smmu_make_cb_group(6), - smmu_make_cb_group(7), - smmu_make_cb_group(8), - smmu_make_cb_group(9), - smmu_make_cb_group(10), - smmu_make_cb_group(11), - smmu_make_cb_group(12), - smmu_make_cb_group(13), - smmu_make_cb_group(14), - smmu_make_cb_group(15), - smmu_make_cb_group(16), - smmu_make_cb_group(17), - smmu_make_cb_group(18), - smmu_make_cb_group(19), - smmu_make_cb_group(20), - smmu_make_cb_group(21), - smmu_make_cb_group(22), - smmu_make_cb_group(23), - smmu_make_cb_group(24), - smmu_make_cb_group(25), - smmu_make_cb_group(26), - smmu_make_cb_group(27), - smmu_make_cb_group(28), - smmu_make_cb_group(29), - smmu_make_cb_group(30), - smmu_make_cb_group(31), - smmu_make_cb_group(32), - smmu_make_cb_group(33), - smmu_make_cb_group(34), - smmu_make_cb_group(35), - smmu_make_cb_group(36), - smmu_make_cb_group(37), - smmu_make_cb_group(38), - smmu_make_cb_group(39), - smmu_make_cb_group(40), - smmu_make_cb_group(41), - smmu_make_cb_group(42), - smmu_make_cb_group(43), - smmu_make_cb_group(44), - smmu_make_cb_group(45), - smmu_make_cb_group(46), - smmu_make_cb_group(47), - smmu_make_cb_group(48), - smmu_make_cb_group(49), - smmu_make_cb_group(50), - smmu_make_cb_group(51), - smmu_make_cb_group(52), - smmu_make_cb_group(53), - smmu_make_cb_group(54), - smmu_make_cb_group(55), - smmu_make_cb_group(56), - smmu_make_cb_group(57), - smmu_make_cb_group(58), - smmu_make_cb_group(59), - smmu_make_cb_group(60), - smmu_make_cb_group(61), - smmu_make_cb_group(62), - smmu_make_cb_group(63), - smmu_bypass_cfg, /* TBU settings */ - _END_OF_TABLE_, -}; - -static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off) -{ - if (smmu_id == 0) - return mmio_read_32(TEGRA_SMMU0_BASE + off); - else if (smmu_id == 1) - return mmio_read_32(TEGRA_SMMU1_BASE + off); - else if (smmu_id == 2) - return mmio_read_32(TEGRA_SMMU2_BASE + off); - else - panic(); -} - -static inline void tegra_smmu_write_32(uint32_t smmu_id, - uint32_t off, uint32_t val) -{ - if (smmu_id == 0) - mmio_write_32(TEGRA_SMMU0_BASE + off, val); - else if (smmu_id == 1) - mmio_write_32(TEGRA_SMMU1_BASE + off, val); - else if (smmu_id == 2) - mmio_write_32(TEGRA_SMMU2_BASE + off, val); - else - panic(); -} - -#endif //__SMMU_PLAT_CONFIG_H diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c new file mode 100644 index 000000000..a4c35e9a8 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +/******************************************************************************* + * Array to hold stream_id override config register offsets + ******************************************************************************/ +const static uint32_t tegra194_streamid_override_regs[] = { + MC_STREAMID_OVERRIDE_CFG_HDAR, + MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, + MC_STREAMID_OVERRIDE_CFG_NVENCSRD, + MC_STREAMID_OVERRIDE_CFG_SATAR, + MC_STREAMID_OVERRIDE_CFG_NVENCSWR, + MC_STREAMID_OVERRIDE_CFG_HDAW, + MC_STREAMID_OVERRIDE_CFG_SATAW, + MC_STREAMID_OVERRIDE_CFG_ISPRA, + MC_STREAMID_OVERRIDE_CFG_ISPFALR, + MC_STREAMID_OVERRIDE_CFG_ISPWA, + MC_STREAMID_OVERRIDE_CFG_ISPWB, + MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, + MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, + MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, + MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, + MC_STREAMID_OVERRIDE_CFG_TSECSRD, + MC_STREAMID_OVERRIDE_CFG_TSECSWR, + MC_STREAMID_OVERRIDE_CFG_SDMMCRA, + MC_STREAMID_OVERRIDE_CFG_SDMMCR, + MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, + MC_STREAMID_OVERRIDE_CFG_SDMMCWA, + MC_STREAMID_OVERRIDE_CFG_SDMMCW, + MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, + MC_STREAMID_OVERRIDE_CFG_VICSRD, + MC_STREAMID_OVERRIDE_CFG_VICSWR, + MC_STREAMID_OVERRIDE_CFG_VIW, + MC_STREAMID_OVERRIDE_CFG_NVDECSRD, + MC_STREAMID_OVERRIDE_CFG_NVDECSWR, + MC_STREAMID_OVERRIDE_CFG_APER, + MC_STREAMID_OVERRIDE_CFG_APEW, + MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, + MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, + MC_STREAMID_OVERRIDE_CFG_SESRD, + MC_STREAMID_OVERRIDE_CFG_SESWR, + MC_STREAMID_OVERRIDE_CFG_AXIAPR, + MC_STREAMID_OVERRIDE_CFG_AXIAPW, + MC_STREAMID_OVERRIDE_CFG_ETRR, + MC_STREAMID_OVERRIDE_CFG_ETRW, + MC_STREAMID_OVERRIDE_CFG_TSECSRDB, + MC_STREAMID_OVERRIDE_CFG_TSECSWRB, + MC_STREAMID_OVERRIDE_CFG_AXISR, + MC_STREAMID_OVERRIDE_CFG_AXISW, + MC_STREAMID_OVERRIDE_CFG_EQOSR, + MC_STREAMID_OVERRIDE_CFG_EQOSW, + MC_STREAMID_OVERRIDE_CFG_UFSHCR, + MC_STREAMID_OVERRIDE_CFG_UFSHCW, + MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, + MC_STREAMID_OVERRIDE_CFG_BPMPR, + MC_STREAMID_OVERRIDE_CFG_BPMPW, + MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, + MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, + MC_STREAMID_OVERRIDE_CFG_AONR, + MC_STREAMID_OVERRIDE_CFG_AONW, + MC_STREAMID_OVERRIDE_CFG_AONDMAR, + MC_STREAMID_OVERRIDE_CFG_AONDMAW, + MC_STREAMID_OVERRIDE_CFG_SCER, + MC_STREAMID_OVERRIDE_CFG_SCEW, + MC_STREAMID_OVERRIDE_CFG_SCEDMAR, + MC_STREAMID_OVERRIDE_CFG_SCEDMAW, + MC_STREAMID_OVERRIDE_CFG_APEDMAR, + MC_STREAMID_OVERRIDE_CFG_APEDMAW, + MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, + MC_STREAMID_OVERRIDE_CFG_VICSRD1, + MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, + MC_STREAMID_OVERRIDE_CFG_VIFALR, + MC_STREAMID_OVERRIDE_CFG_VIFALW, + MC_STREAMID_OVERRIDE_CFG_DLA0RDA, + MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, + MC_STREAMID_OVERRIDE_CFG_DLA0WRA, + MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, + MC_STREAMID_OVERRIDE_CFG_DLA1RDA, + MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, + MC_STREAMID_OVERRIDE_CFG_DLA1WRA, + MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, + MC_STREAMID_OVERRIDE_CFG_PVA0RDA, + MC_STREAMID_OVERRIDE_CFG_PVA0RDB, + MC_STREAMID_OVERRIDE_CFG_PVA0RDC, + MC_STREAMID_OVERRIDE_CFG_PVA0WRA, + MC_STREAMID_OVERRIDE_CFG_PVA0WRB, + MC_STREAMID_OVERRIDE_CFG_PVA0WRC, + MC_STREAMID_OVERRIDE_CFG_PVA1RDA, + MC_STREAMID_OVERRIDE_CFG_PVA1RDB, + MC_STREAMID_OVERRIDE_CFG_PVA1RDC, + MC_STREAMID_OVERRIDE_CFG_PVA1WRA, + MC_STREAMID_OVERRIDE_CFG_PVA1WRB, + MC_STREAMID_OVERRIDE_CFG_PVA1WRC, + MC_STREAMID_OVERRIDE_CFG_RCER, + MC_STREAMID_OVERRIDE_CFG_RCEW, + MC_STREAMID_OVERRIDE_CFG_RCEDMAR, + MC_STREAMID_OVERRIDE_CFG_RCEDMAW, + MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, + MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, + MC_STREAMID_OVERRIDE_CFG_PCIE0R, + MC_STREAMID_OVERRIDE_CFG_PCIE0W, + MC_STREAMID_OVERRIDE_CFG_PCIE1R, + MC_STREAMID_OVERRIDE_CFG_PCIE1W, + MC_STREAMID_OVERRIDE_CFG_PCIE2AR, + MC_STREAMID_OVERRIDE_CFG_PCIE2AW, + MC_STREAMID_OVERRIDE_CFG_PCIE3R, + MC_STREAMID_OVERRIDE_CFG_PCIE3W, + MC_STREAMID_OVERRIDE_CFG_PCIE4R, + MC_STREAMID_OVERRIDE_CFG_PCIE4W, + MC_STREAMID_OVERRIDE_CFG_PCIE5R, + MC_STREAMID_OVERRIDE_CFG_PCIE5W, + MC_STREAMID_OVERRIDE_CFG_ISPFALW, + MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, + MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, + MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, + MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, + MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, + MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, + MC_STREAMID_OVERRIDE_CFG_PCIE5R1, + MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, + MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, + MC_STREAMID_OVERRIDE_CFG_ISPRA1, + MC_STREAMID_OVERRIDE_CFG_MIU0R, + MC_STREAMID_OVERRIDE_CFG_MIU0W, + MC_STREAMID_OVERRIDE_CFG_MIU1R, + MC_STREAMID_OVERRIDE_CFG_MIU1W, + MC_STREAMID_OVERRIDE_CFG_MIU2R, + MC_STREAMID_OVERRIDE_CFG_MIU2W, + MC_STREAMID_OVERRIDE_CFG_MIU3R, + MC_STREAMID_OVERRIDE_CFG_MIU3W +}; + +/******************************************************************************* + * Array to hold the security configs for stream IDs + ******************************************************************************/ +const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { + mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), + mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), + mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE), +}; + +/******************************************************************************* + * Array to hold the transaction override configs + ******************************************************************************/ +const static mc_txn_override_cfg_t tegra194_txn_override_cfgs[] = { + mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR), + mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR), + mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR), + mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR), + mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR), + mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR), + mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR), + mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR), + mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(APEW, CGID_TAG_ADR), + mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR), + mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR), + mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR), + mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR), + mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR), + mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR), + mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR), + mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR), + mc_make_txn_override_cfg(AONW, CGID_TAG_ADR), + mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR), + mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR), + mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR), +}; + +/******************************************************************************* + * Struct to hold the memory controller settings + ******************************************************************************/ +static tegra_mc_settings_t tegra194_mc_settings = { + .streamid_override_cfg = tegra194_streamid_override_regs, + .num_streamid_override_cfgs = ARRAY_SIZE(tegra194_streamid_override_regs), + .streamid_security_cfg = tegra194_streamid_sec_cfgs, + .num_streamid_security_cfgs = ARRAY_SIZE(tegra194_streamid_sec_cfgs), + .txn_override_cfg = tegra194_txn_override_cfgs, + .num_txn_override_cfgs = ARRAY_SIZE(tegra194_txn_override_cfgs) +}; + +/******************************************************************************* + * Handler to return the pointer to the memory controller's settings struct + ******************************************************************************/ +tegra_mc_settings_t *tegra_get_mc_settings(void) +{ + return &tegra194_mc_settings; +} diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c new file mode 100644 index 000000000..2b82f24f5 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -0,0 +1,413 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +/******************************************************************************* + * Array to hold SMMU context for Tegra186 + ******************************************************************************/ +static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { + _START_OF_TABLE_, + mc_make_sid_security_cfg(HDAR), + mc_make_sid_security_cfg(HOST1XDMAR), + mc_make_sid_security_cfg(NVENCSRD), + mc_make_sid_security_cfg(SATAR), + mc_make_sid_security_cfg(NVENCSWR), + mc_make_sid_security_cfg(HDAW), + mc_make_sid_security_cfg(SATAW), + mc_make_sid_security_cfg(ISPRA), + mc_make_sid_security_cfg(ISPFALR), + mc_make_sid_security_cfg(ISPWA), + mc_make_sid_security_cfg(ISPWB), + mc_make_sid_security_cfg(XUSB_HOSTR), + mc_make_sid_security_cfg(XUSB_HOSTW), + mc_make_sid_security_cfg(XUSB_DEVR), + mc_make_sid_security_cfg(XUSB_DEVW), + mc_make_sid_security_cfg(TSECSRD), + mc_make_sid_security_cfg(TSECSWR), + mc_make_sid_security_cfg(SDMMCRA), + mc_make_sid_security_cfg(SDMMCR), + mc_make_sid_security_cfg(SDMMCRAB), + mc_make_sid_security_cfg(SDMMCWA), + mc_make_sid_security_cfg(SDMMCW), + mc_make_sid_security_cfg(SDMMCWAB), + mc_make_sid_security_cfg(VICSRD), + mc_make_sid_security_cfg(VICSWR), + mc_make_sid_security_cfg(VIW), + mc_make_sid_security_cfg(NVDECSRD), + mc_make_sid_security_cfg(NVDECSWR), + mc_make_sid_security_cfg(APER), + mc_make_sid_security_cfg(APEW), + mc_make_sid_security_cfg(NVJPGSRD), + mc_make_sid_security_cfg(NVJPGSWR), + mc_make_sid_security_cfg(SESRD), + mc_make_sid_security_cfg(SESWR), + mc_make_sid_security_cfg(AXIAPR), + mc_make_sid_security_cfg(AXIAPW), + mc_make_sid_security_cfg(ETRR), + mc_make_sid_security_cfg(ETRW), + mc_make_sid_security_cfg(TSECSRDB), + mc_make_sid_security_cfg(TSECSWRB), + mc_make_sid_security_cfg(AXISR), + mc_make_sid_security_cfg(AXISW), + mc_make_sid_security_cfg(EQOSR), + mc_make_sid_security_cfg(EQOSW), + mc_make_sid_security_cfg(UFSHCR), + mc_make_sid_security_cfg(UFSHCW), + mc_make_sid_security_cfg(NVDISPLAYR), + mc_make_sid_security_cfg(BPMPR), + mc_make_sid_security_cfg(BPMPW), + mc_make_sid_security_cfg(BPMPDMAR), + mc_make_sid_security_cfg(BPMPDMAW), + mc_make_sid_security_cfg(AONR), + mc_make_sid_security_cfg(AONW), + mc_make_sid_security_cfg(AONDMAR), + mc_make_sid_security_cfg(AONDMAW), + mc_make_sid_security_cfg(SCER), + mc_make_sid_security_cfg(SCEW), + mc_make_sid_security_cfg(SCEDMAR), + mc_make_sid_security_cfg(SCEDMAW), + mc_make_sid_security_cfg(APEDMAR), + mc_make_sid_security_cfg(APEDMAW), + mc_make_sid_security_cfg(NVDISPLAYR1), + mc_make_sid_security_cfg(VICSRD1), + mc_make_sid_security_cfg(NVDECSRD1), + mc_make_sid_security_cfg(VIFALR), + mc_make_sid_security_cfg(VIFALW), + mc_make_sid_security_cfg(DLA0RDA), + mc_make_sid_security_cfg(DLA0FALRDB), + mc_make_sid_security_cfg(DLA0WRA), + mc_make_sid_security_cfg(DLA0FALWRB), + mc_make_sid_security_cfg(DLA1RDA), + mc_make_sid_security_cfg(DLA1FALRDB), + mc_make_sid_security_cfg(DLA1WRA), + mc_make_sid_security_cfg(DLA1FALWRB), + mc_make_sid_security_cfg(PVA0RDA), + mc_make_sid_security_cfg(PVA0RDB), + mc_make_sid_security_cfg(PVA0RDC), + mc_make_sid_security_cfg(PVA0WRA), + mc_make_sid_security_cfg(PVA0WRB), + mc_make_sid_security_cfg(PVA0WRC), + mc_make_sid_security_cfg(PVA1RDA), + mc_make_sid_security_cfg(PVA1RDB), + mc_make_sid_security_cfg(PVA1RDC), + mc_make_sid_security_cfg(PVA1WRA), + mc_make_sid_security_cfg(PVA1WRB), + mc_make_sid_security_cfg(PVA1WRC), + mc_make_sid_security_cfg(RCER), + mc_make_sid_security_cfg(RCEW), + mc_make_sid_security_cfg(RCEDMAR), + mc_make_sid_security_cfg(RCEDMAW), + mc_make_sid_security_cfg(NVENC1SRD), + mc_make_sid_security_cfg(NVENC1SWR), + mc_make_sid_security_cfg(PCIE0R), + mc_make_sid_security_cfg(PCIE0W), + mc_make_sid_security_cfg(PCIE1R), + mc_make_sid_security_cfg(PCIE1W), + mc_make_sid_security_cfg(PCIE2AR), + mc_make_sid_security_cfg(PCIE2AW), + mc_make_sid_security_cfg(PCIE3R), + mc_make_sid_security_cfg(PCIE3W), + mc_make_sid_security_cfg(PCIE4R), + mc_make_sid_security_cfg(PCIE4W), + mc_make_sid_security_cfg(PCIE5R), + mc_make_sid_security_cfg(PCIE5W), + mc_make_sid_security_cfg(ISPFALW), + mc_make_sid_security_cfg(DLA0RDA1), + mc_make_sid_security_cfg(DLA1RDA1), + mc_make_sid_security_cfg(PVA0RDA1), + mc_make_sid_security_cfg(PVA0RDB1), + mc_make_sid_security_cfg(PVA1RDA1), + mc_make_sid_security_cfg(PVA1RDB1), + mc_make_sid_security_cfg(PCIE5R1), + mc_make_sid_security_cfg(NVENCSRD1), + mc_make_sid_security_cfg(NVENC1SRD1), + mc_make_sid_security_cfg(ISPRA1), + mc_make_sid_security_cfg(MIU0R), + mc_make_sid_security_cfg(MIU0W), + mc_make_sid_security_cfg(MIU1R), + mc_make_sid_security_cfg(MIU1W), + mc_make_sid_security_cfg(MIU2R), + mc_make_sid_security_cfg(MIU2W), + mc_make_sid_security_cfg(MIU3R), + mc_make_sid_security_cfg(MIU3W), + mc_make_sid_override_cfg(HDAR), + mc_make_sid_override_cfg(HOST1XDMAR), + mc_make_sid_override_cfg(NVENCSRD), + mc_make_sid_override_cfg(SATAR), + mc_make_sid_override_cfg(NVENCSWR), + mc_make_sid_override_cfg(HDAW), + mc_make_sid_override_cfg(SATAW), + mc_make_sid_override_cfg(ISPRA), + mc_make_sid_override_cfg(ISPFALR), + mc_make_sid_override_cfg(ISPWA), + mc_make_sid_override_cfg(ISPWB), + mc_make_sid_override_cfg(XUSB_HOSTR), + mc_make_sid_override_cfg(XUSB_HOSTW), + mc_make_sid_override_cfg(XUSB_DEVR), + mc_make_sid_override_cfg(XUSB_DEVW), + mc_make_sid_override_cfg(TSECSRD), + mc_make_sid_override_cfg(TSECSWR), + mc_make_sid_override_cfg(SDMMCRA), + mc_make_sid_override_cfg(SDMMCR), + mc_make_sid_override_cfg(SDMMCRAB), + mc_make_sid_override_cfg(SDMMCWA), + mc_make_sid_override_cfg(SDMMCW), + mc_make_sid_override_cfg(SDMMCWAB), + mc_make_sid_override_cfg(VICSRD), + mc_make_sid_override_cfg(VICSWR), + mc_make_sid_override_cfg(VIW), + mc_make_sid_override_cfg(NVDECSRD), + mc_make_sid_override_cfg(NVDECSWR), + mc_make_sid_override_cfg(APER), + mc_make_sid_override_cfg(APEW), + mc_make_sid_override_cfg(NVJPGSRD), + mc_make_sid_override_cfg(NVJPGSWR), + mc_make_sid_override_cfg(SESRD), + mc_make_sid_override_cfg(SESWR), + mc_make_sid_override_cfg(AXIAPR), + mc_make_sid_override_cfg(AXIAPW), + mc_make_sid_override_cfg(ETRR), + mc_make_sid_override_cfg(ETRW), + mc_make_sid_override_cfg(TSECSRDB), + mc_make_sid_override_cfg(TSECSWRB), + mc_make_sid_override_cfg(AXISR), + mc_make_sid_override_cfg(AXISW), + mc_make_sid_override_cfg(EQOSR), + mc_make_sid_override_cfg(EQOSW), + mc_make_sid_override_cfg(UFSHCR), + mc_make_sid_override_cfg(UFSHCW), + mc_make_sid_override_cfg(NVDISPLAYR), + mc_make_sid_override_cfg(BPMPR), + mc_make_sid_override_cfg(BPMPW), + mc_make_sid_override_cfg(BPMPDMAR), + mc_make_sid_override_cfg(BPMPDMAW), + mc_make_sid_override_cfg(AONR), + mc_make_sid_override_cfg(AONW), + mc_make_sid_override_cfg(AONDMAR), + mc_make_sid_override_cfg(AONDMAW), + mc_make_sid_override_cfg(SCER), + mc_make_sid_override_cfg(SCEW), + mc_make_sid_override_cfg(SCEDMAR), + mc_make_sid_override_cfg(SCEDMAW), + mc_make_sid_override_cfg(APEDMAR), + mc_make_sid_override_cfg(APEDMAW), + mc_make_sid_override_cfg(NVDISPLAYR1), + mc_make_sid_override_cfg(VICSRD1), + mc_make_sid_override_cfg(NVDECSRD1), + mc_make_sid_override_cfg(VIFALR), + mc_make_sid_override_cfg(VIFALW), + mc_make_sid_override_cfg(DLA0RDA), + mc_make_sid_override_cfg(DLA0FALRDB), + mc_make_sid_override_cfg(DLA0WRA), + mc_make_sid_override_cfg(DLA0FALWRB), + mc_make_sid_override_cfg(DLA1RDA), + mc_make_sid_override_cfg(DLA1FALRDB), + mc_make_sid_override_cfg(DLA1WRA), + mc_make_sid_override_cfg(DLA1FALWRB), + mc_make_sid_override_cfg(PVA0RDA), + mc_make_sid_override_cfg(PVA0RDB), + mc_make_sid_override_cfg(PVA0RDC), + mc_make_sid_override_cfg(PVA0WRA), + mc_make_sid_override_cfg(PVA0WRB), + mc_make_sid_override_cfg(PVA0WRC), + mc_make_sid_override_cfg(PVA1RDA), + mc_make_sid_override_cfg(PVA1RDB), + mc_make_sid_override_cfg(PVA1RDC), + mc_make_sid_override_cfg(PVA1WRA), + mc_make_sid_override_cfg(PVA1WRB), + mc_make_sid_override_cfg(PVA1WRC), + mc_make_sid_override_cfg(RCER), + mc_make_sid_override_cfg(RCEW), + mc_make_sid_override_cfg(RCEDMAR), + mc_make_sid_override_cfg(RCEDMAW), + mc_make_sid_override_cfg(NVENC1SRD), + mc_make_sid_override_cfg(NVENC1SWR), + mc_make_sid_override_cfg(PCIE0R), + mc_make_sid_override_cfg(PCIE0W), + mc_make_sid_override_cfg(PCIE1R), + mc_make_sid_override_cfg(PCIE1W), + mc_make_sid_override_cfg(PCIE2AR), + mc_make_sid_override_cfg(PCIE2AW), + mc_make_sid_override_cfg(PCIE3R), + mc_make_sid_override_cfg(PCIE3W), + mc_make_sid_override_cfg(PCIE4R), + mc_make_sid_override_cfg(PCIE4W), + mc_make_sid_override_cfg(PCIE5R), + mc_make_sid_override_cfg(PCIE5W), + mc_make_sid_override_cfg(ISPFALW), + mc_make_sid_override_cfg(DLA0RDA1), + mc_make_sid_override_cfg(DLA1RDA1), + mc_make_sid_override_cfg(PVA0RDA1), + mc_make_sid_override_cfg(PVA0RDB1), + mc_make_sid_override_cfg(PVA1RDA1), + mc_make_sid_override_cfg(PVA1RDB1), + mc_make_sid_override_cfg(PCIE5R1), + mc_make_sid_override_cfg(NVENCSRD1), + mc_make_sid_override_cfg(NVENC1SRD1), + mc_make_sid_override_cfg(ISPRA1), + mc_make_sid_override_cfg(MIU0R), + mc_make_sid_override_cfg(MIU0W), + mc_make_sid_override_cfg(MIU1R), + mc_make_sid_override_cfg(MIU1W), + mc_make_sid_override_cfg(MIU2R), + mc_make_sid_override_cfg(MIU2W), + mc_make_sid_override_cfg(MIU3R), + mc_make_sid_override_cfg(MIU3W), + smmu_make_gnsr0_nsec_cfg(CR0), + smmu_make_gnsr0_sec_cfg(IDR0), + smmu_make_gnsr0_sec_cfg(IDR1), + smmu_make_gnsr0_sec_cfg(IDR2), + smmu_make_gnsr0_nsec_cfg(GFSR), + smmu_make_gnsr0_nsec_cfg(GFSYNR0), + smmu_make_gnsr0_nsec_cfg(GFSYNR1), + smmu_make_gnsr0_nsec_cfg(TLBGSTATUS), + smmu_make_gnsr0_nsec_cfg(PIDR2), + smmu_make_smrg_group(0), + smmu_make_smrg_group(1), + smmu_make_smrg_group(2), + smmu_make_smrg_group(3), + smmu_make_smrg_group(4), + smmu_make_smrg_group(5), + smmu_make_smrg_group(6), + smmu_make_smrg_group(7), + smmu_make_smrg_group(8), + smmu_make_smrg_group(9), + smmu_make_smrg_group(10), + smmu_make_smrg_group(11), + smmu_make_smrg_group(12), + smmu_make_smrg_group(13), + smmu_make_smrg_group(14), + smmu_make_smrg_group(15), + smmu_make_smrg_group(16), + smmu_make_smrg_group(17), + smmu_make_smrg_group(18), + smmu_make_smrg_group(19), + smmu_make_smrg_group(20), + smmu_make_smrg_group(21), + smmu_make_smrg_group(22), + smmu_make_smrg_group(23), + smmu_make_smrg_group(24), + smmu_make_smrg_group(25), + smmu_make_smrg_group(26), + smmu_make_smrg_group(27), + smmu_make_smrg_group(28), + smmu_make_smrg_group(29), + smmu_make_smrg_group(30), + smmu_make_smrg_group(31), + smmu_make_smrg_group(32), + smmu_make_smrg_group(33), + smmu_make_smrg_group(34), + smmu_make_smrg_group(35), + smmu_make_smrg_group(36), + smmu_make_smrg_group(37), + smmu_make_smrg_group(38), + smmu_make_smrg_group(39), + smmu_make_smrg_group(40), + smmu_make_smrg_group(41), + smmu_make_smrg_group(42), + smmu_make_smrg_group(43), + smmu_make_smrg_group(44), + smmu_make_smrg_group(45), + smmu_make_smrg_group(46), + smmu_make_smrg_group(47), + smmu_make_smrg_group(48), + smmu_make_smrg_group(49), + smmu_make_smrg_group(50), + smmu_make_smrg_group(51), + smmu_make_smrg_group(52), + smmu_make_smrg_group(53), + smmu_make_smrg_group(54), + smmu_make_smrg_group(55), + smmu_make_smrg_group(56), + smmu_make_smrg_group(57), + smmu_make_smrg_group(58), + smmu_make_smrg_group(59), + smmu_make_smrg_group(60), + smmu_make_smrg_group(61), + smmu_make_smrg_group(62), + smmu_make_smrg_group(63), + smmu_make_cb_group(0), + smmu_make_cb_group(1), + smmu_make_cb_group(2), + smmu_make_cb_group(3), + smmu_make_cb_group(4), + smmu_make_cb_group(5), + smmu_make_cb_group(6), + smmu_make_cb_group(7), + smmu_make_cb_group(8), + smmu_make_cb_group(9), + smmu_make_cb_group(10), + smmu_make_cb_group(11), + smmu_make_cb_group(12), + smmu_make_cb_group(13), + smmu_make_cb_group(14), + smmu_make_cb_group(15), + smmu_make_cb_group(16), + smmu_make_cb_group(17), + smmu_make_cb_group(18), + smmu_make_cb_group(19), + smmu_make_cb_group(20), + smmu_make_cb_group(21), + smmu_make_cb_group(22), + smmu_make_cb_group(23), + smmu_make_cb_group(24), + smmu_make_cb_group(25), + smmu_make_cb_group(26), + smmu_make_cb_group(27), + smmu_make_cb_group(28), + smmu_make_cb_group(29), + smmu_make_cb_group(30), + smmu_make_cb_group(31), + smmu_make_cb_group(32), + smmu_make_cb_group(33), + smmu_make_cb_group(34), + smmu_make_cb_group(35), + smmu_make_cb_group(36), + smmu_make_cb_group(37), + smmu_make_cb_group(38), + smmu_make_cb_group(39), + smmu_make_cb_group(40), + smmu_make_cb_group(41), + smmu_make_cb_group(42), + smmu_make_cb_group(43), + smmu_make_cb_group(44), + smmu_make_cb_group(45), + smmu_make_cb_group(46), + smmu_make_cb_group(47), + smmu_make_cb_group(48), + smmu_make_cb_group(49), + smmu_make_cb_group(50), + smmu_make_cb_group(51), + smmu_make_cb_group(52), + smmu_make_cb_group(53), + smmu_make_cb_group(54), + smmu_make_cb_group(55), + smmu_make_cb_group(56), + smmu_make_cb_group(57), + smmu_make_cb_group(58), + smmu_make_cb_group(59), + smmu_make_cb_group(60), + smmu_make_cb_group(61), + smmu_make_cb_group(62), + smmu_make_cb_group(63), + smmu_bypass_cfg, /* TBU settings */ + _END_OF_TABLE_, +}; + +/******************************************************************************* + * Handler to return the pointer to the SMMU's context struct + ******************************************************************************/ +smmu_regs_t *plat_get_smmu_ctx(void) +{ + /* index of _END_OF_TABLE_ */ + tegra194_smmu_context[0].val = ARRAY_SIZE(tegra194_smmu_context) - 1; + + return tegra194_smmu_context; +} diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index b6bc44214..95c967f4b 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -57,10 +57,12 @@ BL31_SOURCES += lib/cpus/aarch64/denver.S \ ${SOC_DIR}/drivers/mce/mce.c \ ${SOC_DIR}/drivers/mce/nvg.c \ ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ + ${SOC_DIR}/plat_memctrl.c \ ${SOC_DIR}/plat_psci_handlers.c \ ${SOC_DIR}/plat_setup.c \ ${SOC_DIR}/plat_secondary.c \ - ${SOC_DIR}/plat_sip_calls.c + ${SOC_DIR}/plat_sip_calls.c \ + ${SOC_DIR}/plat_smmu.c ifeq (${ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM}, 1) BL31_SOURCES += ${SOC_DIR}/plat_trampoline.S -- cgit v1.2.3 From cff9b9c2933c6ea2bf51891c7421aeff8383c9e3 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 22 Jun 2017 10:35:38 -0700 Subject: Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits This patch converts the 'target_cpu' and 'target_cluster' variables from the tegra_soc_pwr_domain_on() handler to 32-bits. This fixes the signed comparison warning flagged by the compiler. Change-Id: Idfd7ad2a62749bb0dd032eb9eb5f4b28df32bba0 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 59131b3d2..2b45ee84f 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -250,8 +250,8 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_on(u_register_t mpidr) { - int target_cpu = mpidr & MPIDR_CPU_MASK; - int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> + uint32_t target_cpu = mpidr & MPIDR_CPU_MASK; + uint32_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; if (target_cluster > MPIDR_AFFLVL1) { -- cgit v1.2.3 From b0a86254a058edce1ff59d551f66f82cb19e6fc4 Mon Sep 17 00:00:00 2001 From: Vignesh Radhakrishnan Date: Thu, 25 May 2017 16:27:42 -0700 Subject: Tegra194: Enable fake system suspend Fake system suspend for Tegra194, calls the routine tegra_secure_entrypoint() instead of calling WFI. In essence, this is a debug mode that ensures that the code path of kernel->ATF and back to kernel is executed without depending on other components involved in the system suspend path. This is for ensuring that verification of system suspend can be done on pre-silicon platforms without depending on the rest of the layers being enabled. Change-Id: I18572b169b7ef786f9029600dad9ef5728634f2b Signed-off-by: Vignesh Radhakrishnan --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 57 ++++++++++++++++++++----- plat/nvidia/tegra/soc/t194/plat_sip_calls.c | 21 +++++++++ 2 files changed, 68 insertions(+), 10 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 2b45ee84f..8208df01e 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -19,10 +19,11 @@ #include #include #include +#include extern void prepare_core_pwr_dwn(void); -extern uint8_t tegra_fake_system_suspend; +extern void tegra_secure_entrypoint(void); #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM extern void tegra186_cpu_reset_handler(void); @@ -48,6 +49,14 @@ static struct t18x_psci_percpu_data { unsigned int wake_time; } __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT]; +/* + * tegra_fake_system_suspend acts as a boolean var controlling whether + * we are going to take fake system suspend code or normal system suspend code + * path. This variable is set inside the sip call handlers, when the kernel + * requests an SIP call to set the suspend debug flags. + */ +bool tegra_fake_system_suspend; + int32_t tegra_soc_validate_power_state(unsigned int power_state, psci_power_state_t *req_state) { @@ -96,8 +105,14 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) uint64_t smmu_ctx_base; #endif uint32_t val; - mce_cstate_info_t cstate_info = { 0 }; + mce_cstate_info_t sc7_cstate_info = { + .cluster = TEGRA_NVG_CLUSTER_CC6, + .system = TEGRA_NVG_SYSTEM_SC7, + .system_state_force = 1, + .update_wake_mask = 1, + }; int cpu = plat_my_core_pos(); + int32_t ret = 0; /* get the state ID */ pwr_domain_state = target_state->pwr_domain_state; @@ -112,8 +127,9 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* Enter CPU idle/powerdown */ val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? TEGRA_NVG_CORE_C6 : TEGRA_NVG_CORE_C7; - (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val, + ret = mce_command_handler(MCE_CMD_ENTER_CSTATE, val, percpu_data[cpu].wake_time, 0); + assert(ret == 0); } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { @@ -140,15 +156,10 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) tegra_smmu_save_context(0); #endif - if (tegra_fake_system_suspend == 0U) { + if (!tegra_fake_system_suspend) { /* Prepare for system suspend */ - cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6; - cstate_info.system = TEGRA_NVG_SYSTEM_SC7; - cstate_info.system_state_force = 1; - cstate_info.update_wake_mask = 1; - - mce_update_cstate_info(&cstate_info); + mce_update_cstate_info(&sc7_cstate_info); do { val = mce_command_handler( @@ -230,6 +241,7 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & TEGRA186_STATE_ID_MASK; uint64_t val; + u_register_t ns_sctlr_el1; if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { /* @@ -242,6 +254,31 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) (uintptr_t)tegra186_cpu_reset_handler); memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); + + + /* + * In fake suspend mode, ensure that the loopback procedure + * towards system suspend exit is started, instead of calling + * WFI. This is done by disabling both MMU's of EL1 & El3 + * and calling tegra_secure_entrypoint(). + */ + if (tegra_fake_system_suspend) { + + /* + * Disable EL1's MMU. + */ + ns_sctlr_el1 = read_sctlr_el1(); + ns_sctlr_el1 &= (~((u_register_t)SCTLR_M_BIT)); + write_sctlr_el1(ns_sctlr_el1); + + /* + * Disable MMU to power up the CPU in a "clean" + * state + */ + disable_mmu_el3(); + tegra_secure_entrypoint(); + panic(); + } } return PSCI_E_SUCCESS; diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index eaad73a40..4b6a901db 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -15,14 +15,19 @@ #include #include #include +#include +#include extern uint32_t tegra186_system_powerdn_state; +extern bool tegra_fake_system_suspend; + /******************************************************************************* * Tegra186 SiP SMCs ******************************************************************************/ #define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01 #define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02 +#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03 #define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00 #define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01 #define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02 @@ -110,6 +115,22 @@ int plat_sip_handler(uint32_t smc_fid, return 0; + case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND: + /* + * System suspend mode is set if the platform ATF is running is + * VDK and there is a debug SIP call. This mode ensures that the + * debug path is excercied, instead of regular code path to suit + * the pre-silicon platform needs. These include replacing the + * the call to WFI with calls to system suspend exit procedures. + */ + if (tegra_platform_is_virt_dev_kit()) { + + tegra_fake_system_suspend = true; + return 0; + } + + break; + default: break; } -- cgit v1.2.3 From 2cd2e399f60b11a3bf1cc6e7988425d0d714a975 Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Thu, 22 Jun 2017 12:54:06 +0800 Subject: Tegra194: read-modify-write ACTLR_ELx registers This patch changes direct writes to ACTLR_ELx registers to use read-modify-write instead. Change-Id: I536dce75c01356ce054dd2edee80875e56164439 Signed-off-by: Steven Kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 14 -------------- plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 5 ++++- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 300db8135..9b6e18e9d 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -27,20 +27,6 @@ #define PLAT_MAX_RET_STATE 1 #define PLAT_MAX_OFF_STATE 8 -/******************************************************************************* - * Implementation defined ACTLR_EL3 bit definitions - ******************************************************************************/ -#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) -#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) -#define ACTLR_EL3_L2CTLR_BIT (1 << 4) -#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) -#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) -#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ - ACTLR_EL3_L2ECTLR_BIT | \ - ACTLR_EL3_L2CTLR_BIT | \ - ACTLR_EL3_CPUECTLR_BIT | \ - ACTLR_EL3_CPUACTLR_BIT) - /******************************************************************************* * Secure IRQ definitions ******************************************************************************/ diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index 12dd6cb09..c797a0cf7 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -13,6 +13,7 @@ #include #include #include +#include extern void nvg_set_request_data(uint64_t req, uint64_t data); extern void nvg_set_request(uint64_t req); @@ -342,6 +343,7 @@ int32_t nvg_roc_clean_cache_trbits(void) int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) { int32_t ret = 0; + uint64_t val = 0ULL; /* check for allowed power state */ if ((state != (uint32_t)TEGRA_NVG_CORE_C0) && @@ -356,7 +358,8 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) nvg_set_wake_time(wake_time); /* set the core cstate */ - write_actlr_el1(state); + val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK; + write_actlr_el1(val | (uint64_t)state); } return ret; -- cgit v1.2.3 From 79b65666be657006f5cc7dadaf85103fd136703f Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Fri, 30 Jun 2017 13:51:12 -0700 Subject: Tegra194: Update cpu core-id calculation This patch updates the cpu core id calculation to match with internal numbering method used by the MTS. Change-Id: I5fbe9c8685c23017edc796e114d07c5e979e0d3d Signed-off-by: Krishna Sitaraman --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 8208df01e..adfd6cf41 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -297,7 +297,7 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr) } /* construct the target CPU # */ - target_cpu |= (target_cluster << 2); + target_cpu += (target_cluster << 1); mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); -- cgit v1.2.3 From b6e1109f796911872d97e60bc8293a5d76e2fe6c Mon Sep 17 00:00:00 2001 From: Vignesh Radhakrishnan Date: Tue, 11 Jul 2017 15:16:08 -0700 Subject: Tegra194: Initialize smmu on system suspend exit System suspend sequence involves initializing the SMMU as a part of the system suspend exit, which is currently not present for Tegra194 platform. Thus call tegra_smmu_init() as a part of system suspend exit. Change-Id: I3086301743019e05a40fd221372e7f8713f286ae Signed-off-by: Vignesh Radhakrishnan --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index adfd6cf41..14af725ea 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -331,6 +331,8 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) /* Init SMMU */ + tegra_smmu_init(); + /* * Reset power state info for the last core doing SC7 * entry and exit, we set deepest power state as CC7 -- cgit v1.2.3 From 13dcbc6f2265ac4f3ea018cdb785fb1e8d473119 Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Tue, 25 Jul 2017 12:44:32 +0800 Subject: Tegra194: smmu: ISO support The FPGA configuration is encoded in the high byte of MISCREG_EMU_REVID. Configs GPU and MAX (encoded as 2 and 3) support the ISO SMMU, while BASE (encoded as 1) does not. This patch implements this encoding and returns the proper number of SMMU instances. Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe Signed-off-by: Steven Kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 9 ++++++--- plat/nvidia/tegra/soc/t194/plat_smmu.c | 25 +++++++++++++++++++++++++ plat/nvidia/tegra/soc/t194/platform_t194.mk | 3 --- 3 files changed, 31 insertions(+), 6 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 9b6e18e9d..a9b72716a 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -42,10 +42,13 @@ /******************************************************************************* * Tegra Miscellanous register constants ******************************************************************************/ -#define TEGRA_MISC_BASE 0x00100000 -#define HARDWARE_REVISION_OFFSET 0x4 +#define TEGRA_MISC_BASE 0x00100000U -#define MISCREG_PFCFG 0x200C +#define HARDWARE_REVISION_OFFSET 0x4U +#define MISCREG_EMU_REVID 0x3160U +#define BOARD_MASK_BITS 0xFFU +#define BOARD_SHIFT_BITS 24U +#define MISCREG_PFCFG 0x200CU /******************************************************************************* * Tegra TSA Controller constants diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index 2b82f24f5..64e605bbb 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -9,6 +9,15 @@ #include #include +#define BOARD_SYSTEM_FPGA_BASE U(1) +#define BASE_CONFIG_SMMU_DEVICES U(2) +#define MAX_NUM_SMMU_DEVICES U(3) + +static uint32_t tegra_misc_read_32(uint32_t off) +{ + return mmio_read_32(TEGRA_MISC_BASE + off); +} + /******************************************************************************* * Array to hold SMMU context for Tegra186 ******************************************************************************/ @@ -411,3 +420,19 @@ smmu_regs_t *plat_get_smmu_ctx(void) return tegra194_smmu_context; } + +/******************************************************************************* + * Handler to return the support SMMU devices number + ******************************************************************************/ +uint32_t plat_get_num_smmu_devices(void) +{ + uint32_t ret_num = MAX_NUM_SMMU_DEVICES; + uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \ + BOARD_SHIFT_BITS) && BOARD_MASK_BITS); + + if (board_revid == BOARD_SYSTEM_FPGA_BASE) { + ret_num = BASE_CONFIG_SMMU_DEVICES; + } + + return ret_num; +} diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 95c967f4b..3f624dd56 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -23,9 +23,6 @@ $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) ENABLE_SMMU_DEVICE := 1 $(eval $(call add_define,ENABLE_SMMU_DEVICE)) -NUM_SMMU_DEVICES := 3 -$(eval $(call add_define,NUM_SMMU_DEVICES)) - RESET_TO_BL31 := 1 PROGRAMMABLE_RESET_ADDRESS := 1 -- cgit v1.2.3 From 6907891de5f3d439621738b4247a0c616333cb9f Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Thu, 3 Aug 2017 19:12:14 +0530 Subject: Tegra194: smmu: fix mask for board revision id Need to use bitwise & instead of condition &&. Change-Id: I8f70aac95d116188ba972f3d38b02e1d3dd32acb Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/soc/t194/plat_smmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index 64e605bbb..edca16b7f 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -428,7 +428,7 @@ uint32_t plat_get_num_smmu_devices(void) { uint32_t ret_num = MAX_NUM_SMMU_DEVICES; uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \ - BOARD_SHIFT_BITS) && BOARD_MASK_BITS); + BOARD_SHIFT_BITS) & BOARD_MASK_BITS); if (board_revid == BOARD_SYSTEM_FPGA_BASE) { ret_num = BASE_CONFIG_SMMU_DEVICES; -- cgit v1.2.3 From 68d13a2eb84393b2e8bbf94b16783954d2544638 Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Wed, 24 May 2017 17:21:22 -0700 Subject: Tegra194: Update checks for c-state stats This patch adds proper checks for the cpu c-stats. It checks both cpu id and stat id before sending the nvg request to ccplex. Change-Id: I732957d1e10d6ce6cffb2c6f5963ca614aadd948 Signed-off-by: Krishna Sitaraman --- plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h | 5 +++++ plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 12 +++++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index cc32ec416..3ac5333a0 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -46,6 +46,11 @@ #define CACHE_CLEAN_INVAL_SET (1UL << 1) #define CACHE_CLEAN_INVAL_TR_SET (1UL << 2) +/******************************************************************************* + * C-state statistics macros + ******************************************************************************/ +#define MCE_STAT_ID_SHIFT 16UL + /* declarations for NVG handler functions */ uint64_t nvg_get_version(void); int32_t nvg_enable_power_perf_mode(void); diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index c797a0cf7..c7f659186 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -187,9 +187,15 @@ int32_t nvg_set_cstate_stat_query_value(uint64_t data) { int32_t ret = 0; - /* sanity check stat id */ - if (data > (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) { - ERROR("%s: unknown stat id (%d)\n", __func__, (uint32_t)data); + /* sanity check stat id and core id*/ + if ((data >> MCE_STAT_ID_SHIFT) > + (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) { + ERROR("%s: unknown stat id (%d)\n", __func__, + (uint32_t)(data >> MCE_STAT_ID_SHIFT)); + ret = EINVAL; + } else if ((data & MCE_CORE_ID_MASK) > (uint64_t)PLATFORM_CORE_COUNT) { + ERROR("%s: unknown core id (%d)\n", __func__, + (uint32_t)(data & MCE_CORE_ID_MASK)); ret = EINVAL; } else { nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data); -- cgit v1.2.3 From bc0190416e2f3d3c8d637f5017a31459806d7de9 Mon Sep 17 00:00:00 2001 From: Ajay Gupta Date: Tue, 1 Aug 2017 15:53:04 -0700 Subject: Tegra194: program stream ids for XUSB T194 XUSB has support for XUSB virtualization. It will have one physical function (PF) and four Virtual function (VF) There were below two SIDs for XUSB until T186. 1) #define TEGRA_SID_XUSB_HOST 0x1bU 2) #define TEGRA_SID_XUSB_DEV 0x1cU We have below four new SIDs added for VF(s) 3) #define TEGRA_SID_XUSB_VF0 0x5dU 4) #define TEGRA_SID_XUSB_VF1 0x5eU 5) #define TEGRA_SID_XUSB_VF2 0x5fU 6) #define TEGRA_SID_XUSB_VF3 0x60U When virtualization is enabled then we have to disable SID override and program above SIDs in below newly added SID registers in XUSB PADCTL MMIO space. These registers are TZ protected and so need to be done in ATF. a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) This change disables SID override and programs XUSB SIDs in above registers to support both virtualization and non-virtualization. Change-Id: I38213a72999e933c44c5392441f91034d3b47a39 Signed-off-by: Ajay Gupta --- plat/nvidia/tegra/include/t194/tegra_def.h | 22 +++++++++++++ plat/nvidia/tegra/soc/t194/plat_memctrl.c | 8 ++--- plat/nvidia/tegra/soc/t194/plat_setup.c | 49 +++++++++++++++++++++++++++++ plat/nvidia/tegra/soc/t194/platform_t194.mk | 4 +-- 4 files changed, 77 insertions(+), 6 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index a9b72716a..073442966 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -361,4 +361,26 @@ #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4 #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC +/******************************************************************************* + * XUSB PADCTL + ******************************************************************************/ +#define TEGRA_XUSB_PADCTL_BASE (0x3520000U) +#define TEGRA_XUSB_PADCTL_SIZE (0x10000U) +#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) +#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) + +/******************************************************************************* + * XUSB STREAMIDs + ******************************************************************************/ +#define TEGRA_SID_XUSB_HOST (0x1bU) +#define TEGRA_SID_XUSB_DEV (0x1cU) +#define TEGRA_SID_XUSB_VF0 (0x5dU) +#define TEGRA_SID_XUSB_VF1 (0x5eU) +#define TEGRA_SID_XUSB_VF2 (0x5fU) +#define TEGRA_SID_XUSB_VF3 (0x60U) + #endif /* __TEGRA_DEF_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index a4c35e9a8..0a39ef159 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -151,10 +151,10 @@ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index a3a2515ca..1f0c07b5d 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -92,6 +92,8 @@ static const mmap_region_t tegra_mmap[] = { MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */ MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000, /* 64KB */ + MT_DEVICE | MT_RW | MT_SECURE), {0} }; @@ -151,6 +153,53 @@ void plat_early_platform_setup(void) /* sanity check MCE firmware compatibility */ mce_verify_firmware_version(); + /* Program XUSB STREAMIDs + * Xavier XUSB has support for XUSB virtualization. It will have one + * physical function (PF) and four Virtual function (VF) + * + * There were below two SIDs for XUSB until T186. + * 1) #define TEGRA_SID_XUSB_HOST 0x1bU + * 2) #define TEGRA_SID_XUSB_DEV 0x1cU + * + * We have below four new SIDs added for VF(s) + * 3) #define TEGRA_SID_XUSB_VF0 0x5dU + * 4) #define TEGRA_SID_XUSB_VF1 0x5eU + * 5) #define TEGRA_SID_XUSB_VF2 0x5fU + * 6) #define TEGRA_SID_XUSB_VF3 0x60U + * + * When virtualization is enabled then we have to disable SID override + * and program above SIDs in below newly added SID registers in XUSB + * PADCTL MMIO space. These registers are TZ protected and so need to + * be done in ATF. + * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) + * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) + * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) + * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) + * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) + * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) + * + * This change disables SID override and programs XUSB SIDs in + * above registers to support both virtualization and non-virtualization + * + * Known Limitations: + * If xusb interface disables SMMU in XUSB DT in non-virtualization + * setup then there will be SMMU fault. We need to use WAR at + * https://git-master.nvidia.com/r/1529227/ to the issue. + * + * More details can be found in the bug 1971161 + */ + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); } /* Secure IRQs for Tegra186 */ diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 3f624dd56..7ee8b7e4e 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -39,10 +39,10 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) PLATFORM_MAX_CPUS_PER_CLUSTER := 4 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) -MAX_XLAT_TABLES := 24 +MAX_XLAT_TABLES := 25 $(eval $(call add_define,MAX_XLAT_TABLES)) -MAX_MMAP_REGIONS := 24 +MAX_MMAP_REGIONS := 25 $(eval $(call add_define,MAX_MMAP_REGIONS)) # platform files -- cgit v1.2.3 From cda7d91f67bced518d12dd6ccf52b5619beb307b Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Fri, 14 Jul 2017 13:51:44 -0700 Subject: Tegra194: Update wake mask, wake time for cpu offlining This patch updates the wake mask and wake time to indicate to the mce/mts that the cpu is powering down. Wake time is set to highest possible value and wake mask is set to zero. Change-Id: Ic5abf15e7b98f911def6aa610d300b0668cd287e Signed-off-by: Krishna Sitaraman --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 14af725ea..d77842984 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -216,11 +216,20 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, /* Enable cluster powerdn from last CPU in the cluster */ if (cluster_powerdn) { - /* Enable CC7 state and turn off wake mask */ + /* Enable CC6 */ + /* todo */ - } else { + /* If cluster group needs to be railgated, request CG7 */ + /* todo */ + + /* Turn off wake mask */ + cstate_info.update_wake_mask = 1U; + mce_update_cstate_info(&cstate_info); + } else { /* Turn off wake_mask */ + cstate_info.update_wake_mask = 1U; + mce_update_cstate_info(&cstate_info); } } @@ -347,12 +356,16 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) { int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + int32_t ret = 0; /* Disable Denver's DCO operations */ if (impl == DENVER_IMPL) denver_disable_dco(); /* Turn off CPU */ + ret = mce_command_handler(MCE_CMD_ENTER_CSTATE, + TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); + assert(ret == 0); return PSCI_E_SUCCESS; } -- cgit v1.2.3 From c0e1bcd0d365a5c6795c26bede38c585e5c12ec1 Mon Sep 17 00:00:00 2001 From: Harvey Hsieh Date: Wed, 9 Aug 2017 16:26:33 +0800 Subject: Tegra194: add MC_SECURITY mask defines This patch adds masks for the TZDRAM base/size registers. Change-Id: I5f688793be8cace28d2aa2d177a295e4faffd666 Signed-off-by: Harvey Hsieh --- plat/nvidia/tegra/include/t194/tegra_def.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 073442966..577ee9b46 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -110,6 +110,10 @@ #define MC_SECURITY_CFG1_0 0x74 #define MC_SECURITY_CFG3_0 0x9BC +#define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) +#define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) +#define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) + /* Video Memory carveout configuration registers */ #define MC_VIDEO_PROTECT_BASE_HI 0x978 #define MC_VIDEO_PROTECT_BASE_LO 0x648 -- cgit v1.2.3 From c1485edf7a61f65fcf301d5dd9435092d552c11a Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Thu, 31 Aug 2017 13:35:01 +0800 Subject: Tegra194: correct the TEGRA_CAR_RESET_BASE macro value This patch corrects the TEGRA_CAR_RESET_BASE macro value to 0x20000000 from 0x200000000. Change-Id: Iba25394ea99237df85395c39059926c5a8b26a84 Signed-off-by: Steven Kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 577ee9b46..3d2eee522 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -224,7 +224,7 @@ /******************************************************************************* * Tegra Clock and Reset Controller constants ******************************************************************************/ -#define TEGRA_CAR_RESET_BASE 0x200000000 +#define TEGRA_CAR_RESET_BASE 0x20000000 #define TEGRA_GPU_RESET_REG_OFFSET 0x18UL #define GPU_RESET_BIT (1UL << 0) -- cgit v1.2.3 From 1e6a7f9179eb812273246390bf6b95e9bb04ddd9 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 23 Aug 2017 14:59:09 -0700 Subject: Tegra194: core and cluster count values This patch updates the total number of CPU clusters and number of cores per cluster, in the platform makefile. Change-Id: I569ebc1bb794ecab09a1043511b3d936bf450428 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_setup.c | 4 ++++ plat/nvidia/tegra/soc/t194/platform_t194.mk | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 1f0c07b5d..4471ba091 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -39,6 +39,10 @@ const unsigned char tegra_power_domain_tree_desc[] = { /* No of CPU cores - cluster0 */ PLATFORM_MAX_CPUS_PER_CLUSTER, /* No of CPU cores - cluster1 */ + PLATFORM_MAX_CPUS_PER_CLUSTER, + /* No of CPU cores - cluster2 */ + PLATFORM_MAX_CPUS_PER_CLUSTER, + /* No of CPU cores - cluster3 */ PLATFORM_MAX_CPUS_PER_CLUSTER }; diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 7ee8b7e4e..d16aab8bb 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -33,10 +33,10 @@ COLD_BOOT_SINGLE_CPU := 1 TZDRAM_BASE := 0x40000000 $(eval $(call add_define,TZDRAM_BASE)) -PLATFORM_CLUSTER_COUNT := 2 +PLATFORM_CLUSTER_COUNT := 4 $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) -PLATFORM_MAX_CPUS_PER_CLUSTER := 4 +PLATFORM_MAX_CPUS_PER_CLUSTER := 2 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) MAX_XLAT_TABLES := 25 -- cgit v1.2.3 From f32e852596704f517d7804693d056914fb52a0e3 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 24 Oct 2019 16:06:12 -0700 Subject: Tegra194: memctrl: platform handlers to reprogram MSS Introduce platform handlers to reprogram the MSS settings. Change-Id: Ibb9a5457d1bad9ecccea619d69a62bed3bf7d861 Signed-off-by: Puneet Saxena Signed-off-by: Krishna Reddy Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra_def.h | 177 ---------------- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 328 ++++++++++++++++++++++++++++- plat/nvidia/tegra/soc/t194/plat_setup.c | 1 + plat/nvidia/tegra/soc/t194/plat_smmu.c | 1 + 4 files changed, 328 insertions(+), 179 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 3d2eee522..bdfa05145 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -50,45 +50,6 @@ #define BOARD_SHIFT_BITS 24U #define MISCREG_PFCFG 0x200CU -/******************************************************************************* - * Tegra TSA Controller constants - ******************************************************************************/ -#define TEGRA_TSA_BASE 0x02000000 - -#define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010 -#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034 -#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020 -#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008 -#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008 -#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018 -#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008 -#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028 -#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008 -#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008 -#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008 -#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008 -#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038 -#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018 -#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028 -#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 - -#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) -#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) - /******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ @@ -137,7 +98,6 @@ #define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 /* Memory Controller Reset Control registers */ -#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27) #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) @@ -228,143 +188,6 @@ #define TEGRA_GPU_RESET_REG_OFFSET 0x18UL #define GPU_RESET_BIT (1UL << 0) -/******************************************************************************* - * Stream ID Override Config registers - ******************************************************************************/ -#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U -#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U -#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U -#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U -#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U -#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U -#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U -#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U -#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U -#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U -#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U -#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5E0U -#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5E8U -#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5F0U -#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5F8U -#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U -#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U -#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U -#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U -#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U -#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U -#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U -#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U -#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U -#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U -#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U -#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U -#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U -#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U -#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6A0U -#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6A8U -#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6B0U -#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6B8U -#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6C0U -#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6C8U -#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6D0U -#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6D8U -#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6E0U -#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6E8U -#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6F0U -#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6F8U -#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U -#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U -#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U -#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U -#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U -#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U -#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U -#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U -#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U -#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U -#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U -#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U -#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7C8U -#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7D0U -#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7D8U - -/******************************************************************************* - * Memory Controller transaction override config registers - ******************************************************************************/ -#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530 -#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538 -#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540 -#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548 -#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570 -#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578 -#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580 -#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158C -#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15E4 -#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15EC -#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15F4 -#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15FC -#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604 -#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160C -#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614 -#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161C -#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624 -#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162C -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634 -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163C -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644 -#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164C -#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654 -#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165C -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664 -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166C -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674 -#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167C -#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684 -#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168C -#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694 -#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169C -#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16A4 -#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16AC -#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16B4 -#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16BC -#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16C4 -#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16CC -#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16D4 -#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16DC -#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16E4 -#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16EC -#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16F4 -#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16FC -#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704 -#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170C -#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714 -#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171C -#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724 -#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174C -#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754 -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175C -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764 -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176C -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774 -#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177C -#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784 -#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178C -#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794 -#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179C -#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17CC -#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4 -#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC - /******************************************************************************* * XUSB PADCTL ******************************************************************************/ diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 0a39ef159..a9341b16b 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -4,8 +4,12 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include +#include +#include +#include #include +#include +#include /******************************************************************************* * Array to hold stream_id override config register offsets @@ -297,6 +301,325 @@ const static mc_txn_override_cfg_t tegra194_txn_override_cfgs[] = { mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR), }; +/* To be called by common memctrl_v2.c */ +static void tegra194_memctrl_reconfig_mss_clients(void) +{ + uint32_t reg_val, wdata_0, wdata_1, wdata_2; + + wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB; + if (tegra_platform_is_silicon()) { + wdata_0 |= MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB; + } + + tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); + + /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ + do { + reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); + } while ((reg_val & wdata_0) != wdata_0); + + wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB| + MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB; + if (tegra_platform_is_silicon()) { + wdata_1 |= MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB; + } + tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); + /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ + do { + reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); + } while ((reg_val & wdata_1) != wdata_1); + + wdata_2 = MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB; + if (tegra_platform_is_silicon()) { + wdata_2 |= MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB | + MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB; + } + tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2); + /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ + do { + reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS2); + } while ((reg_val & wdata_2) != wdata_2); + + /* + * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and + * strongly ordered MSS clients. + * + * MC clients with default SO_DEV override still enabled at TSA: + * EQOSW, SATAW, XUSB_DEVW, XUSB_HOSTW, PCIe0w, PCIe1w, PCIe2w, + * PCIe3w, PCIe4w and PCIe5w. + */ + mc_set_tsa_w_passthrough(AONDMAW); + mc_set_tsa_w_passthrough(AONW); + mc_set_tsa_w_passthrough(APEDMAW); + mc_set_tsa_w_passthrough(APEW); + mc_set_tsa_w_passthrough(AXISW); + mc_set_tsa_w_passthrough(BPMPDMAW); + mc_set_tsa_w_passthrough(BPMPW); + mc_set_tsa_w_passthrough(ETRW); + mc_set_tsa_w_passthrough(SCEDMAW); + mc_set_tsa_w_passthrough(RCEDMAW); + mc_set_tsa_w_passthrough(RCEW); + mc_set_tsa_w_passthrough(SDMMCW); + mc_set_tsa_w_passthrough(SDMMCWA); + mc_set_tsa_w_passthrough(SDMMCWAB); + mc_set_tsa_w_passthrough(SESWR); + mc_set_tsa_w_passthrough(TSECSWR); + mc_set_tsa_w_passthrough(TSECSWRB); + mc_set_tsa_w_passthrough(UFSHCW); + mc_set_tsa_w_passthrough(VICSWR); + mc_set_tsa_w_passthrough(VIFALW); + + /* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3 + * ISO clients(DISP, VI, EQOS) should never snoop caches and + * don't need ROC/PCFIFO ordering. + * ISO clients(EQOS) that need ordering should use PCFIFO ordering + * and bypass ROC ordering by using FORCE_NON_COHERENT path. + * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence + * over SMMU attributes. + * Force all Normal memory transactions from ISO and non-ISO to be + * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit). + * Force the SO_DEV transactions from ordered ISO clients(EQOS) to + * non-coherent path and enable MC PCFIFO interlock for ordering. + * Force the SO_DEV transactions from ordered non-ISO clients (PCIe, + * XUSB, SATA) to coherent so that the transactions are + * ordered by ROC. + * PCFIFO ensure write ordering. + * Read after Write ordering is maintained/enforced by MC clients. + * Clients that need PCIe type write ordering must + * go through ROC ordering. + * Ordering enable for Read clients is not necessary. + * R5's and A9 would get necessary ordering from AXI and + * don't need ROC ordering enable: + * - MMIO ordering is through dev mapping and MMIO + * accesses bypass SMMU. + * - Normal memory is accessed through SMMU and ordering is + * ensured by client and AXI. + * - Ack point for Normal memory is WCAM in MC. + * - MMIO's can be early acked and AXI ensures dev memory ordering, + * Client ensures read/write direction change ordering. + * - See Bug 200312466 for more details. + * + * CGID_TAG_ADR is only present from T186 A02. As this code is common + * between A01 and A02, tegra_memctrl_set_overrides() programs + * CGID_TAG_ADR for the necessary clients on A02. + */ + mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, + FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, + FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, + FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, + FORCE_COHERENT_SNOOP); + if (tegra_platform_is_silicon()) { + mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO, + NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO, + FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO, + NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO, + FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO, + NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO, + FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO, + NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO, + FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, + NO_OVERRIDE, NO_OVERRIDE); + } + /* + * At this point, ordering can occur at ROC. So, remove PCFIFO's + * control over ordering requests. + * + * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for + * boot and strongly ordered MSS clients + */ + /* SATAW is ordered client */ + reg_val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL | + mc_set_pcfifo_ordered_boot_so_mss(1, SATAW); + tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, reg_val); + + reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL & + mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) & + mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR); + /* XUSB_DEVW has PCFIFO enabled. */ + reg_val |= mc_set_pcfifo_ordered_boot_so_mss(2, XUSB_DEVW); + tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val); + + reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL & + mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWA) & + mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCW) & + mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB) & + mc_set_pcfifo_unordered_boot_so_mss(3, VICSWR) & + mc_set_pcfifo_unordered_boot_so_mss(3, APEW); + tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, reg_val); + + reg_val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL & + mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) & + mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) & + mc_set_pcfifo_unordered_boot_so_mss(4, TSECSWRB) & + mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) & + mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) & + mc_set_pcfifo_unordered_boot_so_mss(4, BPMPW) & + mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) & + mc_set_pcfifo_unordered_boot_so_mss(4, AONW) & + mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) & + mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) & + mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); + /* EQOSW has PCFIFO order enabled. */ + reg_val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW); + tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val); + + reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & + mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW) & + mc_set_pcfifo_unordered_boot_so_mss(5, VIFALW); + tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, reg_val); + + reg_val = MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL & + mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) & + mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) & + mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W); + /* PCIE1, PCIE2 and PCI3 has PCFIFO enabled. */ + reg_val |= mc_set_pcfifo_ordered_boot_so_mss(6, PCIE1W) | + mc_set_pcfifo_ordered_boot_so_mss(6, PCIE2W) | + mc_set_pcfifo_ordered_boot_so_mss(6, PCIE3W); + tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val); + + reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL & + mc_set_pcfifo_unordered_boot_so_mss(7, PCIE4W) & + mc_set_pcfifo_unordered_boot_so_mss(7, PCIE5W); + tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val); + + /* Set Order Id only for the clients having non zero order id */ + reg_val = MC_CLIENT_ORDER_ID_9_RESET_VAL & + mc_client_order_id(9, XUSB_HOSTW); + tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val); + + reg_val = MC_CLIENT_ORDER_ID_27_RESET_VAL & + mc_client_order_id(27, PCIE0W); + tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val); + + reg_val = MC_CLIENT_ORDER_ID_28_RESET_VAL & + mc_client_order_id(28, PCIE4W) & + mc_client_order_id(28, PCIE5W); + tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val); + + /* Set VC Id only for the clients having different reset values */ + reg_val = MC_HUB_PC_VC_ID_0_RESET_VAL & + /* + * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB, + * TSECSWR and TSECSWRB clients + */ + mc_hub_vc_id(0, APB); + tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val); + + reg_val = MC_HUB_PC_VC_ID_2_RESET_VAL & + /* SDMMCRAB and SDMMCWAB clients */ + mc_hub_vc_id(2, SD); + tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val); + + reg_val = MC_HUB_PC_VC_ID_4_RESET_VAL & + /* AXIR and AXIW clients */ + mc_hub_vc_id(4, NIC); + tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val); + + wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; + tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); + + wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL; + tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); + + wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL; + tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2); +} + /******************************************************************************* * Struct to hold the memory controller settings ******************************************************************************/ @@ -306,7 +629,8 @@ static tegra_mc_settings_t tegra194_mc_settings = { .streamid_security_cfg = tegra194_streamid_sec_cfgs, .num_streamid_security_cfgs = ARRAY_SIZE(tegra194_streamid_sec_cfgs), .txn_override_cfg = tegra194_txn_override_cfgs, - .num_txn_override_cfgs = ARRAY_SIZE(tegra194_txn_override_cfgs) + .num_txn_override_cfgs = ARRAY_SIZE(tegra194_txn_override_cfgs), + .reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients }; /******************************************************************************* diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 4471ba091..b325e4e0d 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index edca16b7f..ccdf7f81d 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -8,6 +8,7 @@ #include #include #include +#include #define BOARD_SYSTEM_FPGA_BASE U(1) #define BASE_CONFIG_SMMU_DEVICES U(2) -- cgit v1.2.3 From 72e8caa7467e72134e45cb769b6dab39daf6b3c3 Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Wed, 16 Aug 2017 20:12:00 +0800 Subject: Tegra194: update cache operations supported by the ROC This patch updates the cache ops to use system registers in order to trigger cache flush/clean operations. Change-Id: I888abad22f22b8a33c7193b991fad8c4a78030d0 Signed-off-by: Steven Kao --- .../tegra/soc/t194/drivers/include/mce_private.h | 3 ++ .../soc/t194/drivers/mce/aarch64/nvg_helpers.S | 21 ++++++++ plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 57 ++++++++++++++-------- 3 files changed, 62 insertions(+), 19 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 3ac5333a0..415dc0f89 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -75,5 +75,8 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); void nvg_set_request_data(uint64_t req, uint64_t data); void nvg_set_request(uint64_t req); uint64_t nvg_get_result(void); +uint64_t nvg_cache_clean(void); +uint64_t nvg_cache_clean_inval(void); +uint64_t nvg_cache_inval_all(void); #endif /* __MCE_PRIVATE_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S index e6a6a9980..3c47208a1 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S @@ -10,6 +10,9 @@ .globl nvg_set_request_data .globl nvg_set_request .globl nvg_get_result + .globl nvg_cache_clean + .globl nvg_cache_clean_inval + .globl nvg_cache_inval_all /* void nvg_set_request_data(uint64_t req, uint64_t data) */ func nvg_set_request_data @@ -29,3 +32,21 @@ func nvg_get_result mrs x0, s3_0_c15_c1_3 ret endfunc nvg_get_result + +/* uint64_t nvg_cache_clean(void) */ +func nvg_cache_clean + mrs x0, s3_0_c15_c3_5 + ret +endfunc nvg_cache_clean + +/* uint64_t nvg_cache_clean_inval(void) */ +func nvg_cache_clean_inval + mrs x0, s3_0_c15_c3_6 + ret +endfunc nvg_cache_clean_inval + +/* uint64_t nvg_cache_inval_all(void) */ +func nvg_cache_inval_all + mrs x0, s3_0_c15_c3_7 + ret +endfunc nvg_cache_inval_all \ No newline at end of file diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index c7f659186..2eba1d33e 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -15,10 +15,8 @@ #include #include -extern void nvg_set_request_data(uint64_t req, uint64_t data); -extern void nvg_set_request(uint64_t req); -extern uint64_t nvg_get_result(void); - +#define ID_AFR0_EL1_CACHE_OPS_SHIFT 12 +#define ID_AFR0_EL1_CACHE_OPS_MASK 0xFU /* * Reports the major and minor version of this interface. * @@ -306,41 +304,62 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) /* * Cache clean operation for all CCPLEX caches. - * - * NVGDATA[0] cache_clean */ int32_t nvg_roc_clean_cache(void) { - nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL, - (uint64_t)CACHE_CLEAN_SET); + int32_t ret = 0; - return 0; + /* check if cache flush through mts is supported */ + if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & + ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { + if (nvg_cache_clean() == 0U) { + ERROR("%s: failed\n", __func__); + ret = EINVAL; + } + } else { + ret = EINVAL; + } + return ret; } /* * Cache clean and invalidate operation for all CCPLEX caches. - * - * NVGDATA[1] cache_clean_inval */ int32_t nvg_roc_flush_cache(void) { - nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL, - (uint64_t)CACHE_CLEAN_INVAL_SET); + int32_t ret = 0; - return 0; + /* check if cache flush through mts is supported */ + if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & + ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { + if (nvg_cache_clean_inval() == 0U) { + ERROR("%s: failed\n", __func__); + ret = EINVAL; + } + } else { + ret = EINVAL; + } + return ret; } /* * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches. - * - * NVGDATA[2] cache_clean_inval_tr */ int32_t nvg_roc_clean_cache_trbits(void) { - nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL, - (uint64_t)CACHE_CLEAN_INVAL_TR_SET); + int32_t ret = 0; - return 0; + /* check if cache flush through mts is supported */ + if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & + ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { + if (nvg_cache_inval_all() == 0U) { + ERROR("%s: failed\n", __func__); + ret = EINVAL; + } + } else { + ret = EINVAL; + } + return ret; } /* -- cgit v1.2.3 From 2bda92025bbc72f35b4a1bee76cfb1a2b002e5e6 Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Fri, 29 Sep 2017 18:09:17 +0800 Subject: Tegra194: update nvg header to v6.1 This patch updates t194_nvg.h to v6.1 and does not issue NVG commands for unsupported platforms. Change-Id: I506b594a70a3651d01a412ab79b3c8919b1d66f1 Signed-off-by: Steven Kao --- .../tegra/soc/t194/drivers/include/t194_nvg.h | 288 +++++++++++---------- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 56 +++- plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 18 +- 3 files changed, 215 insertions(+), 147 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h index 1fe462032..5a72680ac 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h @@ -20,77 +20,82 @@ */ enum { TEGRA_NVG_VERSION_MAJOR = 6, - TEGRA_NVG_VERSION_MINOR = 0, + TEGRA_NVG_VERSION_MINOR = 1 }; typedef enum { - TEGRA_NVG_CHANNEL_VERSION = 0, - TEGRA_NVG_CHANNEL_POWER_PERF = 1, - TEGRA_NVG_CHANNEL_POWER_MODES = 2, - TEGRA_NVG_CHANNEL_WAKE_TIME = 3, - TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, - TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, - TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, - // Value 7 reserved - TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, - // Value 9 reserved - TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, - TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, - // Values 12-42 reserved - TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, - TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, - TEGRA_NVG_CHANNEL_CC3_CTRL = 45, - TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, - TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL = 51, - // 52 FREQ FEEDBACK - TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, - TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, - TEGRA_NVG_CHANNEL_LAST_INDEX, + TEGRA_NVG_CHANNEL_VERSION = 0, + TEGRA_NVG_CHANNEL_POWER_PERF = 1, + TEGRA_NVG_CHANNEL_POWER_MODES = 2, + TEGRA_NVG_CHANNEL_WAKE_TIME = 3, + TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, + TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, + TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, + TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, + TEGRA_NVG_CHANNEL_SHUTDOWN = 42, + TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, + TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, + TEGRA_NVG_CHANNEL_CC3_CTRL = 45, + TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, + TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, + TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, + TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, + TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, + TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 60, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 61, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 62, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 63, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 64, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 65, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 66, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 67, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 68, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 69, + TEGRA_NVG_CHANNEL_LAST_INDEX } tegra_nvg_channel_id_t; - typedef enum { - // Value 0 reserved - NVG_STAT_QUERY_SC7_ENTRIES = 1, - // Values 2-5 reserved - NVG_STAT_QUERY_CC6_ENTRIES = 6, - NVG_STAT_QUERY_CG7_ENTRIES = 7, - // Values 8-9 reserved - NVG_STAT_QUERY_C6_ENTRIES = 10, - // Values 11-13 reserved - NVG_STAT_QUERY_C7_ENTRIES = 14, - // Values 15-31 reserved + NVG_STAT_QUERY_SC7_ENTRIES = 1, + NVG_STAT_QUERY_CC6_ENTRIES = 6, + NVG_STAT_QUERY_CG7_ENTRIES = 7, + NVG_STAT_QUERY_C6_ENTRIES = 10, + NVG_STAT_QUERY_C7_ENTRIES = 14, NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, - NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, - NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56, + NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, + NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56 } tegra_nvg_stat_query_t; - typedef enum { TEGRA_NVG_CORE_C0 = 0, TEGRA_NVG_CORE_C1 = 1, TEGRA_NVG_CORE_C6 = 6, TEGRA_NVG_CORE_C7 = 7, - TEGRA_NVG_CORE_WARMRSTREQ = 8, + TEGRA_NVG_CORE_WARMRSTREQ = 8 } tegra_nvg_core_sleep_state_t; typedef enum { TEGRA_NVG_CLUSTER_CC0 = 0, - TEGRA_NVG_CLUSTER_CC6 = 6, + TEGRA_NVG_CLUSTER_CC6 = 6 } tegra_nvg_cluster_sleep_state_t; typedef enum { - TEGRA_NVG_CCPLEX_CG0 = 0, - TEGRA_NVG_CCPLEX_CG7 = 1, + TEGRA_NVG_CG_CG0 = 0, + TEGRA_NVG_CG_CG7 = 1 } tegra_nvg_cluster_group_sleep_state_t; typedef enum { TEGRA_NVG_SYSTEM_SC0 = 0, TEGRA_NVG_SYSTEM_SC7 = 7, - TEGRA_NVG_SYSTEM_SC8 = 8, + TEGRA_NVG_SYSTEM_SC8 = 8 } tegra_nvg_system_sleep_state_t; // --------------------------------------------------------------------------- @@ -111,19 +116,33 @@ typedef union nvg_channel_1_data_u uint64_t flat; struct nvg_channel_1_data_s { - uint64_t perf_per_watt_mode : 1; - uint64_t reserved_63_1 : 63; + uint32_t perf_per_watt_mode : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; } bits; } nvg_channel_1_data_t; +typedef union +{ + uint64_t flat; + struct nvg_ccplex_cache_control_channel_t { + uint32_t gpu_ways : 5; + uint32_t reserved_7_5 : 3; + uint32_t gpu_only_ways : 5; + uint32_t reserved_31_13 : 19; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_ccplex_cache_control_channel_t; + typedef union nvg_channel_2_data_u { uint64_t flat; struct nvg_channel_2_data_s { - uint64_t reserved_1_0 : 2; - uint64_t battery_saver_mode : 1; - uint64_t reserved_63_3 : 61; + uint32_t reserved_1_0 : 2; + uint32_t battery_saver_mode : 1; + uint32_t reserved_31_3 : 29; + uint32_t reserved_63_32 : 32; } bits; } nvg_channel_2_data_t; @@ -131,8 +150,8 @@ typedef union { uint64_t flat; struct nvg_wake_time_channel_t { - uint64_t wake_time : 32; - uint64_t reserved_63_32 : 32; + uint32_t wake_time : 32; + uint32_t reserved_63_32 : 32; } bits; } nvg_wake_time_channel_t; @@ -140,18 +159,18 @@ typedef union { uint64_t flat; struct nvg_cstate_info_channel_t { - uint64_t cluster_state : 3; - uint64_t reserved_6_3 : 4; - uint64_t update_cluster : 1; - uint64_t cg_cstate : 3; - uint64_t reserved_14_11 : 4; - uint64_t update_cg : 1; - uint64_t system_cstate : 4; - uint64_t reserved_22_20 : 3; - uint64_t update_system : 1; - uint64_t reserved_30_24 : 7; - uint64_t update_wake_mask : 1; - uint64_t wake_mask : 32; + uint32_t cluster_state : 3; + uint32_t reserved_6_3 : 4; + uint32_t update_cluster : 1; + uint32_t cg_cstate : 3; + uint32_t reserved_14_11 : 4; + uint32_t update_cg : 1; + uint32_t system_cstate : 4; + uint32_t reserved_22_20 : 3; + uint32_t update_system : 1; + uint32_t reserved_30_24 : 7; + uint32_t update_wake_mask : 1; + uint32_t wake_mask : 32; } bits; } nvg_cstate_info_channel_t; @@ -159,20 +178,19 @@ typedef union { uint64_t flat; struct nvg_lower_bound_channel_t { - uint64_t crossover_value : 32; - uint64_t reserved_63_32 : 32; + uint32_t crossover_value : 32; + uint32_t reserved_63_32 : 32; } bits; } nvg_lower_bound_channel_t; - typedef union { uint64_t flat; struct nvg_cstate_stat_query_channel_t { - uint64_t unit_id : 4; - uint64_t reserved_15_4 : 12; - uint64_t stat_id : 16; - uint64_t reserved_63_32 : 32; + uint32_t unit_id : 4; + uint32_t reserved_15_4 : 12; + uint32_t stat_id : 16; + uint32_t reserved_63_32 : 32; } bits; } nvg_cstate_stat_query_channel_t; @@ -180,96 +198,102 @@ typedef union { uint64_t flat; struct nvg_is_sc7_allowed_channel_t { - uint64_t is_sc7_allowed : 1; - uint64_t reserved_63_32 : 63; + uint32_t is_sc7_allowed : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; } bits; } nvg_is_sc7_allowed_channel_t; - typedef union { uint64_t flat; struct nvg_core_online_channel_t { - uint64_t core_id : 4; - uint64_t reserved_63_4 : 60; + uint32_t core_id : 4; + uint32_t reserved_31_4 : 28; + uint32_t reserved_63_32 : 32; } bits; } nvg_core_online_channel_t; - typedef union { uint64_t flat; struct nvg_cc3_control_channel_t { - uint64_t freq_req : 8; - uint64_t reserved_30_8 : 23; - uint64_t enable : 1; - uint64_t reserved_63_32 : 32; + uint32_t freq_req : 8; + uint32_t reserved_30_8 : 23; + uint32_t enable : 1; + uint32_t reserved_63_32 : 32; } bits; } nvg_cc3_control_channel_t; +typedef enum { + TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, + TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, + TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, + TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, + TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, + TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, + TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, + TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX +} tegra_nvg_channel_update_gsc_gsc_enum_t; typedef union { uint64_t flat; - struct nvg_update_gsc_channel_t { - uint64_t gsc_enum : 16; - uint64_t reserved_63_16 : 48; + struct nvg_update_ccplex_gsc_channel_t { + uint32_t gsc_enum : 16; + uint32_t reserved_31_16 : 16; + uint32_t reserved_63_32 : 32; } bits; -} nvg_update_gsc_channel_t; - +} nvg_update_ccplex_gsc_channel_t; typedef union { uint64_t flat; - struct nvg_cache_inval_channel_t { - uint64_t cache_clean : 1; - uint64_t cache_clean_inval : 1; - uint64_t cache_clean_inval_tr : 1; - uint64_t reserved_63_3 : 61; + struct nvg_security_config_channel_t { + uint32_t strict_checking_enabled : 1; + uint32_t strict_checking_locked : 1; + uint32_t reserved_31_2 : 30; + uint32_t reserved_63_32 : 32; } bits; -} nvg_cache_inval_channel_t; - +} nvg_security_config_t; -/* GSC type define */ -typedef enum { - TEGRA_NVG_GSC_ALL=0, - TEGRA_NVG_GSC_NVDEC=1, - TEGRA_NVG_GSC_WPR1=2, - TEGRA_NVG_GSC_WPR2=3, - TEGRA_NVG_GSC_TSECA=4, - TEGRA_NVG_GSC_TSECB=5, - - TEGRA_NVG_GSC_BPMP=6, - TEGRA_NVG_GSC_APE=7, - TEGRA_NVG_GSC_SPE=8, - TEGRA_NVG_GSC_SCE=9, - TEGRA_NVG_GSC_APR=10, - TEGRA_NVG_GSC_TZRAM=11, - TEGRA_NVG_GSC_SE=12, - - TEGRA_NVG_GSC_DMCE=13, - TEGRA_NVG_GSC_BPMP_TO_DMCE=14, - TEGRA_NVG_GSC_BPMP_TO_SPE=16, - TEGRA_NVG_GSC_CPU_TZ_TO_BPMP=18, - TEGRA_NVG_GSC_CPU_NS_TO_BPMP=20, - TEGRA_NVG_GSC_IPC_SE_SPE_SCE_BPMP=22, - TEGRA_NVG_GSC_SC7_RESUME_FW=23, - - TEGRA_NVG_GSC_VPR_RESIZE=24, - TEGRA_NVG_GSC_RCE=25, - TEGRA_NVG_GSC_CV=26, - - TEGRA_NVG_GSC_BO_MTS_PACKAGE=28, - TEGRA_NVG_GSC_BO_MCE_PREBOOT=29, - - TEGRA_NVG_GSC_TZ_DRAM_IDX=34, - TEGRA_NVG_GSC_VPR_IDX=35, -} tegra_nvg_gsc_index_t; - -typedef enum { - TEGRA_NVG_CROSSOVER_C6 = 0, - TEGRA_NVG_CROSSOVER_CC6 = 1, - TEGRA_NVG_CROSSOVER_CG7 = 2, -} tegra_nvg_crossover_index_t; +typedef union +{ + uint64_t flat; + struct nvg_shutdown_channel_t { + uint32_t reboot : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_shutdown_t; -#endif // T194_NVG_H +#endif diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index 0a6515e1c..355a5474e 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -16,12 +16,25 @@ #include #include #include +#include #include #include #include #include #include +/* Handler to check if MCE firmware is supported */ +static bool mce_firmware_not_supported(void) +{ + bool status; + + /* these platforms do not load MCE firmware */ + status = tegra_platform_is_linsim() || tegra_platform_is_qt() || + tegra_platform_is_virt_dev_kit(); + + return status; +} + /******************************************************************************* * Common handler for all MCE commands ******************************************************************************/ @@ -174,7 +187,18 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, ******************************************************************************/ int32_t mce_update_gsc_videomem(void) { - return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_VPR_IDX); + int32_t ret; + + /* + * MCE firmware is not running on simulation platforms. + */ + if (mce_firmware_not_supported()) { + ret = -EINVAL; + } else { + ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR); + } + + return ret; } /******************************************************************************* @@ -182,7 +206,18 @@ int32_t mce_update_gsc_videomem(void) ******************************************************************************/ int32_t mce_update_gsc_tzdram(void) { - return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZ_DRAM_IDX); + int32_t ret; + + /* + * MCE firmware is not running on simulation platforms. + */ + if (mce_firmware_not_supported()) { + ret = -EINVAL; + } else { + ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM); + } + + return ret; } /******************************************************************************* @@ -190,7 +225,18 @@ int32_t mce_update_gsc_tzdram(void) ******************************************************************************/ int32_t mce_update_gsc_tzram(void) { - return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZRAM); + int32_t ret; + + /* + * MCE firmware is not running on simulation platforms. + */ + if (mce_firmware_not_supported()) { + ret = -EINVAL; + } else { + ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM); + } + + return ret; } /******************************************************************************* @@ -215,9 +261,7 @@ void mce_verify_firmware_version(void) /* * MCE firmware is not running on simulation platforms. */ - if ((tegra_platform_is_linsim() == 1U) || - (tegra_platform_is_virt_dev_kit() == 1U) || - (tegra_platform_is_qt() == 1U)) { + if (mce_firmware_not_supported()) { return; } diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index 2eba1d33e..6451f02c5 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -142,26 +142,26 @@ void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, * Indices gives MTS the crossover point in TSC ticks for when it becomes * no longer viable to enter the named state * - * Type 0 : NVGDATA[0:31]: C6 Lower bound - * Type 1 : NVGDATA[0:31]: CC6 Lower bound - * Type 2 : NVGDATA[0:31]: CG7 Lower bound + * Type 5 : NVGDATA[0:31]: C6 Lower bound + * Type 6 : NVGDATA[0:31]: CC6 Lower bound + * Type 8 : NVGDATA[0:31]: CG7 Lower bound */ int32_t nvg_update_crossover_time(uint32_t type, uint32_t time) { int32_t ret = 0; switch (type) { - case TEGRA_NVG_CROSSOVER_C6: + case TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND: nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND, (uint64_t)time); break; - case TEGRA_NVG_CROSSOVER_CC6: + case TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND: nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND, (uint64_t)time); break; - case TEGRA_NVG_CROSSOVER_CG7: + case TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND: nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND, (uint64_t)time); break; @@ -288,11 +288,11 @@ int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable) */ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) { - int32_t ret = 0; + int32_t ret; /* sanity check GSC ID */ - if (gsc_idx > (uint32_t)TEGRA_NVG_GSC_VPR_IDX) { - ERROR("%s: unknown gsc_idx (%d)\n", __func__, gsc_idx); + if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) { + ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx); ret = EINVAL; } else { nvg_set_request_data(TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, -- cgit v1.2.3 From 929a764d0cd89a4921d87503c2a1df0324942bcc Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Fri, 29 Sep 2017 16:32:34 +0800 Subject: Tegra194: increase MAX_MMAP_REGIONS macro value This patch increases the MAX_MMAP_REGIONS value to 30 from 25 to allow addition of more MMU mappings. Change-Id: I5c758c432f5cc77299608e25ba2fd92c3822379d Signed-off-by: Steven Kao --- plat/nvidia/tegra/soc/t194/platform_t194.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index d16aab8bb..faeaed35a 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -42,7 +42,7 @@ $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) MAX_XLAT_TABLES := 25 $(eval $(call add_define,MAX_XLAT_TABLES)) -MAX_MMAP_REGIONS := 25 +MAX_MMAP_REGIONS := 30 $(eval $(call add_define,MAX_MMAP_REGIONS)) # platform files -- cgit v1.2.3 From 1d9aad42dbf78bc860e3719d01a768f02d596784 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 3 Oct 2017 15:25:44 -0700 Subject: Tegra194: MC registers to allow CPU accesses to TZRAM This patch adds MC registers and macros to allow CPU to access TZRAM. Change-Id: I46da526aa760c89714f8898591981bb6cfb29237 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra_def.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index bdfa05145..8405f506e 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -65,6 +65,7 @@ #define MC_GSC_BASE_LO_MASK 0xFFFFF #define MC_GSC_BASE_HI_SHIFT 0 #define MC_GSC_BASE_HI_MASK 3 +#define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) /* TZDRAM carveout configuration registers */ #define MC_SECURITY_CFG0_0 0x70 @@ -95,7 +96,10 @@ #define MC_TZRAM_BASE_LO 0x2194 #define MC_TZRAM_BASE_HI 0x2198 #define MC_TZRAM_SIZE 0x219C -#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 +#define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) +#define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) +#define TZRAM_ALLOW_MPCORER (U(1) << 7) +#define TZRAM_ALLOW_MPCOREW (U(1) << 25) /* Memory Controller Reset Control registers */ #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) -- cgit v1.2.3 From a76d4617b42c4fe3c2d0859593dd3edd696a26df Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Fri, 13 Oct 2017 10:28:29 +0800 Subject: Tegra194: remove the GPU reset register macro There is a possibility that once we have checked that the GPU is in reset, some component can get still it out of reset. This patch removes the check register macro. Change-Id: Idbbba36f97e37c7db64ab9e42848a040ccd05acd Signed-off-by: Steven Kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 8405f506e..66c418d3c 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -189,8 +189,6 @@ * Tegra Clock and Reset Controller constants ******************************************************************************/ #define TEGRA_CAR_RESET_BASE 0x20000000 -#define TEGRA_GPU_RESET_REG_OFFSET 0x18UL -#define GPU_RESET_BIT (1UL << 0) /******************************************************************************* * XUSB PADCTL -- cgit v1.2.3 From 6152de3b347203e062d974b1af9b286b1f5c138c Mon Sep 17 00:00:00 2001 From: Anthony Zhou Date: Wed, 20 Sep 2017 17:18:56 +0800 Subject: Tegra194: mce: fix defects flagged by MISRA scan Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Fix variable essential type doesn't match [Rule 10.3] Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: Iaae2ecaba3caf1469c44910d4e6aed0661597a51 Signed-off-by: Anthony Zhou --- .../tegra/soc/t194/drivers/include/mce_private.h | 40 ++++++++--------- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 52 +++++++++++----------- plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 40 ++++++++--------- 3 files changed, 66 insertions(+), 66 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 415dc0f89..91e15247c 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -14,42 +14,42 @@ * Macros to prepare CSTATE info request ******************************************************************************/ /* Description of the parameters for UPDATE_CSTATE_INFO request */ -#define CLUSTER_CSTATE_MASK 0x7UL -#define CLUSTER_CSTATE_SHIFT 0X0UL -#define CLUSTER_CSTATE_UPDATE_BIT (1UL << 7) -#define CCPLEX_CSTATE_MASK 0x3UL -#define CCPLEX_CSTATE_SHIFT 8UL -#define CCPLEX_CSTATE_UPDATE_BIT (1UL << 15) -#define SYSTEM_CSTATE_MASK 0xFUL -#define SYSTEM_CSTATE_SHIFT 16UL -#define SYSTEM_CSTATE_UPDATE_BIT (1UL << 23) -#define CSTATE_WAKE_MASK_UPDATE_BIT (1UL << 31) -#define CSTATE_WAKE_MASK_SHIFT 32UL -#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFUL +#define CLUSTER_CSTATE_MASK 0x7U +#define CLUSTER_CSTATE_SHIFT 0X0U +#define CLUSTER_CSTATE_UPDATE_BIT (1U << 7) +#define CCPLEX_CSTATE_MASK 0x3U +#define CCPLEX_CSTATE_SHIFT 8U +#define CCPLEX_CSTATE_UPDATE_BIT (1U << 15) +#define SYSTEM_CSTATE_MASK 0xFU +#define SYSTEM_CSTATE_SHIFT 16U +#define SYSTEM_CSTATE_UPDATE_BIT (1U << 23) +#define CSTATE_WAKE_MASK_UPDATE_BIT (1U << 31) +#define CSTATE_WAKE_MASK_SHIFT 32U +#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU /******************************************************************************* * Auto-CC3 control macros ******************************************************************************/ -#define MCE_AUTO_CC3_FREQ_MASK 0xFFUL -#define MCE_AUTO_CC3_FREQ_SHIFT 0UL -#define MCE_AUTO_CC3_ENABLE_BIT (1UL << 31) +#define MCE_AUTO_CC3_FREQ_MASK 0xFFU +#define MCE_AUTO_CC3_FREQ_SHIFT 0U +#define MCE_AUTO_CC3_ENABLE_BIT (1U << 31) /******************************************************************************* * Core ID mask (bits 3:0 in the online request) ******************************************************************************/ -#define MCE_CORE_ID_MASK 0xFUL +#define MCE_CORE_ID_MASK 0xFU /******************************************************************************* * Cache control macros ******************************************************************************/ -#define CACHE_CLEAN_SET (1UL << 0) -#define CACHE_CLEAN_INVAL_SET (1UL << 1) -#define CACHE_CLEAN_INVAL_TR_SET (1UL << 2) +#define CACHE_CLEAN_SET (1U << 0) +#define CACHE_CLEAN_INVAL_SET (1U << 1) +#define CACHE_CLEAN_INVAL_TR_SET (1U << 2) /******************************************************************************* * C-state statistics macros ******************************************************************************/ -#define MCE_STAT_ID_SHIFT 16UL +#define MCE_STAT_ID_SHIFT 16U /* declarations for NVG handler functions */ uint64_t nvg_get_version(void); diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index 355a5474e..08f5db82c 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -46,11 +46,11 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, cpu_context_t *ctx = cm_get_context(NON_SECURE); gp_regs_t *gp_regs = get_gpregs_ctx(ctx); - assert(ctx); - assert(gp_regs); + assert(ctx != NULL); + assert(gp_regs != NULL); switch (cmd) { - case MCE_CMD_ENTER_CSTATE: + case (uint64_t)MCE_CMD_ENTER_CSTATE: ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1); if (ret < 0) { ERROR("%s: enter_cstate failed(%d)\n", __func__, ret); @@ -58,14 +58,14 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_UPDATE_CSTATE_INFO: + case (uint64_t)MCE_CMD_UPDATE_CSTATE_INFO: /* * get the parameters required for the update cstate info * command */ - arg3 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4)); - arg4 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5)); - arg5 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6)); + arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4); + arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5); + arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6); /* arg0 cluster * arg1 ccplex @@ -77,13 +77,13 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, nvg_update_cstate_info((uint32_t)arg0, (uint32_t)arg1, (uint32_t)arg2, (uint32_t)arg4, (uint8_t)arg5); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4), (arg3)); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5), (arg4)); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6), (arg5)); + write_ctx_reg(gp_regs, CTX_GPREG_X4, arg3); + write_ctx_reg(gp_regs, CTX_GPREG_X5, arg4); + write_ctx_reg(gp_regs, CTX_GPREG_X6, arg5); break; - case MCE_CMD_UPDATE_CROSSOVER_TIME: + case (uint64_t)MCE_CMD_UPDATE_CROSSOVER_TIME: ret = nvg_update_crossover_time((uint32_t)arg0, (uint32_t)arg1); if (ret < 0) { ERROR("%s: update_crossover_time failed(%d)\n", @@ -92,21 +92,21 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_READ_CSTATE_STATS: + case (uint64_t)MCE_CMD_READ_CSTATE_STATS: ret64 = nvg_get_cstate_stat_query_value(); /* update context to return cstate stats value */ - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64)); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64)); + write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); + write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64); break; - case MCE_CMD_WRITE_CSTATE_STATS: + case (uint64_t)MCE_CMD_WRITE_CSTATE_STATS: ret = nvg_set_cstate_stat_query_value(arg0); break; - case MCE_CMD_IS_SC7_ALLOWED: + case (uint64_t)MCE_CMD_IS_SC7_ALLOWED: ret = nvg_is_sc7_allowed(); if (ret < 0) { ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret); @@ -114,12 +114,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, } /* update context to return SC7 status value */ - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), ((uint64_t)ret)); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X3), ((uint64_t)ret)); + write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)ret); + write_ctx_reg(gp_regs, CTX_GPREG_X3, (uint64_t)ret); break; - case MCE_CMD_ONLINE_CORE: + case (uint64_t)MCE_CMD_ONLINE_CORE: ret = nvg_online_core((uint32_t)arg0); if (ret < 0) { ERROR("%s: online_core failed(%d)\n", __func__, ret); @@ -127,7 +127,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_CC3_CTRL: + case (uint64_t)MCE_CMD_CC3_CTRL: ret = nvg_cc3_ctrl((uint32_t)arg0, (uint8_t)arg2); if (ret < 0) { ERROR("%s: cc3_ctrl failed(%d)\n", __func__, ret); @@ -135,7 +135,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_READ_VERSIONS: + case (uint64_t)MCE_CMD_READ_VERSIONS: /* get the MCE firmware version */ ret64 = nvg_get_version(); @@ -143,12 +143,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, * version = minor(63:32) | major(31:0). Update context * to return major and minor version number. */ - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64 & (uint64_t)0xFFFF)); - write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64 >> 32)); + write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64 & 0xFFFFULL)); + write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64 >> 32U)); break; - case MCE_CMD_ROC_FLUSH_CACHE_TRBITS: + case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE_TRBITS: ret = nvg_roc_clean_cache_trbits(); if (ret < 0) { ERROR("%s: flush cache_trbits failed(%d)\n", __func__, @@ -157,7 +157,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_ROC_FLUSH_CACHE: + case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE: ret = nvg_roc_flush_cache(); if (ret < 0) { ERROR("%s: flush cache failed(%d)\n", __func__, ret); @@ -165,7 +165,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case MCE_CMD_ROC_CLEAN_CACHE: + case (uint64_t)MCE_CMD_ROC_CLEAN_CACHE: ret = nvg_roc_clean_cache(); if (ret < 0) { ERROR("%s: clean cache failed(%d)\n", __func__, ret); diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index 6451f02c5..d608bfa4d 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -25,7 +25,7 @@ */ uint64_t nvg_get_version(void) { - nvg_set_request(TEGRA_NVG_CHANNEL_VERSION); + nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION); return (uint64_t)nvg_get_result(); } @@ -37,7 +37,7 @@ uint64_t nvg_get_version(void) */ int32_t nvg_enable_power_perf_mode(void) { - nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 1U); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U); return 0; } @@ -49,7 +49,7 @@ int32_t nvg_enable_power_perf_mode(void) */ int32_t nvg_disable_power_perf_mode(void) { - nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 0U); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U); return 0; } @@ -61,7 +61,7 @@ int32_t nvg_disable_power_perf_mode(void) */ int32_t nvg_enable_power_saver_modes(void) { - nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 1U); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U); return 0; } @@ -73,7 +73,7 @@ int32_t nvg_enable_power_saver_modes(void) */ int32_t nvg_disable_power_saver_modes(void) { - nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 0U); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U); return 0; } @@ -87,7 +87,7 @@ int32_t nvg_disable_power_saver_modes(void) void nvg_set_wake_time(uint32_t wake_time) { /* time (TSC ticks) until the core is expected to get a wake event */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); } /* @@ -135,7 +135,7 @@ void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT; /* set the updated cstate info */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); } /* @@ -151,18 +151,18 @@ int32_t nvg_update_crossover_time(uint32_t type, uint32_t time) int32_t ret = 0; switch (type) { - case TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND: - nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND, + case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND: + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND, (uint64_t)time); break; - case TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND: - nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND, + case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND: + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND, (uint64_t)time); break; - case TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND: - nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND, + case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND: + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND, (uint64_t)time); break; @@ -196,7 +196,7 @@ int32_t nvg_set_cstate_stat_query_value(uint64_t data) (uint32_t)(data & MCE_CORE_ID_MASK)); ret = EINVAL; } else { - nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data); } return ret; @@ -209,7 +209,7 @@ int32_t nvg_set_cstate_stat_query_value(uint64_t data) */ uint64_t nvg_get_cstate_stat_query_value(void) { - nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE); + nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE); return (uint64_t)nvg_get_result(); } @@ -222,7 +222,7 @@ uint64_t nvg_get_cstate_stat_query_value(void) int32_t nvg_is_sc7_allowed(void) { /* issue command to check if SC7 is allowed */ - nvg_set_request(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED); + nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED); /* 1 = SC7 allowed, 0 = SC7 not allowed */ return (int32_t)nvg_get_result(); @@ -244,8 +244,8 @@ int32_t nvg_online_core(uint32_t core) ret = EINVAL; } else { /* get a core online */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, - (uint64_t)core & MCE_CORE_ID_MASK); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE, + (uint64_t)core & MCE_CORE_ID_MASK); } return ret; @@ -275,7 +275,7 @@ int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable) if (enable != 0U) { val = ((uint64_t)freq & MCE_AUTO_CC3_FREQ_MASK) | MCE_AUTO_CC3_ENABLE_BIT; } - nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val); + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, val); return 0; } @@ -295,7 +295,7 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx); ret = EINVAL; } else { - nvg_set_request_data(TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, + nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, (uint64_t)gsc_idx); } -- cgit v1.2.3 From b6533b56db2b1f3f96367604fd9b1e296f62b750 Mon Sep 17 00:00:00 2001 From: Anthony Zhou Date: Wed, 20 Sep 2017 17:44:43 +0800 Subject: Tegra194: fix defects flagged by MISRA scan Main fixes: Fix invalid use of function pointer [Rule 1.3] Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Fix implicit widening of composite assignment [Rule 10.6] Fixed if statement conditional to be essentially boolean [Rule 14.4] Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: I65a2b33e59aebb7746bd31544c79d57c3d5678c5 Signed-off-by: Anthony Zhou --- plat/nvidia/tegra/include/t194/tegra_def.h | 200 ++++++++++++------------ plat/nvidia/tegra/soc/t194/plat_memctrl.c | 6 +- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 150 ++++++++++-------- plat/nvidia/tegra/soc/t194/plat_secondary.c | 12 +- plat/nvidia/tegra/soc/t194/plat_setup.c | 109 +++++++------ plat/nvidia/tegra/soc/t194/plat_sip_calls.c | 38 +++-- plat/nvidia/tegra/soc/t194/plat_smmu.c | 4 +- 7 files changed, 277 insertions(+), 242 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 66c418d3c..2b578d5cf 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -14,9 +14,9 @@ * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' * parameter. ******************************************************************************/ -#define PSTATE_ID_CORE_IDLE 6 -#define PSTATE_ID_CORE_POWERDN 7 -#define PSTATE_ID_SOC_POWERDN 2 +#define PSTATE_ID_CORE_IDLE U(6) +#define PSTATE_ID_CORE_POWERDN U(7) +#define PSTATE_ID_SOC_POWERDN U(2) /******************************************************************************* * Platform power states (used by PSCI framework) @@ -24,192 +24,192 @@ * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID ******************************************************************************/ -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 8 +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(8) /******************************************************************************* * Secure IRQ definitions ******************************************************************************/ -#define TEGRA186_MAX_SEC_IRQS 5 -#define TEGRA186_BPMP_WDT_IRQ 46 -#define TEGRA186_SPE_WDT_IRQ 47 -#define TEGRA186_SCE_WDT_IRQ 48 -#define TEGRA186_TOP_WDT_IRQ 49 -#define TEGRA186_AON_WDT_IRQ 50 +#define TEGRA186_MAX_SEC_IRQS U(5) +#define TEGRA186_BPMP_WDT_IRQ U(46) +#define TEGRA186_SPE_WDT_IRQ U(47) +#define TEGRA186_SCE_WDT_IRQ U(48) +#define TEGRA186_TOP_WDT_IRQ U(49) +#define TEGRA186_AON_WDT_IRQ U(50) -#define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */ +#define TEGRA186_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */ /******************************************************************************* * Tegra Miscellanous register constants ******************************************************************************/ -#define TEGRA_MISC_BASE 0x00100000U +#define TEGRA_MISC_BASE U(0x00100000) -#define HARDWARE_REVISION_OFFSET 0x4U -#define MISCREG_EMU_REVID 0x3160U -#define BOARD_MASK_BITS 0xFFU -#define BOARD_SHIFT_BITS 24U -#define MISCREG_PFCFG 0x200CU +#define HARDWARE_REVISION_OFFSET U(0x4) +#define MISCREG_EMU_REVID U(0x3160) +#define BOARD_MASK_BITS U(0xFF) +#define BOARD_SHIFT_BITS U(24) +#define MISCREG_PFCFG U(0x200C) /******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ -#define TEGRA_MC_STREAMID_BASE 0x02C00000 -#define TEGRA_MC_BASE 0x02C10000 +#define TEGRA_MC_STREAMID_BASE U(0x02C00000) +#define TEGRA_MC_BASE U(0x02C10000) /* General Security Carveout register macros */ -#define MC_GSC_CONFIG_REGS_SIZE 0x40 -#define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1) -#define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0) -#define MC_GSC_SIZE_RANGE_4KB_SHIFT 27 -#define MC_GSC_BASE_LO_SHIFT 12 -#define MC_GSC_BASE_LO_MASK 0xFFFFF -#define MC_GSC_BASE_HI_SHIFT 0 -#define MC_GSC_BASE_HI_MASK 3 +#define MC_GSC_CONFIG_REGS_SIZE U(0x40) +#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) +#define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0) +#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) +#define MC_GSC_BASE_LO_SHIFT U(12) +#define MC_GSC_BASE_LO_MASK U(0xFFFFF) +#define MC_GSC_BASE_HI_SHIFT U(0) +#define MC_GSC_BASE_HI_MASK U(3) #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) /* TZDRAM carveout configuration registers */ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 -#define MC_SECURITY_CFG3_0 0x9BC +#define MC_SECURITY_CFG0_0 U(0x70) +#define MC_SECURITY_CFG1_0 U(0x74) +#define MC_SECURITY_CFG3_0 U(0x9BC) #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) /* Video Memory carveout configuration registers */ -#define MC_VIDEO_PROTECT_BASE_HI 0x978 -#define MC_VIDEO_PROTECT_BASE_LO 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c +#define MC_VIDEO_PROTECT_BASE_HI U(0x978) +#define MC_VIDEO_PROTECT_BASE_LO U(0x648) +#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) /* * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the * non-overlapping Video memory region */ -#define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 -#define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 -#define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 -#define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC -#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 +#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) +#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) +#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) +#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) +#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ -#define MC_TZRAM_CARVEOUT_CFG 0x2190 -#define MC_TZRAM_BASE_LO 0x2194 -#define MC_TZRAM_BASE_HI 0x2198 -#define MC_TZRAM_SIZE 0x219C +#define MC_TZRAM_CARVEOUT_CFG U(0x2190) +#define MC_TZRAM_BASE_LO U(0x2194) +#define MC_TZRAM_BASE_HI U(0x2198) +#define MC_TZRAM_SIZE U(0x219C) #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) #define TZRAM_ALLOW_MPCORER (U(1) << 7) #define TZRAM_ALLOW_MPCOREW (U(1) << 25) /* Memory Controller Reset Control registers */ -#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) -#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) -#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) -#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31) +#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28) +#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29) +#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30) +#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31) /******************************************************************************* * Tegra UART Controller constants ******************************************************************************/ -#define TEGRA_UARTA_BASE 0x03100000 -#define TEGRA_UARTB_BASE 0x03110000 -#define TEGRA_UARTC_BASE 0x0C280000 -#define TEGRA_UARTD_BASE 0x03130000 -#define TEGRA_UARTE_BASE 0x03140000 -#define TEGRA_UARTF_BASE 0x03150000 -#define TEGRA_UARTG_BASE 0x0C290000 +#define TEGRA_UARTA_BASE U(0x03100000) +#define TEGRA_UARTB_BASE U(0x03110000) +#define TEGRA_UARTC_BASE U(0x0C280000) +#define TEGRA_UARTD_BASE U(0x03130000) +#define TEGRA_UARTE_BASE U(0x03140000) +#define TEGRA_UARTF_BASE U(0x03150000) +#define TEGRA_UARTG_BASE U(0x0C290000) /******************************************************************************* * Tegra Fuse Controller related constants ******************************************************************************/ -#define TEGRA_FUSE_BASE 0x03820000 -#define OPT_SUBREVISION 0x248 -#define SUBREVISION_MASK 0xF +#define TEGRA_FUSE_BASE U(0x03820000) +#define OPT_SUBREVISION U(0x248) +#define SUBREVISION_MASK U(0xF) /******************************************************************************* * GICv2 & interrupt handling related constants ******************************************************************************/ -#define TEGRA_GICD_BASE 0x03881000 -#define TEGRA_GICC_BASE 0x03882000 +#define TEGRA_GICD_BASE U(0x03881000) +#define TEGRA_GICC_BASE U(0x03882000) /******************************************************************************* * Security Engine related constants ******************************************************************************/ -#define TEGRA_SE0_BASE 0x03AC0000 -#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C -#define TEGRA_PKA1_BASE 0x03AD0000 -#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 -#define TEGRA_RNG1_BASE 0x03AE0000 -#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 +#define TEGRA_SE0_BASE U(0x03AC0000) +#define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) +#define TEGRA_PKA1_BASE U(0x03AD0000) +#define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144) +#define TEGRA_RNG1_BASE U(0x03AE0000) +#define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) /******************************************************************************* * Tegra micro-seconds timer constants ******************************************************************************/ -#define TEGRA_TMRUS_BASE 0x0C2E0000 -#define TEGRA_TMRUS_SIZE 0x10000 +#define TEGRA_TMRUS_BASE U(0x0C2E0000) +#define TEGRA_TMRUS_SIZE U(0x10000) /******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ -#define TEGRA_PMC_BASE 0x0C360000 +#define TEGRA_PMC_BASE U(0x0C360000) /******************************************************************************* * Tegra scratch registers constants ******************************************************************************/ -#define TEGRA_SCRATCH_BASE 0x0C390000 -#define SECURE_SCRATCH_RSV1_LO 0x06C -#define SECURE_SCRATCH_RSV1_HI 0x070 -#define SECURE_SCRATCH_RSV6 0x094 -#define SECURE_SCRATCH_RSV11_LO 0x0BC -#define SECURE_SCRATCH_RSV11_HI 0x0C0 -#define SECURE_SCRATCH_RSV53_LO 0x20C -#define SECURE_SCRATCH_RSV53_HI 0x210 -#define SECURE_SCRATCH_RSV54_HI 0x218 -#define SECURE_SCRATCH_RSV55_LO 0x21C -#define SECURE_SCRATCH_RSV55_HI 0x220 +#define TEGRA_SCRATCH_BASE U(0x0C390000) +#define SECURE_SCRATCH_RSV1_LO U(0x06C) +#define SECURE_SCRATCH_RSV1_HI U(0x070) +#define SECURE_SCRATCH_RSV6 U(0x094) +#define SECURE_SCRATCH_RSV11_LO U(0x0BC) +#define SECURE_SCRATCH_RSV11_HI U(0x0C0) +#define SECURE_SCRATCH_RSV53_LO U(0x20C) +#define SECURE_SCRATCH_RSV53_HI U(0x210) +#define SECURE_SCRATCH_RSV54_HI U(0x218) +#define SECURE_SCRATCH_RSV55_LO U(0x21C) +#define SECURE_SCRATCH_RSV55_HI U(0x220) /******************************************************************************* * Tegra Memory Mapped Control Register Access Bus constants ******************************************************************************/ -#define TEGRA_MMCRAB_BASE 0x0E000000 +#define TEGRA_MMCRAB_BASE U(0x0E000000) /******************************************************************************* * Tegra SMMU Controller constants ******************************************************************************/ -#define TEGRA_SMMU0_BASE 0x12000000 -#define TEGRA_SMMU1_BASE 0x11000000 -#define TEGRA_SMMU2_BASE 0x10000000 +#define TEGRA_SMMU0_BASE U(0x12000000) +#define TEGRA_SMMU1_BASE U(0x11000000) +#define TEGRA_SMMU2_BASE U(0x10000000) /******************************************************************************* * Tegra TZRAM constants ******************************************************************************/ -#define TEGRA_TZRAM_BASE 0x40000000 -#define TEGRA_TZRAM_SIZE 0x40000 +#define TEGRA_TZRAM_BASE U(0x40000000) +#define TEGRA_TZRAM_SIZE U(0x40000) /******************************************************************************* * Tegra Clock and Reset Controller constants ******************************************************************************/ -#define TEGRA_CAR_RESET_BASE 0x20000000 +#define TEGRA_CAR_RESET_BASE U(0x20000000) /******************************************************************************* * XUSB PADCTL ******************************************************************************/ -#define TEGRA_XUSB_PADCTL_BASE (0x3520000U) -#define TEGRA_XUSB_PADCTL_SIZE (0x10000U) -#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) -#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) +#define TEGRA_XUSB_PADCTL_BASE U(0x3520000) +#define TEGRA_XUSB_PADCTL_SIZE U(0x10000) +#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c) +#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c) /******************************************************************************* * XUSB STREAMIDs ******************************************************************************/ -#define TEGRA_SID_XUSB_HOST (0x1bU) -#define TEGRA_SID_XUSB_DEV (0x1cU) -#define TEGRA_SID_XUSB_VF0 (0x5dU) -#define TEGRA_SID_XUSB_VF1 (0x5eU) -#define TEGRA_SID_XUSB_VF2 (0x5fU) -#define TEGRA_SID_XUSB_VF3 (0x60U) +#define TEGRA_SID_XUSB_HOST U(0x1b) +#define TEGRA_SID_XUSB_DEV U(0x1c) +#define TEGRA_SID_XUSB_VF0 U(0x5d) +#define TEGRA_SID_XUSB_VF1 U(0x5e) +#define TEGRA_SID_XUSB_VF2 U(0x5f) +#define TEGRA_SID_XUSB_VF3 U(0x60) #endif /* __TEGRA_DEF_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index a9341b16b..0bacc86c0 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -625,11 +625,11 @@ static void tegra194_memctrl_reconfig_mss_clients(void) ******************************************************************************/ static tegra_mc_settings_t tegra194_mc_settings = { .streamid_override_cfg = tegra194_streamid_override_regs, - .num_streamid_override_cfgs = ARRAY_SIZE(tegra194_streamid_override_regs), + .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), .streamid_security_cfg = tegra194_streamid_sec_cfgs, - .num_streamid_security_cfgs = ARRAY_SIZE(tegra194_streamid_sec_cfgs), + .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), .txn_override_cfg = tegra194_txn_override_cfgs, - .num_txn_override_cfgs = ARRAY_SIZE(tegra194_txn_override_cfgs), + .num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_txn_override_cfgs), .reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients }; diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index d77842984..9e24f4149 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -21,8 +21,6 @@ #include #include -extern void prepare_core_pwr_dwn(void); - extern void tegra_secure_entrypoint(void); #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM @@ -31,23 +29,23 @@ extern uint32_t __tegra186_cpu_reset_handler_data, __tegra186_cpu_reset_handler_end; /* TZDRAM offset for saving SMMU context */ -#define TEGRA186_SMMU_CTX_OFFSET 16 +#define TEGRA186_SMMU_CTX_OFFSET 16U #endif /* state id mask */ -#define TEGRA186_STATE_ID_MASK 0xF +#define TEGRA186_STATE_ID_MASK 0xFU /* constants to get power state's wake time */ -#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 -#define TEGRA186_WAKE_TIME_SHIFT 4 +#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0U +#define TEGRA186_WAKE_TIME_SHIFT 4U /* default core wake mask for CPU_SUSPEND */ -#define TEGRA194_CORE_WAKE_MASK 0x180c +#define TEGRA194_CORE_WAKE_MASK 0x180cU /* context size to save during system suspend */ -#define TEGRA186_SE_CONTEXT_SIZE 3 +#define TEGRA186_SE_CONTEXT_SIZE 3U static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; -static struct t18x_psci_percpu_data { - unsigned int wake_time; -} __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT]; +static struct t19x_psci_percpu_data { + uint32_t wake_time; +} __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT]; /* * tegra_fake_system_suspend acts as a boolean var controlling whether @@ -57,14 +55,16 @@ static struct t18x_psci_percpu_data { */ bool tegra_fake_system_suspend; -int32_t tegra_soc_validate_power_state(unsigned int power_state, +int32_t tegra_soc_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) { - int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; - int cpu = plat_my_core_pos(); + uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) & + TEGRA186_STATE_ID_MASK; + uint32_t cpu = plat_my_core_pos(); + int32_t ret = PSCI_E_SUCCESS; /* save the core wake time (in TSC ticks)*/ - percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) + t19x_percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) << TEGRA186_WAKE_TIME_SHIFT; /* @@ -74,8 +74,8 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, * from DRAM in that function, because the L2 cache is not flushed * unless the cluster is entering CC6/CC7. */ - clean_dcache_range((uint64_t)&percpu_data[cpu], - sizeof(percpu_data[cpu])); + clean_dcache_range((uint64_t)&t19x_percpu_data[cpu], + sizeof(t19x_percpu_data[cpu])); /* Sanity check the requested state id */ switch (state_id) { @@ -90,28 +90,29 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, default: ERROR("%s: unsupported state id (%d)\n", __func__, state_id); - return PSCI_E_INVALID_PARAMS; + ret = PSCI_E_INVALID_PARAMS; + break; } - return PSCI_E_SUCCESS; + return ret; } -int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) { const plat_local_state_t *pwr_domain_state; - unsigned int stateid_afflvl0, stateid_afflvl2; + uint8_t stateid_afflvl0, stateid_afflvl2; #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); uint64_t smmu_ctx_base; #endif uint32_t val; mce_cstate_info_t sc7_cstate_info = { - .cluster = TEGRA_NVG_CLUSTER_CC6, - .system = TEGRA_NVG_SYSTEM_SC7, - .system_state_force = 1, - .update_wake_mask = 1, + .cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6, + .system = (uint32_t)TEGRA_NVG_SYSTEM_SC7, + .system_state_force = 1U, + .update_wake_mask = 1U, }; - int cpu = plat_my_core_pos(); + uint32_t cpu = plat_my_core_pos(); int32_t ret = 0; /* get the state ID */ @@ -126,8 +127,8 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* Enter CPU idle/powerdown */ val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? - TEGRA_NVG_CORE_C6 : TEGRA_NVG_CORE_C7; - ret = mce_command_handler(MCE_CMD_ENTER_CSTATE, val, + (uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7; + ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val, percpu_data[cpu].wake_time, 0); assert(ret == 0); @@ -149,7 +150,7 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* save SMMU context */ smmu_ctx_base = params_from_bl2->tzdram_base + ((uintptr_t)&__tegra186_cpu_reset_handler_data - - (uintptr_t)tegra186_cpu_reset_handler) + + (uintptr_t)&tegra186_cpu_reset_handler) + TEGRA186_SMMU_CTX_OFFSET; tegra_smmu_save_context((uintptr_t)smmu_ctx_base); #else @@ -162,17 +163,23 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) mce_update_cstate_info(&sc7_cstate_info); do { - val = mce_command_handler( - MCE_CMD_IS_SC7_ALLOWED, - TEGRA_NVG_CORE_C7, + val = (uint32_t)mce_command_handler( + (uint32_t)MCE_CMD_IS_SC7_ALLOWED, + (uint32_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, - 0); - } while (val == 0); - - /* Instruct the MCE to enter system suspend state */ - (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, - TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); + 0U); + } while (val == 0U); + + /* Instruct the MCE to enter system suspend state */ + ret = mce_command_handler( + (uint64_t)MCE_CMD_ENTER_CSTATE, + (uint64_t)TEGRA_NVG_CORE_C7, + MCE_CORE_SLEEP_TIME_INFINITE, + 0U); + assert(ret == 0); } + } else { + ; /* do nothing */ } return PSCI_E_SUCCESS; @@ -182,20 +189,21 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) * Platform handler to calculate the proper target power level at the * specified affinity level ******************************************************************************/ -plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, +plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, const plat_local_state_t *states, - unsigned int ncpu) + uint32_t ncpu) { plat_local_state_t target = *states; - int cluster_powerdn = 1; - int core_pos = read_mpidr() & MPIDR_CPU_MASK; + int32_t cluster_powerdn = 1; + uint32_t core_pos = (uint32_t)read_mpidr() & MPIDR_CPU_MASK; + uint32_t num_cpus = ncpu, pos = 0; mce_cstate_info_t cstate_info = { 0 }; /* get the current core's power state */ - target = *(states + core_pos); + target = states[core_pos]; /* CPU suspend */ - if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) { + if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CORE_POWERDN)) { /* Program default wake mask */ cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; @@ -204,17 +212,20 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, } /* CPU off */ - if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) { + if ((lvl == MPIDR_AFFLVL1) && (target == PLAT_MAX_OFF_STATE)) { /* find out the number of ON cpus in the cluster */ do { - target = *states++; - if (target != PLAT_MAX_OFF_STATE) + target = states[pos]; + if (target != PLAT_MAX_OFF_STATE) { cluster_powerdn = 0; - } while (--ncpu); + } + --num_cpus; + pos++; + } while (num_cpus != 0U); /* Enable cluster powerdn from last CPU in the cluster */ - if (cluster_powerdn) { + if (cluster_powerdn != 0) { /* Enable CC6 */ /* todo */ @@ -234,20 +245,21 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, } /* System Suspend */ - if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN)) + if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN)) { return PSTATE_ID_SOC_POWERDN; + } /* default state */ return PSCI_LOCAL_STATE_RUN; } #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM -int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) { const plat_local_state_t *pwr_domain_state = target_state->pwr_domain_state; plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); - unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & + uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & TEGRA186_STATE_ID_MASK; uint64_t val; u_register_t ns_sctlr_el1; @@ -264,7 +276,6 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); - /* * In fake suspend mode, ensure that the loopback procedure * towards system suspend exit is started, instead of calling @@ -294,11 +305,12 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) } #endif -int tegra_soc_pwr_domain_on(u_register_t mpidr) +int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) { - uint32_t target_cpu = mpidr & MPIDR_CPU_MASK; - uint32_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> + uint64_t target_cpu = mpidr & MPIDR_CPU_MASK; + uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; + int32_t ret = 0; if (target_cluster > MPIDR_AFFLVL1) { ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr); @@ -306,16 +318,19 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr) } /* construct the target CPU # */ - target_cpu += (target_cluster << 1); + target_cpu += (target_cluster << 1U); - mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); + ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U); + if (ret < 0) { + return PSCI_E_DENIED; + } return PSCI_E_SUCCESS; } -int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) { - int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; + uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; /* * Reset power state info for CPUs when onlining, we set @@ -353,18 +368,21 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) return PSCI_E_SUCCESS; } -int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) { - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; int32_t ret = 0; + (void)target_state; + /* Disable Denver's DCO operations */ - if (impl == DENVER_IMPL) + if (impl == DENVER_IMPL) { denver_disable_dco(); + } /* Turn off CPU */ - ret = mce_command_handler(MCE_CMD_ENTER_CSTATE, - TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); + ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, + (uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U); assert(ret == 0); return PSCI_E_SUCCESS; @@ -384,7 +402,7 @@ __dead2 void tegra_soc_prepare_system_off(void) } } -int tegra_soc_prepare_system_reset(void) +int32_t tegra_soc_prepare_system_reset(void) { return PSCI_E_SUCCESS; } diff --git a/plat/nvidia/tegra/soc/t194/plat_secondary.c b/plat/nvidia/tegra/soc/t194/plat_secondary.c index f5e56b9b0..c54ca28b8 100644 --- a/plat/nvidia/tegra/soc/t194/plat_secondary.c +++ b/plat/nvidia/tegra/soc/t194/plat_secondary.c @@ -12,11 +12,11 @@ #include #include -#define MISCREG_CPU_RESET_VECTOR 0x2000 -#define MISCREG_AA64_RST_LOW 0x2004 -#define MISCREG_AA64_RST_HIGH 0x2008 +#define MISCREG_CPU_RESET_VECTOR 0x2000U +#define MISCREG_AA64_RST_LOW 0x2004U +#define MISCREG_AA64_RST_HIGH 0x2008U -#define CPU_RESET_MODE_AA64 1 +#define CPU_RESET_MODE_AA64 1U extern void tegra_secure_entrypoint(void); @@ -44,11 +44,11 @@ void plat_secondary_setup(void) memcpy((void *)((uintptr_t)cpu_reset_handler_base), (void *)(uintptr_t)tegra186_cpu_reset_handler, (uintptr_t)&__tegra186_smmu_ctx_start - - (uintptr_t)tegra186_cpu_reset_handler); + (uintptr_t)&tegra186_cpu_reset_handler); #endif addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; - addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff); + addr_high = (uint32_t)((cpu_reset_handler_base >> 32U) & 0x7ffU); /* write lower 32 bits first, then the upper 11 bits */ mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index b325e4e0d..08bd71073 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -32,7 +32,7 @@ * the number of power domains at the highest power level. ******************************************************************************* */ -const unsigned char tegra_power_domain_tree_desc[] = { +static const uint8_t tegra_power_domain_tree_desc[] = { /* No of root nodes */ 1, /* No of clusters */ @@ -50,7 +50,7 @@ const unsigned char tegra_power_domain_tree_desc[] = { /******************************************************************************* * This function returns the Tegra default topology tree information. ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) +const uint8_t *plat_get_power_domain_tree_desc(void) { return tegra_power_domain_tree_desc; } @@ -59,46 +59,46 @@ const unsigned char *plat_get_power_domain_tree_desc(void) * Table of regions to map using the MMU. */ static const mmap_region_t tegra_mmap[] = { - MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), {0} }; @@ -114,7 +114,7 @@ const mmap_region_t *plat_get_mmio_map(void) /******************************************************************************* * Handler to get the System Counter Frequency ******************************************************************************/ -unsigned int plat_get_syscnt_freq2(void) +uint32_t plat_get_syscnt_freq2(void) { return 31250000; } @@ -135,18 +135,23 @@ static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { TEGRA_UARTD_BASE, TEGRA_UARTE_BASE, TEGRA_UARTF_BASE, - TEGRA_UARTG_BASE, + TEGRA_UARTG_BASE }; /******************************************************************************* * Retrieve the UART controller base to be used as the console ******************************************************************************/ -uint32_t plat_get_console_from_id(int id) +uint32_t plat_get_console_from_id(int32_t id) { - if (id > TEGRA186_MAX_UART_PORTS) - return 0; + uint32_t ret; - return tegra186_uart_addresses[id]; + if (id > TEGRA186_MAX_UART_PORTS) { + ret = 0; + } else { + ret = tegra186_uart_addresses[id]; + } + + return ret; } /******************************************************************************* @@ -189,7 +194,7 @@ void plat_early_platform_setup(void) * Known Limitations: * If xusb interface disables SMMU in XUSB DT in non-virtualization * setup then there will be SMMU fault. We need to use WAR at - * https://git-master.nvidia.com/r/1529227/ to the issue. + * https:\\git-master.nvidia.com/r/1529227/ to the issue. * * More details can be found in the bug 1971161 */ @@ -246,15 +251,15 @@ static const irq_sec_cfg_t tegra186_sec_irqs[] = { ******************************************************************************/ void plat_gic_setup(void) { - tegra_gic_setup(tegra186_sec_irqs, - sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); + tegra_gic_setup(tegra186_sec_irqs, (uint32_t)ARRAY_SIZE(tegra186_sec_irqs); /* * Initialize the FIQ handler only if the platform supports any * FIQ interrupt sources. */ - if (sizeof(tegra186_sec_irqs) > 0) + if (sizeof(tegra186_sec_irqs) > 0U) { tegra_fiq_handler_setup(); + } } /******************************************************************************* diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index 4b6a901db..38802845d 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -18,10 +18,13 @@ #include #include -extern uint32_t tegra186_system_powerdn_state; - extern bool tegra_fake_system_suspend; +/******************************************************************************* + * Offset to read the ref_clk counter value + ******************************************************************************/ +#define REF_CLK_OFFSET 4ULL + /******************************************************************************* * Tegra186 SiP SMCs ******************************************************************************/ @@ -51,7 +54,7 @@ extern bool tegra_fake_system_suspend; /******************************************************************************* * This function is responsible for handling all T186 SiP calls ******************************************************************************/ -int plat_sip_handler(uint32_t smc_fid, +int32_t plat_sip_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, @@ -60,15 +63,21 @@ int plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags) { - int mce_ret; + int32_t mce_ret, ret = -ENOTSUP; + uint32_t local_smc_fid = smc_fid; + uint64_t local_x1 = x1; + + (void)x4; + (void)cookie; + (void)flags; /* * Convert SMC FID to SMC64 until the linux driver uses * SMC64 encoding. */ - smc_fid |= (SMC_64 << FUNCID_CC_SHIFT); + local_smc_fid |= (SMC_64 << FUNCID_CC_SHIFT); - switch (smc_fid) { + switch (local_smc_fid) { /* * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - @@ -94,18 +103,20 @@ int plat_sip_handler(uint32_t smc_fid, case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: /* clean up the high bits */ - smc_fid &= MCE_CMD_MASK; + local_smc_fid &= MCE_CMD_MASK; /* execute the command and store the result */ mce_ret = mce_command_handler(smc_fid, x1, x2, x3); - write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret); + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, (uint64_t)mce_ret); - return 0; + ret = 0; + break; case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE: /* clean up the high bits */ - x1 = (uint32_t)x1; + local_x1 = (uint32_t)x1; + (void)local_x1; /* * SC8 is a special Tegra186 system state where the CPUs and @@ -113,7 +124,8 @@ int plat_sip_handler(uint32_t smc_fid, * alive. */ - return 0; + ret = 0; + break; case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND: /* @@ -126,7 +138,7 @@ int plat_sip_handler(uint32_t smc_fid, if (tegra_platform_is_virt_dev_kit()) { tegra_fake_system_suspend = true; - return 0; + ret = 0; } break; @@ -135,5 +147,5 @@ int plat_sip_handler(uint32_t smc_fid, break; } - return -ENOTSUP; + return ret; } diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index ccdf7f81d..8913a0117 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -16,7 +16,7 @@ static uint32_t tegra_misc_read_32(uint32_t off) { - return mmio_read_32(TEGRA_MISC_BASE + off); + return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off); } /******************************************************************************* @@ -417,7 +417,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { smmu_regs_t *plat_get_smmu_ctx(void) { /* index of _END_OF_TABLE_ */ - tegra194_smmu_context[0].val = ARRAY_SIZE(tegra194_smmu_context) - 1; + tegra194_smmu_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_smmu_context) - 1U; return tegra194_smmu_context; } -- cgit v1.2.3 From 4a5524eb3d141451e574c1b375816aa0c44165cc Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 17 Oct 2017 10:53:33 -0700 Subject: Tegra194: sanity check target cluster during core power on This patch sanity checks the target cluster value, during core power on, by comparing it against the maximum number of clusters supported by the platform. Reported by: Rohit Khanna Change-Id: I556ce17a58271cc119c86fae0a4d34267f08b338 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 9e24f4149..47a502a11 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -312,7 +312,7 @@ int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) MPIDR_AFFINITY_BITS; int32_t ret = 0; - if (target_cluster > MPIDR_AFFLVL1) { + if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) { ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr); return PSCI_E_NOT_PRESENT; } -- cgit v1.2.3 From 08c085dc2ee6a8e48fb3ed06271dd374331826b1 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 19 Oct 2017 12:02:17 -0700 Subject: Tegra194: mce: remove unsupported functionality This patch cleans up the mce driver files to remove all the unsupported functionality. The MCE/NVG interface is not restricted to the EL3 space, so clients can issue commands to the MCE firmware directly. Change-Id: Idcebc42f31805f9c1abe1c1edc17850151aca11d Signed-off-by: Varun Wadekar --- .../tegra/soc/t194/drivers/include/mce_private.h | 20 ---- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 108 +-------------------- plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 105 -------------------- plat/nvidia/tegra/soc/t194/plat_sip_calls.c | 106 ++------------------ 4 files changed, 10 insertions(+), 329 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 91e15247c..32e7a532a 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -7,7 +7,6 @@ #ifndef __MCE_PRIVATE_H__ #define __MCE_PRIVATE_H__ -#include #include /******************************************************************************* @@ -27,25 +26,11 @@ #define CSTATE_WAKE_MASK_SHIFT 32U #define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU -/******************************************************************************* - * Auto-CC3 control macros - ******************************************************************************/ -#define MCE_AUTO_CC3_FREQ_MASK 0xFFU -#define MCE_AUTO_CC3_FREQ_SHIFT 0U -#define MCE_AUTO_CC3_ENABLE_BIT (1U << 31) - /******************************************************************************* * Core ID mask (bits 3:0 in the online request) ******************************************************************************/ #define MCE_CORE_ID_MASK 0xFU -/******************************************************************************* - * Cache control macros - ******************************************************************************/ -#define CACHE_CLEAN_SET (1U << 0) -#define CACHE_CLEAN_INVAL_SET (1U << 1) -#define CACHE_CLEAN_INVAL_TR_SET (1U << 2) - /******************************************************************************* * C-state statistics macros ******************************************************************************/ @@ -60,16 +45,11 @@ int32_t nvg_disable_power_saver_modes(void); void nvg_set_wake_time(uint32_t wake_time); void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask); -int32_t nvg_update_crossover_time(uint32_t type, uint32_t time); int32_t nvg_set_cstate_stat_query_value(uint64_t data); uint64_t nvg_get_cstate_stat_query_value(void); int32_t nvg_is_sc7_allowed(void); int32_t nvg_online_core(uint32_t core); -int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable); int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); -int32_t nvg_roc_flush_cache(void); -int32_t nvg_roc_clean_cache(void); -int32_t nvg_roc_clean_cache_trbits(void); int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); void nvg_set_request_data(uint64_t req, uint64_t data); diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index 08f5db82c..f6edd58ad 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -41,13 +40,7 @@ static bool mce_firmware_not_supported(void) int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, uint64_t arg2) { - uint64_t ret64 = 0, arg3, arg4, arg5; int32_t ret = 0; - cpu_context_t *ctx = cm_get_context(NON_SECURE); - gp_regs_t *gp_regs = get_gpregs_ctx(ctx); - - assert(ctx != NULL); - assert(gp_regs != NULL); switch (cmd) { case (uint64_t)MCE_CMD_ENTER_CSTATE: @@ -58,65 +51,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case (uint64_t)MCE_CMD_UPDATE_CSTATE_INFO: - /* - * get the parameters required for the update cstate info - * command - */ - arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4); - arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5); - arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6); - - /* arg0 cluster - * arg1 ccplex - * arg2 system - * arg3 sys_state_force => T19x not support - * arg4 wake_mask - * arg5 update_wake_mask - */ - nvg_update_cstate_info((uint32_t)arg0, (uint32_t)arg1, - (uint32_t)arg2, (uint32_t)arg4, (uint8_t)arg5); - - write_ctx_reg(gp_regs, CTX_GPREG_X4, arg3); - write_ctx_reg(gp_regs, CTX_GPREG_X5, arg4); - write_ctx_reg(gp_regs, CTX_GPREG_X6, arg5); - - break; - - case (uint64_t)MCE_CMD_UPDATE_CROSSOVER_TIME: - ret = nvg_update_crossover_time((uint32_t)arg0, (uint32_t)arg1); - if (ret < 0) { - ERROR("%s: update_crossover_time failed(%d)\n", - __func__, ret); - } - - break; - - case (uint64_t)MCE_CMD_READ_CSTATE_STATS: - ret64 = nvg_get_cstate_stat_query_value(); - - /* update context to return cstate stats value */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); - write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64); - - break; - - case (uint64_t)MCE_CMD_WRITE_CSTATE_STATS: - ret = nvg_set_cstate_stat_query_value(arg0); - - break; - case (uint64_t)MCE_CMD_IS_SC7_ALLOWED: ret = nvg_is_sc7_allowed(); if (ret < 0) { ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret); - break; } - /* update context to return SC7 status value */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)ret); - write_ctx_reg(gp_regs, CTX_GPREG_X3, (uint64_t)ret); - break; case (uint64_t)MCE_CMD_ONLINE_CORE: @@ -127,55 +67,9 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, break; - case (uint64_t)MCE_CMD_CC3_CTRL: - ret = nvg_cc3_ctrl((uint32_t)arg0, (uint8_t)arg2); - if (ret < 0) { - ERROR("%s: cc3_ctrl failed(%d)\n", __func__, ret); - } - - break; - - case (uint64_t)MCE_CMD_READ_VERSIONS: - /* get the MCE firmware version */ - ret64 = nvg_get_version(); - - /* - * version = minor(63:32) | major(31:0). Update context - * to return major and minor version number. - */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64 & 0xFFFFULL)); - write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64 >> 32U)); - - break; - - case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE_TRBITS: - ret = nvg_roc_clean_cache_trbits(); - if (ret < 0) { - ERROR("%s: flush cache_trbits failed(%d)\n", __func__, - ret); - } - - break; - - case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE: - ret = nvg_roc_flush_cache(); - if (ret < 0) { - ERROR("%s: flush cache failed(%d)\n", __func__, ret); - } - - break; - - case (uint64_t)MCE_CMD_ROC_CLEAN_CACHE: - ret = nvg_roc_clean_cache(); - if (ret < 0) { - ERROR("%s: clean cache failed(%d)\n", __func__, ret); - } - - break; - default: ERROR("unknown MCE command (%llu)\n", cmd); - ret = EINVAL; + ret = -EINVAL; break; } diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index d608bfa4d..498415a29 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -138,82 +138,6 @@ void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); } -/* - * Indices gives MTS the crossover point in TSC ticks for when it becomes - * no longer viable to enter the named state - * - * Type 5 : NVGDATA[0:31]: C6 Lower bound - * Type 6 : NVGDATA[0:31]: CC6 Lower bound - * Type 8 : NVGDATA[0:31]: CG7 Lower bound - */ -int32_t nvg_update_crossover_time(uint32_t type, uint32_t time) -{ - int32_t ret = 0; - - switch (type) { - case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND: - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND, - (uint64_t)time); - break; - - case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND: - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND, - (uint64_t)time); - break; - - case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND: - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND, - (uint64_t)time); - break; - - default: - ERROR("%s: unknown crossover type (%d)\n", __func__, type); - ret = EINVAL; - break; - } - - return ret; -} - -/* - * These NVG calls allow ARM SW to access CSTATE statistical information - * - * NVGDATA[0:3]: SW(RW) Core/cluster/cg id - * NVGDATA[16:31]: SW(RW) Stat id - */ -int32_t nvg_set_cstate_stat_query_value(uint64_t data) -{ - int32_t ret = 0; - - /* sanity check stat id and core id*/ - if ((data >> MCE_STAT_ID_SHIFT) > - (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) { - ERROR("%s: unknown stat id (%d)\n", __func__, - (uint32_t)(data >> MCE_STAT_ID_SHIFT)); - ret = EINVAL; - } else if ((data & MCE_CORE_ID_MASK) > (uint64_t)PLATFORM_CORE_COUNT) { - ERROR("%s: unknown core id (%d)\n", __func__, - (uint32_t)(data & MCE_CORE_ID_MASK)); - ret = EINVAL; - } else { - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data); - } - - return ret; -} - -/* - * The read-only value associated with the CSTATE_STAT_QUERY_REQUEST - * - * NVGDATA[0:63]: SW(R) Stat count - */ -uint64_t nvg_get_cstate_stat_query_value(void) -{ - nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE); - - return (uint64_t)nvg_get_result(); -} - /* * Return a non-zero value if the CCPLEX is able to enter SC7 * @@ -251,35 +175,6 @@ int32_t nvg_online_core(uint32_t core) return ret; } -/* - * Enables and controls the voltage/frequency hint for CC3. CC3 is disabled - * by default. - * - * NVGDATA[7:0] SW(RW) frequency request - * NVGDATA[31:31] SW(RW) enable bit - */ -int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable) -{ - uint64_t val = 0; - - /* - * If the enable bit is cleared, Auto-CC3 will be disabled by setting - * the SW visible frequency request registers for all non - * floorswept cores valid independent of StandbyWFI and disabling - * the IDLE frequency request register. If set, Auto-CC3 - * will be enabled by setting the ARM SW visible frequency - * request registers for all non floorswept cores to be enabled by - * StandbyWFI or the equivalent signal, and always keeping the IDLE - * frequency request register enabled. - */ - if (enable != 0U) { - val = ((uint64_t)freq & MCE_AUTO_CC3_FREQ_MASK) | MCE_AUTO_CC3_ENABLE_BIT; - } - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, val); - - return 0; -} - /* * MC GSC (General Security Carveout) register values are expected to be * changed by TrustZone ARM code after boot. diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index 38802845d..04602f046 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -20,36 +20,10 @@ extern bool tegra_fake_system_suspend; -/******************************************************************************* - * Offset to read the ref_clk counter value - ******************************************************************************/ -#define REF_CLK_OFFSET 4ULL - /******************************************************************************* * Tegra186 SiP SMCs ******************************************************************************/ -#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01 -#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02 #define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03 -#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00 -#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01 -#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02 -#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03 -#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04 -#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05 -#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06 -#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07 -#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08 -#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09 -#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A -#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B -#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C -#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D -#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E -#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F -#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10 -#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11 -#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12 /******************************************************************************* * This function is responsible for handling all T186 SiP calls @@ -63,88 +37,26 @@ int32_t plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags) { - int32_t mce_ret, ret = -ENOTSUP; - uint32_t local_smc_fid = smc_fid; - uint64_t local_x1 = x1; + int32_t ret = -ENOTSUP; + (void)x1; (void)x4; (void)cookie; (void)flags; - /* - * Convert SMC FID to SMC64 until the linux driver uses - * SMC64 encoding. - */ - local_smc_fid |= (SMC_64 << FUNCID_CC_SHIFT); - - switch (local_smc_fid) { - - /* - * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - - * 0x82FFFFFF SiP SMC space - */ - case TEGRA_SIP_MCE_CMD_ENTER_CSTATE: - case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO: - case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME: - case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS: - case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS: - case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED: - case TEGRA_SIP_MCE_CMD_CC3_CTRL: - case TEGRA_SIP_MCE_CMD_ECHO_DATA: - case TEGRA_SIP_MCE_CMD_READ_VERSIONS: - case TEGRA_SIP_MCE_CMD_ENUM_FEATURES: - case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS: - case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA: - case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA: - case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE: - case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: - case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: - case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: - case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: - - /* clean up the high bits */ - local_smc_fid &= MCE_CMD_MASK; - - /* execute the command and store the result */ - mce_ret = mce_command_handler(smc_fid, x1, x2, x3); - write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, (uint64_t)mce_ret); - - ret = 0; - break; - - case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE: - - /* clean up the high bits */ - local_x1 = (uint32_t)x1; - (void)local_x1; - + if (smc_fid == TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND) { /* - * SC8 is a special Tegra186 system state where the CPUs and - * DRAM are powered down but the other subsystem is still - * alive. - */ - - ret = 0; - break; - - case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND: - /* - * System suspend mode is set if the platform ATF is running is - * VDK and there is a debug SIP call. This mode ensures that the - * debug path is excercied, instead of regular code path to suit - * the pre-silicon platform needs. These include replacing the - * the call to WFI with calls to system suspend exit procedures. + * System suspend mode is set if the platform ATF is + * running on VDK and there is a debug SIP call. This mode + * ensures that the debug path is exercised, instead of + * regular code path to suit the pre-silicon platform needs. + * This includes replacing the call to WFI, with calls to + * system suspend exit procedures. */ if (tegra_platform_is_virt_dev_kit()) { - tegra_fake_system_suspend = true; ret = 0; } - - break; - - default: - break; } return ret; -- cgit v1.2.3 From 159baa4802e7ff1039e4f9451f854bda5ddeea41 Mon Sep 17 00:00:00 2001 From: Anthony Zhou Date: Wed, 25 Oct 2017 18:17:08 +0800 Subject: Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation Rule 8.4, A compatible declaration shall be visible when an object or function with external linkage is defined. Add function delaration to the header file. Add suffix U to the unsigned constant define. Change-Id: I54eba913a5fa38e4fdf3655931dc421d9510c691 Signed-off-by: Anthony Zhou --- plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h | 3 +++ plat/nvidia/tegra/soc/t194/plat_sip_calls.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 32e7a532a..966c90bb3 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -50,6 +50,9 @@ uint64_t nvg_get_cstate_stat_query_value(void); int32_t nvg_is_sc7_allowed(void); int32_t nvg_online_core(uint32_t core); int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); +int32_t nvg_roc_clean_cache(void); +int32_t nvg_roc_flush_cache(void); +int32_t nvg_roc_clean_cache_trbits(void); int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); void nvg_set_request_data(uint64_t req, uint64_t data); diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index 04602f046..03dad8540 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -23,7 +23,7 @@ extern bool tegra_fake_system_suspend; /******************************************************************************* * Tegra186 SiP SMCs ******************************************************************************/ -#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03 +#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03U /******************************************************************************* * This function is responsible for handling all T186 SiP calls -- cgit v1.2.3 From 192fd367a017ff8e63a55e3ff5c771bf4bbaf041 Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Mon, 23 Oct 2017 18:35:14 +0800 Subject: Tegra194: rename secure scratch register macros This patch renames all the secure scratch registers to reflect their usage. This is a list of all the macros being renamed: - SECURE_SCRATCH_RSV44_* -> SCRATCH_BOOT_PARAMS_ADDR_* - SECURE_SCRATCH_RSV97 -> SCRATCH_SECURE_BOOTP_FCFG - SECURE_SCRATCH_RSV99_* -> SCRATCH_SMMU_TABLE_ADDR_* - SECURE_SCRATCH_RSV109_* -> SCRATCH_RESET_VECTOR_* Change-Id: I838ece3da39bc4be8f349782e99bac777755fa39 Signed-off-by: Steven Kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 25 +++++++++++++++---------- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 2 +- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 2 +- plat/nvidia/tegra/soc/t194/plat_secondary.c | 4 ++-- plat/nvidia/tegra/soc/t194/plat_setup.c | 4 ++-- plat/nvidia/tegra/soc/t194/plat_smmu.c | 2 +- 6 files changed, 22 insertions(+), 17 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 2b578d5cf..0037b49e3 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -156,16 +156,21 @@ * Tegra scratch registers constants ******************************************************************************/ #define TEGRA_SCRATCH_BASE U(0x0C390000) -#define SECURE_SCRATCH_RSV1_LO U(0x06C) -#define SECURE_SCRATCH_RSV1_HI U(0x070) -#define SECURE_SCRATCH_RSV6 U(0x094) -#define SECURE_SCRATCH_RSV11_LO U(0x0BC) -#define SECURE_SCRATCH_RSV11_HI U(0x0C0) -#define SECURE_SCRATCH_RSV53_LO U(0x20C) -#define SECURE_SCRATCH_RSV53_HI U(0x210) -#define SECURE_SCRATCH_RSV54_HI U(0x218) -#define SECURE_SCRATCH_RSV55_LO U(0x21C) -#define SECURE_SCRATCH_RSV55_HI U(0x220) +#define SECURE_SCRATCH_RSV44_LO U(0x1C4) +#define SECURE_SCRATCH_RSV44_HI U(0x1C8) +#define SECURE_SCRATCH_RSV97 U(0x36C) +#define SECURE_SCRATCH_RSV99_LO U(0x37C) +#define SECURE_SCRATCH_RSV99_HI U(0x380) +#define SECURE_SCRATCH_RSV109_LO U(0x3CC) +#define SECURE_SCRATCH_RSV109_HI U(0x3D0) + +#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV44_LO +#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV44_HI +#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97 +#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO +#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI +#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO +#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI /******************************************************************************* * Tegra Memory Mapped Control Register Access Bus constants diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 0bacc86c0..0a6345dcc 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -639,4 +639,4 @@ static tegra_mc_settings_t tegra194_mc_settings = { tegra_mc_settings_t *tegra_get_mc_settings(void) { return &tegra194_mc_settings; -} +} \ No newline at end of file diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 47a502a11..0932061d0 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -144,7 +144,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* save 'Secure Boot' Processor Feature Config Register */ val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val); + mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM /* save SMMU context */ diff --git a/plat/nvidia/tegra/soc/t194/plat_secondary.c b/plat/nvidia/tegra/soc/t194/plat_secondary.c index c54ca28b8..0947c31b3 100644 --- a/plat/nvidia/tegra/soc/t194/plat_secondary.c +++ b/plat/nvidia/tegra/soc/t194/plat_secondary.c @@ -55,8 +55,8 @@ void plat_secondary_setup(void) mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); /* save reset vector to be used during SYSTEM_SUSPEND exit */ - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_LO, + mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, addr_low); - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI, + mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, addr_high); } diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 08bd71073..195ee9f9d 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -269,7 +269,7 @@ struct tegra_bl31_params *plat_get_bl31_params(void) { uint32_t val; - val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); + val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR); return (struct tegra_bl31_params *)(uintptr_t)val; } @@ -281,7 +281,7 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void) { uint32_t val; - val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); + val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR); return (plat_params_from_bl2_t *)(uintptr_t)val; } diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index 8913a0117..19917a9ce 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -436,4 +436,4 @@ uint32_t plat_get_num_smmu_devices(void) } return ret_num; -} +} \ No newline at end of file -- cgit v1.2.3 From 6eb3c188abf8bcccc3f833972084fbf796e4eb02 Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Fri, 23 Jun 2017 16:18:58 +0800 Subject: Tegra194: drivers: SE and RNG1/PKA1 context save support This patch adds the driver, to implement the programming sequence to save/restore hardware context, during System Suspend/Resume. Change-Id: If851a81cd4e699b58a0055d0be7f145759792ee9 Signed-off-by: Steven Kao Signed-off-by: Jeff Tsai --- plat/nvidia/tegra/include/t194/tegra_def.h | 8 +- plat/nvidia/tegra/soc/t194/drivers/include/se.h | 13 ++ plat/nvidia/tegra/soc/t194/drivers/se/se.c | 213 +++++++++++++++++++++ plat/nvidia/tegra/soc/t194/drivers/se/se_private.h | 84 ++++++++ plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 49 +++-- plat/nvidia/tegra/soc/t194/platform_t194.mk | 1 + 6 files changed, 338 insertions(+), 30 deletions(-) create mode 100644 plat/nvidia/tegra/soc/t194/drivers/include/se.h create mode 100644 plat/nvidia/tegra/soc/t194/drivers/se/se.c create mode 100644 plat/nvidia/tegra/soc/t194/drivers/se/se_private.h diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 0037b49e3..bc98fa3ae 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -135,11 +135,13 @@ * Security Engine related constants ******************************************************************************/ #define TEGRA_SE0_BASE U(0x03AC0000) -#define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) +#define SE0_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) +#define SE0_AES0_ENTROPY_SRC_AGE_CTRL U(0x2FC) #define TEGRA_PKA1_BASE U(0x03AD0000) -#define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144) +#define SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144) +#define PKA1_MUTEX_WATCHDOG_NS_LIMIT SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL #define TEGRA_RNG1_BASE U(0x03AE0000) -#define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) +#define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) /******************************************************************************* * Tegra micro-seconds timer constants diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/se.h b/plat/nvidia/tegra/soc/t194/drivers/include/se.h new file mode 100644 index 000000000..6e656f677 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/drivers/include/se.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SE_H__ +#define __SE_H__ + +int32_t tegra_se_suspend(void); +void tegra_se_resume(void); + +#endif /* __SE_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c new file mode 100644 index 000000000..3df670c92 --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "se_private.h" + +/******************************************************************************* + * Constants and Macros + ******************************************************************************/ +#define ERR_STATUS_SW_CLEAR U(0xFFFFFFFF) +#define INT_STATUS_SW_CLEAR U(0xFFFFFFFF) +#define MAX_TIMEOUT_MS U(100) /* Timeout in 100ms */ +#define NUM_SE_REGS_TO_SAVE U(4) + +/******************************************************************************* + * Data structure and global variables + ******************************************************************************/ +static uint32_t se_regs[NUM_SE_REGS_TO_SAVE]; + +/* + * Check that SE operation has completed after kickoff. + * + * This function is invoked after an SE operation has been started, + * and it checks the following conditions: + * + * 1. SE_STATUS = IDLE + * 2. AHB bus data transfer is complete. + * 3. SE_ERR_STATUS is clean. + */ +static bool tegra_se_is_operation_complete(void) +{ + uint32_t val = 0, timeout = 0, sha_status, aes_status; + int32_t ret = 0; + bool se_is_busy, txn_has_errors, txn_successful; + + /* + * Poll the status register to check if the operation + * completed. + */ + do { + val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS); + se_is_busy = !!(val & CTX_SAVE_AUTO_SE_BUSY); + + /* sleep until SE finishes */ + if (se_is_busy) { + mdelay(1); + timeout++; + } + + } while (se_is_busy && (timeout < MAX_TIMEOUT_MS)); + + /* any transaction errors? */ + txn_has_errors = (tegra_se_read_32(SHA_ERR_STATUS) != 0U) || + (tegra_se_read_32(AES0_ERR_STATUS) != 0U); + + /* transaction successful? */ + sha_status = tegra_se_read_32(SHA_INT_STATUS) & SHA_SE_OP_DONE; + aes_status = tegra_se_read_32(AES0_INT_STATUS) & AES0_SE_OP_DONE; + txn_successful = (sha_status == SHA_SE_OP_DONE) && + (aes_status == AES0_SE_OP_DONE); + + if ((timeout == MAX_TIMEOUT_MS) || txn_has_errors || !txn_successful) { + ERROR("%s: Atomic context save operation failed!\n", + __func__); + ret = -ECANCELED; + } + + return (ret == 0); +} + +/* + * Wait for SE engine to be idle and clear any pending interrupts, before + * starting the next SE operation. + */ +static bool tegra_se_is_ready(void) +{ + int32_t ret = 0; + uint32_t val = 0, timeout = 0; + bool se_is_ready; + + /* Wait for previous operation to finish */ + do { + val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS); + se_is_ready = (val == CTX_SAVE_AUTO_SE_READY); + + /* sleep until SE is ready */ + if (!se_is_ready) { + mdelay(1); + timeout++; + } + + } while (!se_is_ready && (timeout < MAX_TIMEOUT_MS)); + + if (timeout == MAX_TIMEOUT_MS) { + ERROR("%s: SE is not ready!\n", __func__); + ret = -ETIMEDOUT; + } + + /* Clear any pending interrupts from previous operation */ + tegra_se_write_32(AES0_INT_STATUS, INT_STATUS_SW_CLEAR); + tegra_se_write_32(AES1_INT_STATUS, INT_STATUS_SW_CLEAR); + tegra_se_write_32(RSA_INT_STATUS, INT_STATUS_SW_CLEAR); + tegra_se_write_32(SHA_INT_STATUS, INT_STATUS_SW_CLEAR); + + /* Clear error status for each engine seen from current port */ + tegra_se_write_32(AES0_ERR_STATUS, ERR_STATUS_SW_CLEAR); + tegra_se_write_32(AES1_ERR_STATUS, ERR_STATUS_SW_CLEAR); + tegra_se_write_32(RSA_ERR_STATUS, ERR_STATUS_SW_CLEAR); + tegra_se_write_32(SHA_ERR_STATUS, ERR_STATUS_SW_CLEAR); + + return (ret == 0); +} + +/* + * During System Suspend, this handler triggers the hardware context + * save operation. + */ +static int32_t tegra_se_save_context(void) +{ + int32_t ret = -ECANCELED; + + /* + * 1. Ensure all SE Driver including RNG1/PKA1 are shut down. + * TSEC/R5s are powergated/idle. All tasks on SE1~SE4, RNG1, + * PKA1 are wrapped up. SE0 is ready for use. + * 2. Clear interrupt/error in SE0 status register. + * 3. Scrub SE0 register to avoid false failure for illegal + * configuration. Probably not needed, dependent on HW + * implementation. + * 4. Check SE is ready for HW CTX_SAVE by polling + * SE_CTX_SAVE_AUTO_STATUS.SE_READY. + * + * Steps 1-4 are executed by tegra_se_is_ready(). + * + * 5. Issue context save command. + * 6. Check SE is busy with CTX_SAVE, the command in step5 was not + * dropped for ongoing traffic in any of SE port/engine. + * 7. Poll SE register or wait for SE APB interrupt for task completion + * a. Polling: Read SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE + * b. Interrupt: After receiving interrupt from SE APB, read + * SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE. + * 8. Check AES0 and SHA ERR_STATUS to ensure no error case. + * 9. Check AES0 and SHA INT_STATUS to ensure operation has successfully + * completed. + * + * Steps 6-9 are executed by tegra_se_is_operation_complete(). + */ + if (tegra_se_is_ready()) { + + /* Issue context save command */ + tegra_se_write_32(AES0_OPERATION, SE_OP_CTX_SAVE); + + /* Wait for operation to finish */ + if (tegra_se_is_operation_complete()) { + ret = 0; + } + } + + return ret; +} + +/* + * Handler to power down the SE hardware blocks - SE, RNG1 and PKA1. This + * needs to be called only during System Suspend. + */ +int32_t tegra_se_suspend(void) +{ + int32_t ret = 0; + + /* save SE registers */ + se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT); + se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL); + se_regs[2] = mmio_read_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT); + se_regs[3] = mmio_read_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT); + + /* Save SE context. The BootROM restores it during System Resume */ + ret = tegra_se_save_context(); + if (ret != 0) { + ERROR("%s: context save failed (%d)\n", __func__, ret); + } + + return ret; +} + +/* + * Handler to power up the SE hardware block(s) during System Resume. + */ +void tegra_se_resume(void) +{ + /* + * When TZ takes over after System Resume, TZ should first reconfigure + * SE_MUTEX_WATCHDOG_NS_LIMIT, PKA1_MUTEX_WATCHDOG_NS_LIMIT, + * RNG1_MUTEX_WATCHDOG_NS_LIMIT and SE_ENTROPY_SRC_AGE_CTRL before + * other operations. + */ + mmio_write_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT, se_regs[0]); + mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]); + mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]); + mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]); +} diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h new file mode 100644 index 000000000..7d531bb9d --- /dev/null +++ b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SE_PRIVATE_H__ +#define __SE_PRIVATE_H__ + +#include + +/* SE0_INT_ENABLE_0 */ +#define SE0_INT_ENABLE U(0x88) +#define SE0_DISABLE_ALL_INT U(0x0) + +/* SE0_INT_STATUS_0 */ +#define SE0_INT_STATUS U(0x8C) +#define SE0_CLEAR_ALL_INT_STATUS U(0x3F) + +/* SE0_SHA_INT_STATUS_0 */ +#define SHA_INT_STATUS U(0x184) +#define SHA_SE_OP_DONE (U(1) << 4) + +/* SE0_SHA_ERR_STATUS_0 */ +#define SHA_ERR_STATUS U(0x18C) + +/* SE0_AES0_INT_STATUS_0 */ +#define AES0_INT_STATUS U(0x2F0) +#define AES0_SE_OP_DONE (U(1) << 4) + +/* SE0_AES0_ERR_STATUS_0 */ +#define AES0_ERR_STATUS U(0x2F8) + +/* SE0_AES1_INT_STATUS_0 */ +#define AES1_INT_STATUS U(0x4F0) + +/* SE0_AES1_ERR_STATUS_0 */ +#define AES1_ERR_STATUS U(0x4F8) + +/* SE0_RSA_INT_STATUS_0 */ +#define RSA_INT_STATUS U(0x758) + +/* SE0_RSA_ERR_STATUS_0 */ +#define RSA_ERR_STATUS U(0x760) + +/* SE0_AES0_OPERATION_0 */ +#define AES0_OPERATION U(0x238) +#define OP_MASK_BITS U(0x7) +#define SE_OP_CTX_SAVE U(0x3) + +/* SE0_AES0_CTX_SAVE_CONFIG_0 */ +#define CTX_SAVE_CONFIG U(0x2D4) + +/* SE0_AES0_CTX_SAVE_AUTO_STATUS_0 */ +#define CTX_SAVE_AUTO_STATUS U(0x300) +#define CTX_SAVE_AUTO_SE_READY U(0xFF) +#define CTX_SAVE_AUTO_SE_BUSY (U(0x1) << 31) + +/* SE0_AES0_CTX_SAVE_AUTO_CTRL_0 */ +#define CTX_SAVE_AUTO_CTRL U(0x304) +#define SE_CTX_SAVE_AUTO_EN (U(0x1) << 0) +#define SE_CTX_SAVE_AUTO_LOCK_EN (U(0x1) << 1) + +/* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_0 */ +#define CTX_SAVE_AUTO_START_ADDR U(0x308) + +/* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_HI_0 */ +#define CTX_SAVE_AUTO_START_ADDR_HI U(0x30C) + +/******************************************************************************* + * Inline functions definition + ******************************************************************************/ + +static inline uint32_t tegra_se_read_32(uint32_t offset) +{ + return mmio_read_32(TEGRA_SE0_BASE + offset); +} + +static inline void tegra_se_write_32(uint32_t offset, uint32_t val) +{ + mmio_write_32(TEGRA_SE0_BASE + offset, val); +} + +#endif /* __SE_PRIVATE_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 0932061d0..51c3e9572 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -5,21 +5,24 @@ */ #include -#include #include +#include +#include + +#include #include -#include -#include #include +#include #include +#include +#include #include #include -#include +#include #include -#include -#include #include -#include +#include +#include extern void tegra_secure_entrypoint(void); @@ -39,10 +42,7 @@ extern uint32_t __tegra186_cpu_reset_handler_data, #define TEGRA186_WAKE_TIME_SHIFT 4U /* default core wake mask for CPU_SUSPEND */ #define TEGRA194_CORE_WAKE_MASK 0x180cU -/* context size to save during system suspend */ -#define TEGRA186_SE_CONTEXT_SIZE 3U -static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; static struct t19x_psci_percpu_data { uint32_t wake_time; } __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT]; @@ -134,14 +134,6 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { - /* save SE registers */ - se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + - SE_MUTEX_WATCHDOG_NS_LIMIT); - se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE + - RNG_MUTEX_WATCHDOG_NS_LIMIT); - se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE + - PKA_MUTEX_WATCHDOG_NS_LIMIT); - /* save 'Secure Boot' Processor Feature Config Register */ val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); @@ -157,6 +149,15 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) tegra_smmu_save_context(0); #endif + /* + * Suspend SE, RNG1 and PKA1 only on silcon and fpga, + * since VDK does not support atomic se ctx save + */ + if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { + ret = tegra_se_suspend(); + assert(ret == 0); + } + if (!tegra_fake_system_suspend) { /* Prepare for system suspend */ @@ -345,18 +346,12 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) * context if we are. */ if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { - - mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, - se_regs[0]); - mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, - se_regs[1]); - mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT, - se_regs[2]); - /* Init SMMU */ - tegra_smmu_init(); + /* Resume SE, RNG1 and PKA1 */ + tegra_se_resume(); + /* * Reset power state info for the last core doing SC7 * entry and exit, we set deepest power state as CC7 diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index faeaed35a..ef72eb7f8 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -54,6 +54,7 @@ BL31_SOURCES += lib/cpus/aarch64/denver.S \ ${SOC_DIR}/drivers/mce/mce.c \ ${SOC_DIR}/drivers/mce/nvg.c \ ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ + ${SOC_DIR}/drivers/se/se.c \ ${SOC_DIR}/plat_memctrl.c \ ${SOC_DIR}/plat_psci_handlers.c \ ${SOC_DIR}/plat_setup.c \ -- cgit v1.2.3 From 4b412b507a1648e00fb68b06b8cbe88ac9239317 Mon Sep 17 00:00:00 2001 From: Vignesh Radhakrishnan Date: Sat, 4 Nov 2017 16:36:23 -0700 Subject: Tegra194: mce: fix cg_cstate encoding format This patch does the following: - cstate_info variable is used to pass on requested cstate to mce - Currently, cg_cstate is encoded using 2 bits(bits 8, 9) in cstate_info - cg_cstate values can range from 0 to 7, with 7 representing cg7 - Thus, cg_cstate is to be encoded using 3 bits (val: 0-7) - Fix this, as per ISS and ensure bits 8, 9, 10 are used Change-Id: Idff207e2a88b2f4654e4a956c27054bf5e8f69bb Signed-off-by: Vignesh Radhakrishnan --- plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h | 2 +- plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 966c90bb3..1970a2d17 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -16,7 +16,7 @@ #define CLUSTER_CSTATE_MASK 0x7U #define CLUSTER_CSTATE_SHIFT 0X0U #define CLUSTER_CSTATE_UPDATE_BIT (1U << 7) -#define CCPLEX_CSTATE_MASK 0x3U +#define CCPLEX_CSTATE_MASK 0x7U #define CCPLEX_CSTATE_SHIFT 8U #define CCPLEX_CSTATE_UPDATE_BIT (1U << 15) #define SYSTEM_CSTATE_MASK 0xFU diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index 498415a29..96b2b9113 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -96,7 +96,7 @@ void nvg_set_wake_time(uint32_t wake_time) * * NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE * NVGDATA[7]: SW(W), update cluster flag - * NVGDATA[8:9]: SW(RW), CG_CSTATE + * NVGDATA[8:10]: SW(RW), CG_CSTATE * NVGDATA[15]: SW(W), update ccplex flag * NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE * NVGDATA[23]: SW(W), update system flag -- cgit v1.2.3 From ac2cc6b091c34ba0a0d63ae5c8c8ee2f235fa7a1 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 7 Nov 2017 08:50:55 -0800 Subject: Tegra194: mce: display NVG header version during boot The MCE driver checks the NVG interface version during boot and disaplys the hardware and software versions on the console. The software version is being displayed as zero. This patch updates the prints to use the real NVG header version instead. Change-Id: I8e9d2e6c43a59a8a6d5ca7aa8153b940fce86709 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index f6edd58ad..8c7854e9c 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -167,8 +167,8 @@ void mce_verify_firmware_version(void) minor = (uint32_t)version; major = (uint32_t)(version >> 32); - INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor, - 0, 0); + INFO("MCE Version - HW=%u:%u, SW=%u:%u\n", major, minor, + TEGRA_NVG_VERSION_MAJOR, TEGRA_NVG_VERSION_MINOR); /* * Verify that the MCE firmware version and the interface header -- cgit v1.2.3 From 1c62509e89333bbb1b4c0b933d4b906e77206066 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 10 Nov 2017 11:04:42 -0800 Subject: Tegra194: cleanup references to Tegra186 This patch cleans up all references to the Tegra186 family of SoCs. Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra_def.h | 13 +++--- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 48 ++++++++------------- plat/nvidia/tegra/soc/t194/plat_secondary.c | 20 +++------ plat/nvidia/tegra/soc/t194/plat_setup.c | 56 +++++++------------------ plat/nvidia/tegra/soc/t194/plat_sip_calls.c | 4 +- plat/nvidia/tegra/soc/t194/plat_smmu.c | 4 +- plat/nvidia/tegra/soc/t194/plat_trampoline.S | 36 ++++++++-------- plat/nvidia/tegra/soc/t194/platform_t194.mk | 13 +----- 8 files changed, 66 insertions(+), 128 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index bc98fa3ae..a41c0cd7e 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -30,14 +30,11 @@ /******************************************************************************* * Secure IRQ definitions ******************************************************************************/ -#define TEGRA186_MAX_SEC_IRQS U(5) -#define TEGRA186_BPMP_WDT_IRQ U(46) -#define TEGRA186_SPE_WDT_IRQ U(47) -#define TEGRA186_SCE_WDT_IRQ U(48) -#define TEGRA186_TOP_WDT_IRQ U(49) -#define TEGRA186_AON_WDT_IRQ U(50) - -#define TEGRA186_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */ +#define TEGRA194_MAX_SEC_IRQS U(2) +#define TEGRA194_TOP_WDT_IRQ U(49) +#define TEGRA194_AON_WDT_IRQ U(50) + +#define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */ /******************************************************************************* * Tegra Miscellanous register constants diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 51c3e9572..4517ffed5 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -24,22 +24,18 @@ #include #include -extern void tegra_secure_entrypoint(void); - -#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM -extern void tegra186_cpu_reset_handler(void); -extern uint32_t __tegra186_cpu_reset_handler_data, - __tegra186_cpu_reset_handler_end; +extern void tegra194_cpu_reset_handler(void); +extern uint32_t __tegra194_cpu_reset_handler_data, + __tegra194_cpu_reset_handler_end; /* TZDRAM offset for saving SMMU context */ -#define TEGRA186_SMMU_CTX_OFFSET 16U -#endif +#define TEGRA194_SMMU_CTX_OFFSET 16U /* state id mask */ -#define TEGRA186_STATE_ID_MASK 0xFU +#define TEGRA194_STATE_ID_MASK 0xFU /* constants to get power state's wake time */ -#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0U -#define TEGRA186_WAKE_TIME_SHIFT 4U +#define TEGRA194_WAKE_TIME_MASK 0x0FFFFFF0U +#define TEGRA194_WAKE_TIME_SHIFT 4U /* default core wake mask for CPU_SUSPEND */ #define TEGRA194_CORE_WAKE_MASK 0x180cU @@ -59,13 +55,13 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) { uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) & - TEGRA186_STATE_ID_MASK; + TEGRA194_STATE_ID_MASK; uint32_t cpu = plat_my_core_pos(); int32_t ret = PSCI_E_SUCCESS; /* save the core wake time (in TSC ticks)*/ - t19x_percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) - << TEGRA186_WAKE_TIME_SHIFT; + t19x_percpu_data[cpu].wake_time = (power_state & TEGRA194_WAKE_TIME_MASK) + << TEGRA194_WAKE_TIME_SHIFT; /* * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that @@ -101,10 +97,8 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) { const plat_local_state_t *pwr_domain_state; uint8_t stateid_afflvl0, stateid_afflvl2; -#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); uint64_t smmu_ctx_base; -#endif uint32_t val; mce_cstate_info_t sc7_cstate_info = { .cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6, @@ -118,9 +112,9 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* get the state ID */ pwr_domain_state = target_state->pwr_domain_state; stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & - TEGRA186_STATE_ID_MASK; + TEGRA194_STATE_ID_MASK; stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & - TEGRA186_STATE_ID_MASK; + TEGRA194_STATE_ID_MASK; if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { @@ -138,16 +132,12 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); -#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM /* save SMMU context */ smmu_ctx_base = params_from_bl2->tzdram_base + - ((uintptr_t)&__tegra186_cpu_reset_handler_data - - (uintptr_t)&tegra186_cpu_reset_handler) + - TEGRA186_SMMU_CTX_OFFSET; + ((uintptr_t)&__tegra194_cpu_reset_handler_data - + (uintptr_t)&tegra194_cpu_reset_handler) + + TEGRA194_SMMU_CTX_OFFSET; tegra_smmu_save_context((uintptr_t)smmu_ctx_base); -#else - tegra_smmu_save_context(0); -#endif /* * Suspend SE, RNG1 and PKA1 only on silcon and fpga, @@ -254,14 +244,13 @@ plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, return PSCI_LOCAL_STATE_RUN; } -#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) { const plat_local_state_t *pwr_domain_state = target_state->pwr_domain_state; plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & - TEGRA186_STATE_ID_MASK; + TEGRA194_STATE_ID_MASK; uint64_t val; u_register_t ns_sctlr_el1; @@ -272,8 +261,8 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta * BL3-1 over to TZDRAM. */ val = params_from_bl2->tzdram_base + - ((uintptr_t)&__tegra186_cpu_reset_handler_end - - (uintptr_t)tegra186_cpu_reset_handler); + ((uintptr_t)&__tegra194_cpu_reset_handler_end - + (uintptr_t)&tegra194_cpu_reset_handler); memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); @@ -304,7 +293,6 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta return PSCI_E_SUCCESS; } -#endif int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) { diff --git a/plat/nvidia/tegra/soc/t194/plat_secondary.c b/plat/nvidia/tegra/soc/t194/plat_secondary.c index 0947c31b3..3905f8be9 100644 --- a/plat/nvidia/tegra/soc/t194/plat_secondary.c +++ b/plat/nvidia/tegra/soc/t194/plat_secondary.c @@ -18,12 +18,8 @@ #define CPU_RESET_MODE_AA64 1U -extern void tegra_secure_entrypoint(void); - -#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM -extern void tegra186_cpu_reset_handler(void); -extern uint64_t __tegra186_smmu_ctx_start; -#endif +extern void tegra194_cpu_reset_handler(void); +extern uint64_t __tegra194_smmu_ctx_start; /******************************************************************************* * Setup secondary CPU vectors @@ -31,21 +27,15 @@ extern uint64_t __tegra186_smmu_ctx_start; void plat_secondary_setup(void) { uint32_t addr_low, addr_high; -#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base; -#else - uint64_t cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint; -#endif INFO("Setting up secondary CPU boot\n"); -#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM memcpy((void *)((uintptr_t)cpu_reset_handler_base), - (void *)(uintptr_t)tegra186_cpu_reset_handler, - (uintptr_t)&__tegra186_smmu_ctx_start - - (uintptr_t)&tegra186_cpu_reset_handler); -#endif + (void *)(uintptr_t)tegra194_cpu_reset_handler, + (uintptr_t)&__tegra194_smmu_ctx_start - + (uintptr_t)&tegra194_cpu_reset_handler); addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; addr_high = (uint32_t)((cpu_reset_handler_base >> 32U) & 0x7ffU); diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 195ee9f9d..4b6ec8eaf 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -122,12 +122,12 @@ uint32_t plat_get_syscnt_freq2(void) /******************************************************************************* * Maximum supported UART controllers ******************************************************************************/ -#define TEGRA186_MAX_UART_PORTS 7 +#define TEGRA194_MAX_UART_PORTS 7 /******************************************************************************* * This variable holds the UART port base addresses ******************************************************************************/ -static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { +static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = { 0, /* undefined - treated as an error case */ TEGRA_UARTA_BASE, TEGRA_UARTB_BASE, @@ -145,10 +145,10 @@ uint32_t plat_get_console_from_id(int32_t id) { uint32_t ret; - if (id > TEGRA186_MAX_UART_PORTS) { + if (id > TEGRA194_MAX_UART_PORTS) { ret = 0; } else { - ret = tegra186_uart_addresses[id]; + ret = tegra194_uart_addresses[id]; } return ret; @@ -212,38 +212,12 @@ void plat_early_platform_setup(void) XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); } -/* Secure IRQs for Tegra186 */ -static const irq_sec_cfg_t tegra186_sec_irqs[] = { - [0] = { - TEGRA186_BPMP_WDT_IRQ, - TEGRA186_SEC_IRQ_TARGET_MASK, - INTR_TYPE_EL3, - }, - [1] = { - TEGRA186_BPMP_WDT_IRQ, - TEGRA186_SEC_IRQ_TARGET_MASK, - INTR_TYPE_EL3, - }, - [2] = { - TEGRA186_SPE_WDT_IRQ, - TEGRA186_SEC_IRQ_TARGET_MASK, - INTR_TYPE_EL3, - }, - [3] = { - TEGRA186_SCE_WDT_IRQ, - TEGRA186_SEC_IRQ_TARGET_MASK, - INTR_TYPE_EL3, - }, - [4] = { - TEGRA186_TOP_WDT_IRQ, - TEGRA186_SEC_IRQ_TARGET_MASK, - INTR_TYPE_EL3, - }, - [5] = { - TEGRA186_AON_WDT_IRQ, - TEGRA186_SEC_IRQ_TARGET_MASK, - INTR_TYPE_EL3, - }, +/* Secure IRQs for Tegra194 */ +static const interrupt_prop_t tegra194_interrupt_props[] = { + INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), + INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) }; /******************************************************************************* @@ -251,15 +225,13 @@ static const irq_sec_cfg_t tegra186_sec_irqs[] = { ******************************************************************************/ void plat_gic_setup(void) { - tegra_gic_setup(tegra186_sec_irqs, (uint32_t)ARRAY_SIZE(tegra186_sec_irqs); + tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props)); + tegra_gic_init(); /* - * Initialize the FIQ handler only if the platform supports any - * FIQ interrupt sources. + * Initialize the FIQ handler */ - if (sizeof(tegra186_sec_irqs) > 0U) { - tegra_fiq_handler_setup(); - } + tegra_fiq_handler_setup(); } /******************************************************************************* diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index 03dad8540..8873358cd 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -21,12 +21,12 @@ extern bool tegra_fake_system_suspend; /******************************************************************************* - * Tegra186 SiP SMCs + * Tegra194 SiP SMCs ******************************************************************************/ #define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03U /******************************************************************************* - * This function is responsible for handling all T186 SiP calls + * This function is responsible for handling all T194 SiP calls ******************************************************************************/ int32_t plat_sip_handler(uint32_t smc_fid, uint64_t x1, diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index 19917a9ce..1696d5910 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -20,7 +20,7 @@ static uint32_t tegra_misc_read_32(uint32_t off) } /******************************************************************************* - * Array to hold SMMU context for Tegra186 + * Array to hold SMMU context for Tegra194 ******************************************************************************/ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { _START_OF_TABLE_, @@ -436,4 +436,4 @@ uint32_t plat_get_num_smmu_devices(void) } return ret_num; -} \ No newline at end of file +} diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S index e3ee5e5a5..111fc1524 100644 --- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S @@ -10,13 +10,13 @@ #include #include -#define TEGRA186_SMMU_CTX_SIZE 0x490 +#define TEGRA194_SMMU_CTX_SIZE 0x490 .align 4 - .globl tegra186_cpu_reset_handler + .globl tegra194_cpu_reset_handler /* CPU reset handler routine */ -func tegra186_cpu_reset_handler +func tegra194_cpu_reset_handler /* * The TZRAM loses state during System Suspend. We use this * information to decide if the reset handler is running after a @@ -29,8 +29,8 @@ func tegra186_cpu_reset_handler /* resume from system suspend */ mov x0, #BL31_BASE - adr x1, __tegra186_cpu_reset_handler_end - adr x2, __tegra186_cpu_reset_handler_data + adr x1, __tegra194_cpu_reset_handler_end + adr x2, __tegra194_cpu_reset_handler_data ldr x2, [x2, #8] /* memcpy16 */ @@ -50,13 +50,13 @@ m_loop1: b.ne m_loop1 boot_cpu: - adr x0, __tegra186_cpu_reset_handler_data + adr x0, __tegra194_cpu_reset_handler_data ldr x0, [x0] br x0 -endfunc tegra186_cpu_reset_handler +endfunc tegra194_cpu_reset_handler /* - * Tegra186 reset data (offset 0x0 - 0x2490) + * Tegra194 reset data (offset 0x0 - 0x2490) * * 0x0000: secure world's entrypoint * 0x0008: BL31 size (RO + RW) @@ -65,19 +65,19 @@ endfunc tegra186_cpu_reset_handler */ .align 4 - .type __tegra186_cpu_reset_handler_data, %object - .globl __tegra186_cpu_reset_handler_data -__tegra186_cpu_reset_handler_data: + .type __tegra194_cpu_reset_handler_data, %object + .globl __tegra194_cpu_reset_handler_data +__tegra194_cpu_reset_handler_data: .quad tegra_secure_entrypoint .quad __BL31_END__ - BL31_BASE - .globl __tegra186_smmu_ctx_start -__tegra186_smmu_ctx_start: - .rept TEGRA186_SMMU_CTX_SIZE + .globl __tegra194_smmu_ctx_start +__tegra194_smmu_ctx_start: + .rept TEGRA194_SMMU_CTX_SIZE .quad 0 .endr - .size __tegra186_cpu_reset_handler_data, \ - . - __tegra186_cpu_reset_handler_data + .size __tegra194_cpu_reset_handler_data, \ + . - __tegra194_cpu_reset_handler_data .align 4 - .globl __tegra186_cpu_reset_handler_end -__tegra186_cpu_reset_handler_end: + .globl __tegra194_cpu_reset_handler_end +__tegra194_cpu_reset_handler_end: diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index ef72eb7f8..3db7334af 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -5,15 +5,9 @@ # # platform configs -ENABLE_AFI_DEVICE := 0 -$(eval $(call add_define,ENABLE_AFI_DEVICE)) - ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 0 $(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) -ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM := 1 -$(eval $(call add_define,ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM)) - RELOCATE_TO_BL31_BASE := 1 $(eval $(call add_define,RELOCATE_TO_BL31_BASE)) @@ -60,8 +54,5 @@ BL31_SOURCES += lib/cpus/aarch64/denver.S \ ${SOC_DIR}/plat_setup.c \ ${SOC_DIR}/plat_secondary.c \ ${SOC_DIR}/plat_sip_calls.c \ - ${SOC_DIR}/plat_smmu.c - -ifeq (${ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM}, 1) -BL31_SOURCES += ${SOC_DIR}/plat_trampoline.S -endif + ${SOC_DIR}/plat_smmu.c \ + ${SOC_DIR}/plat_trampoline.S -- cgit v1.2.3 From 653fc38026d223bd111a57826e169edef36c6486 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 10 Nov 2017 13:23:34 -0800 Subject: Tegra194: helper functions for CPU rst handler and SMMU ctx offset This patch adds a helper function to get the SMMU context's offset and uses another helper function to get the CPU trampoline offset. These helper functions are used by the System Suspend entry sequence to save the SMMU context and CPU reset handler to TZDRAM. Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra194_private.h | 15 +++++++++++ plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 8 +++--- plat/nvidia/tegra/soc/t194/plat_secondary.c | 28 +++++++++++--------- plat/nvidia/tegra/soc/t194/plat_trampoline.S | 31 +++++++++++++++++++++-- 4 files changed, 63 insertions(+), 19 deletions(-) create mode 100644 plat/nvidia/tegra/include/t194/tegra194_private.h diff --git a/plat/nvidia/tegra/include/t194/tegra194_private.h b/plat/nvidia/tegra/include/t194/tegra194_private.h new file mode 100644 index 000000000..f5de017bc --- /dev/null +++ b/plat/nvidia/tegra/include/t194/tegra194_private.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __TEGRA194_PRIVATE_H__ +#define __TEGRA194_PRIVATE_H__ + +void tegra194_cpu_reset_handler(void); +uint64_t tegra194_get_cpu_reset_handler_base(void); +uint64_t tegra194_get_cpu_reset_handler_size(void); +uint64_t tegra194_get_smmu_ctx_offset(void); + +#endif /* __TEGRA194_PRIVATE_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 4517ffed5..c25897d56 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -134,9 +135,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* save SMMU context */ smmu_ctx_base = params_from_bl2->tzdram_base + - ((uintptr_t)&__tegra194_cpu_reset_handler_data - - (uintptr_t)&tegra194_cpu_reset_handler) + - TEGRA194_SMMU_CTX_OFFSET; + tegra194_get_smmu_ctx_offset(); tegra_smmu_save_context((uintptr_t)smmu_ctx_base); /* @@ -261,8 +260,7 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta * BL3-1 over to TZDRAM. */ val = params_from_bl2->tzdram_base + - ((uintptr_t)&__tegra194_cpu_reset_handler_end - - (uintptr_t)&tegra194_cpu_reset_handler); + tegra194_get_cpu_reset_handler_size(); memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); diff --git a/plat/nvidia/tegra/soc/t194/plat_secondary.c b/plat/nvidia/tegra/soc/t194/plat_secondary.c index 3905f8be9..c397c91ba 100644 --- a/plat/nvidia/tegra/soc/t194/plat_secondary.c +++ b/plat/nvidia/tegra/soc/t194/plat_secondary.c @@ -9,18 +9,15 @@ #include #include #include +#include #include #include -#define MISCREG_CPU_RESET_VECTOR 0x2000U #define MISCREG_AA64_RST_LOW 0x2004U #define MISCREG_AA64_RST_HIGH 0x2008U #define CPU_RESET_MODE_AA64 1U -extern void tegra194_cpu_reset_handler(void); -extern uint64_t __tegra194_smmu_ctx_start; - /******************************************************************************* * Setup secondary CPU vectors ******************************************************************************/ @@ -28,17 +25,24 @@ void plat_secondary_setup(void) { uint32_t addr_low, addr_high; plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); - uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base; + uint64_t cpu_reset_handler_base, cpu_reset_handler_size; INFO("Setting up secondary CPU boot\n"); - memcpy((void *)((uintptr_t)cpu_reset_handler_base), - (void *)(uintptr_t)tegra194_cpu_reset_handler, - (uintptr_t)&__tegra194_smmu_ctx_start - - (uintptr_t)&tegra194_cpu_reset_handler); - - addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; - addr_high = (uint32_t)((cpu_reset_handler_base >> 32U) & 0x7ffU); + /* + * The BL31 code resides in the TZSRAM which loses state + * when we enter System Suspend. Copy the wakeup trampoline + * code to TZDRAM to help us exit from System Suspend. + */ + cpu_reset_handler_base = tegra194_get_cpu_reset_handler_base(); + cpu_reset_handler_size = tegra194_get_cpu_reset_handler_size(); + memcpy((void *)((uintptr_t)params_from_bl2->tzdram_base), + (void *)((uintptr_t)cpu_reset_handler_base), + cpu_reset_handler_size); + + /* TZDRAM base will be used as the "resume" address */ + addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; + addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); /* write lower 32 bits first, then the upper 11 bits */ mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S index 111fc1524..ea8cbef15 100644 --- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S @@ -70,8 +70,9 @@ endfunc tegra194_cpu_reset_handler __tegra194_cpu_reset_handler_data: .quad tegra_secure_entrypoint .quad __BL31_END__ - BL31_BASE - .globl __tegra194_smmu_ctx_start -__tegra194_smmu_ctx_start: + + .align 4 +__tegra194_smmu_context: .rept TEGRA194_SMMU_CTX_SIZE .quad 0 .endr @@ -81,3 +82,29 @@ __tegra194_smmu_ctx_start: .align 4 .globl __tegra194_cpu_reset_handler_end __tegra194_cpu_reset_handler_end: + + .globl tegra194_get_cpu_reset_handler_size + .globl tegra194_get_cpu_reset_handler_base + .globl tegra194_get_smmu_ctx_offset + +/* return size of the CPU reset handler */ +func tegra194_get_cpu_reset_handler_size + adr x0, __tegra194_cpu_reset_handler_end + adr x1, tegra194_cpu_reset_handler + sub x0, x0, x1 + ret +endfunc tegra194_get_cpu_reset_handler_size + +/* return the start address of the CPU reset handler */ +func tegra194_get_cpu_reset_handler_base + adr x0, tegra194_cpu_reset_handler + ret +endfunc tegra194_get_cpu_reset_handler_base + +/* return the size of the SMMU context */ +func tegra194_get_smmu_ctx_offset + adr x0, __tegra194_smmu_context + adr x1, tegra194_cpu_reset_handler + sub x0, x0, x1 + ret +endfunc tegra194_get_smmu_ctx_offset -- cgit v1.2.3 From 040529e9e67f23dc85f4ff5aec94debf8cecb3cc Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 10 Nov 2017 13:27:29 -0800 Subject: Tegra194: save system suspend entry marker to TZDRAM This patch adds support to save the system suspend entry and exit markers to TZDRAM to help the trampoline code decide if the current warmboot is actually an exit from System Suspend. The Tegra194 platform handler sets the system suspend entry marker before entering SC7 state and the trampoline flips the state back to system resume, on exiting SC7. Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra194_private.h | 1 + plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 3 ++ plat/nvidia/tegra/soc/t194/plat_trampoline.S | 54 ++++++++++++++++++----- 3 files changed, 48 insertions(+), 10 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra194_private.h b/plat/nvidia/tegra/include/t194/tegra194_private.h index f5de017bc..e519cdccc 100644 --- a/plat/nvidia/tegra/include/t194/tegra194_private.h +++ b/plat/nvidia/tegra/include/t194/tegra194_private.h @@ -11,5 +11,6 @@ void tegra194_cpu_reset_handler(void); uint64_t tegra194_get_cpu_reset_handler_base(void); uint64_t tegra194_get_cpu_reset_handler_size(void); uint64_t tegra194_get_smmu_ctx_offset(void); +void tegra194_set_system_suspend_entry(void); #endif /* __TEGRA194_PRIVATE_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index c25897d56..71a666b80 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -167,6 +167,9 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) MCE_CORE_SLEEP_TIME_INFINITE, 0U); assert(ret == 0); + + /* set system suspend state for house-keeping */ + tegra194_set_system_suspend_entry(); } } else { ; /* do nothing */ diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S index ea8cbef15..33c7e6f78 100644 --- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S @@ -10,6 +10,8 @@ #include #include +#define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7 +#define TEGRA194_STATE_SYSTEM_RESUME 0x600D #define TEGRA194_SMMU_CTX_SIZE 0x490 .align 4 @@ -17,17 +19,24 @@ /* CPU reset handler routine */ func tegra194_cpu_reset_handler - /* - * The TZRAM loses state during System Suspend. We use this - * information to decide if the reset handler is running after a - * System Suspend. Resume from system suspend requires restoring - * the entire state from TZDRAM to TZRAM. - */ - mov x0, #BL31_BASE - ldr x0, [x0] - cbnz x0, boot_cpu + /* check if we are exiting system suspend state */ + adr x0, __tegra194_system_suspend_state + ldr x1, [x0] + mov x2, #TEGRA194_STATE_SYSTEM_SUSPEND + lsl x2, x2, #16 + add x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND + cmp x1, x2 + bne boot_cpu + + /* set system resume state */ + mov x1, #TEGRA194_STATE_SYSTEM_RESUME + lsl x1, x1, #16 + mov x2, #TEGRA194_STATE_SYSTEM_RESUME + add x1, x1, x2 + str x1, [x0] + dsb sy - /* resume from system suspend */ + /* prepare to relocate to TZSRAM */ mov x0, #BL31_BASE adr x1, __tegra194_cpu_reset_handler_end adr x2, __tegra194_cpu_reset_handler_data @@ -71,6 +80,10 @@ __tegra194_cpu_reset_handler_data: .quad tegra_secure_entrypoint .quad __BL31_END__ - BL31_BASE + .globl __tegra194_system_suspend_state +__tegra194_system_suspend_state: + .quad 0 + .align 4 __tegra194_smmu_context: .rept TEGRA194_SMMU_CTX_SIZE @@ -86,6 +99,7 @@ __tegra194_cpu_reset_handler_end: .globl tegra194_get_cpu_reset_handler_size .globl tegra194_get_cpu_reset_handler_base .globl tegra194_get_smmu_ctx_offset + .globl tegra194_set_system_suspend_entry /* return size of the CPU reset handler */ func tegra194_get_cpu_reset_handler_size @@ -108,3 +122,23 @@ func tegra194_get_smmu_ctx_offset sub x0, x0, x1 ret endfunc tegra194_get_smmu_ctx_offset + +/* set system suspend state before SC7 entry */ +func tegra194_set_system_suspend_entry + mov x0, #TEGRA_MC_BASE + mov x3, #MC_SECURITY_CFG3_0 + ldr w1, [x0, x3] + lsl x1, x1, #32 + mov x3, #MC_SECURITY_CFG0_0 + ldr w2, [x0, x3] + orr x3, x1, x2 /* TZDRAM base */ + adr x0, __tegra194_system_suspend_state + adr x1, tegra194_cpu_reset_handler + sub x2, x0, x1 /* offset in TZDRAM */ + mov x0, #TEGRA194_STATE_SYSTEM_SUSPEND + lsl x0, x0, #16 + add x0, x0, #TEGRA194_STATE_SYSTEM_SUSPEND + str x0, [x3, x2] /* set value in TZDRAM */ + dsb sy + ret +endfunc tegra194_set_system_suspend_entry -- cgit v1.2.3 From 5ad50d7d81c7c5d27bea3fc86fd6ff5b840e2dfb Mon Sep 17 00:00:00 2001 From: Puneet Saxena Date: Fri, 8 Sep 2017 12:14:03 +0530 Subject: Tegra194: memctrl: override SE client as coherent This patch enables IO coherency for SE clients, SEWR and SERD, by overriding their platform settings to "normal_coherent". This setting also converts read/write requests from these SE clients to Normal type. Change-Id: I31ad195ad30ecc9ee785e5e84184cda2eea5c45a Signed-off-by: Puneet Saxena Signed-off-by: Shravani Dingari Signed-off-by: Jeff Tsai --- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 0a6345dcc..044a4512f 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -388,7 +388,6 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_tsa_w_passthrough(SDMMCW); mc_set_tsa_w_passthrough(SDMMCWA); mc_set_tsa_w_passthrough(SDMMCWAB); - mc_set_tsa_w_passthrough(SESWR); mc_set_tsa_w_passthrough(TSECSWR); mc_set_tsa_w_passthrough(TSECSWRB); mc_set_tsa_w_passthrough(UFSHCW); @@ -468,8 +467,8 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE); + mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE); mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); -- cgit v1.2.3 From 4e697b77868e2c371e577e6cae08533fcdaa07dd Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Tue, 14 Nov 2017 19:12:58 +0800 Subject: Tegra194: memctrl: platform handler for TZDRAM setup This patch provides the platform with flexibility to perform custom steps during TZDRAM setup. Tegra194 platforms checks if the config registers are locked and TZDRAM setup has already been done by the previous bootloaders, before setting up the fence. Change-Id: Ifee7077d4b46a7031c4568934c63e361c53a12e3 Signed-off-by: Steven Kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 3 +++ plat/nvidia/tegra/soc/t194/plat_memctrl.c | 33 +++++++++++++++++++++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index a41c0cd7e..ca2a6ed4f 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -73,6 +73,9 @@ #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) +#define MC_SECURITY_CFG_REG_CTRL_0 U(0x154) +#define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0) + /* Video Memory carveout configuration registers */ #define MC_VIDEO_PROTECT_BASE_HI U(0x978) #define MC_VIDEO_PROTECT_BASE_LO U(0x648) diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 044a4512f..75705cff1 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -638,4 +638,35 @@ static tegra_mc_settings_t tegra194_mc_settings = { tegra_mc_settings_t *tegra_get_mc_settings(void) { return &tegra194_mc_settings; -} \ No newline at end of file +} + +/******************************************************************************* + * Handler to program the scratch registers with TZDRAM settings for the + * resume firmware + ******************************************************************************/ +void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) +{ + /* + * Check if the carveout register is already locked, if locked + * no TZDRAM setup + */ + if ((tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0) & + SECURITY_CFG_WRITE_ACCESS_BIT) == SECURITY_CFG_WRITE_ACCESS_BIT) { + + /* + * Setup the Memory controller to allow only secure accesses to + * the TZDRAM carveout + */ + INFO("Configuring TrustZone DRAM Memory Carveout\n"); + + tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); + tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); + tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); + + /* + * MCE propagates the security configuration values across the + * CCPLEX. + */ + (void)mce_update_gsc_tzdram(); + } +} -- cgit v1.2.3 From 14f528529a6b85b8cb9dc3e2dad4922d30252a2e Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 15 Nov 2017 15:52:01 -0800 Subject: Tegra194: console driver compilation from platform makefiles This patch includes the console driver from individual platform makefile, to allow future platforms to include consoles of their choice. Change-Id: I4c92199717da410c8b5e8d45af67f4345f743dbd Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/platform_t194.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 3db7334af..ea171bdf1 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -42,7 +42,8 @@ $(eval $(call add_define,MAX_MMAP_REGIONS)) # platform files PLAT_INCLUDES += -I${SOC_DIR}/drivers/include -BL31_SOURCES += lib/cpus/aarch64/denver.S \ +BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ + lib/cpus/aarch64/denver.S \ ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ ${COMMON_DIR}/drivers/smmu/smmu.c \ ${SOC_DIR}/drivers/mce/mce.c \ -- cgit v1.2.3 From 1b0f027dd9fbddfa706b1f3b051159543edf345c Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 16 Oct 2017 15:57:17 -0700 Subject: Tegra194: CC6 state from last offline CPU in the cluster This patch enables the CC6 cluster state for the cluster, if the current CPU being offlined is the last CPU in the cluster. Change-Id: I3380a969b534fcd14f9c46433471cc1c2adf6011 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 91 +++++++++++++++---------- 1 file changed, 56 insertions(+), 35 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 71a666b80..6facc1860 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -179,24 +179,39 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) } /******************************************************************************* - * Platform handler to calculate the proper target power level at the - * specified affinity level + * Helper function to check if this is the last ON CPU in the cluster ******************************************************************************/ -plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, - const plat_local_state_t *states, - uint32_t ncpu) +static bool tegra_last_on_cpu_in_cluster(const plat_local_state_t *states, + uint32_t ncpu) { - plat_local_state_t target = *states; - int32_t cluster_powerdn = 1; - uint32_t core_pos = (uint32_t)read_mpidr() & MPIDR_CPU_MASK; + plat_local_state_t target; + bool last_on_cpu = true; uint32_t num_cpus = ncpu, pos = 0; - mce_cstate_info_t cstate_info = { 0 }; - /* get the current core's power state */ - target = states[core_pos]; + do { + target = states[pos]; + if (target != PLAT_MAX_OFF_STATE) { + last_on_cpu = false; + } + --num_cpus; + pos++; + } while (num_cpus != 0U); + + return last_on_cpu; +} + +/******************************************************************************* + * Helper function to get target power state for the cluster + ******************************************************************************/ +static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states, + uint32_t ncpu) +{ + uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK; + plat_local_state_t target = states[core_pos]; + mce_cstate_info_t cstate_info = { 0 }; /* CPU suspend */ - if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CORE_POWERDN)) { + if (target == PSTATE_ID_CORE_POWERDN) { /* Program default wake mask */ cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; @@ -205,45 +220,51 @@ plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, } /* CPU off */ - if ((lvl == MPIDR_AFFLVL1) && (target == PLAT_MAX_OFF_STATE)) { - - /* find out the number of ON cpus in the cluster */ - do { - target = states[pos]; - if (target != PLAT_MAX_OFF_STATE) { - cluster_powerdn = 0; - } - --num_cpus; - pos++; - } while (num_cpus != 0U); + if (target == PLAT_MAX_OFF_STATE) { /* Enable cluster powerdn from last CPU in the cluster */ - if (cluster_powerdn != 0) { - - /* Enable CC6 */ - /* todo */ - - /* If cluster group needs to be railgated, request CG7 */ - /* todo */ + if (tegra_last_on_cpu_in_cluster(states, ncpu)) { - /* Turn off wake mask */ + /* Enable CC6 state and turn off wake mask */ + cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6; cstate_info.update_wake_mask = 1U; mce_update_cstate_info(&cstate_info); } else { + /* Turn off wake_mask */ cstate_info.update_wake_mask = 1U; mce_update_cstate_info(&cstate_info); + target = PSCI_LOCAL_STATE_RUN; } } + return target; +} + +/******************************************************************************* + * Platform handler to calculate the proper target power level at the + * specified affinity level + ******************************************************************************/ +plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, + const plat_local_state_t *states, + uint32_t ncpu) +{ + plat_local_state_t target = PSCI_LOCAL_STATE_RUN; + uint32_t cpu = plat_my_core_pos(); + /* System Suspend */ - if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN)) { - return PSTATE_ID_SOC_POWERDN; + if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) { + target = PSTATE_ID_SOC_POWERDN; + } + + /* CPU off, CPU suspend */ + if (lvl == (uint32_t)MPIDR_AFFLVL1) { + target = tegra_get_afflvl1_pwr_state(states, ncpu); } - /* default state */ - return PSCI_LOCAL_STATE_RUN; + /* target cluster/system state */ + return target; } int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) -- cgit v1.2.3 From ac252f95dd5089cfa9676d15a11018f8f41e692e Mon Sep 17 00:00:00 2001 From: Dilan Lee Date: Thu, 10 Aug 2017 16:01:42 +0800 Subject: Tegra194: mce: enable strict checking "Strict checking" is a mode where secure world can access secure-only areas unlike legacy mode where secure world could access non-secure spaces as well. Secure-only areas are defined as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set. This mode not only helps prevent issues with IO-Coherency but aids with security as well. This patch implements the programming sequence required to enable strict checking mode for Tegra194 SoCs. Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0 Signed-off-by: Dilan Lee --- .../tegra/soc/t194/drivers/include/mce_private.h | 12 ++++- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 51 ++++++++++++++++++++++ plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 13 ++++++ plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 8 ++++ plat/nvidia/tegra/soc/t194/plat_setup.c | 10 +++++ 5 files changed, 93 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 1970a2d17..3994b2d75 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -36,6 +36,12 @@ ******************************************************************************/ #define MCE_STAT_ID_SHIFT 16U +/******************************************************************************* + * Security config macros + ******************************************************************************/ +#define STRICT_CHECKING_ENABLED_SET (1UL << 0) +#define STRICT_CHECKING_LOCKED_SET (1UL << 1) + /* declarations for NVG handler functions */ uint64_t nvg_get_version(void); int32_t nvg_enable_power_perf_mode(void); @@ -54,12 +60,16 @@ int32_t nvg_roc_clean_cache(void); int32_t nvg_roc_flush_cache(void); int32_t nvg_roc_clean_cache_trbits(void); int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); - void nvg_set_request_data(uint64_t req, uint64_t data); void nvg_set_request(uint64_t req); uint64_t nvg_get_result(void); uint64_t nvg_cache_clean(void); uint64_t nvg_cache_clean_inval(void); uint64_t nvg_cache_inval_all(void); +int32_t nvg_roc_clean_cache_trbits(void); +void nvg_enable_strict_checking_mode(void); + +/* MCE helper functions */ +void mce_enable_strict_checking(void); #endif /* __MCE_PRIVATE_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index 8c7854e9c..ba8436be4 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -21,6 +21,7 @@ #include #include #include +#include /* Handler to check if MCE firmware is supported */ static bool mce_firmware_not_supported(void) @@ -184,3 +185,53 @@ void mce_verify_firmware_version(void) panic(); } } + +/******************************************************************************* + * Handler to enable the strict checking mode + ******************************************************************************/ +void mce_enable_strict_checking(void) +{ + uint64_t sctlr = read_sctlr_el3(); + int32_t ret = 0; + + if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { + /* + * Step1: TZ-DRAM and TZRAM should be setup before the MMU is + * enabled. + * + * The common code makes sure that TZDRAM/TZRAM are already + * enabled before calling into this handler. If this is not the + * case, the following sequence must be executed before moving + * on to step 2. + * + * tlbialle1is(); + * tlbialle3is(); + * dsbsy(); + * isb(); + * + */ + if ((sctlr & (uint64_t)SCTLR_M_BIT) == (uint64_t)SCTLR_M_BIT) { + tlbialle1is(); + tlbialle3is(); + dsbsy(); + isb(); + } + + /* + * Step2: SCF flush - Clean and invalidate caches and clear the + * TR-bits + */ + ret = nvg_roc_clean_cache_trbits(); + if (ret < 0) { + ERROR("%s: flush cache_trbits failed(%d)\n", __func__, + ret); + return; + } + + /* + * Step3: Issue the SECURITY_CONFIG request to MCE to enable + * strict checking mode. + */ + nvg_enable_strict_checking_mode(); + } +} diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index 96b2b9113..1dd1f51b9 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -284,3 +284,16 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) return ret; } + +/* + * Enable strict checking mode + * + * NVGDATA[3] strict_check ON + lock + */ +void nvg_enable_strict_checking_mode(void) +{ + uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | + STRICT_CHECKING_LOCKED_SET); + + nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params); +} diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 6facc1860..948fadec9 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -356,6 +357,13 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) * context if we are. */ if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { + + /* + * Enable strict checking after programming the GSC for + * enabling TZSRAM and TZDRAM + */ + mce_enable_strict_checking(); + /* Init SMMU */ tegra_smmu_init(); diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 4b6ec8eaf..278dabe32 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -257,3 +258,12 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void) return (plat_params_from_bl2_t *)(uintptr_t)val; } + +void plat_late_platform_setup(void) +{ + /* + * Enable strict checking after programming the GSC for + * enabling TZSRAM and TZDRAM + */ + mce_enable_strict_checking(); +} -- cgit v1.2.3 From 02b3e311acb745f59bcd7c90bb959f6f63e4332f Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Wed, 8 Nov 2017 11:33:56 +0800 Subject: Tegra194: update nvg header to v6.4 This patch updates the header, t194_nvg.h, to v6.4. This gets it in synch with MTS pre-release 2 - cl39748439. Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ecd7 Signed-off-by: Steven Kao --- .../tegra/soc/t194/drivers/include/t194_nvg.h | 478 +++++++++++---------- 1 file changed, 256 insertions(+), 222 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h index 5a72680ac..cc0da80bf 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h @@ -19,281 +19,315 @@ * occur when there is only new functionality. */ enum { - TEGRA_NVG_VERSION_MAJOR = 6, - TEGRA_NVG_VERSION_MINOR = 1 + TEGRA_NVG_VERSION_MAJOR = 6, + TEGRA_NVG_VERSION_MINOR = 4 }; typedef enum { - TEGRA_NVG_CHANNEL_VERSION = 0, - TEGRA_NVG_CHANNEL_POWER_PERF = 1, - TEGRA_NVG_CHANNEL_POWER_MODES = 2, - TEGRA_NVG_CHANNEL_WAKE_TIME = 3, - TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, - TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, - TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, - TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, - TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, - TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, - TEGRA_NVG_CHANNEL_SHUTDOWN = 42, - TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, - TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, - TEGRA_NVG_CHANNEL_CC3_CTRL = 45, - TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, - TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, - TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, - TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, - TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, - TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, - TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, - TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, - TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, - TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 60, - TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 61, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 62, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 63, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 64, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 65, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 66, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 67, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 68, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 69, - TEGRA_NVG_CHANNEL_LAST_INDEX + TEGRA_NVG_CHANNEL_VERSION = 0, + TEGRA_NVG_CHANNEL_POWER_PERF = 1, + TEGRA_NVG_CHANNEL_POWER_MODES = 2, + TEGRA_NVG_CHANNEL_WAKE_TIME = 3, + TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, + TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, + TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, + TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, + TEGRA_NVG_CHANNEL_SHUTDOWN = 42, + TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, + TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, + TEGRA_NVG_CHANNEL_CC3_CTRL = 45, + TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, + TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, + TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, + TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, + TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, + TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, + TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60, + TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76, + TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77, + TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78, + TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79, + + TEGRA_NVG_CHANNEL_LAST_INDEX } tegra_nvg_channel_id_t; typedef enum { - NVG_STAT_QUERY_SC7_ENTRIES = 1, - NVG_STAT_QUERY_CC6_ENTRIES = 6, - NVG_STAT_QUERY_CG7_ENTRIES = 7, - NVG_STAT_QUERY_C6_ENTRIES = 10, - NVG_STAT_QUERY_C7_ENTRIES = 14, - NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, - NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, - NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, - NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, - NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56 + NVG_STAT_QUERY_SC7_ENTRIES = 1, + NVG_STAT_QUERY_CC6_ENTRIES = 6, + NVG_STAT_QUERY_CG7_ENTRIES = 7, + NVG_STAT_QUERY_C6_ENTRIES = 10, + NVG_STAT_QUERY_C7_ENTRIES = 14, + NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, + NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, + NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, + NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, + NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56, + NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM = 60, + NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM = 61, + NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM = 62, + NVG_STAT_QUERY_C6_ENTRY_TIME_SUM = 63, + NVG_STAT_QUERY_C7_ENTRY_TIME_SUM = 64, + NVG_STAT_QUERY_SC7_EXIT_TIME_SUM = 70, + NVG_STAT_QUERY_CC6_EXIT_TIME_SUM = 71, + NVG_STAT_QUERY_CG7_EXIT_TIME_SUM = 72, + NVG_STAT_QUERY_C6_EXIT_TIME_SUM = 73, + NVG_STAT_QUERY_C7_EXIT_TIME_SUM = 74, + NVG_STAT_QUERY_SC7_ENTRY_LAST = 80, + NVG_STAT_QUERY_CC6_ENTRY_LAST = 81, + NVG_STAT_QUERY_CG7_ENTRY_LAST = 82, + NVG_STAT_QUERY_C6_ENTRY_LAST = 83, + NVG_STAT_QUERY_C7_ENTRY_LAST = 84, + NVG_STAT_QUERY_SC7_EXIT_LAST = 90, + NVG_STAT_QUERY_CC6_EXIT_LAST = 91, + NVG_STAT_QUERY_CG7_EXIT_LAST = 92, + NVG_STAT_QUERY_C6_EXIT_LAST = 93, + NVG_STAT_QUERY_C7_EXIT_LAST = 94 } tegra_nvg_stat_query_t; typedef enum { - TEGRA_NVG_CORE_C0 = 0, - TEGRA_NVG_CORE_C1 = 1, - TEGRA_NVG_CORE_C6 = 6, - TEGRA_NVG_CORE_C7 = 7, - TEGRA_NVG_CORE_WARMRSTREQ = 8 + TEGRA_NVG_CORE_C0 = 0, + TEGRA_NVG_CORE_C1 = 1, + TEGRA_NVG_CORE_C6 = 6, + TEGRA_NVG_CORE_C7 = 7, + TEGRA_NVG_CORE_WARMRSTREQ = 8 } tegra_nvg_core_sleep_state_t; typedef enum { - TEGRA_NVG_CLUSTER_CC0 = 0, - TEGRA_NVG_CLUSTER_CC6 = 6 + TEGRA_NVG_CLUSTER_CC0 = 0, + TEGRA_NVG_CLUSTER_CC6 = 6 } tegra_nvg_cluster_sleep_state_t; typedef enum { - TEGRA_NVG_CG_CG0 = 0, - TEGRA_NVG_CG_CG7 = 1 - + TEGRA_NVG_CG_CG0 = 0, + TEGRA_NVG_CG_CG7 = 7 } tegra_nvg_cluster_group_sleep_state_t; typedef enum { - TEGRA_NVG_SYSTEM_SC0 = 0, - TEGRA_NVG_SYSTEM_SC7 = 7, - TEGRA_NVG_SYSTEM_SC8 = 8 + TEGRA_NVG_SYSTEM_SC0 = 0, + TEGRA_NVG_SYSTEM_SC7 = 7, + TEGRA_NVG_SYSTEM_SC8 = 8 } tegra_nvg_system_sleep_state_t; // --------------------------------------------------------------------------- // NVG Data subformats // --------------------------------------------------------------------------- -typedef union -{ - uint64_t flat; - struct nvg_version_channel_t { - uint64_t minor_version : 32; - uint64_t major_version : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_version_channel_t { + uint32_t minor_version : 32; + uint32_t major_version : 32; + } bits; } nvg_version_data_t; -typedef union nvg_channel_1_data_u -{ - uint64_t flat; - struct nvg_channel_1_data_s - { - uint32_t perf_per_watt_mode : 1; - uint32_t reserved_31_1 : 31; - uint32_t reserved_63_32 : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_power_perf_channel_t { + uint32_t perf_per_watt : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_power_perf_channel_t; + +typedef union { + uint64_t flat; + struct nvg_power_modes_channel_t { + uint32_t low_battery : 1; + uint32_t reserved_1_1 : 1; + uint32_t battery_save : 1; + uint32_t reserved_31_3 : 29; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_power_modes_channel_t; + +typedef union nvg_channel_1_data_u { + uint64_t flat; + struct nvg_channel_1_data_s { + uint32_t perf_per_watt_mode : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; + } bits; } nvg_channel_1_data_t; -typedef union -{ - uint64_t flat; - struct nvg_ccplex_cache_control_channel_t { - uint32_t gpu_ways : 5; - uint32_t reserved_7_5 : 3; - uint32_t gpu_only_ways : 5; - uint32_t reserved_31_13 : 19; - uint32_t reserved_63_32 : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_ccplex_cache_control_channel_t { + uint32_t gpu_ways : 5; + uint32_t reserved_7_5 : 3; + uint32_t gpu_only_ways : 5; + uint32_t reserved_31_13 : 19; + uint32_t reserved_63_32 : 32; + } bits; } nvg_ccplex_cache_control_channel_t; -typedef union nvg_channel_2_data_u -{ - uint64_t flat; - struct nvg_channel_2_data_s - { - uint32_t reserved_1_0 : 2; - uint32_t battery_saver_mode : 1; - uint32_t reserved_31_3 : 29; - uint32_t reserved_63_32 : 32; - } bits; +typedef union nvg_channel_2_data_u { + uint64_t flat; + struct nvg_channel_2_data_s { + uint32_t reserved_1_0 : 2; + uint32_t battery_saver_mode : 1; + uint32_t reserved_31_3 : 29; + uint32_t reserved_63_32 : 32; + } bits; } nvg_channel_2_data_t; -typedef union -{ - uint64_t flat; - struct nvg_wake_time_channel_t { - uint32_t wake_time : 32; - uint32_t reserved_63_32 : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_wake_time_channel_t { + uint32_t wake_time : 32; + uint32_t reserved_63_32 : 32; + } bits; } nvg_wake_time_channel_t; -typedef union -{ - uint64_t flat; - struct nvg_cstate_info_channel_t { - uint32_t cluster_state : 3; - uint32_t reserved_6_3 : 4; - uint32_t update_cluster : 1; - uint32_t cg_cstate : 3; - uint32_t reserved_14_11 : 4; - uint32_t update_cg : 1; - uint32_t system_cstate : 4; - uint32_t reserved_22_20 : 3; - uint32_t update_system : 1; - uint32_t reserved_30_24 : 7; - uint32_t update_wake_mask : 1; - uint32_t wake_mask : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_cstate_info_channel_t { + uint32_t cluster_state : 3; + uint32_t reserved_6_3 : 4; + uint32_t update_cluster : 1; + uint32_t cg_cstate : 3; + uint32_t reserved_14_11 : 4; + uint32_t update_cg : 1; + uint32_t system_cstate : 4; + uint32_t reserved_22_20 : 3; + uint32_t update_system : 1; + uint32_t reserved_30_24 : 7; + uint32_t update_wake_mask : 1; + uint32_t wake_mask : 32; + } bits; } nvg_cstate_info_channel_t; -typedef union -{ - uint64_t flat; - struct nvg_lower_bound_channel_t { - uint32_t crossover_value : 32; - uint32_t reserved_63_32 : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_lower_bound_channel_t { + uint32_t crossover_value : 32; + uint32_t reserved_63_32 : 32; + } bits; } nvg_lower_bound_channel_t; -typedef union -{ - uint64_t flat; - struct nvg_cstate_stat_query_channel_t { - uint32_t unit_id : 4; - uint32_t reserved_15_4 : 12; - uint32_t stat_id : 16; - uint32_t reserved_63_32 : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_cstate_stat_query_channel_t { + uint32_t unit_id : 4; + uint32_t reserved_15_4 : 12; + uint32_t stat_id : 16; + uint32_t reserved_63_32 : 32; + } bits; } nvg_cstate_stat_query_channel_t; -typedef union -{ - uint64_t flat; - struct nvg_is_sc7_allowed_channel_t { - uint32_t is_sc7_allowed : 1; - uint32_t reserved_31_1 : 31; - uint32_t reserved_63_32 : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_is_sc7_allowed_channel_t { + uint32_t is_sc7_allowed : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; + } bits; } nvg_is_sc7_allowed_channel_t; -typedef union -{ - uint64_t flat; - struct nvg_core_online_channel_t { - uint32_t core_id : 4; - uint32_t reserved_31_4 : 28; - uint32_t reserved_63_32 : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_core_online_channel_t { + uint32_t core_id : 4; + uint32_t reserved_31_4 : 28; + uint32_t reserved_63_32 : 32; + } bits; } nvg_core_online_channel_t; -typedef union -{ - uint64_t flat; - struct nvg_cc3_control_channel_t { - uint32_t freq_req : 8; - uint32_t reserved_30_8 : 23; - uint32_t enable : 1; - uint32_t reserved_63_32 : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_cc3_control_channel_t { + uint32_t freq_req : 8; + uint32_t reserved_30_8 : 23; + uint32_t enable : 1; + uint32_t reserved_63_32 : 32; + } bits; } nvg_cc3_control_channel_t; typedef enum { - TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0 , - TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1 , - TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2 , - TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3 , - TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4 , - TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5 , - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6 , - TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7 , - TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8 , - TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9 , - TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, - TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, - TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, - TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, - TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, - TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, - TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, - TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, - TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, - TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, - TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX + TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0, + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1, + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2, + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6, + TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9, + TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, + TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, + TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, + TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, + TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, + TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, + TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, + TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX } tegra_nvg_channel_update_gsc_gsc_enum_t; -typedef union -{ - uint64_t flat; - struct nvg_update_ccplex_gsc_channel_t { - uint32_t gsc_enum : 16; - uint32_t reserved_31_16 : 16; - uint32_t reserved_63_32 : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_update_ccplex_gsc_channel_t { + uint32_t gsc_enum : 16; + uint32_t reserved_31_16 : 16; + uint32_t reserved_63_32 : 32; + } bits; } nvg_update_ccplex_gsc_channel_t; -typedef union -{ - uint64_t flat; - struct nvg_security_config_channel_t { - uint32_t strict_checking_enabled : 1; - uint32_t strict_checking_locked : 1; - uint32_t reserved_31_2 : 30; - uint32_t reserved_63_32 : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_security_config_channel_t { + uint32_t strict_checking_enabled : 1; + uint32_t strict_checking_locked : 1; + uint32_t reserved_31_2 : 30; + uint32_t reserved_63_32 : 32; + } bits; } nvg_security_config_t; -typedef union -{ - uint64_t flat; - struct nvg_shutdown_channel_t { - uint32_t reboot : 1; - uint32_t reserved_31_1 : 31; - uint32_t reserved_63_32 : 32; - } bits; +typedef union { + uint64_t flat; + struct nvg_shutdown_channel_t { + uint32_t reboot : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; + } bits; } nvg_shutdown_t; #endif -- cgit v1.2.3 From f0222c23fd9f56713c2fba553d5da359a4bd9398 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 21 Aug 2019 13:47:58 -0700 Subject: Tegra: include: drivers: introduce spe.h This patch introduces a header file for the spe-console driver. This file currently provides a device struct and a registration function call for clients. Signed-off-by: Varun Wadekar Change-Id: Ic65c056f5bd60871d8a3f44f2c1210035f878799 --- plat/nvidia/tegra/include/drivers/spe.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 plat/nvidia/tegra/include/drivers/spe.h diff --git a/plat/nvidia/tegra/include/drivers/spe.h b/plat/nvidia/tegra/include/drivers/spe.h new file mode 100644 index 000000000..0d6d69d10 --- /dev/null +++ b/plat/nvidia/tegra/include/drivers/spe.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2019, NVIDIA Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPE_H +#define SPE_H + +#include + +#include + +typedef struct { + console_t console; + uintptr_t base; +} console_spe_t; + +/* + * Initialize a new spe console instance and register it with the console + * framework. The |console| pointer must point to storage that will be valid + * for the lifetime of the console, such as a global or static local variable. + * Its contents will be reinitialized from scratch. + */ +int console_spe_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, + console_spe_t *console); + +#endif /* SPE_H */ -- cgit v1.2.3 From 117dbe6ce91b85763d5d63964fb3b458462fddf8 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 21 Aug 2019 14:01:31 -0700 Subject: Tegra: introduce plat_enable_console() This patch introduces the 'plat_enable_console' handler to allow the platform to enable the right console. Tegra194 platform supports multiple console, while all the previous platforms support only one console. For Tegra194 platforms, the previous bootloader checks the platform config and sets the uart-id boot parameter, to 0xFE. On seeing this boot parameter, the platform port uses the proper memory aperture base address to communicate with the SPE. This functionality is currently protected by a platform macro, ENABLE_CONSOLE_SPE. Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/common/tegra_bl31_setup.c | 30 ++-------------- plat/nvidia/tegra/include/t194/tegra_def.h | 6 ++++ plat/nvidia/tegra/include/tegra_private.h | 2 +- plat/nvidia/tegra/soc/t132/plat_setup.c | 28 ++++++++++++--- plat/nvidia/tegra/soc/t186/plat_setup.c | 29 +++++++++++----- plat/nvidia/tegra/soc/t194/plat_setup.c | 53 ++++++++++++++++++++++++----- plat/nvidia/tegra/soc/t194/platform_t194.mk | 9 ++++- plat/nvidia/tegra/soc/t210/plat_setup.c | 26 +++++++++++--- 8 files changed, 127 insertions(+), 56 deletions(-) diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index f89e77a34..a6652766f 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -129,10 +129,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; image_info_t bl32_img_info = { {0} }; - uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end, console_base; - uint32_t console_clock; + uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; int32_t ret; - static console_16550_t console; /* * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so @@ -182,31 +180,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, } /* - * Reference clock used by the FPGAs is a lot slower. + * Enable console for the platform */ - if (tegra_platform_is_fpga()) { - console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; - } else { - console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; - } - - /* - * Get the base address of the UART controller to be used for the - * console - */ - console_base = plat_get_console_from_id(plat_params->uart_id); - - if (console_base != 0U) { - /* - * Configure the UART port to be used as the console - */ - (void)console_16550_register(console_base, - console_clock, - TEGRA_CONSOLE_BAUDRATE, - &console); - console_set_scope(&console.console, CONSOLE_FLAG_BOOT | - CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); - } + plat_enable_console(plat_params->uart_id); /* * The previous bootloader passes the base address of the shared memory diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index ca2a6ed4f..bedf26888 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -143,6 +143,12 @@ #define TEGRA_RNG1_BASE U(0x03AE0000) #define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) +/******************************************************************************* + * Tegra hardware synchronization primitives for the SPE engine + ******************************************************************************/ +#define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000) +#define TEGRA_CONSOLE_SPE_BASE (TEGRA_AON_HSP_SM_6_7_BASE + U(0x8000)) + /******************************************************************************* * Tegra micro-seconds timer constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index fab0eafc3..cd2f77308 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -76,7 +76,7 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state, /* Declarations for plat_setup.c */ const mmap_region_t *plat_get_mmio_map(void); -uint32_t plat_get_console_from_id(int32_t id); +void plat_enable_console(int32_t id); void plat_gic_setup(void); struct tegra_bl31_params *plat_get_bl31_params(void); plat_params_from_bl2_t *plat_get_bl31_plat_params(void); diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c index 570acd900..df6267897 100644 --- a/plat/nvidia/tegra/soc/t132/plat_setup.c +++ b/plat/nvidia/tegra/soc/t132/plat_setup.c @@ -6,9 +6,11 @@ #include #include +#include #include #include #include +#include #include /* sets of MMIO ranges setup */ @@ -85,14 +87,30 @@ static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = { }; /******************************************************************************* - * Retrieve the UART controller base to be used as the console + * Enable console corresponding to the console ID ******************************************************************************/ -uint32_t plat_get_console_from_id(int id) +void plat_enable_console(int32_t id) { - if (id > TEGRA132_MAX_UART_PORTS) - return 0; + static console_16550_t uart_console; + uint32_t console_clock; - return tegra132_uart_addresses[id]; + if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) { + /* + * Reference clock used by the FPGAs is a lot slower. + */ + if (tegra_platform_is_fpga()) { + console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; + } else { + console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; + } + + (void)console_16550_register(tegra132_uart_addresses[id], + console_clock, + TEGRA_CONSOLE_BAUDRATE, + &uart_console); + console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | + CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); + } } /******************************************************************************* diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c index ef0ba4eb1..1018caa94 100644 --- a/plat/nvidia/tegra/soc/t186/plat_setup.c +++ b/plat/nvidia/tegra/soc/t186/plat_setup.c @@ -141,19 +141,30 @@ static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { }; /******************************************************************************* - * Retrieve the UART controller base to be used as the console + * Enable console corresponding to the console ID ******************************************************************************/ -uint32_t plat_get_console_from_id(int32_t id) +void plat_enable_console(int32_t id) { - uint32_t ret; + static console_16550_t uart_console; + uint32_t console_clock; + + if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) { + /* + * Reference clock used by the FPGAs is a lot slower. + */ + if (tegra_platform_is_fpga()) { + console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; + } else { + console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; + } - if (id > TEGRA186_MAX_UART_PORTS) { - ret = 0; - } else { - ret = tegra186_uart_addresses[id]; + (void)console_16550_register(tegra186_uart_addresses[id], + console_clock, + TEGRA_CONSOLE_BAUDRATE, + &uart_console); + console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | + CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); } - - return ret; } /******************************************************************************* diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 278dabe32..8c5710557 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -21,12 +21,16 @@ #include #include #include +#include #include #include #include #include #include +/* ID for spe-console */ +#define TEGRA_CONSOLE_SPE_ID 0xFE + /******************************************************************************* * The Tegra power domain tree has a single system level power domain i.e. a * single root node. The first entry in the power domain descriptor specifies @@ -68,12 +72,14 @@ static const mmap_region_t tegra_mmap[] = { (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), +#if !ENABLE_CONSOLE_SPE MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), +#endif MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */ @@ -84,6 +90,10 @@ static const mmap_region_t tegra_mmap[] = { (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), +#if ENABLE_CONSOLE_SPE + MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), +#endif MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ @@ -120,6 +130,7 @@ uint32_t plat_get_syscnt_freq2(void) return 31250000; } +#if !ENABLE_CONSOLE_SPE /******************************************************************************* * Maximum supported UART controllers ******************************************************************************/ @@ -138,21 +149,47 @@ static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = { TEGRA_UARTF_BASE, TEGRA_UARTG_BASE }; +#endif /******************************************************************************* - * Retrieve the UART controller base to be used as the console + * Enable console corresponding to the console ID ******************************************************************************/ -uint32_t plat_get_console_from_id(int32_t id) +void plat_enable_console(int32_t id) { - uint32_t ret; + uint32_t console_clock = 0U; + +#if ENABLE_CONSOLE_SPE + static console_spe_t spe_console; - if (id > TEGRA194_MAX_UART_PORTS) { - ret = 0; - } else { - ret = tegra194_uart_addresses[id]; + if (id == TEGRA_CONSOLE_SPE_ID) { + (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE, + console_clock, + TEGRA_CONSOLE_BAUDRATE, + &spe_console); + console_set_scope(&spe_console.console, CONSOLE_FLAG_BOOT | + CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); } +#else + static console_16550_t uart_console; - return ret; + if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) { + /* + * Reference clock used by the FPGAs is a lot slower. + */ + if (tegra_platform_is_fpga()) { + console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; + } else { + console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; + } + + (void)console_16550_register(tegra194_uart_addresses[id], + console_clock, + TEGRA_CONSOLE_BAUDRATE, + &uart_console); + console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | + CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); + } +#endif } /******************************************************************************* diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index ea171bdf1..5ec1af296 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -5,6 +5,9 @@ # # platform configs +ENABLE_CONSOLE_SPE := 0 +$(eval $(call add_define,ENABLE_CONSOLE_SPE)) + ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 0 $(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) @@ -42,7 +45,7 @@ $(eval $(call add_define,MAX_MMAP_REGIONS)) # platform files PLAT_INCLUDES += -I${SOC_DIR}/drivers/include -BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ +BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ ${COMMON_DIR}/drivers/smmu/smmu.c \ @@ -57,3 +60,7 @@ BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ ${SOC_DIR}/plat_sip_calls.c \ ${SOC_DIR}/plat_smmu.c \ ${SOC_DIR}/plat_trampoline.S + +ifeq (${ENABLE_CONSOLE_SPE},1) +BL31_SOURCES += ${COMMON_DIR}/drivers/spe/shared_console.S +endif diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c index 2a2d102f7..bfa818419 100644 --- a/plat/nvidia/tegra/soc/t210/plat_setup.c +++ b/plat/nvidia/tegra/soc/t210/plat_setup.c @@ -114,14 +114,30 @@ static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { }; /******************************************************************************* - * Retrieve the UART controller base to be used as the console + * Enable console corresponding to the console ID ******************************************************************************/ -uint32_t plat_get_console_from_id(int id) +void plat_enable_console(int32_t id) { - if (id > TEGRA210_MAX_UART_PORTS) - return 0; + static console_16550_t uart_console; + uint32_t console_clock; - return tegra210_uart_addresses[id]; + if ((id > 0) && (id < TEGRA210_MAX_UART_PORTS)) { + /* + * Reference clock used by the FPGAs is a lot slower. + */ + if (tegra_platform_is_fpga()) { + console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; + } else { + console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; + } + + (void)console_16550_register(tegra210_uart_addresses[id], + console_clock, + TEGRA_CONSOLE_BAUDRATE, + &uart_console); + console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | + CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); + } } /******************************************************************************* -- cgit v1.2.3 From 95397d96617ea2915ead715239ec7fc6e462c42f Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Thu, 30 Nov 2017 11:53:29 +0800 Subject: Tegra194: memctrl: fix logic to check TZDRAM config register access This patch fixes the logic to check if the previous bootloader has disabled access to the TZDRAM configuration registers. The polarity for the bit was incorrect in the previous check. Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03 Signed-off-by: Steven Kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 2 ++ plat/nvidia/tegra/soc/t194/plat_memctrl.c | 10 ++++++---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index bedf26888..212bd48e6 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -75,6 +75,8 @@ #define MC_SECURITY_CFG_REG_CTRL_0 U(0x154) #define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0) +#define SECURITY_CFG_WRITE_ACCESS_ENABLE U(0x0) +#define SECURITY_CFG_WRITE_ACCESS_DISABLE U(0x1) /* Video Memory carveout configuration registers */ #define MC_VIDEO_PROTECT_BASE_HI U(0x978) diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 75705cff1..54dbe7cdb 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -646,12 +646,14 @@ tegra_mc_settings_t *tegra_get_mc_settings(void) ******************************************************************************/ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) { + uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); + /* - * Check if the carveout register is already locked, if locked - * no TZDRAM setup + * Check TZDRAM carveout register access status. Setup TZDRAM fence + * only if access is enabled. */ - if ((tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0) & - SECURITY_CFG_WRITE_ACCESS_BIT) == SECURITY_CFG_WRITE_ACCESS_BIT) { + if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == + SECURITY_CFG_WRITE_ACCESS_ENABLE) { /* * Setup the Memory controller to allow only secure accesses to -- cgit v1.2.3 From 2d1f101067c9e5328b20fe41ef2a6a98e2d7c952 Mon Sep 17 00:00:00 2001 From: Jeetesh Burman Date: Mon, 22 Jan 2018 16:52:11 +0530 Subject: Tegra194: add support to reset GPU This patch adds macros, to define registers required to support GPU reset, for Tegra194 SoCs. Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526 Signed-off-by: Jeetesh Burman --- plat/nvidia/tegra/include/t194/tegra_def.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 212bd48e6..1a9ba0a84 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -204,6 +204,10 @@ * Tegra Clock and Reset Controller constants ******************************************************************************/ #define TEGRA_CAR_RESET_BASE U(0x20000000) +#define TEGRA_GPU_RESET_REG_OFFSET U(0x18) +#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C) +#define GPU_RESET_BIT (U(1) << 0) +#define GPU_SET_BIT (U(1) << 0) /******************************************************************************* * XUSB PADCTL -- cgit v1.2.3 From edbce9aad48fe71a6fed0df8d56eebb61e44632e Mon Sep 17 00:00:00 2001 From: zelalem-aweke Date: Tue, 12 Nov 2019 16:20:17 -0600 Subject: Enable Link Time Optimization in GCC This patch enables LTO for TF-A when compiled with GCC. LTO is disabled by default and is enabled by ENABLE_LTO=1 build option. LTO is enabled only for aarch64 as there seem to be a bug in the aarch32 compiler when LTO is enabled. The changes in the makefiles include: - Adding -flto and associated flags to enable LTO. - Using gcc as a wrapper at link time instead of ld. This is recommended when using LTO as gcc internally takes care of invoking the necessary plugins for LTO. - Adding switches to pass options to ld. - Adding a flag to disable fix for erratum cortex-a53-843419 unless explicitly enabled. This is needed because GCC seem to automatically add the erratum fix when used as a wrapper for LD. Additionally, this patch updates the TF-A user guide with the new build option. Signed-off-by: zelalem-aweke Change-Id: I1188c11974da98434b7dc9344e058cd1eacf5468 --- Makefile | 37 ++++++++++++++++++++++++++++++++-- docs/getting_started/build-options.rst | 4 ++++ make_helpers/build_macros.mk | 6 +++++- make_helpers/defaults.mk | 3 +++ 4 files changed, 47 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 721246d51..eddd48d5a 100644 --- a/Makefile +++ b/Makefile @@ -204,6 +204,18 @@ LD = $(LINKER) AS = $(CC) -c -x assembler-with-cpp $(TF_CFLAGS_$(ARCH)) CPP = $(CC) -E PP = $(CC) -E +else ifneq ($(findstring gcc,$(notdir $(CC))),) +TF_CFLAGS_aarch32 = $(march32-directive) +TF_CFLAGS_aarch64 = $(march64-directive) +ifeq ($(ENABLE_LTO),1) + # Enable LTO only for aarch64 + ifeq (${ARCH},aarch64) + LTO_CFLAGS = -flto + # Use gcc as a wrapper for the ld, recommended for LTO + LINKER := ${CROSS_COMPILE}gcc + endif +endif +LD = $(LINKER) else TF_CFLAGS_aarch32 = $(march32-directive) TF_CFLAGS_aarch64 = $(march64-directive) @@ -300,11 +312,28 @@ GCC_V_OUTPUT := $(shell $(CC) -v 2>&1) ifneq ($(findstring armlink,$(notdir $(LD))),) TF_LDFLAGS += --diag_error=warning --lto_level=O1 TF_LDFLAGS += --remove --info=unused,unusedsymbols +TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) +else ifneq ($(findstring gcc,$(notdir $(LD))),) +# Pass ld options with Wl or Xlinker switches +TF_LDFLAGS += -Wl,--fatal-warnings -O1 +TF_LDFLAGS += -Wl,--gc-sections +ifeq ($(ENABLE_LTO),1) + ifeq (${ARCH},aarch64) + TF_LDFLAGS += -flto -fuse-linker-plugin + endif +endif +# GCC automatically adds fix-cortex-a53-843419 flag when used to link +# which breaks some builds, so disable if errata fix is not explicitly enabled +ifneq (${ERRATA_A53_843419},1) + TF_LDFLAGS += -mno-fix-cortex-a53-843419 +endif +TF_LDFLAGS += -nostdlib +TF_LDFLAGS += $(subst --,-Xlinker --,$(TF_LDFLAGS_$(ARCH))) else TF_LDFLAGS += --fatal-warnings -O1 TF_LDFLAGS += --gc-sections -endif TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) +endif DTC_FLAGS += -I dts -O dtb DTC_CPPFLAGS += -nostdinc -Iinclude -undef -x assembler-with-cpp @@ -405,7 +434,11 @@ endif ifeq ($(ENABLE_PIE),1) TF_CFLAGS += -fpie - TF_LDFLAGS += -pie --no-dynamic-linker + ifneq ($(findstring gcc,$(notdir $(LD))),) + TF_LDFLAGS += -Wl,-pie -Wl,--no-dynamic-linker + else + TF_LDFLAGS += -pie --no-dynamic-linker + endif else PIE_FOUND := $(findstring --enable-default-pie,${GCC_V_OUTPUT}) ifneq ($(PIE_FOUND),) diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index fded1e0c9..051586bc3 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -196,6 +196,10 @@ Common build options builds, but this behaviour can be overridden in each platform's Makefile or in the build command line. + - ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) + support in GCC for TF-A. This option is currently only supported for + AArch64. Default is 0. + - ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM feature. MPAM is an optional Armv8.4 extension that enables various memory system components and resources to define partitions; software running at diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index b89d87ea6..47f3ebd86 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -236,7 +236,7 @@ $(eval BL_CFLAGS := $(BL$(call uppercase,$(3))_CFLAGS)) $(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs $$(ECHO) " CC $$<" - $$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) $(BL_CFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@ + $$(Q)$$(CC) $$(LTO_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(BL_CFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@ -include $(DEP) @@ -433,6 +433,10 @@ ifneq ($(findstring armlink,$(notdir $(LD))),) --map --list="$(MAPFILE)" --scatter=${PLAT_DIR}/scat/bl${1}.scat \ $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) \ $(BUILD_DIR)/build_message.o $(OBJS) +else ifneq ($(findstring gcc,$(notdir $(LD))),) + $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) -Wl,-Map=$(MAPFILE) \ + -Wl,-T$(LINKERFILE) $(BUILD_DIR)/build_message.o \ + $(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) else $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) -Map=$(MAPFILE) \ --script $(LINKERFILE) $(BUILD_DIR)/build_message.o \ diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index b7fb173b1..348b3e52b 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -239,3 +239,6 @@ SANITIZE_UB := off # implementation variant using the ARMv8.1-LSE compare-and-swap instruction. # Default: disabled USE_SPINLOCK_CAS := 0 + +# Enable Link Time Optimization +ENABLE_LTO := 0 -- cgit v1.2.3 From 4960ef301abb1bba83c5a51c3d53dc91ebb3c502 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Wed, 18 Sep 2019 14:36:06 +0100 Subject: Remove -Wunused-const-variable warning -Wunused-const-variable=1 is already included by -Wunused-variable, which is part of -Wall. -Wunused-const-variable=2, which is what we have been using as part of W=1, warns for unused static const variables in headers, which will likely produce a lot of false positives that will take a large effort to fix. Additionally, some of these issues may be caused by different builds of TF-A where some features are used in some builds and ignored in others. Change-Id: Ifa0b16a75344cc1f6240e8d5745005f8f2046d34 Signed-off-by: Justin Chadwell --- Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/Makefile b/Makefile index d634b336b..ba9f5d776 100644 --- a/Makefile +++ b/Makefile @@ -240,7 +240,6 @@ WARNING1 += -Wmissing-declarations WARNING1 += -Wmissing-format-attribute WARNING1 += -Wmissing-prototypes WARNING1 += -Wold-style-definition -WARNING1 += -Wunused-const-variable # Level 2 WARNING2 := -Waggregate-return -- cgit v1.2.3 From 5cffedcec2c0dda50e4172e0cfd769b0e6ad665c Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 14:18:48 -0500 Subject: allwinner: Fix incorrect ARISC code patch offset check The current range check for the offset is wrong: it is counting bytes, while indexing an array of uint32_t. Since the offset is always zero, the parameter is unnecessary. Instead of adding more code to fix the check, remove the parameter to avoid the problem entirely. Signed-off-by: Samuel Holland Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6 --- plat/allwinner/common/include/sunxi_private.h | 5 ++--- plat/allwinner/common/sunxi_common.c | 8 +++----- plat/allwinner/common/sunxi_cpu_ops.c | 2 +- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h index 11668797b..1f410559f 100644 --- a/plat/allwinner/common/include/sunxi_private.h +++ b/plat/allwinner/common/include/sunxi_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,6 @@ void sunxi_security_setup(void); uint16_t sunxi_read_soc_id(void); void sunxi_set_gpio_out(char port, int pin, bool level_high); int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb); -void sunxi_execute_arisc_code(uint32_t *code, size_t size, - int patch_offset, uint16_t param); +void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param); #endif /* SUNXI_PRIVATE_H */ diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c index 3b44aab68..0797452a6 100644 --- a/plat/allwinner/common/sunxi_common.c +++ b/plat/allwinner/common/sunxi_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -172,8 +172,7 @@ DEFINE_BAKERY_LOCK(arisc_lock); * in SRAM, put the address of that into the reset vector and release the * arisc reset line. The SCP will execute that code and pull the line up again. */ -void sunxi_execute_arisc_code(uint32_t *code, size_t size, - int patch_offset, uint16_t param) +void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param) { uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE - 0x4000 + 0x100; @@ -187,8 +186,7 @@ void sunxi_execute_arisc_code(uint32_t *code, size_t size, } while (1); /* Patch up the code to feed in an input parameter. */ - if (patch_offset >= 0 && patch_offset <= (size - 4)) - code[patch_offset] = (code[patch_offset] & ~0xffff) | param; + code[0] = (code[0] & ~0xffff) | param; clean_dcache_range((uintptr_t)code, size); /* diff --git a/plat/allwinner/common/sunxi_cpu_ops.c b/plat/allwinner/common/sunxi_cpu_ops.c index b4c9fcc18..6e29b69bf 100644 --- a/plat/allwinner/common/sunxi_cpu_ops.c +++ b/plat/allwinner/common/sunxi_cpu_ops.c @@ -78,7 +78,7 @@ void sunxi_cpu_off(u_register_t mpidr) * patched into the first instruction. */ sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off), - 0, BIT_32(core)); + BIT_32(core)); } void sunxi_cpu_on(u_register_t mpidr) -- cgit v1.2.3 From e8bb1c2caa19fa224090eca0793586857199af9e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 4 Dec 2019 02:48:37 -0600 Subject: imx: Fix missing inclusion of cdefs.h This was found by compiling with -fno-common: ./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed'; ./build/picopi/release/bl2/imx_caam.o:(.bss.__packed+0x0): first defined here __packed was intended to be the attribute macro from cdefs.h, not an object of the structure type. Signed-off-by: Samuel Holland Change-Id: Id02fac3f098be2d71c35c6b4a18012515532f32a --- plat/imx/common/include/imx_caam.h | 3 ++- plat/imx/common/include/imx_snvs.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/plat/imx/common/include/imx_caam.h b/plat/imx/common/include/imx_caam.h index 335bd0f8b..61005b51c 100644 --- a/plat/imx/common/include/imx_caam.h +++ b/plat/imx/common/include/imx_caam.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #ifndef IMX_CAAM_H #define IMX_CAAM_H +#include #include #include #include diff --git a/plat/imx/common/include/imx_snvs.h b/plat/imx/common/include/imx_snvs.h index 0b3d1085f..565c451dd 100644 --- a/plat/imx/common/include/imx_snvs.h +++ b/plat/imx/common/include/imx_snvs.h @@ -1,11 +1,12 @@ /* - * Copyright (C) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (C) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef IMX_SNVS_H #define IMX_SNVS_H +#include #include #include -- cgit v1.2.3 From 118a67a9a3a810d37bca89aab28922769ca04a84 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 4 Dec 2019 02:45:58 -0600 Subject: imx: Fix multiple definition of ipc_handle This is not conforming C and does not compile with -fno-common. Signed-off-by: Samuel Holland Change-Id: I6535954cc567d6efa06919069b91e3f50975b073 --- plat/imx/common/include/sci/sci_ipc.h | 4 ++-- plat/imx/common/sci/ipc.c | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/plat/imx/common/include/sci/sci_ipc.h b/plat/imx/common/include/sci/sci_ipc.h index 1167ea367..39e9012bc 100644 --- a/plat/imx/common/include/sci/sci_ipc.h +++ b/plat/imx/common/include/sci/sci_ipc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,6 +62,6 @@ void sc_ipc_read(sc_ipc_t ipc, void *data); */ void sc_ipc_write(sc_ipc_t ipc, void *data); -sc_ipc_t ipc_handle; +extern sc_ipc_t ipc_handle; #endif /* SCI_IPC_H */ diff --git a/plat/imx/common/sci/ipc.c b/plat/imx/common/sci/ipc.c index 6491ca575..576911925 100644 --- a/plat/imx/common/sci/ipc.c +++ b/plat/imx/common/sci/ipc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,8 @@ #include #include "imx8_mu.h" +sc_ipc_t ipc_handle; + DEFINE_BAKERY_LOCK(sc_ipc_bakery_lock); #define sc_ipc_lock_init() bakery_lock_init(&sc_ipc_bakery_lock) #define sc_ipc_lock() bakery_lock_get(&sc_ipc_bakery_lock) -- cgit v1.2.3 From ebd6efae67c6a086bc97d807a638bde324d936dc Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 16:11:25 -0500 Subject: Reduce space lost to object alignment Currently, sections within .text/.rodata/.data/.bss are emitted in the order they are seen by the linker. This leads to wasted space, when a section with a larger alignment follows one with a smaller alignment. We can avoid this wasted space by sorting the sections. To take full advantage of this, we must disable generation of common symbols, so "common" data can be sorted along with the rest of .bss. An example of the improvement, from `make DEBUG=1 PLAT=sun50i_a64 bl31`: .text => no change .rodata => 16 bytes saved .data => 11 bytes saved .bss => 576 bytes saved As a side effect, the addition of `-fno-common` in TF_CFLAGS makes it easier to spot bugs in header files. Signed-off-by: Samuel Holland Change-Id: I073630a9b0b84e7302a7a500d4bb4b547be01d51 --- Makefile | 5 +++-- bl1/bl1.ld.S | 14 +++++++------- bl2/bl2.ld.S | 12 ++++++------ bl2/bl2_el3.ld.S | 12 ++++++------ bl2u/bl2u.ld.S | 12 ++++++------ bl31/bl31.ld.S | 12 ++++++------ 6 files changed, 34 insertions(+), 33 deletions(-) diff --git a/Makefile b/Makefile index d634b336b..e10004b70 100644 --- a/Makefile +++ b/Makefile @@ -285,8 +285,9 @@ CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \ ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \ -ffreestanding -Wa,--fatal-warnings TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ - -ffreestanding -fno-builtin -std=gnu99 \ - -Os -ffunction-sections -fdata-sections + -ffunction-sections -fdata-sections \ + -ffreestanding -fno-builtin -fno-common \ + -Os -std=gnu99 ifeq (${SANITIZE_UB},on) TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index c4f6b99fc..877af8e01 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl1_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -44,7 +44,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -72,8 +72,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl1_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -114,7 +114,7 @@ SECTIONS */ .data . : ALIGN(16) { __DATA_RAM_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_RAM_END__ = .; } >RAM AT>ROM @@ -131,7 +131,7 @@ SECTIONS */ .bss : ALIGN(16) { __BSS_START__ = .; - *(.bss*) + *(SORT_BY_ALIGNMENT(.bss*)) *(COMMON) __BSS_END__ = .; } >RAM diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index 30cdf7d78..6230562ed 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl2_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -44,7 +44,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -59,8 +59,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl2_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -93,7 +93,7 @@ SECTIONS */ .data . : { __DATA_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_END__ = .; } >RAM diff --git a/bl2/bl2_el3.ld.S b/bl2/bl2_el3.ld.S index 82b51a862..dc398eb02 100644 --- a/bl2/bl2_el3.ld.S +++ b/bl2/bl2_el3.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,7 +44,7 @@ SECTIONS *bl2_el3_entrypoint.o(.text*) *(.text.asm.*) __TEXT_RESIDENT_END__ = .; - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -52,7 +52,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -82,8 +82,8 @@ SECTIONS *bl2_el3_entrypoint.o(.text*) *(.text.asm.*) __TEXT_RESIDENT_END__ = .; - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* * Ensure 8-byte alignment for cpu_ops so that its fields are also @@ -135,7 +135,7 @@ SECTIONS */ .data . : { __DATA_RAM_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_RAM_END__ = .; } >RAM AT>ROM diff --git a/bl2u/bl2u.ld.S b/bl2u/bl2u.ld.S index 8d4984fbf..8d257cee9 100644 --- a/bl2u/bl2u.ld.S +++ b/bl2u/bl2u.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl2u_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -44,7 +44,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; } >RAM @@ -52,8 +52,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl2u_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) *(.vectors) __RO_END_UNALIGNED__ = .; @@ -80,7 +80,7 @@ SECTIONS */ .data . : { __DATA_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_END__ = .; } >RAM diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index c7d587cb0..708ee329f 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -33,7 +33,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl31_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -41,7 +41,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -87,8 +87,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl31_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -179,7 +179,7 @@ SECTIONS */ .data . : { __DATA_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_END__ = .; } >RAM @@ -211,7 +211,7 @@ SECTIONS */ .bss (NOLOAD) : ALIGN(16) { __BSS_START__ = .; - *(.bss*) + *(SORT_BY_ALIGNMENT(.bss*)) *(COMMON) #if !USE_COHERENT_MEM /* -- cgit v1.2.3 From d005cfbfd98f5450559178f57e1df9acaab42cb6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bence=20Sz=C3=A9pk=C3=BAti?= Date: Fri, 25 Oct 2019 16:52:55 +0200 Subject: libc: Unify intmax_t and uintmax_t on AArch32/64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Conceptually, these are supposed to be the largest integers representable in C, but GCC and Clang define them as long long for compatibility. Signed-off-by: Bence Szépkúti Change-Id: I7c0117f3be167342814d260a371889120dcf6576 --- include/lib/libc/aarch32/stdint_.h | 6 +++++- include/lib/libc/aarch64/stdint_.h | 10 +++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/lib/libc/aarch32/stdint_.h b/include/lib/libc/aarch32/stdint_.h index 4f494859f..def24aabc 100644 --- a/include/lib/libc/aarch32/stdint_.h +++ b/include/lib/libc/aarch32/stdint_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -111,6 +111,10 @@ typedef unsigned long long uint64_fast_t; typedef long intptr_t; typedef unsigned long uintptr_t; +/* + * Conceptually, these are supposed to be the largest integers representable in C, + * but GCC and Clang define them as long long for compatibility. + */ typedef long long intmax_t; typedef unsigned long long uintmax_t; diff --git a/include/lib/libc/aarch64/stdint_.h b/include/lib/libc/aarch64/stdint_.h index b17a435b0..25680bbd6 100644 --- a/include/lib/libc/aarch64/stdint_.h +++ b/include/lib/libc/aarch64/stdint_.h @@ -75,7 +75,7 @@ #define UINT32_C(x) x ## U #define UINT64_C(x) x ## ULL -#define INTMAX_C(x) x ## L +#define INTMAX_C(x) x ## LL #define UINTMAX_C(x) x ## ULL typedef signed char int8_t; @@ -111,8 +111,12 @@ typedef unsigned long long uint64_fast_t; typedef long intptr_t; typedef unsigned long uintptr_t; -typedef long intmax_t; -typedef unsigned long uintmax_t; +/* + * Conceptually, these are supposed to be the largest integers representable in C, + * but GCC and Clang define them as long long for compatibility. + */ +typedef long long intmax_t; +typedef unsigned long long uintmax_t; typedef long register_t; typedef unsigned long u_register_t; -- cgit v1.2.3 From b382ac6887b864ff4252022cbeb13f0405daff79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bence=20Sz=C3=A9pk=C3=BAti?= Date: Fri, 25 Oct 2019 17:48:20 +0200 Subject: libc: Consolidate unified definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As supporting architectures aside from AArch32 and AArch64 is not a concern, keeping identical definitions in two places for a large part of the libc seems counterproductive The int128 types were left un-unified as __int128 is not supported by gcc on AArch32 Signed-off-by: Bence Szépkúti Change-Id: Idf08e6fab7e4680d9da62d3c57266ea2d80472cf --- drivers/arm/sbsa/sbsa.c | 6 +- include/lib/libc/aarch32/stddef_.h | 7 +-- include/lib/libc/aarch32/stdint_.h | 122 ----------------------------------- include/lib/libc/aarch32/stdlib_.h | 5 +- include/lib/libc/aarch32/time_.h | 4 +- include/lib/libc/aarch64/stddef_.h | 7 +-- include/lib/libc/aarch64/stdint_.h | 125 ------------------------------------ include/lib/libc/aarch64/stdlib_.h | 5 +- include/lib/libc/aarch64/time_.h | 4 +- include/lib/libc/stddef.h | 7 ++- include/lib/libc/stdint.h | 126 ++++++++++++++++++++++++++++++++++++- include/lib/libc/stdlib.h | 5 +- include/lib/libc/time.h | 4 +- 13 files changed, 146 insertions(+), 281 deletions(-) delete mode 100644 include/lib/libc/aarch32/stdint_.h delete mode 100644 include/lib/libc/aarch64/stdint_.h diff --git a/drivers/arm/sbsa/sbsa.c b/drivers/arm/sbsa/sbsa.c index 6f00a6019..79c6f2620 100644 --- a/drivers/arm/sbsa/sbsa.c +++ b/drivers/arm/sbsa/sbsa.c @@ -4,11 +4,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include +#include +#include #include #include -#include -#include +#include void sbsa_watchdog_offset_reg_write(uintptr_t base, uint64_t value) { diff --git a/include/lib/libc/aarch32/stddef_.h b/include/lib/libc/aarch32/stddef_.h index 1babfade3..36dc20bd4 100644 --- a/include/lib/libc/aarch32/stddef_.h +++ b/include/lib/libc/aarch32/stddef_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,4 @@ typedef unsigned int size_t; #define SIZET_ #endif -#ifndef _PTRDIFF_T -typedef long ptrdiff_t; -#define _PTRDIFF_T -#endif - #endif /* STDDEF__H */ diff --git a/include/lib/libc/aarch32/stdint_.h b/include/lib/libc/aarch32/stdint_.h deleted file mode 100644 index def24aabc..000000000 --- a/include/lib/libc/aarch32/stdint_.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define INT8_MAX 0x7F -#define INT8_MIN (-INT8_MAX - 1) -#define UINT8_MAX 0xFFU - -#define INT16_MAX 0x7FFF -#define INT16_MIN (-INT16_MAX - 1) -#define UINT16_MAX 0xFFFFU - -#define INT32_MAX 0x7FFFFFFF -#define INT32_MIN (-INT32_MAX - 1) -#define UINT32_MAX 0xFFFFFFFFU - -#define INT64_MAX 0x7FFFFFFFFFFFFFFFLL -#define INT64_MIN (-INT64_MAX - 1LL) -#define UINT64_MAX 0xFFFFFFFFFFFFFFFFULL - -#define INT_LEAST8_MIN INT8_MIN -#define INT_LEAST8_MAX INT8_MAX -#define UINT_LEAST8_MAX UINT8_MAX - -#define INT_LEAST16_MIN INT16_MIN -#define INT_LEAST16_MAX INT16_MAX -#define UINT_LEAST16_MAX UINT16_MAX - -#define INT_LEAST32_MIN INT32_MIN -#define INT_LEAST32_MAX INT32_MAX -#define UINT_LEAST32_MAX UINT32_MAX - -#define INT_LEAST64_MIN INT64_MIN -#define INT_LEAST64_MAX INT64_MAX -#define UINT_LEAST64_MAX UINT64_MAX - -#define INT_FAST8_MIN INT32_MIN -#define INT_FAST8_MAX INT32_MAX -#define UINT_FAST8_MAX UINT32_MAX - -#define INT_FAST16_MIN INT32_MIN -#define INT_FAST16_MAX INT32_MAX -#define UINT_FAST16_MAX UINT32_MAX - -#define INT_FAST32_MIN INT32_MIN -#define INT_FAST32_MAX INT32_MAX -#define UINT_FAST32_MAX UINT32_MAX - -#define INT_FAST64_MIN INT64_MIN -#define INT_FAST64_MAX INT64_MAX -#define UINT_FAST64_MAX UINT64_MAX - -#define INTPTR_MIN INT32_MIN -#define INTPTR_MAX INT32_MAX -#define UINTPTR_MAX UINT32_MAX - -#define INTMAX_MIN INT64_MIN -#define INTMAX_MAX INT64_MAX -#define UINTMAX_MAX UINT64_MAX - -#define PTRDIFF_MIN INT32_MIN -#define PTRDIFF_MAX INT32_MAX - -#define SIZE_MAX UINT32_MAX - -#define INT8_C(x) x -#define INT16_C(x) x -#define INT32_C(x) x -#define INT64_C(x) x ## LL - -#define UINT8_C(x) x -#define UINT16_C(x) x -#define UINT32_C(x) x ## U -#define UINT64_C(x) x ## ULL - -#define INTMAX_C(x) x ## LL -#define UINTMAX_C(x) x ## ULL - -typedef signed char int8_t; -typedef short int16_t; -typedef int int32_t; -typedef long long int64_t; - -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; -typedef unsigned long long uint64_t; - -typedef signed char int8_least_t; -typedef short int16_least_t; -typedef int int32_least_t; -typedef long long int64_least_t; - -typedef unsigned char uint8_least_t; -typedef unsigned short uint16_least_t; -typedef unsigned int uint32_least_t; -typedef unsigned long long uint64_least_t; - -typedef int int8_fast_t; -typedef int int16_fast_t; -typedef int int32_fast_t; -typedef long long int64_fast_t; - -typedef unsigned int uint8_fast_t; -typedef unsigned int uint16_fast_t; -typedef unsigned int uint32_fast_t; -typedef unsigned long long uint64_fast_t; - -typedef long intptr_t; -typedef unsigned long uintptr_t; - -/* - * Conceptually, these are supposed to be the largest integers representable in C, - * but GCC and Clang define them as long long for compatibility. - */ -typedef long long intmax_t; -typedef unsigned long long uintmax_t; - -typedef long register_t; -typedef unsigned long u_register_t; diff --git a/include/lib/libc/aarch32/stdlib_.h b/include/lib/libc/aarch32/stdlib_.h index 9c07857a5..ff53b6f92 100644 --- a/include/lib/libc/aarch32/stdlib_.h +++ b/include/lib/libc/aarch32/stdlib_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,4 @@ typedef unsigned int size_t; #define SIZET_ #endif -#define EXIT_FAILURE 1 -#define EXIT_SUCCESS 0 - #endif /* STDLIB__H */ diff --git a/include/lib/libc/aarch32/time_.h b/include/lib/libc/aarch32/time_.h index a9169c293..cfd487dc6 100644 --- a/include/lib/libc/aarch32/time_.h +++ b/include/lib/libc/aarch32/time_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,4 @@ typedef unsigned int size_t; #define SIZET_ #endif -typedef long int time_t; - #endif /* TIME__H */ diff --git a/include/lib/libc/aarch64/stddef_.h b/include/lib/libc/aarch64/stddef_.h index b7d8209af..6ecc6067c 100644 --- a/include/lib/libc/aarch64/stddef_.h +++ b/include/lib/libc/aarch64/stddef_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,4 @@ typedef unsigned long size_t; #define SIZET_ #endif -#ifndef _PTRDIFF_T -typedef long ptrdiff_t; -#define _PTRDIFF_T -#endif - #endif /* STDDEF__H */ diff --git a/include/lib/libc/aarch64/stdint_.h b/include/lib/libc/aarch64/stdint_.h deleted file mode 100644 index 25680bbd6..000000000 --- a/include/lib/libc/aarch64/stdint_.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define INT8_MAX 0x7F -#define INT8_MIN (-INT8_MAX - 1) -#define UINT8_MAX 0xFFU - -#define INT16_MAX 0x7FFF -#define INT16_MIN (-INT16_MAX - 1) -#define UINT16_MAX 0xFFFFU - -#define INT32_MAX 0x7FFFFFFF -#define INT32_MIN (-INT32_MAX - 1) -#define UINT32_MAX 0xFFFFFFFFU - -#define INT64_MAX 0x7FFFFFFFFFFFFFFFLL -#define INT64_MIN (-INT64_MAX - 1LL) -#define UINT64_MAX 0xFFFFFFFFFFFFFFFFULL - -#define INT_LEAST8_MIN INT8_MIN -#define INT_LEAST8_MAX INT8_MAX -#define UINT_LEAST8_MAX UINT8_MAX - -#define INT_LEAST16_MIN INT16_MIN -#define INT_LEAST16_MAX INT16_MAX -#define UINT_LEAST16_MAX UINT16_MAX - -#define INT_LEAST32_MIN INT32_MIN -#define INT_LEAST32_MAX INT32_MAX -#define UINT_LEAST32_MAX UINT32_MAX - -#define INT_LEAST64_MIN INT64_MIN -#define INT_LEAST64_MAX INT64_MAX -#define UINT_LEAST64_MAX UINT64_MAX - -#define INT_FAST8_MIN INT32_MIN -#define INT_FAST8_MAX INT32_MAX -#define UINT_FAST8_MAX UINT32_MAX - -#define INT_FAST16_MIN INT32_MIN -#define INT_FAST16_MAX INT32_MAX -#define UINT_FAST16_MAX UINT32_MAX - -#define INT_FAST32_MIN INT32_MIN -#define INT_FAST32_MAX INT32_MAX -#define UINT_FAST32_MAX UINT32_MAX - -#define INT_FAST64_MIN INT64_MIN -#define INT_FAST64_MAX INT64_MAX -#define UINT_FAST64_MAX UINT64_MAX - -#define INTPTR_MIN INT64_MIN -#define INTPTR_MAX INT64_MAX -#define UINTPTR_MAX UINT64_MAX - -#define INTMAX_MIN INT64_MIN -#define INTMAX_MAX INT64_MAX -#define UINTMAX_MAX UINT64_MAX - -#define PTRDIFF_MIN INT64_MIN -#define PTRDIFF_MAX INT64_MAX - -#define SIZE_MAX UINT64_MAX - -#define INT8_C(x) x -#define INT16_C(x) x -#define INT32_C(x) x -#define INT64_C(x) x ## LL - -#define UINT8_C(x) x -#define UINT16_C(x) x -#define UINT32_C(x) x ## U -#define UINT64_C(x) x ## ULL - -#define INTMAX_C(x) x ## LL -#define UINTMAX_C(x) x ## ULL - -typedef signed char int8_t; -typedef short int16_t; -typedef int int32_t; -typedef long long int64_t; - -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; -typedef unsigned long long uint64_t; - -typedef signed char int8_least_t; -typedef short int16_least_t; -typedef int int32_least_t; -typedef long long int64_least_t; - -typedef unsigned char uint8_least_t; -typedef unsigned short uint16_least_t; -typedef unsigned int uint32_least_t; -typedef unsigned long long uint64_least_t; - -typedef int int8_fast_t; -typedef int int16_fast_t; -typedef int int32_fast_t; -typedef long long int64_fast_t; - -typedef unsigned int uint8_fast_t; -typedef unsigned int uint16_fast_t; -typedef unsigned int uint32_fast_t; -typedef unsigned long long uint64_fast_t; - -typedef long intptr_t; -typedef unsigned long uintptr_t; - -/* - * Conceptually, these are supposed to be the largest integers representable in C, - * but GCC and Clang define them as long long for compatibility. - */ -typedef long long intmax_t; -typedef unsigned long long uintmax_t; - -typedef long register_t; -typedef unsigned long u_register_t; - -typedef __int128 int128_t; -typedef unsigned __int128 uint128_t; diff --git a/include/lib/libc/aarch64/stdlib_.h b/include/lib/libc/aarch64/stdlib_.h index 81a39d14a..531308a2e 100644 --- a/include/lib/libc/aarch64/stdlib_.h +++ b/include/lib/libc/aarch64/stdlib_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,4 @@ typedef unsigned long size_t; #define SIZET_ #endif -#define EXIT_FAILURE 1 -#define EXIT_SUCCESS 0 - #endif /* STDLIB__H */ diff --git a/include/lib/libc/aarch64/time_.h b/include/lib/libc/aarch64/time_.h index 68ab1b8dd..8b298a39d 100644 --- a/include/lib/libc/aarch64/time_.h +++ b/include/lib/libc/aarch64/time_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,4 @@ typedef unsigned long size_t; #define SIZET_ #endif -typedef long int time_t; - #endif /* TIME__H */ diff --git a/include/lib/libc/stddef.h b/include/lib/libc/stddef.h index c9957bdb1..58a519e52 100644 --- a/include/lib/libc/stddef.h +++ b/include/lib/libc/stddef.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ @@ -13,6 +13,11 @@ #include +#ifndef _PTRDIFF_T +typedef long ptrdiff_t; +#define _PTRDIFF_T +#endif + #ifndef NULL #define NULL ((void *) 0) #endif diff --git a/include/lib/libc/stdint.h b/include/lib/libc/stdint.h index d44a973f1..80b3e965d 100644 --- a/include/lib/libc/stdint.h +++ b/include/lib/libc/stdint.h @@ -4,13 +4,135 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ #ifndef STDINT_H #define STDINT_H -#include +#include + +#define INT8_MAX CHAR_MAX +#define INT8_MIN CHAR_MIN +#define UINT8_MAX UCHAR_MAX + +#define INT16_MAX SHRT_MAX +#define INT16_MIN SHRT_MIN +#define UINT16_MAX USHRT_MAX + +#define INT32_MAX INT_MAX +#define INT32_MIN INT_MIN +#define UINT32_MAX UINT_MAX + +#define INT64_MAX LLONG_MAX +#define INT64_MIN LLONG_MIN +#define UINT64_MAX ULLONG_MAX + +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST8_MAX INT8_MAX +#define UINT_LEAST8_MAX UINT8_MAX + +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST16_MAX INT16_MAX +#define UINT_LEAST16_MAX UINT16_MAX + +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST32_MAX INT32_MAX +#define UINT_LEAST32_MAX UINT32_MAX + +#define INT_LEAST64_MIN INT64_MIN +#define INT_LEAST64_MAX INT64_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +#define INT_FAST8_MIN INT32_MIN +#define INT_FAST8_MAX INT32_MAX +#define UINT_FAST8_MAX UINT32_MAX + +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST16_MAX INT32_MAX +#define UINT_FAST16_MAX UINT32_MAX + +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST32_MAX INT32_MAX +#define UINT_FAST32_MAX UINT32_MAX + +#define INT_FAST64_MIN INT64_MIN +#define INT_FAST64_MAX INT64_MAX +#define UINT_FAST64_MAX UINT64_MAX + +#define INTPTR_MIN LONG_MIN +#define INTPTR_MAX LONG_MAX +#define UINTPTR_MAX ULONG_MAX + +#define INTMAX_MIN LLONG_MIN +#define INTMAX_MAX LLONG_MAX +#define UINTMAX_MAX ULLONG_MAX + +#define PTRDIFF_MIN LONG_MIN +#define PTRDIFF_MAX LONG_MAX + +#define SIZE_MAX UINT64_MAX + +#define INT8_C(x) x +#define INT16_C(x) x +#define INT32_C(x) x +#define INT64_C(x) x ## LL + +#define UINT8_C(x) x +#define UINT16_C(x) x +#define UINT32_C(x) x ## U +#define UINT64_C(x) x ## ULL + +#define INTMAX_C(x) x ## LL +#define UINTMAX_C(x) x ## ULL + +typedef signed char int8_t; +typedef short int16_t; +typedef int int32_t; +typedef long long int64_t; + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; + +typedef signed char int8_least_t; +typedef short int16_least_t; +typedef int int32_least_t; +typedef long long int64_least_t; + +typedef unsigned char uint8_least_t; +typedef unsigned short uint16_least_t; +typedef unsigned int uint32_least_t; +typedef unsigned long long uint64_least_t; + +typedef int int8_fast_t; +typedef int int16_fast_t; +typedef int int32_fast_t; +typedef long long int64_fast_t; + +typedef unsigned int uint8_fast_t; +typedef unsigned int uint16_fast_t; +typedef unsigned int uint32_fast_t; +typedef unsigned long long uint64_fast_t; + +typedef long intptr_t; +typedef unsigned long uintptr_t; + +/* +* Conceptually, these are supposed to be the largest integers representable in C, +* but GCC and Clang define them as long long for compatibility. +*/ +typedef long long intmax_t; +typedef unsigned long long uintmax_t; + +typedef long register_t; +typedef unsigned long u_register_t; + +#ifdef __aarch64__ +typedef __int128 int128_t; +typedef unsigned __int128 uint128_t; +#endif /* __aarch64__ */ #endif /* STDINT_H */ diff --git a/include/lib/libc/stdlib.h b/include/lib/libc/stdlib.h index edd6265f5..84ba37f9a 100644 --- a/include/lib/libc/stdlib.h +++ b/include/lib/libc/stdlib.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ @@ -13,6 +13,9 @@ #include +#define EXIT_FAILURE 1 +#define EXIT_SUCCESS 0 + #ifndef NULL #define NULL ((void *) 0) #endif diff --git a/include/lib/libc/time.h b/include/lib/libc/time.h index 71d3e7ec9..714884b05 100644 --- a/include/lib/libc/time.h +++ b/include/lib/libc/time.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ @@ -13,6 +13,8 @@ #include +typedef long int time_t; + #ifndef NULL #define NULL ((void *) 0) #endif -- cgit v1.2.3 From d45c323a9c34404cbec5711acc9ba2dced8e1ba7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bence=20Sz=C3=A9pk=C3=BAti?= Date: Fri, 25 Oct 2019 18:12:41 +0200 Subject: libc: Consolidate the size_t and NULL definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Consolidate the definition of size_t to one header per AArch, and the definition of NULL to one header Signed-off-by: Bence Szépkúti Change-Id: Iecfbad2cf360cfb705ce7aaa981700fd16219b82 --- include/lib/libc/aarch32/stdio_.h | 7 +------ include/lib/libc/aarch32/stdlib_.h | 15 --------------- include/lib/libc/aarch32/string_.h | 15 --------------- include/lib/libc/aarch32/time_.h | 15 --------------- include/lib/libc/aarch64/stdio_.h | 7 +------ include/lib/libc/aarch64/stdlib_.h | 15 --------------- include/lib/libc/aarch64/string_.h | 15 --------------- include/lib/libc/aarch64/time_.h | 15 --------------- include/lib/libc/stdio.h | 7 ++----- include/lib/libc/stdlib.h | 6 +----- include/lib/libc/string.h | 8 ++------ include/lib/libc/time.h | 6 +----- 12 files changed, 8 insertions(+), 123 deletions(-) delete mode 100644 include/lib/libc/aarch32/stdlib_.h delete mode 100644 include/lib/libc/aarch32/string_.h delete mode 100644 include/lib/libc/aarch32/time_.h delete mode 100644 include/lib/libc/aarch64/stdlib_.h delete mode 100644 include/lib/libc/aarch64/string_.h delete mode 100644 include/lib/libc/aarch64/time_.h diff --git a/include/lib/libc/aarch32/stdio_.h b/include/lib/libc/aarch32/stdio_.h index 50d3cc2ed..5e49425cb 100644 --- a/include/lib/libc/aarch32/stdio_.h +++ b/include/lib/libc/aarch32/stdio_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,11 +7,6 @@ #ifndef STDIO__H #define STDIO__H -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - #ifndef SSIZET_ typedef int ssize_t; #define SSIZET_ diff --git a/include/lib/libc/aarch32/stdlib_.h b/include/lib/libc/aarch32/stdlib_.h deleted file mode 100644 index ff53b6f92..000000000 --- a/include/lib/libc/aarch32/stdlib_.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STDLIB__H -#define STDLIB__H - -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - -#endif /* STDLIB__H */ diff --git a/include/lib/libc/aarch32/string_.h b/include/lib/libc/aarch32/string_.h deleted file mode 100644 index 4e139b0db..000000000 --- a/include/lib/libc/aarch32/string_.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STRING__H -#define STRING__H - -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - -#endif /* STRING__H */ diff --git a/include/lib/libc/aarch32/time_.h b/include/lib/libc/aarch32/time_.h deleted file mode 100644 index cfd487dc6..000000000 --- a/include/lib/libc/aarch32/time_.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef TIME__H -#define TIME__H - -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - -#endif /* TIME__H */ diff --git a/include/lib/libc/aarch64/stdio_.h b/include/lib/libc/aarch64/stdio_.h index 09b0172dd..afaeadc21 100644 --- a/include/lib/libc/aarch64/stdio_.h +++ b/include/lib/libc/aarch64/stdio_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,11 +7,6 @@ #ifndef STDIO__H #define STDIO__H -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - #ifndef SSIZET_ typedef long ssize_t; #define SSIZET_ diff --git a/include/lib/libc/aarch64/stdlib_.h b/include/lib/libc/aarch64/stdlib_.h deleted file mode 100644 index 531308a2e..000000000 --- a/include/lib/libc/aarch64/stdlib_.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STDLIB__H -#define STDLIB__H - -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - -#endif /* STDLIB__H */ diff --git a/include/lib/libc/aarch64/string_.h b/include/lib/libc/aarch64/string_.h deleted file mode 100644 index 71c51a6cd..000000000 --- a/include/lib/libc/aarch64/string_.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STRING__H -#define STRING__H - -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - -#endif /* STRING__H */ diff --git a/include/lib/libc/aarch64/time_.h b/include/lib/libc/aarch64/time_.h deleted file mode 100644 index 8b298a39d..000000000 --- a/include/lib/libc/aarch64/time_.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef TIME__H -#define TIME__H - -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - -#endif /* TIME__H */ diff --git a/include/lib/libc/stdio.h b/include/lib/libc/stdio.h index 3d9323efa..2d9e6557b 100644 --- a/include/lib/libc/stdio.h +++ b/include/lib/libc/stdio.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ @@ -12,12 +12,9 @@ #define STDIO_H #include +#include #include -#ifndef NULL -#define NULL ((void *) 0) -#endif - #define EOF -1 int printf(const char *fmt, ...) __printflike(1, 2); diff --git a/include/lib/libc/stdlib.h b/include/lib/libc/stdlib.h index 84ba37f9a..24e7bae2f 100644 --- a/include/lib/libc/stdlib.h +++ b/include/lib/libc/stdlib.h @@ -11,15 +11,11 @@ #ifndef STDLIB_H #define STDLIB_H -#include +#include #define EXIT_FAILURE 1 #define EXIT_SUCCESS 0 -#ifndef NULL -#define NULL ((void *) 0) -#endif - #define _ATEXIT_MAX 1 extern void abort(void); diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h index ee6eeacef..c92b6808c 100644 --- a/include/lib/libc/string.h +++ b/include/lib/libc/string.h @@ -4,18 +4,14 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ #ifndef STRING_H #define STRING_H -#include - -#ifndef NULL -#define NULL ((void *) 0) -#endif +#include void *memcpy(void *dst, const void *src, size_t len); void *memmove(void *dst, const void *src, size_t len); diff --git a/include/lib/libc/time.h b/include/lib/libc/time.h index 714884b05..c1c95e586 100644 --- a/include/lib/libc/time.h +++ b/include/lib/libc/time.h @@ -11,12 +11,8 @@ #ifndef TIME_H #define TIME_H -#include +#include typedef long int time_t; -#ifndef NULL -#define NULL ((void *) 0) -#endif - #endif /* TIME_H */ -- cgit v1.2.3 From 0376e7c4aa2ce9ae94d72555cea27cd7aff8e32a Mon Sep 17 00:00:00 2001 From: Achin Gupta Date: Fri, 11 Oct 2019 14:44:05 +0100 Subject: Add support for enabling S-EL2 This patch adds support for enabling S-EL2 if this EL is specified in the entry point information being used to initialise a secure context. It is the caller's responsibility to check if S-EL2 is available on the system before requesting this EL through the entry point information. Signed-off-by: Achin Gupta Change-Id: I2752964f078ab528b2e80de71c7d2f35e60569e1 --- include/arch/aarch64/arch.h | 3 +++ lib/el3_runtime/aarch64/context_mgmt.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 3ff2912f1..e48e20185 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -140,6 +140,8 @@ #define ID_AA64PFR0_GIC_MASK ULL(0xf) #define ID_AA64PFR0_SVE_SHIFT U(32) #define ID_AA64PFR0_SVE_MASK ULL(0xf) +#define ID_AA64PFR0_SEL2_SHIFT U(36) +#define ID_AA64PFR0_SEL2_MASK U(0xf) #define ID_AA64PFR0_MPAM_SHIFT U(40) #define ID_AA64PFR0_MPAM_MASK ULL(0xf) #define ID_AA64PFR0_DIT_SHIFT U(48) @@ -285,6 +287,7 @@ #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) #define SCR_ATA_BIT (U(1) << 26) #define SCR_FIEN_BIT (U(1) << 21) +#define SCR_EEL2_BIT (U(1) << 18) #define SCR_API_BIT (U(1) << 17) #define SCR_APK_BIT (U(1) << 16) #define SCR_TWE_BIT (U(1) << 13) diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index d65e02d5e..752a2606e 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -181,6 +181,10 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) scr_el3 |= SCR_HCE_BIT; } + /* Enable S-EL2 if the next EL is EL2 and security state is secure */ + if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) + scr_el3 |= SCR_EEL2_BIT; + /* * Initialise SCTLR_EL1 to the reset value corresponding to the target * execution state setting all fields rather than relying of the hw. -- cgit v1.2.3 From db3ae8538b8a2cc89e2211201ec96df72e597ae0 Mon Sep 17 00:00:00 2001 From: Artsem Artsemenka Date: Tue, 26 Nov 2019 16:40:31 +0000 Subject: S-EL2 Support: Check for AArch64 Check that entry point information requesting S-EL2 has AArch64 as an execution state during context setup. Signed-off-by: Artsem Artsemenka Change-Id: I447263692fed6e55c1b076913e6eb73b1ea735b7 --- include/arch/aarch64/arch.h | 2 +- lib/el3_runtime/aarch64/context_mgmt.c | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index e48e20185..1fcd0f9ba 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -141,7 +141,7 @@ #define ID_AA64PFR0_SVE_SHIFT U(32) #define ID_AA64PFR0_SVE_MASK ULL(0xf) #define ID_AA64PFR0_SEL2_SHIFT U(36) -#define ID_AA64PFR0_SEL2_MASK U(0xf) +#define ID_AA64PFR0_SEL2_MASK ULL(0xf) #define ID_AA64PFR0_MPAM_SHIFT U(40) #define ID_AA64PFR0_MPAM_MASK ULL(0xf) #define ID_AA64PFR0_DIT_SHIFT U(48) diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 752a2606e..b7908adec 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -182,8 +182,14 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) } /* Enable S-EL2 if the next EL is EL2 and security state is secure */ - if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) + if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { + if (GET_RW(ep->spsr) != MODE_RW_64) { + ERROR("S-EL2 can not be used in AArch32."); + panic(); + } + scr_el3 |= SCR_EEL2_BIT; + } /* * Initialise SCTLR_EL1 to the reset value corresponding to the target -- cgit v1.2.3 From 9e78cb189a1f26be765662a27ed5caf81793cfd1 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Sun, 8 Dec 2019 20:48:46 +0100 Subject: rpi3/4: Add support for offlining CPUs The hooks were populated but the power down left the CPU in limbo-land. What we need to do - until there is a way to actually power off - is to turn off the MMU and enter the spinning loop as if we were cold-booted. This allows the on-call to pick up the CPU again. Signed-off-by: Jan Kiszka Change-Id: Iefc7a58424e3578ad3dd355a7bd6eaba4b412699 --- plat/rpi/common/rpi3_pm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/plat/rpi/common/rpi3_pm.c b/plat/rpi/common/rpi3_pm.c index 8c2d070c4..2a6bf076b 100644 --- a/plat/rpi/common/rpi3_pm.c +++ b/plat/rpi/common/rpi3_pm.c @@ -123,6 +123,15 @@ static void rpi3_pwr_domain_off(const psci_power_state_t *target_state) #endif } +void __dead2 plat_secondary_cold_boot_setup(void); + +static void __dead2 +rpi3_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) +{ + disable_mmu_el3(); + plat_secondary_cold_boot_setup(); +} + /******************************************************************************* * Platform handler called when a power domain is about to be turned on. The * mpidr determines the CPU to be turned on. @@ -224,6 +233,7 @@ static void __dead2 rpi3_system_off(void) static const plat_psci_ops_t plat_rpi3_psci_pm_ops = { .cpu_standby = rpi3_cpu_standby, .pwr_domain_off = rpi3_pwr_domain_off, + .pwr_domain_pwr_down_wfi = rpi3_pwr_domain_pwr_down_wfi, .pwr_domain_on = rpi3_pwr_domain_on, .pwr_domain_on_finish = rpi3_pwr_domain_on_finish, .system_off = rpi3_system_off, -- cgit v1.2.3 From 6c77dfc5e6a306033cba9793fe6280511e512bad Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Mon, 9 Dec 2019 11:29:38 +0000 Subject: Use the proper size for tb_fw_cfg_dtb Currently tb_fw_cfg_dtb size is fixed to max, which is generally a page (but depend on the platform). Instead, read the actual size of the dtb with the libfdt "fdt_totalsize" function. This avoid flushing extra memory after updating the dtb with mbedtls heap information when shared heap is used. Change-Id: Ibec727661116429f486464a0c9f15e9760d7afe2 Signed-off-by: Louis Mayencourt --- plat/arm/common/arm_dyn_cfg.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c index 9a5364952..aafb190d5 100644 --- a/plat/arm/common/arm_dyn_cfg.c +++ b/plat/arm/common/arm_dyn_cfg.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include #include +#include #include @@ -21,8 +22,6 @@ /* Variable to store the address to TB_FW_CONFIG passed from BL1 */ static void *tb_fw_cfg_dtb; -static size_t tb_fw_cfg_dtb_size; - #if TRUSTED_BOARD_BOOT @@ -110,7 +109,7 @@ void arm_bl1_set_mbedtls_heap(void) * without the heap info. */ flush_dcache_range((uintptr_t)tb_fw_cfg_dtb, - tb_fw_cfg_dtb_size); + fdt_totalsize(tb_fw_cfg_dtb)); } } @@ -146,7 +145,6 @@ void arm_load_tb_fw_config(void) /* At this point we know that a DTB is indeed available */ config_base = arm_tb_fw_info.image_info.image_base; tb_fw_cfg_dtb = (void *)config_base; - tb_fw_cfg_dtb_size = (size_t)arm_tb_fw_info.image_info.image_max_size; /* The BL2 ep_info arg0 is modified to point to TB_FW_CONFIG */ desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); -- cgit v1.2.3 From a71c59d5cbd112dbaa1299d4b93dcd99bace75e7 Mon Sep 17 00:00:00 2001 From: Ambroise Vincent Date: Tue, 16 Jul 2019 17:19:38 +0100 Subject: arm: Fix current RECLAIM_INIT_CODE behavior Previously the .init section was created even when the reclaim flag was manually set to 0. Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8 Signed-off-by: Ambroise Vincent Zelalem Aweke --- include/plat/arm/common/arm_reclaim_init.ld.S | 5 ++--- plat/arm/board/fvp/include/plat.ld.S | 5 ++++- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/plat/arm/common/arm_reclaim_init.ld.S b/include/plat/arm/common/arm_reclaim_init.ld.S index 8f22170fe..b5bf47365 100644 --- a/include/plat/arm/common/arm_reclaim_init.ld.S +++ b/include/plat/arm/common/arm_reclaim_init.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,10 +27,9 @@ SECTIONS "BL31 init has exceeded progbits limit.") #endif -#if RECLAIM_INIT_CODE ASSERT(__INIT_CODE_END__ <= __STACKS_END__, "Init code ends past the end of the stacks") -#endif + } #endif /* ARM_RECLAIM_INIT_LD_S */ diff --git a/plat/arm/board/fvp/include/plat.ld.S b/plat/arm/board/fvp/include/plat.ld.S index f024f551a..7c8bf0655 100644 --- a/plat/arm/board/fvp/include/plat.ld.S +++ b/plat/arm/board/fvp/include/plat.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,9 @@ #define PLAT_LD_S #include + +#if RECLAIM_INIT_CODE #include +#endif /* RECLAIM_INIT_CODE */ #endif /* PLAT_LD_S */ -- cgit v1.2.3 From 4719bba93d166368d74c83c4cef71598a4bff888 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 3 Dec 2019 08:50:57 -0800 Subject: Tegra194: psci: rename 'percpu_data' variable The per CPU wake times are saved in an array called 't19x_percpu_data'. But, there is one instance in the code where the name of the variable is misspelt. This patch fixes this typographical error to fix compilation errors. Signed-off-by: Varun Wadekar Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735 --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 948fadec9..1188a3b81 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -66,10 +66,10 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state, << TEGRA194_WAKE_TIME_SHIFT; /* - * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that - * the correct value is read in tegra_soc_pwr_domain_suspend(), which - * is called with caches disabled. It is possible to read a stale value - * from DRAM in that function, because the L2 cache is not flushed + * Clean t19x_percpu_data[cpu] to DRAM. This needs to be done to ensure + * that the correct value is read in tegra_soc_pwr_domain_suspend(), + * which is called with caches disabled. It is possible to read a stale + * value from DRAM in that function, because the L2 cache is not flushed * unless the cluster is entering CC6/CC7. */ clean_dcache_range((uint64_t)&t19x_percpu_data[cpu], @@ -125,7 +125,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? (uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7; ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val, - percpu_data[cpu].wake_time, 0); + t19x_percpu_data[cpu].wake_time, 0); assert(ret == 0); } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { -- cgit v1.2.3 From 56c27438bd2ace11c520559a073e6eac92802a13 Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Fri, 9 Feb 2018 21:01:49 +0800 Subject: Tegra194: 40-bit wide memory address space This patch updates the memory address space, physical and virtual, to be 40-bits wide for all Tegra194 platforms. Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c Signed-off-by: Steven Kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 1a9ba0a84..67f5abbd2 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -9,6 +9,12 @@ #include +/******************************************************************************* + * Chip specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) + /******************************************************************************* * These values are used by the PSCI implementation during the `CPU_SUSPEND` * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' -- cgit v1.2.3 From 8ecc429143868a8e991b860f54749344dc71b52e Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Fri, 15 Dec 2017 15:00:09 -0800 Subject: Tegra194: introduce tegra_mc_def.h This patch introduces memory controller register defines for Tegra194 platforms. Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6 Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/include/t194/tegra_mc_def.h | 650 ++++++++++++++++++++++++++ 1 file changed, 650 insertions(+) create mode 100644 plat/nvidia/tegra/include/t194/tegra_mc_def.h diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h new file mode 100644 index 000000000..e0444c160 --- /dev/null +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -0,0 +1,650 @@ +/* + * Copyright (c) 2019, NVIDIA Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __TEGRA_MC_DEF_H__ +#define __TEGRA_MC_DEF_H__ + +/******************************************************************************* + * Memory Controller Order_id registers + ******************************************************************************/ +#define MC_CLIENT_ORDER_ID_9 U(0x2a24) +#define MC_CLIENT_ORDER_ID_9_RESET_VAL 0x00000000U +#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_MASK (0x3U << 12) +#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_ORDER_ID (3U << 12) + +#define MC_CLIENT_ORDER_ID_27 U(0x2a6c) +#define MC_CLIENT_ORDER_ID_27_RESET_VAL 0x00000000U +#define MC_CLIENT_ORDER_ID_27_PCIE0W_MASK (0x3U << 4) +#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (1U << 4) + +#define MC_CLIENT_ORDER_ID_28 U(0x2a70) +#define MC_CLIENT_ORDER_ID_28_RESET_VAL 0x00000000U +#define MC_CLIENT_ORDER_ID_28_PCIE4W_MASK (0x3U << 4) +#define MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID (3U << 4) +#define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12) +#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (2U << 12) + +#define mc_client_order_id(id, client) \ + (~MC_CLIENT_ORDER_ID_##id##_##client##_MASK | \ + MC_CLIENT_ORDER_ID_##id##_##client##_ORDER_ID) + +/******************************************************************************* + * Memory Controller's VC ID configuration registers + ******************************************************************************/ +#define VC_NISO 0U +#define VC_SISO 1U +#define VC_ISO 2U + +#define MC_HUB_PC_VC_ID_0 U(0x2a78) +#define MC_HUB_PC_VC_ID_0_RESET_VAL 0x00020100U +#define MC_HUB_PC_VC_ID_0_APB_VC_ID_MASK (0x3U << 8) +#define MC_HUB_PC_VC_ID_0_APB_VC_ID (VC_NISO << 8) + +#define MC_HUB_PC_VC_ID_2 U(0x2a80) +#define MC_HUB_PC_VC_ID_2_RESET_VAL 0x10001000U +#define MC_HUB_PC_VC_ID_2_SD_VC_ID_MASK (0x3U << 28) +#define MC_HUB_PC_VC_ID_2_SD_VC_ID (VC_NISO << 28) + +#define MC_HUB_PC_VC_ID_4 U(0x2a88) +#define MC_HUB_PC_VC_ID_4_RESET_VAL 0x10020011U +#define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28) +#define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28) + +#define mc_hub_vc_id(id, client) \ + (~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK | \ + MC_HUB_PC_VC_ID_##id##_##client##_VC_ID) + +/******************************************************************************* + * Memory Controller's PCFIFO client configuration registers + ******************************************************************************/ +#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0U + +#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4U +#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20200000U +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0U << 17) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1U << 17) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0U << 21) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1U << 21) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0U << 29) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_ORDERED (1U << 29) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1U << 29) + +#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8U +#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x00002800U +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0U << 11) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1U << 11) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0U << 13) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_ORDERED (1U << 13) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1U << 13) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_UNORDERED (0U << 21) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_MASK (1U << 21) + +#define MC_PCFIFO_CLIENT_CONFIG3 0xddcU +#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0x08000080U +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_UNORDERED (0U << 4) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_MASK (1U << 4) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_UNORDERED (0U << 6) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_MASK (1U << 6) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0U << 7) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1U << 7) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_UNORDERED (0U << 13) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_MASK (1U << 13) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_UNORDERED (0U << 27) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_MASK (1U << 27) + +#define MC_PCFIFO_CLIENT_CONFIG4 0xde0U +#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0x5552a022U +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0U << 1) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1U << 1) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0U << 5) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1U << 5) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_UNORDERED (0U << 7) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK (1U << 7) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1U << 15) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_UNORDERED (0U << 20) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_MASK (1U << 20) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0U << 22) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1U << 22) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_UNORDERED (0U << 24) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_MASK (1U << 24) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0U << 26) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1U << 26) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_UNORDERED (0U << 28) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_MASK (1U << 28) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0U << 30) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1U << 30) + +#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4U +#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0x20000001U +#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0U << 0) +#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1U << 0) +#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_UNORDERED (0U << 30) +#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_MASK (1U << 30) + +#define MC_PCFIFO_CLIENT_CONFIG6 0xb90U +#define MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL 0xaa280000U +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_UNORDERED (0U << 19) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_MASK (1U << 19) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_UNORDERED (0U << 21) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_MASK (1U << 21) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_UNORDERED (0U << 25) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_MASK (1U << 25) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_ORDERED (1U << 27) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_MASK (1U << 27) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_ORDERED (1U << 29) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_MASK (1U << 29) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_ORDERED (1U << 31) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_MASK (1U << 31) + +#define MC_PCFIFO_CLIENT_CONFIG7 0xaccU +#define MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL 0x0000000aU +#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_UNORDERED (0U << 1) +#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_MASK (1U << 1) +#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_UNORDERED (0U << 3) +#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_MASK (1U << 3) + +/******************************************************************************* + * StreamID to indicate no SMMU translations (requests to be steered on the + * SMMU bypass path) + ******************************************************************************/ +#define MC_STREAM_ID_MAX 0x7FU + +/******************************************************************************* + * Stream ID Override Config registers + ******************************************************************************/ +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U +#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xe0U +#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3f8U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U +#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5f0U +#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U +#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4f8U +#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U +#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2a0U +#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5f8U +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U +#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1c8U +#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U +#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U +#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U +#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U +#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6d8U +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U +#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U +#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U +#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1e8U +#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U +#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6f0U +#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U +#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4e8U +#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xb0U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U +#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U +#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U +#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6e8U +#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U +#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U +#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U +#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4d0U +#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U +#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U +#define MC_STREAMID_OVERRIDE_CFG_HDAR 0xa8U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U +#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U +#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6a8U +#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2a8U +#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U +#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3f0U +#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4c8U +#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4d8U +#define MC_STREAMID_OVERRIDE_CFG_MIU5W 0x7e8U +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6b0U +#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U +#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U +#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6c8U +#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U +#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U +#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U +#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U +#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U +#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U +#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6a0U +#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U +#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3c8U +#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U +#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U +#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U +#define MC_STREAMID_OVERRIDE_CFG_APER 0x3d0U +#define MC_STREAMID_OVERRIDE_CFG_MIU7R 0x8U +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7c8U +#define MC_STREAMID_OVERRIDE_CFG_MIU7W 0x10U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U +#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4c0U +#define MC_STREAMID_OVERRIDE_CFG_MIU4W 0x598U +#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1a8U +#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4a0U +#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U +#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U +#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U +#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U +#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U +#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4b0U +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7d8U +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U +#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U +#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U +#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U +#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6b8U +#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6c0U +#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6f8U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U +#define MC_STREAMID_OVERRIDE_CFG_MIU6W 0x7f8U +#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6d0U +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7d0U +#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U +#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U +#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U +#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U +#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U +#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4b8U +#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4a8U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U +#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5e8U +#define MC_STREAMID_OVERRIDE_CFG_MIU6R 0x7f0U +#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U +#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3c0U +#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U +#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U +#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U +#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4f0U +#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3d8U +#define MC_STREAMID_OVERRIDE_CFG_MIU5R 0x7e0U +#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U +#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U +#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0U +#define MC_STREAMID_OVERRIDE_CFG_MIU4R 0x590U +#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U +#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5e0U +#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6e0U +#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U +#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U +#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4e0U +#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U +#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U +#define MC_STREAMID_OVERRIDE_CFG_SATAR 0xf8U +#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U +#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U +#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U +#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U + +/******************************************************************************* + * Macro to calculate Security cfg register addr from StreamID Override register + ******************************************************************************/ +#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t)) + +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4) + +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8) + +#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12) +#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12) + +/******************************************************************************* + * Memory Controller transaction override config registers + ******************************************************************************/ +#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U +#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624U +#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16dcU +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644U +#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U +#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U +#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U +#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162cU +#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654U +#define MC_TXN_OVERRIDE_CONFIG_MIU6R 0x17f4U +#define MC_TXN_OVERRIDE_CONFIG_MIU5R 0x17e4U +#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784U +#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16c4U +#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U +#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178cU +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774U +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16bcU +#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U +#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U +#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U +#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714U +#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U +#define MC_TXN_OVERRIDE_CONFIG_MIU6W 0x17fcU +#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U +#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179cU +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764U +#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U +#define MC_TXN_OVERRIDE_CONFIG_MIU7R 0x1008U +#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U +#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U +#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15f4U +#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17dcU +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176cU +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166cU +#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U +#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U +#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U +#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16ecU +#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16d4U +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674U +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164cU +#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U +#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548U +#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16ccU +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17ccU +#define MC_TXN_OVERRIDE_CONFIG_MIU7W 0x1010U +#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U +#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580U +#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158cU +#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U +#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U +#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U +#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U +#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U +#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U +#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634U +#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U +#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U +#define MC_TXN_OVERRIDE_CONFIG_ISPFALR 0x1228U +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175cU +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16b4U +#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664U +#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174cU +#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U +#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U +#define MC_TXN_OVERRIDE_CONFIG_AXIAPR 0x1410U +#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16e4U +#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724U +#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U +#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578U +#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694U +#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170cU +#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U +#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U +#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U +#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U +#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17d4U +#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614U +#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U +#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U +#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161cU +#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U +#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169cU +#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U +#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604U +#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15e4U +#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16f4U +#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540U +#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171cU +#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U +#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538U +#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160cU +#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15ecU +#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15fcU +#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16fcU +#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530U +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165cU +#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U +#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U +#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U +#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U +#define MC_TXN_OVERRIDE_CONFIG_AXIAPW 0x1418U +#define MC_TXN_OVERRIDE_CONFIG_MIU4R 0x1594U +#define MC_TXN_OVERRIDE_CONFIG_MIU4W 0x159cU +#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U +#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U +#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U +#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U +#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754U +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684U +#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168cU +#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16a4U +#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794U +#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U +#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16acU +#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U +#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U +#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U +#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U +#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U +#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177cU +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163cU +#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167cU +#define MC_TXN_OVERRIDE_CONFIG_MIU5W 0x17ecU +#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U +#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570U +#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U +#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U +#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704U +#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U + +#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4) +#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12) + +/******************************************************************************* + * Non-SO_DEV transactions override values for CGID_TAG bitfield for the + * MC_TXN_OVERRIDE_CONFIG_{module} registers + ******************************************************************************/ +#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U +#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U +#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U +#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U +#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3ULL + +/******************************************************************************* + * Memory Controller Reset Control registers + ******************************************************************************/ +#define MC_CLIENT_HOTRESET_CTRL0 0x200U +#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U +#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0) +#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6) +#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7) +#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8) +#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9) +#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11) +#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15) +#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17) +#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18) +#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19) +#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20) +#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22) +#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29) +#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30) +#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31) +#define MC_CLIENT_HOTRESET_STATUS0 0x204U +#define MC_CLIENT_HOTRESET_CTRL1 0x970U +#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U +#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0) +#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2) +#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5) +#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6) +#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7) +#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8) +#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12) +#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13) +#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 17) +#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 18) +#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 19) +#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 20) +#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 21) +#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 22) +#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 23) +#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1U << 26) +#define MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB (1U << 31) +#define MC_CLIENT_HOTRESET_STATUS1 0x974U +#define MC_CLIENT_HOTRESET_CTRL2 0x97cU +#define MC_CLIENT_HOTRESET_CTRL2_RESET_VAL 0U +#define MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB (1U << 0) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB (1U << 2) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB (1U << 4) +#define MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB (1U << 9) +#define MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB (1U << 10) +#define MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB (1U << 11) +#define MC_CLIENT_HOTRESET_CTRL2_APEDMA_FLUSH_ENB (1U << 14) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB (1U << 16) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB (1U << 17) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB (1U << 22) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB (1U << 23) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB (1U << 25) +#define MC_CLIENT_HOTRESET_STATUS2 0x1898U + +/******************************************************************************* + * Tegra TSA Controller constants + ******************************************************************************/ +#define TEGRA_TSA_BASE U(0x02000000) + +#define TSA_CONFIG_STATIC0_CSR_RESET_R 0x20000000U +#define TSA_CONFIG_STATIC0_CSW_RESET_W 0x20001000U +#define TSA_CONFIG_STATIC0_CSW_RESET_SO_DEV 0x20001000U + +#define TSA_CONFIG_STATIC0_CSW_PCIE1W 0x1004U +#define TSA_CONFIG_STATIC0_CSW_PCIE2AW 0x1008U +#define TSA_CONFIG_STATIC0_CSW_PCIE3W 0x100cU +#define TSA_CONFIG_STATIC0_CSW_PCIE4W 0x1028U +#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x2004U +#define TSA_CONFIG_STATIC0_CSR_SATAR 0x2010U +#define TSA_CONFIG_STATIC0_CSW_SATAW 0x2014U +#define TSA_CONFIG_STATIC0_CSW_PCIE0W 0x2020U +#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x202cU +#define TSA_CONFIG_STATIC0_CSW_NVENC1SWR 0x3004U +#define TSA_CONFIG_STATIC0_CSW_NVENCSWR 0x3010U +#define TSA_CONFIG_STATIC0_CSW_NVDEC1SWR 0x4004U +#define TSA_CONFIG_STATIC0_CSR_ISPFALR 0x4010U +#define TSA_CONFIG_STATIC0_CSW_ISPWA 0x4014U +#define TSA_CONFIG_STATIC0_CSW_ISPWB 0x4018U +#define TSA_CONFIG_STATIC0_CSW_ISPFALW 0x401cU +#define TSA_CONFIG_STATIC0_CSW_NVDECSWR 0x5004U +#define TSA_CONFIG_STATIC0_CSR_EQOSR 0x5010U +#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x5014U +#define TSA_CONFIG_STATIC0_CSR_SDMMCRAB 0x5020U +#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5024U +#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6004U +#define TSA_CONFIG_STATIC0_CSR_SDMMCR 0x6010U +#define TSA_CONFIG_STATIC0_CSR_SDMMCRA 0x6014U +#define TSA_CONFIG_STATIC0_CSW_SDMMCW 0x6018U +#define TSA_CONFIG_STATIC0_CSW_SDMMCWA 0x601cU +#define TSA_CONFIG_STATIC0_CSR_RCER 0x6030U +#define TSA_CONFIG_STATIC0_CSR_RCEDMAR 0x6034U +#define TSA_CONFIG_STATIC0_CSW_RCEW 0x6038U +#define TSA_CONFIG_STATIC0_CSW_RCEDMAW 0x603cU +#define TSA_CONFIG_STATIC0_CSR_SCER 0x6050U +#define TSA_CONFIG_STATIC0_CSR_SCEDMAR 0x6054U +#define TSA_CONFIG_STATIC0_CSW_SCEW 0x6058U +#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x605cU +#define TSA_CONFIG_STATIC0_CSR_AXIAPR 0x7004U +#define TSA_CONFIG_STATIC0_CSR_ETRR 0x7008U +#define TSA_CONFIG_STATIC0_CSR_HOST1XDMAR 0x700cU +#define TSA_CONFIG_STATIC0_CSW_AXIAPW 0x7010U +#define TSA_CONFIG_STATIC0_CSW_ETRW 0x7014U +#define TSA_CONFIG_STATIC0_CSR_NVJPGSRD 0x8004U +#define TSA_CONFIG_STATIC0_CSW_NVJPGSWR 0x8008U +#define TSA_CONFIG_STATIC0_CSR_AXISR 0x8014U +#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8018U +#define TSA_CONFIG_STATIC0_CSR_BPMPR 0x9004U +#define TSA_CONFIG_STATIC0_CSR_BPMPDMAR 0x9008U +#define TSA_CONFIG_STATIC0_CSW_BPMPW 0x900cU +#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9010U +#define TSA_CONFIG_STATIC0_CSR_SESRD 0x9024U +#define TSA_CONFIG_STATIC0_CSR_TSECSRD 0x9028U +#define TSA_CONFIG_STATIC0_CSR_TSECSRDB 0x902cU +#define TSA_CONFIG_STATIC0_CSW_SESWR 0x9030U +#define TSA_CONFIG_STATIC0_CSW_TSECSWR 0x9034U +#define TSA_CONFIG_STATIC0_CSW_TSECSWRB 0x9038U +#define TSA_CONFIG_STATIC0_CSW_PCIE5W 0xb004U +#define TSA_CONFIG_STATIC0_CSW_VICSWR 0xc004U +#define TSA_CONFIG_STATIC0_CSR_APER 0xd004U +#define TSA_CONFIG_STATIC0_CSR_APEDMAR 0xd008U +#define TSA_CONFIG_STATIC0_CSW_APEW 0xd00cU +#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xd010U +#define TSA_CONFIG_STATIC0_CSR_HDAR 0xf004U +#define TSA_CONFIG_STATIC0_CSW_HDAW 0xf008U +#define TSA_CONFIG_STATIC0_CSR_NVDISPLAYR 0xf014U +#define TSA_CONFIG_STATIC0_CSR_VIFALR 0x10004U +#define TSA_CONFIG_STATIC0_CSW_VIW 0x10008U +#define TSA_CONFIG_STATIC0_CSW_VIFALW 0x1000cU +#define TSA_CONFIG_STATIC0_CSR_AONR 0x12004U +#define TSA_CONFIG_STATIC0_CSR_AONDMAR 0x12008U +#define TSA_CONFIG_STATIC0_CSW_AONW 0x1200cU +#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0x12010U +#define TSA_CONFIG_STATIC0_CSR_PCIE1R 0x14004U +#define TSA_CONFIG_STATIC0_CSR_PCIE2AR 0x14008U +#define TSA_CONFIG_STATIC0_CSR_PCIE3R 0x1400cU +#define TSA_CONFIG_STATIC0_CSR_PCIE4R 0x14028U +#define TSA_CONFIG_STATIC0_CSR_XUSB_DEVR 0x15004U +#define TSA_CONFIG_STATIC0_CSR_XUSB_HOSTR 0x15010U +#define TSA_CONFIG_STATIC0_CSR_UFSHCR 0x16004U +#define TSA_CONFIG_STATIC0_CSW_DLA1WRA 0x18004U +#define TSA_CONFIG_STATIC0_CSR_DLA1FALRDB 0x18010U +#define TSA_CONFIG_STATIC0_CSW_DLA1FALWRB 0x18014U +#define TSA_CONFIG_STATIC0_CSW_DLA0WRA 0x19004U +#define TSA_CONFIG_STATIC0_CSR_DLA0FALRDB 0x19010U +#define TSA_CONFIG_STATIC0_CSW_DLA0FALWRB 0x19014U +#define TSA_CONFIG_STATIC0_CSR_PVA1RDC 0x1a004U +#define TSA_CONFIG_STATIC0_CSW_PVA1WRC 0x1a008U +#define TSA_CONFIG_STATIC0_CSW_PVA1WRA 0x1a014U +#define TSA_CONFIG_STATIC0_CSW_PVA1WRB 0x1a020U +#define TSA_CONFIG_STATIC0_CSW_PVA0WRB 0x1b004U +#define TSA_CONFIG_STATIC0_CSR_PVA0RDC 0x1b010U +#define TSA_CONFIG_STATIC0_CSW_PVA0WRC 0x1b014U +#define TSA_CONFIG_STATIC0_CSW_PVA0WRA 0x1b020U +#define TSA_CONFIG_STATIC0_CSR_NVENC1SRD 0x1d004U +#define TSA_CONFIG_STATIC0_CSR_NVENCSRD 0x1d010U +#define TSA_CONFIG_STATIC0_CSR_NVDEC1SRD 0x1e004U +#define TSA_CONFIG_STATIC0_CSR_ISPRA 0x1e010U +#define TSA_CONFIG_STATIC0_CSR_NVDECSRD 0x1f004U +#define TSA_CONFIG_STATIC0_CSR_PCIE0R 0x21004U +#define TSA_CONFIG_STATIC0_CSR_PCIE5R 0x23004U +#define TSA_CONFIG_STATIC0_CSR_VICSRD 0x24004U +#define TSA_CONFIG_STATIC0_CSR_DLA1RDA 0x26004U +#define TSA_CONFIG_STATIC0_CSR_DLA0RDA 0x27004U +#define TSA_CONFIG_STATIC0_CSR_PVA1RDA 0x28004U +#define TSA_CONFIG_STATIC0_CSR_PVA1RDB 0x28010U +#define TSA_CONFIG_STATIC0_CSR_PVA0RDB 0x29004U +#define TSA_CONFIG_STATIC0_CSR_PVA0RDA 0x29010U + +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) + +#endif /* __TEGRA_MC_DEF_H__ */ -- cgit v1.2.3 From fba54d5568fcfad5334319617c959416fe865e0c Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Thu, 26 Oct 2017 17:06:02 +0530 Subject: Tegra194: smmu: add support for backup multiple smmu regs Tegra194 supports multiple SMMU blocks. This patch adds support to save register values for SMMU0 and SMMU2, before entering the System Suspend state. Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/soc/t194/plat_smmu.c | 139 +-------------------------- plat/nvidia/tegra/soc/t194/plat_trampoline.S | 2 +- 2 files changed, 3 insertions(+), 138 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index 1696d5910..640ef4deb 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -270,143 +270,8 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { mc_make_sid_override_cfg(MIU2W), mc_make_sid_override_cfg(MIU3R), mc_make_sid_override_cfg(MIU3W), - smmu_make_gnsr0_nsec_cfg(CR0), - smmu_make_gnsr0_sec_cfg(IDR0), - smmu_make_gnsr0_sec_cfg(IDR1), - smmu_make_gnsr0_sec_cfg(IDR2), - smmu_make_gnsr0_nsec_cfg(GFSR), - smmu_make_gnsr0_nsec_cfg(GFSYNR0), - smmu_make_gnsr0_nsec_cfg(GFSYNR1), - smmu_make_gnsr0_nsec_cfg(TLBGSTATUS), - smmu_make_gnsr0_nsec_cfg(PIDR2), - smmu_make_smrg_group(0), - smmu_make_smrg_group(1), - smmu_make_smrg_group(2), - smmu_make_smrg_group(3), - smmu_make_smrg_group(4), - smmu_make_smrg_group(5), - smmu_make_smrg_group(6), - smmu_make_smrg_group(7), - smmu_make_smrg_group(8), - smmu_make_smrg_group(9), - smmu_make_smrg_group(10), - smmu_make_smrg_group(11), - smmu_make_smrg_group(12), - smmu_make_smrg_group(13), - smmu_make_smrg_group(14), - smmu_make_smrg_group(15), - smmu_make_smrg_group(16), - smmu_make_smrg_group(17), - smmu_make_smrg_group(18), - smmu_make_smrg_group(19), - smmu_make_smrg_group(20), - smmu_make_smrg_group(21), - smmu_make_smrg_group(22), - smmu_make_smrg_group(23), - smmu_make_smrg_group(24), - smmu_make_smrg_group(25), - smmu_make_smrg_group(26), - smmu_make_smrg_group(27), - smmu_make_smrg_group(28), - smmu_make_smrg_group(29), - smmu_make_smrg_group(30), - smmu_make_smrg_group(31), - smmu_make_smrg_group(32), - smmu_make_smrg_group(33), - smmu_make_smrg_group(34), - smmu_make_smrg_group(35), - smmu_make_smrg_group(36), - smmu_make_smrg_group(37), - smmu_make_smrg_group(38), - smmu_make_smrg_group(39), - smmu_make_smrg_group(40), - smmu_make_smrg_group(41), - smmu_make_smrg_group(42), - smmu_make_smrg_group(43), - smmu_make_smrg_group(44), - smmu_make_smrg_group(45), - smmu_make_smrg_group(46), - smmu_make_smrg_group(47), - smmu_make_smrg_group(48), - smmu_make_smrg_group(49), - smmu_make_smrg_group(50), - smmu_make_smrg_group(51), - smmu_make_smrg_group(52), - smmu_make_smrg_group(53), - smmu_make_smrg_group(54), - smmu_make_smrg_group(55), - smmu_make_smrg_group(56), - smmu_make_smrg_group(57), - smmu_make_smrg_group(58), - smmu_make_smrg_group(59), - smmu_make_smrg_group(60), - smmu_make_smrg_group(61), - smmu_make_smrg_group(62), - smmu_make_smrg_group(63), - smmu_make_cb_group(0), - smmu_make_cb_group(1), - smmu_make_cb_group(2), - smmu_make_cb_group(3), - smmu_make_cb_group(4), - smmu_make_cb_group(5), - smmu_make_cb_group(6), - smmu_make_cb_group(7), - smmu_make_cb_group(8), - smmu_make_cb_group(9), - smmu_make_cb_group(10), - smmu_make_cb_group(11), - smmu_make_cb_group(12), - smmu_make_cb_group(13), - smmu_make_cb_group(14), - smmu_make_cb_group(15), - smmu_make_cb_group(16), - smmu_make_cb_group(17), - smmu_make_cb_group(18), - smmu_make_cb_group(19), - smmu_make_cb_group(20), - smmu_make_cb_group(21), - smmu_make_cb_group(22), - smmu_make_cb_group(23), - smmu_make_cb_group(24), - smmu_make_cb_group(25), - smmu_make_cb_group(26), - smmu_make_cb_group(27), - smmu_make_cb_group(28), - smmu_make_cb_group(29), - smmu_make_cb_group(30), - smmu_make_cb_group(31), - smmu_make_cb_group(32), - smmu_make_cb_group(33), - smmu_make_cb_group(34), - smmu_make_cb_group(35), - smmu_make_cb_group(36), - smmu_make_cb_group(37), - smmu_make_cb_group(38), - smmu_make_cb_group(39), - smmu_make_cb_group(40), - smmu_make_cb_group(41), - smmu_make_cb_group(42), - smmu_make_cb_group(43), - smmu_make_cb_group(44), - smmu_make_cb_group(45), - smmu_make_cb_group(46), - smmu_make_cb_group(47), - smmu_make_cb_group(48), - smmu_make_cb_group(49), - smmu_make_cb_group(50), - smmu_make_cb_group(51), - smmu_make_cb_group(52), - smmu_make_cb_group(53), - smmu_make_cb_group(54), - smmu_make_cb_group(55), - smmu_make_cb_group(56), - smmu_make_cb_group(57), - smmu_make_cb_group(58), - smmu_make_cb_group(59), - smmu_make_cb_group(60), - smmu_make_cb_group(61), - smmu_make_cb_group(62), - smmu_make_cb_group(63), + smmu_make_cfg(TEGRA_SMMU0_BASE), + smmu_make_cfg(TEGRA_SMMU2_BASE), smmu_bypass_cfg, /* TBU settings */ _END_OF_TABLE_, }; diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S index 33c7e6f78..696a5774e 100644 --- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S @@ -12,7 +12,7 @@ #define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7 #define TEGRA194_STATE_SYSTEM_RESUME 0x600D -#define TEGRA194_SMMU_CTX_SIZE 0x490 +#define TEGRA194_SMMU_CTX_SIZE 0x80B .align 4 .globl tegra194_cpu_reset_handler -- cgit v1.2.3 From fbd9eb58e60f73a45a59b787eb405f19a3561530 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 3 Dec 2019 14:14:12 -0800 Subject: docs: tegra: add support for Tegra194 class of SoCs This patch adds the Tegra194 SoC information to the nvidia-tegra.rst file. Signed-off-by: Varun Wadekar Change-Id: Id649a5ff1b3f70eeee34b508edb7965e7b7a2454 --- docs/plat/nvidia-tegra.rst | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/docs/plat/nvidia-tegra.rst b/docs/plat/nvidia-tegra.rst index bc9e35b4f..02ff38bef 100644 --- a/docs/plat/nvidia-tegra.rst +++ b/docs/plat/nvidia-tegra.rst @@ -1,6 +1,17 @@ NVIDIA Tegra ============ +- .. rubric:: T194 + :name: t194 + +T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor +configuration. The Carmel cores support the ARM Architecture version 8.2, +executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel +processors are organized as four dual-core clusters, where each cluster has +a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects +these processor complexes and allows heterogeneous multi-processing with all +eight cores if required. + - .. rubric:: T186 :name: t186 @@ -78,9 +89,10 @@ their dispatchers in the image without changing any makefiles. These are the supported Trusted OS' by Tegra platforms. -Tegra132: TLK -Tegra210: TLK and Trusty -Tegra186: Trusty +- Tegra132: TLK +- Tegra210: TLK and Trusty +- Tegra186: Trusty +- Tegra194: Trusty Scatter files ------------- @@ -98,7 +110,7 @@ Preparing the BL31 image to run on Tegra SoCs .. code:: shell CROSS_COMPILE=/bin/aarch64-none-elf- make PLAT=tegra \ - TARGET_SOC= SPD= + TARGET_SOC= SPD= bl31 Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=`` -- cgit v1.2.3 From b4899041e5f0b8e8b388c6511b5233516b8785ec Mon Sep 17 00:00:00 2001 From: Piotr Szczepanik Date: Tue, 10 Dec 2019 20:55:00 +0000 Subject: plat/rockchip: enable power domains of rk3399 before reset This patch fixes hangs that happen after soft resetting of rk3399. Signed-off-by: Piotr Szczepanik Change-Id: If41b12ba1dfcb2ba937361b58eafd50bf5c483d4 --- plat/rockchip/rk3399/drivers/pmu/pmu.c | 19 +++++++++++++++++++ plat/rockchip/rk3399/drivers/pmu/pmu.h | 1 + plat/rockchip/rk3399/drivers/soc/soc.c | 2 ++ 3 files changed, 22 insertions(+) diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index 30941fd07..faee6787d 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -400,6 +400,25 @@ static void pmu_power_domains_resume(void) clk_gate_con_restore(); } +void pmu_power_domains_on(void) +{ + clk_gate_con_disable(); + pmu_set_power_domain(PD_VDU, pmu_pd_on); + pmu_set_power_domain(PD_VCODEC, pmu_pd_on); + pmu_set_power_domain(PD_RGA, pmu_pd_on); + pmu_set_power_domain(PD_IEP, pmu_pd_on); + pmu_set_power_domain(PD_EDP, pmu_pd_on); + pmu_set_power_domain(PD_GMAC, pmu_pd_on); + pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on); + pmu_set_power_domain(PD_HDCP, pmu_pd_on); + pmu_set_power_domain(PD_ISP1, pmu_pd_on); + pmu_set_power_domain(PD_ISP0, pmu_pd_on); + pmu_set_power_domain(PD_VO, pmu_pd_on); + pmu_set_power_domain(PD_TCPD1, pmu_pd_on); + pmu_set_power_domain(PD_TCPD0, pmu_pd_on); + pmu_set_power_domain(PD_GPU, pmu_pd_on); +} + void rk3399_flush_l2_b(void) { uint32_t wait_cnt = 0; diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h index 74db82ff2..bb7de5091 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.h +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h @@ -136,5 +136,6 @@ struct pmu_slpdata_s { extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT]; extern void sram_func_set_ddrctl_pll(uint32_t pll_src); +void pmu_power_domains_on(void); #endif /* PMU_H */ diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c index c877dbde8..98b5ad646 100644 --- a/plat/rockchip/rk3399/drivers/soc/soc.c +++ b/plat/rockchip/rk3399/drivers/soc/soc.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -327,6 +328,7 @@ void soc_global_soft_reset_init(void) void __dead2 soc_global_soft_reset(void) { + pmu_power_domains_on(); set_pll_slow_mode(VPLL_ID); set_pll_slow_mode(NPLL_ID); set_pll_slow_mode(GPLL_ID); -- cgit v1.2.3 From d01969118f1120d469d8f870cd195cb97e55fa90 Mon Sep 17 00:00:00 2001 From: Ambroise Vincent Date: Thu, 18 Jul 2019 10:56:14 +0100 Subject: arm: gicv3: Fix compiler dependent behavior C99 standard: "What constitutes an access to an object that has volatile-qualified type is implementation-defined". GCC is not considering the cast to void of volatile structures as an access and so is not actually issuing reads. Clang does read those structures by copying them on the stack, which in this case creates an overflow because of their large size. This patch removes the cast to void and instead uses the USED attribute to tell the compiler to retain the static variables. Change-Id: I952b5056e3f6e91841e7ef9558434352710ab80d Signed-off-by: Ambroise Vincent Zelalem Aweke --- include/lib/utils.h | 14 ++++++-------- plat/arm/common/arm_gicv3.c | 9 ++++----- 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/include/lib/utils.h b/include/lib/utils.h index cdb125cfa..17ee93694 100644 --- a/include/lib/utils.h +++ b/include/lib/utils.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -79,13 +79,11 @@ void zeromem(void *mem, u_register_t length); * which is constant and does not depend on the execute address of the binary. */ #define DEFINE_LOAD_SYM_ADDR(_name) \ -static inline u_register_t load_addr_## _name(void) \ -{ \ - u_register_t v; \ - /* Create a void reference to silence compiler */ \ - (void) _name; \ - __asm__ volatile ("ldr %0, =" #_name : "=r" (v)); \ - return v; \ +static inline u_register_t load_addr_## _name(void) \ +{ \ + u_register_t v; \ + __asm__ volatile ("ldr %0, =" #_name : "=r" (v) : "X" (#_name));\ + return v; \ } /* Helper to invoke the function defined by DEFINE_LOAD_SYM_ADDR() */ diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index cfc535939..4a3a22ec0 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -44,12 +44,11 @@ static const interrupt_prop_t arm_interrupt_props[] = { /* * We save and restore the GICv3 context on system suspend. Allocate the - * data in the designated EL3 Secure carve-out memory. The `volatile` - * is used to prevent the compiler from removing the gicv3 contexts even - * though the DEFINE_LOAD_SYM_ADDR creates a dummy reference to it. + * data in the designated EL3 Secure carve-out memory. The `used` attribute + * is used to prevent the compiler from removing the gicv3 contexts. */ -static volatile gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram"); -static volatile gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram"); +static gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram") __used; +static gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram") __used; /* Define accessor function to get reference to the GICv3 context */ DEFINE_LOAD_SYM_ADDR(rdist_ctx) -- cgit v1.2.3 From ebff1072681c5ed09bb70d9c4f617476822db757 Mon Sep 17 00:00:00 2001 From: Ambroise Vincent Date: Wed, 19 Jun 2019 17:14:09 +0100 Subject: libc: add memrchr This function scans a string backwards from the end for the first instance of a character. Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763 Signed-off-by: Ambroise Vincent --- include/lib/libc/string.h | 3 ++- lib/libc/libc.mk | 1 + lib/libc/memrchr.c | 24 ++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 lib/libc/memrchr.c diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h index ee6eeacef..de20f6189 100644 --- a/include/lib/libc/string.h +++ b/include/lib/libc/string.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ @@ -23,6 +23,7 @@ int memcmp(const void *s1, const void *s2, size_t len); int strcmp(const char *s1, const char *s2); int strncmp(const char *s1, const char *s2, size_t n); void *memchr(const void *src, int c, size_t len); +void *memrchr(const void *src, int c, size_t len); char *strchr(const char *s, int c); void *memset(void *dst, int val, size_t count); size_t strlen(const char *s); diff --git a/lib/libc/libc.mk b/lib/libc/libc.mk index e1b5560f8..93d30d035 100644 --- a/lib/libc/libc.mk +++ b/lib/libc/libc.mk @@ -12,6 +12,7 @@ LIBC_SRCS := $(addprefix lib/libc/, \ memcmp.c \ memcpy.c \ memmove.c \ + memrchr.c \ memset.c \ printf.c \ putchar.c \ diff --git a/lib/libc/memrchr.c b/lib/libc/memrchr.c new file mode 100644 index 000000000..01caef3ae --- /dev/null +++ b/lib/libc/memrchr.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#undef memrchr + +void *memrchr(const void *src, int c, size_t len) +{ + const unsigned char *s = src + (len - 1); + + while (len--) { + if (*s == (unsigned char)c) { + return (void*) s; + } + + s--; + } + + return NULL; +} -- cgit v1.2.3 From b8622922c8ab7a450a3184b7a5f4929bd95ffaad Mon Sep 17 00:00:00 2001 From: Gilad Ben-Yossef Date: Sun, 15 Sep 2019 13:29:29 +0300 Subject: cryptocell: add cryptocell 712 RSA 3K support Add the support needed to enable using CryptoCell integration with with RSA 3K support. Signed-off-by: Gilad Ben-Yossef Change-Id: I95527cb0c41ae012109e8968dd20a4ae9fe67f17 --- docs/getting_started/build-options.rst | 15 +++++++++++++++ drivers/auth/cryptocell/712/cryptocell_crypto.c | 2 +- drivers/auth/cryptocell/cryptocell_crypto.mk | 4 +++- include/drivers/arm/cryptocell/712/rsa.h | 16 +++++++++------- include/drivers/arm/cryptocell/712/secureboot_gen_defs.h | 16 +++++++++++++--- 5 files changed, 41 insertions(+), 12 deletions(-) diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index fded1e0c9..583e8caf3 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -350,6 +350,21 @@ Common build options compliant and is retained only for compatibility. The default value of this flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. +- ``KEY_SIZE``: This build flag enables the user to select the key size for + the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` + depend on the chosen algorithm and the cryptographic module. + + +-----------+------------------------------------+ + | KEY_ALG | Possible key sizes | + +===========+====================================+ + | rsa | 1024 , 2048 (default), 3072, 4096* | + +-----------+------------------------------------+ + | ecdsa | unavailable | + +-----------+------------------------------------+ + + * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. + Only 3072 bits size is available with CryptoCell 712 SBROM release 2. + - ``HASH_ALG``: This build flag enables the user to select the secure hash algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. The default value of this flag is ``sha256``. diff --git a/drivers/auth/cryptocell/712/cryptocell_crypto.c b/drivers/auth/cryptocell/712/cryptocell_crypto.c index 395c55085..25eb6bcb6 100644 --- a/drivers/auth/cryptocell/712/cryptocell_crypto.c +++ b/drivers/auth/cryptocell/712/cryptocell_crypto.c @@ -225,7 +225,7 @@ static int verify_signature(void *data_ptr, unsigned int data_len, /* Verify the signature */ error = CCSbVerifySignature((uintptr_t)PLAT_CRYPTOCELL_BASE, (uint32_t *)data_ptr, &pk, &signature, - data_len, RSA_PSS_2048); + data_len, RSA_PSS); if (error != CC_OK) return CRYPTO_ERR_SIGNATURE; diff --git a/drivers/auth/cryptocell/cryptocell_crypto.mk b/drivers/auth/cryptocell/cryptocell_crypto.mk index d42a2e7e1..2fc4ddb11 100644 --- a/drivers/auth/cryptocell/cryptocell_crypto.mk +++ b/drivers/auth/cryptocell/cryptocell_crypto.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -12,6 +12,8 @@ TF_MBEDTLS_KEY_ALG_ID := TF_MBEDTLS_RSA # Needs to be set to drive mbed TLS configuration correctly $(eval $(call add_define,TF_MBEDTLS_KEY_ALG_ID)) +$(eval $(call add_define,KEY_SIZE)) + # CCSBROM_LIB_PATH must be set to the Cryptocell SBROM library path ifeq (${CCSBROM_LIB_PATH},) $(error Error: CCSBROM_LIB_PATH not set) diff --git a/include/drivers/arm/cryptocell/712/rsa.h b/include/drivers/arm/cryptocell/712/rsa.h index cd9925b32..825214d20 100644 --- a/include/drivers/arm/cryptocell/712/rsa.h +++ b/include/drivers/arm/cryptocell/712/rsa.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,19 +21,21 @@ extern "C" /************************ Defines ******************************/ -/* the modulus size ion bits */ +/* the modulus size in bits */ +#if (KEY_SIZE == 2048) #define RSA_MOD_SIZE_IN_BITS 2048UL +#elif (KEY_SIZE == 3072) +#define RSA_MOD_SIZE_IN_BITS 3072UL +#else +#error Unsupported CryptoCell key size requested +#endif + #define RSA_MOD_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_MOD_SIZE_IN_BITS)) #define RSA_MOD_SIZE_IN_WORDS (CALC_FULL_32BIT_WORDS(RSA_MOD_SIZE_IN_BITS)) #define RSA_MOD_SIZE_IN_256BITS (RSA_MOD_SIZE_IN_WORDS/8) #define RSA_EXP_SIZE_IN_BITS 17UL #define RSA_EXP_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_EXP_SIZE_IN_BITS)) -/* size of buffer for Barrett modulus tag NP, used in PKA algorithms */ -#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS 132 -#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS)) -#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS (CALC_FULL_32BIT_WORDS(RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS)) - /* * @brief The RSA_CalcNp calculates Np value and saves it into Np_ptr: * diff --git a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h index 68b9ef8ae..ed1f2835c 100644 --- a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h +++ b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,7 +24,14 @@ extern "C" /***********************/ /*RSA definitions*/ +#if (KEY_SIZE == 2048) #define SB_RSA_MOD_SIZE_IN_WORDS 64 +#elif (KEY_SIZE == 3072) +#define SB_RSA_MOD_SIZE_IN_WORDS 96 +#else +#error Unsupported CryptoCell key size requested +#endif + #define SB_RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS 5 @@ -43,9 +50,12 @@ typedef struct { /********* Supported algorithms definitions ***********/ /*! RSA supported algorithms */ +/* Note: this applies to either 2k or 3k based on CryptoCell SBROM library + * version - it means 2k in version 1 and 3k in version 2 (yes, really). + */ typedef enum { - RSA_PSS_2048 = 0x01, /*!< RSA PSS 2048 after hash SHA 256 */ - RSA_PKCS15_2048 = 0x02, /*!< RSA PKX15 */ + RSA_PSS = 0x01, /*!< RSA PSS after hash SHA 256 */ + RSA_PKCS15 = 0x02, /*!< RSA PKX15 */ RSA_Last = 0x7FFFFFFF } CCSbRsaAlg_t; -- cgit v1.2.3 From b662232d189af5289c8810c628da1640b70ae352 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 8 Oct 2019 17:36:14 +0200 Subject: drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When USB3 is on lane 2 and indirect register access is used, the polling at the end of the mvebu_a3700_comphy_usb3_power_on function is incorrect. The LOOPBACK_REG0 register should not be used at all. Instead we have to write the LANE_STATUS1 register address (with offset USB3PHY_LANE2_REG_BASE_OFFSET) into the indirect address register and then we should poll indirect data register. This fixes problems on Turris Mox, which uses lane 2 for USB3. Signed-off-by: Marek Behún Change-Id: I968b0cccee5ddbe10a2b5614e52e52d87682aacd --- drivers/marvell/comphy/phy-comphy-3700.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c index 2e8c4128e..fa5183bc5 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.c +++ b/drivers/marvell/comphy/phy-comphy-3700.c @@ -721,11 +721,11 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, udelay(PLL_SET_DELAY_US); if (comphy_index == COMPHY_LANE2) { - data = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET; + data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET; mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, data); - addr = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET; + addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET; ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, COMPHY_PLL_TIMEOUT, REG_32BIT); } else { -- cgit v1.2.3 From 629dd61f1922231047fc62afc06f75e1d109e19e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 5 Nov 2019 15:21:54 +0100 Subject: drivers: marvell: comphy-a3700: support SGMII COMPHY power off MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for powering off the SGMII COMPHY (on lanes 0 and 1). This is needed sometimes on Turris Mox when using KEXEC. There is also another benefit of a little energy saving when the given network interface is down. Signed-off-by: Marek Behún Change-Id: I55ae0fe3627e7cc0f65c78a00771939d8bf5399f --- drivers/marvell/comphy/phy-comphy-3700.c | 69 ++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c index fa5183bc5..f6a40a587 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.c +++ b/drivers/marvell/comphy/phy-comphy-3700.c @@ -195,6 +195,45 @@ error: ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode); } +/* + * This is something like the inverse of the previous function: for given + * lane it returns COMPHY_*_MODE. + * + * It is useful when powering the phy off. + * + * This function returns COMPHY_USB3_MODE even if the phy was configured + * with COMPHY_USB3D_MODE or COMPHY_USB3H_MODE. (The usb3 phy initialization + * code does not differentiate between these modes.) + * Also it returns COMPHY_SGMII_MODE even if the phy was configures with + * COMPHY_HS_SGMII_MODE. (The sgmii phy initialization code does differentiate + * between these modes, but it is irrelevant when powering the phy off.) + */ +static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index) +{ + uint32_t reg; + + reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); + switch (comphy_index) { + case COMPHY_LANE0: + if ((reg & COMPHY_SELECTOR_USB3_GBE1_SEL_BIT) != 0) + return COMPHY_USB3_MODE; + else + return COMPHY_SGMII_MODE; + case COMPHY_LANE1: + if ((reg & COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT) != 0) + return COMPHY_PCIE_MODE; + else + return COMPHY_SGMII_MODE; + case COMPHY_LANE2: + if ((reg & COMPHY_SELECTOR_USB3_PHY_SEL_BIT) != 0) + return COMPHY_USB3_MODE; + else + return COMPHY_SATA_MODE; + } + + return COMPHY_UNUSED; +} + /* It is only used for SATA and USB3 on comphy lane2. */ static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data, uint16_t mask, int mode) @@ -547,6 +586,23 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, return ret; } +static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index) +{ + int ret = 0; + uint32_t mask, data, offset; + + debug_enter(); + + data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT; + mask = 0; + offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); + reg_set(offset, data, mask); + + debug_exit(); + + return ret; +} + static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, uint32_t comphy_mode) { @@ -908,7 +964,20 @@ int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode) debug_enter(); + if (!mode) { + /* + * The user did not specify which mode should be powered off. + * In this case we can identify this by reading the phy selector + * register. + */ + mode = mvebu_a3700_comphy_get_mode(comphy_index); + } + switch (mode) { + case(COMPHY_SGMII_MODE): + case(COMPHY_HS_SGMII_MODE): + err = mvebu_a3700_comphy_sgmii_power_off(comphy_index); + break; case (COMPHY_USB3_MODE): case (COMPHY_USB3H_MODE): err = mvebu_a3700_comphy_usb3_power_off(); -- cgit v1.2.3 From 0d1b704ad8338df36e428508cba77d26b18fd810 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Thu, 12 Dec 2019 10:46:09 +0800 Subject: intel: s10: Remove unused source code remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by: Hadi Asyrafi Change-Id: I395fed66408f536e8fefd637681e742c63621818 --- plat/intel/soc/stratix10/plat_psci.c | 208 ------------------ plat/intel/soc/stratix10/plat_sip_svc.c | 378 -------------------------------- 2 files changed, 586 deletions(-) delete mode 100644 plat/intel/soc/stratix10/plat_psci.c delete mode 100644 plat/intel/soc/stratix10/plat_sip_svc.c diff --git a/plat/intel/soc/stratix10/plat_psci.c b/plat/intel/soc/stratix10/plat_psci.c deleted file mode 100644 index 73389c95d..000000000 --- a/plat/intel/soc/stratix10/plat_psci.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "platform_def.h" -#include "s10_reset_manager.h" -#include "socfpga_mailbox.h" - -#define S10_RSTMGR_OFST 0xffd11000 -#define S10_RSTMGR_MPUMODRST_OFST 0x20 - -uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; -uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE; - -/******************************************************************************* - * plat handler called when a CPU is about to enter standby. - ******************************************************************************/ -void plat_cpu_standby(plat_local_state_t cpu_state) -{ - /* - * Enter standby state - * dsb is good practice before using wfi to enter low power states - */ - VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state); - dsb(); - wfi(); -} - -/******************************************************************************* - * plat handler called when a power domain is about to be turned on. The - * mpidr determines the CPU to be turned on. - ******************************************************************************/ -int plat_pwr_domain_on(u_register_t mpidr) -{ - unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); - - VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); - - if (cpu_id == -1) - return PSCI_E_INTERN_FAIL; - - *cpuid_release = cpu_id; - - /* release core reset */ - mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); - return PSCI_E_SUCCESS; -} - -/******************************************************************************* - * plat handler called when a power domain is about to be turned off. The - * target_state encodes the power state that each level should transition to. - ******************************************************************************/ -void plat_pwr_domain_off(const psci_power_state_t *target_state) -{ - unsigned int cpu_id = plat_my_core_pos(); - - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - - /* TODO: Prevent interrupts from spuriously waking up this cpu */ - /* gicv2_cpuif_disable(); */ - - /* assert core reset */ - mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); -} - -/******************************************************************************* - * plat handler called when a power domain is about to be suspended. The - * target_state encodes the power state that each level should transition to. - ******************************************************************************/ -void plat_pwr_domain_suspend(const psci_power_state_t *target_state) -{ - unsigned int cpu_id = plat_my_core_pos(); - - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - /* assert core reset */ - mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); - -} - -/******************************************************************************* - * plat handler called when a power domain has just been powered on after - * being turned off earlier. The target_state encodes the low power state that - * each level has woken up from. - ******************************************************************************/ -void plat_pwr_domain_on_finish(const psci_power_state_t *target_state) -{ - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - - /* Program the gic per-cpu distributor or re-distributor interface */ - gicv2_pcpu_distif_init(); - gicv2_set_pe_target_mask(plat_my_core_pos()); - - /* Enable the gic cpu interface */ - gicv2_cpuif_enable(); -} - -/******************************************************************************* - * plat handler called when a power domain has just been powered on after - * having been suspended earlier. The target_state encodes the low power state - * that each level has woken up from. - * TODO: At the moment we reuse the on finisher and reinitialize the secure - * context. Need to implement a separate suspend finisher. - ******************************************************************************/ -void plat_pwr_domain_suspend_finish(const psci_power_state_t *target_state) -{ - unsigned int cpu_id = plat_my_core_pos(); - - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - - /* release core reset */ - mmio_clrbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); -} - -/******************************************************************************* - * plat handlers to shutdown/reboot the system - ******************************************************************************/ -static void __dead2 plat_system_off(void) -{ - wfi(); - ERROR("System Off: operation not handled.\n"); - panic(); -} - -static void __dead2 plat_system_reset(void) -{ - INFO("assert Peripheral from Reset\r\n"); - - deassert_peripheral_reset(); - mailbox_reset_cold(); - - while (1) - wfi(); -} - -int plat_validate_power_state(unsigned int power_state, - psci_power_state_t *req_state) -{ - VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); - - return PSCI_E_SUCCESS; -} - -int plat_validate_ns_entrypoint(unsigned long ns_entrypoint) -{ - VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint); - return PSCI_E_SUCCESS; -} - -void plat_get_sys_suspend_power_state(psci_power_state_t *req_state) -{ - req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; - req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; -} - -/******************************************************************************* - * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard - * platform layer will take care of registering the handlers with PSCI. - ******************************************************************************/ -const plat_psci_ops_t plat_psci_pm_ops = { - .cpu_standby = plat_cpu_standby, - .pwr_domain_on = plat_pwr_domain_on, - .pwr_domain_off = plat_pwr_domain_off, - .pwr_domain_suspend = plat_pwr_domain_suspend, - .pwr_domain_on_finish = plat_pwr_domain_on_finish, - .pwr_domain_suspend_finish = plat_pwr_domain_suspend_finish, - .system_off = plat_system_off, - .system_reset = plat_system_reset, - .validate_power_state = plat_validate_power_state, - .validate_ns_entrypoint = plat_validate_ns_entrypoint, - .get_sys_suspend_power_state = plat_get_sys_suspend_power_state -}; - -/******************************************************************************* - * Export the platform specific power ops. - ******************************************************************************/ -int plat_setup_psci_ops(uintptr_t sec_entrypoint, - const struct plat_psci_ops **psci_ops) -{ - /* Save warm boot entrypoint.*/ - *stratix10_sec_entry = sec_entrypoint; - - *psci_ops = &plat_psci_pm_ops; - return 0; -} diff --git a/plat/intel/soc/stratix10/plat_sip_svc.c b/plat/intel/soc/stratix10/plat_sip_svc.c deleted file mode 100644 index 23a009d12..000000000 --- a/plat/intel/soc/stratix10/plat_sip_svc.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -/* Number of SiP Calls implemented */ -#define SIP_NUM_CALLS 0x3 - -/* Total buffer the driver can hold */ -#define FPGA_CONFIG_BUFFER_SIZE 4 - -int current_block; -int current_buffer; -int current_id = 1; -int max_blocks; -uint32_t bytes_per_block; -uint32_t blocks_submitted; -uint32_t blocks_completed; - -struct fpga_config_info { - uint32_t addr; - int size; - int size_written; - uint32_t write_requested; - int subblocks_sent; - int block_number; -}; - -/* SiP Service UUID */ -DEFINE_SVC_UUID2(intl_svc_uid, - 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, - 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); - -uint64_t plat_sip_handler(uint32_t smc_fid, - uint64_t x1, - uint64_t x2, - uint64_t x3, - uint64_t x4, - void *cookie, - void *handle, - uint64_t flags) -{ - ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); - SMC_RET1(handle, SMC_UNK); -} - -struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; - -static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) -{ - uint32_t args[3]; - - while (max_blocks > 0 && buffer->size > buffer->size_written) { - if (buffer->size - buffer->size_written <= - bytes_per_block) { - args[0] = (1<<8); - args[1] = buffer->addr + buffer->size_written; - args[2] = buffer->size - buffer->size_written; - buffer->size_written += - buffer->size - buffer->size_written; - buffer->subblocks_sent++; - mailbox_send_cmd_async(0x4, - MBOX_RECONFIG_DATA, - args, 3, 0); - current_buffer++; - current_buffer %= FPGA_CONFIG_BUFFER_SIZE; - } else { - args[0] = (1<<8); - args[1] = buffer->addr + buffer->size_written; - args[2] = bytes_per_block; - buffer->size_written += bytes_per_block; - mailbox_send_cmd_async(0x4, - MBOX_RECONFIG_DATA, - args, 3, 0); - buffer->subblocks_sent++; - } - max_blocks--; - } -} - -static int intel_fpga_sdm_write_all(void) -{ - int i; - - for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) - intel_fpga_sdm_write_buffer( - &fpga_config_buffers[current_buffer]); - - return 0; -} - -uint32_t intel_mailbox_fpga_config_isdone(void) -{ - uint32_t args[2]; - uint32_t response[6]; - int status; - - status = mailbox_send_cmd(1, MBOX_RECONFIG_STATUS, args, 0, 0, - response); - - if (status < 0) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (response[RECONFIG_STATUS_STATE] && - response[RECONFIG_STATUS_STATE] != MBOX_CFGSTAT_STATE_CONFIG) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (!(response[RECONFIG_STATUS_PIN_STATUS] & PIN_STATUS_NSTATUS)) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_SEU_ERROR) - return INTEL_SIP_SMC_STATUS_ERROR; - - if ((response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_CONF_DONE) && - (response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_INIT_DONE)) - return INTEL_SIP_SMC_STATUS_OK; - - return INTEL_SIP_SMC_STATUS_ERROR; -} - -static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) -{ - int i; - - for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - if (fpga_config_buffers[i].block_number == current_block) { - fpga_config_buffers[i].subblocks_sent--; - if (fpga_config_buffers[i].subblocks_sent == 0 - && fpga_config_buffers[i].size <= - fpga_config_buffers[i].size_written) { - fpga_config_buffers[i].write_requested = 0; - current_block++; - *buffer_addr_completed = - fpga_config_buffers[i].addr; - return 0; - } - } - } - - return -1; -} - -unsigned int address_in_ddr(uint32_t *addr) -{ - if (((unsigned long long)addr > DRAM_BASE) && - ((unsigned long long)addr < DRAM_BASE + DRAM_SIZE)) - return 0; - - return -1; -} - -int intel_fpga_config_completed_write(uint32_t *completed_addr, - uint32_t *count) -{ - uint32_t status = INTEL_SIP_SMC_STATUS_OK; - *count = 0; - int resp_len = 0; - uint32_t resp[5]; - int all_completed = 1; - int count_check = 0; - - if (address_in_ddr(completed_addr) != 0 || address_in_ddr(count) != 0) - return INTEL_SIP_SMC_STATUS_ERROR; - - for (count_check = 0; count_check < 3; count_check++) - if (address_in_ddr(&completed_addr[*count + count_check]) != 0) - return INTEL_SIP_SMC_STATUS_ERROR; - - resp_len = mailbox_read_response(0x4, resp); - - while (resp_len >= 0 && *count < 3) { - max_blocks++; - if (mark_last_buffer_xfer_completed( - &completed_addr[*count]) == 0) - *count = *count + 1; - else - break; - resp_len = mailbox_read_response(0x4, resp); - } - - if (*count <= 0) { - if (resp_len != MBOX_NO_RESPONSE && - resp_len != MBOX_TIMEOUT && resp_len != 0) { - return INTEL_SIP_SMC_STATUS_ERROR; - } - - *count = 0; - } - - intel_fpga_sdm_write_all(); - - if (*count > 0) - status = INTEL_SIP_SMC_STATUS_OK; - else if (*count == 0) - status = INTEL_SIP_SMC_STATUS_BUSY; - - for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - if (fpga_config_buffers[i].write_requested != 0) { - all_completed = 0; - break; - } - } - - if (all_completed == 1) - return INTEL_SIP_SMC_STATUS_OK; - - return status; -} - -int intel_fpga_config_start(uint32_t config_type) -{ - uint32_t response[3]; - int status = 0; - - status = mailbox_send_cmd(2, MBOX_RECONFIG, 0, 0, 0, - response); - - if (status < 0) - return status; - - max_blocks = response[0]; - bytes_per_block = response[1]; - - for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - fpga_config_buffers[i].size = 0; - fpga_config_buffers[i].size_written = 0; - fpga_config_buffers[i].addr = 0; - fpga_config_buffers[i].write_requested = 0; - fpga_config_buffers[i].block_number = 0; - fpga_config_buffers[i].subblocks_sent = 0; - } - - blocks_submitted = 0; - current_block = 0; - current_buffer = 0; - - return 0; -} - - -uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) -{ - int i = 0; - uint32_t status = INTEL_SIP_SMC_STATUS_OK; - - if (mem < DRAM_BASE || mem > DRAM_BASE + DRAM_SIZE) - status = INTEL_SIP_SMC_STATUS_REJECTED; - - if (mem + size > DRAM_BASE + DRAM_SIZE) - status = INTEL_SIP_SMC_STATUS_REJECTED; - - for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - if (!fpga_config_buffers[i].write_requested) { - fpga_config_buffers[i].addr = mem; - fpga_config_buffers[i].size = size; - fpga_config_buffers[i].size_written = 0; - fpga_config_buffers[i].write_requested = 1; - fpga_config_buffers[i].block_number = - blocks_submitted++; - fpga_config_buffers[i].subblocks_sent = 0; - break; - } - } - - - if (i == FPGA_CONFIG_BUFFER_SIZE) { - status = INTEL_SIP_SMC_STATUS_REJECTED; - return status; - } else if (i == FPGA_CONFIG_BUFFER_SIZE - 1) { - status = INTEL_SIP_SMC_STATUS_BUSY; - } - - intel_fpga_sdm_write_all(); - - return status; -} - -/* - * This function is responsible for handling all SiP calls from the NS world - */ - -uintptr_t sip_smc_handler(uint32_t smc_fid, - u_register_t x1, - u_register_t x2, - u_register_t x3, - u_register_t x4, - void *cookie, - void *handle, - u_register_t flags) -{ - uint32_t status = INTEL_SIP_SMC_STATUS_OK; - uint32_t completed_addr[3]; - uint32_t count = 0; - - switch (smc_fid) { - case SIP_SVC_UID: - /* Return UID to the caller */ - SMC_UUID_RET(handle, intl_svc_uid); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: - status = intel_mailbox_fpga_config_isdone(); - SMC_RET4(handle, status, 0, 0, 0); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: - SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, - INTEL_SIP_SMC_FPGA_CONFIG_ADDR, - INTEL_SIP_SMC_FPGA_CONFIG_SIZE - - INTEL_SIP_SMC_FPGA_CONFIG_ADDR); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_START: - status = intel_fpga_config_start(x1); - SMC_RET4(handle, status, 0, 0, 0); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: - status = intel_fpga_config_write(x1, x2); - SMC_RET4(handle, status, 0, 0, 0); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: - status = intel_fpga_config_completed_write(completed_addr, - &count); - switch (count) { - case 1: - SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, - completed_addr[0], 0, 0); - break; - case 2: - SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, - completed_addr[0], - completed_addr[1], 0); - break; - case 3: - SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, - completed_addr[0], - completed_addr[1], - completed_addr[2]); - break; - case 0: - SMC_RET4(handle, status, 0, 0, 0); - break; - default: - SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); - } - break; - - default: - return plat_sip_handler(smc_fid, x1, x2, x3, x4, - cookie, handle, flags); - } -} - -DECLARE_RT_SVC( - s10_sip_svc, - OEN_SIP_START, - OEN_SIP_END, - SMC_TYPE_FAST, - NULL, - sip_smc_handler -); - -DECLARE_RT_SVC( - s10_sip_svc_std, - OEN_SIP_START, - OEN_SIP_END, - SMC_TYPE_YIELD, - NULL, - sip_smc_handler -); -- cgit v1.2.3 From da90359b7852e13dc21f54f4d42df6d4790fe0cd Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Tue, 26 Nov 2019 11:34:17 +0000 Subject: PIE: make call to GDT relocation fixup generalized When a Firmware is complied as Position Independent Executable it needs to request GDT fixup by passing size of the memory region to el3_entrypoint_common macro. The Global descriptor table fixup will be done early on during cold boot process of primary core. Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be compiled as PIE, it can simply pass fixup size to the common el3 entrypoint macro to fixup GDT. The reason for this patch was to overcome the bug introduced by SHA 330ead806 which called fixup routine for each core causing re-initializing of global pointers thus overwriting any changes done by the previous core. Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055 Signed-off-by: Manish Pandey --- bl1/aarch64/bl1_entrypoint.S | 3 ++- bl2/aarch64/bl2_el3_entrypoint.S | 3 ++- bl31/aarch64/bl31_entrypoint.S | 20 ++++++-------------- include/arch/aarch64/el3_common_macros.S | 29 ++++++++++++++++++++++++++++- 4 files changed, 38 insertions(+), 17 deletions(-) diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index 855add347..00f27184d 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -30,7 +30,8 @@ func bl1_entrypoint _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ _init_memory=1 \ _init_c_runtime=1 \ - _exception_vectors=bl1_exceptions + _exception_vectors=bl1_exceptions \ + _pie_fixup_size=0 /* -------------------------------------------------------------------- * Perform BL1 setup diff --git a/bl2/aarch64/bl2_el3_entrypoint.S b/bl2/aarch64/bl2_el3_entrypoint.S index 6fe2dd923..f97121ef0 100644 --- a/bl2/aarch64/bl2_el3_entrypoint.S +++ b/bl2/aarch64/bl2_el3_entrypoint.S @@ -26,7 +26,8 @@ func bl2_entrypoint _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ _init_memory=1 \ _init_c_runtime=1 \ - _exception_vectors=bl2_el3_exceptions + _exception_vectors=bl2_el3_exceptions \ + _pie_fixup_size=0 /* --------------------------------------------- * Restore parameters of boot rom diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 1ad26e4fe..74b0993f3 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -32,17 +32,6 @@ func bl31_entrypoint mov x22, x2 mov x23, x3 - /* -------------------------------------------------------------------- - * If PIE is enabled, fixup the Global descriptor Table and dynamic - * relocations - * -------------------------------------------------------------------- - */ -#if ENABLE_PIE - mov_imm x0, BL31_BASE - mov_imm x1, BL31_LIMIT - bl fixup_gdt_reloc -#endif /* ENABLE_PIE */ - #if !RESET_TO_BL31 /* --------------------------------------------------------------------- * For !RESET_TO_BL31 systems, only the primary CPU ever reaches @@ -59,7 +48,8 @@ func bl31_entrypoint _secondary_cold_boot=0 \ _init_memory=0 \ _init_c_runtime=1 \ - _exception_vectors=runtime_exceptions + _exception_vectors=runtime_exceptions \ + _pie_fixup_size=BL31_LIMIT - BL31_BASE #else /* --------------------------------------------------------------------- @@ -74,7 +64,8 @@ func bl31_entrypoint _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ _init_memory=1 \ _init_c_runtime=1 \ - _exception_vectors=runtime_exceptions + _exception_vectors=runtime_exceptions \ + _pie_fixup_size=BL31_LIMIT - BL31_BASE /* --------------------------------------------------------------------- * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so @@ -174,7 +165,8 @@ func bl31_warm_entrypoint _secondary_cold_boot=0 \ _init_memory=0 \ _init_c_runtime=0 \ - _exception_vectors=runtime_exceptions + _exception_vectors=runtime_exceptions \ + _pie_fixup_size=0 /* * We're about to enable MMU and participate in PSCI state coordination. diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 378e827ce..b14b7b66e 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -232,11 +232,18 @@ * * _exception_vectors: * Address of the exception vectors to program in the VBAR_EL3 register. + * + * _pie_fixup_size: + * Size of memory region to fixup Global Descriptor Table (GDT). + * + * A non-zero value is expected when firmware needs GDT to be fixed-up. + * * ----------------------------------------------------------------------------- */ .macro el3_entrypoint_common \ _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ - _init_memory, _init_c_runtime, _exception_vectors + _init_memory, _init_c_runtime, _exception_vectors, \ + _pie_fixup_size .if \_init_sctlr /* ------------------------------------------------------------- @@ -283,6 +290,26 @@ do_cold_boot: .endif /* _warm_boot_mailbox */ + .if \_pie_fixup_size +#if ENABLE_PIE + /* + * ------------------------------------------------------------ + * If PIE is enabled fixup the Global descriptor Table only + * once during primary core cold boot path. + * + * Compile time base address, required for fixup, is calculated + * using "pie_fixup" label present within first page. + * ------------------------------------------------------------ + */ + pie_fixup: + ldr x0, =pie_fixup + and x0, x0, #~(PAGE_SIZE - 1) + mov_imm x1, \_pie_fixup_size + add x1, x1, x0 + bl fixup_gdt_reloc +#endif /* ENABLE_PIE */ + .endif /* _pie_fixup_size */ + /* --------------------------------------------------------------------- * Set the exception vectors. * --------------------------------------------------------------------- -- cgit v1.2.3 From 8cca5a79f1cf1e978bdfc97bcd9c878f960694f0 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Wed, 18 Sep 2019 15:32:37 +0100 Subject: Remove -Wmissing-declarations warning from WARNING1 level A function declaration declares the name of the function and the type of the parameter it returns. A function prototype is a function declaration that also specifies the type of the arguments of the function. Essentially, a function prototype helps the compiler ensure whether the function call matches the return type and the right number/type of arguments of function. A function prototype itself serves as a function declaration for new style functions. The warning flag -wmissing-prototype is good enough to check for missing function prototype and is exhaustive compared to -wmissing-declaration, therefore making the later redundant. Note that, at this point, these flags are part of WARNING1 which is not used for TF-A build by default. Several platforms use upstream libraries (such as zlib etc) which are in old style c code. After the TF-A build process is restructred using CMake framework, we plan to enable WARNING1, WARNING2 and WARNING3 incrementally as the new build platform can compile each BL binary of a particular platform with set of unique compilation flags. Change-Id: I9c6bf9da74e0840e4d2624bc12376e199953c213 Signed-off-by: Justin Chadwell --- Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/Makefile b/Makefile index 54d332cd7..ef3ee4b53 100644 --- a/Makefile +++ b/Makefile @@ -248,7 +248,6 @@ WARNINGS := -Wall -Wmissing-include-dirs -Wunused \ # Additional warnings # Level 1 WARNING1 := -Wextra -WARNING1 += -Wmissing-declarations WARNING1 += -Wmissing-format-attribute WARNING1 += -Wmissing-prototypes WARNING1 += -Wold-style-definition -- cgit v1.2.3 From f0063ef948cb3392ae11b61b83605a58471ac7dd Mon Sep 17 00:00:00 2001 From: Ziyuan Xu Date: Tue, 8 Oct 2019 10:27:05 +0800 Subject: plat/rockchip: cliam a macro to enable hdcp feature for DP HDCP is using a binary driver, add macro PLAT_RK_DP_HDCP to make it as an option. Change-Id: I54ef1a3635a28e8ae56654bd1e91dfe011520a7f Signed-off-by: Ziyuan Xu Signed-off-by: Kever Yang --- plat/rockchip/rk3399/plat_sip_calls.c | 4 ++++ plat/rockchip/rk3399/platform.mk | 11 +++++++---- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/plat/rockchip/rk3399/plat_sip_calls.c b/plat/rockchip/rk3399/plat_sip_calls.c index c2cc5b11c..ce8476c9a 100644 --- a/plat/rockchip/rk3399/plat_sip_calls.c +++ b/plat/rockchip/rk3399/plat_sip_calls.c @@ -56,17 +56,21 @@ uintptr_t rockchip_plat_sip_handler(uint32_t smc_fid, void *handle, u_register_t flags) { +#ifdef PLAT_RK_DP_HDCP uint64_t x5, x6; +#endif switch (smc_fid) { case RK_SIP_DDR_CFG: SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4)); +#ifdef PLAT_RK_DP_HDCP case RK_SIP_HDCP_CONTROL: SMC_RET1(handle, dp_hdcp_ctrl(x1)); case RK_SIP_HDCP_KEY_DATA64: x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); x6 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X6); SMC_RET1(handle, dp_hdcp_store_key(x1, x2, x3, x4, x5, x6)); +#endif default: ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); SMC_RET1(handle, SMC_UNK); diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk index cfc48e8f9..4a725eb11 100644 --- a/plat/rockchip/rk3399/platform.mk +++ b/plat/rockchip/rk3399/platform.mk @@ -56,7 +56,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_COMMON}/aarch64/platform_common.c \ ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ ${RK_PLAT_SOC}/plat_sip_calls.c \ - ${RK_PLAT_SOC}/drivers/dp/cdn_dp.c \ ${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \ ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ ${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c \ @@ -87,17 +86,21 @@ $(eval $(call add_define,RK3399M0FW)) RK3399M0PMUFW=${BUILD_M0}/${PLAT_M0}pmu.bin $(eval $(call add_define,RK3399M0PMUFW)) +ifdef PLAT_RK_DP_HDCP +BL31_SOURCES += ${RK_PLAT_SOC}/drivers/dp/cdn_dp.c + HDCPFW=${RK_PLAT_SOC}/drivers/dp/hdcp.bin $(eval $(call add_define,HDCPFW)) +${BUILD_PLAT}/bl31/cdn_dp.o: CCACHE_EXTRAFILES=$(HDCPFW) +${RK_PLAT_SOC}/drivers/dp/cdn_dp.c: $(HDCPFW) +endif + # CCACHE_EXTRAFILES is needed because ccache doesn't handle .incbin export CCACHE_EXTRAFILES ${BUILD_PLAT}/bl31/pmu_fw.o: CCACHE_EXTRAFILES=$(RK3399M0FW):$(RK3399M0PMUFW) ${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c: $(RK3399M0FW) -${BUILD_PLAT}/bl31/cdn_dp.o: CCACHE_EXTRAFILES=$(HDCPFW) -${RK_PLAT_SOC}/drivers/dp/cdn_dp.c: $(HDCPFW) - $(eval $(call MAKE_PREREQ_DIR,${BUILD_M0},${BUILD_PLAT})) .PHONY: $(RK3399M0FW) $(RK3399M0FW): | ${BUILD_M0} -- cgit v1.2.3 From 39a97dce61aca9f618e28e26c6e441c8976f3172 Mon Sep 17 00:00:00 2001 From: Joshua Watt Date: Fri, 13 Dec 2019 13:44:55 -0600 Subject: rockchip: Prevent macro expansion in paths Instead of stringizing the paths to binary files, add them as string defines on the command line (e.g. -DFOO=\"BAR\" instead of -DFOO=BAR). This prevents macros from being expanded inside the string value itself. For example, -DFOO=/path/with-linux-in-it would have been expanded to "/path/with-1-in-it" because `linux=1` is one of the standard GCC defines. Change-Id: I7b65df3c9930faed4f1aff75ad726982ae3671e6 Signed-off-by: Joshua Watt --- plat/rockchip/rk3399/drivers/dp/cdn_dp.c | 2 +- plat/rockchip/rk3399/drivers/pmu/pmu_fw.c | 24 +++++++++++------------- plat/rockchip/rk3399/platform.mk | 6 +++--- 3 files changed, 15 insertions(+), 17 deletions(-) diff --git a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c index aa71fdea6..a8773f4f6 100644 --- a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c +++ b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c @@ -18,7 +18,7 @@ __asm__( ".global hdcp_handler\n" ".balign 4\n" "hdcp_handler:\n" - ".incbin \"" __XSTRING(HDCPFW) "\"\n" + ".incbin \"" HDCPFW "\"\n" ".type hdcp_handler, %function\n" ".size hdcp_handler, .- hdcp_handler\n" ".popsection\n" diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c b/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c index a09ad21e8..25596b188 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c @@ -5,20 +5,18 @@ */ /* convoluted way to make sure that the define is pasted just the right way */ -#define _INCBIN(file, sym, sec) \ +#define INCBIN(file, sym, sec) \ __asm__( \ - ".section " #sec "\n" \ - ".global " #sym "\n" \ - ".type " #sym ", %object\n" \ + ".section " sec "\n" \ + ".global " sym "\n" \ + ".type " sym ", %object\n" \ ".align 4\n" \ - #sym ":\n" \ - ".incbin \"" #file "\"\n" \ - ".size " #sym ", .-" #sym "\n" \ - ".global " #sym "_end\n" \ - #sym "_end:\n" \ + sym ":\n" \ + ".incbin \"" file "\"\n" \ + ".size " sym ", .-" sym "\n" \ + ".global " sym "_end\n" \ + sym "_end:\n" \ ) -#define INCBIN(file, sym, sec) _INCBIN(file, sym, sec) - -INCBIN(RK3399M0FW, rk3399m0_bin, ".sram.incbin"); -INCBIN(RK3399M0PMUFW, rk3399m0pmu_bin, ".pmusram.incbin"); +INCBIN(RK3399M0FW, "rk3399m0_bin", ".sram.incbin"); +INCBIN(RK3399M0PMUFW, "rk3399m0pmu_bin", ".pmusram.incbin"); diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk index cfc48e8f9..643c24f54 100644 --- a/plat/rockchip/rk3399/platform.mk +++ b/plat/rockchip/rk3399/platform.mk @@ -82,13 +82,13 @@ PLAT_M0 := ${PLAT}m0 BUILD_M0 := ${BUILD_PLAT}/m0 RK3399M0FW=${BUILD_M0}/${PLAT_M0}.bin -$(eval $(call add_define,RK3399M0FW)) +$(eval $(call add_define_val,RK3399M0FW,\"$(RK3399M0FW)\")) RK3399M0PMUFW=${BUILD_M0}/${PLAT_M0}pmu.bin -$(eval $(call add_define,RK3399M0PMUFW)) +$(eval $(call add_define_val,RK3399M0PMUFW,\"$(RK3399M0PMUFW)\")) HDCPFW=${RK_PLAT_SOC}/drivers/dp/hdcp.bin -$(eval $(call add_define,HDCPFW)) +$(eval $(call add_define_val,HDCPFW,\"$(HDCPFW)\")) # CCACHE_EXTRAFILES is needed because ccache doesn't handle .incbin export CCACHE_EXTRAFILES -- cgit v1.2.3 From eb75518d988e8a59f21ab1ac77e5ae928526e06e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 14:17:30 -0500 Subject: allwinner: Enable clock before resetting I2C/RSB The clock must be running for the module to be reset. Signed-off-by: Samuel Holland Change-Id: Ic8fafc946f3a1a697174b91288e357ffa033ab9a --- plat/allwinner/common/sunxi_common.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c index 0797452a6..1e21a4262 100644 --- a/plat/allwinner/common/sunxi_common.c +++ b/plat/allwinner/common/sunxi_common.c @@ -150,16 +150,16 @@ int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb) /* set both pins to pull-up */ mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U); - /* assert, then de-assert reset of I2C/RSB controller */ - mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); - mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); - /* un-gate clock */ if (socid != SUNXI_SOC_H6) mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); else mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0)); + /* assert, then de-assert reset of I2C/RSB controller */ + mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); + mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); + return 0; } -- cgit v1.2.3 From c0e109f2feb4fb40c9b345684ab18b8afd9e94cb Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 15:12:20 -0500 Subject: allwinner: Synchronize PMIC enumerations Ensure that the default (zero) value represents the case where we take no action. Previously, if a PLAT=sun50i_a64 build was booted on an unknown SoC ID, it would be treated as an H5 at shutdown. This removes some duplicate code and fixes error propagation on H6. Signed-off-by: Samuel Holland Change-Id: I4e51d8a43a56eccb0d8088593cb9908e52e782bc --- plat/allwinner/sun50i_a64/sunxi_power.c | 3 ++- plat/allwinner/sun50i_h6/sunxi_power.c | 17 +++++++---------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index d48ff56dc..13a6a9ba9 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018, Icenowy Zheng * * SPDX-License-Identifier: BSD-3-Clause @@ -22,6 +22,7 @@ #include static enum pmic_type { + UNKNOWN, GENERIC_H5, GENERIC_A64, REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */ diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c index 5b5bad177..36e3dbe74 100644 --- a/plat/allwinner/sun50i_h6/sunxi_power.c +++ b/plat/allwinner/sun50i_h6/sunxi_power.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018, Icenowy Zheng * * SPDX-License-Identifier: BSD-3-Clause @@ -21,12 +21,10 @@ #define AXP805_ADDR 0x36 #define AXP805_ID 0x03 -enum pmic_type { - NO_PMIC, +static enum pmic_type { + UNKNOWN, AXP805, -}; - -enum pmic_type pmic; +} pmic; int axp_i2c_read(uint8_t chip, uint8_t reg, uint8_t *val) { @@ -79,13 +77,12 @@ int sunxi_pmic_setup(uint16_t socid, const void *fdt) i2c_init((void *)SUNXI_R_I2C_BASE); NOTICE("PMIC: Probing AXP805\n"); - pmic = AXP805; ret = axp805_probe(); if (ret) - pmic = NO_PMIC; - else - pmic = AXP805; + return ret; + + pmic = AXP805; return 0; } -- cgit v1.2.3 From 4538c4983b2f64160afcbe7a4d36b0810b1c430c Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 15:28:14 -0500 Subject: allwinner: Clean up PMIC-related error handling - Check the return value from sunxi_init_platform_r_twi(). - Print the PMIC banner before doing anything that might fail. - Remove double prefixes in error messages. - Consistently omit the trailing period. - No need to print the unknown SoC's ID, since we already did that earlier in bl31_platform_setup(). - On the other hand, do print the ID of the unknown PMIC. - Try to keep the messages concise, as the large string size in these files was causing the firmware to spill into the next page. - Downgrade the banner from NOTICE to INFO. It's purely informational, and people should be using debug builds on untested hardware anyway. Signed-off-by: Samuel Holland Change-Id: Ib909408a5fdaebe05470fbce48d245dd0bf040eb --- plat/allwinner/sun50i_a64/sunxi_power.c | 14 +++++++---- plat/allwinner/sun50i_h6/sunxi_power.c | 42 ++++++++++++++++++++------------- 2 files changed, 34 insertions(+), 22 deletions(-) diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index 13a6a9ba9..b0d042723 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -232,7 +232,7 @@ static void setup_axp803_rails(const void *fdt) /* locate the PMIC DT node, bail out if not found */ node = fdt_node_offset_by_compatible(fdt, -1, "x-powers,axp803"); if (node < 0) { - WARN("BL31: PMIC: Cannot find AXP803 DT node, skipping initial setup.\n"); + WARN("PMIC: No PMIC DT node, skipping setup\n"); return; } @@ -245,7 +245,7 @@ static void setup_axp803_rails(const void *fdt) /* descend into the "regulators" subnode */ node = fdt_subnode_offset(fdt, node, "regulators"); if (node < 0) { - WARN("BL31: PMIC: Cannot find regulators subnode, skipping initial setup.\n"); + WARN("PMIC: No regulators DT node, skipping setup\n"); return; } @@ -275,6 +275,7 @@ static void setup_axp803_rails(const void *fdt) continue; } } + /* * If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts * down. So always enable DC1SW as the very last regulator. @@ -291,11 +292,16 @@ int sunxi_pmic_setup(uint16_t socid, const void *fdt) switch (socid) { case SUNXI_SOC_H5: + NOTICE("PMIC: Assuming H5 reference regulator design\n"); + pmic = REF_DESIGN_H5; - NOTICE("BL31: PMIC: Defaulting to PortL GPIO according to H5 reference design.\n"); + break; case SUNXI_SOC_A64: pmic = GENERIC_A64; + + INFO("PMIC: Probing AXP803 on RSB\n"); + ret = sunxi_init_platform_r_twi(socid, true); if (ret) return ret; @@ -305,14 +311,12 @@ int sunxi_pmic_setup(uint16_t socid, const void *fdt) return ret; pmic = AXP803_RSB; - NOTICE("BL31: PMIC: Detected AXP803 on RSB.\n"); if (fdt) setup_axp803_rails(fdt); break; default: - NOTICE("BL31: PMIC: No support for Allwinner %x SoC.\n", socid); return -ENODEV; } return 0; diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c index 36e3dbe74..08c74f8e0 100644 --- a/plat/allwinner/sun50i_h6/sunxi_power.c +++ b/plat/allwinner/sun50i_h6/sunxi_power.c @@ -31,15 +31,23 @@ int axp_i2c_read(uint8_t chip, uint8_t reg, uint8_t *val) int ret; ret = i2c_write(chip, 0, 0, ®, 1); + if (ret == 0) + ret = i2c_read(chip, 0, 0, val, 1); if (ret) - return ret; + ERROR("PMIC: Cannot read AXP805 register %02x\n", reg); - return i2c_read(chip, 0, 0, val, 1); + return ret; } int axp_i2c_write(uint8_t chip, uint8_t reg, uint8_t val) { - return i2c_write(chip, reg, 1, &val, 1); + int ret; + + ret = i2c_write(chip, reg, 1, &val, 1); + if (ret) + ERROR("PMIC: Cannot write AXP805 register %02x\n", reg); + + return ret; } static int axp805_probe(void) @@ -47,21 +55,18 @@ static int axp805_probe(void) int ret; uint8_t val; + /* Switch the AXP805 to master/single-PMIC mode. */ ret = axp_i2c_write(AXP805_ADDR, 0xff, 0x0); - if (ret) { - ERROR("PMIC: Cannot put AXP805 to master mode.\n"); - return -EPERM; - } + if (ret) + return ret; ret = axp_i2c_read(AXP805_ADDR, AXP805_ID, &val); + if (ret) + return ret; - if (!ret && ((val & 0xcf) == 0x40)) - NOTICE("PMIC: AXP805 detected\n"); - else if (ret) { - ERROR("PMIC: Cannot communicate with AXP805.\n"); - return -EPERM; - } else { - ERROR("PMIC: Non-AXP805 chip attached at AXP805's address.\n"); + val &= 0xcf; + if (val != 0x40) { + ERROR("PMIC: Found unknown PMIC %02x\n", val); return -EINVAL; } @@ -72,12 +77,15 @@ int sunxi_pmic_setup(uint16_t socid, const void *fdt) { int ret; - sunxi_init_platform_r_twi(SUNXI_SOC_H6, false); + INFO("PMIC: Probing AXP805 on I2C\n"); + + ret = sunxi_init_platform_r_twi(SUNXI_SOC_H6, false); + if (ret) + return ret; + /* initialise mi2cv driver */ i2c_init((void *)SUNXI_R_I2C_BASE); - NOTICE("PMIC: Probing AXP805\n"); - ret = axp805_probe(); if (ret) return ret; -- cgit v1.2.3 From 818e67324bbe5fb74191182bd6bbafd1e1baab58 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 15:06:57 -0500 Subject: allwinner: Merge duplicate code in sunxi_power_down The action of last resort isn't going to change between SoCs. This moves that code back to the PSCI implementation, where it more obviously matches the code in sunxi_system_reset(). The two error messages say essentially the same thing anyway. Signed-off-by: Samuel Holland Change-Id: I62ac35fdb5ed78a016e9b18281416f1dcea38a4a --- plat/allwinner/common/include/sunxi_private.h | 2 +- plat/allwinner/common/sunxi_pm.c | 7 ++++++- plat/allwinner/sun50i_a64/sunxi_power.c | 6 +----- plat/allwinner/sun50i_h6/sunxi_power.c | 7 +------ 4 files changed, 9 insertions(+), 13 deletions(-) diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h index 1f410559f..dcf3dc965 100644 --- a/plat/allwinner/common/include/sunxi_private.h +++ b/plat/allwinner/common/include/sunxi_private.h @@ -12,7 +12,7 @@ void sunxi_configure_mmu_el3(int flags); void sunxi_cpu_on(u_register_t mpidr); void sunxi_cpu_off(u_register_t mpidr); void sunxi_disable_secondary_cpus(u_register_t primary_mpidr); -void __dead2 sunxi_power_down(void); +void sunxi_power_down(void); int sunxi_pmic_setup(uint16_t socid, const void *fdt); void sunxi_security_setup(void); diff --git a/plat/allwinner/common/sunxi_pm.c b/plat/allwinner/common/sunxi_pm.c index 13e135325..9b074d2ac 100644 --- a/plat/allwinner/common/sunxi_pm.c +++ b/plat/allwinner/common/sunxi_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -65,6 +65,11 @@ static void __dead2 sunxi_system_off(void) sunxi_disable_secondary_cpus(read_mpidr()); sunxi_power_down(); + + udelay(1000); + ERROR("PSCI: Cannot turn off system, halting\n"); + wfi(); + panic(); } static void __dead2 sunxi_system_reset(void) diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index b0d042723..b6437eae2 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -322,7 +322,7 @@ int sunxi_pmic_setup(uint16_t socid, const void *fdt) return 0; } -void __dead2 sunxi_power_down(void) +void sunxi_power_down(void) { switch (pmic) { case GENERIC_H5: @@ -368,8 +368,4 @@ void __dead2 sunxi_power_down(void) break; } - udelay(1000); - ERROR("PSCI: Cannot turn off system, halting.\n"); - wfi(); - panic(); } diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c index 08c74f8e0..7bb266b88 100644 --- a/plat/allwinner/sun50i_h6/sunxi_power.c +++ b/plat/allwinner/sun50i_h6/sunxi_power.c @@ -95,7 +95,7 @@ int sunxi_pmic_setup(uint16_t socid, const void *fdt) return 0; } -void __dead2 sunxi_power_down(void) +void sunxi_power_down(void) { uint8_t val; @@ -111,9 +111,4 @@ void __dead2 sunxi_power_down(void) default: break; } - - udelay(1000); - ERROR("PSCI: Cannot communicate with PMIC, halting\n"); - wfi(); - panic(); } -- cgit v1.2.3 From df77a9545150aeaef825afd4efd659044f557ca4 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 20:00:27 -0500 Subject: allwinner: a64: power: Make sunxi_turn_off_soc static The function is only used in this file, and it doesn't make sense for it to be used anywhere else. Signed-off-by: Samuel Holland Change-Id: Iab18f082911edcdbc37ceeaff8c512be68e0cb0f --- plat/allwinner/sun50i_a64/sunxi_power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index b6437eae2..d14ced9dc 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -39,7 +39,7 @@ static enum pmic_type { * disabled. * This function only cares about peripherals. */ -void sunxi_turn_off_soc(uint16_t socid) +static void sunxi_turn_off_soc(uint16_t socid) { int i; -- cgit v1.2.3 From 18fbfefbbb1e0b86353d2b849b99fae37bbd95f0 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 19:42:15 -0500 Subject: allwinner: Build PMIC bus drivers only in BL31 These are used by the PMIC setup code, which runs during BL31 initialization, and the PSCI shutdown code, also a part of BL31. They can't be needed before BL31, or it wouldn't be possible to boot. Allwinner platforms don't generally build anything but BL31 anyway, but this change improves clarity and consistency with allwinner-common.mk. Signed-off-by: Samuel Holland Change-Id: I24f1d9ca8b4256e44badf5218d04d8690082babf --- plat/allwinner/sun50i_a64/platform.mk | 4 ++-- plat/allwinner/sun50i_h6/platform.mk | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/allwinner/sun50i_a64/platform.mk b/plat/allwinner/sun50i_a64/platform.mk index b46fbc2d1..17bdf63f3 100644 --- a/plat/allwinner/sun50i_a64/platform.mk +++ b/plat/allwinner/sun50i_a64/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -7,4 +7,4 @@ # The differences between the platform are covered by the include files. include plat/allwinner/common/allwinner-common.mk -PLAT_BL_COMMON_SOURCES += drivers/allwinner/sunxi_rsb.c +BL31_SOURCES += drivers/allwinner/sunxi_rsb.c diff --git a/plat/allwinner/sun50i_h6/platform.mk b/plat/allwinner/sun50i_h6/platform.mk index 5c21eadb2..fa1b0e598 100644 --- a/plat/allwinner/sun50i_h6/platform.mk +++ b/plat/allwinner/sun50i_h6/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -7,4 +7,4 @@ # The differences between the platform are covered by the include files. include plat/allwinner/common/allwinner-common.mk -PLAT_BL_COMMON_SOURCES += drivers/mentor/i2c/mi2cv.c +BL31_SOURCES += drivers/mentor/i2c/mi2cv.c -- cgit v1.2.3 From 3bea03e7b4680c9c856256c18ce963af6c895822 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 21:28:18 -0500 Subject: allwinner: a64: power: Remove duplicate DT check should_enable_regulator() is already checked in the regulators subnode loop before setup_regulator() is called, so there's no need to check it again here. Signed-off-by: Samuel Holland Change-Id: Idb8b8a6e435246f4fb226bc84813449d80a0a977 --- plat/allwinner/sun50i_a64/sunxi_power.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index d14ced9dc..bd6c7eea0 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -203,9 +203,6 @@ static int setup_regulator(const void *fdt, int node, int mvolt; uint8_t regval; - if (!should_enable_regulator(fdt, node)) - return -ENOENT; - mvolt = fdt_get_regulator_millivolt(fdt, node); if (mvolt < reg->min_volt || mvolt > reg->max_volt) return -EINVAL; -- cgit v1.2.3 From 494c823361ea51cc46ee6afd4c8750575421e5a8 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 21:29:56 -0500 Subject: allwinner: a64: power: Remove obsolete register check As of a561e41bf1d2 ("allwinner: power: add enable switches for DCDC1/5") there are no longer regulators without an enable register provided. Since it seems reasonable that this will continue to be the case, drop the check. Signed-off-by: Samuel Holland Change-Id: Icd7ec26fc6450d053e6e6d855fc16229b1d65a39 --- plat/allwinner/sun50i_a64/sunxi_power.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index bd6c7eea0..6e84bf7db 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -212,8 +212,7 @@ static int setup_regulator(const void *fdt, int node, regval = ((regval - reg->split) / 2) + reg->split; axp_write(reg->volt_reg, regval); - if (reg->switch_reg < 0xff) - axp_setbits(reg->switch_reg, BIT(reg->switch_bit)); + axp_setbits(reg->switch_reg, BIT(reg->switch_bit)); INFO("PMIC: AXP803: %s voltage: %d.%03dV\n", reg->dt_name, mvolt / 1000, mvolt % 1000); -- cgit v1.2.3 From 79b8546507fc91bcb3f809c82e7f74aaf0dc7f65 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 21:58:39 -0500 Subject: allwinner: a64: power: Use fdt_for_each_subnode This simplifies the code a bit. Verified to produce the same binary. Signed-off-by: Samuel Holland Change-Id: Ie1ec1ce2ea39c46525840906826c90a8a7eff287 --- plat/allwinner/sun50i_a64/sunxi_power.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index 6e84bf7db..fb3783a8b 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -246,9 +246,7 @@ static void setup_axp803_rails(const void *fdt) } /* iterate over all regulators to find used ones */ - for (node = fdt_first_subnode(fdt, node); - node >= 0; - node = fdt_next_subnode(fdt, node)) { + fdt_for_each_subnode(node, fdt, node) { const struct axp_regulator *reg; const char *name; int length; -- cgit v1.2.3 From f6d9c4cafa6a74f29f7b305a71ef122d470ed03c Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 22:23:33 -0500 Subject: drivers: allwinner: axp: Add AXP805 support This adds the new regulator list, as well as changes to make the switch (equivalent to DC1SW on the AXP803) work on both PMICs. Signed-off-by: Samuel Holland Change-Id: I9a1eac8ddfc54b27096c10a8eebdd51aaf9b8311 --- drivers/allwinner/axp/axp805.c | 33 +++++++++++++++++++++++++++++++++ drivers/allwinner/axp/common.c | 30 ++++++++++++++++++------------ include/drivers/allwinner/axp.h | 1 + 3 files changed, 52 insertions(+), 12 deletions(-) create mode 100644 drivers/allwinner/axp/axp805.c diff --git a/drivers/allwinner/axp/axp805.c b/drivers/allwinner/axp/axp805.c new file mode 100644 index 000000000..8d029c0bd --- /dev/null +++ b/drivers/allwinner/axp/axp805.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +const uint8_t axp_chip_id = AXP805_CHIP_ID; +const char *const axp_compatible = "x-powers,axp805"; + +/* + * The "dcdcd" split changes the step size by a factor of 5, not 2; + * disallow values above the split to maintain accuracy. + */ +const struct axp_regulator axp_regulators[] = { + {"dcdca", 600, 1520, 10, 50, 0x12, 0x10, 0}, + {"dcdcb", 1000, 2550, 50, NA, 0x13, 0x10, 1}, + {"dcdcc", 600, 1520, 10, 50, 0x14, 0x10, 2}, + {"dcdcd", 600, 1500, 20, NA, 0x15, 0x10, 3}, + {"dcdce", 1100, 3400, 100, NA, 0x16, 0x10, 4}, + {"aldo1", 700, 3300, 100, NA, 0x17, 0x10, 5}, + {"aldo2", 700, 3300, 100, NA, 0x18, 0x10, 6}, + {"aldo3", 700, 3300, 100, NA, 0x19, 0x10, 7}, + {"bldo1", 700, 1900, 100, NA, 0x20, 0x11, 0}, + {"bldo2", 700, 1900, 100, NA, 0x21, 0x11, 1}, + {"bldo3", 700, 1900, 100, NA, 0x22, 0x11, 2}, + {"bldo4", 700, 1900, 100, NA, 0x23, 0x11, 3}, + {"cldo1", 700, 3300, 100, NA, 0x24, 0x11, 4}, + {"cldo2", 700, 4200, 100, 27, 0x25, 0x11, 5}, + {"cldo3", 700, 3300, 100, NA, 0x26, 0x11, 6}, + {} +}; diff --git a/drivers/allwinner/axp/common.c b/drivers/allwinner/axp/common.c index a021e1c9d..13437fec8 100644 --- a/drivers/allwinner/axp/common.c +++ b/drivers/allwinner/axp/common.c @@ -108,7 +108,7 @@ static bool should_enable_regulator(const void *fdt, int node) void axp_setup_regulators(const void *fdt) { int node; - bool dc1sw = false; + bool sw = false; if (fdt == NULL) return; @@ -120,6 +120,7 @@ void axp_setup_regulators(const void *fdt) return; } + /* This applies to AXP803 only. */ if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) { axp_clrbits(0x8f, BIT(4)); axp_setbits(0x30, BIT(2)); @@ -144,26 +145,31 @@ void axp_setup_regulators(const void *fdt) continue; name = fdt_get_name(fdt, node, &length); + + /* Enable the switch last to avoid overheating. */ + if (!strncmp(name, "dc1sw", length) || + !strncmp(name, "sw", length)) { + sw = true; + continue; + } + for (reg = axp_regulators; reg->dt_name; reg++) { if (!strncmp(name, reg->dt_name, length)) { setup_regulator(fdt, node, reg); break; } } - - if (!strncmp(name, "dc1sw", length)) { - /* Delay DC1SW enablement to avoid overheating. */ - dc1sw = true; - continue; - } } /* - * If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts - * down. So always enable DC1SW as the very last regulator. + * On the AXP803, if DLDO2 is enabled after DC1SW, the PMIC overheats + * and shuts down. So always enable DC1SW as the very last regulator. */ - if (dc1sw) { - INFO("PMIC: Enabling DC1SW\n"); - axp_setbits(0x12, BIT(7)); + if (sw) { + INFO("PMIC: Enabling DC SW\n"); + if (axp_chip_id == AXP803_CHIP_ID) + axp_setbits(0x12, BIT(7)); + if (axp_chip_id == AXP805_CHIP_ID) + axp_setbits(0x11, BIT(7)); } } diff --git a/include/drivers/allwinner/axp.h b/include/drivers/allwinner/axp.h index f3d6277cb..9c0035f96 100644 --- a/include/drivers/allwinner/axp.h +++ b/include/drivers/allwinner/axp.h @@ -13,6 +13,7 @@ enum { AXP803_CHIP_ID = 0x41, + AXP805_CHIP_ID = 0x40, }; struct axp_regulator { -- cgit v1.2.3 From 0bc752c9adedbda4434fddf68d3bc18c5274360b Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 20:50:57 -0500 Subject: allwinner: Convert AXP803 regulator setup code into a driver Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely independent. However, some H6 boards also need early regulator setup. Most of the register interface and all of the device tree traversal code can be reused between the AXP803 and AXP805. The main difference is the hardware bus interface, so that part is left to the platforms. The remainder is moved into a driver. I factored out the bits that were obviously specific to the AXP803; additional changes for compatibility with other PMICs can be made as needed. The only functional change is that rsb_init() now checks the PMIC's chip ID register against the expected value. This was already being done in the H6 version of the code. Signed-off-by: Samuel Holland Change-Id: Icdcf9edd6565f78cccc503922405129ac27e08a2 --- drivers/allwinner/axp/axp803.c | 22 ++++ drivers/allwinner/axp/common.c | 169 ++++++++++++++++++++++++++++++ include/drivers/allwinner/axp.h | 47 +++++++++ plat/allwinner/sun50i_a64/platform.mk | 4 +- plat/allwinner/sun50i_a64/sunxi_power.c | 177 ++------------------------------ 5 files changed, 252 insertions(+), 167 deletions(-) create mode 100644 drivers/allwinner/axp/axp803.c create mode 100644 drivers/allwinner/axp/common.c create mode 100644 include/drivers/allwinner/axp.h diff --git a/drivers/allwinner/axp/axp803.c b/drivers/allwinner/axp/axp803.c new file mode 100644 index 000000000..53b11c11a --- /dev/null +++ b/drivers/allwinner/axp/axp803.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +const uint8_t axp_chip_id = AXP803_CHIP_ID; +const char *const axp_compatible = "x-powers,axp803"; + +const struct axp_regulator axp_regulators[] = { + {"dcdc1", 1600, 3400, 100, NA, 0x20, 0x10, 0}, + {"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4}, + {"dcdc6", 600, 1520, 10, 50, 0x25, 0x10, 5}, + {"dldo1", 700, 3300, 100, NA, 0x15, 0x12, 3}, + {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4}, + {"dldo3", 700, 3300, 100, NA, 0x17, 0x12, 5}, + {"dldo4", 700, 3300, 100, NA, 0x18, 0x12, 6}, + {"fldo1", 700, 1450, 50, NA, 0x1c, 0x13, 2}, + {} +}; diff --git a/drivers/allwinner/axp/common.c b/drivers/allwinner/axp/common.c new file mode 100644 index 000000000..a021e1c9d --- /dev/null +++ b/drivers/allwinner/axp/common.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include + +int axp_check_id(void) +{ + int ret; + + ret = axp_read(0x03); + if (ret < 0) + return ret; + + ret &= 0xcf; + if (ret != axp_chip_id) { + ERROR("PMIC: Found unknown PMIC %02x\n", ret); + return ret; + } + + return 0; +} + +int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask) +{ + uint8_t val; + int ret; + + ret = axp_read(reg); + if (ret < 0) + return ret; + + val = (ret & ~clr_mask) | set_mask; + + return axp_write(reg, val); +} + +void axp_power_off(void) +{ + /* Set "power disable control" bit */ + axp_setbits(0x32, BIT(7)); +} + +/* + * Retrieve the voltage from a given regulator DTB node. + * Both the regulator-{min,max}-microvolt properties must be present and + * have the same value. Return that value in millivolts. + */ +static int fdt_get_regulator_millivolt(const void *fdt, int node) +{ + const fdt32_t *prop; + uint32_t min_volt; + + prop = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL); + if (prop == NULL) + return -EINVAL; + min_volt = fdt32_to_cpu(*prop); + + prop = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL); + if (prop == NULL) + return -EINVAL; + + if (fdt32_to_cpu(*prop) != min_volt) + return -EINVAL; + + return min_volt / 1000; +} + +static int setup_regulator(const void *fdt, int node, + const struct axp_regulator *reg) +{ + uint8_t val; + int mvolt; + + mvolt = fdt_get_regulator_millivolt(fdt, node); + if (mvolt < reg->min_volt || mvolt > reg->max_volt) + return -EINVAL; + + val = (mvolt / reg->step) - (reg->min_volt / reg->step); + if (val > reg->split) + val = ((val - reg->split) / 2) + reg->split; + + axp_write(reg->volt_reg, val); + axp_setbits(reg->switch_reg, BIT(reg->switch_bit)); + + INFO("PMIC: %s voltage: %d.%03dV\n", reg->dt_name, + mvolt / 1000, mvolt % 1000); + + return 0; +} + +static bool should_enable_regulator(const void *fdt, int node) +{ + if (fdt_getprop(fdt, node, "phandle", NULL) != NULL) + return true; + if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL) + return true; + return false; +} + +void axp_setup_regulators(const void *fdt) +{ + int node; + bool dc1sw = false; + + if (fdt == NULL) + return; + + /* locate the PMIC DT node, bail out if not found */ + node = fdt_node_offset_by_compatible(fdt, -1, axp_compatible); + if (node < 0) { + WARN("PMIC: No PMIC DT node, skipping setup\n"); + return; + } + + if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) { + axp_clrbits(0x8f, BIT(4)); + axp_setbits(0x30, BIT(2)); + INFO("PMIC: Enabling DRIVEVBUS\n"); + } + + /* descend into the "regulators" subnode */ + node = fdt_subnode_offset(fdt, node, "regulators"); + if (node < 0) { + WARN("PMIC: No regulators DT node, skipping setup\n"); + return; + } + + /* iterate over all regulators to find used ones */ + fdt_for_each_subnode(node, fdt, node) { + const struct axp_regulator *reg; + const char *name; + int length; + + /* We only care if it's always on or referenced. */ + if (!should_enable_regulator(fdt, node)) + continue; + + name = fdt_get_name(fdt, node, &length); + for (reg = axp_regulators; reg->dt_name; reg++) { + if (!strncmp(name, reg->dt_name, length)) { + setup_regulator(fdt, node, reg); + break; + } + } + + if (!strncmp(name, "dc1sw", length)) { + /* Delay DC1SW enablement to avoid overheating. */ + dc1sw = true; + continue; + } + } + + /* + * If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts + * down. So always enable DC1SW as the very last regulator. + */ + if (dc1sw) { + INFO("PMIC: Enabling DC1SW\n"); + axp_setbits(0x12, BIT(7)); + } +} diff --git a/include/drivers/allwinner/axp.h b/include/drivers/allwinner/axp.h new file mode 100644 index 000000000..f3d6277cb --- /dev/null +++ b/include/drivers/allwinner/axp.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AXP_H +#define AXP_H + +#include + +#define NA 0xff + +enum { + AXP803_CHIP_ID = 0x41, +}; + +struct axp_regulator { + const char *dt_name; + uint16_t min_volt; + uint16_t max_volt; + uint16_t step; + unsigned char split; + unsigned char volt_reg; + unsigned char switch_reg; + unsigned char switch_bit; +}; + +extern const uint8_t axp_chip_id; +extern const char *const axp_compatible; +extern const struct axp_regulator axp_regulators[]; + +/* + * Since the PMIC can be connected to multiple bus types, + * low-level read/write functions must be provided by the platform + */ +int axp_read(uint8_t reg); +int axp_write(uint8_t reg, uint8_t val); +int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask); +#define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0) +#define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask) + +int axp_check_id(void); +void axp_power_off(void); +void axp_setup_regulators(const void *fdt); + +#endif /* AXP_H */ diff --git a/plat/allwinner/sun50i_a64/platform.mk b/plat/allwinner/sun50i_a64/platform.mk index 17bdf63f3..a76a679ed 100644 --- a/plat/allwinner/sun50i_a64/platform.mk +++ b/plat/allwinner/sun50i_a64/platform.mk @@ -7,4 +7,6 @@ # The differences between the platform are covered by the include files. include plat/allwinner/common/allwinner-common.mk -BL31_SOURCES += drivers/allwinner/sunxi_rsb.c +BL31_SOURCES += drivers/allwinner/axp/axp803.c \ + drivers/allwinner/axp/common.c \ + drivers/allwinner/sunxi_rsb.c diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index fb3783a8b..5b7d76ae9 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -7,14 +7,11 @@ #include -#include - #include -#include #include +#include #include -#include #include #include @@ -114,170 +111,22 @@ static int rsb_init(void) return ret; /* Associate the 8-bit runtime address with the 12-bit bus address. */ - return rsb_assign_runtime_address(AXP803_HW_ADDR, - AXP803_RT_ADDR); -} - -static int axp_write(uint8_t reg, uint8_t val) -{ - return rsb_write(AXP803_RT_ADDR, reg, val); -} - -static int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask) -{ - uint8_t regval; - int ret; - - ret = rsb_read(AXP803_RT_ADDR, reg); - if (ret < 0) + ret = rsb_assign_runtime_address(AXP803_HW_ADDR, + AXP803_RT_ADDR); + if (ret) return ret; - regval = (ret & ~clr_mask) | set_mask; - - return rsb_write(AXP803_RT_ADDR, reg, regval); + return axp_check_id(); } -#define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0) -#define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask) - -static bool should_enable_regulator(const void *fdt, int node) +int axp_read(uint8_t reg) { - if (fdt_getprop(fdt, node, "phandle", NULL) != NULL) - return true; - if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL) - return true; - return false; + return rsb_read(AXP803_RT_ADDR, reg); } -/* - * Retrieve the voltage from a given regulator DTB node. - * Both the regulator-{min,max}-microvolt properties must be present and - * have the same value. Return that value in millivolts. - */ -static int fdt_get_regulator_millivolt(const void *fdt, int node) +int axp_write(uint8_t reg, uint8_t val) { - const fdt32_t *prop; - uint32_t min_volt; - - prop = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL); - if (prop == NULL) - return -EINVAL; - min_volt = fdt32_to_cpu(*prop); - - prop = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL); - if (prop == NULL) - return -EINVAL; - - if (fdt32_to_cpu(*prop) != min_volt) - return -EINVAL; - - return min_volt / 1000; -} - -#define NO_SPLIT 0xff - -static const struct axp_regulator { - char *dt_name; - uint16_t min_volt; - uint16_t max_volt; - uint16_t step; - unsigned char split; - unsigned char volt_reg; - unsigned char switch_reg; - unsigned char switch_bit; -} regulators[] = { - {"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0x10, 0}, - {"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4}, - {"dcdc6", 600, 1520, 10, 50, 0x25, 0x10, 5}, - {"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3}, - {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4}, - {"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5}, - {"dldo4", 700, 3300, 100, NO_SPLIT, 0x18, 0x12, 6}, - {"fldo1", 700, 1450, 50, NO_SPLIT, 0x1c, 0x13, 2}, - {} -}; - -static int setup_regulator(const void *fdt, int node, - const struct axp_regulator *reg) -{ - int mvolt; - uint8_t regval; - - mvolt = fdt_get_regulator_millivolt(fdt, node); - if (mvolt < reg->min_volt || mvolt > reg->max_volt) - return -EINVAL; - - regval = (mvolt / reg->step) - (reg->min_volt / reg->step); - if (regval > reg->split) - regval = ((regval - reg->split) / 2) + reg->split; - - axp_write(reg->volt_reg, regval); - axp_setbits(reg->switch_reg, BIT(reg->switch_bit)); - - INFO("PMIC: AXP803: %s voltage: %d.%03dV\n", reg->dt_name, - mvolt / 1000, mvolt % 1000); - - return 0; -} - -static void setup_axp803_rails(const void *fdt) -{ - int node; - bool dc1sw = false; - - /* locate the PMIC DT node, bail out if not found */ - node = fdt_node_offset_by_compatible(fdt, -1, "x-powers,axp803"); - if (node < 0) { - WARN("PMIC: No PMIC DT node, skipping setup\n"); - return; - } - - if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) { - axp_clrbits(0x8f, BIT(4)); - axp_setbits(0x30, BIT(2)); - INFO("PMIC: AXP803: Enabling DRIVEVBUS\n"); - } - - /* descend into the "regulators" subnode */ - node = fdt_subnode_offset(fdt, node, "regulators"); - if (node < 0) { - WARN("PMIC: No regulators DT node, skipping setup\n"); - return; - } - - /* iterate over all regulators to find used ones */ - fdt_for_each_subnode(node, fdt, node) { - const struct axp_regulator *reg; - const char *name; - int length; - - /* We only care if it's always on or referenced. */ - if (!should_enable_regulator(fdt, node)) - continue; - - name = fdt_get_name(fdt, node, &length); - for (reg = regulators; reg->dt_name; reg++) { - if (!strncmp(name, reg->dt_name, length)) { - setup_regulator(fdt, node, reg); - break; - } - } - - if (!strncmp(name, "dc1sw", length)) { - /* Delay DC1SW enablement to avoid overheating. */ - dc1sw = true; - continue; - } - } - - /* - * If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts - * down. So always enable DC1SW as the very last regulator. - */ - if (dc1sw) { - INFO("PMIC: AXP803: Enabling DC1SW\n"); - axp_setbits(0x12, BIT(7)); - } + return rsb_write(AXP803_RT_ADDR, reg, val); } int sunxi_pmic_setup(uint16_t socid, const void *fdt) @@ -305,9 +154,7 @@ int sunxi_pmic_setup(uint16_t socid, const void *fdt) return ret; pmic = AXP803_RSB; - - if (fdt) - setup_axp803_rails(fdt); + axp_setup_regulators(fdt); break; default: @@ -354,9 +201,7 @@ void sunxi_power_down(void) /* (Re-)init RSB in case the rich OS has disabled it. */ sunxi_init_platform_r_twi(SUNXI_SOC_A64, true); rsb_init(); - - /* Set "power disable control" bit */ - axp_setbits(0x32, BIT(7)); + axp_power_off(); break; default: break; -- cgit v1.2.3 From fb23b104c06d29206864e905eedea48518ec5e47 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 20 Oct 2019 21:34:38 -0500 Subject: allwinner: h6: power: Switch to using the AXP driver Chip ID checking and poweroff work just like they did before. Regulators are now enabled just like on A64/H5. This changes the signatures of the low-level register read/write functions to match the interface expected by the common driver. Signed-off-by: Samuel Holland Change-Id: I14d63d171a094fa1375904928270fa3e21761646 --- plat/allwinner/common/allwinner-common.mk | 5 +++-- plat/allwinner/sun50i_a64/platform.mk | 1 - plat/allwinner/sun50i_h6/platform.mk | 3 ++- plat/allwinner/sun50i_h6/sunxi_power.c | 36 +++++++++++++------------------ 4 files changed, 20 insertions(+), 25 deletions(-) diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk index 6866bd65a..5e8885d7a 100644 --- a/plat/allwinner/common/allwinner-common.mk +++ b/plat/allwinner/common/allwinner-common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -20,7 +20,8 @@ PLAT_BL_COMMON_SOURCES := drivers/ti/uart/${ARCH}/16550_console.S \ ${AW_PLAT}/common/plat_helpers.S \ ${AW_PLAT}/common/sunxi_common.c -BL31_SOURCES += drivers/arm/gic/common/gic_common.c \ +BL31_SOURCES += drivers/allwinner/axp/common.c \ + drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_helpers.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/delay_timer/delay_timer.c \ diff --git a/plat/allwinner/sun50i_a64/platform.mk b/plat/allwinner/sun50i_a64/platform.mk index a76a679ed..f6d5aa9f8 100644 --- a/plat/allwinner/sun50i_a64/platform.mk +++ b/plat/allwinner/sun50i_a64/platform.mk @@ -8,5 +8,4 @@ include plat/allwinner/common/allwinner-common.mk BL31_SOURCES += drivers/allwinner/axp/axp803.c \ - drivers/allwinner/axp/common.c \ drivers/allwinner/sunxi_rsb.c diff --git a/plat/allwinner/sun50i_h6/platform.mk b/plat/allwinner/sun50i_h6/platform.mk index fa1b0e598..4ecc57cf0 100644 --- a/plat/allwinner/sun50i_h6/platform.mk +++ b/plat/allwinner/sun50i_h6/platform.mk @@ -7,4 +7,5 @@ # The differences between the platform are covered by the include files. include plat/allwinner/common/allwinner-common.mk -BL31_SOURCES += drivers/mentor/i2c/mi2cv.c +BL31_SOURCES += drivers/allwinner/axp/axp805.c \ + drivers/mentor/i2c/mi2cv.c diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c index 7bb266b88..443015bac 100644 --- a/plat/allwinner/sun50i_h6/sunxi_power.c +++ b/plat/allwinner/sun50i_h6/sunxi_power.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -19,31 +20,33 @@ #include #define AXP805_ADDR 0x36 -#define AXP805_ID 0x03 static enum pmic_type { UNKNOWN, AXP805, } pmic; -int axp_i2c_read(uint8_t chip, uint8_t reg, uint8_t *val) +int axp_read(uint8_t reg) { + uint8_t val; int ret; - ret = i2c_write(chip, 0, 0, ®, 1); + ret = i2c_write(AXP805_ADDR, 0, 0, ®, 1); if (ret == 0) - ret = i2c_read(chip, 0, 0, val, 1); - if (ret) + ret = i2c_read(AXP805_ADDR, 0, 0, &val, 1); + if (ret) { ERROR("PMIC: Cannot read AXP805 register %02x\n", reg); + return ret; + } - return ret; + return val; } -int axp_i2c_write(uint8_t chip, uint8_t reg, uint8_t val) +int axp_write(uint8_t reg, uint8_t val) { int ret; - ret = i2c_write(chip, reg, 1, &val, 1); + ret = i2c_write(AXP805_ADDR, reg, 1, &val, 1); if (ret) ERROR("PMIC: Cannot write AXP805 register %02x\n", reg); @@ -53,23 +56,16 @@ int axp_i2c_write(uint8_t chip, uint8_t reg, uint8_t val) static int axp805_probe(void) { int ret; - uint8_t val; /* Switch the AXP805 to master/single-PMIC mode. */ - ret = axp_i2c_write(AXP805_ADDR, 0xff, 0x0); + ret = axp_write(0xff, 0x0); if (ret) return ret; - ret = axp_i2c_read(AXP805_ADDR, AXP805_ID, &val); + ret = axp_check_id(); if (ret) return ret; - val &= 0xcf; - if (val != 0x40) { - ERROR("PMIC: Found unknown PMIC %02x\n", val); - return -EINVAL; - } - return 0; } @@ -91,22 +87,20 @@ int sunxi_pmic_setup(uint16_t socid, const void *fdt) return ret; pmic = AXP805; + axp_setup_regulators(fdt); return 0; } void sunxi_power_down(void) { - uint8_t val; - switch (pmic) { case AXP805: /* Re-initialise after rich OS might have used it. */ sunxi_init_platform_r_twi(SUNXI_SOC_H6, false); /* initialise mi2cv driver */ i2c_init((void *)SUNXI_R_I2C_BASE); - axp_i2c_read(AXP805_ADDR, 0x32, &val); - axp_i2c_write(AXP805_ADDR, 0x32, val | 0x80); + axp_power_off(); break; default: break; -- cgit v1.2.3 From 11a96e0ea04f4b2c53e6431f690d7912bb645552 Mon Sep 17 00:00:00 2001 From: Justin Chadwell Date: Wed, 18 Sep 2019 14:47:19 +0100 Subject: Remove -Wpadded warning -Wpadded warns whenever the C compiler automatically includes any padding in a structure. Because TF-A has a large number of structures, this occurs fairly frequently and is incredibly verbose, and as such is unlikely to ever be fixed. The utility of this warning is also extremely limited - knowing that a structure includes padding does not point to the existence of an error, and is probably quite unlikely to indicate actually buggy behaviour. Therefore, it's probably best to keep this warning off at all times. Change-Id: I0797cb75f06b4fea0d2fdc16fd5ad978a31d76ec Signed-off-by: Justin Chadwell --- Makefile | 1 - docs/process/security-hardening.rst | 7 +++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index ef3ee4b53..b9584ca98 100644 --- a/Makefile +++ b/Makefile @@ -261,7 +261,6 @@ WARNING3 := -Wbad-function-cast WARNING3 += -Wcast-qual WARNING3 += -Wconversion WARNING3 += -Wpacked -WARNING3 += -Wpadded WARNING3 += -Wpointer-arith WARNING3 += -Wredundant-decls WARNING3 += -Wswitch-default diff --git a/docs/process/security-hardening.rst b/docs/process/security-hardening.rst index 49678719f..a18a79203 100644 --- a/docs/process/security-hardening.rst +++ b/docs/process/security-hardening.rst @@ -30,9 +30,8 @@ Several build options can be used to check for security issues. Refer to the - W=1 - Adds ``Wextra``, ``Wmissing-declarations``, ``Wmissing-format-attribute``, - ``Wmissing-prototypes``, ``Wold-style-definition`` and - ``Wunused-const-variable``. + Adds ``Wextra``, ``Wmissing-format-attribute``, ``Wmissing-prototypes``, + ``Wold-style-definition`` and ``Wunused-const-variable``. - W=2 @@ -42,7 +41,7 @@ Several build options can be used to check for security issues. Refer to the - W=3 Adds ``Wbad-function-cast``, ``Wcast-qual``, ``Wconversion``, ``Wpacked``, - ``Wpadded``, ``Wpointer-arith``, ``Wredundant-decls`` and + ``Wpointer-arith``, ``Wredundant-decls`` and ``Wswitch-default``. Refer to the GCC or Clang documentation for more information on the individual -- cgit v1.2.3 From 01534e85630fca1997aec86280a83e094789832e Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Mon, 16 Dec 2019 11:49:13 +0100 Subject: Update list of main maintainers Change-Id: Ia4faf873f8946992737f76870ac92bc5cb3f4020 Signed-off-by: Sandrine Bailleux --- docs/about/maintainers.rst | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst index 68f84ea57..d9d7f84fd 100644 --- a/docs/about/maintainers.rst +++ b/docs/about/maintainers.rst @@ -17,10 +17,18 @@ Main maintainers :G: `sandrine-bailleux-arm`_ :M: Alexei Fedorov :G: `AlexeiFedorov`_ -:M: Paul Beesley -:G: `pbeesley-arm`_ :M: György Szing :G: `gyuri-szing`_ +:M: Manish Pandey +:G: `manish-pandey-arm`_ +:M: Mark Dykes +:G: `mardyk01`_ +:M: Olivier Deprez +:G: `odeprez`_ +:M: Bipin Ravi +:G: `bipinravi-arm`_ +:M: Joanna Farley +:G: `joannafarley-arm`_ Allwinner ARMv8 platform port ----------------------------- @@ -300,7 +308,6 @@ Xilinx platform port .. _mtk09422: https://github.com/mtk09422 .. _niej: https://github.com/niej .. _npoushin: https://github.com/npoushin -.. _pbeesley-arm: https://github.com/pbeesley-arm .. _qoriq-open-source: https://github.com/qoriq-open-source .. _remi-triplefault: https://github.com/repk .. _rockchip-linux: https://github.com/rockchip-linux @@ -314,3 +321,8 @@ Xilinx platform port .. _TonyXie06: https://github.com/TonyXie06 .. _vwadekar: https://github.com/vwadekar .. _Yann-lms: https://github.com/Yann-lms +.. _manish-pandey-arm: https://github.com/manish-pandey-arm +.. _mardyk01: https://github.com/mardyk01 +.. _odeprez: https://github.com/odeprez +.. _bipinravi-arm: https://github.com/bipinravi-arm +.. _joannafarley-arm: https://github.com/joannafarley-arm -- cgit v1.2.3 From ae4a90f2ae5043bd157b0dffd8c40b840017b349 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bence=20Sz=C3=A9pk=C3=BAti?= Date: Mon, 16 Dec 2019 14:57:40 +0100 Subject: libc: Fix SIZE_MAX on AArch32 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SIZE_MAX was mistakenly redefined from UINT32_MAX to UINT64_MAX on AArch32 when the arch-specific headers were merged. This value is not currently used by upstream TF-A source code, so no functionality should be affected. Change-Id: I2acf7f8736423697c7377e8ed4b08843ced26e66 Signed-off-by: Bence Szépkúti --- include/lib/libc/stdint.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/lib/libc/stdint.h b/include/lib/libc/stdint.h index 80b3e965d..818870e16 100644 --- a/include/lib/libc/stdint.h +++ b/include/lib/libc/stdint.h @@ -72,7 +72,7 @@ #define PTRDIFF_MIN LONG_MIN #define PTRDIFF_MAX LONG_MAX -#define SIZE_MAX UINT64_MAX +#define SIZE_MAX ULONG_MAX #define INT8_C(x) x #define INT16_C(x) x -- cgit v1.2.3 From c6ee020ea2c7d416d269e92fbb841f8db424ea0f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 8 Oct 2019 16:15:56 +0200 Subject: rockchip: bring TZRAM_SIZE values in line The agreed upon division of early boot locations is 0x40000 for bl31 to leave enough room for u-boot-spl and 0x100000 for bl33 (u-boot). rk3288 and rk3399 already correctly secure the ddr up to the 1MB boundary so pull the other platforms along to also give the Rockchip TF-A enough room to comfortably live in. Signed-off-by: Heiko Stuebner Change-Id: Ie9e0c927d3074a418b6fd23b599d2ed7c15c8c6f --- plat/rockchip/px30/include/platform_def.h | 4 ++-- plat/rockchip/rk3328/include/platform_def.h | 6 +++--- plat/rockchip/rk3368/include/platform_def.h | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/plat/rockchip/px30/include/platform_def.h b/plat/rockchip/px30/include/platform_def.h index 9dccab82b..2f4f672a0 100644 --- a/plat/rockchip/px30/include/platform_def.h +++ b/plat/rockchip/px30/include/platform_def.h @@ -69,9 +69,9 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF text, ro, rw, Size: 512KB */ +/* TF text, ro, rw, Size: 1MB */ #define TZRAM_BASE (0x0) -#define TZRAM_SIZE (0x80000) +#define TZRAM_SIZE (0x100000) /******************************************************************************* * BL31 specific defines. diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h index baac12d3b..e9eb3fafb 100644 --- a/plat/rockchip/rk3328/include/platform_def.h +++ b/plat/rockchip/rk3328/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -66,9 +66,9 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF text, ro, rw, Size: 512KB */ +/* TF text, ro, rw, Size: 1MB */ #define TZRAM_BASE (0x0) -#define TZRAM_SIZE (0x80000) +#define TZRAM_SIZE (0x100000) /******************************************************************************* * BL31 specific defines. diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h index 9334a83ae..2abd56b0b 100644 --- a/plat/rockchip/rk3368/include/platform_def.h +++ b/plat/rockchip/rk3368/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,9 +67,9 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF text, ro, rw, Size: 512KB */ +/* TF text, ro, rw, Size: 1MB */ #define TZRAM_BASE (0x0) -#define TZRAM_SIZE (0x80000) +#define TZRAM_SIZE (0x100000) /******************************************************************************* * BL31 specific defines. -- cgit v1.2.3 From 7f0b2e78e0ca4ce686ac632170073f924e34c5a3 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 9 Oct 2019 14:39:44 +0200 Subject: rockchip: really use base+size for secure ddr regions The calls to secure ddr regions on rk3288 and rk3399 use parameters of base and size - as it custom for specifying memory regions, but the functions themself expect start and endpoints of the area. This only works by chance for the TZRAM, as it starts a 0x0 and therefore its end location is the same as its size. To not fall into a trap later on adapt the functions to really take base+size parameters. Signed-off-by: Heiko Stuebner Change-Id: Idb9fab38aa081f3335a4eca971e7b7f6757fbbab --- plat/rockchip/rk3288/drivers/secure/secure.c | 11 +++++++---- plat/rockchip/rk3399/drivers/secure/secure.c | 7 +++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/plat/rockchip/rk3288/drivers/secure/secure.c b/plat/rockchip/rk3288/drivers/secure/secure.c index 68994e458..25e1cca48 100644 --- a/plat/rockchip/rk3288/drivers/secure/secure.c +++ b/plat/rockchip/rk3288/drivers/secure/secure.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -38,15 +38,18 @@ static void sgrf_ddr_rgn_global_bypass(uint32_t bypass) * SGRF_SOC_CON21 - end address of the RGN_7 + RGN_X control * * @rgn - the DDR regions 0 ~ 7 which are can be configured. - * The @st and @ed indicate the start and end addresses for which to set - * the security, and the unit is byte. When the st_mb == 0, ed_mb == 0, the + * @st - start address to set as secure + * @sz - length of area to set as secure + * The @st_mb and @ed_mb indicate the start and end addresses for which to set + * the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the * address range 0x0 ~ 0xfffff is secure. * * For example, if we would like to set the range [0, 32MB) is security via * DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31. */ -static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, uintptr_t ed) +static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, size_t sz) { + uintptr_t ed = st + sz; uintptr_t st_mb, ed_mb; assert(rgn <= 7); diff --git a/plat/rockchip/rk3399/drivers/secure/secure.c b/plat/rockchip/rk3399/drivers/secure/secure.c index 8286f17c6..13c83ca1f 100644 --- a/plat/rockchip/rk3399/drivers/secure/secure.c +++ b/plat/rockchip/rk3399/drivers/secure/secure.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -45,6 +45,8 @@ static void sgrf_ddr_rgn_global_bypass(uint32_t bypass) * bypass, 1: enable bypass * * @rgn - the DDR regions 0 ~ 7 which are can be configured. + * @st - start address to set as secure + * @sz - length of area to set as secure * The @st_mb and @ed_mb indicate the start and end addresses for which to set * the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the * address range 0x0 ~ 0xfffff is secure. @@ -53,8 +55,9 @@ static void sgrf_ddr_rgn_global_bypass(uint32_t bypass) * DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31. */ static void sgrf_ddr_rgn_config(uint32_t rgn, - uintptr_t st, uintptr_t ed) + uintptr_t st, size_t sz) { + uintptr_t ed = st + sz; uintptr_t st_mb, ed_mb; assert(rgn <= 7); -- cgit v1.2.3 From d25041bf1e1b2a59b723f07c697447415bd42d0a Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 22 Oct 2019 10:31:45 +0800 Subject: intel: Create SiP service header file Separate SiP related definition from mailbox header file Signed-off-by: Hadi Asyrafi Change-Id: I45ba540f29d9261007f7ec23469358747cf140b4 --- plat/intel/soc/common/include/socfpga_mailbox.h | 21 ------------ plat/intel/soc/common/include/socfpga_sip_svc.h | 45 +++++++++++++++++++++++++ plat/intel/soc/common/socfpga_sip_svc.c | 1 + 3 files changed, 46 insertions(+), 21 deletions(-) create mode 100644 plat/intel/soc/common/include/socfpga_sip_svc.h diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index db4c84104..1ba09bc06 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -84,32 +84,11 @@ #define SOFTFUNC_STATUS_CONF_DONE (1 << 0) #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 -/* SMC function IDs for SiP Service queries */ -#define SIP_SVC_CALL_COUNT 0x8200ff00 -#define SIP_SVC_UID 0x8200ff01 -#define SIP_SVC_VERSION 0x8200ff03 - -/* SiP Service Calls version numbers */ -#define SIP_SVC_VERSION_MAJOR 0 -#define SIP_SVC_VERSION_MINOR 1 - /* Mailbox reconfiguration commands */ #define MBOX_RECONFIG 6 #define MBOX_RECONFIG_DATA 8 #define MBOX_RECONFIG_STATUS 9 -/* Sip get memory */ -#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 -#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 -#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 -#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 -#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 -#define INTEL_SIP_SMC_STATUS_OK 0 -#define INTEL_SIP_SMC_STATUS_ERROR 0x4 -#define INTEL_SIP_SMC_STATUS_BUSY 0x1 -#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 -#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x1000 -#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216 void mailbox_set_int(int interrupt_input); int mailbox_init(void); diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h new file mode 100644 index 000000000..33e7e1bcd --- /dev/null +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOCFPGA_SIP_SVC_H +#define SOCFPGA_SIP_SVC_H + + +/* SiP status response */ +#define INTEL_SIP_SMC_STATUS_OK 0 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 + +/* SMC SiP service function identifier */ +#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 +#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 +#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 +#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 +#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 +#define INTEL_SIP_SMC_REG_READ 0xC2000007 +#define INTEL_SIP_SMC_REG_WRITE 0xC2000008 +#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009 +#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B +#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C +#define INTEL_SIP_LEGACY_SMC_ECC_DBE 0xC200000D +#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E +#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F + +/* FPGA config helpers */ +#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x1000 +#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216 + +/* SMC function IDs for SiP Service queries */ +#define SIP_SVC_CALL_COUNT 0x8200ff00 +#define SIP_SVC_UID 0x8200ff01 +#define SIP_SVC_VERSION 0x8200ff03 + +/* SiP Service Calls version numbers */ +#define SIP_SVC_VERSION_MAJOR 0 +#define SIP_SVC_VERSION_MINOR 1 + +#endif /* SOCFPGA_SIP_SVC_H */ diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 88750d771..61218ebed 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -10,6 +10,7 @@ #include #include "socfpga_mailbox.h" +#include "socfpga_sip_svc.h" /* Number of SiP Calls implemented */ #define SIP_NUM_CALLS 0x3 -- cgit v1.2.3 From ec7d0055c955f60189d6a2063bdffa132b7ad0c0 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Mon, 21 Oct 2019 16:25:07 +0800 Subject: intel: Modify mailbox's get_config_status Move the get_config_status out of sip_svc driver. Modify the function so that it can return either CONFIG_STATUS or RECONFIG_STATUS Signed-off-by: Hadi Asyrafi Change-Id: I642d5900339e67f98be61380edc2b838e0dd47af --- plat/intel/soc/common/include/socfpga_mailbox.h | 2 ++ plat/intel/soc/common/soc/socfpga_mailbox.c | 29 +++++++++++++++++++++++++ plat/intel/soc/common/socfpga_sip_svc.c | 29 +------------------------ 3 files changed, 32 insertions(+), 28 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 1ba09bc06..399ac57b8 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -85,6 +85,7 @@ #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 /* Mailbox reconfiguration commands */ +#define MBOX_CONFIG_STATUS 4 #define MBOX_RECONFIG 6 #define MBOX_RECONFIG_DATA 8 #define MBOX_RECONFIG_STATUS 9 @@ -102,5 +103,6 @@ void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, int mailbox_read_response(int job_id, uint32_t *response); int mailbox_get_qspi_clock(void); void mailbox_reset_cold(void); +uint32_t intel_mailbox_get_config_status(uint32_t cmd); #endif /* SOCFPGA_MBOX_H */ diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 27838bfe7..b972c445e 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -8,6 +8,7 @@ #include #include "socfpga_mailbox.h" +#include "socfpga_sip_svc.h" static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, int len) @@ -278,3 +279,31 @@ int mailbox_init(void) return 0; } +uint32_t intel_mailbox_get_config_status(uint32_t cmd) +{ + uint32_t status, res; + uint32_t response[6]; + + status = mailbox_send_cmd(1, cmd, NULL, 0, 0, response); + + if (status < 0) + return INTEL_SIP_SMC_STATUS_ERROR; + + res = response[RECONFIG_STATUS_STATE]; + if (res && res != MBOX_CFGSTAT_STATE_CONFIG) + return INTEL_SIP_SMC_STATUS_ERROR; + + res = response[RECONFIG_STATUS_PIN_STATUS]; + if (!(res & PIN_STATUS_NSTATUS)) + return INTEL_SIP_SMC_STATUS_ERROR; + + res = response[RECONFIG_STATUS_SOFTFUNC_STATUS]; + if (res & SOFTFUNC_STATUS_SEU_ERROR) + return INTEL_SIP_SMC_STATUS_ERROR; + + if ((res & SOFTFUNC_STATUS_CONF_DONE) && + (res & SOFTFUNC_STATUS_INIT_DONE)) + return INTEL_SIP_SMC_STATUS_OK; + + return MBOX_CFGSTAT_STATE_CONFIG; +} diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 61218ebed..421fa44e3 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -100,34 +100,7 @@ static int intel_fpga_sdm_write_all(void) uint32_t intel_mailbox_fpga_config_isdone(void) { - uint32_t args[2]; - uint32_t response[6]; - int status; - - status = mailbox_send_cmd(1, MBOX_RECONFIG_STATUS, args, 0, 0, - response); - - if (status < 0) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (response[RECONFIG_STATUS_STATE] && - response[RECONFIG_STATUS_STATE] != MBOX_CFGSTAT_STATE_CONFIG) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (!(response[RECONFIG_STATUS_PIN_STATUS] & PIN_STATUS_NSTATUS)) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_SEU_ERROR) - return INTEL_SIP_SMC_STATUS_ERROR; - - if ((response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_CONF_DONE) && - (response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_INIT_DONE)) - return INTEL_SIP_SMC_STATUS_OK; - - return INTEL_SIP_SMC_STATUS_ERROR; + return intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); } static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) -- cgit v1.2.3 From 2db1e7663db8f94986bea02ade171693abfbdee6 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 22 Oct 2019 12:59:32 +0800 Subject: intel: stratix10: Enable uboot entrypoint support This patch will provide an entrypoint for uboot's spl into BL31. BL31 will also handle secondary cpu state during uboot's cold boot Signed-off-by: Hadi Asyrafi Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3 --- plat/intel/soc/common/aarch64/plat_helpers.S | 14 +++++++++++++- plat/intel/soc/common/include/platform_def.h | 3 +++ plat/intel/soc/common/include/socfpga_private.h | 1 + plat/intel/soc/stratix10/bl31_plat_setup.c | 4 ++++ 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S index 00fe2d999..27b538a4f 100644 --- a/plat/intel/soc/common/aarch64/plat_helpers.S +++ b/plat/intel/soc/common/aarch64/plat_helpers.S @@ -8,6 +8,7 @@ #include #include #include +#include .globl plat_secondary_cold_boot_setup .globl platform_is_primary_cpu @@ -17,6 +18,7 @@ .globl plat_crash_console_putc .globl plat_crash_console_flush .globl platform_mem_init + .globl plat_secondary_cpus_bl31_entry .globl plat_get_my_entrypoint @@ -33,7 +35,6 @@ func plat_secondary_cold_boot_setup /* Wait until the it gets reset signal from rstmgr gets populated */ poll_mailbox: wfi - mov_imm x0, PLAT_SEC_ENTRY ldr x1, [x0] mov_imm x2, PLAT_CPUID_RELEASE @@ -114,3 +115,14 @@ func platform_mem_init mov x0, #0 ret endfunc platform_mem_init + +func plat_secondary_cpus_bl31_entry + el3_entrypoint_common \ + _init_sctlr=0 \ + _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ + _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ + _init_memory=1 \ + _init_c_runtime=1 \ + _exception_vectors=runtime_exceptions \ + _pie_fixup_size=BL31_LIMIT - BL31_BASE +endfunc plat_secondary_cpus_bl31_entry diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index e57aafb6a..12dd49911 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -19,6 +19,9 @@ #define PLAT_CPUID_RELEASE 0xffe1b000 #define PLAT_SEC_ENTRY 0xffe1b008 +/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ +#define PLAT_CPU_RELEASE_ADDR 0xffd12210 + /* Define next boot image name and offset */ #define PLAT_NS_IMAGE_OFFSET 0x50000 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h index 375484443..ca38f62d8 100644 --- a/plat/intel/soc/common/include/socfpga_private.h +++ b/plat/intel/soc/common/include/socfpga_private.h @@ -61,5 +61,6 @@ uint32_t socfpga_get_spsr_for_bl33_entry(void); unsigned long socfpga_get_ns_image_entrypoint(void); +void plat_secondary_cpus_bl31_entry(void); #endif /* SOCFPGA_PRIVATE_H */ diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index a133f82cb..98ab35e7f 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -100,6 +100,10 @@ void bl31_platform_setup(void) gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); + + /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ + mmio_write_64(PLAT_CPU_RELEASE_ADDR, + (uint64_t)plat_secondary_cpus_bl31_entry); } const mmap_region_t plat_stratix10_mmap[] = { -- cgit v1.2.3 From cf82aff09801e3f66dc355faa434dae83e031cba Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 22 Oct 2019 13:39:14 +0800 Subject: intel: Modify BL31 address mapping Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use of On-Chip RAM for BL31 specific variables filling down from handoff offset to reduce fragmentation Signed-off-by: Hadi Asyrafi Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099 --- plat/intel/soc/common/include/platform_def.h | 28 +++++++++++++++------------- plat/intel/soc/common/socfpga_psci.c | 8 +++----- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index 12dd49911..e91995f9a 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -16,9 +16,6 @@ #define PLAT_SOCFPGA_STRATIX10 1 #define PLAT_SOCFPGA_AGILEX 2 -#define PLAT_CPUID_RELEASE 0xffe1b000 -#define PLAT_SEC_ENTRY 0xffe1b008 - /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ #define PLAT_CPU_RELEASE_ADDR 0xffd12210 @@ -109,19 +106,24 @@ */ -#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define BL1_RO_BASE (0xffe00000) +#define BL1_RO_LIMIT (0xffe0f000) +#define BL1_RW_BASE (0xffe10000) +#define BL1_RW_LIMIT (0xffe1ffff) +#define BL1_RW_SIZE (0x14000) + +#define BL2_BASE (0xffe00000) +#define BL2_LIMIT (0xffe1b000) -#define BL1_RO_BASE (0xffe00000) -#define BL1_RO_LIMIT (0xffe0f000) -#define BL1_RW_BASE (0xffe10000) -#define BL1_RW_LIMIT (0xffe1ffff) -#define BL1_RW_SIZE (0x14000) +#define BL31_BASE (0x1000) +#define BL31_LIMIT (0x81000) -#define BL2_BASE (0xffe00000) -#define BL2_LIMIT (0xffe1b000) +#define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET -#define BL31_BASE (0xffe1c000) -#define BL31_LIMIT (0xffe3bfff) +#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) +#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) /******************************************************************************* * Platform specific page table and MMU setup constants diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c index e29836173..65a4b0929 100644 --- a/plat/intel/soc/common/socfpga_psci.c +++ b/plat/intel/soc/common/socfpga_psci.c @@ -15,8 +15,6 @@ #include "socfpga_plat_def.h" -uintptr_t *socfpga_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; -uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE; /******************************************************************************* * plat handler called when a CPU is about to enter standby. @@ -45,7 +43,7 @@ int socfpga_pwr_domain_on(u_register_t mpidr) if (cpu_id == -1) return PSCI_E_INTERN_FAIL; - *cpuid_release = cpu_id; + mmio_write_64(PLAT_CPUID_RELEASE, cpu_id); /* release core reset */ mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); @@ -183,8 +181,8 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, const struct plat_psci_ops **psci_ops) { /* Save warm boot entrypoint.*/ - *socfpga_sec_entry = sec_entrypoint; - + mmio_write_64(PLAT_SEC_ENTRY, sec_entrypoint); *psci_ops = &socfpga_psci_pm_ops; + return 0; } -- cgit v1.2.3 From 23f31d39bf6c0c2c8476e62e6337f4493bb3c4d7 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Thu, 24 Oct 2019 16:13:09 +0800 Subject: intel: stratix10: Modify BL31 parameter handling Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL Signed-off-by: Hadi Asyrafi Change-Id: I16118d791399f652b6d1093c10092935a3449c32 --- plat/intel/soc/common/include/platform_def.h | 11 +++++++++++ plat/intel/soc/stratix10/bl31_plat_setup.c | 26 ++++++++++++++++++-------- 2 files changed, 29 insertions(+), 8 deletions(-) diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index e91995f9a..d6014d392 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -199,5 +199,16 @@ #define MAX_IO_DEVICES 4 #define MAX_IO_BLOCK_DEVICES 2 +#ifndef __ASSEMBLER__ +struct socfpga_bl31_params { + param_header_t h; + image_info_t *bl31_image_info; + entry_point_info_t *bl32_ep_info; + image_info_t *bl32_image_info; + entry_point_info_t *bl33_ep_info; + image_info_t *bl33_image_info; +}; +#endif + #endif /* PLATFORM_DEF_H */ diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 98ab35e7f..29bd1763f 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -53,23 +53,33 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void *from_bl2 = (void *) arg0; bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; - assert(params_from_bl2 != NULL); - assert(params_from_bl2->h.type == PARAM_BL_PARAMS); - assert(params_from_bl2->h.version >= VERSION_2); /* * Copy BL32 (if populated by BL31) and BL33 entry point information. * They are stored in Secure RAM, in BL31's address space. */ - bl_params_node_t *bl_params = params_from_bl2->head; + if (params_from_bl2->h.type == PARAM_BL_PARAMS && + params_from_bl2->h.version >= VERSION_2) { + + bl_params_node_t *bl_params = params_from_bl2->head; + + while (bl_params) { + if (bl_params->image_id == BL33_IMAGE_ID) + bl33_image_ep_info = *bl_params->ep_info; + + bl_params = bl_params->next_params_info; + } + } else { + struct socfpga_bl31_params *arg_from_bl2 = + (struct socfpga_bl31_params *) from_bl2; - while (bl_params) { - if (bl_params->image_id == BL33_IMAGE_ID) - bl33_image_ep_info = *bl_params->ep_info; + assert(arg_from_bl2->h.type == PARAM_BL31); + assert(arg_from_bl2->h.version >= VERSION_1); - bl_params = bl_params->next_params_info; + bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; + bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; } SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); } -- cgit v1.2.3 From 535fa663bf3fb65868d2be6cd3297298a38dc9ea Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Tue, 17 Dec 2019 09:38:08 +0100 Subject: doc: Fix indentation in build options documentation Sphinx was showing the following warning message: docs/getting_started/build-options.rst:200: WARNING: Bullet list ends without a blank line; unexpected unindent. Change-Id: Iad5d49c1e0d25dd623ad15bce1af31babf860c03 Signed-off-by: Sandrine Bailleux --- docs/getting_started/build-options.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 051586bc3..f082bee87 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -196,7 +196,7 @@ Common build options builds, but this behaviour can be overridden in each platform's Makefile or in the build command line. - - ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) +- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) support in GCC for TF-A. This option is currently only supported for AArch64. Default is 0. -- cgit v1.2.3 From d2483afac92c952b969c4443e3a9ae65bcbb485d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 9 Oct 2019 12:15:56 +0200 Subject: rockchip: px30: move secure init to separate file Similar to others like rk3399 and rk3288 move the secure init to a separate file to unclutter the soc init a bit. Signed-off-by: Heiko Stuebner Change-Id: Iebb38e24f1c7fe5353f139c896fb8ca769bf9691 --- plat/rockchip/px30/drivers/pmu/pmu.c | 1 + plat/rockchip/px30/drivers/secure/secure.c | 68 ++++++++++++++++++++++++++++++ plat/rockchip/px30/drivers/secure/secure.h | 65 ++++++++++++++++++++++++++++ plat/rockchip/px30/drivers/soc/soc.c | 61 +-------------------------- plat/rockchip/px30/drivers/soc/soc.h | 54 ------------------------ plat/rockchip/px30/platform.mk | 2 + 6 files changed, 137 insertions(+), 114 deletions(-) create mode 100644 plat/rockchip/px30/drivers/secure/secure.c create mode 100644 plat/rockchip/px30/drivers/secure/secure.h diff --git a/plat/rockchip/px30/drivers/pmu/pmu.c b/plat/rockchip/px30/drivers/pmu/pmu.c index 0a2515d12..5f4e64f7b 100644 --- a/plat/rockchip/px30/drivers/pmu/pmu.c +++ b/plat/rockchip/px30/drivers/pmu/pmu.c @@ -22,6 +22,7 @@ #include #include #include +#include #include DEFINE_BAKERY_LOCK(rockchip_pd_lock); diff --git a/plat/rockchip/px30/drivers/secure/secure.c b/plat/rockchip/px30/drivers/secure/secure.c new file mode 100644 index 000000000..94a6d4295 --- /dev/null +++ b/plat/rockchip/px30/drivers/secure/secure.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +void secure_timer_init(void) +{ + mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, + TIMER_DIS); + + mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); + mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); + + /* auto reload & enable the timer */ + mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, + TIMER_EN | TIMER_FMODE); +} + +void sgrf_init(void) +{ + uint32_t i, val; + struct param_ddr_usage usg; + + /* general secure regions */ + usg = ddr_region_usage_parse(DDR_PARAM_BASE, + PLAT_MAX_DDR_CAPACITY_MB); + for (i = 0; i < usg.s_nr; i++) { + /* enable secure */ + val = mmio_read_32(FIREWALL_DDR_BASE + + FIREWALL_DDR_FW_DDR_CON_REG); + val |= BIT(7 - i); + mmio_write_32(FIREWALL_DDR_BASE + + FIREWALL_DDR_FW_DDR_CON_REG, val); + /* map top and base */ + mmio_write_32(FIREWALL_DDR_BASE + + FIREWALL_DDR_FW_DDR_RGN(7 - i), + RG_MAP_SECURE(usg.s_top[i], usg.s_base[i])); + } + + /* set ddr rgn0_top and rga0_top as 0 */ + mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); + + /* set all slave ip into no-secure, except stimer */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000); + + /* set master crypto to no-secure, dcf to secure */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003); + + /* set DMAC into no-secure */ + mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS); + mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0); + mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16); + mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS); + + /* soft reset dma before use */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ); + udelay(5); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS); +} diff --git a/plat/rockchip/px30/drivers/secure/secure.h b/plat/rockchip/px30/drivers/secure/secure.h new file mode 100644 index 000000000..498027db2 --- /dev/null +++ b/plat/rockchip/px30/drivers/secure/secure.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SECURE_H +#define SECURE_H + +/*************************************************************************** + * SGRF + ***************************************************************************/ +#define SGRF_SOC_CON(i) ((i) * 0x4) +#define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4) + +#define SGRF_MST_S_ALL_NS 0xffffffff +#define SGRF_SLV_S_ALL_NS 0xffff0000 +#define DMA_IRQ_BOOT_NS 0xffffffff +#define DMA_PERI_CH_NS_15_0 0xffffffff +#define DMA_PERI_CH_NS_19_16 0x000f000f +#define DMA_MANAGER_BOOT_NS 0x00010001 +#define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12) +#define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12) + +/*************************************************************************** + * DDR FIREWALL + ***************************************************************************/ +#define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4) +#define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4) +#define FIREWALL_DDR_FW_DDR_CON_REG 0x40 +#define FIREWALL_DDR_FW_DDR_RGN_NUM 8 +#define FIREWALL_DDR_FW_DDR_MST_NUM 6 + +#define PLAT_MAX_DDR_CAPACITY_MB 4096 +#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base)) + +/************************************************** + * secure timer + **************************************************/ + +/* chanal0~5 */ +#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) + +#define TIMER_LOAD_COUNT0 0x0 +#define TIMER_LOAD_COUNT1 0x4 + +#define TIMER_CUR_VALUE0 0x8 +#define TIMER_CUR_VALUE1 0xc + +#define TIMER_CONTROL_REG 0x10 +#define TIMER_INTSTATUS 0x18 + +#define TIMER_DIS 0x0 +#define TIMER_EN 0x1 + +#define TIMER_FMODE (0x0 << 1) +#define TIMER_RMODE (0x1 << 1) + +#define TIMER_LOAD_COUNT0_MSK (0xffffffff) +#define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000) + +void secure_timer_init(void); +void sgrf_init(void); + +#endif /* SECURE_H */ diff --git a/plat/rockchip/px30/drivers/soc/soc.c b/plat/rockchip/px30/drivers/soc/soc.c index e00561d80..200563dee 100644 --- a/plat/rockchip/px30/drivers/soc/soc.c +++ b/plat/rockchip/px30/drivers/soc/soc.c @@ -12,10 +12,10 @@ #include #include -#include #include #include #include +#include #include #include @@ -83,65 +83,6 @@ void clk_gate_con_disable(void) 0xffff0000); } -void secure_timer_init(void) -{ - mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, - TIMER_DIS); - - mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); - mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); - - /* auto reload & enable the timer */ - mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, - TIMER_EN | TIMER_FMODE); -} - -static void sgrf_init(void) -{ - uint32_t i, val; - struct param_ddr_usage usg; - - /* general secure regions */ - usg = ddr_region_usage_parse(DDR_PARAM_BASE, - PLAT_MAX_DDR_CAPACITY_MB); - for (i = 0; i < usg.s_nr; i++) { - /* enable secure */ - val = mmio_read_32(FIREWALL_DDR_BASE + - FIREWALL_DDR_FW_DDR_CON_REG); - val |= BIT(7 - i); - mmio_write_32(FIREWALL_DDR_BASE + - FIREWALL_DDR_FW_DDR_CON_REG, val); - /* map top and base */ - mmio_write_32(FIREWALL_DDR_BASE + - FIREWALL_DDR_FW_DDR_RGN(7 - i), - RG_MAP_SECURE(usg.s_top[i], usg.s_base[i])); - } - - /* set ddr rgn0_top and rga0_top as 0 */ - mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); - - /* set all slave ip into no-secure, except stimer */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000); - - /* set master crypto to no-secure, dcf to secure */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003); - - /* set DMAC into no-secure */ - mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS); - mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0); - mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16); - mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS); - - /* soft reset dma before use */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ); - udelay(5); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS); -} - static void soc_reset_config_all(void) { uint32_t tmp; diff --git a/plat/rockchip/px30/drivers/soc/soc.h b/plat/rockchip/px30/drivers/soc/soc.h index 69f2de44a..648d18b62 100644 --- a/plat/rockchip/px30/drivers/soc/soc.h +++ b/plat/rockchip/px30/drivers/soc/soc.h @@ -28,21 +28,6 @@ enum pll_mode { DEEP_SLOW_MODE, }; -/*************************************************************************** - * SGRF - ***************************************************************************/ -#define SGRF_SOC_CON(i) ((i) * 0x4) -#define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4) - -#define SGRF_MST_S_ALL_NS 0xffffffff -#define SGRF_SLV_S_ALL_NS 0xffff0000 -#define DMA_IRQ_BOOT_NS 0xffffffff -#define DMA_PERI_CH_NS_15_0 0xffffffff -#define DMA_PERI_CH_NS_19_16 0x000f000f -#define DMA_MANAGER_BOOT_NS 0x00010001 -#define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12) -#define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12) - /*************************************************************************** * GRF ***************************************************************************/ @@ -60,18 +45,6 @@ enum pll_mode { #define GRF_SOC_CON2_NSWDT_RST_EN 12 -/*************************************************************************** - * DDR FIREWALL - ***************************************************************************/ -#define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4) -#define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4) -#define FIREWALL_DDR_FW_DDR_CON_REG 0x40 -#define FIREWALL_DDR_FW_DDR_RGN_NUM 8 -#define FIREWALL_DDR_FW_DDR_MST_NUM 6 - -#define PLAT_MAX_DDR_CAPACITY_MB 4096 -#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base)) - /*************************************************************************** * cru ***************************************************************************/ @@ -136,37 +109,10 @@ enum pll_mode { #define GPIO_INT_STATUS 0x40 #define GPIO_NUMS 4 -/************************************************** - * secure timer - **************************************************/ - -/* chanal0~5 */ -#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) - -#define TIMER_LOAD_COUNT0 0x0 -#define TIMER_LOAD_COUNT1 0x4 - -#define TIMER_CUR_VALUE0 0x8 -#define TIMER_CUR_VALUE1 0xc - -#define TIMER_CONTROL_REG 0x10 -#define TIMER_INTSTATUS 0x18 - -#define TIMER_DIS 0x0 -#define TIMER_EN 0x1 - -#define TIMER_FMODE (0x0 << 1) -#define TIMER_RMODE (0x1 << 1) - -#define TIMER_LOAD_COUNT0_MSK (0xffffffff) -#define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000) - void clk_gate_con_save(uint32_t *clkgt_save); void clk_gate_con_restore(uint32_t *clkgt_save); void clk_gate_con_disable(void); -void secure_timer_init(void); -void secure_timer_disable(void); void px30_soc_reset_config(void); #endif /* __SOC_H__ */ diff --git a/plat/rockchip/px30/platform.mk b/plat/rockchip/px30/platform.mk index ee85cd311..d1299d4af 100644 --- a/plat/rockchip/px30/platform.mk +++ b/plat/rockchip/px30/platform.mk @@ -20,6 +20,7 @@ PLAT_INCLUDES := -Idrivers/arm/gic/common/ \ -I${RK_PLAT_COMMON}/pmusram \ -I${RK_PLAT_SOC}/ \ -I${RK_PLAT_SOC}/drivers/pmu/ \ + -I${RK_PLAT_SOC}/drivers/secure/ \ -I${RK_PLAT_SOC}/drivers/soc/ \ -I${RK_PLAT_SOC}/include/ @@ -52,6 +53,7 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_COMMON}/plat_topology.c \ ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ + ${RK_PLAT_SOC}/drivers/secure/secure.c \ ${RK_PLAT_SOC}/drivers/soc/soc.c \ ${RK_PLAT_SOC}/plat_sip_calls.c -- cgit v1.2.3 From f55ef85ebfd61d708f6c77465edf3f8d059ca93d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 11 Oct 2019 23:26:39 +0200 Subject: rockchip: px30: cleanup securing of ddr regions So far the px30-related ddr security was loading data for regions to secure from a pre-specified memory location and also setting region0 to secure the first megabyte of memory in hard-coded setting (top=0, end=0, meaning 1MB). To make things more explicit and easier to read add a function doing the settings for specified memory areas, like other socs have and also add an assert to make sure any descriptor read from memory does not overlap the TZRAM security in region0 and TEE security in region1. Signed-off-by: Heiko Stuebner Change-Id: I78441875112bf66a62fde5f1789f4e52a78ef95f --- plat/rockchip/px30/drivers/secure/secure.c | 65 ++++++++++++++++++++++-------- plat/rockchip/px30/px30_def.h | 1 + 2 files changed, 50 insertions(+), 16 deletions(-) diff --git a/plat/rockchip/px30/drivers/secure/secure.c b/plat/rockchip/px30/drivers/secure/secure.c index 94a6d4295..bb2b02ab7 100644 --- a/plat/rockchip/px30/drivers/secure/secure.c +++ b/plat/rockchip/px30/drivers/secure/secure.c @@ -4,10 +4,49 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include #include +#include #include #include +/** + * There are 8 regions for DDR security control + * @rgn - the DDR regions 0 ~ 7 which are can be configured. + * @st - start address to set as secure + * @sz - length of area to set as secure + * The internal unit is megabytes, so memory areas need to be aligned + * to megabyte borders. + */ +static void secure_ddr_region(uint32_t rgn, + uintptr_t st, size_t sz) +{ + uintptr_t ed = st + sz; + uintptr_t st_mb, ed_mb; + uint32_t val; + + assert(rgn <= 7); + assert(st < ed); + + /* check aligned 1MB */ + assert(st % SIZE_M(1) == 0); + assert(ed % SIZE_M(1) == 0); + + st_mb = st / SIZE_M(1); + ed_mb = ed / SIZE_M(1); + + /* map top and base */ + mmio_write_32(FIREWALL_DDR_BASE + + FIREWALL_DDR_FW_DDR_RGN(rgn), + RG_MAP_SECURE(ed_mb, st_mb)); + + /* enable secure */ + val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG); + val |= BIT(rgn); + mmio_write_32(FIREWALL_DDR_BASE + + FIREWALL_DDR_FW_DDR_CON_REG, val); +} + void secure_timer_init(void) { mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, @@ -23,27 +62,21 @@ void secure_timer_init(void) void sgrf_init(void) { - uint32_t i, val; + uint32_t i; struct param_ddr_usage usg; /* general secure regions */ usg = ddr_region_usage_parse(DDR_PARAM_BASE, PLAT_MAX_DDR_CAPACITY_MB); - for (i = 0; i < usg.s_nr; i++) { - /* enable secure */ - val = mmio_read_32(FIREWALL_DDR_BASE + - FIREWALL_DDR_FW_DDR_CON_REG); - val |= BIT(7 - i); - mmio_write_32(FIREWALL_DDR_BASE + - FIREWALL_DDR_FW_DDR_CON_REG, val); - /* map top and base */ - mmio_write_32(FIREWALL_DDR_BASE + - FIREWALL_DDR_FW_DDR_RGN(7 - i), - RG_MAP_SECURE(usg.s_top[i], usg.s_base[i])); - } - - /* set ddr rgn0_top and rga0_top as 0 */ - mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); + + /* region-0 for TF-A, region-1 for optional OP-TEE */ + assert(usg.s_nr < 7); + + for (i = 0; i < usg.s_nr; i++) + secure_ddr_region(7 - i, usg.s_top[i], usg.s_base[i]); + + /* secure the trustzone ram */ + secure_ddr_region(0, TZRAM_BASE, TZRAM_SIZE); /* set all slave ip into no-secure, except stimer */ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); diff --git a/plat/rockchip/px30/px30_def.h b/plat/rockchip/px30/px30_def.h index 283b60641..efe789e1e 100644 --- a/plat/rockchip/px30/px30_def.h +++ b/plat/rockchip/px30/px30_def.h @@ -11,6 +11,7 @@ #define MINOR_VERSION (0) #define SIZE_K(n) ((n) * 1024) +#define SIZE_M(n) ((n) * 1024 * 1024) #define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) -- cgit v1.2.3 From df5a96831764c62deaf30b537987ab349abda2f6 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 12 Dec 2019 11:55:26 +0100 Subject: rockchip: make miniloader ddr_parameter handling optional Transfering the regions of ddr memory to additionally protect is very much specific to some rockchip internal first stage bootloader and doesn't get used in either mainline uboot or even Rockchip's published vendor uboot sources. This results in a big error ERROR: over or zero region, nr=0, max=10 getting emitted on every boot for most users and such a message coming from early firmware might actually confuse developers working with the system. As this mechanism seems to be only be used by Rockchip's internal miniloader hide it behind a build conditional, so it doesn't confuse people too much. Signed-off-by: Heiko Stuebner Change-Id: I52c02decc60fd431ea78c7486cad5bac82bdbfbe --- plat/rockchip/px30/drivers/secure/secure.c | 2 ++ plat/rockchip/px30/platform.mk | 5 ++++- plat/rockchip/rk3328/drivers/soc/soc.c | 4 +++- plat/rockchip/rk3328/platform.mk | 5 ++++- 4 files changed, 13 insertions(+), 3 deletions(-) diff --git a/plat/rockchip/px30/drivers/secure/secure.c b/plat/rockchip/px30/drivers/secure/secure.c index bb2b02ab7..144f94537 100644 --- a/plat/rockchip/px30/drivers/secure/secure.c +++ b/plat/rockchip/px30/drivers/secure/secure.c @@ -62,6 +62,7 @@ void secure_timer_init(void) void sgrf_init(void) { +#ifdef PLAT_RK_SECURE_DDR_MINILOADER uint32_t i; struct param_ddr_usage usg; @@ -74,6 +75,7 @@ void sgrf_init(void) for (i = 0; i < usg.s_nr; i++) secure_ddr_region(7 - i, usg.s_top[i], usg.s_base[i]); +#endif /* secure the trustzone ram */ secure_ddr_region(0, TZRAM_BASE, TZRAM_SIZE); diff --git a/plat/rockchip/px30/platform.mk b/plat/rockchip/px30/platform.mk index d1299d4af..87cf18704 100644 --- a/plat/rockchip/px30/platform.mk +++ b/plat/rockchip/px30/platform.mk @@ -46,7 +46,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ ${RK_PLAT_COMMON}/aarch64/platform_common.c \ ${RK_PLAT_COMMON}/bl31_plat_setup.c \ - ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \ ${RK_PLAT_COMMON}/params_setup.c \ ${RK_PLAT_COMMON}/pmusram/cpus_on_fixed_addr.S \ ${RK_PLAT_COMMON}/plat_pm.c \ @@ -57,6 +56,10 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_SOC}/drivers/soc/soc.c \ ${RK_PLAT_SOC}/plat_sip_calls.c +ifdef PLAT_RK_SECURE_DDR_MINILOADER +BL31_SOURCES += ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c +endif + ENABLE_PLAT_COMPAT := 0 MULTI_CONSOLE_API := 1 diff --git a/plat/rockchip/rk3328/drivers/soc/soc.c b/plat/rockchip/rk3328/drivers/soc/soc.c index 59d857244..306308f3f 100644 --- a/plat/rockchip/rk3328/drivers/soc/soc.c +++ b/plat/rockchip/rk3328/drivers/soc/soc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -97,6 +97,7 @@ void secure_timer_init(void) void sgrf_init(void) { +#ifdef PLAT_RK_SECURE_DDR_MINILOADER uint32_t i, val; struct param_ddr_usage usg; @@ -115,6 +116,7 @@ void sgrf_init(void) FIREWALL_DDR_FW_DDR_RGN(7 - i), RG_MAP_SECURE(usg.s_top[i], usg.s_base[i])); } +#endif /* set ddr rgn0_top and rga0_top as 0 */ mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk index 0da4f2dc4..0c5cfae9b 100644 --- a/plat/rockchip/rk3328/platform.mk +++ b/plat/rockchip/rk3328/platform.mk @@ -42,7 +42,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ drivers/delay_timer/generic_delay_timer.c \ lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ - ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \ ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ ${RK_PLAT_COMMON}/params_setup.c \ ${RK_PLAT_COMMON}/bl31_plat_setup.c \ @@ -53,6 +52,10 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ ${RK_PLAT_SOC}/drivers/soc/soc.c +ifdef PLAT_RK_SECURE_DDR_MINILOADER +BL31_SOURCES += ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c +endif + include lib/coreboot/coreboot.mk include lib/libfdt/libfdt.mk -- cgit v1.2.3 From 0ca3913dd898ec0822d4984f8fd6eb86131f1088 Mon Sep 17 00:00:00 2001 From: Olivier Deprez Date: Thu, 19 Sep 2019 17:46:46 +0200 Subject: debugfs: add 9p device interface The 9p interface provides abstraction layers allowing the software that uses devices to be independent from the hardware. This patch provides a file system abstraction to link drivers to their devices and propose a common interface to expose driver operations to higher layers. This file system can be used to access and configure a device by doing read/write operations. Signed-off-by: Ambroise Vincent Signed-off-by: Olivier Deprez Change-Id: Ia9662393baf489855dc0c8f389fe4a0afbc9c255 --- Makefile | 11 + bl31/bl31.mk | 5 + include/lib/debugfs.h | 60 ++++ lib/debugfs/blobs.h | 11 + lib/debugfs/debugfs.mk | 10 + lib/debugfs/dev.c | 849 +++++++++++++++++++++++++++++++++++++++++++++++ lib/debugfs/dev.h | 120 +++++++ lib/debugfs/devc.c | 18 + lib/debugfs/devroot.c | 97 ++++++ make_helpers/defaults.mk | 3 + 10 files changed, 1184 insertions(+) create mode 100644 include/lib/debugfs.h create mode 100644 lib/debugfs/blobs.h create mode 100644 lib/debugfs/debugfs.mk create mode 100644 lib/debugfs/dev.c create mode 100644 lib/debugfs/dev.h create mode 100644 lib/debugfs/devc.c create mode 100644 lib/debugfs/devroot.c diff --git a/Makefile b/Makefile index 54d332cd7..7cee8e062 100644 --- a/Makefile +++ b/Makefile @@ -150,6 +150,15 @@ else endif endif +# USE_DEBUGFS experimental feature recommended only in debug builds +ifeq (${USE_DEBUGFS},1) +ifeq (${DEBUG},1) + $(warning DEBUGFS experimental feature is enabled.) +else + $(warning DEBUGFS experimental, recommended in DEBUG builds ONLY) +endif +endif + ################################################################################ # Toolchain ################################################################################ @@ -734,6 +743,7 @@ $(eval $(call assert_boolean,SPIN_ON_BL1_EXIT)) $(eval $(call assert_boolean,SPM_MM)) $(eval $(call assert_boolean,TRUSTED_BOARD_BOOT)) $(eval $(call assert_boolean,USE_COHERENT_MEM)) +$(eval $(call assert_boolean,USE_DEBUGFS)) $(eval $(call assert_boolean,USE_ROMLIB)) $(eval $(call assert_boolean,USE_TBBR_DEFS)) $(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY)) @@ -800,6 +810,7 @@ $(eval $(call add_define,SPIN_ON_BL1_EXIT)) $(eval $(call add_define,SPM_MM)) $(eval $(call add_define,TRUSTED_BOARD_BOOT)) $(eval $(call add_define,USE_COHERENT_MEM)) +$(eval $(call add_define,USE_DEBUGFS)) $(eval $(call add_define,USE_ROMLIB)) $(eval $(call add_define,USE_TBBR_DEFS)) $(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY)) diff --git a/bl31/bl31.mk b/bl31/bl31.mk index c9ba926c5..85d471c0e 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -43,6 +43,11 @@ ifeq (${ENABLE_PMF}, 1) BL31_SOURCES += lib/pmf/pmf_main.c endif +include lib/debugfs/debugfs.mk +ifeq (${USE_DEBUGFS},1) + BL31_SOURCES += $(DEBUGFS_SRCS) +endif + ifeq (${EL3_EXCEPTION_HANDLING},1) BL31_SOURCES += bl31/ehf.c endif diff --git a/include/lib/debugfs.h b/include/lib/debugfs.h new file mode 100644 index 000000000..b7e33303c --- /dev/null +++ b/include/lib/debugfs.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DEBUGFS_H +#define DEBUGFS_H + +#define NAMELEN 13 /* Maximum length of a file name */ +#define PATHLEN 41 /* Maximum length of a path */ +#define STATLEN 41 /* Size of static part of dir format */ +#define ROOTLEN (2 + 4) /* Size needed to encode root string */ +#define FILNAMLEN (2 + NAMELEN) /* Size needed to encode filename */ +#define DIRLEN (STATLEN + FILNAMLEN + 3*ROOTLEN) /* Size of dir entry */ + +#define KSEEK_SET 0 +#define KSEEK_CUR 1 +#define KSEEK_END 2 + +#define NELEM(tab) (sizeof(tab) / sizeof((tab)[0])) + +typedef unsigned short qid_t; /* FIXME: short type not recommended? */ + +/******************************************************************************* + * This structure contains the necessary information to represent a 9p + * directory. + ******************************************************************************/ +typedef struct { + char name[NAMELEN]; + long length; + unsigned char mode; + unsigned char index; + unsigned char dev; + qid_t qid; +} dir_t; + +/* Permission definitions used as flags */ +#define O_READ (1 << 0) +#define O_WRITE (1 << 1) +#define O_RDWR (1 << 2) +#define O_BIND (1 << 3) +#define O_DIR (1 << 4) +#define O_STAT (1 << 5) + +/* 9p interface */ +int mount(const char *srv, const char *mnt, const char *spec); +int create(const char *name, int flags); +int open(const char *name, int flags); +int close(int fd); +int read(int fd, void *buf, int n); +int write(int fd, void *buf, int n); +int seek(int fd, long off, int whence); +int bind(const char *path, const char *where); +int stat(const char *path, dir_t *dir); + +/* DebugFS initialization */ +void debugfs_init(void); + +#endif /* DEBUGFS_H */ diff --git a/lib/debugfs/blobs.h b/lib/debugfs/blobs.h new file mode 100644 index 000000000..4aa348153 --- /dev/null +++ b/lib/debugfs/blobs.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "dev.h" + +static const dirtab_t blobtab[] = { + {"ctl", DEV_ROOT_QBLOBCTL, 0, O_READ} +}; diff --git a/lib/debugfs/debugfs.mk b/lib/debugfs/debugfs.mk new file mode 100644 index 000000000..030556aea --- /dev/null +++ b/lib/debugfs/debugfs.mk @@ -0,0 +1,10 @@ +# +# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +DEBUGFS_SRCS := $(addprefix lib/debugfs/, \ + dev.c \ + devc.c \ + devroot.c) diff --git a/lib/debugfs/dev.c b/lib/debugfs/dev.c new file mode 100644 index 000000000..0361437b8 --- /dev/null +++ b/lib/debugfs/dev.c @@ -0,0 +1,849 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include "dev.h" + +#define NR_MOUNT_POINTS 4 + +struct mount_point { + chan_t *new; + chan_t *old; +}; + +/* This array contains all the available channels of the filesystem. + * A file descriptor is the index of a specific channel in this array. + */ +static chan_t fdset[NR_CHANS]; + +/* This array contains all the available mount points of the filesystem. */ +static struct mount_point mount_points[NR_MOUNT_POINTS]; + +/* This variable stores the channel associated to the root directory. */ +static chan_t slash_channel; + +/* This function creates a channel from a device index and registers + * it to fdset. + */ +static chan_t *create_new_channel(unsigned char index) +{ + chan_t *channel = NULL; + int i; + + for (i = 0; i < NR_CHANS; i++) { + if (fdset[i].index == NODEV) { + channel = &fdset[i]; + channel->index = index; + break; + } + } + + return channel; +} + +/******************************************************************************* + * This function returns a pointer to an existing channel in fdset from a file + * descriptor. + ******************************************************************************/ +static chan_t *fd_to_channel(int fd) +{ + if ((fd < 0) || (fd >= NR_CHANS) || (fdset[fd].index == NODEV)) { + return NULL; + } + + return &fdset[fd]; +} + +/******************************************************************************* + * This function returns a file descriptor from a channel. + * The caller must be sure that the channel is registered in fdset. + ******************************************************************************/ +static int channel_to_fd(chan_t *channel) +{ + return (channel == NULL) ? -1 : (channel - fdset); +} + +/******************************************************************************* + * This function checks the validity of a mode. + ******************************************************************************/ +static bool is_valid_mode(int mode) +{ + if ((mode & O_READ) && (mode & (O_WRITE | O_RDWR))) { + return false; + } + if ((mode & O_WRITE) && (mode & (O_READ | O_RDWR))) { + return false; + } + if ((mode & O_RDWR) && (mode & (O_READ | O_WRITE))) { + return false; + } + + return true; +} + +/******************************************************************************* + * This function extracts the next part of the given path contained and puts it + * in token. It returns a pointer to the remainder of the path. + ******************************************************************************/ +static const char *next(const char *path, char *token) +{ + int index; + const char *cursor; + + while (*path == '/') { + ++path; + } + + index = 0; + cursor = path; + if (*path != '\0') { + while (*cursor != '/' && *cursor != '\0') { + if (index == NAMELEN) { + return NULL; + } + token[index++] = *cursor++; + } + } + token[index] = '\0'; + + return cursor; +} + +/******************************************************************************* + * This function returns the driver index in devtab of the driver + * identified by id. + ******************************************************************************/ +static int get_device_index(int id) +{ + int index; + dev_t * const *dp; + + for (index = 0, dp = devtab; *dp && (*dp)->id != id; ++dp) { + index++; + } + + if (*dp == NULL) { + return -1; + } + + return index; +} + +/******************************************************************************* + * This function clears a given channel fields + ******************************************************************************/ +static void channel_clear(chan_t *channel) +{ + channel->offset = 0; + channel->qid = 0; + channel->index = NODEV; + channel->dev = 0; + channel->mode = 0; +} + +/******************************************************************************* + * This function closes the channel pointed to by c. + ******************************************************************************/ +void channel_close(chan_t *channel) +{ + if (channel != NULL) { + channel_clear(channel); + } +} + +/******************************************************************************* + * This function copies data from src to dst after applying the offset of the + * channel c. nbytes bytes are expected to be copied unless the data goes over + * dst + len. + * It returns the actual number of bytes that were copied. + ******************************************************************************/ +int buf_to_channel(chan_t *channel, void *dst, void *src, int nbytes, long len) +{ + const char *addr = src; + + if ((channel == NULL) || (dst == NULL) || (src == NULL)) { + return 0; + } + + if (channel->offset >= len) { + return 0; + } + + if ((channel->offset + nbytes) > len) { + nbytes = len - channel->offset; + } + + memcpy(dst, addr + channel->offset, nbytes); + + channel->offset += nbytes; + + return nbytes; +} + +/******************************************************************************* + * This function checks whether a channel (identified by its device index and + * qid) is registered as a mount point. + * Returns a pointer to the channel it is mounted to when found, NULL otherwise. + ******************************************************************************/ +static chan_t *mount_point_to_channel(int index, qid_t qid) +{ + chan_t *channel; + struct mount_point *mp; + + for (mp = mount_points; mp < &mount_points[NR_MOUNT_POINTS]; mp++) { + channel = mp->new; + if (channel == NULL) { + continue; + } + + if ((channel->index == index) && (channel->qid == qid)) { + return mp->old; + } + } + + return NULL; +} + +/******************************************************************************* + * This function calls the attach function of the driver identified by id. + ******************************************************************************/ +chan_t *attach(int id, int dev) +{ + /* Get the devtab index for the driver identified by id */ + int index = get_device_index(id); + + if (index < 0) { + return NULL; + } + + return devtab[index]->attach(id, dev); +} + +/******************************************************************************* + * This function is the default implementation of the driver attach function. + * It creates a new channel and returns a pointer to it. + ******************************************************************************/ +chan_t *devattach(int id, int dev) +{ + chan_t *channel; + int index; + + index = get_device_index(id); + if (index < 0) { + return NULL; + } + + channel = create_new_channel(index); + if (channel == NULL) { + return NULL; + } + + channel->dev = dev; + channel->qid = CHDIR; + + return channel; +} + +/******************************************************************************* + * This function returns a channel given a path. + * It goes through the filesystem, from the root namespace ('/') or from a + * device namespace ('#'), switching channel on mount points. + ******************************************************************************/ +chan_t *path_to_channel(const char *path, int mode) +{ + int i, n; + const char *path_next; + chan_t *mnt, *channel; + char elem[NAMELEN]; + + if (path == NULL) { + return NULL; + } + + switch (path[0]) { + case '/': + channel = clone(&slash_channel, NULL); + path_next = path; + break; + case '#': + path_next = next(path + 1, elem); + if (path_next == NULL) { + goto noent; + } + + n = 0; + for (i = 1; (elem[i] >= '0') && (elem[i] <= '9'); i++) { + n += elem[i] - '0'; + } + + if (elem[i] != '\0') { + goto noent; + } + + channel = attach(elem[0], n); + break; + default: + return NULL; + } + + if (channel == NULL) { + return NULL; + } + + for (path_next = next(path_next, elem); *elem; + path_next = next(path_next, elem)) { + if ((channel->qid & CHDIR) == 0) { + goto notfound; + } + + if (devtab[channel->index]->walk(channel, elem) < 0) { + channel_close(channel); + goto notfound; + } + + mnt = mount_point_to_channel(channel->index, channel->qid); + if (mnt != NULL) { + clone(mnt, channel); + } + } + + if (path_next == NULL) { + goto notfound; + } + + /* TODO: check mode */ + return channel; + +notfound: + channel_close(channel); +noent: + return NULL; +} + +/******************************************************************************* + * This function calls the clone function of the driver associated to the + * channel c. + ******************************************************************************/ +chan_t *clone(chan_t *c, chan_t *nc) +{ + return devtab[c->index]->clone(c, nc); +} + +/******************************************************************************* + * This function is the default implementation of the driver clone function. + * It creates a new channel and returns a pointer to it. + * It clones channel into new_channel. + ******************************************************************************/ +chan_t *devclone(chan_t *channel, chan_t *new_channel) +{ + if (channel == NULL) { + return NULL; + } + + if (new_channel == NULL) { + new_channel = create_new_channel(channel->index); + if (new_channel == NULL) { + return NULL; + } + } + + new_channel->qid = channel->qid; + new_channel->dev = channel->dev; + new_channel->mode = channel->mode; + new_channel->offset = channel->offset; + new_channel->index = channel->index; + + return new_channel; +} + +/******************************************************************************* + * This function is the default implementation of the driver walk function. + * It goes through all the elements of tab using the gen function until a match + * is found with name. + * If a match is found, it copies the qid of the new directory. + ******************************************************************************/ +int devwalk(chan_t *channel, const char *name, const dirtab_t *tab, + int ntab, devgen_t *gen) +{ + int i; + dir_t dir; + + if ((channel == NULL) || (name == NULL) || (gen == NULL)) { + return -1; + } + + if ((name[0] == '.') && (name[1] == '\0')) { + return 1; + } + + for (i = 0; ; i++) { + switch ((*gen)(channel, tab, ntab, i, &dir)) { + case 0: + /* Intentional fall-through */ + case -1: + return -1; + case 1: + if (strncmp(name, dir.name, NAMELEN) != 0) { + continue; + } + channel->qid = dir.qid; + return 1; + } + } +} + +/******************************************************************************* + * This is a helper function which exposes the content of a directory, element + * by element. It is meant to be called until the end of the directory is + * reached or an error occurs. + * It returns -1 on error, 0 on end of directory and 1 when a new file is found. + ******************************************************************************/ +int dirread(chan_t *channel, dir_t *dir, const dirtab_t *tab, + int ntab, devgen_t *gen) +{ + int i, ret; + + if ((channel == NULL) || (dir == NULL) || (gen == NULL)) { + return -1; + } + + i = channel->offset/sizeof(dir_t); + ret = (*gen)(channel, tab, ntab, i, dir); + if (ret == 1) { + channel->offset += sizeof(dir_t); + } + + return ret; +} + +/******************************************************************************* + * This function sets the elements of dir. + ******************************************************************************/ +void make_dir_entry(chan_t *channel, dir_t *dir, + const char *name, long length, qid_t qid, unsigned int mode) +{ + if ((channel == NULL) || (dir == NULL) || (name == NULL)) { + return; + } + + strlcpy(dir->name, name, sizeof(dir->name)); + dir->length = length; + dir->qid = qid; + dir->mode = mode; + + if ((qid & CHDIR) != 0) { + dir->mode |= O_DIR; + } + + dir->index = channel->index; + dir->dev = channel->dev; +} + +/******************************************************************************* + * This function is the default implementation of the internal driver gen + * function. + * It copies and formats the information of the nth element of tab into dir. + ******************************************************************************/ +int devgen(chan_t *channel, const dirtab_t *tab, int ntab, int n, dir_t *dir) +{ + const dirtab_t *dp; + + if ((channel == NULL) || (dir == NULL) || (tab == NULL) || + (n >= ntab)) { + return 0; + } + + dp = &tab[n]; + make_dir_entry(channel, dir, dp->name, dp->length, dp->qid, dp->perm); + return 1; +} + +/******************************************************************************* + * This function returns a file descriptor identifying the channel associated to + * the given path. + ******************************************************************************/ +int open(const char *path, int mode) +{ + chan_t *channel; + + if (path == NULL) { + return -1; + } + + if (is_valid_mode(mode) == false) { + return -1; + } + + channel = path_to_channel(path, mode); + + return channel_to_fd(channel); +} + +/******************************************************************************* + * This function closes the channel identified by the file descriptor fd. + ******************************************************************************/ +int close(int fd) +{ + chan_t *channel; + + channel = fd_to_channel(fd); + if (channel == NULL) { + return -1; + } + + channel_close(channel); + return 0; +} + +/******************************************************************************* + * This function is the default implementation of the driver stat function. + * It goes through all the elements of tab using the gen function until a match + * is found with file. + * If a match is found, dir contains the information file. + ******************************************************************************/ +int devstat(chan_t *dirc, const char *file, dir_t *dir, + const dirtab_t *tab, int ntab, devgen_t *gen) +{ + int i, r = 0; + chan_t *c, *mnt; + + if ((dirc == NULL) || (dir == NULL) || (gen == NULL)) { + return -1; + } + + c = path_to_channel(file, O_STAT); + if (c == NULL) { + return -1; + } + + for (i = 0; ; i++) { + switch ((*gen)(dirc, tab, ntab, i, dir)) { + case 0: + /* Intentional fall-through */ + case -1: + r = -1; + goto leave; + case 1: + mnt = mount_point_to_channel(dir->index, dir->qid); + if (mnt != NULL) { + dir->qid = mnt->qid; + dir->index = mnt->index; + } + + if ((dir->qid != c->qid) || (dir->index != c->index)) { + continue; + } + + goto leave; + } + } + +leave: + channel_close(c); + return r; +} + +/******************************************************************************* + * This function calls the stat function of the driver associated to the parent + * directory of the file in path. + * The result is stored in dir. + ******************************************************************************/ +int stat(const char *path, dir_t *dir) +{ + int r; + size_t len; + chan_t *channel; + char *p, dirname[PATHLEN]; + + if ((path == NULL) || (dir == NULL)) { + return -1; + } + + len = strlen(path); + if ((len + 1) > sizeof(dirname)) { + return -1; + } + + memcpy(dirname, path, len); + for (p = dirname + len; p > dirname; --p) { + if (*p != '/') { + break; + } + } + + p = memrchr(dirname, '/', p - dirname); + if (p == NULL) { + return -1; + } + + dirname[p - dirname + 1] = '\0'; + + channel = path_to_channel(dirname, O_STAT); + if (channel == NULL) { + return -1; + } + + r = devtab[channel->index]->stat(channel, path, dir); + channel_close(channel); + + return r; +} + +/******************************************************************************* + * This function calls the read function of the driver associated to fd. + * It fills buf with at most n bytes. + * It returns the number of bytes that were actually read. + ******************************************************************************/ +int read(int fd, void *buf, int n) +{ + chan_t *channel; + + if (buf == NULL) { + return -1; + } + + channel = fd_to_channel(fd); + if (channel == NULL) { + return -1; + } + + if (((channel->qid & CHDIR) != 0) && (n < sizeof(dir_t))) { + return -1; + } + + return devtab[channel->index]->read(channel, buf, n); +} + +/******************************************************************************* + * This function calls the write function of the driver associated to fd. + * It writes at most n bytes of buf. + * It returns the number of bytes that were actually written. + ******************************************************************************/ +int write(int fd, void *buf, int n) +{ + chan_t *channel; + + if (buf == NULL) { + return -1; + } + + channel = fd_to_channel(fd); + if (channel == NULL) { + return -1; + } + + if ((channel->qid & CHDIR) != 0) { + return -1; + } + + return devtab[channel->index]->write(channel, buf, n); +} + +/******************************************************************************* + * This function calls the seek function of the driver associated to fd. + * It applies the offset off according to the strategy whence. + ******************************************************************************/ +int seek(int fd, long off, int whence) +{ + chan_t *channel; + + channel = fd_to_channel(fd); + if (channel == NULL) { + return -1; + } + + if ((channel->qid & CHDIR) != 0) { + return -1; + } + + return devtab[channel->index]->seek(channel, off, whence); +} + +/******************************************************************************* + * This function is the default error implementation of the driver mount + * function. + ******************************************************************************/ +chan_t *deverrmount(chan_t *channel, const char *spec) +{ + return NULL; +} + +/******************************************************************************* + * This function is the default error implementation of the driver write + * function. + ******************************************************************************/ +int deverrwrite(chan_t *channel, void *buf, int n) +{ + return -1; +} + +/******************************************************************************* + * This function is the default error implementation of the driver seek + * function. + ******************************************************************************/ +int deverrseek(chan_t *channel, long off, int whence) +{ + return -1; +} + +/******************************************************************************* + * This function is the default implementation of the driver seek function. + * It applies the offset off according to the strategy whence to the channel c. + ******************************************************************************/ +int devseek(chan_t *channel, long off, int whence) +{ + switch (whence) { + case KSEEK_SET: + channel->offset = off; + break; + case KSEEK_CUR: + channel->offset += off; + break; + case KSEEK_END: + /* Not implemented */ + return -1; + } + + return 0; +} + +/******************************************************************************* + * This function registers the channel associated to the path new as a mount + * point for the channel c. + ******************************************************************************/ +static int add_mount_point(chan_t *channel, const char *new) +{ + int i; + chan_t *cn; + struct mount_point *mp; + + if (new == NULL) { + goto err0; + } + + cn = path_to_channel(new, O_READ); + if (cn == NULL) { + goto err0; + } + + if ((cn->qid & CHDIR) == 0) { + goto err1; + } + + for (i = NR_MOUNT_POINTS - 1; i >= 0; i--) { + mp = &mount_points[i]; + if (mp->new == NULL) { + break; + } + } + + if (i < 0) { + goto err1; + } + + mp->new = cn; + mp->old = channel; + + return 0; + +err1: + channel_close(cn); +err0: + return -1; +} + +/******************************************************************************* + * This function registers the path new as a mount point for the path old. + ******************************************************************************/ +int bind(const char *old, const char *new) +{ + chan_t *channel; + + channel = path_to_channel(old, O_BIND); + if (channel == NULL) { + return -1; + } + + if (add_mount_point(channel, new) < 0) { + channel_close(channel); + return -1; + } + + return 0; +} + +/******************************************************************************* + * This function calls the mount function of the driver associated to the path + * srv. + * It mounts the path srv on the path where. + ******************************************************************************/ +int mount(const char *srv, const char *where, const char *spec) +{ + chan_t *channel, *mount_point_chan; + int ret; + + channel = path_to_channel(srv, O_RDWR); + if (channel == NULL) { + goto err0; + } + + mount_point_chan = devtab[channel->index]->mount(channel, spec); + if (mount_point_chan == NULL) { + goto err1; + } + + ret = add_mount_point(mount_point_chan, where); + if (ret < 0) { + goto err2; + } + + channel_close(channel); + + return 0; + +err2: + channel_close(mount_point_chan); +err1: + channel_close(channel); +err0: + return -1; +} + +/******************************************************************************* + * This function initializes the device environment. + * It creates the '/' channel. + * It links the device drivers to the physical drivers. + ******************************************************************************/ +void debugfs_init(void) +{ + chan_t *channel, *cloned_channel; + + for (channel = fdset; channel < &fdset[NR_CHANS]; channel++) { + channel_clear(channel); + } + + channel = devattach('/', 0); + if (channel == NULL) { + panic(); + } + + cloned_channel = clone(channel, &slash_channel); + if (cloned_channel == NULL) { + panic(); + } + + channel_close(channel); + devlink(); +} + +__dead2 void devpanic(const char *cause) +{ + panic(); +} diff --git a/lib/debugfs/dev.h b/lib/debugfs/dev.h new file mode 100644 index 000000000..c142651c7 --- /dev/null +++ b/lib/debugfs/dev.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DEV_H +#define DEV_H + +#include +#include +#include + +/* FIXME: need configurability */ +#define NR_CHANS 10 +#define NR_CONSS 1 +#define NR_BINDS 4 +#define NR_FILES 18 + +#define NODEV 255 +#define CHDIR (1 << 15) + +#define SYNCDEV 0 +#define SYNCALL 1 + +typedef struct dev dev_t; +typedef struct chan chan_t; +typedef struct dirtab dirtab_t; +typedef int devgen_t(chan_t *, const dirtab_t *, int, int, dir_t *); +typedef struct attr attr_t; + +enum { + DEV_ROOT_QROOT, + DEV_ROOT_QDEV, + DEV_ROOT_QFIP, + DEV_ROOT_QBLOBS, + DEV_ROOT_QBLOBCTL, + DEV_ROOT_QPSCI +}; + +/******************************************************************************* + * This structure contains the necessary information to represent a directory + * of the filesystem. + ******************************************************************************/ +struct dirtab { + char name[NAMELEN]; + qid_t qid; + long length; + unsigned char perm; + void *data; +}; + +/******************************************************************************* + * This structure defines the interface of device drivers. + * Each driver must implement a subset of those functions. + * It is possible to redirect to default implementations defined in dev.c. + ******************************************************************************/ +/* FIXME: comments for the callbacks */ +struct dev { + char id; + int (*stat)(chan_t *c, const char *file, dir_t *dir); + int (*walk)(chan_t *c, const char *name); + int (*read)(chan_t *c, void *buf, int n); + int (*write)(chan_t *c, void *buf, int n); + int (*seek)(chan_t *c, long off, int whence); + chan_t *(*clone)(chan_t *c, chan_t *nc); + chan_t *(*attach)(int id, int dev); + chan_t *(*mount)(chan_t *c, const char *spec); +}; + +/******************************************************************************* + * This structure defines the channel structure. + * A channel is a handle on an element of the filesystem. + ******************************************************************************/ +struct chan { + long offset; + qid_t qid; + unsigned char index; /* device index in devtab */ + unsigned char dev; + unsigned char mode; +}; + +/******************************************************************************* + * This structure defines an abstract argument passed to physical drivers from + * the configuration file. + ******************************************************************************/ +struct attr { + char *key; + char *value; +}; + +chan_t *path_to_channel(const char *path, int mode); +chan_t *clone(chan_t *c, chan_t *nc); +chan_t *attach(int id, int dev); +void channel_close(chan_t *c); +int buf_to_channel(chan_t *c, void *dst, void *src, int nbytes, long len); +int dirread(chan_t *c, dir_t *dir, const dirtab_t *tab, + int ntab, devgen_t *gen); +void make_dir_entry(chan_t *c, dir_t *dir, const char *name, long length, + qid_t qid, unsigned int mode); +void devlink(void); + +chan_t *devattach(int id, int dev); +int devseek(chan_t *c, long off, int whence); +chan_t *devclone(chan_t *c, chan_t *nc); +int devgen(chan_t *c, const dirtab_t *tab, int ntab, int n, dir_t *dir); +int devwalk(chan_t *c, const char *name, const dirtab_t *tab, int ntab, + devgen_t *gen); +int devstat(chan_t *dirc, const char *file, dir_t *dir, + const dirtab_t *tab, int ntab, devgen_t *gen); + +chan_t *deverrmount(chan_t *c, const char *spec); +int deverrwrite(chan_t *c, void *buf, int n); +int deverrseek(chan_t *c, long off, int whence); + +extern dev_t *const devtab[]; + +void __dead2 devpanic(const char *cause); + +#endif /* DEV_H */ diff --git a/lib/debugfs/devc.c b/lib/debugfs/devc.c new file mode 100644 index 000000000..13c553d3e --- /dev/null +++ b/lib/debugfs/devc.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +typedef struct dev dev_t; + +extern dev_t rootdevtab; + +dev_t *const devtab[] = { + &rootdevtab, + 0 +}; + +void devlink(void) +{ +} diff --git a/lib/debugfs/devroot.c b/lib/debugfs/devroot.c new file mode 100644 index 000000000..9dd6c92ef --- /dev/null +++ b/lib/debugfs/devroot.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include "blobs.h" +#include "dev.h" + +/******************************************************************************* + * This array contains the directories available from the root directory. + ******************************************************************************/ +static const dirtab_t dirtab[] = { + {"dev", CHDIR | DEV_ROOT_QDEV, 0, O_READ}, + {"blobs", CHDIR | DEV_ROOT_QBLOBS, 0, O_READ}, + {"fip", CHDIR | DEV_ROOT_QFIP, 0, O_READ} +}; + +static const dirtab_t devfstab[] = { +}; + +/******************************************************************************* + * This function exposes the elements of the root directory. + * It also exposes the content of the dev and blobs directories. + ******************************************************************************/ +static int rootgen(chan_t *channel, const dirtab_t *tab, int ntab, + int n, dir_t *dir) +{ + switch (channel->qid & ~CHDIR) { + case DEV_ROOT_QROOT: + tab = dirtab; + ntab = NELEM(dirtab); + break; + case DEV_ROOT_QDEV: + tab = devfstab; + ntab = NELEM(devfstab); + break; + case DEV_ROOT_QBLOBS: + tab = blobtab; + ntab = NELEM(blobtab); + break; + default: + return 0; + } + + return devgen(channel, tab, ntab, n, dir); +} + +static int rootwalk(chan_t *channel, const char *name) +{ + return devwalk(channel, name, NULL, 0, rootgen); +} + +/******************************************************************************* + * This function copies at most n bytes from the element referred by c into buf. + ******************************************************************************/ +static int rootread(chan_t *channel, void *buf, int size) +{ + const dirtab_t *dp; + dir_t *dir; + + if ((channel->qid & CHDIR) != 0) { + if (size < sizeof(dir_t)) { + return -1; + } + + dir = buf; + return dirread(channel, dir, NULL, 0, rootgen); + } + + /* Only makes sense when using debug language */ + assert(channel->qid != DEV_ROOT_QBLOBCTL); + + dp = &blobtab[channel->qid - DEV_ROOT_QBLOBCTL]; + return buf_to_channel(channel, buf, dp->data, size, dp->length); +} + +static int rootstat(chan_t *channel, const char *file, dir_t *dir) +{ + return devstat(channel, file, dir, NULL, 0, rootgen); +} + +const dev_t rootdevtab = { + .id = '/', + .stat = rootstat, + .clone = devclone, + .attach = devattach, + .walk = rootwalk, + .read = rootread, + .write = deverrwrite, + .mount = deverrmount, + .seek = devseek +}; diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 348b3e52b..797f75c30 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -194,6 +194,9 @@ TRUSTED_BOARD_BOOT := 0 # Build option to choose whether Trusted Firmware uses Coherent memory or not. USE_COHERENT_MEM := 1 +# Build option to add debugfs support +USE_DEBUGFS := 0 + # Build option to choose whether Trusted Firmware uses library at ROM USE_ROMLIB := 0 -- cgit v1.2.3 From d310239d775c34d237b8c4b81baa6f6a12207824 Mon Sep 17 00:00:00 2001 From: Olivier Deprez Date: Wed, 6 Nov 2019 14:00:43 +0100 Subject: debugfs: add FIP device Add a FIP driver hooked to debugfs 9p interface. This is an abstraction of the FIP filesystem layer on top of a mass storage, or memory block driver. Signed-off-by: Olivier Deprez Change-Id: If275ea0824763de43ab666dab2a06de5352ff940 --- lib/debugfs/blobs.h | 3 +- lib/debugfs/debugfs.mk | 3 +- lib/debugfs/devc.c | 2 + lib/debugfs/devfip.c | 317 +++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 323 insertions(+), 2 deletions(-) create mode 100644 lib/debugfs/devfip.c diff --git a/lib/debugfs/blobs.h b/lib/debugfs/blobs.h index 4aa348153..54ca9f75d 100644 --- a/lib/debugfs/blobs.h +++ b/lib/debugfs/blobs.h @@ -7,5 +7,6 @@ #include "dev.h" static const dirtab_t blobtab[] = { - {"ctl", DEV_ROOT_QBLOBCTL, 0, O_READ} + {"ctl", DEV_ROOT_QBLOBCTL, 0, O_READ}, + {"fip.bin", DEV_ROOT_QBLOBCTL + 1, 0x100000, O_READ, (void *)0x8000000} }; diff --git a/lib/debugfs/debugfs.mk b/lib/debugfs/debugfs.mk index 030556aea..2c0260006 100644 --- a/lib/debugfs/debugfs.mk +++ b/lib/debugfs/debugfs.mk @@ -7,4 +7,5 @@ DEBUGFS_SRCS := $(addprefix lib/debugfs/, \ dev.c \ devc.c \ - devroot.c) + devroot.c \ + devfip.c) diff --git a/lib/debugfs/devc.c b/lib/debugfs/devc.c index 13c553d3e..1099a85d8 100644 --- a/lib/debugfs/devc.c +++ b/lib/debugfs/devc.c @@ -7,9 +7,11 @@ typedef struct dev dev_t; extern dev_t rootdevtab; +extern dev_t fipdevtab; dev_t *const devtab[] = { &rootdevtab, + &fipdevtab, 0 }; diff --git a/lib/debugfs/devfip.c b/lib/debugfs/devfip.c new file mode 100644 index 000000000..5581b219f --- /dev/null +++ b/lib/debugfs/devfip.c @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "dev.h" + +#define NR_FIPS 1 +#define STOC_HEADER (sizeof(fip_toc_header_t)) +#define STOC_ENTRY (sizeof(fip_toc_entry_t)) + +struct fipfile { + chan_t *c; + long offset[NR_FILES]; + long size[NR_FILES]; +}; + +struct fip_entry { + uuid_t uuid; + long long offset_address; + long long size; + long long flags; +}; + +struct uuidnames { + const char name[NAMELEN]; + const uuid_t uuid; +}; + +/******************************************************************************* + * This array links the FIP file names to their UUID. + * The elements are ordered according to the image number stored in + * tbbr_img_def.h, starting at index 1. + * + * TODO: this name to uuid binding will preferably be done using + * the coming Property Access Layer / Firmware CONFiguration feature. + ******************************************************************************/ +static const struct uuidnames uuidnames[] = { + {"", { {0}, {0}, {0}, 0, 0, {0} } }, + {"bl2.bin", UUID_TRUSTED_BOOT_FIRMWARE_BL2}, + {"scp-bl2.bin", UUID_SCP_FIRMWARE_SCP_BL2}, + {"bl31.bin", UUID_EL3_RUNTIME_FIRMWARE_BL31}, + {"bl32.bin", UUID_SECURE_PAYLOAD_BL32}, + {"bl33.bin", UUID_NON_TRUSTED_FIRMWARE_BL33}, + {"tb-fw.crt", UUID_TRUSTED_BOOT_FW_CERT}, + {"trstd-k.crt", UUID_TRUSTED_KEY_CERT}, + {"scp-fw-k.crt", UUID_SCP_FW_KEY_CERT}, + {"soc-fw-k.crt", UUID_SOC_FW_KEY_CERT}, + {"tos-fw-k.crt", UUID_TRUSTED_OS_FW_KEY_CERT}, + {"nt-fw-k.crt", UUID_NON_TRUSTED_FW_KEY_CERT}, + {"scp-fw-c.crt", UUID_SCP_FW_CONTENT_CERT}, + {"soc-fw-c.crt", UUID_SOC_FW_CONTENT_CERT}, + {"tos-fw-c.crt", UUID_TRUSTED_OS_FW_CONTENT_CERT}, + {"nt-fw-c.crt", UUID_NON_TRUSTED_FW_CONTENT_CERT}, + { }, + {"fwu.crt", UUID_TRUSTED_FWU_CERT}, + {"scp-bl2u.bin", UUID_TRUSTED_UPDATE_FIRMWARE_SCP_BL2U}, + {"bl2u.bin", UUID_TRUSTED_UPDATE_FIRMWARE_BL2U}, + {"ns-bl2u.bin", UUID_TRUSTED_UPDATE_FIRMWARE_NS_BL2U}, + {"bl32-xtr1.bin", UUID_SECURE_PAYLOAD_BL32_EXTRA1}, + {"bl32-xtr2.bin", UUID_SECURE_PAYLOAD_BL32_EXTRA2}, + {"hw.cfg", UUID_HW_CONFIG}, + {"tb-fw.cfg", UUID_TB_FW_CONFIG}, + {"soc-fw.cfg", UUID_SOC_FW_CONFIG}, + {"tos-fw.cfg", UUID_TOS_FW_CONFIG}, + {"nt-fw.cfg", UUID_NT_FW_CONFIG}, + {"rot-k.crt", UUID_ROT_KEY_CERT}, + {"nt-k.crt", UUID_NON_TRUSTED_WORLD_KEY_CERT} +}; + +/******************************************************************************* + * This array contains all the available FIP files. + ******************************************************************************/ +static struct fipfile archives[NR_FIPS]; + +/******************************************************************************* + * This variable stores the current number of registered FIP files. + ******************************************************************************/ +static int nfips; + +/******************************************************************************* + * This function parses the ToC of the FIP. + ******************************************************************************/ +static int get_entry(chan_t *c, struct fip_entry *entry) +{ + int n; + + n = devtab[c->index]->read(c, entry, sizeof(struct fip_entry)); + if (n <= 0) { + return n; + } + + if (n != sizeof(struct fip_entry)) { + return -1; + } + + if ((entry->size > LONG_MAX) || (entry->offset_address > LONG_MAX)) { + return -1; + } + + if (entry->size == 0) { + return 0; + } + + return 1; +} + +/******************************************************************************* + * This function exposes the FIP images as files. + ******************************************************************************/ +static int fipgen(chan_t *c, const dirtab_t *tab, int ntab, int n, dir_t *dir) +{ + int i, r; + long off; + chan_t nc; + struct fip_entry entry; + struct fipfile *fip; + static const char unk[] = "unknown"; + + if (c->dev >= nfips) { + panic(); + } + + clone(archives[c->dev].c, &nc); + fip = &archives[nc.dev]; + + off = STOC_HEADER; + for (i = 0; i <= n; i++) { + if (fip->offset[i] == -1) { + return 0; + } + + if (devtab[nc.index]->seek(&nc, off, KSEEK_SET) < 0) { + return -1; + } + + r = get_entry(&nc, &entry); + if (r <= 0) { + return r; + } + + off += sizeof(entry); + } + + for (i = 1; i < NELEM(uuidnames); i++) { + if (memcmp(&uuidnames[i].uuid, + &entry.uuid, sizeof(uuid_t)) == 0) { + break; + } + } + + if (i < NELEM(uuidnames)) { + make_dir_entry(c, dir, uuidnames[i].name, + entry.size, n, O_READ); + } else { + // TODO: set name depending on uuid node value + make_dir_entry(c, dir, unk, entry.size, n, O_READ); + } + + return 1; +} + +static int fipwalk(chan_t *c, const char *name) +{ + return devwalk(c, name, NULL, 0, fipgen); +} + +static int fipstat(chan_t *c, const char *file, dir_t *dir) +{ + return devstat(c, file, dir, NULL, 0, fipgen); +} + +/******************************************************************************* + * This function copies at most n bytes of the FIP image referred by c into + * buf. + ******************************************************************************/ +static int fipread(chan_t *c, void *buf, int n) +{ + long off; + chan_t cs; + struct fipfile *fip; + long size; + + /* Only makes sense when using debug language */ + assert(c->qid != CHDIR); + + if ((c->dev >= nfips) || ((c->qid & CHDIR) != 0)) { + panic(); + } + + fip = &archives[c->dev]; + + if ((c->qid >= NR_FILES) || (fip->offset[c->qid] < 0)) { + panic(); + } + + clone(fip->c, &cs); + + size = fip->size[c->qid]; + if (c->offset >= size) { + return 0; + } + + if (n < 0) { + return -1; + } + + if (n > (size - c->offset)) { + n = size - c->offset; + } + + off = fip->offset[c->qid] + c->offset; + if (devtab[cs.index]->seek(&cs, off, KSEEK_SET) < 0) { + return -1; + } + + n = devtab[cs.index]->read(&cs, buf, n); + if (n > 0) { + c->offset += n; + } + + return n; +} + +/******************************************************************************* + * This function parses the FIP spec and registers its images in order to + * expose them as files in the driver namespace. + * It acts as an initialization function for the FIP driver. + * It returns a pointer to the newly created channel. + ******************************************************************************/ +static chan_t *fipmount(chan_t *c, const char *spec) +{ + int r, n, t; + chan_t *cspec; + uint32_t hname; + struct fip_entry entry; + struct fipfile *fip; + dir_t dir; + + if (nfips == NR_FIPS) { + return NULL; + } + + fip = &archives[nfips]; + + for (n = 0; n < NR_FILES; n++) { + fip->offset[n] = -1; + } + + cspec = path_to_channel(spec, O_READ); + if (cspec == NULL) { + return NULL; + } + + fip->c = cspec; + + r = devtab[cspec->index]->read(cspec, &hname, sizeof(hname)); + if (r < 0) { + goto err; + } + + if ((r != sizeof(hname)) || (hname != TOC_HEADER_NAME)) { + goto err; + } + + if (stat(spec, &dir) < 0) { + goto err; + } + + t = cspec->index; + if (devtab[t]->seek(cspec, STOC_HEADER, KSEEK_SET) < 0) { + goto err; + } + + for (n = 0; n < NR_FILES; n++) { + switch (get_entry(cspec, &entry)) { + case 0: + return attach('F', nfips++); + case -1: + goto err; + default: + if ((entry.offset_address + entry.size) > dir.length) { + goto err; + } + + fip->offset[n] = entry.offset_address; + fip->size[n] = entry.size; + break; + } + } + +err: + channel_close(cspec); + return NULL; +} + +const dev_t fipdevtab = { + .id = 'F', + .stat = fipstat, + .clone = devclone, + .attach = devattach, + .walk = fipwalk, + .read = fipread, + .write = deverrwrite, + .mount = fipmount, + .seek = devseek +}; + -- cgit v1.2.3 From 68dd5e15ebb81cb85e2208fa77fc827d67bb7609 Mon Sep 17 00:00:00 2001 From: "Tien Hock, Loh" Date: Wed, 30 Oct 2019 14:54:25 +0800 Subject: plat: intel: Fix mailbox send_cmd issue There are a few issues in mailbox that needs to be fixed. - Send doorbell after an indirect cmd - Do not ring doorbell when polling mailbox response as it should've been sent by send_cmd - remove unneeded cmd_free_offset check - Fix mailbox initialization - Fix get_config_status returning a wrong status when the status is busy - Add command length in mailbox command header Signed-off-by: Tien Hock, Loh Change-Id: If613e2ca889a540a616c62d69ad0086a7cd46536 --- plat/intel/soc/common/include/socfpga_mailbox.h | 8 ++++- plat/intel/soc/common/soc/socfpga_mailbox.c | 47 ++++++++++++++++--------- 2 files changed, 37 insertions(+), 18 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 399ac57b8..55f9b0549 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -11,6 +11,7 @@ #define MBOX_OFFSET 0xffa30000 +#define MBOX_MAX_JOB_ID 0xf #define MBOX_ATF_CLIENT_ID 0x1 #define MBOX_JOB_ID 0x1 @@ -66,6 +67,9 @@ #define MBOX_CMD_GET_IDCODE 16 #define MBOX_CMD_QSPI_SET_CS 52 +/* Mailbox CANCEL command */ +#define MBOX_CMD_CANCEL 0x3 + /* Mailbox REBOOT commands */ #define MBOX_CMD_REBOOT_HPS 71 @@ -98,11 +102,13 @@ void mailbox_set_qspi_open(void); void mailbox_set_qspi_direct(void); int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent, uint32_t *response); -void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, +int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent); int mailbox_read_response(int job_id, uint32_t *response); int mailbox_get_qspi_clock(void); void mailbox_reset_cold(void); +void mailbox_clear_response(void); + uint32_t intel_mailbox_get_config_status(uint32_t cmd); #endif /* SOCFPGA_MBOX_H */ diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index b972c445e..cb3d08875 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -18,12 +18,6 @@ static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN); - if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) { - INFO("Insufficient buffer in mailbox\n"); - return MBOX_INSUFFICIENT_BUFFER; - } - - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + (cmd_free_offset++ * 4), header_cmd); @@ -109,7 +103,6 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response) int resp = 0; int total_resp_len = 0; - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); while (1) { while (timeout > 0 && @@ -159,7 +152,6 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response) response_length = MBOX_RESP_LEN(resp); while (response_length) { - response_length--; resp = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + @@ -177,9 +169,11 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response) } } -void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, +int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent) { + int timeout = 100000; + if (urgent) mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); @@ -188,29 +182,49 @@ void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, MBOX_CMD_LEN_CMD(len) | MBOX_INDIRECT | cmd, args, len); + + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); + + while (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { + if (timeout-- < 0) + return MBOX_NO_RESPONSE; + } + + return 0; } int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent, uint32_t *response) { - int status; + int status = 0; if (urgent) { urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & MBOX_STATUS_UA_MASK; mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd); - status = 0; - } else { + } + + else { status = fill_mailbox_circular_buffer( MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | MBOX_JOB_ID_CMD(job_id) | + MBOX_CMD_LEN_CMD(len) | cmd, args, len); } if (status) return status; - return mailbox_poll_response(job_id, urgent, response); + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); + status = mailbox_poll_response(job_id, urgent, response); + + return status; +} + +void mailbox_clear_response(void) +{ + mmio_write_32(MBOX_OFFSET + MBOX_ROUT, + mmio_read_32(MBOX_OFFSET + MBOX_RIN)); } void mailbox_set_int(int interrupt) @@ -267,14 +281,13 @@ int mailbox_init(void) mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE | MBOX_INT_FLAG_UAE); - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, 0); if (status) return status; - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); + mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE | + MBOX_INT_FLAG_UAE); return 0; } @@ -305,5 +318,5 @@ uint32_t intel_mailbox_get_config_status(uint32_t cmd) (res & SOFTFUNC_STATUS_INIT_DONE)) return INTEL_SIP_SMC_STATUS_OK; - return MBOX_CFGSTAT_STATE_CONFIG; + return INTEL_SIP_SMC_STATUS_BUSY; } -- cgit v1.2.3 From cefb37eb39f1d077b55cd3f00323c8bb215cfe30 Mon Sep 17 00:00:00 2001 From: "Tien Hock, Loh" Date: Wed, 30 Oct 2019 14:49:40 +0800 Subject: plat: intel: Fix FPGA manager on reconfiguration Fixes the SiP Service driver that is responsible for FPGA reconfiguration. Also change the base address of FPGA reconfiguration to 0x400000. Signed-off-by: Tien Hock, Loh Change-Id: I2b84c12c85cd5fc235247131fec4916ed2fb56c8 --- plat/intel/soc/common/include/socfpga_sip_svc.h | 2 +- plat/intel/soc/common/socfpga_sip_svc.c | 50 +++++++++++++++---------- 2 files changed, 32 insertions(+), 20 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index 33e7e1bcd..6bb41f31b 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -30,7 +30,7 @@ #define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F /* FPGA config helpers */ -#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x1000 +#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216 /* SMC function IDs for SiP Service queries */ diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 421fa44e3..4a09526b9 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -18,13 +18,14 @@ /* Total buffer the driver can hold */ #define FPGA_CONFIG_BUFFER_SIZE 4 -int current_block; -int current_buffer; -int current_id = 1; -int max_blocks; -uint32_t bytes_per_block; -uint32_t blocks_submitted; -uint32_t blocks_completed; +static int current_block; +static int read_block; +static int current_buffer; +static int send_id; +static int rcv_id; +static int max_blocks; +static uint32_t bytes_per_block; +static uint32_t blocks_submitted; struct fpga_config_info { uint32_t addr; @@ -68,7 +69,8 @@ static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) buffer->size_written += buffer->size - buffer->size_written; buffer->subblocks_sent++; - mailbox_send_cmd_async(0x4, + mailbox_send_cmd_async( + send_id++ % MBOX_MAX_JOB_ID, MBOX_RECONFIG_DATA, args, 3, 0); current_buffer++; @@ -78,7 +80,8 @@ static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) args[1] = buffer->addr + buffer->size_written; args[2] = bytes_per_block; buffer->size_written += bytes_per_block; - mailbox_send_cmd_async(0x4, + mailbox_send_cmd_async( + send_id++ % MBOX_MAX_JOB_ID, MBOX_RECONFIG_DATA, args, 3, 0); buffer->subblocks_sent++; @@ -134,6 +137,8 @@ unsigned int address_in_ddr(uint32_t *addr) return -1; } +int mailbox_poll_response(int job_id, int urgent, uint32_t *response); + int intel_fpga_config_completed_write(uint32_t *completed_addr, uint32_t *count) { @@ -142,30 +147,29 @@ int intel_fpga_config_completed_write(uint32_t *completed_addr, int resp_len = 0; uint32_t resp[5]; int all_completed = 1; - int count_check = 0; - if (address_in_ddr(completed_addr) != 0 || address_in_ddr(count) != 0) - return INTEL_SIP_SMC_STATUS_ERROR; + while (*count < 3) { - for (count_check = 0; count_check < 3; count_check++) - if (address_in_ddr(&completed_addr[*count + count_check]) != 0) - return INTEL_SIP_SMC_STATUS_ERROR; + resp_len = mailbox_read_response( + rcv_id % MBOX_MAX_JOB_ID, resp); - resp_len = mailbox_read_response(0x4, resp); + if (resp_len < 0) + break; - while (resp_len >= 0 && *count < 3) { max_blocks++; + rcv_id++; + if (mark_last_buffer_xfer_completed( &completed_addr[*count]) == 0) *count = *count + 1; else break; - resp_len = mailbox_read_response(0x4, resp); } if (*count <= 0) { if (resp_len != MBOX_NO_RESPONSE && resp_len != MBOX_TIMEOUT && resp_len != 0) { + mailbox_clear_response(); return INTEL_SIP_SMC_STATUS_ERROR; } @@ -197,7 +201,11 @@ int intel_fpga_config_start(uint32_t config_type) uint32_t response[3]; int status = 0; - status = mailbox_send_cmd(2, MBOX_RECONFIG, 0, 0, 0, + mailbox_clear_response(); + + mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, response); + + status = mailbox_send_cmd(1, MBOX_RECONFIG, 0, 0, 0, response); if (status < 0) @@ -217,7 +225,10 @@ int intel_fpga_config_start(uint32_t config_type) blocks_submitted = 0; current_block = 0; + read_block = 0; current_buffer = 0; + send_id = 0; + rcv_id = 0; return 0; } @@ -323,6 +334,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, SMC_RET4(handle, status, 0, 0, 0); break; default: + mailbox_clear_response(); SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); } break; -- cgit v1.2.3 From 8014a53ae08ee759fd6283fc2e81034abf1d30d7 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 12 Nov 2019 14:55:26 +0800 Subject: intel: Mailbox driver logic fixes Fix mailbox driver urgent command handling, doorbell routine, and logic optimization. Signed-off-by: Hadi Asyrafi Change-Id: If536a383f449ca2a68d60274303ec24f92411505 --- plat/intel/soc/common/soc/socfpga_mailbox.c | 35 +++++++++++------------------ 1 file changed, 13 insertions(+), 22 deletions(-) diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index cb3d08875..54add7a56 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -6,6 +6,7 @@ #include #include +#include #include "socfpga_mailbox.h" #include "socfpga_sip_svc.h" @@ -41,21 +42,14 @@ int mailbox_read_response(int job_id, uint32_t *response) int response_length = 0; int resp = 0; int total_resp_len = 0; - int timeout = 100000; - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - - while (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { - if (timeout-- < 0) - return MBOX_NO_RESPONSE; - } - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); + if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM)) + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); - while (rout != rin) { + if (rout != rin) { resp = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + ((rout++)*4)); @@ -96,22 +90,22 @@ int mailbox_read_response(int job_id, uint32_t *response) int mailbox_poll_response(int job_id, int urgent, uint32_t *response) { - int timeout = 80000; + int timeout = 0xFFFFFF; int rin = 0; int rout = 0; int response_length = 0; int resp = 0; int total_resp_len = 0; - while (1) { + while (timeout > 0 && - mmio_read_32(MBOX_OFFSET + - MBOX_DOORBELL_FROM_SDM) != 1) { + !(mmio_read_32(MBOX_OFFSET + + MBOX_DOORBELL_FROM_SDM) & 1)) { timeout--; } - if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { + if (!timeout) { INFO("Timed out waiting for SDM"); return MBOX_TIMEOUT; } @@ -119,6 +113,7 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response) mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); if (urgent & 1) { + mdelay(5); if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & MBOX_STATUS_UA_MASK) ^ (urgent & MBOX_STATUS_UA_MASK)) { @@ -172,8 +167,6 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response) int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent) { - int timeout = 100000; - if (urgent) mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); @@ -185,11 +178,6 @@ int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - while (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { - if (timeout-- < 0) - return MBOX_NO_RESPONSE; - } - return 0; } @@ -281,6 +269,9 @@ int mailbox_init(void) mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE | MBOX_INT_FLAG_UAE); + mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); + status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, 0); if (status) -- cgit v1.2.3 From b68ba6cc798f4dbc4c489fefc01f21b7ed9c79ce Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 12 Nov 2019 15:03:00 +0800 Subject: intel: Fix mailbox config return status Modify mailbox config return code to improve debugging. Signed-off-by: Hadi Asyrafi Change-Id: I0a223291f4c5296203b3295a679a5857a446c692 --- plat/intel/soc/common/include/socfpga_mailbox.h | 26 +++++++++++++++++-------- plat/intel/soc/common/soc/socfpga_mailbox.c | 12 ++++++------ 2 files changed, 24 insertions(+), 14 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 55f9b0549..20e0d44d3 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -79,14 +79,24 @@ #define MBOX_WRONG_ID -3 /* Mailbox status */ -#define RECONFIG_STATUS_STATE 0 -#define RECONFIG_STATUS_PIN_STATUS 2 -#define RECONFIG_STATUS_SOFTFUNC_STATUS 3 -#define PIN_STATUS_NSTATUS (U(1) << 31) -#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) -#define SOFTFUNC_STATUS_INIT_DONE (1 << 1) -#define SOFTFUNC_STATUS_CONF_DONE (1 << 0) -#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 +#define RECONFIG_STATUS_STATE 0 +#define RECONFIG_STATUS_PIN_STATUS 2 +#define RECONFIG_STATUS_SOFTFUNC_STATUS 3 +#define PIN_STATUS_NSTATUS (U(1) << 31) +#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) +#define SOFTFUNC_STATUS_INIT_DONE (1 << 1) +#define SOFTFUNC_STATUS_CONF_DONE (1 << 0) +#define MBOX_CFGSTAT_STATE_IDLE 0x00000000 +#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 +#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 +#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 +#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 +#define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 +#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 +#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 +#define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 +#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 +#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 /* Mailbox reconfiguration commands */ #define MBOX_CONFIG_STATUS 4 diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 54add7a56..bf18d7753 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -291,23 +291,23 @@ uint32_t intel_mailbox_get_config_status(uint32_t cmd) status = mailbox_send_cmd(1, cmd, NULL, 0, 0, response); if (status < 0) - return INTEL_SIP_SMC_STATUS_ERROR; + return status; res = response[RECONFIG_STATUS_STATE]; if (res && res != MBOX_CFGSTAT_STATE_CONFIG) - return INTEL_SIP_SMC_STATUS_ERROR; + return res; res = response[RECONFIG_STATUS_PIN_STATUS]; if (!(res & PIN_STATUS_NSTATUS)) - return INTEL_SIP_SMC_STATUS_ERROR; + return MBOX_CFGSTAT_STATE_ERROR_HARDWARE; res = response[RECONFIG_STATUS_SOFTFUNC_STATUS]; if (res & SOFTFUNC_STATUS_SEU_ERROR) - return INTEL_SIP_SMC_STATUS_ERROR; + return MBOX_CFGSTAT_STATE_ERROR_HARDWARE; if ((res & SOFTFUNC_STATUS_CONF_DONE) && (res & SOFTFUNC_STATUS_INIT_DONE)) - return INTEL_SIP_SMC_STATUS_OK; + return 0; - return INTEL_SIP_SMC_STATUS_BUSY; + return MBOX_CFGSTAT_STATE_CONFIG; } -- cgit v1.2.3 From 96612fcac4f674d78812bf7b1570a9113fe184bc Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 12 Nov 2019 16:39:46 +0800 Subject: intel: Introduce mailbox response length handling Mailbox driver now handles variable response length Signed-off-by: Hadi Asyrafi Change-Id: Ic96854fdaadaf48379c5de688392df974e1c99c3 --- plat/intel/soc/common/include/socfpga_mailbox.h | 4 +-- plat/intel/soc/common/soc/socfpga_mailbox.c | 33 ++++++++++++++----------- plat/intel/soc/common/socfpga_sip_svc.c | 8 +++--- 3 files changed, 25 insertions(+), 20 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 20e0d44d3..c5f2fbe77 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -111,10 +111,10 @@ void mailbox_set_qspi_close(void); void mailbox_set_qspi_open(void); void mailbox_set_qspi_direct(void); int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response); + int len, int urgent, uint32_t *response, int resp_len); int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent); -int mailbox_read_response(int job_id, uint32_t *response); +int mailbox_read_response(int job_id, uint32_t *response, int resp_len); int mailbox_get_qspi_clock(void); void mailbox_reset_cold(void); void mailbox_clear_response(void); diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index bf18d7753..eb35c4a08 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -35,7 +35,7 @@ static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, return 0; } -int mailbox_read_response(int job_id, uint32_t *response) +int mailbox_read_response(int job_id, uint32_t *response, int resp_len) { int rin = 0; int rout = 0; @@ -73,8 +73,9 @@ int mailbox_read_response(int job_id, uint32_t *response) resp = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + (rout)*4); - if (response) { + if (response && resp_len) { *(response + total_resp_len) = resp; + resp_len--; total_resp_len++; } rout++; @@ -88,7 +89,8 @@ int mailbox_read_response(int job_id, uint32_t *response) } -int mailbox_poll_response(int job_id, int urgent, uint32_t *response) +int mailbox_poll_response(int job_id, int urgent, uint32_t *response, + int resp_len) { int timeout = 0xFFFFFF; int rin = 0; @@ -151,8 +153,9 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response) resp = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + (rout)*4); - if (response) { + if (response && resp_len) { *(response + total_resp_len) = resp; + resp_len--; total_resp_len++; } rout++; @@ -182,7 +185,7 @@ int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, } int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response) + int len, int urgent, uint32_t *response, int resp_len) { int status = 0; @@ -204,7 +207,7 @@ int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, return status; mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - status = mailbox_poll_response(job_id, urgent, response); + status = mailbox_poll_response(job_id, urgent, response, resp_len); return status; } @@ -226,24 +229,25 @@ void mailbox_set_int(int interrupt) void mailbox_set_qspi_open(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, NULL, 0); } void mailbox_set_qspi_direct(void) { - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, NULL, 0); } void mailbox_set_qspi_close(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, NULL, 0); } int mailbox_get_qspi_clock(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); + return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, + NULL, 0); } void mailbox_qspi_set_cs(int device_select) @@ -254,13 +258,13 @@ void mailbox_qspi_set_cs(int device_select) cs_setting = (cs_setting << 28); mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting, - 1, 0, 0); + 1, 0, NULL, 0); } void mailbox_reset_cold(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, NULL, 0); } int mailbox_init(void) @@ -272,7 +276,7 @@ int mailbox_init(void) mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, 0); + status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, NULL, 0); if (status) return status; @@ -288,7 +292,8 @@ uint32_t intel_mailbox_get_config_status(uint32_t cmd) uint32_t status, res; uint32_t response[6]; - status = mailbox_send_cmd(1, cmd, NULL, 0, 0, response); + status = mailbox_send_cmd(1, cmd, NULL, 0, 0, response, + sizeof(response) / sizeof(response[0])); if (status < 0) return status; diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 4a09526b9..2f5305d11 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -150,8 +150,8 @@ int intel_fpga_config_completed_write(uint32_t *completed_addr, while (*count < 3) { - resp_len = mailbox_read_response( - rcv_id % MBOX_MAX_JOB_ID, resp); + resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID, + resp, sizeof(resp) / sizeof(resp[0])); if (resp_len < 0) break; @@ -203,10 +203,10 @@ int intel_fpga_config_start(uint32_t config_type) mailbox_clear_response(); - mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, response); + mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0); status = mailbox_send_cmd(1, MBOX_RECONFIG, 0, 0, 0, - response); + response, sizeof(response) / sizeof(response[0])); if (status < 0) return status; -- cgit v1.2.3 From 7c58fd4ee31cfabcce7aeedac6310a0009c639ab Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 12 Nov 2019 16:29:03 +0800 Subject: intel: Fix SMC SIP service Fix FPGA reconfiguration driver logic Signed-off-by: Hadi Asyrafi Change-Id: I0299c1a71f3456e9b441340314662494b8d3e4a0 --- plat/intel/soc/common/socfpga_sip_svc.c | 125 ++++++++++++++++---------------- 1 file changed, 62 insertions(+), 63 deletions(-) diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 2f5305d11..c3c6ae034 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -56,54 +56,54 @@ uint64_t socfpga_sip_handler(uint32_t smc_fid, struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; -static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) +static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) { uint32_t args[3]; while (max_blocks > 0 && buffer->size > buffer->size_written) { - if (buffer->size - buffer->size_written <= - bytes_per_block) { - args[0] = (1<<8); - args[1] = buffer->addr + buffer->size_written; + args[0] = (1<<8); + args[1] = buffer->addr + buffer->size_written; + if (buffer->size - buffer->size_written <= bytes_per_block) { args[2] = buffer->size - buffer->size_written; - buffer->size_written += - buffer->size - buffer->size_written; - buffer->subblocks_sent++; - mailbox_send_cmd_async( - send_id++ % MBOX_MAX_JOB_ID, - MBOX_RECONFIG_DATA, - args, 3, 0); current_buffer++; current_buffer %= FPGA_CONFIG_BUFFER_SIZE; - } else { - args[0] = (1<<8); - args[1] = buffer->addr + buffer->size_written; + } else args[2] = bytes_per_block; - buffer->size_written += bytes_per_block; - mailbox_send_cmd_async( - send_id++ % MBOX_MAX_JOB_ID, - MBOX_RECONFIG_DATA, - args, 3, 0); - buffer->subblocks_sent++; - } + + buffer->size_written += args[2]; + mailbox_send_cmd_async( + send_id++ % MBOX_MAX_JOB_ID, + MBOX_RECONFIG_DATA, + args, 3, 0); + + buffer->subblocks_sent++; max_blocks--; } + + return !max_blocks; } static int intel_fpga_sdm_write_all(void) { - int i; - - for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) - intel_fpga_sdm_write_buffer( - &fpga_config_buffers[current_buffer]); - + for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) + if (intel_fpga_sdm_write_buffer( + &fpga_config_buffers[current_buffer])) + break; return 0; } uint32_t intel_mailbox_fpga_config_isdone(void) { - return intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); + uint32_t ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); + + if (ret) { + if (ret == MBOX_CFGSTAT_STATE_CONFIG) + return INTEL_SIP_SMC_STATUS_BUSY; + else + return INTEL_SIP_SMC_STATUS_ERROR; + } + + return INTEL_SIP_SMC_STATUS_OK; } static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) @@ -128,17 +128,6 @@ static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) return -1; } -unsigned int address_in_ddr(uint32_t *addr) -{ - if (((unsigned long long)addr > DRAM_BASE) && - ((unsigned long long)addr < DRAM_BASE + DRAM_SIZE)) - return 0; - - return -1; -} - -int mailbox_poll_response(int job_id, int urgent, uint32_t *response); - int intel_fpga_config_completed_write(uint32_t *completed_addr, uint32_t *count) { @@ -233,42 +222,52 @@ int intel_fpga_config_start(uint32_t config_type) return 0; } +static bool is_fpga_config_buffer_full(void) +{ + for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) + if (!fpga_config_buffers[i].write_requested) + return false; + return true; +} + +static bool is_address_in_ddr_range(uint64_t addr) +{ + if (addr >= DRAM_BASE && addr <= DRAM_BASE + DRAM_SIZE) + return true; + + return false; +} uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) { - int i = 0; - uint32_t status = INTEL_SIP_SMC_STATUS_OK; + int i; - if (mem < DRAM_BASE || mem > DRAM_BASE + DRAM_SIZE) - status = INTEL_SIP_SMC_STATUS_REJECTED; + intel_fpga_sdm_write_all(); - if (mem + size > DRAM_BASE + DRAM_SIZE) - status = INTEL_SIP_SMC_STATUS_REJECTED; + if (!is_address_in_ddr_range(mem) || + !is_address_in_ddr_range(mem + size) || + is_fpga_config_buffer_full()) + return INTEL_SIP_SMC_STATUS_REJECTED; for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - if (!fpga_config_buffers[i].write_requested) { - fpga_config_buffers[i].addr = mem; - fpga_config_buffers[i].size = size; - fpga_config_buffers[i].size_written = 0; - fpga_config_buffers[i].write_requested = 1; - fpga_config_buffers[i].block_number = + int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; + + if (!fpga_config_buffers[j].write_requested) { + fpga_config_buffers[j].addr = mem; + fpga_config_buffers[j].size = size; + fpga_config_buffers[j].size_written = 0; + fpga_config_buffers[j].write_requested = 1; + fpga_config_buffers[j].block_number = blocks_submitted++; - fpga_config_buffers[i].subblocks_sent = 0; + fpga_config_buffers[j].subblocks_sent = 0; break; } } + if (is_fpga_config_buffer_full()) + return INTEL_SIP_SMC_STATUS_BUSY; - if (i == FPGA_CONFIG_BUFFER_SIZE) { - status = INTEL_SIP_SMC_STATUS_REJECTED; - return status; - } else if (i == FPGA_CONFIG_BUFFER_SIZE - 1) { - status = INTEL_SIP_SMC_STATUS_BUSY; - } - - intel_fpga_sdm_write_all(); - - return status; + return INTEL_SIP_SMC_STATUS_OK; } /* -- cgit v1.2.3 From 4c4cff6b6fc9d603101c00fb3f1addc4ab80bcd5 Mon Sep 17 00:00:00 2001 From: Simon South Date: Sun, 20 Oct 2019 15:20:19 -0400 Subject: rockchip: rk3328: Enable workaround for erratum 855873 Enable the workaround for Cortex-A53 erratum 855873 for the Rockchip RK3328, silencing a warning at startup. Change-Id: I5aa29d674d23c096c599abcb5e7dac970f9607d8 Signed-off-by: Simon South --- plat/rockchip/rk3328/platform.mk | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk index 0c5cfae9b..0219422f9 100644 --- a/plat/rockchip/rk3328/platform.mk +++ b/plat/rockchip/rk3328/platform.mk @@ -59,6 +59,9 @@ endif include lib/coreboot/coreboot.mk include lib/libfdt/libfdt.mk +# Enable workarounds for selected Cortex-A53 errata +ERRATA_A53_855873 := 1 + $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) $(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER)) -- cgit v1.2.3 From 9d7251918d338585f74a9122f904d1c0aafdf0f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bence=20Sz=C3=A9pk=C3=BAti?= Date: Thu, 24 Oct 2019 15:53:23 +0200 Subject: SiP: Don't validate entrypoint if state switch is impossible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switching execution states is only possible if EL3 is AArch64. As such there is no need to validate the entrypoint on AArch32 builds. Signed-off-by: Bence Szépkúti Change-Id: I3c1eb25b5df296a492870641d274bf65213c6608 --- plat/arm/common/aarch64/execution_state_switch.c | 181 +++++++++++++++++++++++ plat/arm/common/arm_common.mk | 6 +- plat/arm/common/arm_sip_svc.c | 15 +- plat/arm/common/execution_state_switch.c | 179 ---------------------- 4 files changed, 192 insertions(+), 189 deletions(-) create mode 100644 plat/arm/common/aarch64/execution_state_switch.c delete mode 100644 plat/arm/common/execution_state_switch.c diff --git a/plat/arm/common/aarch64/execution_state_switch.c b/plat/arm/common/aarch64/execution_state_switch.c new file mode 100644 index 000000000..8835fa135 --- /dev/null +++ b/plat/arm/common/aarch64/execution_state_switch.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Handle SMC from a lower exception level to switch its execution state + * (either from AArch64 to AArch32, or vice versa). + * + * smc_fid: + * SMC function ID - either ARM_SIP_SVC_STATE_SWITCH_64 or + * ARM_SIP_SVC_STATE_SWITCH_32. + * pc_hi, pc_lo: + * PC upon re-entry to the calling exception level; width dependent on the + * calling exception level. + * cookie_hi, cookie_lo: + * Opaque pointer pairs received from the caller to pass it back, upon + * re-entry. + * handle: + * Handle to saved context. + */ +int arm_execution_state_switch(unsigned int smc_fid, + uint32_t pc_hi, + uint32_t pc_lo, + uint32_t cookie_hi, + uint32_t cookie_lo, + void *handle) +{ + bool caller_64, thumb = false, from_el2; + unsigned int el, endianness; + u_register_t spsr, pc, scr, sctlr; + entry_point_info_t ep; + cpu_context_t *ctx = (cpu_context_t *) handle; + el3_state_t *el3_ctx = get_el3state_ctx(ctx); + + /* Validate supplied entry point */ + pc = (u_register_t) (((uint64_t) pc_hi << 32) | pc_lo); + if (arm_validate_ns_entrypoint(pc) != 0) + goto invalid_param; + + /* That the SMC originated from NS is already validated by the caller */ + + /* + * Disallow state switch if any of the secondaries have been brought up. + */ + if (psci_secondaries_brought_up() != 0) + goto exec_denied; + + spsr = read_ctx_reg(el3_ctx, CTX_SPSR_EL3); + caller_64 = (GET_RW(spsr) == MODE_RW_64); + + if (caller_64) { + /* + * If the call originated from AArch64, expect 32-bit pointers when + * switching to AArch32. + */ + if ((pc_hi != 0U) || (cookie_hi != 0U)) + goto invalid_param; + + pc = pc_lo; + + /* Instruction state when entering AArch32 */ + thumb = (pc & 1U) != 0U; + } else { + /* Construct AArch64 PC */ + pc = (((u_register_t) pc_hi) << 32) | pc_lo; + } + + /* Make sure PC is 4-byte aligned, except for Thumb */ + if (((pc & 0x3U) != 0U) && !thumb) + goto invalid_param; + + /* + * EL3 controls register width of the immediate lower EL only. Expect + * this request from EL2/Hyp unless: + * + * - EL2 is not implemented; + * - EL2 is implemented, but was disabled. This can be inferred from + * SCR_EL3.HCE. + */ + from_el2 = caller_64 ? (GET_EL(spsr) == MODE_EL2) : + (GET_M32(spsr) == MODE32_hyp); + scr = read_ctx_reg(el3_ctx, CTX_SCR_EL3); + if (!from_el2) { + /* The call is from NS privilege level other than HYP */ + + /* + * Disallow switching state if there's a Hypervisor in place; + * this request must be taken up with the Hypervisor instead. + */ + if ((scr & SCR_HCE_BIT) != 0U) + goto exec_denied; + } + + /* + * Return to the caller using the same endianness. Extract + * endianness bit from the respective system control register + * directly. + */ + sctlr = from_el2 ? read_sctlr_el2() : read_sctlr_el1(); + endianness = ((sctlr & SCTLR_EE_BIT) != 0U) ? 1U : 0U; + + /* Construct SPSR for the exception state we're about to switch to */ + if (caller_64) { + unsigned long long impl; + + /* + * Switching from AArch64 to AArch32. Ensure this CPU implements + * the target EL in AArch32. + */ + impl = from_el2 ? el_implemented(2) : el_implemented(1); + if (impl != EL_IMPL_A64_A32) + goto exec_denied; + + /* Return to the equivalent AArch32 privilege level */ + el = from_el2 ? MODE32_hyp : MODE32_svc; + spsr = SPSR_MODE32((u_register_t) el, + thumb ? SPSR_T_THUMB : SPSR_T_ARM, + endianness, DISABLE_ALL_EXCEPTIONS); + } else { + /* + * Switching from AArch32 to AArch64. Since it's not possible to + * implement an EL as AArch32-only (from which this call was + * raised), it's safe to assume AArch64 is also implemented. + */ + el = from_el2 ? MODE_EL2 : MODE_EL1; + spsr = SPSR_64((u_register_t) el, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + } + + /* + * Use the context management library to re-initialize the existing + * context with the execution state flipped. Since the library takes + * entry_point_info_t pointer as the argument, construct a dummy one + * with PC, state width, endianness, security etc. appropriately set. + * Other entries in the entry point structure are irrelevant for + * purpose. + */ + zeromem(&ep, sizeof(ep)); + ep.pc = pc; + ep.spsr = (uint32_t) spsr; + SET_PARAM_HEAD(&ep, PARAM_EP, VERSION_1, + ((unsigned int) ((endianness != 0U) ? EP_EE_BIG : + EP_EE_LITTLE) + | NON_SECURE | EP_ST_DISABLE)); + + /* + * Re-initialize the system register context, and exit EL3 as if for the + * first time. State switch is effectively a soft reset of the + * calling EL. + */ + cm_init_my_context(&ep); + cm_prepare_el3_exit(NON_SECURE); + + /* + * State switch success. The caller of SMC wouldn't see the SMC + * returning. Instead, execution starts at the supplied entry point, + * with context pointers populated in registers 0 and 1. + */ + SMC_RET2(handle, cookie_hi, cookie_lo); + +invalid_param: + SMC_RET1(handle, STATE_SW_E_PARAM); + +exec_denied: + /* State switch denied */ + SMC_RET1(handle, STATE_SW_E_DENIED); +} diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index acc379797..ccb851e9d 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -215,13 +215,15 @@ BL2U_SOURCES += drivers/delay_timer/delay_timer.c \ BL31_SOURCES += plat/arm/common/arm_bl31_setup.c \ plat/arm/common/arm_pm.c \ plat/arm/common/arm_topology.c \ - plat/arm/common/execution_state_switch.c \ plat/common/plat_psci_common.c ifeq (${ENABLE_PMF}, 1) -BL31_SOURCES += plat/arm/common/arm_sip_svc.c \ +ifeq (${ARCH}, aarch64) +BL31_SOURCES += plat/arm/common/aarch64/execution_state_switch.c\ + plat/arm/common/arm_sip_svc.c \ lib/pmf/pmf_smc.c endif +endif ifeq (${EL3_EXCEPTION_HANDLING},1) BL31_SOURCES += plat/arm/common/aarch64/arm_ehf.c diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c index 3d308a335..a61f5f8bb 100644 --- a/plat/arm/common/arm_sip_svc.c +++ b/plat/arm/common/arm_sip_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -50,23 +50,22 @@ static uintptr_t arm_sip_handler(unsigned int smc_fid, switch (smc_fid) { case ARM_SIP_SVC_EXE_STATE_SWITCH: { - u_register_t pc; - + /* Execution state can be switched only if EL3 is AArch64 */ +#ifdef __aarch64__ /* Allow calls from non-secure only */ if (!is_caller_non_secure(flags)) SMC_RET1(handle, STATE_SW_E_DENIED); - /* Validate supplied entry point */ - pc = (u_register_t) ((x1 << 32) | (uint32_t) x2); - if (arm_validate_ns_entrypoint(pc) != 0) - SMC_RET1(handle, STATE_SW_E_PARAM); - /* * Pointers used in execution state switch are all 32 bits wide */ return (uintptr_t) arm_execution_state_switch(smc_fid, (uint32_t) x1, (uint32_t) x2, (uint32_t) x3, (uint32_t) x4, handle); +#else + /* State switch denied */ + SMC_RET1(handle, STATE_SW_E_DENIED); +#endif /* __aarch64__ */ } case ARM_SIP_SVC_CALL_COUNT: diff --git a/plat/arm/common/execution_state_switch.c b/plat/arm/common/execution_state_switch.c deleted file mode 100644 index 00ac16ef0..000000000 --- a/plat/arm/common/execution_state_switch.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Handle SMC from a lower exception level to switch its execution state - * (either from AArch64 to AArch32, or vice versa). - * - * smc_fid: - * SMC function ID - either ARM_SIP_SVC_STATE_SWITCH_64 or - * ARM_SIP_SVC_STATE_SWITCH_32. - * pc_hi, pc_lo: - * PC upon re-entry to the calling exception level; width dependent on the - * calling exception level. - * cookie_hi, cookie_lo: - * Opaque pointer pairs received from the caller to pass it back, upon - * re-entry. - * handle: - * Handle to saved context. - */ -int arm_execution_state_switch(unsigned int smc_fid, - uint32_t pc_hi, - uint32_t pc_lo, - uint32_t cookie_hi, - uint32_t cookie_lo, - void *handle) -{ - /* Execution state can be switched only if EL3 is AArch64 */ -#ifdef __aarch64__ - bool caller_64, thumb = false, from_el2; - unsigned int el, endianness; - u_register_t spsr, pc, scr, sctlr; - entry_point_info_t ep; - cpu_context_t *ctx = (cpu_context_t *) handle; - el3_state_t *el3_ctx = get_el3state_ctx(ctx); - - /* That the SMC originated from NS is already validated by the caller */ - - /* - * Disallow state switch if any of the secondaries have been brought up. - */ - if (psci_secondaries_brought_up() != 0) - goto exec_denied; - - spsr = read_ctx_reg(el3_ctx, CTX_SPSR_EL3); - caller_64 = (GET_RW(spsr) == MODE_RW_64); - - if (caller_64) { - /* - * If the call originated from AArch64, expect 32-bit pointers when - * switching to AArch32. - */ - if ((pc_hi != 0U) || (cookie_hi != 0U)) - goto invalid_param; - - pc = pc_lo; - - /* Instruction state when entering AArch32 */ - thumb = (pc & 1U) != 0U; - } else { - /* Construct AArch64 PC */ - pc = (((u_register_t) pc_hi) << 32) | pc_lo; - } - - /* Make sure PC is 4-byte aligned, except for Thumb */ - if (((pc & 0x3U) != 0U) && !thumb) - goto invalid_param; - - /* - * EL3 controls register width of the immediate lower EL only. Expect - * this request from EL2/Hyp unless: - * - * - EL2 is not implemented; - * - EL2 is implemented, but was disabled. This can be inferred from - * SCR_EL3.HCE. - */ - from_el2 = caller_64 ? (GET_EL(spsr) == MODE_EL2) : - (GET_M32(spsr) == MODE32_hyp); - scr = read_ctx_reg(el3_ctx, CTX_SCR_EL3); - if (!from_el2) { - /* The call is from NS privilege level other than HYP */ - - /* - * Disallow switching state if there's a Hypervisor in place; - * this request must be taken up with the Hypervisor instead. - */ - if ((scr & SCR_HCE_BIT) != 0U) - goto exec_denied; - } - - /* - * Return to the caller using the same endianness. Extract - * endianness bit from the respective system control register - * directly. - */ - sctlr = from_el2 ? read_sctlr_el2() : read_sctlr_el1(); - endianness = ((sctlr & SCTLR_EE_BIT) != 0U) ? 1U : 0U; - - /* Construct SPSR for the exception state we're about to switch to */ - if (caller_64) { - unsigned long long impl; - - /* - * Switching from AArch64 to AArch32. Ensure this CPU implements - * the target EL in AArch32. - */ - impl = from_el2 ? el_implemented(2) : el_implemented(1); - if (impl != EL_IMPL_A64_A32) - goto exec_denied; - - /* Return to the equivalent AArch32 privilege level */ - el = from_el2 ? MODE32_hyp : MODE32_svc; - spsr = SPSR_MODE32((u_register_t) el, - thumb ? SPSR_T_THUMB : SPSR_T_ARM, - endianness, DISABLE_ALL_EXCEPTIONS); - } else { - /* - * Switching from AArch32 to AArch64. Since it's not possible to - * implement an EL as AArch32-only (from which this call was - * raised), it's safe to assume AArch64 is also implemented. - */ - el = from_el2 ? MODE_EL2 : MODE_EL1; - spsr = SPSR_64((u_register_t) el, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); - } - - /* - * Use the context management library to re-initialize the existing - * context with the execution state flipped. Since the library takes - * entry_point_info_t pointer as the argument, construct a dummy one - * with PC, state width, endianness, security etc. appropriately set. - * Other entries in the entry point structure are irrelevant for - * purpose. - */ - zeromem(&ep, sizeof(ep)); - ep.pc = pc; - ep.spsr = (uint32_t) spsr; - SET_PARAM_HEAD(&ep, PARAM_EP, VERSION_1, - ((unsigned int) ((endianness != 0U) ? EP_EE_BIG : - EP_EE_LITTLE) - | NON_SECURE | EP_ST_DISABLE)); - - /* - * Re-initialize the system register context, and exit EL3 as if for the - * first time. State switch is effectively a soft reset of the - * calling EL. - */ - cm_init_my_context(&ep); - cm_prepare_el3_exit(NON_SECURE); - - /* - * State switch success. The caller of SMC wouldn't see the SMC - * returning. Instead, execution starts at the supplied entry point, - * with context pointers populated in registers 0 and 1. - */ - SMC_RET2(handle, cookie_hi, cookie_lo); - -invalid_param: - SMC_RET1(handle, STATE_SW_E_PARAM); - -exec_denied: -#endif /* __aarch64__ */ - /* State switch denied */ - SMC_RET1(handle, STATE_SW_E_DENIED); -} -- cgit v1.2.3 From 0531ada53798d7e700410c96f1889069c35127b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bence=20Sz=C3=A9pk=C3=BAti?= Date: Thu, 7 Nov 2019 12:09:24 +0100 Subject: pmf: Make the runtime instrumentation work on AArch32 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Ported the pmf asm macros and the asm code in the bl31 entrypoint necessary for the instrumentation to AArch32. Since smc dispatch is handled by the bl32 payload on AArch32, we provide this service only if AARCH32_SP=sp_min is set. Signed-off-by: Bence Szépkúti Change-Id: Id33b7e9762ae86a4f4b40d7f1b37a90e5130c8ac --- bl31/aarch64/bl31_entrypoint.S | 2 +- bl32/sp_min/aarch32/entrypoint.S | 68 ++++++++++++++++++++++++++++++++ bl32/sp_min/sp_min.ld.S | 8 ++++ bl32/sp_min/sp_min_main.c | 7 ++++ include/lib/pmf/aarch32/pmf_asm_macros.S | 28 +++++++++++++ include/lib/pmf/aarch64/pmf_asm_macros.S | 30 ++++++++++++++ include/lib/pmf/pmf_asm_macros.S | 30 -------------- plat/arm/common/arm_common.mk | 3 ++ 8 files changed, 145 insertions(+), 31 deletions(-) create mode 100644 include/lib/pmf/aarch32/pmf_asm_macros.S create mode 100644 include/lib/pmf/aarch64/pmf_asm_macros.S delete mode 100644 include/lib/pmf/pmf_asm_macros.S diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 74b0993f3..665a05e88 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index 0a684754c..f3a1e440b 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -10,6 +10,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -164,6 +167,20 @@ func sp_min_handle_smc /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */ str lr, [sp, #SMC_CTX_LR_MON] +#if ENABLE_RUNTIME_INSTRUMENTATION + /* + * Read the timestamp value and store it on top of the C runtime stack. + * The value will be saved to the per-cpu data once the C stack is + * available, as a valid stack is needed to call _cpu_data() + */ + strd r0, r1, [sp, #SMC_CTX_GPREG_R0] + ldcopr16 r0, r1, CNTPCT_64 + ldr lr, [sp, #SMC_CTX_SP_MON] + strd r0, r1, [lr, #-8]! + str lr, [sp, #SMC_CTX_SP_MON] + ldrd r0, r1, [sp, #SMC_CTX_GPREG_R0] +#endif + smccc_save_gp_mode_regs clrex_on_monitor_entry @@ -175,6 +192,23 @@ func sp_min_handle_smc mov r2, sp /* handle */ ldr sp, [r2, #SMC_CTX_SP_MON] +#if ENABLE_RUNTIME_INSTRUMENTATION + /* Save handle to a callee saved register */ + mov r6, r2 + + /* + * Restore the timestamp value and store it in per-cpu data. The value + * will be extracted from per-cpu data by the C level SMC handler and + * saved to the PMF timestamp region. + */ + ldrd r4, r5, [sp], #8 + bl _cpu_data + strd r4, r5, [r0, #CPU_DATA_PMF_TS0_OFFSET] + + /* Restore handle */ + mov r2, r6 +#endif + ldr r0, [r2, #SMC_CTX_SCR] and r3, r0, #SCR_NS_BIT /* flags */ @@ -239,6 +273,16 @@ endfunc sp_min_handle_fiq * The Warm boot entrypoint for SP_MIN. */ func sp_min_warm_entrypoint +#if ENABLE_RUNTIME_INSTRUMENTATION + /* + * This timestamp update happens with cache off. The next + * timestamp collection will need to do cache maintenance prior + * to timestamp update. + */ + pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR + ldcopr16 r2, r3, CNTPCT_64 + strd r2, r3, [r0] +#endif /* * On the warm boot path, most of the EL3 initialisations performed by * 'el3_entrypoint_common' must be skipped: @@ -295,6 +339,30 @@ func sp_min_warm_entrypoint bl smc_get_next_ctx /* r0 points to `smc_ctx_t` */ /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */ + +#if ENABLE_RUNTIME_INSTRUMENTATION + /* Save smc_ctx_t */ + mov r5, r0 + + pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI + mov r4, r0 + + /* + * Invalidate before updating timestamp to ensure previous timestamp + * updates on the same cache line with caches disabled are properly + * seen by the same core. Without the cache invalidate, the core might + * write into a stale cache line. + */ + mov r1, #PMF_TS_SIZE + bl inv_dcache_range + + ldcopr16 r0, r1, CNTPCT_64 + strd r0, r1, [r4] + + /* Restore smc_ctx_t */ + mov r0, r5 +#endif + b sp_min_exit endfunc sp_min_warm_entrypoint diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S index 4559903bf..6997a7fdb 100644 --- a/bl32/sp_min/sp_min.ld.S +++ b/bl32/sp_min/sp_min.ld.S @@ -55,6 +55,14 @@ SECTIONS KEEP(*(rt_svc_descs)) __RT_SVC_DESCS_END__ = .; +#if ENABLE_PMF + /* Ensure 4-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(4); + __PMF_SVC_DESCS_START__ = .; + KEEP(*(pmf_svc_descs)) + __PMF_SVC_DESCS_END__ = .; +#endif /* ENABLE_PMF */ + /* * Ensure 4-byte alignment for cpu_ops so that its fields are also * aligned. Also ensure cpu_ops inclusion. diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c index f39e33b6b..f050160f3 100644 --- a/bl32/sp_min/sp_min_main.c +++ b/bl32/sp_min/sp_min_main.c @@ -19,7 +19,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -28,6 +30,11 @@ #include "sp_min_private.h" +#if ENABLE_RUNTIME_INSTRUMENTATION +PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID, + RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE) +#endif + /* Pointers to per-core cpu contexts */ static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT]; diff --git a/include/lib/pmf/aarch32/pmf_asm_macros.S b/include/lib/pmf/aarch32/pmf_asm_macros.S new file mode 100644 index 000000000..1dbb408ca --- /dev/null +++ b/include/lib/pmf/aarch32/pmf_asm_macros.S @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMF_ASM_MACROS_S +#define PMF_ASM_MACROS_S + +#define PMF_TS_SIZE 8 + + /* + * This macro calculates the address of the per-cpu timestamp + * for the given service name and local timestamp id. + * Clobbers: r0 - r4 + */ + .macro pmf_calc_timestamp_addr _name, _tid + mov r4, lr + bl plat_my_core_pos + mov lr, r4 + ldr r1, =__PERCPU_TIMESTAMP_SIZE__ + mov r2, #(\_tid * PMF_TS_SIZE) + mla r0, r0, r1, r2 + ldr r1, =pmf_ts_mem_\_name + add r0, r0, r1 + .endm + +#endif /* PMF_ASM_MACROS_S */ diff --git a/include/lib/pmf/aarch64/pmf_asm_macros.S b/include/lib/pmf/aarch64/pmf_asm_macros.S new file mode 100644 index 000000000..5f3e6b7ec --- /dev/null +++ b/include/lib/pmf/aarch64/pmf_asm_macros.S @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMF_ASM_MACROS_S +#define PMF_ASM_MACROS_S + +#define PMF_TS_SIZE 8 + + /* + * This macro calculates the address of the per-cpu timestamp + * for the given service name and local timestamp id. + * Clobbers: x0 - x9 + */ + .macro pmf_calc_timestamp_addr _name, _tid + mov x9, x30 + bl plat_my_core_pos + mov x30, x9 + adr x2, __PMF_PERCPU_TIMESTAMP_END__ + adr x1, __PMF_TIMESTAMP_START__ + sub x1, x2, x1 + mov x2, #(\_tid * PMF_TS_SIZE) + madd x0, x0, x1, x2 + adr x1, pmf_ts_mem_\_name + add x0, x0, x1 + .endm + +#endif /* PMF_ASM_MACROS_S */ diff --git a/include/lib/pmf/pmf_asm_macros.S b/include/lib/pmf/pmf_asm_macros.S deleted file mode 100644 index 5f3e6b7ec..000000000 --- a/include/lib/pmf/pmf_asm_macros.S +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PMF_ASM_MACROS_S -#define PMF_ASM_MACROS_S - -#define PMF_TS_SIZE 8 - - /* - * This macro calculates the address of the per-cpu timestamp - * for the given service name and local timestamp id. - * Clobbers: x0 - x9 - */ - .macro pmf_calc_timestamp_addr _name, _tid - mov x9, x30 - bl plat_my_core_pos - mov x30, x9 - adr x2, __PMF_PERCPU_TIMESTAMP_END__ - adr x1, __PMF_TIMESTAMP_START__ - sub x1, x2, x1 - mov x2, #(\_tid * PMF_TS_SIZE) - madd x0, x0, x1, x2 - adr x1, pmf_ts_mem_\_name - add x0, x0, x1 - .endm - -#endif /* PMF_ASM_MACROS_S */ diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index ccb851e9d..cda39b7d2 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -222,6 +222,9 @@ ifeq (${ARCH}, aarch64) BL31_SOURCES += plat/arm/common/aarch64/execution_state_switch.c\ plat/arm/common/arm_sip_svc.c \ lib/pmf/pmf_smc.c +else +BL32_SOURCES += plat/arm/common/arm_sip_svc.c \ + lib/pmf/pmf_smc.c endif endif -- cgit v1.2.3 From e9e19fb2fe684a740afc4820b3ee4cc38ad67d70 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 17 Dec 2019 11:49:00 -0800 Subject: Tegra: per-CPU GIC CPU interface init This patch enables per-CPU GIC CPU interfaces during CPU power on. The previous code initialized the distributor for all CPUs, which was not required. Signed-off-by: Varun Wadekar Change-Id: Ifd957b2367da06405b4c3e2225411adbaec35bb8 --- plat/nvidia/tegra/common/tegra_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index a8c70eaa5..39dc42c5b 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -244,7 +244,7 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) /* * Initialize the GIC cpu and distributor interfaces */ - tegra_gic_init(); + tegra_gic_pcpu_init(); /* * Check if we are exiting from deep sleep. -- cgit v1.2.3 From bb9549babc17631f7c7b944ad3213c5a8d173bdd Mon Sep 17 00:00:00 2001 From: Jan Dabros Date: Mon, 2 Dec 2019 13:30:03 +0100 Subject: aarch64: Fix stack pointer maintenance on EA handling path EA handlers for exceptions taken from lower ELs at the end invokes el3_exit function. However there was a bug with sp maintenance which resulted in el3_exit setting runtime stack to context. This in turn caused memory corruption on consecutive EL3 entries. Signed-off-by: Jan Dabros Change-Id: I0424245c27c369c864506f4baa719968890ce659 --- bl31/aarch64/ea_delegate.S | 13 +++++++++---- lib/el3_runtime/aarch64/context.S | 8 ++++++++ 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S index 3cc4d56a3..1d28d5e0f 100644 --- a/bl31/aarch64/ea_delegate.S +++ b/bl31/aarch64/ea_delegate.S @@ -102,9 +102,11 @@ func enter_lower_el_sync_ea /* Setup exception class and syndrome arguments for platform handler */ mov x0, #ERROR_EA_SYNC mrs x1, esr_el3 - adr x30, el3_exit - b delegate_sync_ea + bl delegate_sync_ea + /* el3_exit assumes SP_EL0 on entry */ + msr spsel, #MODE_SP_EL0 + b el3_exit 2: ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] @@ -146,8 +148,11 @@ func enter_lower_el_async_ea /* Setup exception class and syndrome arguments for platform handler */ mov x0, #ERROR_EA_ASYNC mrs x1, esr_el3 - adr x30, el3_exit - b delegate_async_ea + bl delegate_async_ea + + /* el3_exit assumes SP_EL0 on entry */ + msr spsel, #MODE_SP_EL0 + b el3_exit endfunc enter_lower_el_async_ea diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 110142520..1bbd61005 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -6,6 +6,7 @@ #include #include +#include #include .global el1_sysregs_context_save @@ -477,6 +478,13 @@ endfunc restore_gp_pmcr_pauth_regs * ------------------------------------------------------------------ */ func el3_exit +#if ENABLE_ASSERTIONS + /* el3_exit assumes SP_EL0 on entry */ + mrs x17, spsel + cmp x17, #MODE_SP_EL0 + ASM_ASSERT(eq) +#endif + /* ---------------------------------------------------------- * Save the current SP_EL0 i.e. the EL3 runtime stack which * will be used for handling the next SMC. -- cgit v1.2.3 From 992f091b5de3b0837c95a338a4e739f6ca2f254f Mon Sep 17 00:00:00 2001 From: Ambroise Vincent Date: Fri, 12 Jul 2019 13:47:03 +0100 Subject: debugfs: add SMC channel Provide an SMC interface to the 9p filesystem. This permits accessing firmware drivers through a common interface, using standardized read/write/control operations. Signed-off-by: Ambroise Vincent Signed-off-by: Olivier Deprez Change-Id: I9314662314bb060f6bc02714476574da158b2a7d --- docs/components/arm-sip-service.rst | 341 ++++++++++++++++++++++++++++++ docs/components/debugfs-design.rst | 132 ++++++++++++ docs/getting_started/build-options.rst | 4 + include/lib/debugfs.h | 23 ++ include/plat/arm/common/arm_sip_svc.h | 8 +- lib/debugfs/debugfs.mk | 2 + lib/debugfs/debugfs_smc.c | 209 ++++++++++++++++++ plat/arm/board/fvp/fvp_common.c | 4 + plat/arm/board/fvp/include/platform_def.h | 6 +- plat/arm/board/fvp/platform.mk | 4 + plat/arm/common/arm_bl31_setup.c | 7 +- plat/arm/common/arm_sip_svc.c | 24 ++- 12 files changed, 759 insertions(+), 5 deletions(-) create mode 100644 docs/components/debugfs-design.rst create mode 100644 lib/debugfs/debugfs_smc.c diff --git a/docs/components/arm-sip-service.rst b/docs/components/arm-sip-service.rst index 2d58586b9..01bc04d71 100644 --- a/docs/components/arm-sip-service.rst +++ b/docs/components/arm-sip-service.rst @@ -17,6 +17,7 @@ The Arm SiP implementation offers the following services: - Performance Measurement Framework (PMF) - Execution State Switching service +- DebugFS interface Source definitions for Arm SiP service are located in the ``arm_sip_svc.h`` header file. @@ -87,6 +88,346 @@ Instead, execution starts at the supplied entry point, with the CPU registers 0 and 1 populated with the supplied *Cookie hi* and *Cookie lo* values, respectively. +DebugFS interface +----------------- + +The optional DebugFS interface is accessed through an SMC SiP service. Refer +to the component documentation for details. + +String parameters are passed through a shared buffer using a specific union: + +.. code:: c + + union debugfs_parms { + struct { + char fname[MAX_PATH_LEN]; + } open; + + struct mount { + char srv[MAX_PATH_LEN]; + char where[MAX_PATH_LEN]; + char spec[MAX_PATH_LEN]; + } mount; + + struct { + char path[MAX_PATH_LEN]; + dir_t dir; + } stat; + + struct { + char oldpath[MAX_PATH_LEN]; + char newpath[MAX_PATH_LEN]; + } bind; + }; + +Format of the dir_t structure as such: + +.. code:: c + + typedef struct { + char name[NAMELEN]; + long length; + unsigned char mode; + unsigned char index; + unsigned char dev; + qid_t qid; + } dir_t; + + +* Identifiers + +======================== ============================================= +SMC_OK 0 +SMC_UNK -1 +DEBUGFS_E_INVALID_PARAMS -2 +======================== ============================================= + +======================== ============================================= +MOUNT 0 +CREATE 1 +OPEN 2 +CLOSE 3 +READ 4 +WRITE 5 +SEEK 6 +BIND 7 +STAT 8 +INIT 10 +VERSION 11 +======================== ============================================= + +MOUNT +~~~~~ + +Description +^^^^^^^^^^^ +This operation mounts a blob of data pointed to by path stored in `src`, at +filesystem location pointed to by path stored in `where`, using driver pointed +to by path in `spec`. + +Parameters +^^^^^^^^^^ +======== ============================================================ +uint32_t FunctionID (0x82000030 / 0xC2000030) +uint32_t ``MOUNT`` +======== ============================================================ + +Return values +^^^^^^^^^^^^^ + +=============== ========================================================== +int32_t w0 == SMC_OK on success + + w0 == DEBUGFS_E_INVALID_PARAMS if mount operation failed +=============== ========================================================== + +OPEN +~~~~ + +Description +^^^^^^^^^^^ +This operation opens the file path pointed to by `fname`. + +Parameters +^^^^^^^^^^ + +======== ============================================================ +uint32_t FunctionID (0x82000030 / 0xC2000030) +uint32_t ``OPEN`` +uint32_t mode +======== ============================================================ + +mode can be one of: + +.. code:: c + + enum mode { + O_READ = 1 << 0, + O_WRITE = 1 << 1, + O_RDWR = 1 << 2, + O_BIND = 1 << 3, + O_DIR = 1 << 4, + O_STAT = 1 << 5 + }; + +Return values +^^^^^^^^^^^^^ + +=============== ========================================================== +int32_t w0 == SMC_OK on success + + w0 == DEBUGFS_E_INVALID_PARAMS if open operation failed + +uint32_t w1: file descriptor id on success. +=============== ========================================================== + +CLOSE +~~~~~ + +Description +^^^^^^^^^^^ + +This operation closes a file described by a file descriptor obtained by a +previous call to OPEN. + +Parameters +^^^^^^^^^^ + +======== ============================================================ +uint32_t FunctionID (0x82000030 / 0xC2000030) +uint32_t ``CLOSE`` +uint32_t File descriptor id returned by OPEN +======== ============================================================ + +Return values +^^^^^^^^^^^^^ +=============== ========================================================== +int32_t w0 == SMC_OK on success + + w0 == DEBUGFS_E_INVALID_PARAMS if close operation failed +=============== ========================================================== + +READ +~~~~ + +Description +^^^^^^^^^^^ + +This operation reads a number of bytes from a file descriptor obtained by +a previous call to OPEN. + +Parameters +^^^^^^^^^^ + +======== ============================================================ +uint32_t FunctionID (0x82000030 / 0xC2000030) +uint32_t ``READ`` +uint32_t File descriptor id returned by OPEN +uint32_t Number of bytes to read +======== ============================================================ + +Return values +^^^^^^^^^^^^^ + +On success, the read data is retrieved from the shared buffer after the +operation. + +=============== ========================================================== +int32_t w0 == SMC_OK on success + + w0 == DEBUGFS_E_INVALID_PARAMS if read operation failed + +uint32_t w1: number of bytes read on success. +=============== ========================================================== + +SEEK +~~~~ + +Description +^^^^^^^^^^^ + +Move file pointer for file described by given `file descriptor` of given +`offset` related to `whence`. + +Parameters +^^^^^^^^^^ + +======== ============================================================ +uint32_t FunctionID (0x82000030 / 0xC2000030) +uint32_t ``SEEK`` +uint32_t File descriptor id returned by OPEN +sint32_t offset in the file relative to whence +uint32_t whence +======== ============================================================ + +whence can be one of: + +========= ============================================================ +KSEEK_SET 0 +KSEEK_CUR 1 +KSEEK_END 2 +========= ============================================================ + +Return values +^^^^^^^^^^^^^ + +=============== ========================================================== +int32_t w0 == SMC_OK on success + + w0 == DEBUGFS_E_INVALID_PARAMS if seek operation failed +=============== ========================================================== + +BIND +~~~~ + +Description +^^^^^^^^^^^ + +Create a link from `oldpath` to `newpath`. + +Parameters +^^^^^^^^^^ + +======== ============================================================ +uint32_t FunctionID (0x82000030 / 0xC2000030) +uint32_t ``BIND`` +======== ============================================================ + +Return values +^^^^^^^^^^^^^ + +=============== ========================================================== +int32_t w0 == SMC_OK on success + + w0 == DEBUGFS_E_INVALID_PARAMS if bind operation failed +=============== ========================================================== + +STAT +~~~~ + +Description +^^^^^^^^^^^ + +Perform a stat operation on provided file `name` and returns the directory +entry statistics into `dir`. + +Parameters +^^^^^^^^^^ + +======== ============================================================ +uint32_t FunctionID (0x82000030 / 0xC2000030) +uint32_t ``STAT`` +======== ============================================================ + +Return values +^^^^^^^^^^^^^ + +=============== ========================================================== +int32_t w0 == SMC_OK on success + + w0 == DEBUGFS_E_INVALID_PARAMS if stat operation failed +=============== ========================================================== + +INIT +~~~~ + +Description +^^^^^^^^^^^ +Initial call to setup the shared exchange buffer. Notice if successful once, +subsequent calls fail after a first initialization. The caller maps the same +page frame in its virtual space and uses this buffer to exchange string +parameters with filesystem primitives. + +Parameters +^^^^^^^^^^ + +======== ============================================================ +uint32_t FunctionID (0x82000030 / 0xC2000030) +uint32_t ``INIT`` +uint64_t Physical address of the shared buffer. +======== ============================================================ + +Return values +^^^^^^^^^^^^^ + +=============== ====================================================== +int32_t w0 == SMC_OK on success + + w0 == DEBUGFS_E_INVALID_PARAMS if already initialized, + or internal error occurred. +=============== ====================================================== + +VERSION +~~~~~~~ + +Description +^^^^^^^^^^^ +Returns the debugfs interface version if implemented in TF-A. + +Parameters +^^^^^^^^^^ + +======== ============================================================ +uint32_t FunctionID (0x82000030 / 0xC2000030) +uint32_t ``VERSION`` +======== ============================================================ + +Return values +^^^^^^^^^^^^^ + +=============== ====================================================== +int32_t w0 == SMC_OK on success + + w0 == SMC_UNK if interface is not implemented + +uint32_t w1: On success, debugfs interface version, 32 bits + value with major version number in upper 16 bits and + minor version in lower 16 bits. +=============== ====================================================== + +* CREATE(1) and WRITE (5) command identifiers are unimplemented and + return `SMC_UNK`. + -------------- *Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/components/debugfs-design.rst b/docs/components/debugfs-design.rst new file mode 100644 index 000000000..06916f3d9 --- /dev/null +++ b/docs/components/debugfs-design.rst @@ -0,0 +1,132 @@ +======== +Debug FS +======== + +.. contents:: + +Overview +-------- + +The *DebugFS* feature is primarily aimed at exposing firmware debug data to +higher SW layers such as a non-secure component. Such component can be the +TFTF test payload or a Linux kernel module. + +Virtual filesystem +------------------ + +The core functionality lies in a virtual file system based on a 9p file server +interface (`Notes on the Plan 9 Kernel Source`_). The implementation permits +exposing virtual files, firmware drivers, and file blobs. + +Namespace +~~~~~~~~~ + +Two namespaces are exposed: + + - # is used as root for drivers (e.g. #t0 is the first uart) + - / is used as root for virtual "files" (e.g. /fip, or /dev/uart) + +9p interface +~~~~~~~~~~~~ + +The associated primitives are: + +- Unix-like: + + - open(): create a file descriptor that acts as a handle to the file passed as + an argument. + - close(): close the file descriptor created by open(). + - read(): read from a file to a buffer. + - write(): write from a buffer to a file. + - seek(): set the file position indicator of a file descriptor either to a + relative or an absolute offset. + - stat(): get information about a file (type, mode, size, ...). + +.. code:: c + + int open(const char *name, int flags); + int close(int fd); + int read(int fd, void *buf, int n); + int write(int fd, void *buf, int n); + int seek(int fd, long off, int whence); + int stat(char *path, dir_t *dir); + +- Specific primitives : + + - mount(): create a link between a driver and spec. + - create(): create a file in a specific location. + - bind(): expose the content of a directory to another directory. + +.. code:: c + + int mount(char *srv, char *mnt, char *spec); + int create(const char *name, int flags); + int bind(char *path, char *where); + +This interface is embedded into the BL31 run-time payload when selected by build +options. The interface multiplexes drivers or emulated "files": + +- Debug data can be partitioned into different virtual files e.g. expose PMF + measurements through a file, and internal firmware state counters through + another file. +- This permits direct access to a firmware driver, mainly for test purposes + (e.g. a hardware device that may not be accessible to non-privileged/ + non-secure layers, or for which no support exists in the NS side). + +SMC interface +------------- + +The communication with the 9p layer in BL31 is made through an SMC conduit +(`SMC Calling Convention PDD`_), using a specific SiP Function Id. An NS shared +buffer is used to pass path string parameters, or e.g. to exchange data on a +read operation. Refer to `ARM SiP Services`_ for a description of the SMC +interface. + +Security considerations +----------------------- + +- Due to the nature of the exposed data, the feature is considered experimental + and importantly **shall only be used in debug builds**. +- Several primitive imply string manipulations and usage of string formats. +- Special care is taken with the shared buffer to avoid TOCTOU attacks. + +Limitations +----------- + +- In order to setup the shared buffer, the component consuming the interface + needs to allocate a physical page frame and transmit its address. +- In order to map the shared buffer, BL31 requires enabling the dynamic xlat + table option. +- Data exchange is limited by the shared buffer length. A large read operation + might be split into multiple read operations of smaller chunks. +- On concurrent access, a spinlock is implemented in the BL31 service to protect + the internal work buffer, and re-entrancy into the filesystem layers. +- Notice, a physical device driver if exposed by the firmware may conflict with + the higher level OS if the latter implements its own driver for the same + physical device. + +Applications +------------ + +The SMC interface is accessible from an NS environment, that is: + +- a test payload, bootloader or hypervisor running at NS-EL2 +- a Linux kernel driver running at NS-EL1 +- a Linux userspace application through the kernel driver + +References +---------- + +.. [#] `SMC Calling Convention PDD`_ +.. [#] `Notes on the Plan 9 Kernel Source`_ +.. [#] `Linux 9p remote filesystem protocol`_ +.. [#] `ARM SiP Services`_ + +-------------- + +*Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.* + +.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ +.. _Notes on the Plan 9 Kernel Source: http://lsub.org/who/nemo/9.pdf +.. _Linux 9p remote filesystem protocol: https://www.kernel.org/doc/Documentation/filesystems/9p.txt +.. _ARM SiP Services: arm-sip-service.rst diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 051586bc3..469fd34b7 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -544,6 +544,10 @@ Common build options (Coherent memory region is included) or 0 (Coherent memory region is excluded). Default is 1. +- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature + exposing a virtual filesystem interface through BL31 as a SiP SMC function. + Default is 0. + - ``USE_ROMLIB``: This flag determines whether library at ROM will be used. This feature creates a library of functions to be placed in ROM and thus reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default diff --git a/include/lib/debugfs.h b/include/lib/debugfs.h index b7e33303c..8ed237ae2 100644 --- a/include/lib/debugfs.h +++ b/include/lib/debugfs.h @@ -56,5 +56,28 @@ int stat(const char *path, dir_t *dir); /* DebugFS initialization */ void debugfs_init(void); +int debugfs_smc_setup(void); + +/* Debugfs version returned through SMC interface */ +#define DEBUGFS_VERSION (0x000000001U) + +/* Function ID for accessing the debugfs interface */ +#define DEBUGFS_FID_VALUE (0x30U) + +#define is_debugfs_fid(_fid) \ + (((_fid) & FUNCID_NUM_MASK) == DEBUGFS_FID_VALUE) + +/* Error code for debugfs SMC interface failures */ +#define DEBUGFS_E_INVALID_PARAMS (-2) +#define DEBUGFS_E_DENIED (-3) + +uintptr_t debugfs_smc_handler(unsigned int smc_fid, + u_register_t cmd, + u_register_t arg2, + u_register_t arg3, + u_register_t arg4, + void *cookie, + void *handle, + uintptr_t flags); #endif /* DEBUGFS_H */ diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h index 16573ce6a..85fdb289f 100644 --- a/include/plat/arm/common/arm_sip_svc.h +++ b/include/plat/arm/common/arm_sip_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,9 +16,15 @@ /* U(0x8200ff02) is reserved */ #define ARM_SIP_SVC_VERSION U(0x8200ff03) +/* PMF_SMC_GET_TIMESTAMP_32 0x82000010 */ +/* PMF_SMC_GET_TIMESTAMP_64 0xC2000010 */ + /* Function ID for requesting state switch of lower EL */ #define ARM_SIP_SVC_EXE_STATE_SWITCH U(0x82000020) +/* DEBUGFS_SMC_32 0x82000030U */ +/* DEBUGFS_SMC_64 0xC2000030U */ + /* ARM SiP Service Calls version numbers */ #define ARM_SIP_SVC_VERSION_MAJOR U(0x0) #define ARM_SIP_SVC_VERSION_MINOR U(0x2) diff --git a/lib/debugfs/debugfs.mk b/lib/debugfs/debugfs.mk index 2c0260006..138fc72a1 100644 --- a/lib/debugfs/debugfs.mk +++ b/lib/debugfs/debugfs.mk @@ -9,3 +9,5 @@ DEBUGFS_SRCS := $(addprefix lib/debugfs/, \ devc.c \ devroot.c \ devfip.c) + +DEBUGFS_SRCS += lib/debugfs/debugfs_smc.c diff --git a/lib/debugfs/debugfs_smc.c b/lib/debugfs/debugfs_smc.c new file mode 100644 index 000000000..400c166d7 --- /dev/null +++ b/lib/debugfs/debugfs_smc.c @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#define MAX_PATH_LEN 256 + +#define MOUNT 0 +#define CREATE 1 +#define OPEN 2 +#define CLOSE 3 +#define READ 4 +#define WRITE 5 +#define SEEK 6 +#define BIND 7 +#define STAT 8 +#define INIT 10 +#define VERSION 11 + +/* This is the virtual address to which we map the NS shared buffer */ +#define DEBUGFS_SHARED_BUF_VIRT ((void *)0x81000000U) + +static union debugfs_parms { + struct { + char fname[MAX_PATH_LEN]; + } open; + + struct { + char srv[MAX_PATH_LEN]; + char where[MAX_PATH_LEN]; + char spec[MAX_PATH_LEN]; + } mount; + + struct { + char path[MAX_PATH_LEN]; + dir_t dir; + } stat; + + struct { + char oldpath[MAX_PATH_LEN]; + char newpath[MAX_PATH_LEN]; + } bind; +} parms; + +/* debugfs_access_lock protects shared buffer and internal */ +/* FS functions from concurrent acccesses. */ +static spinlock_t debugfs_access_lock; + +static bool debugfs_initialized; + +uintptr_t debugfs_smc_handler(unsigned int smc_fid, + u_register_t cmd, + u_register_t arg2, + u_register_t arg3, + u_register_t arg4, + void *cookie, + void *handle, + u_register_t flags) +{ + int64_t smc_ret = DEBUGFS_E_INVALID_PARAMS, smc_resp = 0; + int ret; + + /* Allow calls from non-secure only */ + if (is_caller_secure(flags)) { + SMC_RET1(handle, DEBUGFS_E_DENIED); + } + + /* Expect a SiP service fast call */ + if ((GET_SMC_TYPE(smc_fid) != SMC_TYPE_FAST) || + (GET_SMC_OEN(smc_fid) != OEN_SIP_START)) { + SMC_RET1(handle, SMC_UNK); + } + + /* Truncate parameters if 32b SMC convention call */ + if (GET_SMC_CC(smc_fid) == SMC_32) { + arg2 &= 0xffffffff; + arg3 &= 0xffffffff; + arg4 &= 0xffffffff; + } + + spin_lock(&debugfs_access_lock); + + if (debugfs_initialized == true) { + /* Copy NS shared buffer to internal secure location */ + memcpy(&parms, (void *)DEBUGFS_SHARED_BUF_VIRT, + sizeof(union debugfs_parms)); + } + + switch (cmd) { + case INIT: + if (debugfs_initialized == false) { + /* TODO: check PA validity e.g. whether */ + /* it is an NS region. */ + ret = mmap_add_dynamic_region(arg2, + (uintptr_t)DEBUGFS_SHARED_BUF_VIRT, + PAGE_SIZE_4KB, + MT_MEMORY | MT_RW | MT_NS); + if (ret == 0) { + debugfs_initialized = true; + smc_ret = SMC_OK; + smc_resp = 0; + } + } + break; + + case VERSION: + smc_ret = SMC_OK; + smc_resp = DEBUGFS_VERSION; + break; + + case MOUNT: + ret = mount(parms.mount.srv, + parms.mount.where, + parms.mount.spec); + if (ret == 0) { + smc_ret = SMC_OK; + smc_resp = 0; + } + break; + + case OPEN: + ret = open(parms.open.fname, arg2); + if (ret >= 0) { + smc_ret = SMC_OK; + smc_resp = ret; + } + break; + + case CLOSE: + ret = close(arg2); + if (ret == 0) { + smc_ret = SMC_OK; + smc_resp = 0; + } + break; + + case READ: + ret = read(arg2, DEBUGFS_SHARED_BUF_VIRT, arg3); + if (ret >= 0) { + smc_ret = SMC_OK; + smc_resp = ret; + } + break; + + case SEEK: + ret = seek(arg2, arg3, arg4); + if (ret == 0) { + smc_ret = SMC_OK; + smc_resp = 0; + } + break; + + case BIND: + ret = bind(parms.bind.oldpath, parms.bind.newpath); + if (ret == 0) { + smc_ret = SMC_OK; + smc_resp = 0; + } + break; + + case STAT: + ret = stat(parms.stat.path, &parms.stat.dir); + if (ret == 0) { + memcpy((void *)DEBUGFS_SHARED_BUF_VIRT, &parms, + sizeof(union debugfs_parms)); + smc_ret = SMC_OK; + smc_resp = 0; + } + break; + + /* Not implemented */ + case CREATE: + /* Intentional fall-through */ + + /* Not implemented */ + case WRITE: + /* Intentional fall-through */ + + default: + smc_ret = SMC_UNK; + smc_resp = 0; + } + + spin_unlock(&debugfs_access_lock); + + SMC_RET2(handle, smc_ret, smc_resp); + + /* Not reached */ + return smc_ret; +} + +int debugfs_smc_setup(void) +{ + debugfs_initialized = false; + debugfs_access_lock.lock = 0; + + return 0; +} diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index a94879624..5c0df7a7d 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -122,6 +122,10 @@ const mmap_region_t plat_arm_mmap[] = { #ifdef IMAGE_BL31 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, +#if USE_DEBUGFS + /* Required by devfip, can be removed if devfip is not used */ + V2M_MAP_FLASH0_RW, +#endif /* USE_DEBUGFS */ ARM_MAP_EL3_TZC_DRAM, V2M_MAP_IOFPGA, MAP_DEVICE0, diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 98dd0a97f..2b441747a 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -68,7 +68,11 @@ # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 # else # define PLAT_ARM_MMAP_ENTRIES 8 -# define MAX_XLAT_TABLES 5 +# if USE_DEBUGFS +# define MAX_XLAT_TABLES 6 +# else +# define MAX_XLAT_TABLES 5 +# endif # endif #elif defined(IMAGE_BL32) # define PLAT_ARM_MMAP_ENTRIES 8 diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 3a9972bb4..8cf2612a7 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -291,6 +291,10 @@ else # if AArch64 endif endif +ifeq (${USE_DEBUGFS},1) + BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 +endif + # Add support for platform supplied linker script for BL31 build $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index ab90f46a8..939885f98 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -231,6 +232,10 @@ void arm_bl31_platform_setup(void) #if RAS_EXTENSION ras_init(); #endif + +#if USE_DEBUGFS + debugfs_init(); +#endif /* USE_DEBUGFS */ } /******************************************************************************* diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c index 3d308a335..c8f480f18 100644 --- a/plat/arm/common/arm_sip_svc.c +++ b/plat/arm/common/arm_sip_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -20,8 +21,18 @@ DEFINE_SVC_UUID2(arm_sip_svc_uid, static int arm_sip_setup(void) { - if (pmf_setup() != 0) + if (pmf_setup() != 0) { return 1; + } + +#if USE_DEBUGFS + + if (debugfs_smc_setup() != 0) { + return 1; + } + +#endif /* USE_DEBUGFS */ + return 0; } @@ -48,6 +59,15 @@ static uintptr_t arm_sip_handler(unsigned int smc_fid, handle, flags); } +#if USE_DEBUGFS + + if (is_debugfs_fid(smc_fid)) { + return debugfs_smc_handler(smc_fid, x1, x2, x3, x4, cookie, + handle, flags); + } + +#endif /* USE_DEBUGFS */ + switch (smc_fid) { case ARM_SIP_SVC_EXE_STATE_SWITCH: { u_register_t pc; -- cgit v1.2.3 From 2783205da9a50b41eeb4dbd721e992457bb2151d Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 17 Dec 2019 21:23:24 -0800 Subject: Tegra: prepare boot parameters for Trusty This patch saves the boot parameters provided by the previous bootloader during cold boot and passes them to Trusty. Commit 06ff251ec introduced the plat_trusty_set_boot_args() handler, but did not consider the boot parameters passed by the previous bootloader. This patch fixes that anomaly. Change-Id: Ib40dcd02b67c94cea5cefce09edb0be4a998db37 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/common/tegra_bl31_setup.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index a6652766f..25fd84cdc 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -54,8 +54,9 @@ static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { .tzdram_size = TZDRAM_SIZE }; -static unsigned long bl32_mem_size; -static unsigned long bl32_boot_params; +#ifdef SPD_trusty +static aapcs64_params_t bl32_args; +#endif /******************************************************************************* * This variable holds the non-secure image entry address @@ -155,8 +156,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, if (arg_from_bl2->bl32_ep_info != NULL) { bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; - bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0; - bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2; +#ifdef SPD_trusty + /* save BL32 boot parameters */ + memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args)); +#endif } /* @@ -273,17 +276,20 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, #ifdef SPD_trusty void plat_trusty_set_boot_args(aapcs64_params_t *args) { - args->arg0 = bl32_mem_size; - args->arg1 = bl32_boot_params; - args->arg2 = TRUSTY_PARAMS_LEN_BYTES; + /* + * arg0 = TZDRAM aperture available for BL32 + * arg1 = BL32 boot params + * arg2 = EKS Blob Length + * arg3 = Boot Profiler Carveout Base + */ + args->arg0 = bl32_args.arg0; + args->arg1 = bl32_args.arg2; /* update EKS size */ - if (args->arg4 != 0U) { - args->arg2 = args->arg4; - } + args->arg2 = bl32_args.arg4; /* Profiler Carveout Base */ - args->arg3 = args->arg5; + args->arg3 = bl32_args.arg5; } #endif -- cgit v1.2.3 From 79c6c342e0abb1de2306ca51fc72794143413a07 Mon Sep 17 00:00:00 2001 From: Vishnu Banavath Date: Fri, 13 Dec 2019 16:53:17 +0000 Subject: fdts: a5ds: add L2 cache node in devicetree This change is to add L2 cache node into a5ds device tree. Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947 Signed-off-by: Vishnu Banavath --- fdts/a5ds.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts index 91212e8a0..042b6afc5 100644 --- a/fdts/a5ds.dts +++ b/fdts/a5ds.dts @@ -27,24 +27,28 @@ compatible = "arm,cortex-a5"; enable-method = "psci"; reg = <0>; + next-level-cache = <&L2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a5"; enable-method = "psci"; reg = <1>; + next-level-cache = <&L2>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a5"; enable-method = "psci"; reg = <2>; + next-level-cache = <&L2>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a5"; enable-method = "psci"; reg = <3>; + next-level-cache = <&L2>; }; }; @@ -53,6 +57,16 @@ reg = <0x80000000 0x7F000000>; }; + L2: cache-controller@1C010000 { + compatible = "arm,pl310-cache"; + reg = <0x1C010000 0x1000>; + interrupts = <0 84 4>; + cache-level = <2>; + cache-unified; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + refclk100mhz: refclk100mhz { compatible = "fixed-clock"; #clock-cells = <0>; -- cgit v1.2.3 From ab3b00fbfd0afc94a4b7afd95001043636dbc1d1 Mon Sep 17 00:00:00 2001 From: Vishnu Banavath Date: Fri, 13 Dec 2019 17:07:45 +0000 Subject: fdts: a5ds: cleanup enable-method in devicetree Same enable method is used by all the four cores. So, make it globally for all the cores instead of adding it to individual level. Change-Id: I9b5728b0e0545c9e27160ea586009d929eb78cad Signed-off-by: Vishnu Banavath --- fdts/a5ds.dts | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts index 042b6afc5..fc8783dd8 100644 --- a/fdts/a5ds.dts +++ b/fdts/a5ds.dts @@ -22,31 +22,28 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "psci"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a5"; - enable-method = "psci"; reg = <0>; next-level-cache = <&L2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a5"; - enable-method = "psci"; reg = <1>; next-level-cache = <&L2>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a5"; - enable-method = "psci"; reg = <2>; next-level-cache = <&L2>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a5"; - enable-method = "psci"; reg = <3>; next-level-cache = <&L2>; }; -- cgit v1.2.3 From 5ddcbdd8158d30ce2fc8b7f4084bc1df455eac44 Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Thu, 19 Dec 2019 11:59:31 +0000 Subject: TF-A: Fix BL2 bug in dynamic configuration initialisation This patch fixes the bug in BL2 dynamic configuration initialisation which prevents loading NT_FW_CONFIG image (ref. GENFW-3471). It also adds parentheses around 'if' statement conditions to fix Coverity defect. Change-Id: I353566c29b84341887e13bf8098a4fedfc4e00ff Signed-off-by: Alexei Fedorov --- plat/arm/common/arm_dyn_cfg.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c index aafb190d5..e6c5a7361 100644 --- a/plat/arm/common/arm_dyn_cfg.c +++ b/plat/arm/common/arm_dyn_cfg.c @@ -243,7 +243,8 @@ void arm_bl2_dyn_cfg_init(void) #ifdef BL31_BASE /* Ensure the configs don't overlap with BL31 */ - if ((image_base > BL31_BASE) || ((image_base + image_size) > BL31_BASE)) + if ((image_base >= BL31_BASE) && + (image_base <= BL31_LIMIT)) continue; #endif /* Ensure the configs are loaded in a valid address */ @@ -254,7 +255,8 @@ void arm_bl2_dyn_cfg_init(void) * If BL32 is present, ensure that the configs don't * overlap with it. */ - if (image_base >= BL32_BASE && image_base <= BL32_LIMIT) + if ((image_base >= BL32_BASE) && + (image_base <= BL32_LIMIT)) continue; #endif } @@ -263,7 +265,10 @@ void arm_bl2_dyn_cfg_init(void) cfg_mem_params->image_info.image_base = (uintptr_t)image_base; cfg_mem_params->image_info.image_max_size = image_size; - /* Remove the IMAGE_ATTRIB_SKIP_LOADING attribute from HW_CONFIG node */ + /* + * Remove the IMAGE_ATTRIB_SKIP_LOADING attribute from + * HW_CONFIG or FW_CONFIG nodes + */ cfg_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; } -- cgit v1.2.3 From 3f3c341ae58321ec1b86162916d80b6db9187759 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Mon, 16 Sep 2019 11:29:03 +0000 Subject: Remove dependency between SPM_MM and ENABLE_SPM build flags There are two different implementations of Secure Partition management in TF-A. One is based on the "Management Mode" (MM) design, the other is based on the Secure Partition Client Interface (SPCI) specification. Currently there is a dependency between their build flags that shouldn't exist, making further development harder than it should be. This patch removes that dependency, making the two flags function independently. Before: ENABLE_SPM=1 is required for using either implementation. By default, the SPCI-based implementation is enabled and this is overridden if SPM_MM=1. After: ENABLE_SPM=1 enables the SPCI-based implementation. SPM_MM=1 enables the MM-based implementation. The two build flags are mutually exclusive. Note that the name of the ENABLE_SPM flag remains a bit ambiguous - this will be improved in a subsequent patch. For this patch the intention was to leave the name as-is so that it is easier to track the changes that were made. Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a Signed-off-by: Paul Beesley --- Makefile | 8 ++++++++ bl31/bl31.ld.S | 2 +- bl31/bl31.mk | 20 ++++++++++---------- docs/getting_started/build-options.rst | 8 ++++++-- include/plat/arm/common/arm_def.h | 4 ++-- include/plat/arm/common/plat_arm.h | 2 +- make_helpers/defaults.mk | 6 +++--- plat/arm/board/fvp/fvp_common.c | 12 ++++++------ plat/arm/board/fvp/include/platform_def.h | 4 ++-- plat/arm/board/fvp/platform.mk | 2 -- plat/arm/common/aarch64/arm_ehf.c | 4 ++-- plat/arm/common/arm_common.mk | 2 -- plat/arm/css/sgi/include/sgi_base_platform_def.h | 6 +++--- plat/arm/css/sgi/sgi_plat.c | 14 +++++++------- plat/nvidia/tegra/scat/bl31.scat | 2 +- plat/socionext/synquacer/platform.mk | 4 ++-- plat/socionext/synquacer/sq_bl31_setup.c | 4 ++-- services/std_svc/std_svc_setup.c | 4 ++-- 18 files changed, 58 insertions(+), 50 deletions(-) diff --git a/Makefile b/Makefile index b9584ca98..ff7c5b7d4 100644 --- a/Makefile +++ b/Makefile @@ -571,6 +571,14 @@ ifeq ($(CTX_INCLUDE_MTE_REGS),1) endif endif +# The SPCI-based SPM implementation and the MM-based SPM implementation cannot +# be enabled at the same time. +ifeq ($(ENABLE_SPM),1) + ifeq ($(SPM_MM),1) + $(error Use only one of the ENABLE_SPM and SPM_MM flags) + endif +endif + ################################################################################ # Process platform overrideable behaviour ################################################################################ diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 708ee329f..a4be3b234 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -142,7 +142,7 @@ SECTIONS ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, "cpu_ops not defined for this platform.") -#if ENABLE_SPM +#if ENABLE_SPM || SPM_MM #ifndef SPM_SHIM_EXCEPTIONS_VMA #define SPM_SHIM_EXCEPTIONS_VMA RAM #endif diff --git a/bl31/bl31.mk b/bl31/bl31.mk index c9ba926c5..7ff054a7e 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -5,22 +5,22 @@ # ################################################################################ -# Include SPM Makefile +# Include Makefile for either of the supported SPM implementations ################################################################################ ifeq (${ENABLE_SPM},1) - ifeq (${SPM_MM},1) - ifeq (${EL3_EXCEPTION_HANDLING},0) - $(error EL3_EXCEPTION_HANDLING must be 1 for SPM support) - endif - $(info Including makefile of SPM based on MM) - include services/std_svc/spm_mm/spm.mk + $(info Including SPM (SPCI) makefile) + include services/std_svc/spm/spm.mk +endif + +ifeq (${SPM_MM},1) + ifeq (${EL3_EXCEPTION_HANDLING},0) + $(error EL3_EXCEPTION_HANDLING must be 1 for SPM support) else - $(info Including SPM makefile) - include services/std_svc/spm/spm.mk + $(info Including SPM Management Mode (MM) makefile) + include services/std_svc/spm_mm/spm.mk endif endif - include lib/psci/psci_lib.mk BL31_SOURCES += bl31/bl31_main.c \ diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 731b87624..87ce94eb4 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -235,8 +235,9 @@ Common build options The default is 1 but is automatically disabled when the target architecture is AArch32. -- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM). - Refer to :ref:`Secure Partition Manager` for more details about +- ``ENABLE_SPM`` : Boolean option to enable the SPCI-based Secure Partition + Manager (SPM) implementation. + Refer to the :ref:`Secure Partition Manager` guide for more details about this feature. Default is 0. - ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension @@ -507,6 +508,9 @@ Common build options firmware images have been loaded in memory, and the MMU and caches are turned off. Refer to the "Debugging options" section for more details. +- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure + Partition Manager (SPM) implementation. The default value is ``0``. + - ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles secure interrupts (caught through the FIQ line). Platforms can enable this directive if they need to handle such interruption. When enabled, diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 941190fdc..8095bed70 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -500,9 +500,9 @@ * SPD and no SPM, as they are the only ones that can be used as BL32. */ #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME -# if defined(SPD_none) && !ENABLE_SPM +# if defined(SPD_none) && !ENABLE_SPM && !SPM_MM # undef BL32_BASE -# endif /* defined(SPD_none) && !ENABLE_SPM */ +# endif /* defined(SPD_none) && !ENABLE_SPM && !SPM_MM*/ #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ /******************************************************************************* diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index c00a04126..02feec708 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -38,7 +38,7 @@ typedef struct arm_tzc_regions_info { * - Region 1 with secure access only; * - the remaining DRAM regions access from the given Non-Secure masters. ******************************************************************************/ -#if ENABLE_SPM && SPM_MM +#if SPM_MM #define ARM_TZC_REGIONS_DEF \ {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ TZC_REGION_S_RDWR, 0}, \ diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 348b3e52b..ac5d959ae 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -178,11 +178,11 @@ RECLAIM_INIT_CODE := 0 # SPD choice SPD := none -# For including the Secure Partition Manager +# Enable the SPCI-based Secure Partition Manager implementation ENABLE_SPM := 0 -# Use the SPM based on MM -SPM_MM := 1 +# Enable the Management Mode (MM)-based Secure Partition Manager implementation +SPM_MM := 0 # Flag to introduce an infinite loop in BL1 just before it exits into the next # image. This is meant to help debugging the post-BL2 phase. diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index a94879624..fca4d0133 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -96,10 +96,10 @@ const mmap_region_t plat_arm_mmap[] = { ARM_MAP_BL1_RW, #endif #endif /* TRUSTED_BOARD_BOOT */ -#if ENABLE_SPM && SPM_MM +#if SPM_MM ARM_SP_IMAGE_MMAP, #endif -#if ENABLE_SPM && !SPM_MM +#if ENABLE_SPM PLAT_MAP_SP_PACKAGE_MEM_RW, #endif #if ARM_BL31_IN_DRAM @@ -127,16 +127,16 @@ const mmap_region_t plat_arm_mmap[] = { MAP_DEVICE0, MAP_DEVICE1, ARM_V2M_MAP_MEM_PROTECT, -#if ENABLE_SPM && SPM_MM +#if SPM_MM ARM_SPM_BUF_EL3_MMAP, #endif -#if ENABLE_SPM && !SPM_MM +#if ENABLE_SPM PLAT_MAP_SP_PACKAGE_MEM_RO, #endif {0} }; -#if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM +#if defined(IMAGE_BL31) && SPM_MM const mmap_region_t plat_arm_secure_partition_mmap[] = { V2M_MAP_IOFPGA_EL0, /* for the UART */ MAP_REGION_FLAT(DEVICE0_BASE, \ @@ -190,7 +190,7 @@ static unsigned int get_interconnect_master(void) } #endif -#if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM +#if defined(IMAGE_BL31) && SPM_MM /* * Boot information passed to a secure partition during initialisation. Linear * indices in MP information will be filled at runtime. diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 98dd0a97f..1a251b828 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -61,7 +61,7 @@ * plat_arm_mmap array defined for each BL stage. */ #if defined(IMAGE_BL31) -# if ENABLE_SPM +# if ENABLE_SPM || SPM_MM # define PLAT_ARM_MMAP_ENTRIES 9 # define MAX_XLAT_TABLES 9 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 @@ -116,7 +116,7 @@ * calculated using the current BL31 PROGBITS debug size plus the sizes of * BL2 and BL1-RW */ -#if ENABLE_SPM && !SPM_MM +#if ENABLE_SPM #define PLAT_ARM_MAX_BL31_SIZE UL(0x60000) #else #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 3a9972bb4..446969c5b 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -282,9 +282,7 @@ else # if AArch64 BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 endif ifeq (${ENABLE_SPM},1) - ifeq (${SPM_MM},0) BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 - endif endif ifeq (${SPD},trusty) BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 diff --git a/plat/arm/common/aarch64/arm_ehf.c b/plat/arm/common/aarch64/arm_ehf.c index 4ae992c95..5144afc65 100644 --- a/plat/arm/common/aarch64/arm_ehf.c +++ b/plat/arm/common/aarch64/arm_ehf.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,7 +24,7 @@ ehf_pri_desc_t arm_exceptions[] = { /* Normal priority SDEI */ EHF_PRI_DESC(ARM_PRI_BITS, PLAT_SDEI_NORMAL_PRI), #endif -#if ENABLE_SPM +#if ENABLE_SPM || SPM_MM EHF_PRI_DESC(ARM_PRI_BITS, PLAT_SP_PRI), #endif }; diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index cda39b7d2..a60e34957 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -249,14 +249,12 @@ PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c \ endif # SPM uses libfdt in Arm platforms -ifeq (${SPM_MM},0) ifeq (${ENABLE_SPM},1) BL31_SOURCES += common/fdt_wrappers.c \ plat/common/plat_spm_rd.c \ plat/common/plat_spm_sp.c \ ${LIBFDT_SRCS} endif -endif ifneq (${TRUSTED_BOARD_BOOT},0) diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index a9cc85278..a42c7599d 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,7 +28,7 @@ * plat_arm_mmap array defined for each BL stage. */ #if defined(IMAGE_BL31) -# if ENABLE_SPM +# if ENABLE_SPM || SPM_MM # define PLAT_ARM_MMAP_ENTRIES 9 # define MAX_XLAT_TABLES 7 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 @@ -101,7 +101,7 @@ #elif defined(IMAGE_BL2U) # define PLATFORM_STACK_SIZE 0x400 #elif defined(IMAGE_BL31) -# if ENABLE_SPM +# if ENABLE_SPM || SPM_MM # define PLATFORM_STACK_SIZE 0x500 # else # define PLATFORM_STACK_SIZE 0x400 diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c index 3e207ecc2..ef13cdcef 100644 --- a/plat/arm/css/sgi/sgi_plat.c +++ b/plat/arm/css/sgi/sgi_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,7 +46,7 @@ const mmap_region_t plat_arm_mmap[] = { #if ARM_BL31_IN_DRAM ARM_MAP_BL31_SEC_DRAM, #endif -#if ENABLE_SPM +#if SPM_MM ARM_SP_IMAGE_MMAP, #endif #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3 @@ -61,13 +61,13 @@ const mmap_region_t plat_arm_mmap[] = { V2M_MAP_IOFPGA, CSS_SGI_MAP_DEVICE, SOC_CSS_MAP_DEVICE, -#if ENABLE_SPM +#if SPM_MM ARM_SPM_BUF_EL3_MMAP, #endif {0} }; -#if ENABLE_SPM && defined(IMAGE_BL31) +#if SPM_MM && defined(IMAGE_BL31) const mmap_region_t plat_arm_secure_partition_mmap[] = { PLAT_ARM_SECURE_MAP_DEVICE, ARM_SP_IMAGE_MMAP, @@ -77,12 +77,12 @@ const mmap_region_t plat_arm_secure_partition_mmap[] = { ARM_SPM_BUF_EL0_MMAP, {0} }; -#endif /* ENABLE_SPM && defined(IMAGE_BL31) */ +#endif /* SPM_MM && defined(IMAGE_BL31) */ #endif ARM_CASSERT_MMAP -#if ENABLE_SPM && defined(IMAGE_BL31) +#if SPM_MM && defined(IMAGE_BL31) /* * Boot information passed to a secure partition during initialisation. Linear * indices in MP information will be filled at runtime. @@ -130,7 +130,7 @@ const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( { return &plat_arm_secure_partition_boot_info; } -#endif /* ENABLE_SPM && defined(IMAGE_BL31) */ +#endif /* SPM_MM && defined(IMAGE_BL31) */ #if TRUSTED_BOARD_BOOT int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) diff --git a/plat/nvidia/tegra/scat/bl31.scat b/plat/nvidia/tegra/scat/bl31.scat index 2f5fd9ecb..ff7719a2e 100644 --- a/plat/nvidia/tegra/scat/bl31.scat +++ b/plat/nvidia/tegra/scat/bl31.scat @@ -95,7 +95,7 @@ LR_RO_DATA +0 /* cpu_ops must always be defined */ ScatterAssert(ImageLength(__CPU_OPS__) > 0) -#if ENABLE_SPM +#if ENABLE_SPM || SPM_MM LR_SPM +0 { /* diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk index fe1448ff1..ab1f69e68 100644 --- a/plat/socionext/synquacer/platform.mk +++ b/plat/socionext/synquacer/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -57,7 +57,7 @@ BL31_SOURCES += $(PLAT_PATH)/drivers/scp/sq_scmi.c \ drivers/arm/css/mhu/css_mhu_doorbell.c endif -ifeq (${ENABLE_SPM},1) +ifeq (${SPM_MM},1) $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) BL31_SOURCES += $(PLAT_PATH)/sq_spm.c diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c index c78fe9188..b86402179 100644 --- a/plat/socionext/synquacer/sq_bl31_setup.c +++ b/plat/socionext/synquacer/sq_bl31_setup.c @@ -159,7 +159,7 @@ void bl31_plat_runtime_setup(void) void bl31_plat_arch_setup(void) { static const mmap_region_t secure_partition_mmap[] = { -#if ENABLE_SPM && SPM_MM +#if SPM_MM MAP_REGION_FLAT(PLAT_SPM_BUF_BASE, PLAT_SPM_BUF_SIZE, MT_RW_DATA | MT_SECURE), @@ -173,7 +173,7 @@ void bl31_plat_arch_setup(void) sq_mmap_setup(BL31_BASE, BL31_SIZE, secure_partition_mmap); enable_mmu_el3(XLAT_TABLE_NC); -#if ENABLE_SPM && SPM_MM +#if SPM_MM memcpy((void *)SPM_SHIM_EXCEPTIONS_START, (void *)SPM_SHIM_EXCEPTIONS_LMA, (uintptr_t)SPM_SHIM_EXCEPTIONS_END - diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c index 1d80fa343..1219b34c0 100644 --- a/services/std_svc/std_svc_setup.c +++ b/services/std_svc/std_svc_setup.c @@ -45,7 +45,7 @@ static int32_t std_svc_setup(void) ret = 1; } -#if ENABLE_SPM +#if ENABLE_SPM || SPM_MM if (spm_setup() != 0) { ret = 1; } @@ -103,7 +103,7 @@ static uintptr_t std_svc_smc_handler(uint32_t smc_fid, SMC_RET1(handle, ret); } -#if ENABLE_SPM && SPM_MM +#if SPM_MM /* * Dispatch SPM calls to SPM SMC handler and return its return * value -- cgit v1.2.3 From 538b002046b567ed3c431633623f335b90476e40 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Mon, 14 Oct 2019 15:27:12 +0000 Subject: spm: Remove SPM Alpha 1 prototype and support files The Secure Partition Manager (SPM) prototype implementation is being removed. This is preparatory work for putting in place a dispatcher component that, in turn, enables partition managers at S-EL2 / S-EL1. This patch removes: - The core service files (std_svc/spm) - The Resource Descriptor headers (include/services) - SPRT protocol support and service definitions - SPCI protocol support and service definitions Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426 Signed-off-by: Paul Beesley Signed-off-by: Artsem Artsemenka --- Makefile | 10 - bl31/bl31.ld.S | 2 +- bl31/bl31.mk | 9 +- docs/getting_started/build-options.rst | 5 - include/lib/sprt/sprt_common.h | 38 - include/lib/sprt/sprt_host.h | 26 - include/plat/arm/common/arm_def.h | 6 +- include/plat/arm/common/arm_spm_def.h | 40 -- include/services/sp_res_desc.h | 253 ------- include/services/sp_res_desc_def.h | 94 --- include/services/spci_svc.h | 124 ---- include/services/spm_svc.h | 8 - include/services/sprt_svc.h | 74 -- lib/sprt/sprt_host.c | 48 -- lib/sprt/sprt_host.mk | 11 - lib/sprt/sprt_queue.c | 104 --- lib/sprt/sprt_queue.h | 47 -- make_helpers/defaults.mk | 3 - plat/arm/board/fvp/fvp_common.c | 6 - plat/arm/board/fvp/include/platform_def.h | 6 +- plat/arm/board/fvp/platform.mk | 3 - plat/arm/common/aarch64/arm_ehf.c | 2 +- plat/arm/common/arm_common.mk | 8 - plat/arm/css/sgi/include/sgi_base_platform_def.h | 4 +- plat/arm/css/sgi/sgi-common.mk | 4 +- plat/common/plat_spm_rd.c | 316 --------- plat/common/plat_spm_sp.c | 93 --- plat/nvidia/tegra/scat/bl31.scat | 2 +- services/std_svc/spm/README.rst | 3 - services/std_svc/spm/aarch64/spm_helpers.S | 74 -- services/std_svc/spm/aarch64/spm_shim_exceptions.S | 128 ---- services/std_svc/spm/spci.c | 769 --------------------- services/std_svc/spm/spm.mk | 30 - services/std_svc/spm/spm_buffers.c | 112 --- services/std_svc/spm/spm_main.c | 359 ---------- services/std_svc/spm/spm_private.h | 119 ---- services/std_svc/spm/spm_setup.c | 167 ----- services/std_svc/spm/spm_shim_private.h | 34 - services/std_svc/spm/spm_xlat.c | 381 ---------- services/std_svc/spm/sprt.c | 219 ------ services/std_svc/std_svc_setup.c | 2 +- 41 files changed, 13 insertions(+), 3730 deletions(-) delete mode 100644 include/lib/sprt/sprt_common.h delete mode 100644 include/lib/sprt/sprt_host.h delete mode 100644 include/services/sp_res_desc.h delete mode 100644 include/services/sp_res_desc_def.h delete mode 100644 include/services/spci_svc.h delete mode 100644 include/services/sprt_svc.h delete mode 100644 lib/sprt/sprt_host.c delete mode 100644 lib/sprt/sprt_host.mk delete mode 100644 lib/sprt/sprt_queue.c delete mode 100644 lib/sprt/sprt_queue.h delete mode 100644 plat/common/plat_spm_rd.c delete mode 100644 plat/common/plat_spm_sp.c delete mode 100644 services/std_svc/spm/README.rst delete mode 100644 services/std_svc/spm/aarch64/spm_helpers.S delete mode 100644 services/std_svc/spm/aarch64/spm_shim_exceptions.S delete mode 100644 services/std_svc/spm/spci.c delete mode 100644 services/std_svc/spm/spm.mk delete mode 100644 services/std_svc/spm/spm_buffers.c delete mode 100644 services/std_svc/spm/spm_main.c delete mode 100644 services/std_svc/spm/spm_private.h delete mode 100644 services/std_svc/spm/spm_setup.c delete mode 100644 services/std_svc/spm/spm_shim_private.h delete mode 100644 services/std_svc/spm/spm_xlat.c delete mode 100644 services/std_svc/spm/sprt.c diff --git a/Makefile b/Makefile index ff7c5b7d4..4bbe7154f 100644 --- a/Makefile +++ b/Makefile @@ -571,14 +571,6 @@ ifeq ($(CTX_INCLUDE_MTE_REGS),1) endif endif -# The SPCI-based SPM implementation and the MM-based SPM implementation cannot -# be enabled at the same time. -ifeq ($(ENABLE_SPM),1) - ifeq ($(SPM_MM),1) - $(error Use only one of the ENABLE_SPM and SPM_MM flags) - endif -endif - ################################################################################ # Process platform overrideable behaviour ################################################################################ @@ -719,7 +711,6 @@ $(eval $(call assert_boolean,ENABLE_PMF)) $(eval $(call assert_boolean,ENABLE_PSCI_STAT)) $(eval $(call assert_boolean,ENABLE_RUNTIME_INSTRUMENTATION)) $(eval $(call assert_boolean,ENABLE_SPE_FOR_LOWER_ELS)) -$(eval $(call assert_boolean,ENABLE_SPM)) $(eval $(call assert_boolean,ENABLE_SVE_FOR_NS)) $(eval $(call assert_boolean,ERROR_DEPRECATED)) $(eval $(call assert_boolean,FAULT_INJECTION_SUPPORT)) @@ -784,7 +775,6 @@ $(eval $(call add_define,ENABLE_PMF)) $(eval $(call add_define,ENABLE_PSCI_STAT)) $(eval $(call add_define,ENABLE_RUNTIME_INSTRUMENTATION)) $(eval $(call add_define,ENABLE_SPE_FOR_LOWER_ELS)) -$(eval $(call add_define,ENABLE_SPM)) $(eval $(call add_define,ENABLE_SVE_FOR_NS)) $(eval $(call add_define,ERROR_DEPRECATED)) $(eval $(call add_define,FAULT_INJECTION_SUPPORT)) diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index a4be3b234..a598e59cf 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -142,7 +142,7 @@ SECTIONS ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, "cpu_ops not defined for this platform.") -#if ENABLE_SPM || SPM_MM +#if SPM_MM #ifndef SPM_SHIM_EXCEPTIONS_VMA #define SPM_SHIM_EXCEPTIONS_VMA RAM #endif diff --git a/bl31/bl31.mk b/bl31/bl31.mk index 7ff054a7e..33d414dcd 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -5,16 +5,11 @@ # ################################################################################ -# Include Makefile for either of the supported SPM implementations +# Include Makefile for the SPM-MM implementation ################################################################################ -ifeq (${ENABLE_SPM},1) - $(info Including SPM (SPCI) makefile) - include services/std_svc/spm/spm.mk -endif - ifeq (${SPM_MM},1) ifeq (${EL3_EXCEPTION_HANDLING},0) - $(error EL3_EXCEPTION_HANDLING must be 1 for SPM support) + $(error EL3_EXCEPTION_HANDLING must be 1 for SPM-MM support) else $(info Including SPM Management Mode (MM) makefile) include services/std_svc/spm_mm/spm.mk diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 87ce94eb4..87429f285 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -235,11 +235,6 @@ Common build options The default is 1 but is automatically disabled when the target architecture is AArch32. -- ``ENABLE_SPM`` : Boolean option to enable the SPCI-based Secure Partition - Manager (SPM) implementation. - Refer to the :ref:`Secure Partition Manager` guide for more details about - this feature. Default is 0. - - ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension (SVE) for the Non-secure world only. SVE is an optional architectural feature for AArch64. Note that when SVE is enabled for the Non-secure world, access diff --git a/include/lib/sprt/sprt_common.h b/include/lib/sprt/sprt_common.h deleted file mode 100644 index 27d502749..000000000 --- a/include/lib/sprt/sprt_common.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPRT_COMMON_H -#define SPRT_COMMON_H - -#define SPRT_MAX_MSG_ARGS 6 - -/* - * Message types supported. - */ -#define SPRT_MSG_TYPE_SERVICE_HANDLE_OPEN 1 -#define SPRT_MSG_TYPE_SERVICE_HANDLE_CLOSE 2 -/* TODO: Add other types of SPRT messages. */ -#define SPRT_MSG_TYPE_SERVICE_TUN_REQUEST 10 - -/* - * Struct that defines the layout of the fields corresponding to a request in - * shared memory. - */ -struct __attribute__((__packed__)) sprt_queue_entry_message { - uint32_t type; /* Type of message (result of an SPCI call). */ - uint16_t client_id; /* SPCI client ID */ - uint16_t service_handle;/* SPCI service handle */ - uint32_t session_id; /* Optional SPCI session ID */ - uint32_t token; /* SPCI request token */ - uint64_t args[SPRT_MAX_MSG_ARGS]; -}; - -#define SPRT_QUEUE_ENTRY_MSG_SIZE (sizeof(struct sprt_queue_entry_message)) - -#define SPRT_QUEUE_NUM_BLOCKING 0 -#define SPRT_QUEUE_NUM_NON_BLOCKING 1 - -#endif /* SPRT_COMMON_H */ diff --git a/include/lib/sprt/sprt_host.h b/include/lib/sprt/sprt_host.h deleted file mode 100644 index f888141dd..000000000 --- a/include/lib/sprt/sprt_host.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef SPRT_HOST_H -#define SPRT_HOST_H - -#include - -#include "sprt_common.h" - -/* - * Initialize the specified buffer to be used by SPM. - */ -void sprt_initialize_queues(void *buffer_base, size_t buffer_size); - -/* - * Push a message to the queue number `queue_num` in a buffer that has been - * initialized by `sprt_initialize_queues`. - */ -int sprt_push_message(void *buffer_base, - const struct sprt_queue_entry_message *message, - int queue_num); - -#endif /* SPRT_HOST_H */ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 8095bed70..72e2e8e96 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -457,7 +457,7 @@ * Trusted DRAM (if available) or the DRAM region secured by the TrustZone * controller. */ -# if ENABLE_SPM +# if SPM_MM # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) @@ -500,9 +500,9 @@ * SPD and no SPM, as they are the only ones that can be used as BL32. */ #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME -# if defined(SPD_none) && !ENABLE_SPM && !SPM_MM +# if defined(SPD_none) && !SPM_MM # undef BL32_BASE -# endif /* defined(SPD_none) && !ENABLE_SPM && !SPM_MM*/ +# endif /* defined(SPD_none) && !SPM_MM*/ #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ /******************************************************************************* diff --git a/include/plat/arm/common/arm_spm_def.h b/include/plat/arm/common/arm_spm_def.h index 16c806ba6..c43583de2 100644 --- a/include/plat/arm/common/arm_spm_def.h +++ b/include/plat/arm/common/arm_spm_def.h @@ -9,31 +9,6 @@ #include #include -/* - * Reserve 4 MiB for binaries of Secure Partitions and Resource Description - * blobs. - */ -#define PLAT_SP_PACKAGE_BASE BL32_BASE -#define PLAT_SP_PACKAGE_SIZE ULL(0x400000) - -#define PLAT_MAP_SP_PACKAGE_MEM_RO MAP_REGION_FLAT( \ - PLAT_SP_PACKAGE_BASE, \ - PLAT_SP_PACKAGE_SIZE, \ - MT_MEMORY | MT_RO | MT_SECURE) -#define PLAT_MAP_SP_PACKAGE_MEM_RW MAP_REGION_FLAT( \ - PLAT_SP_PACKAGE_BASE, \ - PLAT_SP_PACKAGE_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) - -/* - * The rest of the memory reserved for BL32 is free for SPM to use it as memory - * pool to allocate memory regions requested in the resource description. - */ -#define PLAT_SPM_HEAP_BASE (PLAT_SP_PACKAGE_BASE + PLAT_SP_PACKAGE_SIZE) -#define PLAT_SPM_HEAP_SIZE (BL32_LIMIT - BL32_BASE - PLAT_SP_PACKAGE_SIZE) - -#if SPM_MM - /* * If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the * region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition @@ -121,23 +96,8 @@ /* Total number of memory regions with distinct properties */ #define ARM_SP_IMAGE_NUM_MEM_REGIONS 6 -#endif /* SPM_MM */ - /* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */ #define PLAT_SPM_COOKIE_0 ULL(0) #define PLAT_SPM_COOKIE_1 ULL(0) -/* - * Max number of elements supported by SPM in this platform. The defines below - * are used to allocate memory at compile time for different arrays in SPM. - */ -#define PLAT_SPM_MAX_PARTITIONS U(2) - -#define PLAT_SPM_MEM_REGIONS_MAX U(80) -#define PLAT_SPM_NOTIFICATIONS_MAX U(30) -#define PLAT_SPM_SERVICES_MAX U(30) - -#define PLAT_SPCI_HANDLES_MAX_NUM U(20) -#define PLAT_SPM_RESPONSES_MAX U(30) - #endif /* ARM_SPM_DEF_H */ diff --git a/include/services/sp_res_desc.h b/include/services/sp_res_desc.h deleted file mode 100644 index b8be72eeb..000000000 --- a/include/services/sp_res_desc.h +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_RES_DESC_H -#define SPM_RES_DESC_H - -#include - -#include - -/******************************************************************************* - * Attribute Section - ******************************************************************************/ - -struct sp_rd_sect_attribute { - /* - * Version of the resource description. - */ - uint16_t version; - - /* - * Type of the Secure Partition: - * - bit[0]: SP Type - * - b'0: UP SP - * - b'1: MP SP - * If UP SP: - * - bit[1]: Type of UP SP - * - b'0: Migratable UP SP - * - b'1: Pinned UP SP - */ - uint16_t sp_type; - - /* - * If this is a Pinned UP SP, PE on which the Pinned UP SP will run. - */ - uint32_t pe_mpidr; - - /* - * Run-Time Exception Level: - * - 0: SEL0 SP - * - 1: SEL1 SP - */ - uint8_t runtime_el; - - /* - * Type of Execution: - * - 0: Init-time only - * - 1: Run-time Execution - */ - uint8_t exec_type; - - /* - * Expected behavior upon failure: - * - 0: Restartable - * - 1: One-Shot - */ - uint8_t panic_policy; - - /* - * Translation Granule to use in the SP translation regime: - * - 0: 4KB - * - 1: 16KB - * - 2: 64KB - */ - uint8_t xlat_granule; - - /* - * Size of the SP binary in bytes. - */ - uint32_t binary_size; - - /* - * - If SP is NOT PIE: - * - VA Address where the SP expects to be loaded. - * - If SP is PIE: - * - Ignored. - */ - uint64_t load_address; - - /* - * Initial execution address. This is a VA as the SP sees it. - */ - uint64_t entrypoint; -}; - -/******************************************************************************* - * Memory Region Section - ******************************************************************************/ - -struct sp_rd_sect_mem_region { - /* - * Name of a Memory region, including null terminator. Reserved names: - * - "Client Shared Memory Region": - * Memory region where memory shared by clients shall be mapped. - * - "Queue Memory Region": - * Memory region shared with SPM for SP queue management. - */ - char name[RD_MEM_REGION_NAME_LEN]; - - /* - * Memory Attributes: - * - bits[3:0]: Type of memory - * - 0: Device - * - 1: Code - * - 2: Data - * - 3: BSS - * - 4: Read-only Data - * - 5: SPM-to-SP Shared Memory Region - * - 6: Client Shared Memory Region - * - 7: Miscellaneous - * - If memory is { SPM-to-SP shared Memory, Client Shared Memory, - * Miscellaneous } - * - bits[4]: Position Independent - * - b'0: Position Dependent - * - b'1: Position Independent - */ - uint32_t attr; - - /* - * Base address of the memory region. - */ - uint64_t base; - - /* - * Size of the memory region. - */ - uint64_t size; - - /* - * Pointer to next memory region (or NULL if this is the last one). - */ - struct sp_rd_sect_mem_region *next; -}; - -/******************************************************************************* - * Notification Section - ******************************************************************************/ - -struct sp_rd_sect_notification { - /* - * Notification attributes: - * - bit[31]: Notification Type - * - b'0: Platform Notification - * - b'1: Interrupt - * If Notification Type == Platform Notification - * - bits[15:0]: Implementation-defined Notification ID - * If Notification Type == Interrupt - * - bits[15:0]: IRQ number - * - bits[23:16]: Interrupt Priority - * - bit[24]: Trigger Type - * - b'0: Edge Triggered - * - b'1: Level Triggered - * - bit[25]: Trigger Level - * - b'0: Falling or Low - * - b'1: Rising or High - */ - uint32_t attr; - - /* - * Processing Element. - * If Notification Type == Interrupt && IRQ number is { SGI, LPI } - * - PE ID to which IRQ will be forwarded - */ - uint32_t pe; - - /* - * Pointer to next notification (or NULL if this is the last one). - */ - struct sp_rd_sect_notification *next; -}; - -/******************************************************************************* - * Service Description Section - ******************************************************************************/ - -struct sp_rd_sect_service { - /* - * Service identifier. - */ - uint32_t uuid[4]; - - /* - * Accessibility Options: - * - bit[0]: Accessibility by secure-world clients - * - b'0: Not Accessible - * - b'1: Accessible - * - bit[1]: Accessible by EL3 - * - b'0: Not Accessible - * - b'1: Accessible - * - bit[2]: Accessible by normal-world clients - * - b'0: Not Accessible - * - b'1: Accessible - */ - uint8_t accessibility; - - /* - * Request type supported: - * - bit[0]: Blocking request - * - b'0: Not Enable - * - b'1: Enable - * - bit[1]: Non-blocking request - * - b'0: Not Enable - * - b'1: Enable - */ - uint8_t request_type; - - /* - * Maximum number of client connections that the service can support. - */ - uint16_t connection_quota; - - /* - * If the service requires secure world memory to be shared with its - * clients: - * - Maximum amount of secure world memory in bytes to reserve from the - * secure world memory pool for the service. - */ - uint32_t secure_mem_size; - - /* - * Interrupt number used to notify the SP for the service. - * - Should also be enabled in the Notification Section. - */ - uint32_t interrupt_num; - - /* - * Pointer to next service (or NULL if this is the last one). - */ - struct sp_rd_sect_service *next; -}; - -/******************************************************************************* - * Complete resource description struct - ******************************************************************************/ - -struct sp_res_desc { - - /* Attribute Section */ - struct sp_rd_sect_attribute attribute; - - /* System Resource Section */ - struct sp_rd_sect_mem_region *mem_region; - - struct sp_rd_sect_notification *notification; - - /* Service Section */ - struct sp_rd_sect_service *service; -}; - -#endif /* SPM_RES_DESC_H */ diff --git a/include/services/sp_res_desc_def.h b/include/services/sp_res_desc_def.h deleted file mode 100644 index 5a3c50d7f..000000000 --- a/include/services/sp_res_desc_def.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_RES_DESC_DEFS_H -#define SPM_RES_DESC_DEFS_H - -#include - -/******************************************************************************* - * Attribute Section - ******************************************************************************/ - -#define RD_ATTR_TYPE_UP_MIGRATABLE U(0) -#define RD_ATTR_TYPE_UP_PINNED U(2) -#define RD_ATTR_TYPE_MP U(1) - -#define RD_ATTR_RUNTIME_SEL0 U(0) -#define RD_ATTR_RUNTIME_SEL1 U(1) - -#define RD_ATTR_INIT_ONLY U(0) -#define RD_ATTR_RUNTIME U(1) - -#define RD_ATTR_PANIC_RESTART U(0) -#define RD_ATTR_PANIC_ONESHOT U(1) - -#define RD_ATTR_XLAT_GRANULE_4KB U(0) -#define RD_ATTR_XLAT_GRANULE_16KB U(1) -#define RD_ATTR_XLAT_GRANULE_64KB U(2) - -/******************************************************************************* - * Memory Region Section - ******************************************************************************/ - -#define RD_MEM_REGION_NAME_LEN U(32) - -#define RD_MEM_DEVICE U(0) -#define RD_MEM_NORMAL_CODE U(1) -#define RD_MEM_NORMAL_DATA U(2) -#define RD_MEM_NORMAL_BSS U(3) -#define RD_MEM_NORMAL_RODATA U(4) -#define RD_MEM_NORMAL_SPM_SP_SHARED_MEM U(5) -#define RD_MEM_NORMAL_CLIENT_SHARED_MEM U(6) -#define RD_MEM_NORMAL_MISCELLANEOUS U(7) - -#define RD_MEM_MASK U(15) - -#define RD_MEM_IS_PIE (U(1) << 4) - -/******************************************************************************* - * Notification Section - ******************************************************************************/ - -#define RD_NOTIF_TYPE_PLATFORM (U(0) << 31) -#define RD_NOTIF_TYPE_INTERRUPT (U(1) << 31) - -#define RD_NOTIF_PLAT_ID_MASK U(0xFFFF) -#define RD_NOTIF_PLAT_ID_SHIFT U(0) - -#define RD_NOTIF_PLATFORM(id) \ - (RD_NOTIF_TYPE_PLATFORM \ - | (((id) & RD_NOTIF_PLAT_ID_MASK) << RD_NOTIF_PLAT_ID_SHIFT)) - -#define RD_NOTIF_IRQ_NUM_MASK U(0xFFFF) -#define RD_NOTIF_IRQ_NUM_SHIFT U(0) -#define RD_NOTIF_IRQ_PRIO_MASK U(0xFF) -#define RD_NOTIF_IRQ_PRIO_SHIFT U(16) - -#define RD_NOTIF_IRQ_EDGE_FALLING U(0) -#define RD_NOTIF_IRQ_EDGE_RISING U(2) -#define RD_NOTIF_IRQ_LEVEL_LOW U(1) -#define RD_NOTIF_IRQ_LEVEL_HIGH U(3) -#define RD_NOTIF_IRQ_TRIGGER_SHIFT U(24) - -#define RD_NOTIF_IRQ(num, prio, trig) \ - (RD_NOTIF_TYPE_IRQ \ - | (((num) & RD_NOTIF_IRQ_NUM_MASK) << RD_NOTIF_IRQ_NUM_SHIFT) \ - | (((prio) & RD_NOTIF_IRQ_PRIO_MASK) << RD_NOTIF_IRQ_PRIO_SHIFT) \ - | (((trig) << RD_NOTIF_IRQ_TRIGGER_SHIFT))) - -/******************************************************************************* - * Service Description Section - ******************************************************************************/ - -#define RD_SERV_ACCESS_SECURE (U(1) << 0) -#define RD_SERV_ACCESS_EL3 (U(1) << 1) -#define RD_SERV_ACCESS_NORMAL (U(1) << 2) - -#define RD_SERV_SUPPORT_BLOCKING (U(1) << 0) -#define RD_SERV_SUPPORT_NON_BLOCKING (U(1) << 0) - -#endif /* SPM_RES_DESC_DEFS_H */ diff --git a/include/services/spci_svc.h b/include/services/spci_svc.h deleted file mode 100644 index 1d02bfa9c..000000000 --- a/include/services/spci_svc.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPCI_SVC_H -#define SPCI_SVC_H - -#include -#include - -/* SPCI_VERSION helpers */ - -#define SPCI_VERSION_MAJOR U(0) -#define SPCI_VERSION_MAJOR_SHIFT 16 -#define SPCI_VERSION_MAJOR_MASK U(0x7FFF) -#define SPCI_VERSION_MINOR U(1) -#define SPCI_VERSION_MINOR_SHIFT 0 -#define SPCI_VERSION_MINOR_MASK U(0xFFFF) -#define SPCI_VERSION_FORM(major, minor) ((((major) & SPCI_VERSION_MAJOR_MASK) \ - << SPCI_VERSION_MAJOR_SHIFT) | \ - ((minor) & SPCI_VERSION_MINOR_MASK)) -#define SPCI_VERSION_COMPILED SPCI_VERSION_FORM(SPCI_VERSION_MAJOR, \ - SPCI_VERSION_MINOR) - -/* Definitions to build the complete SMC ID */ - -#define SPCI_FID_MISC_FLAG (U(0) << 27) -#define SPCI_FID_MISC_SHIFT U(20) -#define SPCI_FID_MISC_MASK U(0x7F) - -#define SPCI_FID_TUN_FLAG (U(1) << 27) -#define SPCI_FID_TUN_SHIFT U(24) -#define SPCI_FID_TUN_MASK U(0x7) - -#define OEN_SPCI_START U(0x30) -#define OEN_SPCI_END U(0x3F) - -#define SPCI_SMC(spci_fid) ((OEN_SPCI_START << FUNCID_OEN_SHIFT) | \ - (U(1) << 31) | (spci_fid)) -#define SPCI_MISC_32(misc_fid) ((SMC_32 << FUNCID_CC_SHIFT) | \ - SPCI_FID_MISC_FLAG | \ - SPCI_SMC((misc_fid) << SPCI_FID_MISC_SHIFT)) -#define SPCI_MISC_64(misc_fid) ((SMC_64 << FUNCID_CC_SHIFT) | \ - SPCI_FID_MISC_FLAG | \ - SPCI_SMC((misc_fid) << SPCI_FID_MISC_SHIFT)) -#define SPCI_TUN_32(tun_fid) ((SMC_32 << FUNCID_CC_SHIFT) | \ - SPCI_FID_TUN_FLAG | \ - SPCI_SMC((tun_fid) << SPCI_FID_TUN_SHIFT)) -#define SPCI_TUN_64(tun_fid) ((SMC_64 << FUNCID_CC_SHIFT) | \ - SPCI_FID_TUN_FLAG | \ - SPCI_SMC((tun_fid) << SPCI_FID_TUN_SHIFT)) - -/* SPCI miscellaneous functions */ - -#define SPCI_FID_VERSION U(0x0) -#define SPCI_FID_SERVICE_HANDLE_OPEN U(0x2) -#define SPCI_FID_SERVICE_HANDLE_CLOSE U(0x3) -#define SPCI_FID_SERVICE_MEM_REGISTER U(0x4) -#define SPCI_FID_SERVICE_MEM_UNREGISTER U(0x5) -#define SPCI_FID_SERVICE_MEM_PUBLISH U(0x6) -#define SPCI_FID_SERVICE_REQUEST_BLOCKING U(0x7) -#define SPCI_FID_SERVICE_REQUEST_START U(0x8) -#define SPCI_FID_SERVICE_GET_RESPONSE U(0x9) -#define SPCI_FID_SERVICE_RESET_CLIENT_STATE U(0xA) - -/* SPCI tunneling functions */ - -#define SPCI_FID_SERVICE_TUN_REQUEST_START U(0x0) -#define SPCI_FID_SERVICE_REQUEST_RESUME U(0x1) -#define SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING U(0x2) - -/* Complete SMC IDs and associated values */ - -#define SPCI_VERSION SPCI_MISC_32(SPCI_FID_VERSION) - -#define SPCI_SERVICE_HANDLE_OPEN SPCI_MISC_32(SPCI_FID_SERVICE_HANDLE_OPEN) -#define SPCI_SERVICE_HANDLE_OPEN_NOTIFY_BIT U(1) - -#define SPCI_SERVICE_HANDLE_CLOSE SPCI_MISC_32(SPCI_FID_SERVICE_HANDLE_CLOSE) - -#define SPCI_SERVICE_MEM_REGISTER_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_REGISTER) -#define SPCI_SERVICE_MEM_REGISTER_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_REGISTER) - -#define SPCI_SERVICE_MEM_UNREGISTER_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_UNREGISTER) -#define SPCI_SERVICE_MEM_UNREGISTER_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_UNREGISTER) - -#define SPCI_SERVICE_MEM_PUBLISH_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_PUBLISH) -#define SPCI_SERVICE_MEM_PUBLISH_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_PUBLISH) - -#define SPCI_SERVICE_REQUEST_BLOCKING_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_REQUEST_BLOCKING) -#define SPCI_SERVICE_REQUEST_BLOCKING_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_REQUEST_BLOCKING) - -#define SPCI_SERVICE_REQUEST_START_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_REQUEST_START) -#define SPCI_SERVICE_REQUEST_START_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_REQUEST_START) - -#define SPCI_SERVICE_GET_RESPONSE_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_GET_RESPONSE) -#define SPCI_SERVICE_GET_RESPONSE_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_GET_RESPONSE) - -#define SPCI_SERVICE_RESET_CLIENT_STATE_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_RESET_CLIENT_STATE) -#define SPCI_SERVICE_RESET_CLIENT_STATE_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_RESET_CLIENT_STATE) - -#define SPCI_SERVICE_TUN_REQUEST_START_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_TUN_REQUEST_START) -#define SPCI_SERVICE_TUN_REQUEST_START_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_TUN_REQUEST_START) - -#define SPCI_SERVICE_REQUEST_RESUME_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_REQUEST_RESUME) -#define SPCI_SERVICE_REQUEST_RESUME_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_REQUEST_RESUME) - -#define SPCI_SERVICE_TUN_REQUEST_BLOCKING_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING) -#define SPCI_SERVICE_TUN_REQUEST_BLOCKING_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING) - -/* SPCI error codes. */ - -#define SPCI_SUCCESS 0 -#define SPCI_NOT_SUPPORTED -1 -#define SPCI_INVALID_PARAMETER -2 -#define SPCI_NO_MEMORY -3 -#define SPCI_BUSY -4 -#define SPCI_QUEUED -5 -#define SPCI_DENIED -6 -#define SPCI_NOT_PRESENT -7 - -#endif /* SPCI_SVC_H */ diff --git a/include/services/spm_svc.h b/include/services/spm_svc.h index a3723a0f5..c8dbe5d55 100644 --- a/include/services/spm_svc.h +++ b/include/services/spm_svc.h @@ -7,8 +7,6 @@ #ifndef SPM_SVC_H #define SPM_SVC_H -#if SPM_MM - #include #define SPM_VERSION_MAJOR U(0) @@ -61,16 +59,12 @@ #define SPM_DENIED -3 #define SPM_NO_MEMORY -5 -#endif /* SPM_MM */ - #ifndef __ASSEMBLER__ #include int32_t spm_setup(void); -#if SPM_MM - uint64_t spm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, @@ -83,8 +77,6 @@ uint64_t spm_smc_handler(uint32_t smc_fid, /* Helper to enter a Secure Partition */ uint64_t spm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3); -#endif /* SPM_MM */ - #endif /* __ASSEMBLER__ */ #endif /* SPM_SVC_H */ diff --git a/include/services/sprt_svc.h b/include/services/sprt_svc.h deleted file mode 100644 index 2421ea251..000000000 --- a/include/services/sprt_svc.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPRT_SVC_H -#define SPRT_SVC_H - -#include -#include - -/* SPRT_VERSION helpers */ - -#define SPRT_VERSION_MAJOR U(0) -#define SPRT_VERSION_MAJOR_SHIFT 16 -#define SPRT_VERSION_MAJOR_MASK U(0x7FFF) -#define SPRT_VERSION_MINOR U(1) -#define SPRT_VERSION_MINOR_SHIFT 0 -#define SPRT_VERSION_MINOR_MASK U(0xFFFF) -#define SPRT_VERSION_FORM(major, minor) ((((major) & SPRT_VERSION_MAJOR_MASK) \ - << SPRT_VERSION_MAJOR_SHIFT) | \ - ((minor) & SPRT_VERSION_MINOR_MASK)) -#define SPRT_VERSION_COMPILED SPRT_VERSION_FORM(SPRT_VERSION_MAJOR, \ - SPRT_VERSION_MINOR) - -/* SPRT function IDs */ - -#define SPRT_FID_VERSION U(0x0) -#define SPRT_FID_PUT_RESPONSE U(0x1) -#define SPRT_FID_YIELD U(0x5) -#define SPRT_FID_PANIC U(0x7) -#define SPRT_FID_MEMORY_PERM_ATTR_GET U(0xB) -#define SPRT_FID_MEMORY_PERM_ATTR_SET U(0xC) - -#define SPRT_FID_MASK U(0xFF) - -/* Definitions to build the complete SMC ID */ - -#define OEN_SPRT_START U(0x20) -#define OEN_SPRT_END U(0x2F) - -#define SPRT_SMC_64(sprt_fid) ((OEN_SPRT_START << FUNCID_OEN_SHIFT) | \ - (U(1) << 31) | ((sprt_fid) & SPRT_FID_MASK) | \ - (SMC_64 << FUNCID_CC_SHIFT)) -#define SPRT_SMC_32(sprt_fid) ((OEN_SPRT_START << FUNCID_OEN_SHIFT) | \ - (U(1) << 31) | ((sprt_fid) & SPRT_FID_MASK) | \ - (SMC_32 << FUNCID_CC_SHIFT)) - -/* Complete SMC IDs */ - -#define SPRT_VERSION SPRT_SMC_32(SPRT_FID_VERSION) -#define SPRT_PUT_RESPONSE_AARCH64 SPRT_SMC_64(SPRT_FID_PUT_RESPONSE) -#define SPRT_YIELD_AARCH64 SPRT_SMC_64(SPRT_FID_YIELD) -#define SPRT_PANIC_AARCH64 SPRT_SMC_64(SPRT_FID_PANIC) -#define SPRT_MEMORY_PERM_ATTR_GET_AARCH64 SPRT_SMC_64(SPRT_FID_MEMORY_PERM_ATTR_GET) -#define SPRT_MEMORY_PERM_ATTR_SET_AARCH64 SPRT_SMC_64(SPRT_FID_MEMORY_PERM_ATTR_SET) - -/* Defines used by SPRT_MEMORY_PERM_ATTR_{GET,SET}_AARCH64 */ - -#define SPRT_MEMORY_PERM_ATTR_RO U(0) -#define SPRT_MEMORY_PERM_ATTR_RW U(1) -#define SPRT_MEMORY_PERM_ATTR_RO_EXEC U(2) -/* U(3) is reserved */ -#define SPRT_MEMORY_PERM_ATTR_MASK U(3) -#define SPRT_MEMORY_PERM_ATTR_SHIFT 3 - -/* SPRT error codes. */ - -#define SPRT_SUCCESS 0 -#define SPRT_NOT_SUPPORTED -1 -#define SPRT_INVALID_PARAMETER -2 - -#endif /* SPRT_SVC_H */ diff --git a/lib/sprt/sprt_host.c b/lib/sprt/sprt_host.c deleted file mode 100644 index c4d436e1c..000000000 --- a/lib/sprt/sprt_host.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include "sprt_common.h" -#include "sprt_queue.h" - -void sprt_initialize_queues(void *buffer_base, size_t buffer_size) -{ - /* Initialize queue for blocking messages */ - - void *blocking_base = buffer_base; - uint32_t blocking_num = 4U; - size_t blocking_size = SPRT_QUEUE_HEADER_SIZE + - SPRT_QUEUE_ENTRY_MSG_SIZE * blocking_num; - - sprt_queue_init(blocking_base, blocking_num, SPRT_QUEUE_ENTRY_MSG_SIZE); - - /* Initialize queue for non-blocking messages */ - - void *non_blocking_base = (void *)((uintptr_t)blocking_base + blocking_size); - size_t non_blocking_size = buffer_size - blocking_size; - uint32_t non_blocking_num = (non_blocking_size - SPRT_QUEUE_HEADER_SIZE) / - SPRT_QUEUE_ENTRY_MSG_SIZE; - - sprt_queue_init(non_blocking_base, non_blocking_num, SPRT_QUEUE_ENTRY_MSG_SIZE); -} - -int sprt_push_message(void *buffer_base, - const struct sprt_queue_entry_message *message, - int queue_num) -{ - struct sprt_queue *q = buffer_base; - - while (queue_num-- > 0) { - uintptr_t next_addr = (uintptr_t)q + sizeof(struct sprt_queue) + - q->entry_num * q->entry_size; - q = (struct sprt_queue *) next_addr; - } - - return sprt_queue_push(q, message); -} diff --git a/lib/sprt/sprt_host.mk b/lib/sprt/sprt_host.mk deleted file mode 100644 index abcfe5e49..000000000 --- a/lib/sprt/sprt_host.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2018, Arm Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -SPRT_LIB_SOURCES := $(addprefix lib/sprt/, \ - sprt_host.c \ - sprt_queue.c) - -SPRT_LIB_INCLUDES := -Iinclude/lib/sprt/ diff --git a/lib/sprt/sprt_queue.c b/lib/sprt/sprt_queue.c deleted file mode 100644 index 2bd4139ea..000000000 --- a/lib/sprt/sprt_queue.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -#include "sprt_queue.h" - -void sprt_queue_init(void *queue_base, uint32_t entry_num, uint32_t entry_size) -{ - assert(queue_base != NULL); - assert(entry_size > 0U); - assert(entry_num > 0U); - - struct sprt_queue *queue = (struct sprt_queue *)queue_base; - - queue->entry_num = entry_num; - queue->entry_size = entry_size; - queue->idx_write = 0U; - queue->idx_read = 0U; - - memset(queue->data, 0, entry_num * entry_size); -} - -int sprt_queue_is_empty(void *queue_base) -{ - assert(queue_base != NULL); - - struct sprt_queue *queue = (struct sprt_queue *)queue_base; - - return (queue->idx_write == queue->idx_read); -} - -int sprt_queue_is_full(void *queue_base) -{ - assert(queue_base != NULL); - - struct sprt_queue *queue = (struct sprt_queue *)queue_base; - - uint32_t idx_next_write = (queue->idx_write + 1) % queue->entry_num; - - return (idx_next_write == queue->idx_read); -} - -int sprt_queue_push(void *queue_base, const void *entry) -{ - assert(entry != NULL); - assert(queue_base != NULL); - - if (sprt_queue_is_full(queue_base) != 0) { - return -ENOMEM; - } - - struct sprt_queue *queue = (struct sprt_queue *)queue_base; - - uint8_t *dst_entry = &queue->data[queue->entry_size * queue->idx_write]; - - memcpy(dst_entry, entry, queue->entry_size); - - /* - * Make sure that the message data is visible before increasing the - * counter of available messages. - */ - __asm__ volatile("dmb st" ::: "memory"); - - queue->idx_write = (queue->idx_write + 1) % queue->entry_num; - - __asm__ volatile("dmb st" ::: "memory"); - - return 0; -} - -int sprt_queue_pop(void *queue_base, void *entry) -{ - assert(entry != NULL); - assert(queue_base != NULL); - - if (sprt_queue_is_empty(queue_base) != 0) { - return -ENOENT; - } - - struct sprt_queue *queue = (struct sprt_queue *)queue_base; - - uint8_t *src_entry = &queue->data[queue->entry_size * queue->idx_read]; - - memcpy(entry, src_entry, queue->entry_size); - - /* - * Make sure that the message data is visible before increasing the - * counter of read messages. - */ - __asm__ volatile("dmb st" ::: "memory"); - - queue->idx_read = (queue->idx_read + 1) % queue->entry_num; - - __asm__ volatile("dmb st" ::: "memory"); - - return 0; -} diff --git a/lib/sprt/sprt_queue.h b/lib/sprt/sprt_queue.h deleted file mode 100644 index 4ea1bc231..000000000 --- a/lib/sprt/sprt_queue.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPRT_QUEUE_H -#define SPRT_QUEUE_H - -#include - -/* Struct that defines a queue. Not to be used directly. */ -struct __attribute__((__packed__)) sprt_queue { - uint32_t entry_num; /* Number of entries */ - uint32_t entry_size; /* Size of an entry */ - uint32_t idx_write; /* Index of first empty entry */ - uint32_t idx_read; /* Index of first entry to read */ - uint8_t data[0]; /* Start of data */ -}; - -#define SPRT_QUEUE_HEADER_SIZE (sizeof(struct sprt_queue)) - -/* - * Initializes a memory region to be used as a queue of the given number of - * entries with the specified size. - */ -void sprt_queue_init(void *queue_base, uint32_t entry_num, uint32_t entry_size); - -/* Returns 1 if the queue is empty, 0 otherwise */ -int sprt_queue_is_empty(void *queue_base); - -/* Returns 1 if the queue is full, 0 otherwise */ -int sprt_queue_is_full(void *queue_base); - -/* - * Pushes a new entry intro the queue. Returns 0 on success, -ENOMEM if the - * queue is full. - */ -int sprt_queue_push(void *queue_base, const void *entry); - -/* - * Pops an entry from the queue. Returns 0 on success, -ENOENT if the queue is - * empty. - */ -int sprt_queue_pop(void *queue_base, void *entry); - -#endif /* SPRT_QUEUE_H */ diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index ac5d959ae..1e312362c 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -178,9 +178,6 @@ RECLAIM_INIT_CODE := 0 # SPD choice SPD := none -# Enable the SPCI-based Secure Partition Manager implementation -ENABLE_SPM := 0 - # Enable the Management Mode (MM)-based Secure Partition Manager implementation SPM_MM := 0 diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index fca4d0133..0b1b32102 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -99,9 +99,6 @@ const mmap_region_t plat_arm_mmap[] = { #if SPM_MM ARM_SP_IMAGE_MMAP, #endif -#if ENABLE_SPM - PLAT_MAP_SP_PACKAGE_MEM_RW, -#endif #if ARM_BL31_IN_DRAM ARM_MAP_BL31_SEC_DRAM, #endif @@ -129,9 +126,6 @@ const mmap_region_t plat_arm_mmap[] = { ARM_V2M_MAP_MEM_PROTECT, #if SPM_MM ARM_SPM_BUF_EL3_MMAP, -#endif -#if ENABLE_SPM - PLAT_MAP_SP_PACKAGE_MEM_RO, #endif {0} }; diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 1a251b828..fa855cf7f 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -61,7 +61,7 @@ * plat_arm_mmap array defined for each BL stage. */ #if defined(IMAGE_BL31) -# if ENABLE_SPM || SPM_MM +# if SPM_MM # define PLAT_ARM_MMAP_ENTRIES 9 # define MAX_XLAT_TABLES 9 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 @@ -116,11 +116,7 @@ * calculated using the current BL31 PROGBITS debug size plus the sizes of * BL2 and BL1-RW */ -#if ENABLE_SPM -#define PLAT_ARM_MAX_BL31_SIZE UL(0x60000) -#else #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) -#endif #ifndef __aarch64__ /* diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 446969c5b..55ad1c71d 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -281,9 +281,6 @@ else # if AArch64 ifeq (${RESET_TO_BL31},1) BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 endif - ifeq (${ENABLE_SPM},1) - BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 - endif ifeq (${SPD},trusty) BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 endif diff --git a/plat/arm/common/aarch64/arm_ehf.c b/plat/arm/common/aarch64/arm_ehf.c index 5144afc65..69ebd798f 100644 --- a/plat/arm/common/aarch64/arm_ehf.c +++ b/plat/arm/common/aarch64/arm_ehf.c @@ -24,7 +24,7 @@ ehf_pri_desc_t arm_exceptions[] = { /* Normal priority SDEI */ EHF_PRI_DESC(ARM_PRI_BITS, PLAT_SDEI_NORMAL_PRI), #endif -#if ENABLE_SPM || SPM_MM +#if SPM_MM EHF_PRI_DESC(ARM_PRI_BITS, PLAT_SP_PRI), #endif }; diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index a60e34957..9d4f05e9e 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -248,14 +248,6 @@ PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c \ lib/extensions/pauth/pauth_helpers.S endif -# SPM uses libfdt in Arm platforms -ifeq (${ENABLE_SPM},1) -BL31_SOURCES += common/fdt_wrappers.c \ - plat/common/plat_spm_rd.c \ - plat/common/plat_spm_sp.c \ - ${LIBFDT_SRCS} -endif - ifneq (${TRUSTED_BOARD_BOOT},0) # Include common TBB sources diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index a42c7599d..e21457304 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -28,7 +28,7 @@ * plat_arm_mmap array defined for each BL stage. */ #if defined(IMAGE_BL31) -# if ENABLE_SPM || SPM_MM +# if SPM_MM # define PLAT_ARM_MMAP_ENTRIES 9 # define MAX_XLAT_TABLES 7 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 @@ -101,7 +101,7 @@ #elif defined(IMAGE_BL2U) # define PLATFORM_STACK_SIZE 0x400 #elif defined(IMAGE_BL31) -# if ENABLE_SPM || SPM_MM +# if SPM_MM # define PLATFORM_STACK_SIZE 0x500 # else # define PLATFORM_STACK_SIZE 0x400 diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk index b736b0bb6..71601118f 100644 --- a/plat/arm/css/sgi/sgi-common.mk +++ b/plat/arm/css/sgi/sgi-common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -10,8 +10,6 @@ CSS_ENT_BASE := plat/arm/css/sgi RAS_EXTENSION := 0 -ENABLE_SPM := 0 - SDEI_SUPPORT := 0 EL3_EXCEPTION_HANDLING := 0 diff --git a/plat/common/plat_spm_rd.c b/plat/common/plat_spm_rd.c deleted file mode 100644 index ebd3e6dc6..000000000 --- a/plat/common/plat_spm_rd.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include - -#include -#include -#include -#include -#include - -/******************************************************************************* - * Resource pool - ******************************************************************************/ -static struct sp_rd_sect_mem_region rd_mem_regions[PLAT_SPM_MEM_REGIONS_MAX]; -static OBJECT_POOL_ARRAY(rd_mem_regions_pool, rd_mem_regions); - -static struct sp_rd_sect_notification rd_notifs[PLAT_SPM_NOTIFICATIONS_MAX]; -static OBJECT_POOL_ARRAY(rd_notifs_pool, rd_notifs); - -static struct sp_rd_sect_service rd_services[PLAT_SPM_SERVICES_MAX]; -static OBJECT_POOL_ARRAY(rd_services_pool, rd_services); - -/******************************************************************************* - * Attribute section handler - ******************************************************************************/ -static void rd_parse_attribute(struct sp_rd_sect_attribute *attr, - const void *fdt, int node) -{ - int rc = 0; - - /* The minimum size that can be read from the DTB is 32-bit. */ - uint32_t version, sp_type, runtime_el, exec_type; - uint32_t panic_policy, xlat_granule; - - rc |= fdtw_read_cells(fdt, node, "version", 1, &version); - - if (version != 1) { - ERROR("Unsupported resource description version: 0x%x\n", - version); - panic(); - } - - rc |= fdtw_read_cells(fdt, node, "sp_type", 1, &sp_type); - rc |= fdtw_read_cells(fdt, node, "pe_mpidr", 1, &attr->pe_mpidr); - rc |= fdtw_read_cells(fdt, node, "runtime_el", 1, &runtime_el); - rc |= fdtw_read_cells(fdt, node, "exec_type", 1, &exec_type); - rc |= fdtw_read_cells(fdt, node, "panic_policy", 1, &panic_policy); - rc |= fdtw_read_cells(fdt, node, "xlat_granule", 1, &xlat_granule); - rc |= fdtw_read_cells(fdt, node, "binary_size", 1, &attr->binary_size); - rc |= fdtw_read_cells(fdt, node, "load_address", 2, &attr->load_address); - rc |= fdtw_read_cells(fdt, node, "entrypoint", 2, &attr->entrypoint); - - attr->version = version; - attr->sp_type = sp_type; - attr->runtime_el = runtime_el; - attr->exec_type = exec_type; - attr->panic_policy = panic_policy; - attr->xlat_granule = xlat_granule; - - VERBOSE(" Attribute Section:\n"); - VERBOSE(" version: 0x%x\n", version); - VERBOSE(" sp_type: 0x%x\n", sp_type); - VERBOSE(" pe_mpidr: 0x%x\n", attr->pe_mpidr); - VERBOSE(" runtime_el: 0x%x\n", runtime_el); - VERBOSE(" exec_type: 0x%x\n", exec_type); - VERBOSE(" panic_policy: 0x%x\n", panic_policy); - VERBOSE(" xlat_granule: 0x%x\n", xlat_granule); - VERBOSE(" binary_size: 0x%x\n", attr->binary_size); - VERBOSE(" load_address: 0x%llx\n", attr->load_address); - VERBOSE(" entrypoint: 0x%llx\n", attr->entrypoint); - - if (rc) { - ERROR("Failed to read attribute node elements.\n"); - panic(); - } -} - -/******************************************************************************* - * Memory regions section handlers - ******************************************************************************/ -static void rd_parse_memory_region(struct sp_rd_sect_mem_region *rdmem, - const void *fdt, int node) -{ - int rc = 0; - char name[RD_MEM_REGION_NAME_LEN]; - - rc |= fdtw_read_string(fdt, node, "str", (char *)&name, sizeof(name)); - rc |= fdtw_read_cells(fdt, node, "attr", 1, &rdmem->attr); - rc |= fdtw_read_cells(fdt, node, "base", 2, &rdmem->base); - rc |= fdtw_read_cells(fdt, node, "size", 2, &rdmem->size); - - size_t len = strlcpy(rdmem->name, name, RD_MEM_REGION_NAME_LEN); - - if (len >= RD_MEM_REGION_NAME_LEN) { - WARN("Memory region name truncated: '%s'\n", name); - } - - VERBOSE(" Memory Region:\n"); - VERBOSE(" name: '%s'\n", rdmem->name); - VERBOSE(" attr: 0x%x\n", rdmem->attr); - VERBOSE(" base: 0x%llx\n", rdmem->base); - VERBOSE(" size: 0x%llx\n", rdmem->size); - - if (rc) { - ERROR("Failed to read mem_region node elements.\n"); - panic(); - } -} - -static void rd_parse_memory_regions(struct sp_res_desc *rd, const void *fdt, - int node) -{ - int child; - struct sp_rd_sect_mem_region *rdmem, *old_rdmem; - - fdt_for_each_subnode(child, fdt, node) { - rdmem = pool_alloc(&rd_mem_regions_pool); - - /* Add element to the start of the list */ - old_rdmem = rd->mem_region; - rd->mem_region = rdmem; - rdmem->next = old_rdmem; - - rd_parse_memory_region(rdmem, fdt, child); - } - - if ((child < 0) && (child != -FDT_ERR_NOTFOUND)) { - ERROR("%d: fdt_for_each_subnode(): %d\n", __LINE__, node); - panic(); - } -} - -/******************************************************************************* - * Notifications section handlers - ******************************************************************************/ -static void rd_parse_notification(struct sp_rd_sect_notification *rdnot, - const void *fdt, int node) -{ - int rc = 0; - - rc |= fdtw_read_cells(fdt, node, "attr", 1, &rdnot->attr); - rc |= fdtw_read_cells(fdt, node, "pe", 1, &rdnot->pe); - - VERBOSE(" Notification:\n"); - VERBOSE(" attr: 0x%x\n", rdnot->attr); - VERBOSE(" pe: 0x%x\n", rdnot->pe); - - if (rc) { - ERROR("Failed to read notification node elements.\n"); - panic(); - } -} - -static void rd_parse_notifications(struct sp_res_desc *rd, const void *fdt, int node) -{ - int child; - struct sp_rd_sect_notification *rdnot, *old_rdnot; - - fdt_for_each_subnode(child, fdt, node) { - rdnot = pool_alloc(&rd_notifs_pool); - - /* Add element to the start of the list */ - old_rdnot = rd->notification; - rd->notification = rdnot; - rdnot->next = old_rdnot; - - rd_parse_notification(rdnot, fdt, child); - } - - if ((child < 0) && (child != -FDT_ERR_NOTFOUND)) { - ERROR("%d: fdt_for_each_subnode(): %d\n", __LINE__, child); - panic(); - } -} - -/******************************************************************************* - * Services section handlers - ******************************************************************************/ -static void rd_parse_service(struct sp_rd_sect_service *rdsvc, const void *fdt, - int node) -{ - int rc = 0; - - /* The minimum size that can be read from the DTB is 32-bit. */ - uint32_t accessibility, request_type, connection_quota; - - rc |= fdtw_read_array(fdt, node, "uuid", 4, &rdsvc->uuid); - rc |= fdtw_read_cells(fdt, node, "accessibility", 1, &accessibility); - rc |= fdtw_read_cells(fdt, node, "request_type", 1, &request_type); - rc |= fdtw_read_cells(fdt, node, "connection_quota", 1, &connection_quota); - rc |= fdtw_read_cells(fdt, node, "sec_mem_size", 1, &rdsvc->secure_mem_size); - rc |= fdtw_read_cells(fdt, node, "interrupt_num", 1, &rdsvc->interrupt_num); - - rdsvc->accessibility = accessibility; - rdsvc->request_type = request_type; - rdsvc->connection_quota = connection_quota; - - VERBOSE(" Service:\n"); - VERBOSE(" uuid: 0x%08x 0x%08x 0x%08x 0x%08x\n", rdsvc->uuid[0], - rdsvc->uuid[1], rdsvc->uuid[2], rdsvc->uuid[3]); - VERBOSE(" accessibility: 0x%x\n", accessibility); - VERBOSE(" request_type: 0x%x\n", request_type); - VERBOSE(" connection_quota: 0x%x\n", connection_quota); - VERBOSE(" secure_memory_size: 0x%x\n", rdsvc->secure_mem_size); - VERBOSE(" interrupt_num: 0x%x\n", rdsvc->interrupt_num); - - if (rc) { - ERROR("Failed to read attribute node elements.\n"); - panic(); - } -} - -static void rd_parse_services(struct sp_res_desc *rd, const void *fdt, int node) -{ - int child; - struct sp_rd_sect_service *rdsvc, *old_rdsvc; - - fdt_for_each_subnode(child, fdt, node) { - rdsvc = pool_alloc(&rd_services_pool); - - /* Add element to the start of the list */ - old_rdsvc = rd->service; - rd->service = rdsvc; - rdsvc->next = old_rdsvc; - - rd_parse_service(rdsvc, fdt, child); - } - - if ((child < 0) && (child != -FDT_ERR_NOTFOUND)) { - ERROR("%d: fdt_for_each_subnode(): %d\n", __LINE__, node); - panic(); - } -} - -/******************************************************************************* - * Root node handler - ******************************************************************************/ -static void rd_parse_root(struct sp_res_desc *rd, const void *fdt, int root) -{ - int node; - char *str; - - str = "attribute"; - node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str)); - if (node < 0) { - ERROR("Root node doesn't contain subnode '%s'\n", str); - panic(); - } else { - rd_parse_attribute(&rd->attribute, fdt, node); - } - - str = "memory_regions"; - node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str)); - if (node < 0) { - ERROR("Root node doesn't contain subnode '%s'\n", str); - panic(); - } else { - rd_parse_memory_regions(rd, fdt, node); - } - - str = "notifications"; - node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str)); - if (node < 0) { - WARN("Root node doesn't contain subnode '%s'\n", str); - } else { - rd_parse_notifications(rd, fdt, node); - } - - str = "services"; - node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str)); - if (node < 0) { - WARN("Root node doesn't contain subnode '%s'\n", str); - } else { - rd_parse_services(rd, fdt, node); - } -} - -/******************************************************************************* - * Platform handler to load resource descriptor blobs into the active Secure - * Partition context. - ******************************************************************************/ -int plat_spm_sp_rd_load(struct sp_res_desc *rd, const void *ptr, size_t size) -{ - int rc; - int root_node; - - assert(rd != NULL); - assert(ptr != NULL); - - INFO("Reading RD blob at address %p\n", ptr); - - rc = fdt_check_header(ptr); - if (rc != 0) { - ERROR("Wrong format for resource descriptor blob (%d).\n", rc); - return -1; - } - - root_node = fdt_node_offset_by_compatible(ptr, -1, "arm,sp_rd"); - if (root_node < 0) { - ERROR("Unrecognized resource descriptor blob (%d)\n", rc); - return -1; - } - - rd_parse_root(rd, ptr, root_node); - - return 0; -} diff --git a/plat/common/plat_spm_sp.c b/plat/common/plat_spm_sp.c deleted file mode 100644 index bc3d6a015..000000000 --- a/plat/common/plat_spm_sp.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include - -static unsigned int sp_next; - -/******************************************************************************* - * Platform handler get the address of a Secure Partition and its resource - * description blob. It iterates through all SPs detected by the platform. If - * there is information for another SP, it returns 0. If there are no more SPs, - * it returns -1. - ******************************************************************************/ -int plat_spm_sp_get_next_address(void **sp_base, size_t *sp_size, - void **rd_base, size_t *rd_size) -{ - assert((sp_base != NULL) && (sp_size != NULL)); - assert((rd_base != NULL) && (rd_base != NULL)); - - const uint64_t *pkg_base = (uint64_t *)PLAT_SP_PACKAGE_BASE; - - struct sp_pkg_header *pkg_header = (struct sp_pkg_header *)pkg_base; - - if (sp_next == 0) { - if (pkg_header->version != 0x1) { - ERROR("SP package has an unsupported version 0x%llx\n", - pkg_header->version); - panic(); - } - } - - if (sp_next >= pkg_header->number_of_sp) { - /* No more partitions in the package */ - return -1; - } - - const struct sp_pkg_entry *entry_list = - (const struct sp_pkg_entry *)((uintptr_t)pkg_base - + sizeof(struct sp_pkg_header)); - - const struct sp_pkg_entry *entry = &(entry_list[sp_next]); - - uint64_t sp_offset = entry->sp_offset; - uint64_t rd_offset = entry->rd_offset; - - uintptr_t pkg_sp_base = ((uintptr_t)PLAT_SP_PACKAGE_BASE + sp_offset); - uintptr_t pkg_rd_base = ((uintptr_t)PLAT_SP_PACKAGE_BASE + rd_offset); - - uint64_t pkg_sp_size = entry->sp_size; - uint64_t pkg_rd_size = entry->rd_size; - - uintptr_t pkg_end = (uintptr_t)PLAT_SP_PACKAGE_BASE - + (uintptr_t)PLAT_SP_PACKAGE_SIZE - 1U; - - /* - * Check for overflows. The package header isn't trusted, so assert() - * can't be used here. - */ - - uintptr_t pkg_sp_end = pkg_sp_base + pkg_sp_size - 1U; - uintptr_t pkg_rd_end = pkg_rd_base + pkg_rd_size - 1U; - - if ((pkg_sp_end > pkg_end) || (pkg_sp_end < pkg_sp_base)) { - ERROR("Invalid Secure Partition size (0x%llx)\n", pkg_sp_size); - panic(); - } - - if ((pkg_rd_end > pkg_end) || (pkg_rd_end < pkg_rd_base)) { - ERROR("Invalid Resource Description blob size (0x%llx)\n", - pkg_rd_size); - panic(); - } - - /* Return location of the binaries. */ - - *sp_base = (void *)pkg_sp_base; - *sp_size = pkg_sp_size; - *rd_base = (void *)pkg_rd_base; - *rd_size = pkg_rd_size; - - sp_next++; - - return 0; -} diff --git a/plat/nvidia/tegra/scat/bl31.scat b/plat/nvidia/tegra/scat/bl31.scat index ff7719a2e..2d6d2b3d2 100644 --- a/plat/nvidia/tegra/scat/bl31.scat +++ b/plat/nvidia/tegra/scat/bl31.scat @@ -95,7 +95,7 @@ LR_RO_DATA +0 /* cpu_ops must always be defined */ ScatterAssert(ImageLength(__CPU_OPS__) > 0) -#if ENABLE_SPM || SPM_MM +#if SPM_MM LR_SPM +0 { /* diff --git a/services/std_svc/spm/README.rst b/services/std_svc/spm/README.rst deleted file mode 100644 index 63406a3bb..000000000 --- a/services/std_svc/spm/README.rst +++ /dev/null @@ -1,3 +0,0 @@ -This is a prototype loosely based on the SPCI Alpha and SPRT pre-alpha -specifications. Any interface / platform API introduced for this is subject to -change as it evolves. diff --git a/services/std_svc/spm/aarch64/spm_helpers.S b/services/std_svc/spm/aarch64/spm_helpers.S deleted file mode 100644 index aa35811f1..000000000 --- a/services/std_svc/spm/aarch64/spm_helpers.S +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "../spm_private.h" - - .global spm_secure_partition_enter - .global spm_secure_partition_exit - - /* --------------------------------------------------------------------- - * This function is called with SP_EL0 as stack. Here we stash our EL3 - * callee-saved registers on to the stack as a part of saving the C - * runtime and enter the secure payload. - * 'x0' contains a pointer to the memory where the address of the C - * runtime context is to be saved. - * --------------------------------------------------------------------- - */ -func spm_secure_partition_enter - /* Make space for the registers that we're going to save */ - mov x3, sp - str x3, [x0, #0] - sub sp, sp, #SP_C_RT_CTX_SIZE - - /* Save callee-saved registers on to the stack */ - stp x19, x20, [sp, #SP_C_RT_CTX_X19] - stp x21, x22, [sp, #SP_C_RT_CTX_X21] - stp x23, x24, [sp, #SP_C_RT_CTX_X23] - stp x25, x26, [sp, #SP_C_RT_CTX_X25] - stp x27, x28, [sp, #SP_C_RT_CTX_X27] - stp x29, x30, [sp, #SP_C_RT_CTX_X29] - - /* --------------------------------------------------------------------- - * Everything is setup now. el3_exit() will use the secure context to - * restore to the general purpose and EL3 system registers to ERET - * into the secure payload. - * --------------------------------------------------------------------- - */ - b el3_exit -endfunc spm_secure_partition_enter - - /* --------------------------------------------------------------------- - * This function is called with 'x0' pointing to a C runtime context - * saved in spm_secure_partition_enter(). - * It restores the saved registers and jumps to that runtime with 'x0' - * as the new SP register. This destroys the C runtime context that had - * been built on the stack below the saved context by the caller. Later - * the second parameter 'x1' is passed as a return value to the caller. - * --------------------------------------------------------------------- - */ -func spm_secure_partition_exit - /* Restore the previous stack */ - mov sp, x0 - - /* Restore callee-saved registers on to the stack */ - ldp x19, x20, [x0, #(SP_C_RT_CTX_X19 - SP_C_RT_CTX_SIZE)] - ldp x21, x22, [x0, #(SP_C_RT_CTX_X21 - SP_C_RT_CTX_SIZE)] - ldp x23, x24, [x0, #(SP_C_RT_CTX_X23 - SP_C_RT_CTX_SIZE)] - ldp x25, x26, [x0, #(SP_C_RT_CTX_X25 - SP_C_RT_CTX_SIZE)] - ldp x27, x28, [x0, #(SP_C_RT_CTX_X27 - SP_C_RT_CTX_SIZE)] - ldp x29, x30, [x0, #(SP_C_RT_CTX_X29 - SP_C_RT_CTX_SIZE)] - - /* --------------------------------------------------------------------- - * This should take us back to the instruction after the call to the - * last spm_secure_partition_enter().* Place the second parameter to x0 - * so that the caller will see it as a return value from the original - * entry call. - * --------------------------------------------------------------------- - */ - mov x0, x1 - ret -endfunc spm_secure_partition_exit diff --git a/services/std_svc/spm/aarch64/spm_shim_exceptions.S b/services/std_svc/spm/aarch64/spm_shim_exceptions.S deleted file mode 100644 index dab615012..000000000 --- a/services/std_svc/spm/aarch64/spm_shim_exceptions.S +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -/* ----------------------------------------------------------------------------- - * Very simple stackless exception handlers used by the spm shim layer. - * ----------------------------------------------------------------------------- - */ - .globl spm_shim_exceptions_ptr - -vector_base spm_shim_exceptions_ptr, .spm_shim_exceptions - - /* ----------------------------------------------------- - * Current EL with SP0 : 0x0 - 0x200 - * ----------------------------------------------------- - */ -vector_entry SynchronousExceptionSP0, .spm_shim_exceptions - b . -end_vector_entry SynchronousExceptionSP0 - -vector_entry IrqSP0, .spm_shim_exceptions - b . -end_vector_entry IrqSP0 - -vector_entry FiqSP0, .spm_shim_exceptions - b . -end_vector_entry FiqSP0 - -vector_entry SErrorSP0, .spm_shim_exceptions - b . -end_vector_entry SErrorSP0 - - /* ----------------------------------------------------- - * Current EL with SPx: 0x200 - 0x400 - * ----------------------------------------------------- - */ -vector_entry SynchronousExceptionSPx, .spm_shim_exceptions - b . -end_vector_entry SynchronousExceptionSPx - -vector_entry IrqSPx, .spm_shim_exceptions - b . -end_vector_entry IrqSPx - -vector_entry FiqSPx, .spm_shim_exceptions - b . -end_vector_entry FiqSPx - -vector_entry SErrorSPx, .spm_shim_exceptions - b . -end_vector_entry SErrorSPx - - /* ----------------------------------------------------- - * Lower EL using AArch64 : 0x400 - 0x600. No exceptions - * are handled since secure_partition does not implement - * a lower EL - * ----------------------------------------------------- - */ -vector_entry SynchronousExceptionA64, .spm_shim_exceptions - msr tpidr_el1, x30 - mrs x30, esr_el1 - ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH - - cmp x30, #EC_AARCH64_SVC - b.eq do_smc - - cmp x30, #EC_AARCH32_SVC - b.eq do_smc - - cmp x30, #EC_AARCH64_SYS - b.eq handle_sys_trap - - /* Fail in all the other cases */ - b panic - - /* --------------------------------------------- - * Tell SPM that we are done initialising - * --------------------------------------------- - */ -do_smc: - mrs x30, tpidr_el1 - smc #0 - eret - - /* AArch64 system instructions trap are handled as a panic for now */ -handle_sys_trap: -panic: - b panic -end_vector_entry SynchronousExceptionA64 - -vector_entry IrqA64, .spm_shim_exceptions - b . -end_vector_entry IrqA64 - -vector_entry FiqA64, .spm_shim_exceptions - b . -end_vector_entry FiqA64 - -vector_entry SErrorA64, .spm_shim_exceptions - b . -end_vector_entry SErrorA64 - - /* ----------------------------------------------------- - * Lower EL using AArch32 : 0x600 - 0x800 - * ----------------------------------------------------- - */ -vector_entry SynchronousExceptionA32, .spm_shim_exceptions - b . -end_vector_entry SynchronousExceptionA32 - -vector_entry IrqA32, .spm_shim_exceptions - b . -end_vector_entry IrqA32 - -vector_entry FiqA32, .spm_shim_exceptions - b . -end_vector_entry FiqA32 - -vector_entry SErrorA32, .spm_shim_exceptions - b . -end_vector_entry SErrorA32 diff --git a/services/std_svc/spm/spci.c b/services/std_svc/spm/spci.c deleted file mode 100644 index 2e12a6c6b..000000000 --- a/services/std_svc/spm/spci.c +++ /dev/null @@ -1,769 +0,0 @@ -/* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "spm_private.h" - -/******************************************************************************* - * Macros to print UUIDs. - ******************************************************************************/ -#define PRINT_UUID_FORMAT "%08x-%08x-%08x-%08x" -#define PRINT_UUID_ARGS(x) x[0], x[1], x[2], x[3] - -/******************************************************************************* - * Array of structs that contains information about all handles of Secure - * Services that are currently open. - ******************************************************************************/ -typedef enum spci_handle_status { - HANDLE_STATUS_CLOSED = 0, - HANDLE_STATUS_OPEN, -} spci_handle_status_t; - -typedef struct spci_handle { - /* 16-bit value used as reference in all SPCI calls */ - uint16_t handle; - - /* Client ID of the client that requested the handle */ - uint16_t client_id; - - /* Current status of the handle */ - spci_handle_status_t status; - - /* - * Context of the Secure Partition that provides the Secure Service - * referenced by this handle. - */ - sp_context_t *sp_ctx; - - /* - * The same handle might be used for multiple requests, keep a reference - * counter of them. - */ - unsigned int num_active_requests; -} spci_handle_t; - -static spci_handle_t spci_handles[PLAT_SPCI_HANDLES_MAX_NUM]; -static spinlock_t spci_handles_lock; - -/* - * Given a handle and a client ID, return the element of the spci_handles - * array that contains the information of the handle. It can only return open - * handles. It returns NULL if it couldn't find the element in the array. - */ -static spci_handle_t *spci_handle_info_get(uint16_t handle, uint16_t client_id) -{ - size_t i; - - for (i = 0; i < ARRAY_SIZE(spci_handles); i++) { - spci_handle_t *h = &(spci_handles[i]); - - /* Only check for open handles */ - if (h->status == HANDLE_STATUS_CLOSED) { - continue; - } - - /* Check if either the handle or the client ID are different */ - if ((h->handle != handle) || (h->client_id != client_id)) { - continue; - } - - return h; - } - - return NULL; -} - -/* - * Returns a unique value for a handle. This function must be called while - * spci_handles_lock is locked. It returns 0 on success, -1 on error. - */ -static int spci_create_handle_value(uint16_t *handle) -{ - /* - * Trivial implementation that relies on the fact that any handle will - * be closed before 2^16 more handles have been opened. - */ - static uint16_t handle_count; - - *handle = handle_count; - - handle_count++; - - return 0; -} - -/******************************************************************************* - * Returns a unique token for a Secure Service request. - ******************************************************************************/ -static uint32_t spci_create_token_value(void) -{ - /* - * Trivial implementation that relies on the fact that any response will - * be read before 2^32 more service requests have been done. - */ - static uint32_t token_count; - - return token_count++; -} - -/******************************************************************************* - * This function looks for a Secure Partition that has a Secure Service - * identified by the given UUID. It returns a handle that the client can use to - * access the service, and an SPCI_*** error code. - ******************************************************************************/ -static uint64_t spci_service_handle_open_poll(void *handle, u_register_t x1, - u_register_t x2, u_register_t x3, u_register_t x4, - u_register_t x5, u_register_t x6, u_register_t x7) -{ - unsigned int i; - sp_context_t *sp_ptr; - uint16_t service_handle; - - /* Bits 31:16 of w7 are reserved (MBZ). */ - assert((x7 & 0xFFFF0000U) == 0); - - uint16_t client_id = x7 & 0x0000FFFFU; - uint32_t uuid[4] = { x1, x2, x3, x4 }; - - /* Get pointer to the Secure Partition that handles this service */ - sp_ptr = spm_sp_get_by_uuid(&uuid); - if (sp_ptr == NULL) { - WARN("SPCI: Service requested by client 0x%04x not found\n", - client_id); - WARN("SPCI: UUID: " PRINT_UUID_FORMAT "\n", - PRINT_UUID_ARGS(uuid)); - - SMC_RET2(handle, SPCI_NOT_PRESENT, 0); - } - - /* Get lock of the array of handles */ - spin_lock(&spci_handles_lock); - - /* - * We need to record the client ID and Secure Partition that correspond - * to this handle. Look for the first free entry in the array. - */ - for (i = 0; i < PLAT_SPCI_HANDLES_MAX_NUM; i++) { - if (spci_handles[i].status == HANDLE_STATUS_CLOSED) { - break; - } - } - - if (i == PLAT_SPCI_HANDLES_MAX_NUM) { - spin_unlock(&spci_handles_lock); - - WARN("SPCI: Can't open more handles. Client 0x%04x\n", - client_id); - WARN("SPCI: UUID: " PRINT_UUID_FORMAT "\n", - PRINT_UUID_ARGS(uuid)); - - SMC_RET2(handle, SPCI_NO_MEMORY, 0); - } - - /* Create new handle value */ - if (spci_create_handle_value(&service_handle) != 0) { - spin_unlock(&spci_handles_lock); - - WARN("SPCI: Can't create a new handle value. Client 0x%04x\n", - client_id); - WARN("SPCI: UUID: " PRINT_UUID_FORMAT "\n", - PRINT_UUID_ARGS(uuid)); - - SMC_RET2(handle, SPCI_NO_MEMORY, 0); - } - - /* Save all information about this handle */ - spci_handles[i].status = HANDLE_STATUS_OPEN; - spci_handles[i].client_id = client_id; - spci_handles[i].handle = service_handle; - spci_handles[i].num_active_requests = 0U; - spci_handles[i].sp_ctx = sp_ptr; - - /* Release lock of the array of handles */ - spin_unlock(&spci_handles_lock); - - VERBOSE("SPCI: Service handle request by client 0x%04x: 0x%04x\n", - client_id, service_handle); - VERBOSE("SPCI: UUID: " PRINT_UUID_FORMAT "\n", PRINT_UUID_ARGS(uuid)); - - /* The handle is returned in the top 16 bits of x1 */ - SMC_RET2(handle, SPCI_SUCCESS, ((uint32_t)service_handle) << 16); -} - -/******************************************************************************* - * This function closes a handle that a specific client uses to access a Secure - * Service. It returns a SPCI_*** error code. - ******************************************************************************/ -static uint64_t spci_service_handle_close(void *handle, u_register_t x1) -{ - spci_handle_t *handle_info; - uint16_t client_id = x1 & 0x0000FFFFU; - uint16_t service_handle = (x1 >> 16) & 0x0000FFFFU; - - spin_lock(&spci_handles_lock); - - handle_info = spci_handle_info_get(service_handle, client_id); - - if (handle_info == NULL) { - spin_unlock(&spci_handles_lock); - - WARN("SPCI: Tried to close invalid handle 0x%04x by client 0x%04x\n", - service_handle, client_id); - - SMC_RET1(handle, SPCI_INVALID_PARAMETER); - } - - if (handle_info->status != HANDLE_STATUS_OPEN) { - spin_unlock(&spci_handles_lock); - - WARN("SPCI: Tried to close handle 0x%04x by client 0x%04x in status %d\n", - service_handle, client_id, handle_info->status); - - SMC_RET1(handle, SPCI_INVALID_PARAMETER); - } - - if (handle_info->num_active_requests != 0U) { - spin_unlock(&spci_handles_lock); - - /* A handle can't be closed if there are requests left */ - WARN("SPCI: Tried to close handle 0x%04x by client 0x%04x with %d requests left\n", - service_handle, client_id, - handle_info->num_active_requests); - - SMC_RET1(handle, SPCI_BUSY); - } - - memset(handle_info, 0, sizeof(spci_handle_t)); - - handle_info->status = HANDLE_STATUS_CLOSED; - - spin_unlock(&spci_handles_lock); - - VERBOSE("SPCI: Closed handle 0x%04x by client 0x%04x.\n", - service_handle, client_id); - - SMC_RET1(handle, SPCI_SUCCESS); -} - -/******************************************************************************* - * This function requests a Secure Service from a given handle and client ID. - ******************************************************************************/ -static uint64_t spci_service_request_blocking(void *handle, - uint32_t smc_fid, u_register_t x1, u_register_t x2, - u_register_t x3, u_register_t x4, u_register_t x5, - u_register_t x6, u_register_t x7) -{ - spci_handle_t *handle_info; - sp_context_t *sp_ctx; - cpu_context_t *cpu_ctx; - uint32_t rx0; - u_register_t rx1, rx2, rx3; - uint16_t request_handle, client_id; - - /* Get handle array lock */ - spin_lock(&spci_handles_lock); - - /* Get pointer to struct of this open handle and client ID. */ - request_handle = (x7 >> 16U) & 0x0000FFFFU; - client_id = x7 & 0x0000FFFFU; - - handle_info = spci_handle_info_get(request_handle, client_id); - if (handle_info == NULL) { - spin_unlock(&spci_handles_lock); - - WARN("SPCI_SERVICE_TUN_REQUEST_BLOCKING: Not found.\n"); - WARN(" Handle 0x%04x. Client ID 0x%04x\n", request_handle, - client_id); - - SMC_RET1(handle, SPCI_BUSY); - } - - /* Get pointer to the Secure Partition that handles the service */ - sp_ctx = handle_info->sp_ctx; - assert(sp_ctx != NULL); - cpu_ctx = &(sp_ctx->cpu_ctx); - - /* Blocking requests are only allowed if the queue is empty */ - if (handle_info->num_active_requests > 0) { - spin_unlock(&spci_handles_lock); - - SMC_RET1(handle, SPCI_BUSY); - } - - if (spm_sp_request_increase_if_zero(sp_ctx) == -1) { - spin_unlock(&spci_handles_lock); - - SMC_RET1(handle, SPCI_BUSY); - } - - /* Prevent this handle from being closed */ - handle_info->num_active_requests += 1; - - /* Release handle lock */ - spin_unlock(&spci_handles_lock); - - /* Save the Normal world context */ - cm_el1_sysregs_context_save(NON_SECURE); - - /* Wait until the Secure Partition is idle and set it to busy. */ - sp_state_wait_switch(sp_ctx, SP_STATE_IDLE, SP_STATE_BUSY); - - /* Pass arguments to the Secure Partition */ - struct sprt_queue_entry_message message = { - .type = SPRT_MSG_TYPE_SERVICE_TUN_REQUEST, - .client_id = client_id, - .service_handle = request_handle, - .session_id = x6, - .token = 0, /* No token needed for blocking requests */ - .args = {smc_fid, x1, x2, x3, x4, x5} - }; - - spin_lock(&(sp_ctx->spm_sp_buffer_lock)); - int rc = sprt_push_message((void *)sp_ctx->spm_sp_buffer_base, &message, - SPRT_QUEUE_NUM_BLOCKING); - spin_unlock(&(sp_ctx->spm_sp_buffer_lock)); - if (rc != 0) { - /* - * This shouldn't happen, blocking requests can only be made if - * the request queue is empty. - */ - assert(rc == -ENOMEM); - ERROR("SPCI_SERVICE_TUN_REQUEST_BLOCKING: Queue is full.\n"); - panic(); - } - - /* Jump to the Secure Partition. */ - rx0 = spm_sp_synchronous_entry(sp_ctx, 0); - - /* Verify returned value */ - if (rx0 != SPRT_PUT_RESPONSE_AARCH64) { - ERROR("SPM: %s: Unexpected x0 value 0x%x\n", __func__, rx0); - panic(); - } - - rx1 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X3); - rx2 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X4); - rx3 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X5); - - /* Flag Secure Partition as idle. */ - assert(sp_ctx->state == SP_STATE_BUSY); - sp_state_set(sp_ctx, SP_STATE_IDLE); - - /* Decrease count of requests. */ - spin_lock(&spci_handles_lock); - handle_info->num_active_requests -= 1; - spin_unlock(&spci_handles_lock); - spm_sp_request_decrease(sp_ctx); - - /* Restore non-secure state */ - cm_el1_sysregs_context_restore(NON_SECURE); - cm_set_next_eret_context(NON_SECURE); - - SMC_RET4(handle, SPCI_SUCCESS, rx1, rx2, rx3); -} - -/******************************************************************************* - * This function handles the returned values from the Secure Partition. - ******************************************************************************/ -static void spci_handle_returned_values(const cpu_context_t *cpu_ctx, - uint64_t ret) -{ - if (ret == SPRT_PUT_RESPONSE_AARCH64) { - uint32_t token; - uint64_t x3, x4, x5, x6; - - token = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X1); - x3 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X3); - x4 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X4); - x5 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X5); - x6 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X6); - - uint16_t client_id = x6 & 0xFFFFU; - uint16_t service_handle = x6 >> 16; - - int rc = spm_response_add(client_id, service_handle, token, - x3, x4, x5); - if (rc != 0) { - /* - * This is error fatal because we can't return to the SP - * from this SMC. The SP has crashed. - */ - panic(); - } - } else if ((ret != SPRT_YIELD_AARCH64) && - (ret != SPM_SECURE_PARTITION_PREEMPTED)) { - ERROR("SPM: %s: Unexpected x0 value 0x%llx\n", __func__, ret); - panic(); - } -} - -/******************************************************************************* - * This function requests a Secure Service from a given handle and client ID. - ******************************************************************************/ -static uint64_t spci_service_request_start(void *handle, - uint32_t smc_fid, u_register_t x1, u_register_t x2, - u_register_t x3, u_register_t x4, u_register_t x5, - u_register_t x6, u_register_t x7) -{ - spci_handle_t *handle_info; - sp_context_t *sp_ctx; - cpu_context_t *cpu_ctx; - uint16_t request_handle, client_id; - uint32_t token; - - /* Get handle array lock */ - spin_lock(&spci_handles_lock); - - /* Get pointer to struct of this open handle and client ID. */ - request_handle = (x7 >> 16U) & 0x0000FFFFU; - client_id = x7 & 0x0000FFFFU; - - handle_info = spci_handle_info_get(request_handle, client_id); - if (handle_info == NULL) { - spin_unlock(&spci_handles_lock); - - WARN("SPCI_SERVICE_TUN_REQUEST_START: Not found.\n" - " Handle 0x%04x. Client ID 0x%04x\n", request_handle, - client_id); - - SMC_RET1(handle, SPCI_INVALID_PARAMETER); - } - - /* Get pointer to the Secure Partition that handles the service */ - sp_ctx = handle_info->sp_ctx; - assert(sp_ctx != NULL); - cpu_ctx = &(sp_ctx->cpu_ctx); - - /* Prevent this handle from being closed */ - handle_info->num_active_requests += 1; - - spm_sp_request_increase(sp_ctx); - - /* Create new token for this request */ - token = spci_create_token_value(); - - /* Release handle lock */ - spin_unlock(&spci_handles_lock); - - /* Pass arguments to the Secure Partition */ - struct sprt_queue_entry_message message = { - .type = SPRT_MSG_TYPE_SERVICE_TUN_REQUEST, - .client_id = client_id, - .service_handle = request_handle, - .session_id = x6, - .token = token, - .args = {smc_fid, x1, x2, x3, x4, x5} - }; - - spin_lock(&(sp_ctx->spm_sp_buffer_lock)); - int rc = sprt_push_message((void *)sp_ctx->spm_sp_buffer_base, &message, - SPRT_QUEUE_NUM_NON_BLOCKING); - spin_unlock(&(sp_ctx->spm_sp_buffer_lock)); - if (rc != 0) { - WARN("SPCI_SERVICE_TUN_REQUEST_START: SPRT queue full.\n" - " Handle 0x%04x. Client ID 0x%04x\n", request_handle, - client_id); - SMC_RET1(handle, SPCI_NO_MEMORY); - } - - /* Try to enter the partition. If it's not possible, simply return. */ - if (sp_state_try_switch(sp_ctx, SP_STATE_IDLE, SP_STATE_BUSY) != 0) { - SMC_RET2(handle, SPCI_SUCCESS, token); - } - - /* Save the Normal world context */ - cm_el1_sysregs_context_save(NON_SECURE); - - /* - * This request is non-blocking and needs to be interruptible by - * non-secure interrupts. Enable their routing to EL3 during the - * processing of the Secure Partition's service on this core. - */ - - /* Jump to the Secure Partition. */ - uint64_t ret = spm_sp_synchronous_entry(sp_ctx, 1); - - /* Handle returned values */ - spci_handle_returned_values(cpu_ctx, ret); - - /* Flag Secure Partition as idle. */ - assert(sp_ctx->state == SP_STATE_BUSY); - sp_state_set(sp_ctx, SP_STATE_IDLE); - - /* Restore non-secure state */ - cm_el1_sysregs_context_restore(NON_SECURE); - cm_set_next_eret_context(NON_SECURE); - - SMC_RET2(handle, SPCI_SUCCESS, token); -} - -/******************************************************************************* - * This function returns the response of a Secure Service given a handle, a - * client ID and a token. If not available, it will schedule a Secure Partition - * and give it CPU time. - ******************************************************************************/ -static uint64_t spci_service_request_resume(void *handle, u_register_t x1, - u_register_t x7) -{ - int rc; - u_register_t rx1 = 0, rx2 = 0, rx3 = 0; - spci_handle_t *handle_info; - sp_context_t *sp_ctx; - cpu_context_t *cpu_ctx; - uint32_t token = (uint32_t) x1; - uint16_t client_id = x7 & 0x0000FFFF; - uint16_t service_handle = (x7 >> 16) & 0x0000FFFF; - - /* Get pointer to struct of this open handle and client ID. */ - spin_lock(&spci_handles_lock); - - handle_info = spci_handle_info_get(service_handle, client_id); - if (handle_info == NULL) { - spin_unlock(&spci_handles_lock); - WARN("SPCI_SERVICE_REQUEST_RESUME: Not found.\n" - "Handle 0x%04x. Client ID 0x%04x, Token 0x%08x.\n", - client_id, service_handle, token); - - SMC_RET1(handle, SPCI_INVALID_PARAMETER); - } - - /* Get pointer to the Secure Partition that handles the service */ - sp_ctx = handle_info->sp_ctx; - assert(sp_ctx != NULL); - cpu_ctx = &(sp_ctx->cpu_ctx); - - spin_unlock(&spci_handles_lock); - - /* Look for a valid response in the global queue */ - rc = spm_response_get(client_id, service_handle, token, - &rx1, &rx2, &rx3); - if (rc == 0) { - /* Decrease request count */ - spin_lock(&spci_handles_lock); - handle_info->num_active_requests -= 1; - spin_unlock(&spci_handles_lock); - spm_sp_request_decrease(sp_ctx); - - SMC_RET4(handle, SPCI_SUCCESS, rx1, rx2, rx3); - } - - /* Try to enter the partition. If it's not possible, simply return. */ - if (sp_state_try_switch(sp_ctx, SP_STATE_IDLE, SP_STATE_BUSY) != 0) { - SMC_RET1(handle, SPCI_QUEUED); - } - - /* Save the Normal world context */ - cm_el1_sysregs_context_save(NON_SECURE); - - /* - * This request is non-blocking and needs to be interruptible by - * non-secure interrupts. Enable their routing to EL3 during the - * processing of the Secure Partition's service on this core. - */ - - /* Jump to the Secure Partition. */ - uint64_t ret = spm_sp_synchronous_entry(sp_ctx, 1); - - /* Handle returned values */ - spci_handle_returned_values(cpu_ctx, ret); - - /* Flag Secure Partition as idle. */ - assert(sp_ctx->state == SP_STATE_BUSY); - sp_state_set(sp_ctx, SP_STATE_IDLE); - - /* Restore non-secure state */ - cm_el1_sysregs_context_restore(NON_SECURE); - cm_set_next_eret_context(NON_SECURE); - - /* Look for a valid response in the global queue */ - rc = spm_response_get(client_id, service_handle, token, - &rx1, &rx2, &rx3); - if (rc != 0) { - SMC_RET1(handle, SPCI_QUEUED); - } - - /* Decrease request count */ - spin_lock(&spci_handles_lock); - handle_info->num_active_requests -= 1; - spin_unlock(&spci_handles_lock); - spm_sp_request_decrease(sp_ctx); - - /* Return response */ - SMC_RET4(handle, SPCI_SUCCESS, rx1, rx2, rx3); -} - -/******************************************************************************* - * This function returns the response of a Secure Service given a handle, a - * client ID and a token. - ******************************************************************************/ -static uint64_t spci_service_get_response(void *handle, u_register_t x1, - u_register_t x7) - -{ - int rc; - u_register_t rx1 = 0, rx2 = 0, rx3 = 0; - spci_handle_t *handle_info; - uint32_t token = (uint32_t) x1; - uint16_t client_id = x7 & 0x0000FFFF; - uint16_t service_handle = (x7 >> 16) & 0x0000FFFF; - - /* Get pointer to struct of this open handle and client ID. */ - - spin_lock(&spci_handles_lock); - - handle_info = spci_handle_info_get(service_handle, client_id); - if (handle_info == NULL) { - spin_unlock(&spci_handles_lock); - WARN("SPCI_SERVICE_GET_RESPONSE: Not found.\n" - "Handle 0x%04x. Client ID 0x%04x, Token 0x%08x.\n", - client_id, service_handle, token); - - SMC_RET1(handle, SPCI_INVALID_PARAMETER); - } - - spin_unlock(&spci_handles_lock); - - /* Look for a valid response in the global queue */ - rc = spm_response_get(client_id, service_handle, token, - &rx1, &rx2, &rx3); - - if (rc != 0) { - SMC_RET1(handle, SPCI_QUEUED); - } - - /* Decrease request count */ - spin_lock(&spci_handles_lock); - handle_info->num_active_requests -= 1; - sp_context_t *sp_ctx; - sp_ctx = handle_info->sp_ctx; - spin_unlock(&spci_handles_lock); - spm_sp_request_decrease(sp_ctx); - - /* Return response */ - SMC_RET4(handle, SPCI_SUCCESS, rx1, rx2, rx3); -} - -/******************************************************************************* - * This function handles all SMCs in the range reserved for SPCI. - ******************************************************************************/ -static uintptr_t spci_smc_handler(uint32_t smc_fid, u_register_t x1, - u_register_t x2, u_register_t x3, - u_register_t x4, void *cookie, void *handle, - u_register_t flags) -{ - uint32_t spci_fid; - - /* SPCI only supported from the Non-secure world for now */ - if (is_caller_non_secure(flags) == SMC_FROM_SECURE) { - SMC_RET1(handle, SMC_UNK); - } - - if ((smc_fid & SPCI_FID_TUN_FLAG) == 0) { - - /* Miscellaneous calls */ - - spci_fid = (smc_fid >> SPCI_FID_MISC_SHIFT) & SPCI_FID_MISC_MASK; - - switch (spci_fid) { - - case SPCI_FID_VERSION: - SMC_RET1(handle, SPCI_VERSION_COMPILED); - - case SPCI_FID_SERVICE_HANDLE_OPEN: - { - if ((smc_fid & SPCI_SERVICE_HANDLE_OPEN_NOTIFY_BIT) != 0) { - /* Not supported for now */ - WARN("SPCI_SERVICE_HANDLE_OPEN_NOTIFY not supported.\n"); - SMC_RET1(handle, SPCI_INVALID_PARAMETER); - } - - uint64_t x5 = SMC_GET_GP(handle, CTX_GPREG_X5); - uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6); - uint64_t x7 = SMC_GET_GP(handle, CTX_GPREG_X7); - - return spci_service_handle_open_poll(handle, x1, x2, x3, - x4, x5, x6, x7); - } - case SPCI_FID_SERVICE_HANDLE_CLOSE: - return spci_service_handle_close(handle, x1); - - case SPCI_FID_SERVICE_REQUEST_BLOCKING: - { - uint64_t x5 = SMC_GET_GP(handle, CTX_GPREG_X5); - uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6); - uint64_t x7 = SMC_GET_GP(handle, CTX_GPREG_X7); - - return spci_service_request_blocking(handle, - smc_fid, x1, x2, x3, x4, x5, x6, x7); - } - - case SPCI_FID_SERVICE_REQUEST_START: - { - uint64_t x5 = SMC_GET_GP(handle, CTX_GPREG_X5); - uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6); - uint64_t x7 = SMC_GET_GP(handle, CTX_GPREG_X7); - - return spci_service_request_start(handle, - smc_fid, x1, x2, x3, x4, x5, x6, x7); - } - - case SPCI_FID_SERVICE_GET_RESPONSE: - { - uint64_t x7 = SMC_GET_GP(handle, CTX_GPREG_X7); - - return spci_service_get_response(handle, x1, x7); - } - - default: - break; - } - - } else { - - /* Tunneled calls */ - - spci_fid = (smc_fid >> SPCI_FID_TUN_SHIFT) & SPCI_FID_TUN_MASK; - - switch (spci_fid) { - - case SPCI_FID_SERVICE_REQUEST_RESUME: - { - uint64_t x7 = SMC_GET_GP(handle, CTX_GPREG_X7); - - return spci_service_request_resume(handle, x1, x7); - } - - default: - break; - } - } - - WARN("SPCI: Unsupported call 0x%08x\n", smc_fid); - SMC_RET1(handle, SPCI_NOT_SUPPORTED); -} - -DECLARE_RT_SVC( - spci_handler, - OEN_SPCI_START, - OEN_SPCI_END, - SMC_TYPE_FAST, - NULL, - spci_smc_handler -); diff --git a/services/std_svc/spm/spm.mk b/services/std_svc/spm/spm.mk deleted file mode 100644 index 448aba409..000000000 --- a/services/std_svc/spm/spm.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -ifneq (${SPD},none) - $(error "Error: SPD and SPM are incompatible build options.") -endif -ifneq (${ARCH},aarch64) - $(error "Error: SPM is only supported on aarch64.") -endif - -include lib/sprt/sprt_host.mk - -SPM_SOURCES := $(addprefix services/std_svc/spm/, \ - ${ARCH}/spm_helpers.S \ - ${ARCH}/spm_shim_exceptions.S \ - spci.c \ - spm_buffers.c \ - spm_main.c \ - spm_setup.c \ - spm_xlat.c \ - sprt.c) \ - ${SPRT_LIB_SOURCES} - -INCLUDES += ${SPRT_LIB_INCLUDES} - -# Let the top-level Makefile know that we intend to include a BL32 image -NEED_BL32 := yes diff --git a/services/std_svc/spm/spm_buffers.c b/services/std_svc/spm/spm_buffers.c deleted file mode 100644 index 79398ba15..000000000 --- a/services/std_svc/spm/spm_buffers.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -#include "./spm_private.h" - -/******************************************************************************* - * Secure Service response global array. All the responses to the requests done - * to the Secure Partition are stored here. They are removed from the array as - * soon as their value is read. - ******************************************************************************/ -struct sprt_response { - int is_valid; - uint32_t token; - uint16_t client_id, handle; - u_register_t x1, x2, x3; -}; - -static struct sprt_response responses[PLAT_SPM_RESPONSES_MAX]; - -static spinlock_t responses_lock; - -/* Add response to the global response buffer. Returns 0 on success else -1. */ -int spm_response_add(uint16_t client_id, uint16_t handle, uint32_t token, - u_register_t x1, u_register_t x2, u_register_t x3) -{ - spin_lock(&responses_lock); - - /* Make sure that there isn't any other response with the same token. */ - for (unsigned int i = 0U; i < ARRAY_SIZE(responses); i++) { - struct sprt_response *resp = &(responses[i]); - - if ((resp->is_valid == 1) && (resp->token == token)) { - spin_unlock(&responses_lock); - - return -1; - } - } - - for (unsigned int i = 0U; i < ARRAY_SIZE(responses); i++) { - struct sprt_response *resp = &(responses[i]); - - if (resp->is_valid == 0) { - resp->token = token; - resp->client_id = client_id; - resp->handle = handle; - resp->x1 = x1; - resp->x2 = x2; - resp->x3 = x3; - - dmbish(); - - resp->is_valid = 1; - - spin_unlock(&responses_lock); - - return 0; - } - } - - spin_unlock(&responses_lock); - - return -1; -} - -/* - * Returns a response from the requests array and removes it from it. Returns 0 - * on success, -1 if it wasn't found. - */ -int spm_response_get(uint16_t client_id, uint16_t handle, uint32_t token, - u_register_t *x1, u_register_t *x2, u_register_t *x3) -{ - spin_lock(&responses_lock); - - for (unsigned int i = 0U; i < ARRAY_SIZE(responses); i++) { - struct sprt_response *resp = &(responses[i]); - - /* Ignore invalid entries */ - if (resp->is_valid == 0) { - continue; - } - - /* Make sure that all the information matches the stored one */ - if ((resp->token != token) || (resp->client_id != client_id) || - (resp->handle != handle)) { - continue; - } - - *x1 = resp->x1; - *x2 = resp->x2; - *x3 = resp->x3; - - dmbish(); - - resp->is_valid = 0; - - spin_unlock(&responses_lock); - - return 0; - } - - spin_unlock(&responses_lock); - - return -1; -} diff --git a/services/std_svc/spm/spm_main.c b/services/std_svc/spm/spm_main.c deleted file mode 100644 index 3a63f1c69..000000000 --- a/services/std_svc/spm/spm_main.c +++ /dev/null @@ -1,359 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "spm_private.h" - -/******************************************************************************* - * Secure Partition context information. - ******************************************************************************/ -sp_context_t sp_ctx_array[PLAT_SPM_MAX_PARTITIONS]; - -/* Last Secure Partition last used by the CPU */ -sp_context_t *cpu_sp_ctx[PLATFORM_CORE_COUNT]; - -void spm_cpu_set_sp_ctx(unsigned int linear_id, sp_context_t *sp_ctx) -{ - assert(linear_id < PLATFORM_CORE_COUNT); - - cpu_sp_ctx[linear_id] = sp_ctx; -} - -sp_context_t *spm_cpu_get_sp_ctx(unsigned int linear_id) -{ - assert(linear_id < PLATFORM_CORE_COUNT); - - return cpu_sp_ctx[linear_id]; -} - -/******************************************************************************* - * Functions to keep track of how many requests a Secure Partition has received - * and hasn't finished. - ******************************************************************************/ -void spm_sp_request_increase(sp_context_t *sp_ctx) -{ - spin_lock(&(sp_ctx->request_count_lock)); - sp_ctx->request_count++; - spin_unlock(&(sp_ctx->request_count_lock)); -} - -void spm_sp_request_decrease(sp_context_t *sp_ctx) -{ - spin_lock(&(sp_ctx->request_count_lock)); - sp_ctx->request_count--; - spin_unlock(&(sp_ctx->request_count_lock)); -} - -/* Returns 0 if it was originally 0, -1 otherwise. */ -int spm_sp_request_increase_if_zero(sp_context_t *sp_ctx) -{ - int ret = -1; - - spin_lock(&(sp_ctx->request_count_lock)); - if (sp_ctx->request_count == 0U) { - sp_ctx->request_count++; - ret = 0U; - } - spin_unlock(&(sp_ctx->request_count_lock)); - - return ret; -} - -/******************************************************************************* - * This function returns a pointer to the context of the Secure Partition that - * handles the service specified by an UUID. It returns NULL if the UUID wasn't - * found. - ******************************************************************************/ -sp_context_t *spm_sp_get_by_uuid(const uint32_t (*svc_uuid)[4]) -{ - unsigned int i; - - for (i = 0U; i < PLAT_SPM_MAX_PARTITIONS; i++) { - - sp_context_t *sp_ctx = &sp_ctx_array[i]; - - if (sp_ctx->is_present == 0) { - continue; - } - - struct sp_rd_sect_service *rdsvc; - - for (rdsvc = sp_ctx->rd.service; rdsvc != NULL; - rdsvc = rdsvc->next) { - uint32_t *rd_uuid = (uint32_t *)(rdsvc->uuid); - - if (memcmp(rd_uuid, svc_uuid, sizeof(*svc_uuid)) == 0) { - return sp_ctx; - } - } - } - - return NULL; -} - -/******************************************************************************* - * Set state of a Secure Partition context. - ******************************************************************************/ -void sp_state_set(sp_context_t *sp_ptr, sp_state_t state) -{ - spin_lock(&(sp_ptr->state_lock)); - sp_ptr->state = state; - spin_unlock(&(sp_ptr->state_lock)); -} - -/******************************************************************************* - * Wait until the state of a Secure Partition is the specified one and change it - * to the desired state. - ******************************************************************************/ -void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to) -{ - int success = 0; - - while (success == 0) { - spin_lock(&(sp_ptr->state_lock)); - - if (sp_ptr->state == from) { - sp_ptr->state = to; - - success = 1; - } - - spin_unlock(&(sp_ptr->state_lock)); - } -} - -/******************************************************************************* - * Check if the state of a Secure Partition is the specified one and, if so, - * change it to the desired state. Returns 0 on success, -1 on error. - ******************************************************************************/ -int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to) -{ - int ret = -1; - - spin_lock(&(sp_ptr->state_lock)); - - if (sp_ptr->state == from) { - sp_ptr->state = to; - - ret = 0; - } - - spin_unlock(&(sp_ptr->state_lock)); - - return ret; -} - -/******************************************************************************* - * This function takes an SP context pointer and performs a synchronous entry - * into it. - ******************************************************************************/ -uint64_t spm_sp_synchronous_entry(sp_context_t *sp_ctx, int can_preempt) -{ - uint64_t rc; - unsigned int linear_id = plat_my_core_pos(); - - assert(sp_ctx != NULL); - - /* Assign the context of the SP to this CPU */ - spm_cpu_set_sp_ctx(linear_id, sp_ctx); - cm_set_context(&(sp_ctx->cpu_ctx), SECURE); - - /* Restore the context assigned above */ - cm_el1_sysregs_context_restore(SECURE); - cm_set_next_eret_context(SECURE); - - /* Invalidate TLBs at EL1. */ - tlbivmalle1(); - dsbish(); - - if (can_preempt == 1) { - enable_intr_rm_local(INTR_TYPE_NS, SECURE); - } else { - disable_intr_rm_local(INTR_TYPE_NS, SECURE); - } - - /* Enter Secure Partition */ - rc = spm_secure_partition_enter(&sp_ctx->c_rt_ctx); - - /* Save secure state */ - cm_el1_sysregs_context_save(SECURE); - - return rc; -} - -/******************************************************************************* - * This function returns to the place where spm_sp_synchronous_entry() was - * called originally. - ******************************************************************************/ -__dead2 void spm_sp_synchronous_exit(uint64_t rc) -{ - /* Get context of the SP in use by this CPU. */ - unsigned int linear_id = plat_my_core_pos(); - sp_context_t *ctx = spm_cpu_get_sp_ctx(linear_id); - - /* - * The SPM must have initiated the original request through a - * synchronous entry into the secure partition. Jump back to the - * original C runtime context with the value of rc in x0; - */ - spm_secure_partition_exit(ctx->c_rt_ctx, rc); - - panic(); -} - -/******************************************************************************* - * This function is the handler registered for Non secure interrupts by the SPM. - * It validates the interrupt and upon success arranges entry into the normal - * world for handling the interrupt. - ******************************************************************************/ -static uint64_t spm_ns_interrupt_handler(uint32_t id, uint32_t flags, - void *handle, void *cookie) -{ - /* Check the security state when the exception was generated */ - assert(get_interrupt_src_ss(flags) == SECURE); - - spm_sp_synchronous_exit(SPM_SECURE_PARTITION_PREEMPTED); -} - -/******************************************************************************* - * Jump to each Secure Partition for the first time. - ******************************************************************************/ -static int32_t spm_init(void) -{ - uint64_t rc = 0; - sp_context_t *ctx; - - for (unsigned int i = 0U; i < PLAT_SPM_MAX_PARTITIONS; i++) { - - ctx = &sp_ctx_array[i]; - - if (ctx->is_present == 0) { - continue; - } - - INFO("Secure Partition %u init...\n", i); - - ctx->state = SP_STATE_RESET; - - rc = spm_sp_synchronous_entry(ctx, 0); - if (rc != SPRT_YIELD_AARCH64) { - ERROR("Unexpected return value 0x%llx\n", rc); - panic(); - } - - ctx->state = SP_STATE_IDLE; - - INFO("Secure Partition %u initialized.\n", i); - } - - return rc; -} - -/******************************************************************************* - * Initialize contexts of all Secure Partitions. - ******************************************************************************/ -int32_t spm_setup(void) -{ - int rc; - sp_context_t *ctx; - void *sp_base, *rd_base; - size_t sp_size, rd_size; - uint64_t flags = 0U; - - /* Disable MMU at EL1 (initialized by BL2) */ - disable_mmu_icache_el1(); - - /* - * Non-blocking services can be interrupted by Non-secure interrupts. - * Register an interrupt handler for NS interrupts when generated while - * the CPU is in secure state. They are routed to EL3. - */ - set_interrupt_rm_flag(flags, SECURE); - - uint64_t rc_int = register_interrupt_type_handler(INTR_TYPE_NS, - spm_ns_interrupt_handler, flags); - if (rc_int) { - ERROR("SPM: Failed to register NS interrupt handler with rc = %llx\n", - rc_int); - panic(); - } - - /* Setup shim layer */ - spm_exceptions_xlat_init_context(); - - /* - * Setup all Secure Partitions. - */ - unsigned int i = 0U; - - while (1) { - rc = plat_spm_sp_get_next_address(&sp_base, &sp_size, - &rd_base, &rd_size); - if (rc < 0) { - /* Reached the end of the package. */ - break; - } - - if (i >= PLAT_SPM_MAX_PARTITIONS) { - ERROR("Too many partitions in the package.\n"); - panic(); - } - - ctx = &sp_ctx_array[i]; - - assert(ctx->is_present == 0); - - /* Initialize context of the SP */ - INFO("Secure Partition %u context setup start...\n", i); - - /* Save location of the image in physical memory */ - ctx->image_base = (uintptr_t)sp_base; - ctx->image_size = sp_size; - - rc = plat_spm_sp_rd_load(&ctx->rd, rd_base, rd_size); - if (rc < 0) { - ERROR("Error while loading RD blob.\n"); - panic(); - } - - spm_sp_setup(ctx); - - ctx->is_present = 1; - - INFO("Secure Partition %u setup done.\n", i); - - i++; - } - - if (i == 0U) { - ERROR("No present partitions in the package.\n"); - panic(); - } - - /* Register init function for deferred init. */ - bl31_register_bl32_init(&spm_init); - - return 0; -} diff --git a/services/std_svc/spm/spm_private.h b/services/std_svc/spm/spm_private.h deleted file mode 100644 index efc91cb41..000000000 --- a/services/std_svc/spm/spm_private.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_PRIVATE_H -#define SPM_PRIVATE_H - -#include - -/******************************************************************************* - * Constants that allow assembler code to preserve callee-saved registers of the - * C runtime context while performing a security state switch. - ******************************************************************************/ -#define SP_C_RT_CTX_X19 0x0 -#define SP_C_RT_CTX_X20 0x8 -#define SP_C_RT_CTX_X21 0x10 -#define SP_C_RT_CTX_X22 0x18 -#define SP_C_RT_CTX_X23 0x20 -#define SP_C_RT_CTX_X24 0x28 -#define SP_C_RT_CTX_X25 0x30 -#define SP_C_RT_CTX_X26 0x38 -#define SP_C_RT_CTX_X27 0x40 -#define SP_C_RT_CTX_X28 0x48 -#define SP_C_RT_CTX_X29 0x50 -#define SP_C_RT_CTX_X30 0x58 - -#define SP_C_RT_CTX_SIZE 0x60 -#define SP_C_RT_CTX_ENTRIES (SP_C_RT_CTX_SIZE >> DWORD_SHIFT) - -/* Value returned by spm_sp_synchronous_entry() when a partition is preempted */ -#define SPM_SECURE_PARTITION_PREEMPTED U(0x1234) - -#ifndef __ASSEMBLER__ - -#include - -#include -#include -#include - -typedef enum sp_state { - SP_STATE_RESET = 0, - SP_STATE_IDLE, - SP_STATE_BUSY -} sp_state_t; - -typedef struct sp_context { - /* 1 if the partition is present, 0 otherwise */ - int is_present; - - /* Location of the image in physical memory */ - unsigned long long image_base; - size_t image_size; - - uint64_t c_rt_ctx; - cpu_context_t cpu_ctx; - struct sp_res_desc rd; - - /* Translation tables context */ - xlat_ctx_t *xlat_ctx_handle; - spinlock_t xlat_ctx_lock; - - sp_state_t state; - spinlock_t state_lock; - - unsigned int request_count; - spinlock_t request_count_lock; - - /* Base and size of the shared SPM<->SP buffer */ - uintptr_t spm_sp_buffer_base; - size_t spm_sp_buffer_size; - spinlock_t spm_sp_buffer_lock; -} sp_context_t; - -/* Functions used to enter/exit a Secure Partition synchronously */ -uint64_t spm_sp_synchronous_entry(sp_context_t *sp_ctx, int can_preempt); -__dead2 void spm_sp_synchronous_exit(uint64_t rc); - -/* Assembly helpers */ -uint64_t spm_secure_partition_enter(uint64_t *c_rt_ctx); -void __dead2 spm_secure_partition_exit(uint64_t c_rt_ctx, uint64_t ret); - -/* Secure Partition setup */ -void spm_sp_setup(sp_context_t *sp_ctx); - -/* Secure Partition state management helpers */ -void sp_state_set(sp_context_t *sp_ptr, sp_state_t state); -void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to); -int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to); - -/* Functions to keep track of the number of active requests per SP */ -void spm_sp_request_increase(sp_context_t *sp_ctx); -void spm_sp_request_decrease(sp_context_t *sp_ctx); -int spm_sp_request_increase_if_zero(sp_context_t *sp_ctx); - -/* Functions related to the shim layer translation tables */ -void spm_exceptions_xlat_init_context(void); -uint64_t *spm_exceptions_xlat_get_base_table(void); - -/* Functions related to the translation tables management */ -void spm_sp_xlat_context_alloc(sp_context_t *sp_ctx); -void sp_map_memory_regions(sp_context_t *sp_ctx); - -/* Functions to handle Secure Partition contexts */ -void spm_cpu_set_sp_ctx(unsigned int linear_id, sp_context_t *sp_ctx); -sp_context_t *spm_cpu_get_sp_ctx(unsigned int linear_id); -sp_context_t *spm_sp_get_by_uuid(const uint32_t (*svc_uuid)[4]); - -/* Functions to manipulate response and requests buffers */ -int spm_response_add(uint16_t client_id, uint16_t handle, uint32_t token, - u_register_t x1, u_register_t x2, u_register_t x3); -int spm_response_get(uint16_t client_id, uint16_t handle, uint32_t token, - u_register_t *x1, u_register_t *x2, u_register_t *x3); - -#endif /* __ASSEMBLER__ */ - -#endif /* SPM_PRIVATE_H */ diff --git a/services/std_svc/spm/spm_setup.c b/services/std_svc/spm/spm_setup.c deleted file mode 100644 index 2ed44d134..000000000 --- a/services/std_svc/spm/spm_setup.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "spm_private.h" -#include "spm_shim_private.h" - -/* Setup context of the Secure Partition */ -void spm_sp_setup(sp_context_t *sp_ctx) -{ - cpu_context_t *ctx = &(sp_ctx->cpu_ctx); - - /* - * Initialize CPU context - * ---------------------- - */ - - entry_point_info_t ep_info = {0}; - - SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE); - - /* Setup entrypoint and SPSR */ - ep_info.pc = sp_ctx->rd.attribute.entrypoint; - ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS); - - /* - * X0: Unused (MBZ). - * X1: Unused (MBZ). - * X2: cookie value (Implementation Defined) - * X3: cookie value (Implementation Defined) - * X4 to X7 = 0 - */ - ep_info.args.arg0 = 0; - ep_info.args.arg1 = 0; - ep_info.args.arg2 = PLAT_SPM_COOKIE_0; - ep_info.args.arg3 = PLAT_SPM_COOKIE_1; - - cm_setup_context(ctx, &ep_info); - - /* - * Setup translation tables - * ------------------------ - */ - - /* Assign translation tables context. */ - spm_sp_xlat_context_alloc(sp_ctx); - - sp_map_memory_regions(sp_ctx); - - /* - * MMU-related registers - * --------------------- - */ - xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle; - - uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; - - setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table, - xlat_ctx->pa_max_address, xlat_ctx->va_max_address, - EL1_EL0_REGIME); - - write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, - mmu_cfg_params[MMU_CFG_MAIR]); - - /* Enable translations using TTBR1_EL1 */ - int t1sz = 64 - __builtin_ctzll(SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE); - mmu_cfg_params[MMU_CFG_TCR] &= ~TCR_EPD1_BIT; - mmu_cfg_params[MMU_CFG_TCR] |= - ((uint64_t)t1sz << TCR_T1SZ_SHIFT) | - TCR_SH1_INNER_SHAREABLE | - TCR_RGN1_OUTER_WBA | TCR_RGN1_INNER_WBA | - TCR_TG1_4K; - - write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, - mmu_cfg_params[MMU_CFG_TCR]); - - write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1, - mmu_cfg_params[MMU_CFG_TTBR0]); - - write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR1_EL1, - (uint64_t)spm_exceptions_xlat_get_base_table()); - - /* Setup SCTLR_EL1 */ - u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); - - sctlr_el1 |= - /*SCTLR_EL1_RES1 |*/ - /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */ - SCTLR_UCI_BIT | - /* RW regions at xlat regime EL1&0 are forced to be XN. */ - SCTLR_WXN_BIT | - /* Don't trap to EL1 execution of WFI or WFE at EL0. */ - SCTLR_NTWI_BIT | SCTLR_NTWE_BIT | - /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */ - SCTLR_UCT_BIT | - /* Don't trap to EL1 execution of DZ ZVA at EL0. */ - SCTLR_DZE_BIT | - /* Enable SP Alignment check for EL0 */ - SCTLR_SA0_BIT | - /* Allow cacheable data and instr. accesses to normal memory. */ - SCTLR_C_BIT | SCTLR_I_BIT | - /* Alignment fault checking enabled when at EL1 and EL0. */ - SCTLR_A_BIT | - /* Enable MMU. */ - SCTLR_M_BIT - ; - - sctlr_el1 &= ~( - /* Explicit data accesses at EL0 are little-endian. */ - SCTLR_E0E_BIT | - /* Accesses to DAIF from EL0 are trapped to EL1. */ - SCTLR_UMA_BIT - ); - - write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); - - /* - * Setup other system registers - * ---------------------------- - */ - - /* - * Shim exception vector base address. It is mapped at the start of the - * address space accessed by TTBR1_EL1, which means that the base - * address of the exception vectors depends on the size of the address - * space specified in TCR_EL1.T1SZ. - */ - write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1, - UINT64_MAX - (SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE - 1ULL)); - - /* - * FPEN: Allow the Secure Partition to access FP/SIMD registers. - * Note that SPM will not do any saving/restoring of these registers on - * behalf of the SP. This falls under the SP's responsibility. - * TTA: Enable access to trace registers. - * ZEN (v8.2): Trap SVE instructions and access to SVE registers. - */ - write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1, - CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE)); - - /* - * Prepare shared buffers - * ---------------------- - */ - - /* Initialize SPRT queues */ - sprt_initialize_queues((void *)sp_ctx->spm_sp_buffer_base, - sp_ctx->spm_sp_buffer_size); -} diff --git a/services/std_svc/spm/spm_shim_private.h b/services/std_svc/spm/spm_shim_private.h deleted file mode 100644 index fc510b111..000000000 --- a/services/std_svc/spm/spm_shim_private.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_SHIM_PRIVATE_H -#define SPM_SHIM_PRIVATE_H - -#include - -#include - -/* Assembly source */ -IMPORT_SYM(uintptr_t, spm_shim_exceptions_ptr, SPM_SHIM_EXCEPTIONS_PTR); - -/* Linker symbols */ -IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START); -IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END); - -/* Definitions */ - -#define SPM_SHIM_EXCEPTIONS_SIZE \ - (SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START) - -/* - * Use the smallest virtual address space size allowed in ARMv8.0 for - * compatibility. - */ -#define SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 25) -#define SPM_SHIM_MMAP_REGIONS 1 -#define SPM_SHIM_XLAT_TABLES 1 - -#endif /* SPM_SHIM_PRIVATE_H */ diff --git a/services/std_svc/spm/spm_xlat.c b/services/std_svc/spm/spm_xlat.c deleted file mode 100644 index 5d5bc519f..000000000 --- a/services/std_svc/spm/spm_xlat.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -#include "spm_private.h" -#include "spm_shim_private.h" - -/******************************************************************************* - * Instantiation of translation table context - ******************************************************************************/ - -/* Place translation tables by default along with the ones used by BL31. */ -#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME -#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table" -#endif - -/* - * Allocate elements of the translation contexts for the Secure Partitions. - */ - -/* Allocate an array of mmap_region per partition. */ -static struct mmap_region sp_mmap_regions[PLAT_SP_IMAGE_MMAP_REGIONS + 1] - [PLAT_SPM_MAX_PARTITIONS]; -static OBJECT_POOL(sp_mmap_regions_pool, sp_mmap_regions, - sizeof(mmap_region_t) * (PLAT_SP_IMAGE_MMAP_REGIONS + 1), - PLAT_SPM_MAX_PARTITIONS); - -/* Allocate individual translation tables. */ -static uint64_t sp_xlat_tables[XLAT_TABLE_ENTRIES] - [(PLAT_SP_IMAGE_MAX_XLAT_TABLES + 1) * PLAT_SPM_MAX_PARTITIONS] - __aligned(XLAT_TABLE_SIZE) __section(PLAT_SP_IMAGE_XLAT_SECTION_NAME); -static OBJECT_POOL(sp_xlat_tables_pool, sp_xlat_tables, - XLAT_TABLE_ENTRIES * sizeof(uint64_t), - (PLAT_SP_IMAGE_MAX_XLAT_TABLES + 1) * PLAT_SPM_MAX_PARTITIONS); - -/* Allocate arrays. */ -static int sp_xlat_mapped_regions[PLAT_SP_IMAGE_MAX_XLAT_TABLES] - [PLAT_SPM_MAX_PARTITIONS]; -static OBJECT_POOL(sp_xlat_mapped_regions_pool, sp_xlat_mapped_regions, - sizeof(int) * PLAT_SP_IMAGE_MAX_XLAT_TABLES, PLAT_SPM_MAX_PARTITIONS); - -/* Allocate individual contexts. */ -static xlat_ctx_t sp_xlat_ctx[PLAT_SPM_MAX_PARTITIONS]; -static OBJECT_POOL(sp_xlat_ctx_pool, sp_xlat_ctx, sizeof(xlat_ctx_t), - PLAT_SPM_MAX_PARTITIONS); - -/* Get handle of Secure Partition translation context */ -void spm_sp_xlat_context_alloc(sp_context_t *sp_ctx) -{ - /* Allocate xlat context elements */ - - xlat_ctx_t *ctx = pool_alloc(&sp_xlat_ctx_pool); - - struct mmap_region *mmap = pool_alloc(&sp_mmap_regions_pool); - - uint64_t *base_table = pool_alloc(&sp_xlat_tables_pool); - uint64_t **tables = pool_alloc_n(&sp_xlat_tables_pool, - PLAT_SP_IMAGE_MAX_XLAT_TABLES); - - int *mapped_regions = pool_alloc(&sp_xlat_mapped_regions_pool); - - /* Calculate the size of the virtual address space needed */ - - uintptr_t va_size = 0U; - struct sp_rd_sect_mem_region *rdmem; - - for (rdmem = sp_ctx->rd.mem_region; rdmem != NULL; rdmem = rdmem->next) { - uintptr_t end_va = (uintptr_t)rdmem->base + - (uintptr_t)rdmem->size; - - if (end_va > va_size) - va_size = end_va; - } - - if (va_size == 0U) { - ERROR("No regions in resource description.\n"); - panic(); - } - - /* - * Get the power of two that is greater or equal to the top VA. The - * values of base and size in the resource description are 32-bit wide - * so the values will never overflow when using a uintptr_t. - */ - if (!IS_POWER_OF_TWO(va_size)) { - va_size = 1ULL << - ((sizeof(va_size) * 8) - __builtin_clzll(va_size)); - } - - if (va_size > PLAT_VIRT_ADDR_SPACE_SIZE) { - ERROR("Resource description requested too much virtual memory.\n"); - panic(); - } - - uintptr_t min_va_size; - - /* The following sizes are only valid for 4KB pages */ - assert(PAGE_SIZE == (4U * 1024U)); - - if (is_armv8_4_ttst_present()) { - VERBOSE("Using ARMv8.4-TTST\n"); - min_va_size = 1ULL << (64 - TCR_TxSZ_MAX_TTST); - } else { - min_va_size = 1ULL << (64 - TCR_TxSZ_MAX); - } - - if (va_size < min_va_size) { - va_size = min_va_size; - } - - /* Initialize xlat context */ - - xlat_setup_dynamic_ctx(ctx, PLAT_PHY_ADDR_SPACE_SIZE - 1ULL, - va_size - 1ULL, mmap, - PLAT_SP_IMAGE_MMAP_REGIONS, tables, - PLAT_SP_IMAGE_MAX_XLAT_TABLES, base_table, - EL1_EL0_REGIME, mapped_regions); - - sp_ctx->xlat_ctx_handle = ctx; -}; - -/******************************************************************************* - * Translation table context used for S-EL1 exception vectors - ******************************************************************************/ - -REGISTER_XLAT_CONTEXT2(spm_sel1, SPM_SHIM_MMAP_REGIONS, SPM_SHIM_XLAT_TABLES, - SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE, - EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME); - -void spm_exceptions_xlat_init_context(void) -{ - /* This region contains the exception vectors used at S-EL1. */ - mmap_region_t sel1_exception_vectors = - MAP_REGION(SPM_SHIM_EXCEPTIONS_PTR, - 0x0UL, - SPM_SHIM_EXCEPTIONS_SIZE, - MT_CODE | MT_SECURE | MT_PRIVILEGED); - - mmap_add_region_ctx(&spm_sel1_xlat_ctx, - &sel1_exception_vectors); - - init_xlat_tables_ctx(&spm_sel1_xlat_ctx); -} - -uint64_t *spm_exceptions_xlat_get_base_table(void) -{ - return spm_sel1_xlat_ctx.base_table; -} - -/******************************************************************************* - * Functions to allocate memory for regions. - ******************************************************************************/ - -/* - * The region with base PLAT_SPM_HEAP_BASE and size PLAT_SPM_HEAP_SIZE is - * reserved for SPM to use as heap to allocate memory regions of Secure - * Partitions. This is only done at boot. - */ -static OBJECT_POOL(spm_heap_mem, (void *)PLAT_SPM_HEAP_BASE, 1U, - PLAT_SPM_HEAP_SIZE); - -static uintptr_t spm_alloc_heap(size_t size) -{ - return (uintptr_t)pool_alloc_n(&spm_heap_mem, size); -} - -/******************************************************************************* - * Functions to map memory regions described in the resource description. - ******************************************************************************/ -static unsigned int rdmem_attr_to_mmap_attr(uint32_t attr) -{ - unsigned int index = attr & RD_MEM_MASK; - - const unsigned int mmap_attr_arr[8] = { - MT_DEVICE | MT_RW | MT_SECURE, /* RD_MEM_DEVICE */ - MT_CODE | MT_SECURE, /* RD_MEM_NORMAL_CODE */ - MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_DATA */ - MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_BSS */ - MT_RO_DATA | MT_SECURE, /* RD_MEM_NORMAL_RODATA */ - MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_SPM_SP_SHARED_MEM */ - MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_CLIENT_SHARED_MEM */ - MT_MEMORY | MT_RW | MT_SECURE /* RD_MEM_NORMAL_MISCELLANEOUS */ - }; - - if (index >= ARRAY_SIZE(mmap_attr_arr)) { - ERROR("Unsupported RD memory attributes 0x%x\n", attr); - panic(); - } - - return mmap_attr_arr[index]; -} - -/* - * The data provided in the resource description structure is not directly - * compatible with a mmap_region structure. This function handles the conversion - * and maps it. - */ -static void map_rdmem(sp_context_t *sp_ctx, struct sp_rd_sect_mem_region *rdmem) -{ - int rc; - mmap_region_t mmap; - - /* Location of the SP image */ - uintptr_t sp_size = sp_ctx->image_size; - uintptr_t sp_base_va = sp_ctx->rd.attribute.load_address; - unsigned long long sp_base_pa = sp_ctx->image_base; - - /* Location of the memory region to map */ - size_t rd_size = rdmem->size; - uintptr_t rd_base_va = rdmem->base; - unsigned long long rd_base_pa; - - unsigned int memtype = rdmem->attr & RD_MEM_MASK; - - if (rd_size == 0U) { - VERBOSE("Memory region '%s' is empty. Ignored.\n", rdmem->name); - return; - } - - VERBOSE("Adding memory region '%s'\n", rdmem->name); - - mmap.granularity = REGION_DEFAULT_GRANULARITY; - - /* Check if the RD region is inside of the SP image or not */ - int is_outside = (rd_base_va + rd_size <= sp_base_va) || - (sp_base_va + sp_size <= rd_base_va); - - /* Set to 1 if it is needed to zero this region */ - int zero_region = 0; - - switch (memtype) { - case RD_MEM_DEVICE: - /* Device regions are mapped 1:1 */ - rd_base_pa = rd_base_va; - break; - - case RD_MEM_NORMAL_CODE: - case RD_MEM_NORMAL_RODATA: - { - if (is_outside == 1) { - ERROR("Code and rodata sections must be fully contained in the image."); - panic(); - } - - /* Get offset into the image */ - rd_base_pa = sp_base_pa + rd_base_va - sp_base_va; - break; - } - case RD_MEM_NORMAL_DATA: - { - if (is_outside == 1) { - ERROR("Data sections must be fully contained in the image."); - panic(); - } - - rd_base_pa = spm_alloc_heap(rd_size); - - /* Get offset into the image */ - void *img_pa = (void *)(sp_base_pa + rd_base_va - sp_base_va); - - VERBOSE(" Copying data from %p to 0x%llx\n", img_pa, rd_base_pa); - - /* Map destination */ - rc = mmap_add_dynamic_region(rd_base_pa, rd_base_pa, - rd_size, MT_MEMORY | MT_RW | MT_SECURE); - if (rc != 0) { - ERROR("Unable to map data region at EL3: %d\n", rc); - panic(); - } - - /* Copy original data to destination */ - memcpy((void *)rd_base_pa, img_pa, rd_size); - - /* Unmap destination region */ - rc = mmap_remove_dynamic_region(rd_base_pa, rd_size); - if (rc != 0) { - ERROR("Unable to remove data region at EL3: %d\n", rc); - panic(); - } - - break; - } - case RD_MEM_NORMAL_MISCELLANEOUS: - /* Allow SPM to change the attributes of the region. */ - mmap.granularity = PAGE_SIZE; - rd_base_pa = spm_alloc_heap(rd_size); - zero_region = 1; - break; - - case RD_MEM_NORMAL_SPM_SP_SHARED_MEM: - if ((sp_ctx->spm_sp_buffer_base != 0) || - (sp_ctx->spm_sp_buffer_size != 0)) { - ERROR("A partition must have only one SPM<->SP buffer.\n"); - panic(); - } - rd_base_pa = spm_alloc_heap(rd_size); - zero_region = 1; - /* Save location of this buffer, it is needed by SPM */ - sp_ctx->spm_sp_buffer_base = rd_base_pa; - sp_ctx->spm_sp_buffer_size = rd_size; - break; - - case RD_MEM_NORMAL_CLIENT_SHARED_MEM: - /* Fallthrough */ - case RD_MEM_NORMAL_BSS: - rd_base_pa = spm_alloc_heap(rd_size); - zero_region = 1; - break; - - default: - panic(); - } - - mmap.base_pa = rd_base_pa; - mmap.base_va = rd_base_va; - mmap.size = rd_size; - - /* Only S-EL0 mappings supported for now */ - mmap.attr = rdmem_attr_to_mmap_attr(rdmem->attr) | MT_USER; - - VERBOSE(" VA: 0x%lx PA: 0x%llx (0x%lx, attr: 0x%x)\n", - mmap.base_va, mmap.base_pa, mmap.size, mmap.attr); - - /* Map region in the context of the Secure Partition */ - mmap_add_region_ctx(sp_ctx->xlat_ctx_handle, &mmap); - - if (zero_region == 1) { - VERBOSE(" Zeroing region...\n"); - - rc = mmap_add_dynamic_region(mmap.base_pa, mmap.base_pa, - mmap.size, MT_MEMORY | MT_RW | MT_SECURE); - if (rc != 0) { - ERROR("Unable to map memory at EL3 to zero: %d\n", - rc); - panic(); - } - - zeromem((void *)mmap.base_pa, mmap.size); - - /* - * Unmap destination region unless it is the SPM<->SP buffer, - * which must be used by SPM. - */ - if (memtype != RD_MEM_NORMAL_SPM_SP_SHARED_MEM) { - rc = mmap_remove_dynamic_region(rd_base_pa, rd_size); - if (rc != 0) { - ERROR("Unable to remove region at EL3: %d\n", rc); - panic(); - } - } - } -} - -void sp_map_memory_regions(sp_context_t *sp_ctx) -{ - struct sp_rd_sect_mem_region *rdmem; - - for (rdmem = sp_ctx->rd.mem_region; rdmem != NULL; rdmem = rdmem->next) { - map_rdmem(sp_ctx, rdmem); - } - - init_xlat_tables_ctx(sp_ctx->xlat_ctx_handle); -} diff --git a/services/std_svc/spm/sprt.c b/services/std_svc/spm/sprt.c deleted file mode 100644 index 20ad2afb2..000000000 --- a/services/std_svc/spm/sprt.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "spm_private.h" - -/******************************************************************************* - * Functions to manipulate memory regions - ******************************************************************************/ - -/* - * Attributes are encoded using a different format in the SMC interface than in - * the Trusted Firmware, where the mmap_attr_t enum type is used. This function - * converts an attributes value from the SMC format to the mmap_attr_t format by - * setting MT_RW/MT_RO, MT_USER/MT_PRIVILEGED and MT_EXECUTE/MT_EXECUTE_NEVER. - * The other fields are left as 0 because they are ignored by the function - * xlat_change_mem_attributes_ctx(). - */ -static unsigned int smc_attr_to_mmap_attr(unsigned int attributes) -{ - unsigned int perm = attributes & SPRT_MEMORY_PERM_ATTR_MASK; - - if (perm == SPRT_MEMORY_PERM_ATTR_RW) { - return MT_RW | MT_EXECUTE_NEVER | MT_USER; - } else if (perm == SPRT_MEMORY_PERM_ATTR_RO) { - return MT_RO | MT_EXECUTE_NEVER | MT_USER; - } else if (perm == SPRT_MEMORY_PERM_ATTR_RO_EXEC) { - return MT_RO | MT_USER; - } else { - return UINT_MAX; - } -} - -/* - * This function converts attributes from the Trusted Firmware format into the - * SMC interface format. - */ -static unsigned int mmap_attr_to_smc_attr(unsigned int attr) -{ - unsigned int perm; - - /* No access from EL0. */ - if ((attr & MT_USER) == 0U) - return UINT_MAX; - - if ((attr & MT_RW) != 0) { - assert(MT_TYPE(attr) != MT_DEVICE); - perm = SPRT_MEMORY_PERM_ATTR_RW; - } else { - if ((attr & MT_EXECUTE_NEVER) != 0U) { - perm = SPRT_MEMORY_PERM_ATTR_RO; - } else { - perm = SPRT_MEMORY_PERM_ATTR_RO_EXEC; - } - } - - return perm << SPRT_MEMORY_PERM_ATTR_SHIFT; -} - -static int32_t sprt_memory_perm_attr_get(sp_context_t *sp_ctx, uintptr_t base_va) -{ - uint32_t attributes; - - spin_lock(&(sp_ctx->xlat_ctx_lock)); - - int ret = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle, - base_va, &attributes); - - spin_unlock(&(sp_ctx->xlat_ctx_lock)); - - /* Convert error codes of xlat_get_mem_attributes_ctx() into SPM. */ - assert((ret == 0) || (ret == -EINVAL)); - - if (ret != 0) - return SPRT_INVALID_PARAMETER; - - unsigned int perm = mmap_attr_to_smc_attr(attributes); - - if (perm == UINT_MAX) - return SPRT_INVALID_PARAMETER; - - return SPRT_SUCCESS | perm; -} - -static int32_t sprt_memory_perm_attr_set(sp_context_t *sp_ctx, - u_register_t page_address, u_register_t pages_count, - u_register_t smc_attributes) -{ - int ret; - uintptr_t base_va = (uintptr_t) page_address; - size_t size = pages_count * PAGE_SIZE; - - VERBOSE(" Start address : 0x%lx\n", base_va); - VERBOSE(" Number of pages: %i (%zi bytes)\n", (int) pages_count, size); - VERBOSE(" Attributes : 0x%lx\n", smc_attributes); - - uint32_t mmap_attr = smc_attr_to_mmap_attr(smc_attributes); - - if (mmap_attr == UINT_MAX) { - WARN("%s: Invalid memory attributes: 0x%lx\n", __func__, - smc_attributes); - return SPRT_INVALID_PARAMETER; - } - - /* - * Perform some checks before actually trying to change the memory - * attributes. - */ - - spin_lock(&(sp_ctx->xlat_ctx_lock)); - - uint32_t attributes; - - ret = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle, - base_va, &attributes); - - if (ret != 0) { - spin_unlock(&(sp_ctx->xlat_ctx_lock)); - return SPRT_INVALID_PARAMETER; - } - - if ((attributes & MT_USER) == 0U) { - /* Prohibit changing attributes of S-EL1 regions */ - spin_unlock(&(sp_ctx->xlat_ctx_lock)); - return SPRT_INVALID_PARAMETER; - } - - ret = xlat_change_mem_attributes_ctx(sp_ctx->xlat_ctx_handle, - base_va, size, mmap_attr); - - spin_unlock(&(sp_ctx->xlat_ctx_lock)); - - /* Convert error codes of xlat_change_mem_attributes_ctx() into SPM. */ - assert((ret == 0) || (ret == -EINVAL)); - - return (ret == 0) ? SPRT_SUCCESS : SPRT_INVALID_PARAMETER; -} - -/******************************************************************************* - * This function handles all SMCs in the range reserved for SPRT. - ******************************************************************************/ -static uintptr_t sprt_smc_handler(uint32_t smc_fid, u_register_t x1, - u_register_t x2, u_register_t x3, - u_register_t x4, void *cookie, void *handle, - u_register_t flags) -{ - /* SPRT only supported from the Secure world */ - if (is_caller_non_secure(flags) == SMC_FROM_NON_SECURE) { - SMC_RET1(handle, SMC_UNK); - } - - assert(handle == cm_get_context(SECURE)); - - /* - * Only S-EL0 partitions are supported for now. Make the next ERET into - * the partition jump directly to S-EL0 instead of S-EL1. - */ - cm_set_elr_spsr_el3(SECURE, read_elr_el1(), read_spsr_el1()); - - switch (smc_fid) { - case SPRT_VERSION: - SMC_RET1(handle, SPRT_VERSION_COMPILED); - - case SPRT_PUT_RESPONSE_AARCH64: - spm_sp_synchronous_exit(SPRT_PUT_RESPONSE_AARCH64); - - case SPRT_YIELD_AARCH64: - spm_sp_synchronous_exit(SPRT_YIELD_AARCH64); - - case SPRT_MEMORY_PERM_ATTR_GET_AARCH64: - { - /* Get context of the SP in use by this CPU. */ - unsigned int linear_id = plat_my_core_pos(); - sp_context_t *sp_ctx = spm_cpu_get_sp_ctx(linear_id); - - SMC_RET1(handle, sprt_memory_perm_attr_get(sp_ctx, x1)); - } - - case SPRT_MEMORY_PERM_ATTR_SET_AARCH64: - { - /* Get context of the SP in use by this CPU. */ - unsigned int linear_id = plat_my_core_pos(); - sp_context_t *sp_ctx = spm_cpu_get_sp_ctx(linear_id); - - SMC_RET1(handle, sprt_memory_perm_attr_set(sp_ctx, x1, x2, x3)); - } - - default: - break; - } - - WARN("SPRT: Unsupported call 0x%08x\n", smc_fid); - SMC_RET1(handle, SPRT_NOT_SUPPORTED); -} - -DECLARE_RT_SVC( - sprt_handler, - OEN_SPRT_START, - OEN_SPRT_END, - SMC_TYPE_FAST, - NULL, - sprt_smc_handler -); diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c index 1219b34c0..7a95c5b06 100644 --- a/services/std_svc/std_svc_setup.c +++ b/services/std_svc/std_svc_setup.c @@ -45,7 +45,7 @@ static int32_t std_svc_setup(void) ret = 1; } -#if ENABLE_SPM || SPM_MM +#if SPM_MM if (spm_setup() != 0) { ret = 1; } -- cgit v1.2.3 From aeaa225cbe24d63539261210e5aa901454de2a5b Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Tue, 15 Oct 2019 10:57:42 +0000 Subject: spm-mm: Refactor secure_partition.h and its contents Before adding any new SPM-related components we should first do some cleanup around the existing SPM-MM implementation. The aim is to make sure that any SPM-MM components have names that clearly indicate that they are MM-related. Otherwise, when adding new SPM code, it could quickly become confusing as it would be unclear to which component the code belongs. The secure_partition.h header is a clear example of this, as the name is generic so it could easily apply to any SPM-related code, when it is in fact SPM-MM specific. This patch renames the file and the two structures defined within it, and then modifies any references in files that use the header. Change-Id: I44bd95fab774c358178b3e81262a16da500fda26 Signed-off-by: Paul Beesley --- .../components/secure-partition-manager-design.rst | 2 +- include/plat/common/platform.h | 4 +- include/services/secure_partition.h | 54 ---------------------- include/services/spm_mm_partition.h | 50 ++++++++++++++++++++ plat/arm/board/fvp/fvp_common.c | 10 ++-- plat/arm/common/arm_common.c | 2 +- plat/arm/css/sgi/sgi_plat.c | 10 ++-- plat/socionext/synquacer/sq_spm.c | 12 ++--- services/std_svc/spm_mm/spm_main.c | 2 +- services/std_svc/spm_mm/spm_setup.c | 24 +++++----- services/std_svc/spm_mm/spm_xlat.c | 4 +- 11 files changed, 85 insertions(+), 89 deletions(-) delete mode 100644 include/services/secure_partition.h create mode 100644 include/services/spm_mm_partition.h diff --git a/docs/components/secure-partition-manager-design.rst b/docs/components/secure-partition-manager-design.rst index de0792d15..5c75bafdc 100644 --- a/docs/components/secure-partition-manager-design.rst +++ b/docs/components/secure-partition-manager-design.rst @@ -160,7 +160,7 @@ are implemented. Partition. - ``plat_get_secure_partition_boot_info()`` returns a - ``secure_partition_boot_info_t`` struct that is populated by the platform + ``spm_mm_boot_info_t`` struct that is populated by the platform with information about the memory map of the Secure Partition. For an example of all the changes in context, you may refer to commit diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index eeae62141..9efb2fd52 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -22,7 +22,7 @@ struct image_desc; struct bl_load_info; struct bl_params; struct mmap_region; -struct secure_partition_boot_info; +struct spm_mm_boot_info; struct sp_res_desc; /******************************************************************************* @@ -267,7 +267,7 @@ int get_mbedtls_heap_helper(void **heap_addr, size_t *heap_size); * Secure Partitions functions ******************************************************************************/ const struct mmap_region *plat_get_secure_partition_mmap(void *cookie); -const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( +const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( void *cookie); int plat_spm_sp_rd_load(struct sp_res_desc *rd, const void *ptr, size_t size); int plat_spm_sp_get_next_address(void **sp_base, size_t *sp_size, diff --git a/include/services/secure_partition.h b/include/services/secure_partition.h deleted file mode 100644 index 0510f80ec..000000000 --- a/include/services/secure_partition.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SECURE_PARTITION_H -#define SECURE_PARTITION_H - -#if SPM_MM - -#include - -#include - -/* - * Flags used by the secure_partition_mp_info structure to describe the - * characteristics of a cpu. Only a single flag is defined at the moment to - * indicate the primary cpu. - */ -#define MP_INFO_FLAG_PRIMARY_CPU U(0x00000001) - -/* - * This structure is used to provide information required to initialise a S-EL0 - * partition. - */ -typedef struct secure_partition_mp_info { - uint64_t mpidr; - uint32_t linear_id; - uint32_t flags; -} secure_partition_mp_info_t; - -typedef struct secure_partition_boot_info { - param_header_t h; - uint64_t sp_mem_base; - uint64_t sp_mem_limit; - uint64_t sp_image_base; - uint64_t sp_stack_base; - uint64_t sp_heap_base; - uint64_t sp_ns_comm_buf_base; - uint64_t sp_shared_buf_base; - uint64_t sp_image_size; - uint64_t sp_pcpu_stack_size; - uint64_t sp_heap_size; - uint64_t sp_ns_comm_buf_size; - uint64_t sp_shared_buf_size; - uint32_t num_sp_mem_regions; - uint32_t num_cpus; - secure_partition_mp_info_t *mp_info; -} secure_partition_boot_info_t; - -#endif /* SPM_MM */ - -#endif /* SECURE_PARTITION_H */ diff --git a/include/services/spm_mm_partition.h b/include/services/spm_mm_partition.h new file mode 100644 index 000000000..ad5ceefbb --- /dev/null +++ b/include/services/spm_mm_partition.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPM_MM_PARTITION_H +#define SPM_MM_PARTITION_H + +#include + +#include + +/* + * Flags used by the spm_mm_mp_info structure to describe the + * characteristics of a cpu. Only a single flag is defined at the moment to + * indicate the primary cpu. + */ +#define MP_INFO_FLAG_PRIMARY_CPU U(0x00000001) + +/* + * This structure is used to provide information required to initialise a S-EL0 + * partition. + */ +typedef struct spm_mm_mp_info { + uint64_t mpidr; + uint32_t linear_id; + uint32_t flags; +} spm_mm_mp_info_t; + +typedef struct spm_mm_boot_info { + param_header_t h; + uint64_t sp_mem_base; + uint64_t sp_mem_limit; + uint64_t sp_image_base; + uint64_t sp_stack_base; + uint64_t sp_heap_base; + uint64_t sp_ns_comm_buf_base; + uint64_t sp_shared_buf_base; + uint64_t sp_image_size; + uint64_t sp_pcpu_stack_size; + uint64_t sp_heap_size; + uint64_t sp_ns_comm_buf_size; + uint64_t sp_shared_buf_size; + uint32_t num_sp_mem_regions; + uint32_t num_cpus; + spm_mm_mp_info_t *mp_info; +} spm_mm_boot_info_t; + +#endif /* SPM_MM_PARTITION_H */ diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index 0b1b32102..c36cd6f17 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include "fvp_private.h" @@ -189,7 +189,7 @@ static unsigned int get_interconnect_master(void) * Boot information passed to a secure partition during initialisation. Linear * indices in MP information will be filled at runtime. */ -static secure_partition_mp_info_t sp_mp_info[] = { +static spm_mm_mp_info_t sp_mp_info[] = { [0] = {0x80000000, 0}, [1] = {0x80000001, 0}, [2] = {0x80000002, 0}, @@ -200,10 +200,10 @@ static secure_partition_mp_info_t sp_mp_info[] = { [7] = {0x80000103, 0}, }; -const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { +const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { .h.type = PARAM_SP_IMAGE_BOOT_INFO, .h.version = VERSION_1, - .h.size = sizeof(secure_partition_boot_info_t), + .h.size = sizeof(spm_mm_boot_info_t), .h.attr = 0, .sp_mem_base = ARM_SP_IMAGE_BASE, .sp_mem_limit = ARM_SP_IMAGE_LIMIT, @@ -227,7 +227,7 @@ const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) return plat_arm_secure_partition_mmap; } -const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( +const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( void *cookie) { return &plat_arm_secure_partition_boot_info; diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index bc0cf9a85..03d842a51 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include /* Weak definitions may be overridden in specific ARM standard platform */ #pragma weak plat_get_ns_image_entrypoint diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c index ef13cdcef..b611eaff5 100644 --- a/plat/arm/css/sgi/sgi_plat.c +++ b/plat/arm/css/sgi/sgi_plat.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ V2M_FLASH0_SIZE, \ @@ -87,7 +87,7 @@ ARM_CASSERT_MMAP * Boot information passed to a secure partition during initialisation. Linear * indices in MP information will be filled at runtime. */ -static secure_partition_mp_info_t sp_mp_info[] = { +static spm_mm_mp_info_t sp_mp_info[] = { [0] = {0x81000000, 0}, [1] = {0x81000100, 0}, [2] = {0x81000200, 0}, @@ -98,10 +98,10 @@ static secure_partition_mp_info_t sp_mp_info[] = { [7] = {0x81010300, 0}, }; -const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { +const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { .h.type = PARAM_SP_IMAGE_BOOT_INFO, .h.version = VERSION_1, - .h.size = sizeof(secure_partition_boot_info_t), + .h.size = sizeof(spm_mm_boot_info_t), .h.attr = 0, .sp_mem_base = ARM_SP_IMAGE_BASE, .sp_mem_limit = ARM_SP_IMAGE_LIMIT, @@ -125,7 +125,7 @@ const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) return plat_arm_secure_partition_mmap; } -const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( +const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( void *cookie) { return &plat_arm_secure_partition_boot_info; diff --git a/plat/socionext/synquacer/sq_spm.c b/plat/socionext/synquacer/sq_spm.c index 01cce1739..7bea1114e 100644 --- a/plat/socionext/synquacer/sq_spm.c +++ b/plat/socionext/synquacer/sq_spm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,7 @@ #include #include -#include +#include static const mmap_region_t plat_arm_secure_partition_mmap[] = { PLAT_SQ_FLASH_MMAP, @@ -27,7 +27,7 @@ static const mmap_region_t plat_arm_secure_partition_mmap[] = { * Boot information passed to a secure partition during initialisation. Linear * indices in MP information will be filled at runtime. */ -static secure_partition_mp_info_t sp_mp_info[] = { +static spm_mm_mp_info_t sp_mp_info[] = { {0x80000000, 0}, {0x80000001, 0}, {0x80000100, 0}, {0x80000101, 0}, {0x80000200, 0}, {0x80000201, 0}, {0x80000300, 0}, {0x80000301, 0}, {0x80000400, 0}, {0x80000401, 0}, {0x80000500, 0}, {0x80000501, 0}, @@ -36,10 +36,10 @@ static secure_partition_mp_info_t sp_mp_info[] = { {0x80000a00, 0}, {0x80000a01, 0}, {0x80000b00, 0}, {0x80000b01, 0}, }; -const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { +const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { .h.type = PARAM_SP_IMAGE_BOOT_INFO, .h.version = VERSION_1, - .h.size = sizeof(secure_partition_boot_info_t), + .h.size = sizeof(spm_mm_boot_info_t), .h.attr = 0, .sp_mem_base = BL32_BASE, .sp_mem_limit = BL32_LIMIT, @@ -63,7 +63,7 @@ const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) return plat_arm_secure_partition_mmap; } -const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( +const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( void *cookie) { return &plat_arm_secure_partition_boot_info; diff --git a/services/std_svc/spm_mm/spm_main.c b/services/std_svc/spm_mm/spm_main.c index 706b69d9f..b2f93a636 100644 --- a/services/std_svc/spm_mm/spm_main.c +++ b/services/std_svc/spm_mm/spm_main.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include diff --git a/services/std_svc/spm_mm/spm_setup.c b/services/std_svc/spm_mm/spm_setup.c index aae6cd5e2..7d03eb588 100644 --- a/services/std_svc/spm_mm/spm_setup.c +++ b/services/std_svc/spm_mm/spm_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include "spm_private.h" #include "spm_shim_private.h" @@ -192,22 +192,22 @@ void spm_sp_setup(sp_context_t *sp_ctx) void *shared_buf_ptr = (void *) PLAT_SPM_BUF_BASE; /* Copy the boot information into the shared buffer with the SP. */ - assert((uintptr_t)shared_buf_ptr + sizeof(secure_partition_boot_info_t) + assert((uintptr_t)shared_buf_ptr + sizeof(spm_mm_boot_info_t) <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)); assert(PLAT_SPM_BUF_BASE <= (UINTPTR_MAX - PLAT_SPM_BUF_SIZE + 1)); - const secure_partition_boot_info_t *sp_boot_info = + const spm_mm_boot_info_t *sp_boot_info = plat_get_secure_partition_boot_info(NULL); assert(sp_boot_info != NULL); memcpy((void *) shared_buf_ptr, (const void *) sp_boot_info, - sizeof(secure_partition_boot_info_t)); + sizeof(spm_mm_boot_info_t)); /* Pointer to the MP information from the platform port. */ - secure_partition_mp_info_t *sp_mp_info = - ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info; + spm_mm_mp_info_t *sp_mp_info = + ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info; assert(sp_mp_info != NULL); @@ -215,15 +215,15 @@ void spm_sp_setup(sp_context_t *sp_ctx) * Point the shared buffer MP information pointer to where the info will * be populated, just after the boot info. */ - ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info = - (secure_partition_mp_info_t *) ((uintptr_t)shared_buf_ptr - + sizeof(secure_partition_boot_info_t)); + ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info = + (spm_mm_mp_info_t *) ((uintptr_t)shared_buf_ptr + + sizeof(spm_mm_boot_info_t)); /* * Update the shared buffer pointer to where the MP information for the * payload will be populated */ - shared_buf_ptr = ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info; + shared_buf_ptr = ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info; /* * Copy the cpu information into the shared buffer area after the boot @@ -242,7 +242,7 @@ void spm_sp_setup(sp_context_t *sp_ctx) * Calculate the linear indices of cores in boot information for the * secure partition and flag the primary CPU */ - sp_mp_info = (secure_partition_mp_info_t *) shared_buf_ptr; + sp_mp_info = (spm_mm_mp_info_t *) shared_buf_ptr; for (unsigned int index = 0; index < sp_boot_info->num_cpus; index++) { u_register_t mpidr = sp_mp_info[index].mpidr; diff --git a/services/std_svc/spm_mm/spm_xlat.c b/services/std_svc/spm_mm/spm_xlat.c index f54168e33..a2df1afb0 100644 --- a/services/std_svc/spm_mm/spm_xlat.c +++ b/services/std_svc/spm_mm/spm_xlat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include "spm_private.h" -- cgit v1.2.3 From 0bf9f567a79033ff6db8c38111fc37fe07714896 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Tue, 15 Oct 2019 12:51:55 +0000 Subject: spm-mm: Refactor spm_svc.h and its contents Change-Id: I91c192924433226b54d33e57d56d146c1c6df81b Signed-off-by: Paul Beesley --- .../components/secure-partition-manager-design.rst | 41 +++++----- include/services/spm_mm_svc.h | 88 ++++++++++++++++++++++ include/services/spm_svc.h | 82 -------------------- plat/arm/css/sgi/sgi_ras.c | 10 +-- services/std_svc/spm_mm/spm_main.c | 44 +++++------ services/std_svc/spm_mm/spm_xlat.c | 30 ++++---- services/std_svc/std_svc_setup.c | 10 +-- 7 files changed, 156 insertions(+), 149 deletions(-) create mode 100644 include/services/spm_mm_svc.h delete mode 100644 include/services/spm_svc.h diff --git a/docs/components/secure-partition-manager-design.rst b/docs/components/secure-partition-manager-design.rst index 5c75bafdc..9aba95450 100644 --- a/docs/components/secure-partition-manager-design.rst +++ b/docs/components/secure-partition-manager-design.rst @@ -308,8 +308,8 @@ allows the Secure Partition to: Miscellaneous interfaces ------------------------ -``SPM_VERSION_AARCH32`` -^^^^^^^^^^^^^^^^^^^^^^^ +``SPM_MM_VERSION_AARCH32`` +^^^^^^^^^^^^^^^^^^^^^^^^^^ - Description @@ -369,7 +369,7 @@ Secure Partition Initialisation The SPM is responsible for initialising the architectural execution context to enable initialisation of a service in S-EL0. The responsibilities of the SPM are listed below. At the end of initialisation, the partition issues a -``SP_EVENT_COMPLETE_AARCH64`` call (described later) to signal readiness for +``MM_SP_EVENT_COMPLETE_AARCH64`` call (described later) to signal readiness for handling requests for services implemented by the Secure Partition. The initialisation event is executed as a Fast Call. @@ -488,12 +488,12 @@ Runtime Event Delegation The SPM receives requests for Secure Partition services through a synchronous invocation (i.e. a SMC from the Non-secure world). These requests are delegated to the partition by programming a return from the last -``SP_EVENT_COMPLETE_AARCH64`` call received from the partition. The last call +``MM_SP_EVENT_COMPLETE_AARCH64`` call received from the partition. The last call was made to signal either completion of Secure Partition initialisation or completion of a partition service request. -``SP_EVENT_COMPLETE_AARCH64`` -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +``MM_SP_EVENT_COMPLETE_AARCH64`` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - Description @@ -569,7 +569,7 @@ completion of a partition service request. - Caller responsibilities - A Secure Partition must only call ``SP_EVENT_COMPLETE_AARCH64`` to signal + A Secure Partition must only call ``MM_SP_EVENT_COMPLETE_AARCH64`` to signal completion of a request that was delegated to it by the SPM. - Callee responsibilities @@ -613,18 +613,19 @@ data and code) will be known only when the file is loaded into memory. In this case, the Secure Partition needs a way to change the access permissions of its memory regions. The SPM provides this feature through the -``SP_MEMORY_ATTRIBUTES_SET_AARCH64`` SVC interface. This interface is available -to the Secure Partition during a specific time window: from the first entry into -the Secure Partition up to the first ``SP_EVENT_COMPLETE`` call that signals the -Secure Partition has finished its initialisation. Once the initialisation is -complete, the SPM does not allow changes to the memory attributes. +``MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64`` SVC interface. This interface is +available to the Secure Partition during a specific time window: from the first +entry into the Secure Partition up to the first ``SP_EVENT_COMPLETE`` call that +signals the Secure Partition has finished its initialisation. Once the +initialisation is complete, the SPM does not allow changes to the memory +attributes. This section describes the standard SVC interface that is implemented by the SPM to determine and change permission attributes of memory regions that belong to a Secure Partition. -``SP_MEMORY_ATTRIBUTES_GET_AARCH64`` -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +``MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64`` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - Description @@ -673,7 +674,7 @@ Secure Partition. - ``NOT_SUPPORTED`` : The SPM does not support retrieval of attributes of any memory page that is accessible by the Secure Partition, or the function was called from the Non-secure world. Also returned if it is - used after ``SP_EVENT_COMPLETE_AARCH64``. + used after ``MM_SP_EVENT_COMPLETE_AARCH64``. See `Error Codes`_ for integer values that are associated with each return code. @@ -696,8 +697,8 @@ Secure Partition. The SPM must not return the memory access controls for a page of memory that is not accessible from a Secure Partition. -``SP_MEMORY_ATTRIBUTES_SET_AARCH64`` -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +``MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64`` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - Description @@ -762,7 +763,7 @@ Secure Partition. - ``NOT_SUPPORTED``: The SPM does not permit change of attributes of any memory region that is accessible by the Secure Partition. Function was called from the Non-secure world. Also returned if it is used after - ``SP_EVENT_COMPLETE_AARCH64``. + ``MM_SP_EVENT_COMPLETE_AARCH64``. See `Error Codes`_ for integer values that are associated with each return code. @@ -776,8 +777,8 @@ Secure Partition. currently supported. This function is only available at boot time. This interface is revoked after - the Secure Partition sends the first ``SP_EVENT_COMPLETE_AARCH64`` to signal - that it is initialised and ready to receive run-time requests. + the Secure Partition sends the first ``MM_SP_EVENT_COMPLETE_AARCH64`` to + signal that it is initialised and ready to receive run-time requests. - Caller responsibilities diff --git a/include/services/spm_mm_svc.h b/include/services/spm_mm_svc.h new file mode 100644 index 000000000..89fb2b45d --- /dev/null +++ b/include/services/spm_mm_svc.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPM_MM_SVC_H +#define SPM_MM_SVC_H + +#include + +#define SPM_MM_VERSION_MAJOR U(0) +#define SPM_MM_VERSION_MAJOR_SHIFT 16 +#define SPM_MM_VERSION_MAJOR_MASK U(0x7FFF) +#define SPM_MM_VERSION_MINOR U(1) +#define SPM_MM_VERSION_MINOR_SHIFT 0 +#define SPM_MM_VERSION_MINOR_MASK U(0xFFFF) +#define SPM_MM_VERSION_FORM(major, minor) ((major << \ + SPM_MM_VERSION_MAJOR_SHIFT) | \ + (minor)) +#define SPM_MM_VERSION_COMPILED SPM_MM_VERSION_FORM(SPM_MM_VERSION_MAJOR, \ + SPM_MM_VERSION_MINOR) + +/* These macros are used to identify SPM-MM calls using the SMC function ID */ +#define SPM_MM_FID_MASK U(0xffff) +#define SPM_MM_FID_MIN_VALUE U(0x40) +#define SPM_MM_FID_MAX_VALUE U(0x7f) +#define is_spm_mm_fid(_fid) \ + ((((_fid) & SPM_MM_FID_MASK) >= SPM_MM_FID_MIN_VALUE) && \ + (((_fid) & SPM_MM_FID_MASK) <= SPM_MM_FID_MAX_VALUE)) + +/* + * SMC IDs defined for accessing services implemented by the Secure Partition + * Manager from the Secure Partition(s). These services enable a partition to + * handle delegated events and request privileged operations from the manager. + * They occupy the range 0x60-0x7f. + */ +#define SPM_MM_VERSION_AARCH32 U(0x84000060) +#define MM_SP_EVENT_COMPLETE_AARCH64 U(0xC4000061) +#define MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 U(0xC4000064) +#define MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 U(0xC4000065) + +/* + * Macros used by MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64. + */ + +#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS U(0) +#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW U(1) +/* Value U(2) is reserved. */ +#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO U(3) +#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK U(3) +#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT 0 + +#define MM_SP_MEMORY_ATTRIBUTES_EXEC (U(0) << 2) +#define MM_SP_MEMORY_ATTRIBUTES_NON_EXEC (U(1) << 2) + + +/* SPM error codes. */ +#define SPM_MM_SUCCESS 0 +#define SPM_MM_NOT_SUPPORTED -1 +#define SPM_MM_INVALID_PARAMETER -2 +#define SPM_MM_DENIED -3 +#define SPM_MM_NO_MEMORY -5 + +#ifndef __ASSEMBLER__ + +#include + +int32_t spm_mm_setup(void); + +uint64_t spm_mm_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); + +/* Helper to enter a secure partition */ +uint64_t spm_mm_sp_call(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3); + +#endif /* __ASSEMBLER__ */ + +#endif /* SPM_MM_SVC_H */ diff --git a/include/services/spm_svc.h b/include/services/spm_svc.h deleted file mode 100644 index c8dbe5d55..000000000 --- a/include/services/spm_svc.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_SVC_H -#define SPM_SVC_H - -#include - -#define SPM_VERSION_MAJOR U(0) -#define SPM_VERSION_MAJOR_SHIFT 16 -#define SPM_VERSION_MAJOR_MASK U(0x7FFF) -#define SPM_VERSION_MINOR U(1) -#define SPM_VERSION_MINOR_SHIFT 0 -#define SPM_VERSION_MINOR_MASK U(0xFFFF) -#define SPM_VERSION_FORM(major, minor) ((major << SPM_VERSION_MAJOR_SHIFT) | (minor)) -#define SPM_VERSION_COMPILED SPM_VERSION_FORM(SPM_VERSION_MAJOR, SPM_VERSION_MINOR) - -/* The macros below are used to identify SPM calls from the SMC function ID */ -#define SPM_FID_MASK U(0xffff) -#define SPM_FID_MIN_VALUE U(0x40) -#define SPM_FID_MAX_VALUE U(0x7f) -#define is_spm_fid(_fid) \ - ((((_fid) & SPM_FID_MASK) >= SPM_FID_MIN_VALUE) && \ - (((_fid) & SPM_FID_MASK) <= SPM_FID_MAX_VALUE)) - -/* - * SMC IDs defined for accessing services implemented by the Secure Partition - * Manager from the Secure Partition(s). These services enable a partition to - * handle delegated events and request privileged operations from the manager. - * They occupy the range 0x60-0x7f. - */ -#define SPM_VERSION_AARCH32 U(0x84000060) -#define SP_EVENT_COMPLETE_AARCH64 U(0xC4000061) -#define SP_MEMORY_ATTRIBUTES_GET_AARCH64 U(0xC4000064) -#define SP_MEMORY_ATTRIBUTES_SET_AARCH64 U(0xC4000065) - -/* - * Macros used by SP_MEMORY_ATTRIBUTES_SET_AARCH64. - */ - -#define SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS U(0) -#define SP_MEMORY_ATTRIBUTES_ACCESS_RW U(1) -/* Value U(2) is reserved. */ -#define SP_MEMORY_ATTRIBUTES_ACCESS_RO U(3) -#define SP_MEMORY_ATTRIBUTES_ACCESS_MASK U(3) -#define SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT 0 - -#define SP_MEMORY_ATTRIBUTES_EXEC (U(0) << 2) -#define SP_MEMORY_ATTRIBUTES_NON_EXEC (U(1) << 2) - - -/* SPM error codes. */ -#define SPM_SUCCESS 0 -#define SPM_NOT_SUPPORTED -1 -#define SPM_INVALID_PARAMETER -2 -#define SPM_DENIED -3 -#define SPM_NO_MEMORY -5 - -#ifndef __ASSEMBLER__ - -#include - -int32_t spm_setup(void); - -uint64_t spm_smc_handler(uint32_t smc_fid, - uint64_t x1, - uint64_t x2, - uint64_t x3, - uint64_t x4, - void *cookie, - void *handle, - uint64_t flags); - -/* Helper to enter a Secure Partition */ -uint64_t spm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3); - -#endif /* __ASSEMBLER__ */ - -#endif /* SPM_SVC_H */ diff --git a/plat/arm/css/sgi/sgi_ras.c b/plat/arm/css/sgi/sgi_ras.c index 0001ffdde..de05a0737 100644 --- a/plat/arm/css/sgi/sgi_ras.c +++ b/plat/arm/css/sgi/sgi_ras.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include @@ -142,11 +142,11 @@ static int sgi_ras_intr_handler(const struct err_record_info *err_rec, sizeof(ras_map->ras_ev_num)); header->message_len = 4; - spm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0, - plat_my_core_pos()); + spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0, + plat_my_core_pos()); /* - * Do an EOI of the RAS interuupt. This allows the + * Do an EOI of the RAS interrupt. This allows the * sdei event to be dispatched at the SDEI event's * priority. */ diff --git a/services/std_svc/spm_mm/spm_main.c b/services/std_svc/spm_mm/spm_main.c index b2f93a636..ff0d0014d 100644 --- a/services/std_svc/spm_mm/spm_main.c +++ b/services/std_svc/spm_mm/spm_main.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include "spm_private.h" @@ -157,7 +157,7 @@ static int32_t spm_init(void) /******************************************************************************* * Initialize contexts of all Secure Partitions. ******************************************************************************/ -int32_t spm_setup(void) +int32_t spm_mm_setup(void) { sp_context_t *ctx; @@ -185,7 +185,7 @@ int32_t spm_setup(void) /******************************************************************************* * Function to perform a call to a Secure Partition. ******************************************************************************/ -uint64_t spm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3) +uint64_t spm_mm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3) { uint64_t rc; sp_context_t *sp_ptr = &sp_ctx; @@ -223,12 +223,12 @@ static uint64_t mm_communicate(uint32_t smc_fid, uint64_t mm_cookie, /* Cookie. Reserved for future use. It must be zero. */ if (mm_cookie != 0U) { ERROR("MM_COMMUNICATE: cookie is not zero\n"); - SMC_RET1(handle, SPM_INVALID_PARAMETER); + SMC_RET1(handle, SPM_MM_INVALID_PARAMETER); } if (comm_buffer_address == 0U) { ERROR("MM_COMMUNICATE: comm_buffer_address is zero\n"); - SMC_RET1(handle, SPM_INVALID_PARAMETER); + SMC_RET1(handle, SPM_MM_INVALID_PARAMETER); } if (comm_size_address != 0U) { @@ -251,8 +251,8 @@ static uint64_t mm_communicate(uint32_t smc_fid, uint64_t mm_cookie, /* Save the Normal world context */ cm_el1_sysregs_context_save(NON_SECURE); - rc = spm_sp_call(smc_fid, comm_buffer_address, comm_size_address, - plat_my_core_pos()); + rc = spm_mm_sp_call(smc_fid, comm_buffer_address, comm_size_address, + plat_my_core_pos()); /* Restore non-secure state */ cm_el1_sysregs_context_restore(NON_SECURE); @@ -270,7 +270,7 @@ static uint64_t mm_communicate(uint32_t smc_fid, uint64_t mm_cookie, /******************************************************************************* * Secure Partition Manager SMC handler. ******************************************************************************/ -uint64_t spm_smc_handler(uint32_t smc_fid, +uint64_t spm_mm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, @@ -295,29 +295,29 @@ uint64_t spm_smc_handler(uint32_t smc_fid, switch (smc_fid) { - case SPM_VERSION_AARCH32: - SMC_RET1(handle, SPM_VERSION_COMPILED); + case SPM_MM_VERSION_AARCH32: + SMC_RET1(handle, SPM_MM_VERSION_COMPILED); - case SP_EVENT_COMPLETE_AARCH64: + case MM_SP_EVENT_COMPLETE_AARCH64: spm_sp_synchronous_exit(x1); - case SP_MEMORY_ATTRIBUTES_GET_AARCH64: - INFO("Received SP_MEMORY_ATTRIBUTES_GET_AARCH64 SMC\n"); + case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64: + INFO("Received MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 SMC\n"); if (sp_ctx.state != SP_STATE_RESET) { - WARN("SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n"); - SMC_RET1(handle, SPM_NOT_SUPPORTED); + WARN("MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n"); + SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); } SMC_RET1(handle, spm_memory_attributes_get_smc_handler( &sp_ctx, x1)); - case SP_MEMORY_ATTRIBUTES_SET_AARCH64: - INFO("Received SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n"); + case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64: + INFO("Received MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n"); if (sp_ctx.state != SP_STATE_RESET) { - WARN("SP_MEMORY_ATTRIBUTES_SET_AARCH64 is available at boot time only\n"); - SMC_RET1(handle, SPM_NOT_SUPPORTED); + WARN("MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 is available at boot time only\n"); + SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); } SMC_RET1(handle, spm_memory_attributes_set_smc_handler( @@ -340,10 +340,10 @@ uint64_t spm_smc_handler(uint32_t smc_fid, case MM_COMMUNICATE_AARCH64: return mm_communicate(smc_fid, x1, x2, x3, handle); - case SP_MEMORY_ATTRIBUTES_GET_AARCH64: - case SP_MEMORY_ATTRIBUTES_SET_AARCH64: + case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64: + case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64: /* SMC interfaces reserved for secure callers. */ - SMC_RET1(handle, SPM_NOT_SUPPORTED); + SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); default: break; diff --git a/services/std_svc/spm_mm/spm_xlat.c b/services/std_svc/spm_mm/spm_xlat.c index a2df1afb0..0c2399c4f 100644 --- a/services/std_svc/spm_mm/spm_xlat.c +++ b/services/std_svc/spm_mm/spm_xlat.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include "spm_private.h" #include "spm_shim_private.h" @@ -50,21 +50,21 @@ static unsigned int smc_attr_to_mmap_attr(unsigned int attributes) { unsigned int tf_attr = 0U; - unsigned int access = (attributes & SP_MEMORY_ATTRIBUTES_ACCESS_MASK) - >> SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT; + unsigned int access = (attributes & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK) + >> MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT; - if (access == SP_MEMORY_ATTRIBUTES_ACCESS_RW) { + if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW) { tf_attr |= MT_RW | MT_USER; - } else if (access == SP_MEMORY_ATTRIBUTES_ACCESS_RO) { + } else if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO) { tf_attr |= MT_RO | MT_USER; } else { /* Other values are reserved. */ - assert(access == SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS); + assert(access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS); /* The only requirement is that there's no access from EL0 */ tf_attr |= MT_RO | MT_PRIVILEGED; } - if ((attributes & SP_MEMORY_ATTRIBUTES_NON_EXEC) == 0) { + if ((attributes & MM_SP_MEMORY_ATTRIBUTES_NON_EXEC) == 0) { tf_attr |= MT_EXECUTE; } else { tf_attr |= MT_EXECUTE_NEVER; @@ -85,21 +85,21 @@ static unsigned int smc_mmap_to_smc_attr(unsigned int attr) if ((attr & MT_USER) == 0) { /* No access from EL0. */ - data_access = SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS; + data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS; } else { if ((attr & MT_RW) != 0) { assert(MT_TYPE(attr) != MT_DEVICE); - data_access = SP_MEMORY_ATTRIBUTES_ACCESS_RW; + data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW; } else { - data_access = SP_MEMORY_ATTRIBUTES_ACCESS_RO; + data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO; } } - smc_attr |= (data_access & SP_MEMORY_ATTRIBUTES_ACCESS_MASK) - << SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT; + smc_attr |= (data_access & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK) + << MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT; if ((attr & MT_EXECUTE_NEVER) != 0U) { - smc_attr |= SP_MEMORY_ATTRIBUTES_NON_EXEC; + smc_attr |= MM_SP_MEMORY_ATTRIBUTES_NON_EXEC; } return smc_attr; @@ -123,7 +123,7 @@ int32_t spm_memory_attributes_get_smc_handler(sp_context_t *sp_ctx, if (rc == 0) { return (int32_t) smc_mmap_to_smc_attr(attributes); } else { - return SPM_INVALID_PARAMETER; + return SPM_MM_INVALID_PARAMETER; } } @@ -151,5 +151,5 @@ int spm_memory_attributes_set_smc_handler(sp_context_t *sp_ctx, /* Convert error codes of xlat_change_mem_attributes_ctx() into SPM. */ assert((ret == 0) || (ret == -EINVAL)); - return (ret == 0) ? SPM_SUCCESS : SPM_INVALID_PARAMETER; + return (ret == 0) ? SPM_MM_SUCCESS : SPM_MM_INVALID_PARAMETER; } diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c index 7a95c5b06..7787a2fa2 100644 --- a/services/std_svc/std_svc_setup.c +++ b/services/std_svc/std_svc_setup.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -46,7 +46,7 @@ static int32_t std_svc_setup(void) } #if SPM_MM - if (spm_setup() != 0) { + if (spm_mm_setup() != 0) { ret = 1; } #endif @@ -108,9 +108,9 @@ static uintptr_t std_svc_smc_handler(uint32_t smc_fid, * Dispatch SPM calls to SPM SMC handler and return its return * value */ - if (is_spm_fid(smc_fid)) { - return spm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, - handle, flags); + if (is_spm_mm_fid(smc_fid)) { + return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, + handle, flags); } #endif -- cgit v1.2.3 From 962c44e77cc14ca6a9d4316e53a72348f94d4657 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Tue, 15 Oct 2019 14:11:41 +0000 Subject: spm-mm: Remove mm_svc.h header The contents of this header have been merged into the spm_mm_svc.h header file. Change-Id: I01530b2e4ec1b4c091ce339758025e2216e740a4 Signed-off-by: Paul Beesley --- include/services/mm_svc.h | 35 ----------------------------------- include/services/spm_mm_svc.h | 26 ++++++++++++++++++++++++++ plat/arm/css/sgi/sgi_ras.c | 1 - services/std_svc/spm_mm/spm_main.c | 1 - 4 files changed, 26 insertions(+), 37 deletions(-) delete mode 100644 include/services/mm_svc.h diff --git a/include/services/mm_svc.h b/include/services/mm_svc.h deleted file mode 100644 index c11132696..000000000 --- a/include/services/mm_svc.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef MM_SVC_H -#define MM_SVC_H - -#if SPM_MM - -#include - -#define MM_VERSION_MAJOR U(1) -#define MM_VERSION_MAJOR_SHIFT 16 -#define MM_VERSION_MAJOR_MASK U(0x7FFF) -#define MM_VERSION_MINOR U(0) -#define MM_VERSION_MINOR_SHIFT 0 -#define MM_VERSION_MINOR_MASK U(0xFFFF) -#define MM_VERSION_FORM(major, minor) ((major << MM_VERSION_MAJOR_SHIFT) | (minor)) -#define MM_VERSION_COMPILED MM_VERSION_FORM(MM_VERSION_MAJOR, MM_VERSION_MINOR) - -/* - * SMC IDs defined in [1] for accessing MM services from the Non-secure world. - * These FIDs occupy the range 0x40 - 0x5f. - * [1] DEN0060A_ARM_MM_Interface_Specification.pdf - */ -#define MM_VERSION_AARCH32 U(0x84000040) - -#define MM_COMMUNICATE_AARCH64 U(0xC4000041) -#define MM_COMMUNICATE_AARCH32 U(0x84000041) - -#endif /* SPM_MM */ - -#endif /* MM_SVC_H */ diff --git a/include/services/spm_mm_svc.h b/include/services/spm_mm_svc.h index 89fb2b45d..3148beb80 100644 --- a/include/services/spm_mm_svc.h +++ b/include/services/spm_mm_svc.h @@ -9,6 +9,23 @@ #include +/* + * The MM_VERSION_XXX definitions are used when responding to the + * MM_VERSION_AARCH32 service request. The version returned is different between + * this request and the SPM_MM_VERSION_AARCH32 request - both have been retained + * for compatibility. + */ +#define MM_VERSION_MAJOR U(1) +#define MM_VERSION_MAJOR_SHIFT 16 +#define MM_VERSION_MAJOR_MASK U(0x7FFF) +#define MM_VERSION_MINOR U(0) +#define MM_VERSION_MINOR_SHIFT 0 +#define MM_VERSION_MINOR_MASK U(0xFFFF) +#define MM_VERSION_FORM(major, minor) ((major << MM_VERSION_MAJOR_SHIFT) | \ + (minor)) +#define MM_VERSION_COMPILED MM_VERSION_FORM(MM_VERSION_MAJOR, \ + MM_VERSION_MINOR) + #define SPM_MM_VERSION_MAJOR U(0) #define SPM_MM_VERSION_MAJOR_SHIFT 16 #define SPM_MM_VERSION_MAJOR_MASK U(0x7FFF) @@ -29,6 +46,15 @@ ((((_fid) & SPM_MM_FID_MASK) >= SPM_MM_FID_MIN_VALUE) && \ (((_fid) & SPM_MM_FID_MASK) <= SPM_MM_FID_MAX_VALUE)) +/* + * SMC IDs defined in [1] for accessing MM services from the Non-secure world. + * These FIDs occupy the range 0x40 - 0x5f. + * [1] DEN0060A_ARM_MM_Interface_Specification.pdf + */ +#define MM_VERSION_AARCH32 U(0x84000040) +#define MM_COMMUNICATE_AARCH64 U(0xC4000041) +#define MM_COMMUNICATE_AARCH32 U(0x84000041) + /* * SMC IDs defined for accessing services implemented by the Secure Partition * Manager from the Secure Partition(s). These services enable a partition to diff --git a/plat/arm/css/sgi/sgi_ras.c b/plat/arm/css/sgi/sgi_ras.c index de05a0737..f56544e72 100644 --- a/plat/arm/css/sgi/sgi_ras.c +++ b/plat/arm/css/sgi/sgi_ras.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/services/std_svc/spm_mm/spm_main.c b/services/std_svc/spm_mm/spm_main.c index ff0d0014d..433e3351f 100644 --- a/services/std_svc/spm_mm/spm_main.c +++ b/services/std_svc/spm_mm/spm_main.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include -- cgit v1.2.3 From 442e09284220b023ab79cce89058039751f42d5b Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Tue, 15 Oct 2019 14:20:34 +0000 Subject: spm-mm: Rename component makefile Change-Id: Idcd2a35cd2b30d77a7ca031f7e0172814bdb8cab Signed-off-by: Paul Beesley --- bl31/bl31.mk | 2 +- services/std_svc/spm_mm/spm.mk | 26 -------------------------- services/std_svc/spm_mm/spm_mm.mk | 26 ++++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 27 deletions(-) delete mode 100644 services/std_svc/spm_mm/spm.mk create mode 100644 services/std_svc/spm_mm/spm_mm.mk diff --git a/bl31/bl31.mk b/bl31/bl31.mk index 33d414dcd..7e1b51dc0 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -12,7 +12,7 @@ ifeq (${SPM_MM},1) $(error EL3_EXCEPTION_HANDLING must be 1 for SPM-MM support) else $(info Including SPM Management Mode (MM) makefile) - include services/std_svc/spm_mm/spm.mk + include services/std_svc/spm_mm/spm_mm.mk endif endif diff --git a/services/std_svc/spm_mm/spm.mk b/services/std_svc/spm_mm/spm.mk deleted file mode 100644 index 3aa10ee55..000000000 --- a/services/std_svc/spm_mm/spm.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -ifneq (${SPD},none) - $(error "Error: SPD and SPM are incompatible build options.") -endif -ifneq (${ARCH},aarch64) - $(error "Error: SPM is only supported on aarch64.") -endif - -SPM_SOURCES := $(addprefix services/std_svc/spm_mm/, \ - ${ARCH}/spm_helpers.S \ - ${ARCH}/spm_shim_exceptions.S \ - spm_main.c \ - spm_setup.c \ - spm_xlat.c) - - -# Let the top-level Makefile know that we intend to include a BL32 image -NEED_BL32 := yes - -# required so that SPM code executing at S-EL0 can access the timer registers -NS_TIMER_SWITCH := 1 diff --git a/services/std_svc/spm_mm/spm_mm.mk b/services/std_svc/spm_mm/spm_mm.mk new file mode 100644 index 000000000..4812e75fb --- /dev/null +++ b/services/std_svc/spm_mm/spm_mm.mk @@ -0,0 +1,26 @@ +# +# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +ifneq (${SPD},none) + $(error "Error: SPD and SPM_MM are incompatible build options.") +endif +ifneq (${ARCH},aarch64) + $(error "Error: SPM_MM is only supported on aarch64.") +endif + +SPM_SOURCES := $(addprefix services/std_svc/spm_mm/, \ + ${ARCH}/spm_helpers.S \ + ${ARCH}/spm_shim_exceptions.S \ + spm_main.c \ + spm_setup.c \ + spm_xlat.c) + + +# Let the top-level Makefile know that we intend to include a BL32 image +NEED_BL32 := yes + +# required so that SPM code executing at S-EL0 can access the timer registers +NS_TIMER_SWITCH := 1 -- cgit v1.2.3 From ff362d5fbdaa1869d6cdde34e8e1f01292ffea24 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Tue, 15 Oct 2019 14:23:23 +0000 Subject: spm-mm: Rename spm_private.h Change-Id: Ie47009158032c2e8f35febd7bf5458156f334ead Signed-off-by: Paul Beesley --- services/std_svc/spm_mm/aarch64/spm_helpers.S | 4 +- services/std_svc/spm_mm/spm_main.c | 2 +- services/std_svc/spm_mm/spm_mm_private.h | 71 +++++++++++++++++++++++++++ services/std_svc/spm_mm/spm_private.h | 71 --------------------------- services/std_svc/spm_mm/spm_setup.c | 2 +- services/std_svc/spm_mm/spm_xlat.c | 2 +- 6 files changed, 76 insertions(+), 76 deletions(-) create mode 100644 services/std_svc/spm_mm/spm_mm_private.h delete mode 100644 services/std_svc/spm_mm/spm_private.h diff --git a/services/std_svc/spm_mm/aarch64/spm_helpers.S b/services/std_svc/spm_mm/aarch64/spm_helpers.S index aa35811f1..2c3aaf7ae 100644 --- a/services/std_svc/spm_mm/aarch64/spm_helpers.S +++ b/services/std_svc/spm_mm/aarch64/spm_helpers.S @@ -1,11 +1,11 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include -#include "../spm_private.h" +#include "../spm_mm_private.h" .global spm_secure_partition_enter .global spm_secure_partition_exit diff --git a/services/std_svc/spm_mm/spm_main.c b/services/std_svc/spm_mm/spm_main.c index 433e3351f..14c0038ba 100644 --- a/services/std_svc/spm_mm/spm_main.c +++ b/services/std_svc/spm_mm/spm_main.c @@ -22,7 +22,7 @@ #include #include -#include "spm_private.h" +#include "spm_mm_private.h" /******************************************************************************* * Secure Partition context information. diff --git a/services/std_svc/spm_mm/spm_mm_private.h b/services/std_svc/spm_mm/spm_mm_private.h new file mode 100644 index 000000000..45b4789ad --- /dev/null +++ b/services/std_svc/spm_mm/spm_mm_private.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPM_MM_PRIVATE_H +#define SPM_MM_PRIVATE_H + +#include + +/******************************************************************************* + * Constants that allow assembler code to preserve callee-saved registers of the + * C runtime context while performing a security state switch. + ******************************************************************************/ +#define SP_C_RT_CTX_X19 0x0 +#define SP_C_RT_CTX_X20 0x8 +#define SP_C_RT_CTX_X21 0x10 +#define SP_C_RT_CTX_X22 0x18 +#define SP_C_RT_CTX_X23 0x20 +#define SP_C_RT_CTX_X24 0x28 +#define SP_C_RT_CTX_X25 0x30 +#define SP_C_RT_CTX_X26 0x38 +#define SP_C_RT_CTX_X27 0x40 +#define SP_C_RT_CTX_X28 0x48 +#define SP_C_RT_CTX_X29 0x50 +#define SP_C_RT_CTX_X30 0x58 + +#define SP_C_RT_CTX_SIZE 0x60 +#define SP_C_RT_CTX_ENTRIES (SP_C_RT_CTX_SIZE >> DWORD_SHIFT) + +#ifndef __ASSEMBLER__ + +#include + +#include +#include + +typedef enum sp_state { + SP_STATE_RESET = 0, + SP_STATE_IDLE, + SP_STATE_BUSY +} sp_state_t; + +typedef struct sp_context { + uint64_t c_rt_ctx; + cpu_context_t cpu_ctx; + xlat_ctx_t *xlat_ctx_handle; + + sp_state_t state; + spinlock_t state_lock; +} sp_context_t; + +/* Assembly helpers */ +uint64_t spm_secure_partition_enter(uint64_t *c_rt_ctx); +void __dead2 spm_secure_partition_exit(uint64_t c_rt_ctx, uint64_t ret); + +void spm_sp_setup(sp_context_t *sp_ctx); + +xlat_ctx_t *spm_get_sp_xlat_context(void); + +int32_t spm_memory_attributes_get_smc_handler(sp_context_t *sp_ctx, + uintptr_t base_va); +int spm_memory_attributes_set_smc_handler(sp_context_t *sp_ctx, + u_register_t page_address, + u_register_t pages_count, + u_register_t smc_attributes); + +#endif /* __ASSEMBLER__ */ + +#endif /* SPM_MM_PRIVATE_H */ diff --git a/services/std_svc/spm_mm/spm_private.h b/services/std_svc/spm_mm/spm_private.h deleted file mode 100644 index ba94a4d08..000000000 --- a/services/std_svc/spm_mm/spm_private.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_PRIVATE_H -#define SPM_PRIVATE_H - -#include - -/******************************************************************************* - * Constants that allow assembler code to preserve callee-saved registers of the - * C runtime context while performing a security state switch. - ******************************************************************************/ -#define SP_C_RT_CTX_X19 0x0 -#define SP_C_RT_CTX_X20 0x8 -#define SP_C_RT_CTX_X21 0x10 -#define SP_C_RT_CTX_X22 0x18 -#define SP_C_RT_CTX_X23 0x20 -#define SP_C_RT_CTX_X24 0x28 -#define SP_C_RT_CTX_X25 0x30 -#define SP_C_RT_CTX_X26 0x38 -#define SP_C_RT_CTX_X27 0x40 -#define SP_C_RT_CTX_X28 0x48 -#define SP_C_RT_CTX_X29 0x50 -#define SP_C_RT_CTX_X30 0x58 - -#define SP_C_RT_CTX_SIZE 0x60 -#define SP_C_RT_CTX_ENTRIES (SP_C_RT_CTX_SIZE >> DWORD_SHIFT) - -#ifndef __ASSEMBLER__ - -#include - -#include -#include - -typedef enum sp_state { - SP_STATE_RESET = 0, - SP_STATE_IDLE, - SP_STATE_BUSY -} sp_state_t; - -typedef struct sp_context { - uint64_t c_rt_ctx; - cpu_context_t cpu_ctx; - xlat_ctx_t *xlat_ctx_handle; - - sp_state_t state; - spinlock_t state_lock; -} sp_context_t; - -/* Assembly helpers */ -uint64_t spm_secure_partition_enter(uint64_t *c_rt_ctx); -void __dead2 spm_secure_partition_exit(uint64_t c_rt_ctx, uint64_t ret); - -void spm_sp_setup(sp_context_t *sp_ctx); - -xlat_ctx_t *spm_get_sp_xlat_context(void); - -int32_t spm_memory_attributes_get_smc_handler(sp_context_t *sp_ctx, - uintptr_t base_va); -int spm_memory_attributes_set_smc_handler(sp_context_t *sp_ctx, - u_register_t page_address, - u_register_t pages_count, - u_register_t smc_attributes); - -#endif /* __ASSEMBLER__ */ - -#endif /* SPM_PRIVATE_H */ diff --git a/services/std_svc/spm_mm/spm_setup.c b/services/std_svc/spm_mm/spm_setup.c index 7d03eb588..2ef35b75f 100644 --- a/services/std_svc/spm_mm/spm_setup.c +++ b/services/std_svc/spm_mm/spm_setup.c @@ -18,7 +18,7 @@ #include #include -#include "spm_private.h" +#include "spm_mm_private.h" #include "spm_shim_private.h" /* Setup context of the Secure Partition */ diff --git a/services/std_svc/spm_mm/spm_xlat.c b/services/std_svc/spm_mm/spm_xlat.c index 0c2399c4f..45fc704c3 100644 --- a/services/std_svc/spm_mm/spm_xlat.c +++ b/services/std_svc/spm_mm/spm_xlat.c @@ -14,7 +14,7 @@ #include #include -#include "spm_private.h" +#include "spm_mm_private.h" #include "spm_shim_private.h" /* Place translation tables by default along with the ones used by BL31. */ -- cgit v1.2.3 From 6b54236ea2564eae7f9610153b6ef747a909bb67 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Tue, 15 Oct 2019 16:11:46 +0000 Subject: spm-mm: Rename spm_shim_private.h Change-Id: I575188885ebed8c5f0682ac6e0e7dd159155727f Signed-off-by: Paul Beesley --- services/std_svc/spm_mm/spm_mm_shim_private.h | 26 ++++++++++++++++++++++++++ services/std_svc/spm_mm/spm_setup.c | 2 +- services/std_svc/spm_mm/spm_shim_private.h | 26 -------------------------- services/std_svc/spm_mm/spm_xlat.c | 2 +- 4 files changed, 28 insertions(+), 28 deletions(-) create mode 100644 services/std_svc/spm_mm/spm_mm_shim_private.h delete mode 100644 services/std_svc/spm_mm/spm_shim_private.h diff --git a/services/std_svc/spm_mm/spm_mm_shim_private.h b/services/std_svc/spm_mm/spm_mm_shim_private.h new file mode 100644 index 000000000..0c8d894f1 --- /dev/null +++ b/services/std_svc/spm_mm/spm_mm_shim_private.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPM_MM_SHIM_PRIVATE_H +#define SPM_MM_SHIM_PRIVATE_H + +#include + +#include + +/* Assembly source */ +IMPORT_SYM(uintptr_t, spm_shim_exceptions_ptr, SPM_SHIM_EXCEPTIONS_PTR); + +/* Linker symbols */ +IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START); +IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END); + +/* Definitions */ + +#define SPM_SHIM_EXCEPTIONS_SIZE \ + (SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START) + +#endif /* SPM_MM_SHIM_PRIVATE_H */ diff --git a/services/std_svc/spm_mm/spm_setup.c b/services/std_svc/spm_mm/spm_setup.c index 2ef35b75f..ccb2f9058 100644 --- a/services/std_svc/spm_mm/spm_setup.c +++ b/services/std_svc/spm_mm/spm_setup.c @@ -19,7 +19,7 @@ #include #include "spm_mm_private.h" -#include "spm_shim_private.h" +#include "spm_mm_shim_private.h" /* Setup context of the Secure Partition */ void spm_sp_setup(sp_context_t *sp_ctx) diff --git a/services/std_svc/spm_mm/spm_shim_private.h b/services/std_svc/spm_mm/spm_shim_private.h deleted file mode 100644 index 7fe9692b4..000000000 --- a/services/std_svc/spm_mm/spm_shim_private.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPM_SHIM_PRIVATE_H -#define SPM_SHIM_PRIVATE_H - -#include - -#include - -/* Assembly source */ -IMPORT_SYM(uintptr_t, spm_shim_exceptions_ptr, SPM_SHIM_EXCEPTIONS_PTR); - -/* Linker symbols */ -IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START); -IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END); - -/* Definitions */ - -#define SPM_SHIM_EXCEPTIONS_SIZE \ - (SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START) - -#endif /* SPM_SHIM_PRIVATE_H */ diff --git a/services/std_svc/spm_mm/spm_xlat.c b/services/std_svc/spm_mm/spm_xlat.c index 45fc704c3..6c02f0743 100644 --- a/services/std_svc/spm_mm/spm_xlat.c +++ b/services/std_svc/spm_mm/spm_xlat.c @@ -15,7 +15,7 @@ #include #include "spm_mm_private.h" -#include "spm_shim_private.h" +#include "spm_mm_shim_private.h" /* Place translation tables by default along with the ones used by BL31. */ #ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME -- cgit v1.2.3 From 6b1d9e6c3907074284b7d632bd2ca0ee0db5c6e2 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Tue, 15 Oct 2019 16:13:10 +0000 Subject: spm-mm: Rename source files Change-Id: I851be04fc5de8a95ea11270996f8ca33f0fccadb Signed-off-by: Paul Beesley --- services/std_svc/spm_mm/spm_main.c | 353 --------------------------------- services/std_svc/spm_mm/spm_mm.mk | 6 +- services/std_svc/spm_mm/spm_mm_main.c | 353 +++++++++++++++++++++++++++++++++ services/std_svc/spm_mm/spm_mm_setup.c | 254 ++++++++++++++++++++++++ services/std_svc/spm_mm/spm_mm_xlat.c | 155 +++++++++++++++ services/std_svc/spm_mm/spm_setup.c | 254 ------------------------ services/std_svc/spm_mm/spm_xlat.c | 155 --------------- 7 files changed, 765 insertions(+), 765 deletions(-) delete mode 100644 services/std_svc/spm_mm/spm_main.c create mode 100644 services/std_svc/spm_mm/spm_mm_main.c create mode 100644 services/std_svc/spm_mm/spm_mm_setup.c create mode 100644 services/std_svc/spm_mm/spm_mm_xlat.c delete mode 100644 services/std_svc/spm_mm/spm_setup.c delete mode 100644 services/std_svc/spm_mm/spm_xlat.c diff --git a/services/std_svc/spm_mm/spm_main.c b/services/std_svc/spm_mm/spm_main.c deleted file mode 100644 index 14c0038ba..000000000 --- a/services/std_svc/spm_mm/spm_main.c +++ /dev/null @@ -1,353 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "spm_mm_private.h" - -/******************************************************************************* - * Secure Partition context information. - ******************************************************************************/ -static sp_context_t sp_ctx; - -/******************************************************************************* - * Set state of a Secure Partition context. - ******************************************************************************/ -void sp_state_set(sp_context_t *sp_ptr, sp_state_t state) -{ - spin_lock(&(sp_ptr->state_lock)); - sp_ptr->state = state; - spin_unlock(&(sp_ptr->state_lock)); -} - -/******************************************************************************* - * Wait until the state of a Secure Partition is the specified one and change it - * to the desired state. - ******************************************************************************/ -void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to) -{ - int success = 0; - - while (success == 0) { - spin_lock(&(sp_ptr->state_lock)); - - if (sp_ptr->state == from) { - sp_ptr->state = to; - - success = 1; - } - - spin_unlock(&(sp_ptr->state_lock)); - } -} - -/******************************************************************************* - * Check if the state of a Secure Partition is the specified one and, if so, - * change it to the desired state. Returns 0 on success, -1 on error. - ******************************************************************************/ -int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to) -{ - int ret = -1; - - spin_lock(&(sp_ptr->state_lock)); - - if (sp_ptr->state == from) { - sp_ptr->state = to; - - ret = 0; - } - - spin_unlock(&(sp_ptr->state_lock)); - - return ret; -} - -/******************************************************************************* - * This function takes an SP context pointer and performs a synchronous entry - * into it. - ******************************************************************************/ -static uint64_t spm_sp_synchronous_entry(sp_context_t *ctx) -{ - uint64_t rc; - - assert(ctx != NULL); - - /* Assign the context of the SP to this CPU */ - cm_set_context(&(ctx->cpu_ctx), SECURE); - - /* Restore the context assigned above */ - cm_el1_sysregs_context_restore(SECURE); - cm_set_next_eret_context(SECURE); - - /* Invalidate TLBs at EL1. */ - tlbivmalle1(); - dsbish(); - - /* Enter Secure Partition */ - rc = spm_secure_partition_enter(&ctx->c_rt_ctx); - - /* Save secure state */ - cm_el1_sysregs_context_save(SECURE); - - return rc; -} - -/******************************************************************************* - * This function returns to the place where spm_sp_synchronous_entry() was - * called originally. - ******************************************************************************/ -__dead2 static void spm_sp_synchronous_exit(uint64_t rc) -{ - sp_context_t *ctx = &sp_ctx; - - /* - * The SPM must have initiated the original request through a - * synchronous entry into the secure partition. Jump back to the - * original C runtime context with the value of rc in x0; - */ - spm_secure_partition_exit(ctx->c_rt_ctx, rc); - - panic(); -} - -/******************************************************************************* - * Jump to each Secure Partition for the first time. - ******************************************************************************/ -static int32_t spm_init(void) -{ - uint64_t rc; - sp_context_t *ctx; - - INFO("Secure Partition init...\n"); - - ctx = &sp_ctx; - - ctx->state = SP_STATE_RESET; - - rc = spm_sp_synchronous_entry(ctx); - assert(rc == 0); - - ctx->state = SP_STATE_IDLE; - - INFO("Secure Partition initialized.\n"); - - return !rc; -} - -/******************************************************************************* - * Initialize contexts of all Secure Partitions. - ******************************************************************************/ -int32_t spm_mm_setup(void) -{ - sp_context_t *ctx; - - /* Disable MMU at EL1 (initialized by BL2) */ - disable_mmu_icache_el1(); - - /* Initialize context of the SP */ - INFO("Secure Partition context setup start...\n"); - - ctx = &sp_ctx; - - /* Assign translation tables context. */ - ctx->xlat_ctx_handle = spm_get_sp_xlat_context(); - - spm_sp_setup(ctx); - - /* Register init function for deferred init. */ - bl31_register_bl32_init(&spm_init); - - INFO("Secure Partition setup done.\n"); - - return 0; -} - -/******************************************************************************* - * Function to perform a call to a Secure Partition. - ******************************************************************************/ -uint64_t spm_mm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3) -{ - uint64_t rc; - sp_context_t *sp_ptr = &sp_ctx; - - /* Wait until the Secure Partition is idle and set it to busy. */ - sp_state_wait_switch(sp_ptr, SP_STATE_IDLE, SP_STATE_BUSY); - - /* Set values for registers on SP entry */ - cpu_context_t *cpu_ctx = &(sp_ptr->cpu_ctx); - - write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X0, smc_fid); - write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X1, x1); - write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X2, x2); - write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X3, x3); - - /* Jump to the Secure Partition. */ - rc = spm_sp_synchronous_entry(sp_ptr); - - /* Flag Secure Partition as idle. */ - assert(sp_ptr->state == SP_STATE_BUSY); - sp_state_set(sp_ptr, SP_STATE_IDLE); - - return rc; -} - -/******************************************************************************* - * MM_COMMUNICATE handler - ******************************************************************************/ -static uint64_t mm_communicate(uint32_t smc_fid, uint64_t mm_cookie, - uint64_t comm_buffer_address, - uint64_t comm_size_address, void *handle) -{ - uint64_t rc; - - /* Cookie. Reserved for future use. It must be zero. */ - if (mm_cookie != 0U) { - ERROR("MM_COMMUNICATE: cookie is not zero\n"); - SMC_RET1(handle, SPM_MM_INVALID_PARAMETER); - } - - if (comm_buffer_address == 0U) { - ERROR("MM_COMMUNICATE: comm_buffer_address is zero\n"); - SMC_RET1(handle, SPM_MM_INVALID_PARAMETER); - } - - if (comm_size_address != 0U) { - VERBOSE("MM_COMMUNICATE: comm_size_address is not 0 as recommended.\n"); - } - - /* - * The current secure partition design mandates - * - at any point, only a single core can be - * executing in the secure partiton. - * - a core cannot be preempted by an interrupt - * while executing in secure partition. - * Raise the running priority of the core to the - * interrupt level configured for secure partition - * so as to block any interrupt from preempting this - * core. - */ - ehf_activate_priority(PLAT_SP_PRI); - - /* Save the Normal world context */ - cm_el1_sysregs_context_save(NON_SECURE); - - rc = spm_mm_sp_call(smc_fid, comm_buffer_address, comm_size_address, - plat_my_core_pos()); - - /* Restore non-secure state */ - cm_el1_sysregs_context_restore(NON_SECURE); - cm_set_next_eret_context(NON_SECURE); - - /* - * Exited from secure partition. This core can take - * interrupts now. - */ - ehf_deactivate_priority(PLAT_SP_PRI); - - SMC_RET1(handle, rc); -} - -/******************************************************************************* - * Secure Partition Manager SMC handler. - ******************************************************************************/ -uint64_t spm_mm_smc_handler(uint32_t smc_fid, - uint64_t x1, - uint64_t x2, - uint64_t x3, - uint64_t x4, - void *cookie, - void *handle, - uint64_t flags) -{ - unsigned int ns; - - /* Determine which security state this SMC originated from */ - ns = is_caller_non_secure(flags); - - if (ns == SMC_FROM_SECURE) { - - /* Handle SMCs from Secure world. */ - - assert(handle == cm_get_context(SECURE)); - - /* Make next ERET jump to S-EL0 instead of S-EL1. */ - cm_set_elr_spsr_el3(SECURE, read_elr_el1(), read_spsr_el1()); - - switch (smc_fid) { - - case SPM_MM_VERSION_AARCH32: - SMC_RET1(handle, SPM_MM_VERSION_COMPILED); - - case MM_SP_EVENT_COMPLETE_AARCH64: - spm_sp_synchronous_exit(x1); - - case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64: - INFO("Received MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 SMC\n"); - - if (sp_ctx.state != SP_STATE_RESET) { - WARN("MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n"); - SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); - } - SMC_RET1(handle, - spm_memory_attributes_get_smc_handler( - &sp_ctx, x1)); - - case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64: - INFO("Received MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n"); - - if (sp_ctx.state != SP_STATE_RESET) { - WARN("MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 is available at boot time only\n"); - SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); - } - SMC_RET1(handle, - spm_memory_attributes_set_smc_handler( - &sp_ctx, x1, x2, x3)); - default: - break; - } - } else { - - /* Handle SMCs from Non-secure world. */ - - assert(handle == cm_get_context(NON_SECURE)); - - switch (smc_fid) { - - case MM_VERSION_AARCH32: - SMC_RET1(handle, MM_VERSION_COMPILED); - - case MM_COMMUNICATE_AARCH32: - case MM_COMMUNICATE_AARCH64: - return mm_communicate(smc_fid, x1, x2, x3, handle); - - case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64: - case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64: - /* SMC interfaces reserved for secure callers. */ - SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); - - default: - break; - } - } - - SMC_RET1(handle, SMC_UNK); -} diff --git a/services/std_svc/spm_mm/spm_mm.mk b/services/std_svc/spm_mm/spm_mm.mk index 4812e75fb..1de31a681 100644 --- a/services/std_svc/spm_mm/spm_mm.mk +++ b/services/std_svc/spm_mm/spm_mm.mk @@ -14,9 +14,9 @@ endif SPM_SOURCES := $(addprefix services/std_svc/spm_mm/, \ ${ARCH}/spm_helpers.S \ ${ARCH}/spm_shim_exceptions.S \ - spm_main.c \ - spm_setup.c \ - spm_xlat.c) + spm_mm_main.c \ + spm_mm_setup.c \ + spm_mm_xlat.c) # Let the top-level Makefile know that we intend to include a BL32 image diff --git a/services/std_svc/spm_mm/spm_mm_main.c b/services/std_svc/spm_mm/spm_mm_main.c new file mode 100644 index 000000000..14c0038ba --- /dev/null +++ b/services/std_svc/spm_mm/spm_mm_main.c @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "spm_mm_private.h" + +/******************************************************************************* + * Secure Partition context information. + ******************************************************************************/ +static sp_context_t sp_ctx; + +/******************************************************************************* + * Set state of a Secure Partition context. + ******************************************************************************/ +void sp_state_set(sp_context_t *sp_ptr, sp_state_t state) +{ + spin_lock(&(sp_ptr->state_lock)); + sp_ptr->state = state; + spin_unlock(&(sp_ptr->state_lock)); +} + +/******************************************************************************* + * Wait until the state of a Secure Partition is the specified one and change it + * to the desired state. + ******************************************************************************/ +void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to) +{ + int success = 0; + + while (success == 0) { + spin_lock(&(sp_ptr->state_lock)); + + if (sp_ptr->state == from) { + sp_ptr->state = to; + + success = 1; + } + + spin_unlock(&(sp_ptr->state_lock)); + } +} + +/******************************************************************************* + * Check if the state of a Secure Partition is the specified one and, if so, + * change it to the desired state. Returns 0 on success, -1 on error. + ******************************************************************************/ +int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to) +{ + int ret = -1; + + spin_lock(&(sp_ptr->state_lock)); + + if (sp_ptr->state == from) { + sp_ptr->state = to; + + ret = 0; + } + + spin_unlock(&(sp_ptr->state_lock)); + + return ret; +} + +/******************************************************************************* + * This function takes an SP context pointer and performs a synchronous entry + * into it. + ******************************************************************************/ +static uint64_t spm_sp_synchronous_entry(sp_context_t *ctx) +{ + uint64_t rc; + + assert(ctx != NULL); + + /* Assign the context of the SP to this CPU */ + cm_set_context(&(ctx->cpu_ctx), SECURE); + + /* Restore the context assigned above */ + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + /* Invalidate TLBs at EL1. */ + tlbivmalle1(); + dsbish(); + + /* Enter Secure Partition */ + rc = spm_secure_partition_enter(&ctx->c_rt_ctx); + + /* Save secure state */ + cm_el1_sysregs_context_save(SECURE); + + return rc; +} + +/******************************************************************************* + * This function returns to the place where spm_sp_synchronous_entry() was + * called originally. + ******************************************************************************/ +__dead2 static void spm_sp_synchronous_exit(uint64_t rc) +{ + sp_context_t *ctx = &sp_ctx; + + /* + * The SPM must have initiated the original request through a + * synchronous entry into the secure partition. Jump back to the + * original C runtime context with the value of rc in x0; + */ + spm_secure_partition_exit(ctx->c_rt_ctx, rc); + + panic(); +} + +/******************************************************************************* + * Jump to each Secure Partition for the first time. + ******************************************************************************/ +static int32_t spm_init(void) +{ + uint64_t rc; + sp_context_t *ctx; + + INFO("Secure Partition init...\n"); + + ctx = &sp_ctx; + + ctx->state = SP_STATE_RESET; + + rc = spm_sp_synchronous_entry(ctx); + assert(rc == 0); + + ctx->state = SP_STATE_IDLE; + + INFO("Secure Partition initialized.\n"); + + return !rc; +} + +/******************************************************************************* + * Initialize contexts of all Secure Partitions. + ******************************************************************************/ +int32_t spm_mm_setup(void) +{ + sp_context_t *ctx; + + /* Disable MMU at EL1 (initialized by BL2) */ + disable_mmu_icache_el1(); + + /* Initialize context of the SP */ + INFO("Secure Partition context setup start...\n"); + + ctx = &sp_ctx; + + /* Assign translation tables context. */ + ctx->xlat_ctx_handle = spm_get_sp_xlat_context(); + + spm_sp_setup(ctx); + + /* Register init function for deferred init. */ + bl31_register_bl32_init(&spm_init); + + INFO("Secure Partition setup done.\n"); + + return 0; +} + +/******************************************************************************* + * Function to perform a call to a Secure Partition. + ******************************************************************************/ +uint64_t spm_mm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3) +{ + uint64_t rc; + sp_context_t *sp_ptr = &sp_ctx; + + /* Wait until the Secure Partition is idle and set it to busy. */ + sp_state_wait_switch(sp_ptr, SP_STATE_IDLE, SP_STATE_BUSY); + + /* Set values for registers on SP entry */ + cpu_context_t *cpu_ctx = &(sp_ptr->cpu_ctx); + + write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X0, smc_fid); + write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X1, x1); + write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X2, x2); + write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X3, x3); + + /* Jump to the Secure Partition. */ + rc = spm_sp_synchronous_entry(sp_ptr); + + /* Flag Secure Partition as idle. */ + assert(sp_ptr->state == SP_STATE_BUSY); + sp_state_set(sp_ptr, SP_STATE_IDLE); + + return rc; +} + +/******************************************************************************* + * MM_COMMUNICATE handler + ******************************************************************************/ +static uint64_t mm_communicate(uint32_t smc_fid, uint64_t mm_cookie, + uint64_t comm_buffer_address, + uint64_t comm_size_address, void *handle) +{ + uint64_t rc; + + /* Cookie. Reserved for future use. It must be zero. */ + if (mm_cookie != 0U) { + ERROR("MM_COMMUNICATE: cookie is not zero\n"); + SMC_RET1(handle, SPM_MM_INVALID_PARAMETER); + } + + if (comm_buffer_address == 0U) { + ERROR("MM_COMMUNICATE: comm_buffer_address is zero\n"); + SMC_RET1(handle, SPM_MM_INVALID_PARAMETER); + } + + if (comm_size_address != 0U) { + VERBOSE("MM_COMMUNICATE: comm_size_address is not 0 as recommended.\n"); + } + + /* + * The current secure partition design mandates + * - at any point, only a single core can be + * executing in the secure partiton. + * - a core cannot be preempted by an interrupt + * while executing in secure partition. + * Raise the running priority of the core to the + * interrupt level configured for secure partition + * so as to block any interrupt from preempting this + * core. + */ + ehf_activate_priority(PLAT_SP_PRI); + + /* Save the Normal world context */ + cm_el1_sysregs_context_save(NON_SECURE); + + rc = spm_mm_sp_call(smc_fid, comm_buffer_address, comm_size_address, + plat_my_core_pos()); + + /* Restore non-secure state */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + /* + * Exited from secure partition. This core can take + * interrupts now. + */ + ehf_deactivate_priority(PLAT_SP_PRI); + + SMC_RET1(handle, rc); +} + +/******************************************************************************* + * Secure Partition Manager SMC handler. + ******************************************************************************/ +uint64_t spm_mm_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + unsigned int ns; + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + + if (ns == SMC_FROM_SECURE) { + + /* Handle SMCs from Secure world. */ + + assert(handle == cm_get_context(SECURE)); + + /* Make next ERET jump to S-EL0 instead of S-EL1. */ + cm_set_elr_spsr_el3(SECURE, read_elr_el1(), read_spsr_el1()); + + switch (smc_fid) { + + case SPM_MM_VERSION_AARCH32: + SMC_RET1(handle, SPM_MM_VERSION_COMPILED); + + case MM_SP_EVENT_COMPLETE_AARCH64: + spm_sp_synchronous_exit(x1); + + case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64: + INFO("Received MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 SMC\n"); + + if (sp_ctx.state != SP_STATE_RESET) { + WARN("MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n"); + SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); + } + SMC_RET1(handle, + spm_memory_attributes_get_smc_handler( + &sp_ctx, x1)); + + case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64: + INFO("Received MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n"); + + if (sp_ctx.state != SP_STATE_RESET) { + WARN("MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 is available at boot time only\n"); + SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); + } + SMC_RET1(handle, + spm_memory_attributes_set_smc_handler( + &sp_ctx, x1, x2, x3)); + default: + break; + } + } else { + + /* Handle SMCs from Non-secure world. */ + + assert(handle == cm_get_context(NON_SECURE)); + + switch (smc_fid) { + + case MM_VERSION_AARCH32: + SMC_RET1(handle, MM_VERSION_COMPILED); + + case MM_COMMUNICATE_AARCH32: + case MM_COMMUNICATE_AARCH64: + return mm_communicate(smc_fid, x1, x2, x3, handle); + + case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64: + case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64: + /* SMC interfaces reserved for secure callers. */ + SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); + + default: + break; + } + } + + SMC_RET1(handle, SMC_UNK); +} diff --git a/services/std_svc/spm_mm/spm_mm_setup.c b/services/std_svc/spm_mm/spm_mm_setup.c new file mode 100644 index 000000000..ccb2f9058 --- /dev/null +++ b/services/std_svc/spm_mm/spm_mm_setup.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "spm_mm_private.h" +#include "spm_mm_shim_private.h" + +/* Setup context of the Secure Partition */ +void spm_sp_setup(sp_context_t *sp_ctx) +{ + cpu_context_t *ctx = &(sp_ctx->cpu_ctx); + + /* + * Initialize CPU context + * ---------------------- + */ + + entry_point_info_t ep_info = {0}; + + SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE); + + /* Setup entrypoint and SPSR */ + ep_info.pc = BL32_BASE; + ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS); + + /* + * X0: Virtual address of a buffer shared between EL3 and Secure EL0. + * The buffer will be mapped in the Secure EL1 translation regime + * with Normal IS WBWA attributes and RO data and Execute Never + * instruction access permissions. + * + * X1: Size of the buffer in bytes + * + * X2: cookie value (Implementation Defined) + * + * X3: cookie value (Implementation Defined) + * + * X4 to X7 = 0 + */ + ep_info.args.arg0 = PLAT_SPM_BUF_BASE; + ep_info.args.arg1 = PLAT_SPM_BUF_SIZE; + ep_info.args.arg2 = PLAT_SPM_COOKIE_0; + ep_info.args.arg3 = PLAT_SPM_COOKIE_1; + + cm_setup_context(ctx, &ep_info); + + /* + * SP_EL0: A non-zero value will indicate to the SP that the SPM has + * initialized the stack pointer for the current CPU through + * implementation defined means. The value will be 0 otherwise. + */ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0, + PLAT_SP_IMAGE_STACK_BASE + PLAT_SP_IMAGE_STACK_PCPU_SIZE); + + /* + * Setup translation tables + * ------------------------ + */ + +#if ENABLE_ASSERTIONS + + /* Get max granularity supported by the platform. */ + unsigned int max_granule = xlat_arch_get_max_supported_granule_size(); + + VERBOSE("Max translation granule size supported: %u KiB\n", + max_granule / 1024U); + + unsigned int max_granule_mask = max_granule - 1U; + + /* Base must be aligned to the max granularity */ + assert((PLAT_SP_IMAGE_NS_BUF_BASE & max_granule_mask) == 0); + + /* Size must be a multiple of the max granularity */ + assert((PLAT_SP_IMAGE_NS_BUF_SIZE & max_granule_mask) == 0); + +#endif /* ENABLE_ASSERTIONS */ + + /* This region contains the exception vectors used at S-EL1. */ + const mmap_region_t sel1_exception_vectors = + MAP_REGION_FLAT(SPM_SHIM_EXCEPTIONS_START, + SPM_SHIM_EXCEPTIONS_SIZE, + MT_CODE | MT_SECURE | MT_PRIVILEGED); + mmap_add_region_ctx(sp_ctx->xlat_ctx_handle, + &sel1_exception_vectors); + + mmap_add_ctx(sp_ctx->xlat_ctx_handle, + plat_get_secure_partition_mmap(NULL)); + + init_xlat_tables_ctx(sp_ctx->xlat_ctx_handle); + + /* + * MMU-related registers + * --------------------- + */ + xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle; + + uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; + + setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table, + xlat_ctx->pa_max_address, xlat_ctx->va_max_address, + EL1_EL0_REGIME); + + write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, + mmu_cfg_params[MMU_CFG_MAIR]); + + write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, + mmu_cfg_params[MMU_CFG_TCR]); + + write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1, + mmu_cfg_params[MMU_CFG_TTBR0]); + + /* Setup SCTLR_EL1 */ + u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); + + sctlr_el1 |= + /*SCTLR_EL1_RES1 |*/ + /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */ + SCTLR_UCI_BIT | + /* RW regions at xlat regime EL1&0 are forced to be XN. */ + SCTLR_WXN_BIT | + /* Don't trap to EL1 execution of WFI or WFE at EL0. */ + SCTLR_NTWI_BIT | SCTLR_NTWE_BIT | + /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */ + SCTLR_UCT_BIT | + /* Don't trap to EL1 execution of DZ ZVA at EL0. */ + SCTLR_DZE_BIT | + /* Enable SP Alignment check for EL0 */ + SCTLR_SA0_BIT | + /* Allow cacheable data and instr. accesses to normal memory. */ + SCTLR_C_BIT | SCTLR_I_BIT | + /* Enable MMU. */ + SCTLR_M_BIT + ; + + sctlr_el1 &= ~( + /* Explicit data accesses at EL0 are little-endian. */ + SCTLR_E0E_BIT | + /* + * Alignment fault checking disabled when at EL1 and EL0 as + * the UEFI spec permits unaligned accesses. + */ + SCTLR_A_BIT | + /* Accesses to DAIF from EL0 are trapped to EL1. */ + SCTLR_UMA_BIT + ); + + write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); + + /* + * Setup other system registers + * ---------------------------- + */ + + /* Shim Exception Vector Base Address */ + write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1, + SPM_SHIM_EXCEPTIONS_PTR); + + write_ctx_reg(get_sysregs_ctx(ctx), CTX_CNTKCTL_EL1, + EL0PTEN_BIT | EL0VTEN_BIT | EL0PCTEN_BIT | EL0VCTEN_BIT); + + /* + * FPEN: Allow the Secure Partition to access FP/SIMD registers. + * Note that SPM will not do any saving/restoring of these registers on + * behalf of the SP. This falls under the SP's responsibility. + * TTA: Enable access to trace registers. + * ZEN (v8.2): Trap SVE instructions and access to SVE registers. + */ + write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1, + CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE)); + + /* + * Prepare information in buffer shared between EL3 and S-EL0 + * ---------------------------------------------------------- + */ + + void *shared_buf_ptr = (void *) PLAT_SPM_BUF_BASE; + + /* Copy the boot information into the shared buffer with the SP. */ + assert((uintptr_t)shared_buf_ptr + sizeof(spm_mm_boot_info_t) + <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)); + + assert(PLAT_SPM_BUF_BASE <= (UINTPTR_MAX - PLAT_SPM_BUF_SIZE + 1)); + + const spm_mm_boot_info_t *sp_boot_info = + plat_get_secure_partition_boot_info(NULL); + + assert(sp_boot_info != NULL); + + memcpy((void *) shared_buf_ptr, (const void *) sp_boot_info, + sizeof(spm_mm_boot_info_t)); + + /* Pointer to the MP information from the platform port. */ + spm_mm_mp_info_t *sp_mp_info = + ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info; + + assert(sp_mp_info != NULL); + + /* + * Point the shared buffer MP information pointer to where the info will + * be populated, just after the boot info. + */ + ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info = + (spm_mm_mp_info_t *) ((uintptr_t)shared_buf_ptr + + sizeof(spm_mm_boot_info_t)); + + /* + * Update the shared buffer pointer to where the MP information for the + * payload will be populated + */ + shared_buf_ptr = ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info; + + /* + * Copy the cpu information into the shared buffer area after the boot + * information. + */ + assert(sp_boot_info->num_cpus <= PLATFORM_CORE_COUNT); + + assert((uintptr_t)shared_buf_ptr + <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE - + (sp_boot_info->num_cpus * sizeof(*sp_mp_info)))); + + memcpy(shared_buf_ptr, (const void *) sp_mp_info, + sp_boot_info->num_cpus * sizeof(*sp_mp_info)); + + /* + * Calculate the linear indices of cores in boot information for the + * secure partition and flag the primary CPU + */ + sp_mp_info = (spm_mm_mp_info_t *) shared_buf_ptr; + + for (unsigned int index = 0; index < sp_boot_info->num_cpus; index++) { + u_register_t mpidr = sp_mp_info[index].mpidr; + + sp_mp_info[index].linear_id = plat_core_pos_by_mpidr(mpidr); + if (plat_my_core_pos() == sp_mp_info[index].linear_id) + sp_mp_info[index].flags |= MP_INFO_FLAG_PRIMARY_CPU; + } +} diff --git a/services/std_svc/spm_mm/spm_mm_xlat.c b/services/std_svc/spm_mm/spm_mm_xlat.c new file mode 100644 index 000000000..6c02f0743 --- /dev/null +++ b/services/std_svc/spm_mm/spm_mm_xlat.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "spm_mm_private.h" +#include "spm_mm_shim_private.h" + +/* Place translation tables by default along with the ones used by BL31. */ +#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME +#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table" +#endif + +/* Allocate and initialise the translation context for the secure partitions. */ +REGISTER_XLAT_CONTEXT2(sp, + PLAT_SP_IMAGE_MMAP_REGIONS, + PLAT_SP_IMAGE_MAX_XLAT_TABLES, + PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE, + EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME); + +/* Lock used for SP_MEMORY_ATTRIBUTES_GET and SP_MEMORY_ATTRIBUTES_SET */ +static spinlock_t mem_attr_smc_lock; + +/* Get handle of Secure Partition translation context */ +xlat_ctx_t *spm_get_sp_xlat_context(void) +{ + return &sp_xlat_ctx; +}; + +/* + * Attributes are encoded using a different format in the SMC interface than in + * the Trusted Firmware, where the mmap_attr_t enum type is used. This function + * converts an attributes value from the SMC format to the mmap_attr_t format by + * setting MT_RW/MT_RO, MT_USER/MT_PRIVILEGED and MT_EXECUTE/MT_EXECUTE_NEVER. + * The other fields are left as 0 because they are ignored by the function + * xlat_change_mem_attributes_ctx(). + */ +static unsigned int smc_attr_to_mmap_attr(unsigned int attributes) +{ + unsigned int tf_attr = 0U; + + unsigned int access = (attributes & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK) + >> MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT; + + if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW) { + tf_attr |= MT_RW | MT_USER; + } else if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO) { + tf_attr |= MT_RO | MT_USER; + } else { + /* Other values are reserved. */ + assert(access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS); + /* The only requirement is that there's no access from EL0 */ + tf_attr |= MT_RO | MT_PRIVILEGED; + } + + if ((attributes & MM_SP_MEMORY_ATTRIBUTES_NON_EXEC) == 0) { + tf_attr |= MT_EXECUTE; + } else { + tf_attr |= MT_EXECUTE_NEVER; + } + + return tf_attr; +} + +/* + * This function converts attributes from the Trusted Firmware format into the + * SMC interface format. + */ +static unsigned int smc_mmap_to_smc_attr(unsigned int attr) +{ + unsigned int smc_attr = 0U; + + unsigned int data_access; + + if ((attr & MT_USER) == 0) { + /* No access from EL0. */ + data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS; + } else { + if ((attr & MT_RW) != 0) { + assert(MT_TYPE(attr) != MT_DEVICE); + data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW; + } else { + data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO; + } + } + + smc_attr |= (data_access & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK) + << MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT; + + if ((attr & MT_EXECUTE_NEVER) != 0U) { + smc_attr |= MM_SP_MEMORY_ATTRIBUTES_NON_EXEC; + } + + return smc_attr; +} + +int32_t spm_memory_attributes_get_smc_handler(sp_context_t *sp_ctx, + uintptr_t base_va) +{ + uint32_t attributes; + + spin_lock(&mem_attr_smc_lock); + + int rc = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle, + base_va, &attributes); + + spin_unlock(&mem_attr_smc_lock); + + /* Convert error codes of xlat_get_mem_attributes_ctx() into SPM. */ + assert((rc == 0) || (rc == -EINVAL)); + + if (rc == 0) { + return (int32_t) smc_mmap_to_smc_attr(attributes); + } else { + return SPM_MM_INVALID_PARAMETER; + } +} + +int spm_memory_attributes_set_smc_handler(sp_context_t *sp_ctx, + u_register_t page_address, + u_register_t pages_count, + u_register_t smc_attributes) +{ + uintptr_t base_va = (uintptr_t) page_address; + size_t size = (size_t) (pages_count * PAGE_SIZE); + uint32_t attributes = (uint32_t) smc_attributes; + + INFO(" Start address : 0x%lx\n", base_va); + INFO(" Number of pages: %i (%zi bytes)\n", (int) pages_count, size); + INFO(" Attributes : 0x%x\n", attributes); + + spin_lock(&mem_attr_smc_lock); + + int ret = xlat_change_mem_attributes_ctx(sp_ctx->xlat_ctx_handle, + base_va, size, + smc_attr_to_mmap_attr(attributes)); + + spin_unlock(&mem_attr_smc_lock); + + /* Convert error codes of xlat_change_mem_attributes_ctx() into SPM. */ + assert((ret == 0) || (ret == -EINVAL)); + + return (ret == 0) ? SPM_MM_SUCCESS : SPM_MM_INVALID_PARAMETER; +} diff --git a/services/std_svc/spm_mm/spm_setup.c b/services/std_svc/spm_mm/spm_setup.c deleted file mode 100644 index ccb2f9058..000000000 --- a/services/std_svc/spm_mm/spm_setup.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "spm_mm_private.h" -#include "spm_mm_shim_private.h" - -/* Setup context of the Secure Partition */ -void spm_sp_setup(sp_context_t *sp_ctx) -{ - cpu_context_t *ctx = &(sp_ctx->cpu_ctx); - - /* - * Initialize CPU context - * ---------------------- - */ - - entry_point_info_t ep_info = {0}; - - SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE); - - /* Setup entrypoint and SPSR */ - ep_info.pc = BL32_BASE; - ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS); - - /* - * X0: Virtual address of a buffer shared between EL3 and Secure EL0. - * The buffer will be mapped in the Secure EL1 translation regime - * with Normal IS WBWA attributes and RO data and Execute Never - * instruction access permissions. - * - * X1: Size of the buffer in bytes - * - * X2: cookie value (Implementation Defined) - * - * X3: cookie value (Implementation Defined) - * - * X4 to X7 = 0 - */ - ep_info.args.arg0 = PLAT_SPM_BUF_BASE; - ep_info.args.arg1 = PLAT_SPM_BUF_SIZE; - ep_info.args.arg2 = PLAT_SPM_COOKIE_0; - ep_info.args.arg3 = PLAT_SPM_COOKIE_1; - - cm_setup_context(ctx, &ep_info); - - /* - * SP_EL0: A non-zero value will indicate to the SP that the SPM has - * initialized the stack pointer for the current CPU through - * implementation defined means. The value will be 0 otherwise. - */ - write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0, - PLAT_SP_IMAGE_STACK_BASE + PLAT_SP_IMAGE_STACK_PCPU_SIZE); - - /* - * Setup translation tables - * ------------------------ - */ - -#if ENABLE_ASSERTIONS - - /* Get max granularity supported by the platform. */ - unsigned int max_granule = xlat_arch_get_max_supported_granule_size(); - - VERBOSE("Max translation granule size supported: %u KiB\n", - max_granule / 1024U); - - unsigned int max_granule_mask = max_granule - 1U; - - /* Base must be aligned to the max granularity */ - assert((PLAT_SP_IMAGE_NS_BUF_BASE & max_granule_mask) == 0); - - /* Size must be a multiple of the max granularity */ - assert((PLAT_SP_IMAGE_NS_BUF_SIZE & max_granule_mask) == 0); - -#endif /* ENABLE_ASSERTIONS */ - - /* This region contains the exception vectors used at S-EL1. */ - const mmap_region_t sel1_exception_vectors = - MAP_REGION_FLAT(SPM_SHIM_EXCEPTIONS_START, - SPM_SHIM_EXCEPTIONS_SIZE, - MT_CODE | MT_SECURE | MT_PRIVILEGED); - mmap_add_region_ctx(sp_ctx->xlat_ctx_handle, - &sel1_exception_vectors); - - mmap_add_ctx(sp_ctx->xlat_ctx_handle, - plat_get_secure_partition_mmap(NULL)); - - init_xlat_tables_ctx(sp_ctx->xlat_ctx_handle); - - /* - * MMU-related registers - * --------------------- - */ - xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle; - - uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; - - setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table, - xlat_ctx->pa_max_address, xlat_ctx->va_max_address, - EL1_EL0_REGIME); - - write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, - mmu_cfg_params[MMU_CFG_MAIR]); - - write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, - mmu_cfg_params[MMU_CFG_TCR]); - - write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1, - mmu_cfg_params[MMU_CFG_TTBR0]); - - /* Setup SCTLR_EL1 */ - u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); - - sctlr_el1 |= - /*SCTLR_EL1_RES1 |*/ - /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */ - SCTLR_UCI_BIT | - /* RW regions at xlat regime EL1&0 are forced to be XN. */ - SCTLR_WXN_BIT | - /* Don't trap to EL1 execution of WFI or WFE at EL0. */ - SCTLR_NTWI_BIT | SCTLR_NTWE_BIT | - /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */ - SCTLR_UCT_BIT | - /* Don't trap to EL1 execution of DZ ZVA at EL0. */ - SCTLR_DZE_BIT | - /* Enable SP Alignment check for EL0 */ - SCTLR_SA0_BIT | - /* Allow cacheable data and instr. accesses to normal memory. */ - SCTLR_C_BIT | SCTLR_I_BIT | - /* Enable MMU. */ - SCTLR_M_BIT - ; - - sctlr_el1 &= ~( - /* Explicit data accesses at EL0 are little-endian. */ - SCTLR_E0E_BIT | - /* - * Alignment fault checking disabled when at EL1 and EL0 as - * the UEFI spec permits unaligned accesses. - */ - SCTLR_A_BIT | - /* Accesses to DAIF from EL0 are trapped to EL1. */ - SCTLR_UMA_BIT - ); - - write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); - - /* - * Setup other system registers - * ---------------------------- - */ - - /* Shim Exception Vector Base Address */ - write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1, - SPM_SHIM_EXCEPTIONS_PTR); - - write_ctx_reg(get_sysregs_ctx(ctx), CTX_CNTKCTL_EL1, - EL0PTEN_BIT | EL0VTEN_BIT | EL0PCTEN_BIT | EL0VCTEN_BIT); - - /* - * FPEN: Allow the Secure Partition to access FP/SIMD registers. - * Note that SPM will not do any saving/restoring of these registers on - * behalf of the SP. This falls under the SP's responsibility. - * TTA: Enable access to trace registers. - * ZEN (v8.2): Trap SVE instructions and access to SVE registers. - */ - write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1, - CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE)); - - /* - * Prepare information in buffer shared between EL3 and S-EL0 - * ---------------------------------------------------------- - */ - - void *shared_buf_ptr = (void *) PLAT_SPM_BUF_BASE; - - /* Copy the boot information into the shared buffer with the SP. */ - assert((uintptr_t)shared_buf_ptr + sizeof(spm_mm_boot_info_t) - <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)); - - assert(PLAT_SPM_BUF_BASE <= (UINTPTR_MAX - PLAT_SPM_BUF_SIZE + 1)); - - const spm_mm_boot_info_t *sp_boot_info = - plat_get_secure_partition_boot_info(NULL); - - assert(sp_boot_info != NULL); - - memcpy((void *) shared_buf_ptr, (const void *) sp_boot_info, - sizeof(spm_mm_boot_info_t)); - - /* Pointer to the MP information from the platform port. */ - spm_mm_mp_info_t *sp_mp_info = - ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info; - - assert(sp_mp_info != NULL); - - /* - * Point the shared buffer MP information pointer to where the info will - * be populated, just after the boot info. - */ - ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info = - (spm_mm_mp_info_t *) ((uintptr_t)shared_buf_ptr - + sizeof(spm_mm_boot_info_t)); - - /* - * Update the shared buffer pointer to where the MP information for the - * payload will be populated - */ - shared_buf_ptr = ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info; - - /* - * Copy the cpu information into the shared buffer area after the boot - * information. - */ - assert(sp_boot_info->num_cpus <= PLATFORM_CORE_COUNT); - - assert((uintptr_t)shared_buf_ptr - <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE - - (sp_boot_info->num_cpus * sizeof(*sp_mp_info)))); - - memcpy(shared_buf_ptr, (const void *) sp_mp_info, - sp_boot_info->num_cpus * sizeof(*sp_mp_info)); - - /* - * Calculate the linear indices of cores in boot information for the - * secure partition and flag the primary CPU - */ - sp_mp_info = (spm_mm_mp_info_t *) shared_buf_ptr; - - for (unsigned int index = 0; index < sp_boot_info->num_cpus; index++) { - u_register_t mpidr = sp_mp_info[index].mpidr; - - sp_mp_info[index].linear_id = plat_core_pos_by_mpidr(mpidr); - if (plat_my_core_pos() == sp_mp_info[index].linear_id) - sp_mp_info[index].flags |= MP_INFO_FLAG_PRIMARY_CPU; - } -} diff --git a/services/std_svc/spm_mm/spm_xlat.c b/services/std_svc/spm_mm/spm_xlat.c deleted file mode 100644 index 6c02f0743..000000000 --- a/services/std_svc/spm_mm/spm_xlat.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "spm_mm_private.h" -#include "spm_mm_shim_private.h" - -/* Place translation tables by default along with the ones used by BL31. */ -#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME -#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table" -#endif - -/* Allocate and initialise the translation context for the secure partitions. */ -REGISTER_XLAT_CONTEXT2(sp, - PLAT_SP_IMAGE_MMAP_REGIONS, - PLAT_SP_IMAGE_MAX_XLAT_TABLES, - PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE, - EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME); - -/* Lock used for SP_MEMORY_ATTRIBUTES_GET and SP_MEMORY_ATTRIBUTES_SET */ -static spinlock_t mem_attr_smc_lock; - -/* Get handle of Secure Partition translation context */ -xlat_ctx_t *spm_get_sp_xlat_context(void) -{ - return &sp_xlat_ctx; -}; - -/* - * Attributes are encoded using a different format in the SMC interface than in - * the Trusted Firmware, where the mmap_attr_t enum type is used. This function - * converts an attributes value from the SMC format to the mmap_attr_t format by - * setting MT_RW/MT_RO, MT_USER/MT_PRIVILEGED and MT_EXECUTE/MT_EXECUTE_NEVER. - * The other fields are left as 0 because they are ignored by the function - * xlat_change_mem_attributes_ctx(). - */ -static unsigned int smc_attr_to_mmap_attr(unsigned int attributes) -{ - unsigned int tf_attr = 0U; - - unsigned int access = (attributes & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK) - >> MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT; - - if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW) { - tf_attr |= MT_RW | MT_USER; - } else if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO) { - tf_attr |= MT_RO | MT_USER; - } else { - /* Other values are reserved. */ - assert(access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS); - /* The only requirement is that there's no access from EL0 */ - tf_attr |= MT_RO | MT_PRIVILEGED; - } - - if ((attributes & MM_SP_MEMORY_ATTRIBUTES_NON_EXEC) == 0) { - tf_attr |= MT_EXECUTE; - } else { - tf_attr |= MT_EXECUTE_NEVER; - } - - return tf_attr; -} - -/* - * This function converts attributes from the Trusted Firmware format into the - * SMC interface format. - */ -static unsigned int smc_mmap_to_smc_attr(unsigned int attr) -{ - unsigned int smc_attr = 0U; - - unsigned int data_access; - - if ((attr & MT_USER) == 0) { - /* No access from EL0. */ - data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS; - } else { - if ((attr & MT_RW) != 0) { - assert(MT_TYPE(attr) != MT_DEVICE); - data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW; - } else { - data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO; - } - } - - smc_attr |= (data_access & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK) - << MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT; - - if ((attr & MT_EXECUTE_NEVER) != 0U) { - smc_attr |= MM_SP_MEMORY_ATTRIBUTES_NON_EXEC; - } - - return smc_attr; -} - -int32_t spm_memory_attributes_get_smc_handler(sp_context_t *sp_ctx, - uintptr_t base_va) -{ - uint32_t attributes; - - spin_lock(&mem_attr_smc_lock); - - int rc = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle, - base_va, &attributes); - - spin_unlock(&mem_attr_smc_lock); - - /* Convert error codes of xlat_get_mem_attributes_ctx() into SPM. */ - assert((rc == 0) || (rc == -EINVAL)); - - if (rc == 0) { - return (int32_t) smc_mmap_to_smc_attr(attributes); - } else { - return SPM_MM_INVALID_PARAMETER; - } -} - -int spm_memory_attributes_set_smc_handler(sp_context_t *sp_ctx, - u_register_t page_address, - u_register_t pages_count, - u_register_t smc_attributes) -{ - uintptr_t base_va = (uintptr_t) page_address; - size_t size = (size_t) (pages_count * PAGE_SIZE); - uint32_t attributes = (uint32_t) smc_attributes; - - INFO(" Start address : 0x%lx\n", base_va); - INFO(" Number of pages: %i (%zi bytes)\n", (int) pages_count, size); - INFO(" Attributes : 0x%x\n", attributes); - - spin_lock(&mem_attr_smc_lock); - - int ret = xlat_change_mem_attributes_ctx(sp_ctx->xlat_ctx_handle, - base_va, size, - smc_attr_to_mmap_attr(attributes)); - - spin_unlock(&mem_attr_smc_lock); - - /* Convert error codes of xlat_change_mem_attributes_ctx() into SPM. */ - assert((ret == 0) || (ret == -EINVAL)); - - return (ret == 0) ? SPM_MM_SUCCESS : SPM_MM_INVALID_PARAMETER; -} -- cgit v1.2.3 From 99c69109ec2602eba16d5fa190fef9cd6e5cef22 Mon Sep 17 00:00:00 2001 From: Paul Beesley Date: Tue, 15 Oct 2019 16:14:14 +0000 Subject: spm-mm: Rename aarch64 assembly files Change-Id: I2bab67f319758dd033aa689d985227cad796cdea Signed-off-by: Paul Beesley --- services/std_svc/spm_mm/aarch64/spm_helpers.S | 74 ------------ services/std_svc/spm_mm/aarch64/spm_mm_helpers.S | 74 ++++++++++++ .../spm_mm/aarch64/spm_mm_shim_exceptions.S | 128 +++++++++++++++++++++ .../std_svc/spm_mm/aarch64/spm_shim_exceptions.S | 128 --------------------- services/std_svc/spm_mm/spm_mm.mk | 4 +- 5 files changed, 204 insertions(+), 204 deletions(-) delete mode 100644 services/std_svc/spm_mm/aarch64/spm_helpers.S create mode 100644 services/std_svc/spm_mm/aarch64/spm_mm_helpers.S create mode 100644 services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S delete mode 100644 services/std_svc/spm_mm/aarch64/spm_shim_exceptions.S diff --git a/services/std_svc/spm_mm/aarch64/spm_helpers.S b/services/std_svc/spm_mm/aarch64/spm_helpers.S deleted file mode 100644 index 2c3aaf7ae..000000000 --- a/services/std_svc/spm_mm/aarch64/spm_helpers.S +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "../spm_mm_private.h" - - .global spm_secure_partition_enter - .global spm_secure_partition_exit - - /* --------------------------------------------------------------------- - * This function is called with SP_EL0 as stack. Here we stash our EL3 - * callee-saved registers on to the stack as a part of saving the C - * runtime and enter the secure payload. - * 'x0' contains a pointer to the memory where the address of the C - * runtime context is to be saved. - * --------------------------------------------------------------------- - */ -func spm_secure_partition_enter - /* Make space for the registers that we're going to save */ - mov x3, sp - str x3, [x0, #0] - sub sp, sp, #SP_C_RT_CTX_SIZE - - /* Save callee-saved registers on to the stack */ - stp x19, x20, [sp, #SP_C_RT_CTX_X19] - stp x21, x22, [sp, #SP_C_RT_CTX_X21] - stp x23, x24, [sp, #SP_C_RT_CTX_X23] - stp x25, x26, [sp, #SP_C_RT_CTX_X25] - stp x27, x28, [sp, #SP_C_RT_CTX_X27] - stp x29, x30, [sp, #SP_C_RT_CTX_X29] - - /* --------------------------------------------------------------------- - * Everything is setup now. el3_exit() will use the secure context to - * restore to the general purpose and EL3 system registers to ERET - * into the secure payload. - * --------------------------------------------------------------------- - */ - b el3_exit -endfunc spm_secure_partition_enter - - /* --------------------------------------------------------------------- - * This function is called with 'x0' pointing to a C runtime context - * saved in spm_secure_partition_enter(). - * It restores the saved registers and jumps to that runtime with 'x0' - * as the new SP register. This destroys the C runtime context that had - * been built on the stack below the saved context by the caller. Later - * the second parameter 'x1' is passed as a return value to the caller. - * --------------------------------------------------------------------- - */ -func spm_secure_partition_exit - /* Restore the previous stack */ - mov sp, x0 - - /* Restore callee-saved registers on to the stack */ - ldp x19, x20, [x0, #(SP_C_RT_CTX_X19 - SP_C_RT_CTX_SIZE)] - ldp x21, x22, [x0, #(SP_C_RT_CTX_X21 - SP_C_RT_CTX_SIZE)] - ldp x23, x24, [x0, #(SP_C_RT_CTX_X23 - SP_C_RT_CTX_SIZE)] - ldp x25, x26, [x0, #(SP_C_RT_CTX_X25 - SP_C_RT_CTX_SIZE)] - ldp x27, x28, [x0, #(SP_C_RT_CTX_X27 - SP_C_RT_CTX_SIZE)] - ldp x29, x30, [x0, #(SP_C_RT_CTX_X29 - SP_C_RT_CTX_SIZE)] - - /* --------------------------------------------------------------------- - * This should take us back to the instruction after the call to the - * last spm_secure_partition_enter().* Place the second parameter to x0 - * so that the caller will see it as a return value from the original - * entry call. - * --------------------------------------------------------------------- - */ - mov x0, x1 - ret -endfunc spm_secure_partition_exit diff --git a/services/std_svc/spm_mm/aarch64/spm_mm_helpers.S b/services/std_svc/spm_mm/aarch64/spm_mm_helpers.S new file mode 100644 index 000000000..2c3aaf7ae --- /dev/null +++ b/services/std_svc/spm_mm/aarch64/spm_mm_helpers.S @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "../spm_mm_private.h" + + .global spm_secure_partition_enter + .global spm_secure_partition_exit + + /* --------------------------------------------------------------------- + * This function is called with SP_EL0 as stack. Here we stash our EL3 + * callee-saved registers on to the stack as a part of saving the C + * runtime and enter the secure payload. + * 'x0' contains a pointer to the memory where the address of the C + * runtime context is to be saved. + * --------------------------------------------------------------------- + */ +func spm_secure_partition_enter + /* Make space for the registers that we're going to save */ + mov x3, sp + str x3, [x0, #0] + sub sp, sp, #SP_C_RT_CTX_SIZE + + /* Save callee-saved registers on to the stack */ + stp x19, x20, [sp, #SP_C_RT_CTX_X19] + stp x21, x22, [sp, #SP_C_RT_CTX_X21] + stp x23, x24, [sp, #SP_C_RT_CTX_X23] + stp x25, x26, [sp, #SP_C_RT_CTX_X25] + stp x27, x28, [sp, #SP_C_RT_CTX_X27] + stp x29, x30, [sp, #SP_C_RT_CTX_X29] + + /* --------------------------------------------------------------------- + * Everything is setup now. el3_exit() will use the secure context to + * restore to the general purpose and EL3 system registers to ERET + * into the secure payload. + * --------------------------------------------------------------------- + */ + b el3_exit +endfunc spm_secure_partition_enter + + /* --------------------------------------------------------------------- + * This function is called with 'x0' pointing to a C runtime context + * saved in spm_secure_partition_enter(). + * It restores the saved registers and jumps to that runtime with 'x0' + * as the new SP register. This destroys the C runtime context that had + * been built on the stack below the saved context by the caller. Later + * the second parameter 'x1' is passed as a return value to the caller. + * --------------------------------------------------------------------- + */ +func spm_secure_partition_exit + /* Restore the previous stack */ + mov sp, x0 + + /* Restore callee-saved registers on to the stack */ + ldp x19, x20, [x0, #(SP_C_RT_CTX_X19 - SP_C_RT_CTX_SIZE)] + ldp x21, x22, [x0, #(SP_C_RT_CTX_X21 - SP_C_RT_CTX_SIZE)] + ldp x23, x24, [x0, #(SP_C_RT_CTX_X23 - SP_C_RT_CTX_SIZE)] + ldp x25, x26, [x0, #(SP_C_RT_CTX_X25 - SP_C_RT_CTX_SIZE)] + ldp x27, x28, [x0, #(SP_C_RT_CTX_X27 - SP_C_RT_CTX_SIZE)] + ldp x29, x30, [x0, #(SP_C_RT_CTX_X29 - SP_C_RT_CTX_SIZE)] + + /* --------------------------------------------------------------------- + * This should take us back to the instruction after the call to the + * last spm_secure_partition_enter().* Place the second parameter to x0 + * so that the caller will see it as a return value from the original + * entry call. + * --------------------------------------------------------------------- + */ + mov x0, x1 + ret +endfunc spm_secure_partition_exit diff --git a/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S b/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S new file mode 100644 index 000000000..dab615012 --- /dev/null +++ b/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +/* ----------------------------------------------------------------------------- + * Very simple stackless exception handlers used by the spm shim layer. + * ----------------------------------------------------------------------------- + */ + .globl spm_shim_exceptions_ptr + +vector_base spm_shim_exceptions_ptr, .spm_shim_exceptions + + /* ----------------------------------------------------- + * Current EL with SP0 : 0x0 - 0x200 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionSP0, .spm_shim_exceptions + b . +end_vector_entry SynchronousExceptionSP0 + +vector_entry IrqSP0, .spm_shim_exceptions + b . +end_vector_entry IrqSP0 + +vector_entry FiqSP0, .spm_shim_exceptions + b . +end_vector_entry FiqSP0 + +vector_entry SErrorSP0, .spm_shim_exceptions + b . +end_vector_entry SErrorSP0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x400 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionSPx, .spm_shim_exceptions + b . +end_vector_entry SynchronousExceptionSPx + +vector_entry IrqSPx, .spm_shim_exceptions + b . +end_vector_entry IrqSPx + +vector_entry FiqSPx, .spm_shim_exceptions + b . +end_vector_entry FiqSPx + +vector_entry SErrorSPx, .spm_shim_exceptions + b . +end_vector_entry SErrorSPx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x600. No exceptions + * are handled since secure_partition does not implement + * a lower EL + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionA64, .spm_shim_exceptions + msr tpidr_el1, x30 + mrs x30, esr_el1 + ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + + cmp x30, #EC_AARCH64_SVC + b.eq do_smc + + cmp x30, #EC_AARCH32_SVC + b.eq do_smc + + cmp x30, #EC_AARCH64_SYS + b.eq handle_sys_trap + + /* Fail in all the other cases */ + b panic + + /* --------------------------------------------- + * Tell SPM that we are done initialising + * --------------------------------------------- + */ +do_smc: + mrs x30, tpidr_el1 + smc #0 + eret + + /* AArch64 system instructions trap are handled as a panic for now */ +handle_sys_trap: +panic: + b panic +end_vector_entry SynchronousExceptionA64 + +vector_entry IrqA64, .spm_shim_exceptions + b . +end_vector_entry IrqA64 + +vector_entry FiqA64, .spm_shim_exceptions + b . +end_vector_entry FiqA64 + +vector_entry SErrorA64, .spm_shim_exceptions + b . +end_vector_entry SErrorA64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x600 - 0x800 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionA32, .spm_shim_exceptions + b . +end_vector_entry SynchronousExceptionA32 + +vector_entry IrqA32, .spm_shim_exceptions + b . +end_vector_entry IrqA32 + +vector_entry FiqA32, .spm_shim_exceptions + b . +end_vector_entry FiqA32 + +vector_entry SErrorA32, .spm_shim_exceptions + b . +end_vector_entry SErrorA32 diff --git a/services/std_svc/spm_mm/aarch64/spm_shim_exceptions.S b/services/std_svc/spm_mm/aarch64/spm_shim_exceptions.S deleted file mode 100644 index dab615012..000000000 --- a/services/std_svc/spm_mm/aarch64/spm_shim_exceptions.S +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -/* ----------------------------------------------------------------------------- - * Very simple stackless exception handlers used by the spm shim layer. - * ----------------------------------------------------------------------------- - */ - .globl spm_shim_exceptions_ptr - -vector_base spm_shim_exceptions_ptr, .spm_shim_exceptions - - /* ----------------------------------------------------- - * Current EL with SP0 : 0x0 - 0x200 - * ----------------------------------------------------- - */ -vector_entry SynchronousExceptionSP0, .spm_shim_exceptions - b . -end_vector_entry SynchronousExceptionSP0 - -vector_entry IrqSP0, .spm_shim_exceptions - b . -end_vector_entry IrqSP0 - -vector_entry FiqSP0, .spm_shim_exceptions - b . -end_vector_entry FiqSP0 - -vector_entry SErrorSP0, .spm_shim_exceptions - b . -end_vector_entry SErrorSP0 - - /* ----------------------------------------------------- - * Current EL with SPx: 0x200 - 0x400 - * ----------------------------------------------------- - */ -vector_entry SynchronousExceptionSPx, .spm_shim_exceptions - b . -end_vector_entry SynchronousExceptionSPx - -vector_entry IrqSPx, .spm_shim_exceptions - b . -end_vector_entry IrqSPx - -vector_entry FiqSPx, .spm_shim_exceptions - b . -end_vector_entry FiqSPx - -vector_entry SErrorSPx, .spm_shim_exceptions - b . -end_vector_entry SErrorSPx - - /* ----------------------------------------------------- - * Lower EL using AArch64 : 0x400 - 0x600. No exceptions - * are handled since secure_partition does not implement - * a lower EL - * ----------------------------------------------------- - */ -vector_entry SynchronousExceptionA64, .spm_shim_exceptions - msr tpidr_el1, x30 - mrs x30, esr_el1 - ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH - - cmp x30, #EC_AARCH64_SVC - b.eq do_smc - - cmp x30, #EC_AARCH32_SVC - b.eq do_smc - - cmp x30, #EC_AARCH64_SYS - b.eq handle_sys_trap - - /* Fail in all the other cases */ - b panic - - /* --------------------------------------------- - * Tell SPM that we are done initialising - * --------------------------------------------- - */ -do_smc: - mrs x30, tpidr_el1 - smc #0 - eret - - /* AArch64 system instructions trap are handled as a panic for now */ -handle_sys_trap: -panic: - b panic -end_vector_entry SynchronousExceptionA64 - -vector_entry IrqA64, .spm_shim_exceptions - b . -end_vector_entry IrqA64 - -vector_entry FiqA64, .spm_shim_exceptions - b . -end_vector_entry FiqA64 - -vector_entry SErrorA64, .spm_shim_exceptions - b . -end_vector_entry SErrorA64 - - /* ----------------------------------------------------- - * Lower EL using AArch32 : 0x600 - 0x800 - * ----------------------------------------------------- - */ -vector_entry SynchronousExceptionA32, .spm_shim_exceptions - b . -end_vector_entry SynchronousExceptionA32 - -vector_entry IrqA32, .spm_shim_exceptions - b . -end_vector_entry IrqA32 - -vector_entry FiqA32, .spm_shim_exceptions - b . -end_vector_entry FiqA32 - -vector_entry SErrorA32, .spm_shim_exceptions - b . -end_vector_entry SErrorA32 diff --git a/services/std_svc/spm_mm/spm_mm.mk b/services/std_svc/spm_mm/spm_mm.mk index 1de31a681..656488b8e 100644 --- a/services/std_svc/spm_mm/spm_mm.mk +++ b/services/std_svc/spm_mm/spm_mm.mk @@ -12,8 +12,8 @@ ifneq (${ARCH},aarch64) endif SPM_SOURCES := $(addprefix services/std_svc/spm_mm/, \ - ${ARCH}/spm_helpers.S \ - ${ARCH}/spm_shim_exceptions.S \ + ${ARCH}/spm_mm_helpers.S \ + ${ARCH}/spm_mm_shim_exceptions.S \ spm_mm_main.c \ spm_mm_setup.c \ spm_mm_xlat.c) -- cgit v1.2.3 From ba4b453b595344d4b9c21d85ac07aa2fa4928c96 Mon Sep 17 00:00:00 2001 From: Sheetal Tigadoli Date: Fri, 12 Apr 2019 15:28:44 +0530 Subject: lib: cpu: Add additional field definition for A72 L2 control Add additional field definitions for Cortex_A72 L2 Control registers Change-Id: I5ef3a6db41cd7c5d9904172720682716276b7889 Signed-off-by: Sheetal Tigadoli --- include/lib/cpus/aarch64/cortex_a72.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 4a444c67a..28b440e19 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -43,7 +43,14 @@ ******************************************************************************/ #define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0 +#define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE (ULL(1) << 28) +#define CORTEX_A72_L2ACTLR_FORCE_L2_LOGIC_CLK_ACTIVE (ULL(1) << 27) +#define CORTEX_A72_L2ACTLR_FORCE_L2_GIC_TIMER_RCG_CLK_ACTIVE (ULL(1) << 26) #define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14) +#define CORTEX_A72_L2ACTLR_DISABLE_DSB_WITH_NO_DVM_SYNC (ULL(1) << 11) +#define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8) +#define CORTEX_A72_L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT (ULL(1) << 7) +#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (ULL(1) << 6) /******************************************************************************* * L2 Control register specific definitions. @@ -51,8 +58,12 @@ #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) +#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5) #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) +#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT U(9) +#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7) +#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7) #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) -- cgit v1.2.3 From 83e955241aafb4bfac8f2b6db402d7bfc34a5167 Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Wed, 18 Dec 2019 15:56:27 -0600 Subject: Workaround for Hercules erratum 1688305 Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions of Hercules core. The erratum can be avoided by setting bit 1 of the implementation defined register CPUACTLR2_EL1 to 1 to prevent store- release from being dispatched before it is the oldest. Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed Signed-off-by: Madhukar Pappireddy --- docs/design/cpu-specific-build-macros.rst | 6 +++ include/lib/cpus/aarch64/cortex_hercules.h | 3 ++ lib/cpus/aarch64/cortex_hercules.S | 65 +++++++++++++++++++++++++----- lib/cpus/cpu-ops.mk | 8 ++++ 4 files changed, 71 insertions(+), 11 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 891703bf0..7fa027f42 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -227,6 +227,12 @@ For Cortex-A76, the following errata build flags are defined : - ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +For Hercules, the following errata build flags are defined : + +- ``ERRATA_HERCULES_1688305``: This applies errata 1688305 workaround to + Hercules CPU. This needs to be enabled only for revision r0p0 - r1p0 of + the CPU. + For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 diff --git a/include/lib/cpus/aarch64/cortex_hercules.h b/include/lib/cpus/aarch64/cortex_hercules.h index b943e7a4d..d5ca85ed2 100644 --- a/include/lib/cpus/aarch64/cortex_hercules.h +++ b/include/lib/cpus/aarch64/cortex_hercules.h @@ -27,6 +27,9 @@ ******************************************************************************/ #define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30) +#define CORTEX_HERCULES_ACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_HERCULES_ACTLR2_EL1_BIT_1 (ULL(1) << 1) + /******************************************************************************* * CPU Activity Monitor Unit register specific definitions. ******************************************************************************/ diff --git a/lib/cpus/aarch64/cortex_hercules.S b/lib/cpus/aarch64/cortex_hercules.S index 4e048145f..a23919626 100644 --- a/lib/cpus/aarch64/cortex_hercules.S +++ b/lib/cpus/aarch64/cortex_hercules.S @@ -16,12 +16,49 @@ #error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled" #endif + +/* -------------------------------------------------- + * Errata Workaround for Hercules Erratum 1688305. + * This applies to revision r0p0 and r1p0 of Hercules. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_hercules_1688305_wa + /* Compare x0 against revision r1p0 */ + mov x17, x30 + bl check_errata_1688305 + cbz x0, 1f + mrs x1, CORTEX_HERCULES_ACTLR2_EL1 + orr x1, x1, CORTEX_HERCULES_ACTLR2_EL1_BIT_1 + msr CORTEX_HERCULES_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_hercules_1688305_wa + +func check_errata_1688305 + /* Applies to r0p0 and r1p0 */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1688305 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-Hercules * ------------------------------------------------- */ -#if ENABLE_AMU func cortex_hercules_reset_func + mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_HERCULES_1688305 + mov x0, x18 + bl errata_hercules_1688305_wa +#endif + +#if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT @@ -39,11 +76,11 @@ func cortex_hercules_reset_func /* Enable group1 counters */ mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK msr CPUAMCNTENSET1_EL0, x0 - isb +#endif - ret + isb + ret x19 endfunc cortex_hercules_reset_func -#endif /* --------------------------------------------- * HW will do the cache maintenance while powering down @@ -66,6 +103,18 @@ endfunc cortex_hercules_core_pwr_dwn */ #if REPORT_ERRATA func cortex_hercules_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_HERCULES_1688305, cortex_hercules, 1688305 + + ldp x8, x30, [sp], #16 ret endfunc cortex_hercules_errata_report #endif @@ -89,12 +138,6 @@ func cortex_hercules_cpu_reg_dump ret endfunc cortex_hercules_cpu_reg_dump -#if ENABLE_AMU -#define HERCULES_RESET_FUNC cortex_hercules_reset_func -#else -#define HERCULES_RESET_FUNC CPU_NO_RESET_FUNC -#endif - declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \ - HERCULES_RESET_FUNC, \ + cortex_hercules_reset_func, \ cortex_hercules_core_pwr_dwn diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 078888ebf..c9b9b387e 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -234,6 +234,10 @@ ERRATA_A76_1275112 ?=0 # only to revision <= r3p0 of the Cortex A76 cpu. ERRATA_A76_1286807 ?=0 +# Flag to apply erratum 1688305 workaround during reset. This erratum applies +# to revisions r0p0 - r1p0 of the Hercules cpu. +ERRATA_HERCULES_1688305 ?=0 + # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=1 @@ -467,6 +471,10 @@ $(eval $(call add_define,ERRATA_A76_1275112)) $(eval $(call assert_boolean,ERRATA_A76_1286807)) $(eval $(call add_define,ERRATA_A76_1286807)) +# Process ERRATA_HERCULES_1688305 flag +$(eval $(call assert_boolean,ERRATA_HERCULES_1688305)) +$(eval $(call add_define,ERRATA_HERCULES_1688305)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) -- cgit v1.2.3 From ecd138df71ef59b59b0cf3be8d91206626b86274 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 8 Jul 2019 13:46:44 +0900 Subject: uniphier: call uniphier_scp_is_running() only when on-chip STM is supported uniphier_scp_is_running() reads the UNIPHIER_STMBE2COM register, but it does not exist on all SoCs. Do not call this function if the on-chip SCP is not supported. Change-Id: I7c71ca0735e3a8e095c3f22ba6165f82a2986362 Signed-off-by: Masahiro Yamada --- plat/socionext/uniphier/platform.mk | 1 + plat/socionext/uniphier/uniphier_psci.c | 25 ++++++++++++++++++------- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk index d97458490..d31fbe88f 100644 --- a/plat/socionext/uniphier/platform.mk +++ b/plat/socionext/uniphier/platform.mk @@ -60,6 +60,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ plat/common/plat_gicv3.c \ plat/common/plat_psci_common.c \ $(PLAT_PATH)/uniphier_bl31_setup.c \ + $(PLAT_PATH)/uniphier_boot_device.c \ $(PLAT_PATH)/uniphier_cci.c \ $(PLAT_PATH)/uniphier_gicv3.c \ $(PLAT_PATH)/uniphier_psci.c \ diff --git a/plat/socionext/uniphier/uniphier_psci.c b/plat/socionext/uniphier/uniphier_psci.c index 464252ddd..2acc87440 100644 --- a/plat/socionext/uniphier/uniphier_psci.c +++ b/plat/socionext/uniphier/uniphier_psci.c @@ -6,6 +6,7 @@ #include #include +#include #include #include @@ -113,17 +114,27 @@ static const struct plat_psci_ops uniphier_psci_ops = { int plat_setup_psci_ops(uintptr_t sec_entrypoint, const struct plat_psci_ops **psci_ops) { + unsigned int soc; + + soc = uniphier_get_soc_id(); + if (soc == UNIPHIER_SOC_UNKNOWN) { + ERROR("unsupported SoC\n"); + return -ENOTSUP; + } + + if (uniphier_get_boot_master(soc) == UNIPHIER_BOOT_MASTER_SCP) { + uniphier_psci_scp_mode = uniphier_scp_is_running(); + flush_dcache_range((uint64_t)&uniphier_psci_scp_mode, + sizeof(uniphier_psci_scp_mode)); + + if (uniphier_psci_scp_mode) + uniphier_scp_open_com(); + } + uniphier_sec_entrypoint = sec_entrypoint; flush_dcache_range((uint64_t)&uniphier_sec_entrypoint, sizeof(uniphier_sec_entrypoint)); - uniphier_psci_scp_mode = uniphier_scp_is_running(); - flush_dcache_range((uint64_t)&uniphier_psci_scp_mode, - sizeof(uniphier_psci_scp_mode)); - - if (uniphier_psci_scp_mode) - uniphier_scp_open_com(); - *psci_ops = &uniphier_psci_ops; return 0; -- cgit v1.2.3 From a0278474669839bc2698da82ea2f4973eb7c8830 Mon Sep 17 00:00:00 2001 From: Roger Lu Date: Tue, 24 Dec 2019 15:32:37 +0800 Subject: mediatek: mt8183: add Vmodem/Vcore DVS init level spm resume will restore Vmodem/Vcore voltages back based on the SPM_DVS_LEVEL. Change-Id: I37ff7ce4ba62219c1858acea816c5bc9ce6c493e Signed-off-by: Roger Lu --- plat/mediatek/mt8183/drivers/spm/spm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/plat/mediatek/mt8183/drivers/spm/spm.c b/plat/mediatek/mt8183/drivers/spm/spm.c index 547af5781..d6d2344c1 100644 --- a/plat/mediatek/mt8183/drivers/spm/spm.c +++ b/plat/mediatek/mt8183/drivers/spm/spm.c @@ -12,6 +12,12 @@ DEFINE_BAKERY_LOCK(spm_lock); +/* SPM_DVS_LEVEL */ +#define SPM_VMODEM_LEVEL_MASK (0xff << 16) +#define SPM_VMODEM_LEVEL (1U << 18) +#define SPM_VCORE_LEVEL_MASK (0xff) +#define SPM_VCORE_LEVEL (1U << 1) + /* CLK_SCP_CFG_0 */ #define SPM_CK_OFF_CONTROL (0x3FF) @@ -339,6 +345,11 @@ void spm_boot_init(void) spm_lock_init(); mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); + /* Set Vmodem / Vcore DVS init level */ + mmio_clrsetbits_32(SPM_DVS_LEVEL, + SPM_VMODEM_LEVEL_MASK | SPM_VCORE_LEVEL_MASK, + SPM_VMODEM_LEVEL | SPM_VCORE_LEVEL); + /* switch ck_off/axi_26m control to SPM */ mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL); mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL); -- cgit v1.2.3 From f998a052fd94ea082833109f25b94ed5bfa24e8b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 25 Jul 2019 10:57:38 +0900 Subject: uniphier: run BL33 at EL2 All the SoCs in 64-bit UniPhier SoC family support EL2. Just hard-code MODE_EL2 instead of using el_implemented() helper. Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0 Signed-off-by: Masahiro Yamada --- plat/socionext/uniphier/uniphier_image_desc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/socionext/uniphier/uniphier_image_desc.c b/plat/socionext/uniphier/uniphier_image_desc.c index 9e171e073..817029a2c 100644 --- a/plat/socionext/uniphier/uniphier_image_desc.c +++ b/plat/socionext/uniphier/uniphier_image_desc.c @@ -80,7 +80,7 @@ static struct bl_mem_params_node uniphier_image_descs[] = { VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), .ep_info.pc = UNIPHIER_BL33_BASE, - .ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, + .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), .next_handoff_image_id = INVALID_IMAGE_ID, -- cgit v1.2.3 From f8578e641b38694a6a2dee84ef7a7b3b0b50bd0f Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Oct 2018 21:40:18 -0500 Subject: bl31: Split into two separate memory regions Some platforms are extremely memory constrained and must split BL31 between multiple non-contiguous areas in SRAM. Allow the NOBITS sections (.bss, stacks, page tables, and coherent memory) to be placed in a separate region of RAM from the loaded firmware image. Because the NOBITS region may be at a lower address than the rest of BL31, __RW_{START,END}__ and __BL31_{START,END}__ cannot include this region, or el3_entrypoint_common would attempt to invalidate the dcache for the entire address space. New symbols __NOBITS_{START,END}__ are added when SEPARATE_NOBITS_REGION is enabled, and the dcached for the NOBITS region is invalidated separately. Signed-off-by: Samuel Holland Change-Id: Idedfec5e4dbee77e94f2fdd356e6ae6f4dc79d37 --- Makefile | 2 ++ bl31/bl31.ld.S | 40 ++++++++++++++++++++++++++++---- docs/design/firmware-design.rst | 5 ++++ docs/getting_started/build-options.rst | 7 ++++++ include/arch/aarch64/el3_common_macros.S | 8 +++++++ make_helpers/defaults.mk | 4 ++++ 6 files changed, 62 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 073c2ed3e..42fdb7326 100644 --- a/Makefile +++ b/Makefile @@ -736,6 +736,7 @@ $(eval $(call assert_boolean,RAS_EXTENSION)) $(eval $(call assert_boolean,RESET_TO_BL31)) $(eval $(call assert_boolean,SAVE_KEYS)) $(eval $(call assert_boolean,SEPARATE_CODE_AND_RODATA)) +$(eval $(call assert_boolean,SEPARATE_NOBITS_REGION)) $(eval $(call assert_boolean,SPIN_ON_BL1_EXIT)) $(eval $(call assert_boolean,SPM_MM)) $(eval $(call assert_boolean,TRUSTED_BOARD_BOOT)) @@ -800,6 +801,7 @@ $(eval $(call add_define,PSCI_EXTENDED_STATE_ID)) $(eval $(call add_define,RAS_EXTENSION)) $(eval $(call add_define,RESET_TO_BL31)) $(eval $(call add_define,SEPARATE_CODE_AND_RODATA)) +$(eval $(call add_define,SEPARATE_NOBITS_REGION)) $(eval $(call add_define,RECLAIM_INIT_CODE)) $(eval $(call add_define,SPD_${SPD})) $(eval $(call add_define,SPIN_ON_BL1_EXIT)) diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index a598e59cf..42227f0f3 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -15,6 +15,11 @@ ENTRY(bl31_entrypoint) MEMORY { RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE +#if SEPARATE_NOBITS_REGION + NOBITS (rw!a): ORIGIN = BL31_NOBITS_BASE, LENGTH = BL31_NOBITS_LIMIT - BL31_NOBITS_BASE +#else +#define NOBITS RAM +#endif } #ifdef PLAT_EXTRA_LD_SCRIPT @@ -198,11 +203,28 @@ SECTIONS ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") #endif +#if SEPARATE_NOBITS_REGION + /* + * Define a linker symbol to mark end of the RW memory area for this + * image. + */ + __RW_END__ = .; + __BL31_END__ = .; + + ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") + + . = BL31_NOBITS_BASE; + ASSERT(. == ALIGN(PAGE_SIZE), + "BL31 NOBITS base address is not aligned on a page boundary.") + + __NOBITS_START__ = .; +#endif + stacks (NOLOAD) : { __STACKS_START__ = .; *(tzfw_normal_stacks) __STACKS_END__ = .; - } >RAM + } >NOBITS /* * The .bss section gets initialised to 0 at runtime. @@ -262,7 +284,7 @@ SECTIONS __PMF_TIMESTAMP_END__ = .; #endif /* ENABLE_PMF */ __BSS_END__ = .; - } >RAM + } >NOBITS /* * The xlat_table section is for full, aligned page tables (4K). @@ -272,7 +294,7 @@ SECTIONS */ xlat_table (NOLOAD) : { *(xlat_table) - } >RAM + } >NOBITS #if USE_COHERENT_MEM /* @@ -298,9 +320,18 @@ SECTIONS */ . = ALIGN(PAGE_SIZE); __COHERENT_RAM_END__ = .; - } >RAM + } >NOBITS #endif +#if SEPARATE_NOBITS_REGION + /* + * Define a linker symbol to mark end of the NOBITS memory area for this + * image. + */ + __NOBITS_END__ = .; + + ASSERT(. <= BL31_NOBITS_LIMIT, "BL31 NOBITS region has exceeded its limit.") +#else /* * Define a linker symbol to mark end of the RW memory area for this * image. @@ -309,4 +340,5 @@ SECTIONS __BL31_END__ = .; ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") +#endif } diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index cae94b5d8..5fc1335b3 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -1500,6 +1500,11 @@ sections then the resulting binary file would contain zero bytes in place of this NOBITS section, making the image unnecessarily bigger. Smaller images allow faster loading from the FIP to the main memory. +For BL31, a platform can specify an alternate location for NOBITS sections +(other than immediately following PROGBITS sections) by setting +``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and +``BL31_NOBITS_LIMIT``. + Linker scripts and symbols ~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 37c28a5a4..d7bb0449e 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -491,6 +491,13 @@ Common build options pages" section in :ref:`Firmware Design`. This flag is disabled by default and affects all BL images. +- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS + sections of BL31 (.bss, stacks, page tables, and coherent memory) to be + allocated in RAM discontiguous from the loaded firmware image. When set, the + platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and + ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS + sections are placed in RAM immediately following the loaded firmware image. + - ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. This build option is only valid if ``ARCH=aarch64``. The value should be the path to the directory containing the SPD source, relative to diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index b14b7b66e..156b18a4f 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -382,6 +382,14 @@ add x1, x1, :lo12:__RW_END__ sub x1, x1, x0 bl inv_dcache_range +#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION + adrp x0, __NOBITS_START__ + add x0, x0, :lo12:__NOBITS_START__ + adrp x1, __NOBITS_END__ + add x1, x1, :lo12:__NOBITS_END__ + sub x1, x1, x0 + bl inv_dcache_range +#endif #endif adrp x0, __BSS_START__ add x0, x0, :lo12:__BSS_START__ diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index a1f9db9d3..53832c561 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -171,6 +171,10 @@ SDEI_SUPPORT := 0 # platform Makefile is free to override this value. SEPARATE_CODE_AND_RODATA := 0 +# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a +# separate memory region, which may be discontiguous from the rest of BL31. +SEPARATE_NOBITS_REGION := 0 + # If the BL31 image initialisation code is recalimed after use for the secondary # cores stack RECLAIM_INIT_CODE := 0 -- cgit v1.2.3 From ed306a86c5495444a753d6e3e5ceb88cd21053d5 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 27 Oct 2019 14:07:52 -0500 Subject: allwinner: Move the NOBITS region to SRAM A1 This frees up space in SRAM A2 that will be used by the SCP firmware and SCPI shared memory. Signed-off-by: Samuel Holland Change-Id: I8ce035257451e2d142666fe0cd045e59d4d57b35 --- plat/allwinner/common/allwinner-common.mk | 3 +++ plat/allwinner/common/include/platform_def.h | 6 +++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk index 5e8885d7a..af26ec08b 100644 --- a/plat/allwinner/common/allwinner-common.mk +++ b/plat/allwinner/common/allwinner-common.mk @@ -56,6 +56,9 @@ PROGRAMMABLE_RESET_ADDRESS := 1 # Allow mapping read-only data as execute-never. SEPARATE_CODE_AND_RODATA := 1 +# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL. +SEPARATE_NOBITS_REGION := 1 + # BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL RESET_TO_BL31 := 1 diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h index ede3881a7..4de8b0bc4 100644 --- a/plat/allwinner/common/include/platform_def.h +++ b/plat/allwinner/common/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,6 +16,10 @@ #define BL31_BASE SUNXI_SRAM_A2_BASE #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE) +/* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ +#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) +#define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) + /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */ #define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20)) -- cgit v1.2.3 From 252c1d1d4ba29c4cb5173bb2e14d011f018886c2 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 27 Nov 2019 13:09:40 -0600 Subject: allwinner: Remove unused include path Signed-off-by: Samuel Holland Change-Id: Ia2f69e26e34462e113bc2cad4dcb923e20b8fb95 --- plat/allwinner/common/allwinner-common.mk | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk index 5e8885d7a..d28101121 100644 --- a/plat/allwinner/common/allwinner-common.mk +++ b/plat/allwinner/common/allwinner-common.mk @@ -8,8 +8,7 @@ include lib/xlat_tables_v2/xlat_tables.mk AW_PLAT := plat/allwinner -PLAT_INCLUDES := -Iinclude/plat/arm/common \ - -Iinclude/plat/arm/common/aarch64 \ +PLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \ -I${AW_PLAT}/common/include \ -I${AW_PLAT}/${PLAT}/include -- cgit v1.2.3 From 13d33d52ce3e75d2be5a4d2bead31911a3baafa2 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 22 Oct 2019 13:28:51 +0800 Subject: intel: Enable SiP SMC secure register access Enable access to secure registers by non-secure world through secure monitor calls Signed-off-by: Hadi Asyrafi Change-Id: I80610e08c7cf31f17f47a7597c269131a8de2491 --- plat/intel/soc/common/socfpga_sip_svc.c | 107 +++++++++++++++++++++++++++++--- 1 file changed, 97 insertions(+), 10 deletions(-) diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index c3c6ae034..f58b58faf 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "socfpga_mailbox.h" @@ -270,6 +271,79 @@ uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) return INTEL_SIP_SMC_STATUS_OK; } +static int is_out_of_sec_range(uint64_t reg_addr) +{ + switch (reg_addr) { + case(0xF8011100): /* ECCCTRL1 */ + case(0xF8011104): /* ECCCTRL2 */ + case(0xF8011110): /* ERRINTEN */ + case(0xF8011114): /* ERRINTENS */ + case(0xF8011118): /* ERRINTENR */ + case(0xF801111C): /* INTMODE */ + case(0xF8011120): /* INTSTAT */ + case(0xF8011124): /* DIAGINTTEST */ + case(0xF801112C): /* DERRADDRA */ + case(0xFFD12028): /* SDMMCGRP_CTRL */ + case(0xFFD12044): /* EMAC0 */ + case(0xFFD12048): /* EMAC1 */ + case(0xFFD1204C): /* EMAC2 */ + case(0xFFD12090): /* ECC_INT_MASK_VALUE */ + case(0xFFD12094): /* ECC_INT_MASK_SET */ + case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ + case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ + case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ + case(0xFFD120C0): /* NOC_TIMEOUT */ + case(0xFFD120C4): /* NOC_IDLEREQ_SET */ + case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ + case(0xFFD120D0): /* NOC_IDLEACK */ + case(0xFFD120D4): /* NOC_IDLESTATUS */ + case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ + case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ + case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ + case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ + return 0; + + default: + break; + } + + return -1; +} + +/* Secure register access */ +uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) +{ + if (is_out_of_sec_range(reg_addr)) + return INTEL_SIP_SMC_STATUS_ERROR; + + *retval = mmio_read_32(reg_addr); + + return INTEL_SIP_SMC_STATUS_OK; +} + +uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, + uint32_t *retval) +{ + if (is_out_of_sec_range(reg_addr)) + return INTEL_SIP_SMC_STATUS_ERROR; + + mmio_write_32(reg_addr, val); + + return intel_secure_reg_read(reg_addr, retval); +} + +uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, + uint32_t val, uint32_t *retval) +{ + if (!intel_secure_reg_read(reg_addr, retval)) { + *retval &= ~mask; + *retval |= val; + return intel_secure_reg_write(reg_addr, *retval, retval); + } + + return INTEL_SIP_SMC_STATUS_ERROR; +} + /* * This function is responsible for handling all SiP calls from the NS world */ @@ -283,6 +357,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, void *handle, u_register_t flags) { + uint32_t val = 0; uint32_t status = INTEL_SIP_SMC_STATUS_OK; uint32_t completed_addr[3]; uint32_t count = 0; @@ -291,25 +366,25 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, case SIP_SVC_UID: /* Return UID to the caller */ SMC_UUID_RET(handle, intl_svc_uid); - break; + case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: status = intel_mailbox_fpga_config_isdone(); SMC_RET4(handle, status, 0, 0, 0); - break; + case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_ADDR, INTEL_SIP_SMC_FPGA_CONFIG_SIZE - INTEL_SIP_SMC_FPGA_CONFIG_ADDR); - break; + case INTEL_SIP_SMC_FPGA_CONFIG_START: status = intel_fpga_config_start(x1); SMC_RET4(handle, status, 0, 0, 0); - break; + case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: status = intel_fpga_config_write(x1, x2); SMC_RET4(handle, status, 0, 0, 0); - break; + case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: status = intel_fpga_config_completed_write(completed_addr, &count); @@ -317,26 +392,38 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, case 1: SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, completed_addr[0], 0, 0); - break; + case 2: SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, completed_addr[0], completed_addr[1], 0); - break; + case 3: SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, completed_addr[0], completed_addr[1], completed_addr[2]); - break; + case 0: SMC_RET4(handle, status, 0, 0, 0); - break; + default: mailbox_clear_response(); SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); } - break; + + case INTEL_SIP_SMC_REG_READ: + status = intel_secure_reg_read(x1, &val); + SMC_RET3(handle, status, val, x1); + + case INTEL_SIP_SMC_REG_WRITE: + status = intel_secure_reg_write(x1, (uint32_t)x2, &val); + SMC_RET3(handle, status, val, x1); + + case INTEL_SIP_SMC_REG_UPDATE: + status = intel_secure_reg_update(x1, (uint32_t)x2, + (uint32_t)x3, &val); + SMC_RET3(handle, status, val, x1); default: return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, -- cgit v1.2.3 From 32cf34acacd29b2abdf04c4913d9e09a1d194fb8 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 22 Oct 2019 14:23:57 +0800 Subject: intel: Implement platform specific system reset 2 Add support for platform specific warm-reset through psci system reset 2. - system_reset2 implementation that calls for l2 cache reset - Check for magic number and request for warm reset in bl2 - Create a shared reset manager header file for Agilex and Stratix 10 - Clean up parameter info in plat_get_next_bl_params Signed-off-by: Hadi Asyrafi Change-Id: I3fdd9a2711c80d9bd3dc05b81527781d840bd726 --- plat/intel/soc/common/aarch64/plat_helpers.S | 22 +++++++++++++++++ plat/intel/soc/common/include/platform_def.h | 9 +++++++ .../soc/common/include/socfpga_reset_manager.h | 18 ++++++++++++++ plat/intel/soc/common/socfpga_image_load.c | 26 ++++++++++++++++++++ plat/intel/soc/common/socfpga_psci.c | 28 ++++++++++++++++++++++ 5 files changed, 103 insertions(+) create mode 100644 plat/intel/soc/common/include/socfpga_reset_manager.h diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S index 27b538a4f..5cb9b699a 100644 --- a/plat/intel/soc/common/aarch64/plat_helpers.S +++ b/plat/intel/soc/common/aarch64/plat_helpers.S @@ -66,12 +66,34 @@ func plat_my_core_pos ret endfunc plat_my_core_pos +func warm_reset_req + str xzr, [x4] + bl plat_is_my_cpu_primary + cbz x0, cpu_in_wfi + mov_imm x1, PLAT_SEC_ENTRY + str xzr, [x1] + mrs x1, rmr_el3 + orr x1, x1, #0x02 + msr rmr_el3, x1 + isb + dsb sy +cpu_in_wfi: + wfi + b cpu_in_wfi +endfunc warm_reset_req + func plat_get_my_entrypoint + ldr x4, =L2_RESET_DONE_REG + ldr x5, [x4] + ldr x1, =L2_RESET_DONE_STATUS + cmp x1, x5 + b.eq warm_reset_req mov_imm x1, PLAT_SEC_ENTRY ldr x0, [x1] ret endfunc plat_get_my_entrypoint + /* --------------------------------------------- * int plat_crash_console_init(void) * Function to initialize the crash console diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index d6014d392..06f3a1b0d 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -19,6 +19,15 @@ /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ #define PLAT_CPU_RELEASE_ADDR 0xffd12210 +/* + * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset + * is done and HPS should trigger warm reset via RMR_EL3. + */ +#define L2_RESET_DONE_REG 0xFFD12218 + +/* Magic word to indicate L2 reset is completed */ +#define L2_RESET_DONE_STATUS 0x1228E5E7 + /* Define next boot image name and offset */ #define PLAT_NS_IMAGE_OFFSET 0x50000 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 diff --git a/plat/intel/soc/common/include/socfpga_reset_manager.h b/plat/intel/soc/common/include/socfpga_reset_manager.h new file mode 100644 index 000000000..3fbf242f4 --- /dev/null +++ b/plat/intel/soc/common/include/socfpga_reset_manager.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOCFPGA_RESETMANAGER_H +#define SOCFPGA_RESETMANAGER_H + +#define SOCFPGA_RSTMGR_STAT 0xffd11000 +#define SOCFPGA_RSTMGR_HDSKEN 0xffd11010 +#define SOCFPGA_RSTMGR_COLDMODRST 0xffd11034 +#define SOCFPGA_RSTMGR_HDSKTIMEOUT 0xffd11064 + +#define SOCFPGA_RSTMGR_HDSKEN_SET 0x0000010D +#define SOCFPGA_RSTMGR_SDMWARMRST 0x00000002 + +#endif /* SOCFPGA_RESETMANAGER_H */ diff --git a/plat/intel/soc/common/socfpga_image_load.c b/plat/intel/soc/common/socfpga_image_load.c index 67c02bc7d..a5c327990 100644 --- a/plat/intel/soc/common/socfpga_image_load.c +++ b/plat/intel/soc/common/socfpga_image_load.c @@ -28,5 +28,31 @@ bl_load_info_t *plat_get_bl_image_load_info(void) ******************************************************************************/ bl_params_t *plat_get_next_bl_params(void) { + unsigned int count; + unsigned int img_id = 0U; + unsigned int link_index = 0U; + bl_params_node_t *bl_exec_node = NULL; + bl_mem_params_node_t *desc_ptr; + + /* If there is no image to start with, return NULL */ + if (bl_mem_params_desc_num == 0U) + return NULL; + + /* Clean next_params_info in BL image node */ + for (count = 0U; count < bl_mem_params_desc_num; count++) { + + desc_ptr = &bl_mem_params_desc_ptr[link_index]; + bl_exec_node = &desc_ptr->params_node_mem; + bl_exec_node->next_params_info = NULL; + + /* If no next hand-off image then break out */ + img_id = desc_ptr->next_handoff_image_id; + if (img_id == INVALID_IMAGE_ID) + break; + + /* Get the index for the next hand-off image */ + link_index = get_bl_params_node_index(img_id); + } + return get_next_bl_params_from_mem_params_desc(); } diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c index 65a4b0929..1ba48eae1 100644 --- a/plat/intel/soc/common/socfpga_psci.c +++ b/plat/intel/soc/common/socfpga_psci.c @@ -13,6 +13,7 @@ #include "socfpga_mailbox.h" #include "socfpga_plat_def.h" +#include "socfpga_reset_manager.h" @@ -75,6 +76,7 @@ void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state) for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); + /* assert core reset */ mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); @@ -136,6 +138,31 @@ static void __dead2 socfpga_system_reset(void) wfi(); } +static int socfpga_system_reset2(int is_vendor, int reset_type, + u_register_t cookie) +{ + /* disable cpuif */ + gicv2_cpuif_disable(); + + /* Store magic number */ + mmio_write_32(L2_RESET_DONE_REG, L2_RESET_DONE_STATUS); + + /* Increase timeout */ + mmio_write_32(SOCFPGA_RSTMGR_HDSKTIMEOUT, 0xffffff); + + /* Enable handshakes */ + mmio_setbits_32(SOCFPGA_RSTMGR_HDSKEN, SOCFPGA_RSTMGR_HDSKEN_SET); + + /* Reset L2 module */ + mmio_setbits_32(SOCFPGA_RSTMGR_COLDMODRST, 0x100); + + while (1) + wfi(); + + /* Should not reach here */ + return 0; +} + int socfpga_validate_power_state(unsigned int power_state, psci_power_state_t *req_state) { @@ -169,6 +196,7 @@ const plat_psci_ops_t socfpga_psci_pm_ops = { .pwr_domain_suspend_finish = socfpga_pwr_domain_suspend_finish, .system_off = socfpga_system_off, .system_reset = socfpga_system_reset, + .system_reset2 = socfpga_system_reset2, .validate_power_state = socfpga_validate_power_state, .validate_ns_entrypoint = socfpga_validate_ns_entrypoint, .get_sys_suspend_power_state = socfpga_get_sys_suspend_power_state -- cgit v1.2.3 From 3d9f726438bea5fe0eb2a88b54d2c6c29b026b93 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Wed, 16 Oct 2019 13:02:22 +0800 Subject: intel: Fix memory calibration Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by: Hadi Asyrafi Change-Id: I1a50a5d8a6518ba085d853cb636efa07326552b4 --- plat/intel/soc/agilex/soc/agilex_memory_controller.c | 7 +++---- plat/intel/soc/stratix10/soc/s10_memory_controller.c | 13 ++++++------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/plat/intel/soc/agilex/soc/agilex_memory_controller.c b/plat/intel/soc/agilex/soc/agilex_memory_controller.c index 5f3cae7be..2aabe87cc 100644 --- a/plat/intel/soc/agilex/soc/agilex_memory_controller.c +++ b/plat/intel/soc/agilex/soc/agilex_memory_controller.c @@ -20,9 +20,8 @@ #define PRE_CALIBRATION_DELAY 1 #define POST_CALIBRATION_DELAY 1 #define TIMEOUT_EMIF_CALIBRATION 1000 -#define CLEAR_EMIF_DELAY 50000 -#define CLEAR_EMIF_TIMEOUT 0x100000 -#define TIMEOUT_INT_RESP 10000 +#define CLEAR_EMIF_DELAY 1000 +#define CLEAR_EMIF_TIMEOUT 1000 #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) #define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t)) @@ -125,7 +124,7 @@ static int mem_calibration(void) data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRCALSTAT); if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1) break; - mdelay(1); + udelay(500); } while (++timeout < TIMEOUT_EMIF_CALIBRATION); if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { diff --git a/plat/intel/soc/stratix10/soc/s10_memory_controller.c b/plat/intel/soc/stratix10/soc/s10_memory_controller.c index ed06f5498..cb4525149 100644 --- a/plat/intel/soc/stratix10/soc/s10_memory_controller.c +++ b/plat/intel/soc/stratix10/soc/s10_memory_controller.c @@ -22,10 +22,9 @@ #define MAX_MEM_CAL_RETRY 3 #define PRE_CALIBRATION_DELAY 1 #define POST_CALIBRATION_DELAY 1 -#define TIMEOUT_EMIF_CALIBRATION 100 -#define CLEAR_EMIF_DELAY 50000 -#define CLEAR_EMIF_TIMEOUT 0x100000 -#define TIMEOUT_INT_RESP 10000 +#define TIMEOUT_EMIF_CALIBRATION 1000 +#define CLEAR_EMIF_DELAY 1000 +#define CLEAR_EMIF_TIMEOUT 1000 #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) #define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t)) @@ -128,13 +127,13 @@ static int mem_calibration(void) data = mmio_read_32(S10_MPFE_HMC_ADP_DDRCALSTAT); if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1) break; - udelay(1); + udelay(500); } while (++timeout < TIMEOUT_EMIF_CALIBRATION); if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { status = clear_emif(); - if (status) - ERROR("Failed to clear Emif\n"); + if (status) + ERROR("Failed to clear Emif\n"); } else { break; } -- cgit v1.2.3 From cd50ffd2fcbebc47173174151919333960ebe732 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 12 Dec 2019 12:00:15 +0000 Subject: console: 16550: Prepare for skipping initialisation On some platforms the UART might have already been initialised, for instance by firmware running before TF-A or by a separate management processor. In this case it would not be need to initialise it again (doing so could create spurious characters). But more importantly this saves us from knowing the right baudrate and the right base clock rate for the UART. This can lead to more robust and versatile firmware builds. Allow to skip the 16550 UART initialisation and baud rate divisor programming, by interpreting an input clock rate of "0" to signify this case. This will just skip the call to console_16550_core_init, but still will register the console properly. Users should just pass 0 as the second parameter, the baudrate (third parameter) will then be ignored as well. Fix copy & paste typos in comments for the console_16550_register() function on the way. Signed-off-by: Andre Przywara Change-Id: I9f8fca5b358f878fac0f31dc411358fd160786ee --- drivers/ti/uart/aarch32/16550_console.S | 18 +++++++++++++----- drivers/ti/uart/aarch64/16550_console.S | 9 ++++++++- include/drivers/ti/uart/uart_16550.h | 5 +++++ 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/ti/uart/aarch32/16550_console.S b/drivers/ti/uart/aarch32/16550_console.S index 692188412..5cd9b30cd 100644 --- a/drivers/ti/uart/aarch32/16550_console.S +++ b/drivers/ti/uart/aarch32/16550_console.S @@ -89,16 +89,19 @@ endfunc console_16550_core_init .globl console_16550_register /* ------------------------------------------------------- - * int console_stm32_register(uintptr_t baseaddr, + * int console_16550_register(uintptr_t baseaddr, * uint32_t clock, uint32_t baud, - * struct console_stm32 *console); - * Function to initialize and register a new STM32 + * console_16550_t *console); + * Function to initialize and register a new 16550 * console. Storage passed in for the console struct * *must* be persistent (i.e. not from the stack). + * If r1 (UART clock) is 0, initialisation will be + * skipped, relying on previous code to have done + * this already. r2 is ignored then as well. * In: r0 - UART register base address * r1 - UART clock in Hz - * r2 - Baud rate - * r3 - pointer to empty console_stm32 struct + * r2 - Baud rate (ignored if r1 is 0) + * r3 - pointer to empty console_16550_t struct * Out: return 1 on success, 0 on error * Clobber list : r0, r1, r2 * ------------------------------------------------------- @@ -110,10 +113,15 @@ func console_16550_register beq register_fail str r0, [r4, #CONSOLE_T_16550_BASE] + /* A clock rate of zero means to skip the initialisation. */ + cmp r1, #0 + beq register_16550 + bl console_16550_core_init cmp r0, #0 beq register_fail +register_16550: mov r0, r4 pop {r4, lr} finish_console_register 16550 putc=1, getc=1, flush=1 diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S index dab46e8c5..80c1b8646 100644 --- a/drivers/ti/uart/aarch64/16550_console.S +++ b/drivers/ti/uart/aarch64/16550_console.S @@ -92,9 +92,12 @@ endfunc console_16550_core_init * Function to initialize and register a new 16550 * console. Storage passed in for the console struct * *must* be persistent (i.e. not from the stack). + * If w1 (UART clock) is 0, initialisation will be + * skipped, relying on previous code to have done + * this already. w2 is ignored then as well. * In: x0 - UART register base address * w1 - UART clock in Hz - * w2 - Baud rate + * w2 - Baud rate (ignored if w1 is 0) * x3 - pointer to empty console_16550_t struct * Out: return 1 on success, 0 on error * Clobber list : x0, x1, x2, x6, x7, x14 @@ -106,9 +109,13 @@ func console_16550_register cbz x6, register_fail str x0, [x6, #CONSOLE_T_16550_BASE] + /* A clock rate of zero means to skip the initialisation. */ + cbz w1, register_16550 + bl console_16550_core_init cbz x0, register_fail +register_16550: mov x0, x6 mov x30, x7 finish_console_register 16550 putc=1, getc=1, flush=1 diff --git a/include/drivers/ti/uart/uart_16550.h b/include/drivers/ti/uart/uart_16550.h index 32e38f0ac..2b95fa33a 100644 --- a/include/drivers/ti/uart/uart_16550.h +++ b/include/drivers/ti/uart/uart_16550.h @@ -87,6 +87,11 @@ typedef struct { * framework. The |console| pointer must point to storage that will be valid * for the lifetime of the console, such as a global or static local variable. * Its contents will be reinitialized from scratch. + * When |clock| has a value of 0, the UART will *not* be initialised. This + * means the UART should already be enabled and the baudrate and clock setup + * should have been done already, either by platform specific code or by + * previous firmware stages. The |baud| parameter will be ignored in this + * case as well. */ int console_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_16550_t *console); -- cgit v1.2.3 From 0eda713b9bd65222155900aacf3a67805351f88f Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 12 Dec 2019 16:31:11 +0000 Subject: plat: rpi4: Skip UART initialisation So far we have seen two different clock setups for the Raspberry Pi 4 board, with the VPU clock divider being different. This was handled by reading the divider register and adjusting the base clock rate accordingly. Recently a new GPU firmware version appeared that changed the clock rate *again*, though this time at a higher level, so the VPU rate (and the apparent PLLC parent clock) did not seem to change, judging by reading the clock registers. So rather than playing cat and mouse with the GPU firmware or going further down the rabbit hole of exploring the whole clock tree, let's just skip the baud rate programming altogether. This works because the GPU firmware actually sets up and programs the debug UART already, so we can just use it. Pass 0 as the base clock rate to let the console driver skip the setup, also remove the no longer needed clock code. Signed-off-by: Andre Przywara Change-Id: Ica88a3f3c9c11059357c1e6dd8f7a4d9b1f98fd7 --- plat/rpi/rpi4/aarch64/plat_helpers.S | 4 ++-- plat/rpi/rpi4/include/rpi_hw.h | 8 -------- plat/rpi/rpi4/rpi4_bl31_setup.c | 16 +++++----------- 3 files changed, 7 insertions(+), 21 deletions(-) diff --git a/plat/rpi/rpi4/aarch64/plat_helpers.S b/plat/rpi/rpi4/aarch64/plat_helpers.S index 46073b791..083c30e71 100644 --- a/plat/rpi/rpi4/aarch64/plat_helpers.S +++ b/plat/rpi/rpi4/aarch64/plat_helpers.S @@ -136,8 +136,8 @@ endfunc platform_mem_init */ func plat_crash_console_init mov_imm x0, PLAT_RPI3_UART_BASE - mov_imm x1, PLAT_RPI4_VPU_CLK_RATE - mov_imm x2, PLAT_RPI3_UART_BAUDRATE + mov x1, xzr + mov x2, xzr b console_16550_core_init endfunc plat_crash_console_init diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h index ed367ee20..b1dd4e92e 100644 --- a/plat/rpi/rpi4/include/rpi_hw.h +++ b/plat/rpi/rpi4/include/rpi_hw.h @@ -58,13 +58,6 @@ */ #define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) -/* - * Clock controller - */ -#define RPI4_IO_CLOCK_OFFSET ULL(0x00101000) -#define RPI4_CLOCK_BASE (RPI_IO_BASE + RPI4_IO_CLOCK_OFFSET) -#define RPI4_VPU_CLOCK_DIVIDER ULL(0x0000000c) - /* * Hardware random number generator. */ @@ -88,7 +81,6 @@ */ #define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) #define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET) -#define PLAT_RPI4_VPU_CLK_RATE ULL(1000000000) /* * GPIO controller diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c index 53ab0c2e2..9e3b53979 100644 --- a/plat/rpi/rpi4/rpi4_bl31_setup.c +++ b/plat/rpi/rpi4/rpi4_bl31_setup.c @@ -119,8 +119,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - uint32_t div_reg; - /* * LOCAL_CONTROL: * Bit 9 clear: Increment by 1 (vs. 2). @@ -136,16 +134,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, /* * Initialize the console to provide early debug support. - * Different GPU firmware revisions set up the VPU divider differently, - * so read the actual divider register to learn the UART base clock - * rate. The divider is encoded as a 12.12 fixed point number, but we - * just care about the integer part of it. + * We rely on the GPU firmware to have initialised the UART correctly, + * as the baud base clock rate differs across GPU firmware revisions. + * Providing a base clock of 0 lets the 16550 UART init routine skip + * the initial enablement and baud rate setup. */ - div_reg = mmio_read_32(RPI4_CLOCK_BASE + RPI4_VPU_CLOCK_DIVIDER); - div_reg = (div_reg >> 12) & 0xfff; - if (div_reg == 0) - div_reg = 1; - rpi3_console_init(PLAT_RPI4_VPU_CLK_RATE / div_reg); + rpi3_console_init(0); bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry(); -- cgit v1.2.3 From 8c80c86573898eb59127a32b089e753f40e254fb Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 2 Jan 2020 11:09:03 +0100 Subject: compiler_rt: Import aeabi_ldivmode.S file and dependencies Import aeabi_ldivmod.S with divmoddi4.c and divdi3.c from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). This is to get the __aeabi_ldivmod builtin, which is required by a patch using signed long long division. Change-Id: Iee4c421deb3175142655e19074cd3732edd82227 Signed-off-by: Lionel Debieve --- lib/compiler-rt/builtins/arm/aeabi_ldivmod.S | 46 ++++++++++++++++++++++++++++ lib/compiler-rt/builtins/divdi3.c | 29 ++++++++++++++++++ lib/compiler-rt/builtins/divmoddi4.c | 25 +++++++++++++++ lib/compiler-rt/compiler-rt.mk | 11 ++++--- 4 files changed, 107 insertions(+), 4 deletions(-) create mode 100644 lib/compiler-rt/builtins/arm/aeabi_ldivmod.S create mode 100644 lib/compiler-rt/builtins/divdi3.c create mode 100644 lib/compiler-rt/builtins/divmoddi4.c diff --git a/lib/compiler-rt/builtins/arm/aeabi_ldivmod.S b/lib/compiler-rt/builtins/arm/aeabi_ldivmod.S new file mode 100644 index 000000000..038ae5d72 --- /dev/null +++ b/lib/compiler-rt/builtins/arm/aeabi_ldivmod.S @@ -0,0 +1,46 @@ +//===-- aeabi_ldivmod.S - EABI ldivmod implementation ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is dual licensed under the MIT and the University of Illinois Open +// Source Licenses. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "../assembly.h" + +// struct { int64_t quot, int64_t rem} +// __aeabi_ldivmod(int64_t numerator, int64_t denominator) { +// int64_t rem, quot; +// quot = __divmoddi4(numerator, denominator, &rem); +// return {quot, rem}; +// } + +#if defined(__MINGW32__) +#define __aeabi_ldivmod __rt_sdiv64 +#endif + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_ldivmod) + push {r6, lr} + sub sp, sp, #16 + add r6, sp, #8 + str r6, [sp] +#if defined(__MINGW32__) + movs r6, r0 + movs r0, r2 + movs r2, r6 + movs r6, r1 + movs r1, r3 + movs r3, r6 +#endif + bl SYMBOL_NAME(__divmoddi4) + ldr r2, [sp, #8] + ldr r3, [sp, #12] + add sp, sp, #16 + pop {r6, pc} +END_COMPILERRT_FUNCTION(__aeabi_ldivmod) + +NO_EXEC_STACK_DIRECTIVE + diff --git a/lib/compiler-rt/builtins/divdi3.c b/lib/compiler-rt/builtins/divdi3.c new file mode 100644 index 000000000..b8eebcb20 --- /dev/null +++ b/lib/compiler-rt/builtins/divdi3.c @@ -0,0 +1,29 @@ +/* ===-- divdi3.c - Implement __divdi3 -------------------------------------=== + * + * The LLVM Compiler Infrastructure + * + * This file is dual licensed under the MIT and the University of Illinois Open + * Source Licenses. See LICENSE.TXT for details. + * + * ===----------------------------------------------------------------------=== + * + * This file implements __divdi3 for the compiler_rt library. + * + * ===----------------------------------------------------------------------=== + */ + +#include "int_lib.h" + +/* Returns: a / b */ + +COMPILER_RT_ABI di_int +__divdi3(di_int a, di_int b) +{ + const int bits_in_dword_m1 = (int)(sizeof(di_int) * CHAR_BIT) - 1; + di_int s_a = a >> bits_in_dword_m1; /* s_a = a < 0 ? -1 : 0 */ + di_int s_b = b >> bits_in_dword_m1; /* s_b = b < 0 ? -1 : 0 */ + a = (a ^ s_a) - s_a; /* negate if s_a == -1 */ + b = (b ^ s_b) - s_b; /* negate if s_b == -1 */ + s_a ^= s_b; /*sign of quotient */ + return (__udivmoddi4(a, b, (du_int*)0) ^ s_a) - s_a; /* negate if s_a == -1 */ +} diff --git a/lib/compiler-rt/builtins/divmoddi4.c b/lib/compiler-rt/builtins/divmoddi4.c new file mode 100644 index 000000000..0d4df67a6 --- /dev/null +++ b/lib/compiler-rt/builtins/divmoddi4.c @@ -0,0 +1,25 @@ +/*===-- divmoddi4.c - Implement __divmoddi4 --------------------------------=== + * + * The LLVM Compiler Infrastructure + * + * This file is dual licensed under the MIT and the University of Illinois Open + * Source Licenses. See LICENSE.TXT for details. + * + * ===----------------------------------------------------------------------=== + * + * This file implements __divmoddi4 for the compiler_rt library. + * + * ===----------------------------------------------------------------------=== + */ + +#include "int_lib.h" + +/* Returns: a / b, *rem = a % b */ + +COMPILER_RT_ABI di_int +__divmoddi4(di_int a, di_int b, di_int* rem) +{ + di_int d = __divdi3(a,b); + *rem = a - (d*b); + return d; +} diff --git a/lib/compiler-rt/compiler-rt.mk b/lib/compiler-rt/compiler-rt.mk index 49e497eb8..1ffc9d678 100644 --- a/lib/compiler-rt/compiler-rt.mk +++ b/lib/compiler-rt/compiler-rt.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -29,8 +29,11 @@ # ifeq (${ARCH},aarch32) -COMPILER_RT_SRCS := lib/compiler-rt/builtins/arm/aeabi_uldivmod.S \ - lib/compiler-rt/builtins/udivmoddi4.c \ +COMPILER_RT_SRCS := lib/compiler-rt/builtins/arm/aeabi_ldivmod.S \ + lib/compiler-rt/builtins/arm/aeabi_uldivmod.S \ lib/compiler-rt/builtins/ctzdi2.c \ - lib/compiler-rt/builtins/lshrdi3.c + lib/compiler-rt/builtins/divdi3.c \ + lib/compiler-rt/builtins/divmoddi4.c \ + lib/compiler-rt/builtins/lshrdi3.c \ + lib/compiler-rt/builtins/udivmoddi4.c endif -- cgit v1.2.3 From de9bf1d8a2de952bfc17cdf7082b41f9c185e54d Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Thu, 2 Jan 2020 17:11:22 -0600 Subject: GCC: Upgrade to version 9.2-2019.12 of toolchain This toolchain provides multiple cross compilers and are publicly available on www.developer.arm.com We thoroughly test TF-A in CI using: AArch32 bare-metal target (arm-none-eabi) AArch64 ELF bare-metal target (aarch64-none-elf) Change-Id: I2360a3ac6705c68dca781b85e9894867df255b3e Signed-off-by: Madhukar Pappireddy --- docs/getting_started/initial-build.rst | 8 ++++---- docs/getting_started/prerequisites.rst | 2 +- docs/plat/allwinner.rst | 4 ++-- docs/plat/arm/fvp/index.rst | 2 +- docs/plat/arm/juno/index.rst | 2 +- docs/plat/hikey.rst | 2 +- docs/plat/imx8.rst | 2 +- docs/plat/imx8m.rst | 2 +- docs/plat/intel-agilex.rst | 2 +- docs/plat/intel-stratix10.rst | 2 +- docs/plat/ls1043a.rst | 4 ++-- docs/plat/marvell/build.rst | 2 +- docs/plat/meson-g12a.rst | 2 +- docs/plat/meson-gxbb.rst | 2 +- docs/plat/meson-gxl.rst | 2 +- docs/plat/mt8183.rst | 2 +- docs/plat/poplar.rst | 2 +- docs/plat/qemu-sbsa.rst | 2 +- docs/plat/rockchip.rst | 2 +- docs/plat/rpi3.rst | 8 ++++---- docs/plat/rpi4.rst | 2 +- docs/plat/ti-k3.rst | 2 +- 22 files changed, 30 insertions(+), 30 deletions(-) diff --git a/docs/getting_started/initial-build.rst b/docs/getting_started/initial-build.rst index 41cd4d1c9..893aba245 100644 --- a/docs/getting_started/initial-build.rst +++ b/docs/getting_started/initial-build.rst @@ -8,13 +8,13 @@ Performing an Initial Build .. code:: shell - export CROSS_COMPILE=/bin/aarch64-linux-gnu- + export CROSS_COMPILE=/bin/aarch64-none-elf- For AArch32: .. code:: shell - export CROSS_COMPILE=/bin/arm-eabi- + export CROSS_COMPILE=/bin/arm-none-eabi- It is possible to build TF-A using Clang or Arm Compiler 6. To do so ``CC`` needs to point to the clang or armclang binary, which will @@ -32,7 +32,7 @@ Performing an Initial Build .. code:: shell - export CROSS_COMPILE=/bin/aarch64-linux-gnu- + export CROSS_COMPILE=/bin/aarch64-none-elf- make CC=/bin/armclang PLAT= all Clang will be selected when the base name of the path assigned to ``CC`` @@ -43,7 +43,7 @@ Performing an Initial Build .. code:: shell - export CROSS_COMPILE=/bin/aarch64-linux-gnu- + export CROSS_COMPILE=/bin/aarch64-none-elf- make CC=/bin/clang PLAT= all - Change to the root directory of the TF-A source tree and build. diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst index 27ad0ed5f..3e0c8fff2 100644 --- a/docs/getting_started/prerequisites.rst +++ b/docs/getting_started/prerequisites.rst @@ -26,7 +26,7 @@ Toolchain |TF-A| can be built with any of the following *cross-compiler* toolchains that target the Armv7-A or Armv8-A architectures: -- GCC >= 8.3-2019.03 (from the `Arm Developer website`_) +- GCC >= 9.2-2019.12 (from the `Arm Developer website`_) - Clang >= 4.0 - Arm Compiler >= 6.0 diff --git a/docs/plat/allwinner.rst b/docs/plat/allwinner.rst index a1e06590a..5c905d86b 100644 --- a/docs/plat/allwinner.rst +++ b/docs/plat/allwinner.rst @@ -26,13 +26,13 @@ To build for machines with an A64 or H5 SoC: .. code:: shell - make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31 + make CROSS_COMPILE=aarch64-none-elf- PLAT=sun50i_a64 DEBUG=1 bl31 To build for machines with an H6 SoC: .. code:: shell - make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31 + make CROSS_COMPILE=aarch64-none-elf- PLAT=sun50i_h6 DEBUG=1 bl31 .. _U-Boot documentation: http://git.denx.de/?p=u-boot.git;f=board/sunxi/README.sunxi64;hb=HEAD diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index b6396b97c..37010e1a5 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -223,7 +223,7 @@ address ``0x82000000``, the firmware can be built like this: .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- \ + CROSS_COMPILE=aarch64-none-elf- \ make PLAT=fvp DEBUG=1 \ RESET_TO_BL31=1 \ ARM_LINUX_KERNEL_AS_BL33=1 \ diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst index 6429ede7a..cf328fac9 100644 --- a/docs/plat/arm/juno/index.rst +++ b/docs/plat/arm/juno/index.rst @@ -136,7 +136,7 @@ a single FIP binary. It assumes that a Linaro release has been installed. .. code:: shell - export CROSS_COMPILE=/bin/aarch64-linux-gnu- + export CROSS_COMPILE=/bin/aarch64-none-elf- - The following parameters should be used to build BL1 and BL2 in AArch64 and point to the BL32 file. diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst index 372d38867..d7a01a881 100644 --- a/docs/plat/hikey.rst +++ b/docs/plat/hikey.rst @@ -78,7 +78,7 @@ Build Procedure EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey/${BUILD_OPTION}_${AARCH64_TOOLCHAIN} # Build fastboot for Trusted Firmware-A. It's used for recovery mode. cd ${BUILD_PATH}/atf-fastboot - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=hikey DEBUG=1 + CROSS_COMPILE=aarch64-none-elf- make PLAT=hikey DEBUG=1 # Convert DEBUG/RELEASE to debug/release FASTBOOT_BUILD_OPTION=$(echo ${BUILD_OPTION} | tr '[A-Z]' '[a-z]') cd ${EDK2_DIR} diff --git a/docs/plat/imx8.rst b/docs/plat/imx8.rst index 49ba37412..cec1a39d8 100644 --- a/docs/plat/imx8.rst +++ b/docs/plat/imx8.rst @@ -40,7 +40,7 @@ Build Procedure .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make PLAT= bl31 + CROSS_COMPILE=aarch64-none-elf- make PLAT= bl31 Target_SoC should be "imx8qm" for i.MX8QM SoC. Target_SoC should be "imx8qx" for i.MX8QX SoC. diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst index 8acd13cf7..0116b34a9 100644 --- a/docs/plat/imx8m.rst +++ b/docs/plat/imx8m.rst @@ -28,7 +28,7 @@ Build Procedure .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make PLAT= bl31 + CROSS_COMPILE=aarch64-none-elf- make PLAT= bl31 Target_SoC should be "imx8mq" for i.MX8MQ SoC. Target_SoC should be "imx8mm" for i.MX8MM SoC. diff --git a/docs/plat/intel-agilex.rst b/docs/plat/intel-agilex.rst index ff27b6b5f..f60bf14ad 100644 --- a/docs/plat/intel-agilex.rst +++ b/docs/plat/intel-agilex.rst @@ -41,7 +41,7 @@ Build Procedure .. code:: bash - make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=agilex + make CROSS_COMPILE=aarch64-none-elf- bl2 fip PLAT=agilex BL33=PEI.ROM Install Procedure diff --git a/docs/plat/intel-stratix10.rst b/docs/plat/intel-stratix10.rst index 7f8d18e03..5f33d12de 100644 --- a/docs/plat/intel-stratix10.rst +++ b/docs/plat/intel-stratix10.rst @@ -41,7 +41,7 @@ Build Procedure .. code:: bash - make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=stratix10 + make CROSS_COMPILE=aarch64-none-elf- bl2 fip PLAT=stratix10 BL33=PEI.ROM Install Procedure diff --git a/docs/plat/ls1043a.rst b/docs/plat/ls1043a.rst index 72a51f3cc..5a8f7558f 100644 --- a/docs/plat/ls1043a.rst +++ b/docs/plat/ls1043a.rst @@ -59,13 +59,13 @@ Build Procedure .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 bl1 + CROSS_COMPILE=aarch64-none-elf- make PLAT=ls1043 bl1 Build fip: .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 fip \ + CROSS_COMPILE=aarch64-none-elf- make PLAT=ls1043 fip \ BL33=u-boot.bin NEED_BL32=yes BL32=tee.bin SPD=opteed Deploy TF-A Images diff --git a/docs/plat/marvell/build.rst b/docs/plat/marvell/build.rst index c10bcff79..d0e37c683 100644 --- a/docs/plat/marvell/build.rst +++ b/docs/plat/marvell/build.rst @@ -9,7 +9,7 @@ Build Instructions .. code:: shell - > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu- + > export CROSS_COMPILE=/path/to/toolchain/aarch64-none-elf- (2) Set path for FIP images: diff --git a/docs/plat/meson-g12a.rst b/docs/plat/meson-g12a.rst index 7cd1bf746..8b06cc287 100644 --- a/docs/plat/meson-g12a.rst +++ b/docs/plat/meson-g12a.rst @@ -17,7 +17,7 @@ In order to build it: .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=g12a + CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=g12a This port has been tested on a SEI510 board. After building it, follow the instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the diff --git a/docs/plat/meson-gxbb.rst b/docs/plat/meson-gxbb.rst index 2cd8342cb..f891ecd81 100644 --- a/docs/plat/meson-gxbb.rst +++ b/docs/plat/meson-gxbb.rst @@ -17,7 +17,7 @@ In order to build it: .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxbb bl31 + CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=gxbb bl31 This port has been tested in a ODROID-C2. After building it, follow the instructions in the `U-Boot repository`_, replacing the mentioned **bl31.bin** diff --git a/docs/plat/meson-gxl.rst b/docs/plat/meson-gxl.rst index c6d850446..170d7c774 100644 --- a/docs/plat/meson-gxl.rst +++ b/docs/plat/meson-gxl.rst @@ -17,7 +17,7 @@ In order to build it: .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxl + CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=gxl This port has been tested on a Lepotato. After building it, follow the instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the diff --git a/docs/plat/mt8183.rst b/docs/plat/mt8183.rst index c639be1ee..7a0830f08 100644 --- a/docs/plat/mt8183.rst +++ b/docs/plat/mt8183.rst @@ -17,4 +17,4 @@ How to Build .. code:: shell - make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8183 DEBUG=1 + make CROSS_COMPILE=aarch64-none-elf- PLAT=mt8183 DEBUG=1 diff --git a/docs/plat/poplar.rst b/docs/plat/poplar.rst index 215f55142..040b59396 100644 --- a/docs/plat/poplar.rst +++ b/docs/plat/poplar.rst @@ -68,7 +68,7 @@ Build Procedure .. code:: bash - make CROSS_COMPILE=aarch64-linux-gnu- all fip SPD=none PLAT=poplar + make CROSS_COMPILE=aarch64-none-elf- all fip SPD=none PLAT=poplar BL33=u-boot.bin - Build l-loader (generated the final fastboot.bin) diff --git a/docs/plat/qemu-sbsa.rst b/docs/plat/qemu-sbsa.rst index 51fe41404..5e8535c72 100644 --- a/docs/plat/qemu-sbsa.rst +++ b/docs/plat/qemu-sbsa.rst @@ -27,7 +27,7 @@ To build TF-A: git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa cd tfa - export CROSS_COMPILE=aarch64-linux-gnu- + export CROSS_COMPILE=aarch64-none-elf- make PLAT=qemu_sbsa all fip Images will be placed at build/qemu_sbsa/release (bl1.bin and fip.bin). diff --git a/docs/plat/rockchip.rst b/docs/plat/rockchip.rst index b7c43fbe1..2c3c38fb5 100644 --- a/docs/plat/rockchip.rst +++ b/docs/plat/rockchip.rst @@ -35,7 +35,7 @@ these images need to get build from the TF-A repository. For AARCH64 architectures the build command looks like - make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl32 + make CROSS_COMPILE=aarch64-none-elf- PLAT=rk3399 bl32 while AARCH32 needs a slightly different command diff --git a/docs/plat/rpi3.rst b/docs/plat/rpi3.rst index 38c3dfa82..5c7b6d5dd 100644 --- a/docs/plat/rpi3.rst +++ b/docs/plat/rpi3.rst @@ -315,7 +315,7 @@ Then compile TF-A. For a 32-bit kernel, use the following command line: .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \ + CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \ RPI3_BL33_IN_AARCH32=1 \ BL33=../rpi3-arm-tf-bootstrap/aarch32/el2-bootstrap.bin @@ -323,7 +323,7 @@ For a 64-bit kernel, use this other command line: .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \ + CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \ BL33=../rpi3-arm-tf-bootstrap/aarch64/el2-bootstrap.bin However, enabling PSCI support in a 64-bit kernel is really easy. In the @@ -340,7 +340,7 @@ For a 64-bit kernel: .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \ + CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \ PRELOADED_BL33_BASE=0x02000000 \ RPI3_PRELOADED_DTB_BASE=0x01000000 \ RPI3_DIRECT_LINUX_BOOT=1 @@ -349,7 +349,7 @@ For a 32-bit kernel: .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \ + CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \ PRELOADED_BL33_BASE=0x02000000 \ RPI3_PRELOADED_DTB_BASE=0x01000000 \ RPI3_DIRECT_LINUX_BOOT=1 \ diff --git a/docs/plat/rpi4.rst b/docs/plat/rpi4.rst index 0f529c103..e87aef71a 100644 --- a/docs/plat/rpi4.rst +++ b/docs/plat/rpi4.rst @@ -22,7 +22,7 @@ one universal binary (bl31.bin), which can be built with: .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi4 DEBUG=1 + CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi4 DEBUG=1 Copy the generated build/rpi4/debug/bl31.bin to the SD card, either renaming it to ``armstub8.bin`` or adding an entry starting with ``armstub=``, diff --git a/docs/plat/ti-k3.rst b/docs/plat/ti-k3.rst index 4843227df..2626e6741 100644 --- a/docs/plat/ti-k3.rst +++ b/docs/plat/ti-k3.rst @@ -27,7 +27,7 @@ TF-A: .. code:: shell - make CROSS_COMPILE=aarch64-linux-gnu- PLAT=k3 SPD=opteed all + make CROSS_COMPILE=aarch64-none-elf- PLAT=k3 SPD=opteed all OP-TEE: -- cgit v1.2.3 From c20c05252c755ed0805f38f93201c4d582af0516 Mon Sep 17 00:00:00 2001 From: Vishnu Banavath Date: Fri, 13 Dec 2019 17:18:15 +0000 Subject: drivers: add a driver for snoop control unit The SCU connects one to four Cortex-A5/Cortex-A9 processors to the memory system through the AXI interfaces. The SCU functions are to: - maintain data cache coherency between the Cortex-A5/Cortex-A9 processors - initiate L2 AXI memory accesses - arbitrate between Cortex-A5/Cortex-A9 processors requesting L2 accesses - manage ACP accesses. Snoop Control Unit will enable to snoop on other CPUs caches. This is very important when it comes to synchronizing data between CPUs. As an example, there is a high chance that data might be cache'd and other CPUs can't see the change. In such cases, if snoop control unit is enabled, data is synchoronized immediately between CPUs and the changes are visible to other CPUs. This driver provides functionality to enable SCU as well as enabling user to know the following - number of CPUs present - is a particular CPU operating in SMP mode or AMP mode - data cache size of a particular CPU - does SCU has ACP port - is L2CPRESENT Change-Id: I0d977970154fa60df57caf449200d471f02312a0 Signed-off-by: Vishnu Banavath --- drivers/arm/scu/scu.c | 51 ++++++++++++++++++++++++++ include/drivers/arm/scu.h | 20 ++++++++++ plat/arm/board/a5ds/a5ds_pm.c | 3 +- plat/arm/board/a5ds/include/platform_def.h | 3 ++ plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c | 5 +++ plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk | 3 +- 6 files changed, 82 insertions(+), 3 deletions(-) create mode 100644 drivers/arm/scu/scu.c create mode 100644 include/drivers/arm/scu.h diff --git a/drivers/arm/scu/scu.c b/drivers/arm/scu/scu.c new file mode 100644 index 000000000..aceac92fa --- /dev/null +++ b/drivers/arm/scu/scu.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +/******************************************************************************* + * Turn ON snoop control unit. This is needed to synchronize the data between + * CPU's. + ******************************************************************************/ +void enable_snoop_ctrl_unit(uintptr_t base) +{ + uint32_t scu_ctrl; + + INFO("[SCU]: enabling snoop control unit ... \n"); + + assert(base != 0U); + scu_ctrl = mmio_read_32(base + SCU_CTRL_REG); + + /* already enabled? */ + if ((scu_ctrl & SCU_ENABLE_BIT) != 0) { + return; + } + + scu_ctrl |= SCU_ENABLE_BIT; + mmio_write_32(base + SCU_CTRL_REG, scu_ctrl); +} + +/******************************************************************************* + * Snoop Control Unit configuration register. This is read-only register and + * contains information such as + * - number of CPUs present + * - is a particular CPU operating in SMP mode or AMP mode + * - data cache size of a particular CPU + * - does SCU has ACP port + * - is L2CPRESENT + * NOTE: user of this API should interpert the bits in this register according + * to the TRM + ******************************************************************************/ +uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base) +{ + assert(base != 0U); + + return mmio_read_32(base + SCU_CFG_REG); +} diff --git a/include/drivers/arm/scu.h b/include/drivers/arm/scu.h new file mode 100644 index 000000000..992539f21 --- /dev/null +++ b/include/drivers/arm/scu.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCU_H +#define SCU_H + +#include + +#define SCU_CTRL_REG 0x00 +#define SCU_CFG_REG 0x04 + +#define SCU_ENABLE_BIT (1 << 0) + +void enable_snoop_ctrl_unit(uintptr_t base); +uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base); + +#endif /* SCU_H */ diff --git a/plat/arm/board/a5ds/a5ds_pm.c b/plat/arm/board/a5ds/a5ds_pm.c index cc734b005..7774002e6 100644 --- a/plat/arm/board/a5ds/a5ds_pm.c +++ b/plat/arm/board/a5ds/a5ds_pm.c @@ -4,11 +4,10 @@ * SPDX-License-Identifier: BSD-3-Clause */ #include - +#include #include #include #include -#include /******************************************************************************* * Platform handler called when a power domain is about to be turned on. The diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h index e9e4b9aef..d200af686 100644 --- a/plat/arm/board/a5ds/include/platform_def.h +++ b/plat/arm/board/a5ds/include/platform_def.h @@ -334,6 +334,9 @@ #define A5DS_HOLD_STATE_WAIT 0 #define A5DS_HOLD_STATE_GO 1 +/* Snoop Control Unit base address */ +#define A5DS_SCU_BASE 0x1C000000 + /* * GIC related constants to cater for GICv2 */ diff --git a/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c index 8b45af85b..a951dc7b4 100644 --- a/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c +++ b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c @@ -4,12 +4,17 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include #include + void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); + + /* enable snoop control unit */ + enable_snoop_ctrl_unit(A5DS_SCU_BASE); } /* diff --git a/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk index da1d785c2..4b0c97dfd 100644 --- a/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk +++ b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk @@ -5,7 +5,8 @@ # # SP_MIN source files specific to A5DS platform -BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \ +BL32_SOURCES += drivers/arm/scu/scu.c \ + drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ lib/aarch32/arm32_aeabi_divmod.c \ lib/aarch32/arm32_aeabi_divmod_a32.S \ -- cgit v1.2.3 From 3333d2caf4756447779cd0994a1411745f20fdc3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 15 Oct 2019 22:47:57 +0200 Subject: rcar_gen3: drivers: ddr: Move DDR drivers out of staging Now that DDR drivers are mostly cleaned up , move them out of staging. Signed-off-by: Marek Vasut Change-Id: I9de63f847a0ef9ac27a79fb0f848c351fd7f4da6 --- drivers/renesas/rcar/ddr/boot_init_dram.h | 18 + drivers/renesas/rcar/ddr/ddr.mk | 17 + .../renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h | 8 + drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk | 13 + drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c | 699 +++ drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c | 1712 ++++++ drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c | 339 ++ drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c | 4442 +++++++++++++++ .../renesas/rcar/ddr/ddr_b/boot_init_dram_config.c | 1794 ++++++ .../renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h | 95 + drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk | 7 + drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h | 5887 ++++++++++++++++++++ drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h | 441 ++ .../renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h | 538 ++ drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h | 468 ++ drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h | 587 ++ drivers/renesas/rcar/ddr/ddr_regs.h | 257 + drivers/renesas/rcar/ddr/dram_sub_func.c | 165 + drivers/renesas/rcar/ddr/dram_sub_func.h | 17 + drivers/staging/renesas/rcar/ddr/boot_init_dram.h | 18 - drivers/staging/renesas/rcar/ddr/ddr.mk | 17 - .../renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h | 8 - drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk | 13 - .../staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c | 699 --- .../staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c | 1712 ------ .../staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c | 339 -- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 4442 --------------- .../renesas/rcar/ddr/ddr_b/boot_init_dram_config.c | 1794 ------ .../renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h | 95 - drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk | 7 - .../staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h | 5887 -------------------- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h | 441 -- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h | 538 -- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h | 468 -- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h | 587 -- drivers/staging/renesas/rcar/ddr/ddr_regs.h | 257 - drivers/staging/renesas/rcar/ddr/dram_sub_func.c | 165 - drivers/staging/renesas/rcar/ddr/dram_sub_func.h | 17 - plat/renesas/rcar/platform.mk | 4 +- 39 files changed, 17506 insertions(+), 17506 deletions(-) create mode 100644 drivers/renesas/rcar/ddr/boot_init_dram.h create mode 100644 drivers/renesas/rcar/ddr/ddr.mk create mode 100644 drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h create mode 100644 drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk create mode 100644 drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c create mode 100644 drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c create mode 100644 drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c create mode 100644 drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c create mode 100644 drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c create mode 100644 drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h create mode 100644 drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk create mode 100644 drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h create mode 100644 drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h create mode 100644 drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h create mode 100644 drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h create mode 100644 drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h create mode 100644 drivers/renesas/rcar/ddr/ddr_regs.h create mode 100644 drivers/renesas/rcar/ddr/dram_sub_func.c create mode 100644 drivers/renesas/rcar/ddr/dram_sub_func.h delete mode 100644 drivers/staging/renesas/rcar/ddr/boot_init_dram.h delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr.mk delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h delete mode 100644 drivers/staging/renesas/rcar/ddr/ddr_regs.h delete mode 100644 drivers/staging/renesas/rcar/ddr/dram_sub_func.c delete mode 100644 drivers/staging/renesas/rcar/ddr/dram_sub_func.h diff --git a/drivers/renesas/rcar/ddr/boot_init_dram.h b/drivers/renesas/rcar/ddr/boot_init_dram.h new file mode 100644 index 000000000..ac237b2ef --- /dev/null +++ b/drivers/renesas/rcar/ddr/boot_init_dram.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOOT_INIT_DRAM_H +#define BOOT_INIT_DRAM_H + +extern int32_t rcar_dram_init(void); + +#define INITDRAM_OK 0 +#define INITDRAM_NG 0xffffffff +#define INITDRAM_ERR_I 0xffffffff +#define INITDRAM_ERR_O 0xfffffffe +#define INITDRAM_ERR_T 0xfffffff0 + +#endif /* BOOT_INIT_DRAM_H */ diff --git a/drivers/renesas/rcar/ddr/ddr.mk b/drivers/renesas/rcar/ddr/ddr.mk new file mode 100644 index 000000000..c26993d00 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr.mk @@ -0,0 +1,17 @@ +# +# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +ifeq (${RCAR_LSI},${RCAR_E3}) + include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk + BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c +else ifeq (${RCAR_LSI},${RCAR_D3}) + include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk +else ifeq (${RCAR_LSI},${RCAR_V3M}) + include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk +else + include drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk + BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c +endif diff --git a/drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h new file mode 100644 index 000000000..0f89b4350 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "../ddr_regs.h" diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk new file mode 100644 index 000000000..7882558d0 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk @@ -0,0 +1,13 @@ +# +# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +ifeq (${RCAR_LSI},${RCAR_E3}) +BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c +else ifeq (${RCAR_LSI},${RCAR_D3}) +BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c +else +BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c +endif diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c new file mode 100644 index 000000000..a49510ed5 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c @@ -0,0 +1,699 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include "rcar_def.h" +#include "../ddr_regs.h" + +#define RCAR_DDR_VERSION "rev.0.01" + +#if RCAR_LSI != RCAR_D3 +#error "Don't have DDR initialize routine." +#endif + +static void init_ddr_d3_1866(void) +{ + uint32_t i, r2, r3, r5, r6, r7, r12; + + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBKIND, 0x00000007); + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); + mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); + mmio_write_32(DBSC_DBTR0, 0x0000000D); + mmio_write_32(DBSC_DBTR1, 0x00000009); + mmio_write_32(DBSC_DBTR2, 0x00000000); + mmio_write_32(DBSC_DBTR3, 0x0000000D); + mmio_write_32(DBSC_DBTR4, 0x000D000D); + mmio_write_32(DBSC_DBTR5, 0x0000002D); + mmio_write_32(DBSC_DBTR6, 0x00000020); + mmio_write_32(DBSC_DBTR7, 0x00060006); + mmio_write_32(DBSC_DBTR8, 0x00000021); + mmio_write_32(DBSC_DBTR9, 0x00000007); + mmio_write_32(DBSC_DBTR10, 0x0000000E); + mmio_write_32(DBSC_DBTR11, 0x0000000C); + mmio_write_32(DBSC_DBTR12, 0x00140014); + mmio_write_32(DBSC_DBTR13, 0x000000F2); + mmio_write_32(DBSC_DBTR14, 0x00170006); + mmio_write_32(DBSC_DBTR15, 0x00060005); + mmio_write_32(DBSC_DBTR16, 0x09210507); + mmio_write_32(DBSC_DBTR17, 0x040E0000); + mmio_write_32(DBSC_DBTR18, 0x00000200); + mmio_write_32(DBSC_DBTR19, 0x012B004B); + mmio_write_32(DBSC_DBTR20, 0x020000FB); + mmio_write_32(DBSC_DBTR21, 0x00040004); + mmio_write_32(DBSC_DBBL, 0x00000000); + mmio_write_32(DBSC_DBODT0, 0x00000001); + mmio_write_32(DBSC_DBADJ0, 0x00000001); + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + mmio_write_32(DBSC_DBSCHRW1, 0x00000046); + mmio_write_32(DBSC_SCFCTST0, 0x0D020D04); + mmio_write_32(DBSC_SCFCTST1, 0x0306040C); + + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); + mmio_write_32(DBSC_DBCMD, 0x01000001); + mmio_write_32(DBSC_DBCMD, 0x08000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9; + r3 = (r2 << 16) + (r2 << 8) + r2; + r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; + mmio_write_32(DBSC_DBPDRGA_0, 0x00000011); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000012); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000016); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000017); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000018); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000019); + mmio_write_32(DBSC_DBPDRGD_0, r6); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); + mmio_write_32(DBSC_DBCMD, 0x08000001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + for (i = 0; i < 2; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + + if (r6 > 0) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | + ((r6 + (r5 << 1)) & 0xFF)); + } + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + for (i = 0; i < 2; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + r12 = (r5 >> 0x2); + + if (r12 < r6) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | + ((r6 + r5 + + (r5 >> 1) + r12) & 0xFF)); + } + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) + ; + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); + + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); + mmio_write_32(DBSC_DBCALCNF, 0x0100401B); + mmio_write_32(DBSC_DBRFCNF1, 0x00080E23); + mmio_write_32(DBSC_DBRFCNF2, 0x00010000); + mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); + mmio_write_32(DBSC_DBRFEN, 0x00000001); + mmio_write_32(DBSC_DBACEN, 0x00000001); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); + +#ifdef ddr_qos_init_setting // only for non qos_init + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); + mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); + mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHRW0, 0x22421111); + mmio_write_32(DBSC_SCFCTST2, 0x012F1123); + mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); + mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); + mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS92, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); + mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); + mmio_write_32(0xE67F0018, 0x00000001); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); +#endif +} + +static void init_ddr_d3_1600(void) +{ + uint32_t i, r2, r3, r5, r6, r7, r12; + + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBKIND, 0x00000007); + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); + mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); + mmio_write_32(DBSC_DBTR0, 0x0000000B); + mmio_write_32(DBSC_DBTR1, 0x00000008); + mmio_write_32(DBSC_DBTR2, 0x00000000); + mmio_write_32(DBSC_DBTR3, 0x0000000B); + mmio_write_32(DBSC_DBTR4, 0x000B000B); + mmio_write_32(DBSC_DBTR5, 0x00000027); + mmio_write_32(DBSC_DBTR6, 0x0000001C); + mmio_write_32(DBSC_DBTR7, 0x00060006); + mmio_write_32(DBSC_DBTR8, 0x00000020); + mmio_write_32(DBSC_DBTR9, 0x00000006); + mmio_write_32(DBSC_DBTR10, 0x0000000C); + mmio_write_32(DBSC_DBTR11, 0x0000000A); + mmio_write_32(DBSC_DBTR12, 0x00120012); + mmio_write_32(DBSC_DBTR13, 0x000000D0); + mmio_write_32(DBSC_DBTR14, 0x00140005); + mmio_write_32(DBSC_DBTR15, 0x00050004); + mmio_write_32(DBSC_DBTR16, 0x071F0305); + mmio_write_32(DBSC_DBTR17, 0x040C0000); + mmio_write_32(DBSC_DBTR18, 0x00000200); + mmio_write_32(DBSC_DBTR19, 0x01000040); + mmio_write_32(DBSC_DBTR20, 0x020000D8); + mmio_write_32(DBSC_DBTR21, 0x00040004); + mmio_write_32(DBSC_DBBL, 0x00000000); + mmio_write_32(DBSC_DBODT0, 0x00000001); + mmio_write_32(DBSC_DBADJ0, 0x00000001); + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + mmio_write_32(DBSC_DBSCHRW1, 0x00000046); + mmio_write_32(DBSC_SCFCTST0, 0x0D020C04); + mmio_write_32(DBSC_SCFCTST1, 0x0305040C); + + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); + mmio_write_32(DBSC_DBCMD, 0x01000001); + mmio_write_32(DBSC_DBCMD, 0x08000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000098); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9; + r3 = (r2 << 16) + (r2 << 8) + r2; + r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; + mmio_write_32(DBSC_DBPDRGA_0, 0x00000011); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000012); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000016); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000017); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000018); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000019); + mmio_write_32(DBSC_DBPDRGD_0, r6); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); + mmio_write_32(DBSC_DBCMD, 0x08000001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + for (i = 0; i < 2; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + if (r6 > 0) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | + ((r6 + (r5 << 1)) & 0xFF)); + } + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + for (i = 0; i < 2; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + r12 = (r5 >> 0x2); + + if (r12 < r6) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | + ((r6 + r5 + + (r5 >> 1) + r12) & 0xFF)); + } + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) + ; + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); + + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); + mmio_write_32(DBSC_DBCALCNF, 0x0100401B); + mmio_write_32(DBSC_DBRFCNF1, 0x00080C30); + mmio_write_32(DBSC_DBRFCNF2, 0x00010000); + mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); + mmio_write_32(DBSC_DBRFEN, 0x00000001); + mmio_write_32(DBSC_DBACEN, 0x00000001); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); + +#ifdef ddr_qos_init_setting // only for non qos_init + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); + mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); + mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHRW0, 0x22421111); + mmio_write_32(DBSC_SCFCTST2, 0x012F1123); + mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); + mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); + mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS92, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); + mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); + mmio_write_32(0xE67F0018, 0x00000001); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); +#endif +} + +#define PRR 0xFFF00044U +#define PRR_PRODUCT_MASK 0x00007F00U +#define PRR_PRODUCT_D3 0x00005800U + +#define MODEMR_MD19 BIT(19) + +int32_t rcar_dram_init(void) +{ + uint32_t reg; + uint32_t ddr_mbps; + + reg = mmio_read_32(PRR); + if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_D3) { + ERROR("LSI Product ID (PRR=0x%x) DDR initialize not supported.\n", + reg); + panic(); + } + + reg = mmio_read_32(RST_MODEMR); + if (reg & MODEMR_MD19) { + init_ddr_d3_1866(); + ddr_mbps = 1866; + } else { + init_ddr_d3_1600(); + ddr_mbps = 1600; + } + + NOTICE("BL2: DDR%d\n", ddr_mbps); + + return 0; +} diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c new file mode 100644 index 000000000..fc278ef57 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c @@ -0,0 +1,1712 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include "boot_init_dram.h" +#include "rcar_def.h" +#include "../ddr_regs.h" + +#include "../dram_sub_func.h" + +#define RCAR_E3_DDR_VERSION "rev.0.12" + +/* Average periodic refresh interval[ns]. Support 3900,7800 */ +#ifdef ddr_qos_init_setting +#define REFRESH_RATE 3900U +#else +#if RCAR_REF_INT == 1 +#define REFRESH_RATE 7800U +#else +#define REFRESH_RATE 3900U +#endif +#endif + +/* + * Initialize ddr + */ +uint32_t init_ddr(void) +{ + uint32_t i, r2, r5, r6, r7, r12; + uint32_t ddr_md; + uint32_t regval, j; + uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4; + uint32_t bdlcount_0c_div8, bdlcount_0c_div16; + uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; + uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; + uint32_t pdr_ctl; + uint32_t byp_ctl; + + if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) { + pdqsr_ctl = 1; + lcdl_ctl = 1; + pdr_ctl = 1; + byp_ctl = 1; + } else { + pdqsr_ctl = 0; + lcdl_ctl = 0; + pdr_ctl = 0; + byp_ctl = 0; + } + + /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ + ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0); + + /* 1584Mbps setting */ + if (ddr_md == 0) { + mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); + mmio_write_32(CPG_CPGWPCR, 0xA5A50000); + + mmio_write_32(CPG_SRCR4, 0x20000000); + + mmio_write_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ + while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) + ; + + mmio_write_32(CPG_SRSTCLR4, 0x20000000); + + mmio_write_32(CPG_CPGWPCR, 0xA5A50001); + } + + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBKIND, 0x00000007); + +#if RCAR_DRAM_DDR3L_MEMCONF == 0 + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); /* 1GB */ +#else + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); /* 2GB(default) */ +#endif + +#if RCAR_DRAM_DDR3L_MEMDUAL == 1 + r2 = mmio_read_32(0xE6790614); + mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */ +#endif + + mmio_write_32(DBSC_DBPHYCONF0, 0x1); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR0, 0xB); + mmio_write_32(DBSC_DBTR1, 0x8); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR0, 0xD); + mmio_write_32(DBSC_DBTR1, 0x9); + } + + mmio_write_32(DBSC_DBTR2, 0x00000000); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR3, 0x0000000B); + mmio_write_32(DBSC_DBTR4, 0x000B000B); + mmio_write_32(DBSC_DBTR5, 0x00000027); + mmio_write_32(DBSC_DBTR6, 0x0000001C); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR3, 0x0000000D); + mmio_write_32(DBSC_DBTR4, 0x000D000D); + mmio_write_32(DBSC_DBTR5, 0x0000002D); + mmio_write_32(DBSC_DBTR6, 0x00000020); + } + + mmio_write_32(DBSC_DBTR7, 0x00060006); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR8, 0x00000020); + mmio_write_32(DBSC_DBTR9, 0x00000006); + mmio_write_32(DBSC_DBTR10, 0x0000000C); + mmio_write_32(DBSC_DBTR11, 0x0000000A); + mmio_write_32(DBSC_DBTR12, 0x00120012); + mmio_write_32(DBSC_DBTR13, 0x000000CE); + mmio_write_32(DBSC_DBTR14, 0x00140005); + mmio_write_32(DBSC_DBTR15, 0x00050004); + mmio_write_32(DBSC_DBTR16, 0x071F0305); + mmio_write_32(DBSC_DBTR17, 0x040C0000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR8, 0x00000021); + mmio_write_32(DBSC_DBTR9, 0x00000007); + mmio_write_32(DBSC_DBTR10, 0x0000000E); + mmio_write_32(DBSC_DBTR11, 0x0000000C); + mmio_write_32(DBSC_DBTR12, 0x00140014); + mmio_write_32(DBSC_DBTR13, 0x000000F2); + mmio_write_32(DBSC_DBTR14, 0x00170006); + mmio_write_32(DBSC_DBTR15, 0x00060005); + mmio_write_32(DBSC_DBTR16, 0x09210507); + mmio_write_32(DBSC_DBTR17, 0x040E0000); + } + + mmio_write_32(DBSC_DBTR18, 0x00000200); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR19, 0x01000040); + mmio_write_32(DBSC_DBTR20, 0x020000D6); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR19, 0x0129004B); + mmio_write_32(DBSC_DBTR20, 0x020000FB); + } + + mmio_write_32(DBSC_DBTR21, 0x00040004); + mmio_write_32(DBSC_DBBL, 0x00000000); + mmio_write_32(DBSC_DBODT0, 0x00000001); + mmio_write_32(DBSC_DBADJ0, 0x00000001); + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + mmio_write_32(DBSC_DBSCHRW1, 0x00000046); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_SCFCTST0, 0x0D050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0306030C); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_SCFCTST0, 0x0C050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0305030C); + } + + /* + * Initial_Step0( INITBYP ) + */ + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); + mmio_write_32(DBSC_DBCMD, 0x01840001); + mmio_write_32(DBSC_DBCMD, 0x08840000); + NOTICE("BL2: [COLD_BOOT]\n"); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + /* + * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training ) + */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + /* + * Initial_Step2( DRAMRST/DRAMINT training ) + */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + if (byp_ctl == 1) + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720); + else + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) - + 400 + 0x08B00000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) - + 400 + 0x0A300000); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + if (REFRESH_RATE > 3900) /* [7]SRT=0 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x18); + else /* [7]SRT=1 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x98); + } else { /* 1856Mbps */ + if (REFRESH_RATE > 3900) /* [7]SRT=0 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x20); + else /* [7]SRT=1 */ + mmio_write_32(DBSC_DBPDRGD_0, 0xA0); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); + mmio_write_32(DBSC_DBCMD, 0x08840001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + /* + * Initial_Step3( WL/QSG training ) + */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + + if (r6 > 0) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | + ((r6 + ((r5) << 1)) & + 0xFF)); + } + } + + /* + * Initial_Step4( WLADJ training ) + */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); + + if (pdqsr_ctl == 0) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + /* + * Initial_Step5(Read Data Bit Deskew) + */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00011001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + } + + /* + * Initial_Step6(Write Data Bit Deskew) + */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00012001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + /* + * Initial_Step7(Read Data Eye Training) + */ + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00014001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + } + + /* + * Initial_Step8(Write Data Eye Training) + */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00018001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + /* + * Initial_Step3_2( DQS Gate Training ) + */ + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + r12 = (r5 >> 0x2); + if (r12 < r6) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + + (r5 >> 1) + r12) & 0xFF)); + } + } + + /* + * Initial_Step5-2_7-2( Rd bit Rd eye ) + */ + if (pdqsr_ctl == 0) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + if (lcdl_ctl == 1) { + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> + 8; + bdlcount_0c_div2 = bdlcount_0c >> 1; + bdlcount_0c_div4 = bdlcount_0c >> 2; + bdlcount_0c_div8 = bdlcount_0c >> 3; + bdlcount_0c_div16 = bdlcount_0c >> 4; + + if (ddr_md == 0) { /* 1584Mbps */ + lcdl_judge1 = bdlcount_0c_div2 + + bdlcount_0c_div4 + + bdlcount_0c_div8; + lcdl_judge2 = bdlcount_0c + + bdlcount_0c_div4 + + bdlcount_0c_div16; + } else { /* 1856Mbps */ + lcdl_judge1 = bdlcount_0c_div2 + + bdlcount_0c_div4; + lcdl_judge2 = bdlcount_0c + + bdlcount_0c_div4; + } + + if (dqsgd_0c <= lcdl_judge1) + continue; + + if (dqsgd_0c <= lcdl_judge2) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & + 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGD_0, + (dqsgd_0c - bdlcount_0c_div8) | + regval); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & + 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & + 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGD_0, regval | + (gatesl_0c + 1)); + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); + rdqsd_0c = (regval & 0xFF00) >> 8; + rdqsnd_0c = (regval & 0xFF0000) >> 16; + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, + (regval & 0xFF0000FF) | + ((rdqsd_0c + + bdlcount_0c_div4) << 8) | + ((rdqsnd_0c + + bdlcount_0c_div4) << 16)); + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); + rbd_0c[0] = (regval) & 0x1f; + rbd_0c[1] = (regval >> 8) & 0x1f; + rbd_0c[2] = (regval >> 16) & 0x1f; + rbd_0c[3] = (regval >> 24) & 0x1f; + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & + 0xE0E0E0E0; + for (j = 0; j < 4; j++) { + rbd_0c[j] = rbd_0c[j] + + bdlcount_0c_div4; + if (rbd_0c[j] > 0x1F) + rbd_0c[j] = 0x1F; + regval = regval | (rbd_0c[j] << 8 * j); + } + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); + rbd_0c[0] = (regval) & 0x1f; + rbd_0c[1] = (regval >> 8) & 0x1f; + rbd_0c[2] = (regval >> 16) & 0x1f; + rbd_0c[3] = (regval >> 24) & 0x1f; + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & + 0xE0E0E0E0; + for (j = 0; j < 4; j++) { + rbd_0c[j] = rbd_0c[j] + + bdlcount_0c_div4; + if (rbd_0c[j] > 0x1F) + rbd_0c[j] = 0x1F; + regval = regval | (rbd_0c[j] << 8 * j); + } + mmio_write_32(DBSC_DBPDRGD_0, regval); + } + } + mmio_write_32(DBSC_DBPDRGA_0, 0x2); + mmio_write_32(DBSC_DBPDRGD_0, 0x7D81E37); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + if (byp_ctl == 1) + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720); + else + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); + + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); + mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000); + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBRFCNF1, + (REFRESH_RATE * 99 / 125) + 0x00080000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBRFCNF1, + (REFRESH_RATE * 116 / 125) + 0x00080000); + } + + mmio_write_32(DBSC_DBRFCNF2, 0x00010000); + mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); + mmio_write_32(DBSC_DBRFEN, 0x00000001); + mmio_write_32(DBSC_DBACEN, 0x00000001); + + if (pdqsr_ctl == 1) { + mmio_write_32(0xE67F0018, 0x00000001); + regval = mmio_read_32(0x40000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + } + + /* + * Initial_Step9( Initial End ) + */ + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); + +#ifdef ddr_qos_init_setting /* only for non qos_init */ + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); + mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); + mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHRW0, 0x22421111); + mmio_write_32(DBSC_SCFCTST2, 0x012F1123); + mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); + mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); + mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); + mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); + + if (pdqsr_ctl == 0) + mmio_write_32(0xE67F0018, 0x00000001); + + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); +#endif + + return 1; +} + +static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) +{ + /* + * recovery_Step0(DBSC Setting 1) / same "init_ddr" + */ + uint32_t r2, r5, r6, r7, r12, i; + uint32_t ddr_md; + uint32_t err; + uint32_t regval, j; + uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4; + uint32_t bdlcount_0c_div8, bdlcount_0c_div16; + uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; + uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; + uint32_t pdr_ctl; + uint32_t byp_ctl; + + if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) { + pdqsr_ctl = 1; + lcdl_ctl = 1; + pdr_ctl = 1; + byp_ctl = 1; + } else { + pdqsr_ctl = 0; + lcdl_ctl = 0; + pdr_ctl = 0; + byp_ctl = 0; + } + + /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ + ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0); + + /* 1584Mbps setting */ + if (ddr_md == 0) { + mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); + mmio_write_32(CPG_CPGWPCR, 0xA5A50000); + + mmio_write_32(CPG_SRCR4, 0x20000000); + + mmio_write_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ + while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) + ; + + mmio_write_32(CPG_SRSTCLR4, 0x20000000); + + mmio_write_32(CPG_CPGWPCR, 0xA5A50001); + } + + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBKIND, 0x00000007); + +#if RCAR_DRAM_DDR3L_MEMCONF == 0 + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); +#else + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); +#endif + +#if RCAR_DRAM_DDR3L_MEMDUAL == 1 + r2 = mmio_read_32(0xE6790614); + mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */ +#endif + + mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR0, 0x0000000B); + mmio_write_32(DBSC_DBTR1, 0x00000008); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR0, 0x0000000D); + mmio_write_32(DBSC_DBTR1, 0x00000009); + } + + mmio_write_32(DBSC_DBTR2, 0x00000000); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR3, 0x0000000B); + mmio_write_32(DBSC_DBTR4, 0x000B000B); + mmio_write_32(DBSC_DBTR5, 0x00000027); + mmio_write_32(DBSC_DBTR6, 0x0000001C); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR3, 0x0000000D); + mmio_write_32(DBSC_DBTR4, 0x000D000D); + mmio_write_32(DBSC_DBTR5, 0x0000002D); + mmio_write_32(DBSC_DBTR6, 0x00000020); + } + + mmio_write_32(DBSC_DBTR7, 0x00060006); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR8, 0x00000020); + mmio_write_32(DBSC_DBTR9, 0x00000006); + mmio_write_32(DBSC_DBTR10, 0x0000000C); + mmio_write_32(DBSC_DBTR11, 0x0000000A); + mmio_write_32(DBSC_DBTR12, 0x00120012); + mmio_write_32(DBSC_DBTR13, 0x000000CE); + mmio_write_32(DBSC_DBTR14, 0x00140005); + mmio_write_32(DBSC_DBTR15, 0x00050004); + mmio_write_32(DBSC_DBTR16, 0x071F0305); + mmio_write_32(DBSC_DBTR17, 0x040C0000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR8, 0x00000021); + mmio_write_32(DBSC_DBTR9, 0x00000007); + mmio_write_32(DBSC_DBTR10, 0x0000000E); + mmio_write_32(DBSC_DBTR11, 0x0000000C); + mmio_write_32(DBSC_DBTR12, 0x00140014); + mmio_write_32(DBSC_DBTR13, 0x000000F2); + mmio_write_32(DBSC_DBTR14, 0x00170006); + mmio_write_32(DBSC_DBTR15, 0x00060005); + mmio_write_32(DBSC_DBTR16, 0x09210507); + mmio_write_32(DBSC_DBTR17, 0x040E0000); + } + + mmio_write_32(DBSC_DBTR18, 0x00000200); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR19, 0x01000040); + mmio_write_32(DBSC_DBTR20, 0x020000D6); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR19, 0x0129004B); + mmio_write_32(DBSC_DBTR20, 0x020000FB); + } + + mmio_write_32(DBSC_DBTR21, 0x00040004); + mmio_write_32(DBSC_DBBL, 0x00000000); + mmio_write_32(DBSC_DBODT0, 0x00000001); + mmio_write_32(DBSC_DBADJ0, 0x00000001); + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + mmio_write_32(DBSC_DBSCHRW1, 0x00000046); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_SCFCTST0, 0x0D050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0306030C); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_SCFCTST0, 0x0C050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0305030C); + } + + /* + * recovery_Step1(PHY setting 1) + */ + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); + mmio_write_32(DBSC_DBCMD, 0x01840001); + mmio_write_32(DBSC_DBCMD, 0x0A840000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); /* DDR_PLLCR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); /* DDR_PGCR1 */ + if (byp_ctl == 1) + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720); + else + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); /* DDR_DXCCR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); /* DDR_ACIOCR0 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) - + 400 + 0x08B00000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) - + 400 + 0x0A300000); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + if (REFRESH_RATE > 3900) + mmio_write_32(DBSC_DBPDRGD_0, 0x18); /* [7]SRT=0 */ + else + mmio_write_32(DBSC_DBPDRGD_0, 0x98); /* [7]SRT=1 */ + } else { /* 1856Mbps */ + if (REFRESH_RATE > 3900) + mmio_write_32(DBSC_DBPDRGD_0, 0x20); /* [7]SRT=0 */ + else + mmio_write_32(DBSC_DBPDRGD_0, 0xA0); /* [7]SRT=1 */ + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); /* DDR_DSGCR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x40010000); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000092); /* DDR_ZQ0DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000096); /* DDR_ZQ1DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0xC4285FBF); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A); /* DDR_ZQ2DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00050001); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + /* ddr backupmode end */ + if (ddr_backup) + NOTICE("BL2: [WARM_BOOT]\n"); + else + NOTICE("BL2: [COLD_BOOT]\n"); + + err = rcar_dram_update_boot_status(ddr_backup); + if (err) { + NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); + return INITDRAM_ERR_I; + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000092); /* DDR_ZQ0DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000096); /* DDR_ZQ1DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04285FBF); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A); /* DDR_ZQ2DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x08000000); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00000003); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + + mmio_write_32(DBSC_DBPDRGA_0, 0x0000000C); + mmio_write_32(DBSC_DBPDRGD_0, 0x18000040); + + /* + * recovery_Step2(PHY setting 2) + */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + + mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000); + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBRFCNF1, + (REFRESH_RATE * 99 / 125) + 0x00080000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBRFCNF1, + (REFRESH_RATE * 116 / 125) + 0x00080000); + } + + mmio_write_32(DBSC_DBRFCNF2, 0x00010000); + mmio_write_32(DBSC_DBRFEN, 0x00000001); + mmio_write_32(DBSC_DBCMD, 0x0A840001); + while (mmio_read_32(DBSC_DBWAIT) & BIT(0)) + ; + + mmio_write_32(DBSC_DBCMD, 0x00000000); + + mmio_write_32(DBSC_DBCMD, 0x04840010); + while (mmio_read_32(DBSC_DBWAIT) & BIT(0)) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00010701); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + + if (r6 > 0) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, + r2 | ((r6 + (r5 << 1)) & 0xFF)); + } + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); + + if (pdqsr_ctl == 0) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00011001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00012001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00014001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00018001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + r12 = r5 >> 0x2; + + if (r12 < r6) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, + r2 | + ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); + } + } + + if (pdqsr_ctl == 0) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + if (lcdl_ctl == 1) { + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000B0 + i * 0x20); + dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x000000FF; + mmio_write_32(DBSC_DBPDRGA_0, 0x000000B1 + i * 0x20); + bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) & + 0x0000FF00) >> 8; + bdlcount_0c_div2 = (bdlcount_0c >> 1); + bdlcount_0c_div4 = (bdlcount_0c >> 2); + bdlcount_0c_div8 = (bdlcount_0c >> 3); + bdlcount_0c_div16 = (bdlcount_0c >> 4); + + if (ddr_md == 0) { /* 1584Mbps */ + lcdl_judge1 = bdlcount_0c_div2 + + bdlcount_0c_div4 + + bdlcount_0c_div8; + lcdl_judge2 = bdlcount_0c + + bdlcount_0c_div4 + + bdlcount_0c_div16; + } else { /* 1856Mbps */ + lcdl_judge1 = bdlcount_0c_div2 + + bdlcount_0c_div4; + lcdl_judge2 = bdlcount_0c + + bdlcount_0c_div4; + } + + if (dqsgd_0c <= lcdl_judge1) + continue; + + if (dqsgd_0c <= lcdl_judge2) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & + 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGD_0, + (dqsgd_0c - bdlcount_0c_div8) | + regval); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & + 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & + 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGD_0, + regval | (gatesl_0c + 1)); + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0); + rdqsd_0c = (regval & 0xFF00) >> 8; + rdqsnd_0c = (regval & 0xFF0000) >> 16; + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, + (regval & 0xFF0000FF) | + ((rdqsd_0c + + bdlcount_0c_div4) << 8) | + ((rdqsnd_0c + + bdlcount_0c_div4) << 16)); + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); + rbd_0c[0] = (regval) & 0x1f; + rbd_0c[1] = (regval >> 8) & 0x1f; + rbd_0c[2] = (regval >> 16) & 0x1f; + rbd_0c[3] = (regval >> 24) & 0x1f; + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & + 0xE0E0E0E0; + for (j = 0; j < 4; j++) { + rbd_0c[j] = rbd_0c[j] + + bdlcount_0c_div4; + if (rbd_0c[j] > 0x1F) + rbd_0c[j] = 0x1F; + regval = regval | (rbd_0c[j] << 8 * j); + } + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); + rbd_0c[0] = regval & 0x1f; + rbd_0c[1] = (regval >> 8) & 0x1f; + rbd_0c[2] = (regval >> 16) & 0x1f; + rbd_0c[3] = (regval >> 24) & 0x1f; + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & + 0xE0E0E0E0; + for (j = 0; j < 4; j++) { + rbd_0c[j] = rbd_0c[j] + + bdlcount_0c_div4; + if (rbd_0c[j] > 0x1F) + rbd_0c[j] = 0x1F; + regval = regval | (rbd_0c[j] << 8 * j); + } + mmio_write_32(DBSC_DBPDRGD_0, regval); + } + } + mmio_write_32(DBSC_DBPDRGA_0, 0x00000002); + mmio_write_32(DBSC_DBPDRGD_0, 0x07D81E37); + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + if (byp_ctl == 1) + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720); + else + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) + ; + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); + + /* + * recovery_Step3(DBSC Setting 2) + */ + mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); + mmio_write_32(DBSC_DBACEN, 0x00000001); + + if (pdqsr_ctl == 1) { + mmio_write_32(0xE67F0018, 0x00000001); + regval = mmio_read_32(0x40000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + } + + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); + +#ifdef ddr_qos_init_setting /* only for non qos_init */ + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); + mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); + mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHRW0, 0x22421111); + mmio_write_32(DBSC_SCFCTST2, 0x012F1123); + mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); + mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); + mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); + mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); + + if (pdqsr_ctl == 0) + mmio_write_32(0xE67F0018, 0x00000001); + + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); +#endif + + return 1; + +} /* recovery_from_backup_mode */ + +/* + * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps + */ + +/* + * DDR Initialize entry for IPL + */ +int32_t rcar_dram_init(void) +{ + uint32_t dataL; + uint32_t failcount; + uint32_t md = 0; + uint32_t ddr = 0; + uint32_t ddr_backup; + + md = *((volatile uint32_t*)RST_MODEMR); + ddr = (md & 0x00080000) >> 19; + if (ddr == 0x0) + NOTICE("BL2: DDR1584(%s)\n", RCAR_E3_DDR_VERSION); + else if (ddr == 0x1) + NOTICE("BL2: DDR1856(%s)\n", RCAR_E3_DDR_VERSION); + + rcar_dram_get_boot_status(&ddr_backup); + + if (ddr_backup == DRAM_BOOT_STATUS_WARM) + dataL = recovery_from_backup_mode(ddr_backup); /* WARM boot */ + else + dataL = init_ddr(); /* COLD boot */ + + if (dataL == 1) + failcount = 0; + else + failcount = 1; + + if (failcount == 0) + return INITDRAM_OK; + else + return INITDRAM_NG; + +} diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c new file mode 100644 index 000000000..5410771c9 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include "boot_init_dram.h" +#include "rcar_def.h" +#include "../ddr_regs.h" + +static uint32_t init_ddr_v3m_1600(void) +{ + uint32_t i, r2, r5, r6, r7, r12; + + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBKIND, 0x00000007); +#if RCAR_DRAM_DDR3L_MEMCONF == 0 + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); // 1GB: Eagle +#else + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); // 2GB: V3MSK +#endif + mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); + mmio_write_32(DBSC_DBTR0, 0x0000000B); + mmio_write_32(DBSC_DBTR1, 0x00000008); + mmio_write_32(DBSC_DBTR3, 0x0000000B); + mmio_write_32(DBSC_DBTR4, 0x000B000B); + mmio_write_32(DBSC_DBTR5, 0x00000027); + mmio_write_32(DBSC_DBTR6, 0x0000001C); + mmio_write_32(DBSC_DBTR7, 0x00060006); + mmio_write_32(DBSC_DBTR8, 0x00000020); + mmio_write_32(DBSC_DBTR9, 0x00000006); + mmio_write_32(DBSC_DBTR10, 0x0000000C); + mmio_write_32(DBSC_DBTR11, 0x0000000B); + mmio_write_32(DBSC_DBTR12, 0x00120012); + mmio_write_32(DBSC_DBTR13, 0x01180118); + mmio_write_32(DBSC_DBTR14, 0x00140005); + mmio_write_32(DBSC_DBTR15, 0x00050004); + mmio_write_32(DBSC_DBTR16, 0x071D0305); + mmio_write_32(DBSC_DBTR17, 0x040C0010); + mmio_write_32(DBSC_DBTR18, 0x00000200); + mmio_write_32(DBSC_DBTR19, 0x01000040); + mmio_write_32(DBSC_DBTR20, 0x02000120); + mmio_write_32(DBSC_DBTR21, 0x00040004); + mmio_write_32(DBSC_DBBL, 0x00000000); + mmio_write_32(DBSC_DBODT0, 0x00000001); + mmio_write_32(DBSC_DBADJ0, 0x00000001); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00082010); + mmio_write_32(DBSC_DBCAM0CNF2, 0x00002000); + mmio_write_32(DBSC_DBSCHCNT0, 0x080f003f); + mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHRW0, 0x00000200); + mmio_write_32(DBSC_DBSCHRW1, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000600); + mmio_write_32(DBSC_DBSCHQOS41, 0x00000480); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000180); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000400); + mmio_write_32(DBSC_DBSCHQOS91, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS92, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS131, 0x00000240); + mmio_write_32(DBSC_DBSCHQOS132, 0x00000180); + mmio_write_32(DBSC_DBSCHQOS133, 0x000000c0); + mmio_write_32(DBSC_DBSCHQOS140, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS141, 0x00000180); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS151, 0x000000c0); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000040); + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00040C04); + mmio_write_32(DBSC_DBCAM0CNF2, 0x000001c4); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000003); + mmio_write_32(DBSC_DBSCHRW1, 0x001a0080); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); + + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); + mmio_write_32(DBSC_DBCMD, 0x01000001); + mmio_write_32(DBSC_DBCMD, 0x08000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD_0, 0x08C0C170); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000018); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x13C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); + mmio_write_32(DBSC_DBCMD, 0x08000001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + + if (r6 > 0) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | + (((r5 << 1) + r6) & 0xFF)); + } + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00A0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00B8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF); + + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x7); + r12 = (r5 >> 2); + if (r6 - r12 > 0) { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); + + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, ((r6 - r12) & 0xFF) | r2); + } else { + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, (r7 & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | + ((r6 + r5 + + (r5 >> 1) + r12) & 0xFF)); + } + } + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) + ; + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); + + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000000); + mmio_write_32(DBSC_DBBUS0CNF0, 0x00010001); + mmio_write_32(DBSC_DBCALCNF, 0x0100200E); + mmio_write_32(DBSC_DBRFCNF1, 0x00081860); + mmio_write_32(DBSC_DBRFCNF2, 0x00010000); + mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); + mmio_write_32(DBSC_DBRFEN, 0x00000001); + mmio_write_32(DBSC_DBACEN, 0x00000001); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); + mmio_write_32(0xE67F0024, 0x00000001); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); + + return INITDRAM_OK; +} + +int32_t rcar_dram_init(void) +{ + return init_ddr_v3m_1600(); +} diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c new file mode 100644 index 000000000..1d6e83a2c --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -0,0 +1,4442 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include + +#include "ddr_regdef.h" +#include "init_dram_tbl_h3.h" +#include "init_dram_tbl_m3.h" +#include "init_dram_tbl_h3ver2.h" +#include "init_dram_tbl_m3n.h" +#include "boot_init_dram_regdef.h" +#include "boot_init_dram.h" +#include "dram_sub_func.h" +#include "micro_delay.h" +#include "rcar_def.h" + +#define DDR_BACKUPMODE +#define FATAL_MSG(x) NOTICE(x) + +/* variables */ +#ifdef RCAR_DDR_FIXED_LSI_TYPE +#ifndef RCAR_AUTO +#define RCAR_AUTO 99 +#define RCAR_H3 0 +#define RCAR_M3 1 +#define RCAR_M3N 2 +#define RCAR_E3 3 /* NON */ +#define RCAR_H3N 4 + +#define RCAR_CUT_10 0 +#define RCAR_CUT_11 1 +#define RCAR_CUT_20 10 +#define RCAR_CUT_30 20 +#endif +#ifndef RCAR_LSI +#define RCAR_LSI RCAR_AUTO +#endif + +#if (RCAR_LSI == RCAR_AUTO) +static uint32_t prr_product; +static uint32_t prr_cut; +#else +#if (RCAR_LSI == RCAR_H3) +static const uint32_t prr_product = PRR_PRODUCT_H3; +#elif(RCAR_LSI == RCAR_M3) +static const uint32_t prr_product = PRR_PRODUCT_M3; +#elif(RCAR_LSI == RCAR_M3N) +static const uint32_t prr_product = PRR_PRODUCT_M3N; +#elif(RCAR_LSI == RCAR_H3N) +static const uint32_t prr_product = PRR_PRODUCT_H3; +#endif /* RCAR_LSI */ + +#ifndef RCAR_LSI_CUT +static uint32_t prr_cut; +#else /* RCAR_LSI_CUT */ +#if (RCAR_LSI_CUT == RCAR_CUT_10) +static const uint32_t prr_cut = PRR_PRODUCT_10; +#elif(RCAR_LSI_CUT == RCAR_CUT_11) +static const uint32_t prr_cut = PRR_PRODUCT_11; +#elif(RCAR_LSI_CUT == RCAR_CUT_20) +static const uint32_t prr_cut = PRR_PRODUCT_20; +#elif(RCAR_LSI_CUT == RCAR_CUT_30) +static const uint32_t prr_cut = PRR_PRODUCT_30; +#endif /* RCAR_LSI_CUT */ +#endif /* RCAR_LSI_CUT */ +#endif /* RCAR_AUTO_NON */ +#else /* RCAR_DDR_FIXED_LSI_TYPE */ +static uint32_t prr_product; +static uint32_t prr_cut; +#endif /* RCAR_DDR_FIXED_LSI_TYPE */ + +static const uint32_t *p_ddr_regdef_tbl; +static uint32_t brd_clk; +static uint32_t brd_clkdiv; +static uint32_t brd_clkdiva; +static uint32_t ddr_mbps; +static uint32_t ddr_mbpsdiv; +static uint32_t ddr_tccd; +static uint32_t ddr_phycaslice; +static const struct _boardcnf *board_cnf; +static uint32_t ddr_phyvalid; +static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; +static uint32_t ch_have_this_cs[CS_CNT] __aligned(64); +static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9]; +static uint32_t max_density; +static uint32_t ddr0800_mul; +static uint32_t ddr_mul; +static uint32_t DDR_PHY_SLICE_REGSET_OFS; +static uint32_t DDR_PHY_ADR_V_REGSET_OFS; +static uint32_t DDR_PHY_ADR_I_REGSET_OFS; +static uint32_t DDR_PHY_ADR_G_REGSET_OFS; +static uint32_t DDR_PI_REGSET_OFS; +static uint32_t DDR_PHY_SLICE_REGSET_SIZE; +static uint32_t DDR_PHY_ADR_V_REGSET_SIZE; +static uint32_t DDR_PHY_ADR_I_REGSET_SIZE; +static uint32_t DDR_PHY_ADR_G_REGSET_SIZE; +static uint32_t DDR_PI_REGSET_SIZE; +static uint32_t DDR_PHY_SLICE_REGSET_NUM; +static uint32_t DDR_PHY_ADR_V_REGSET_NUM; +static uint32_t DDR_PHY_ADR_I_REGSET_NUM; +static uint32_t DDR_PHY_ADR_G_REGSET_NUM; +static uint32_t DDR_PI_REGSET_NUM; +static uint32_t DDR_PHY_ADR_I_NUM; +#define DDR_PHY_REGSET_MAX 128 +#define DDR_PI_REGSET_MAX 320 +static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; +static uint32_t pll3_mode; +static uint32_t loop_max; +#ifdef DDR_BACKUPMODE +uint32_t ddr_backup; +/* #define DDR_BACKUPMODE_HALF //for Half channel(ch0,1 only) */ +#endif + +#ifdef ddr_qos_init_setting /* only for non qos_init */ +#define OPERATING_FREQ (400U) /* Mhz */ +#define BASE_SUB_SLOT_NUM (0x6U) +#define SUB_SLOT_CYCLE (0x7EU) /* 126 */ +#define QOSWT_WTSET0_CYCLE \ + ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \ + OPERATING_FREQ) /* unit:ns */ + +uint32_t get_refperiod(void) +{ + return QOSWT_WTSET0_CYCLE; +} +#else /* ddr_qos_init_setting // only for non qos_init */ +extern uint32_t get_refperiod(void); +#endif /* ddr_qos_init_setting // only for non qos_init */ + +#define _reg_PHY_RX_CAL_X_NUM 11 +static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { + _reg_PHY_RX_CAL_DQ0, + _reg_PHY_RX_CAL_DQ1, + _reg_PHY_RX_CAL_DQ2, + _reg_PHY_RX_CAL_DQ3, + _reg_PHY_RX_CAL_DQ4, + _reg_PHY_RX_CAL_DQ5, + _reg_PHY_RX_CAL_DQ6, + _reg_PHY_RX_CAL_DQ7, + _reg_PHY_RX_CAL_DM, + _reg_PHY_RX_CAL_DQS, + _reg_PHY_RX_CAL_FDBK +}; + +#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 +static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY + [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { + _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ3_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ4_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ5_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ6_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ7_SLAVE_DELAY, + _reg_PHY_CLK_WRDM_SLAVE_DELAY, + _reg_PHY_CLK_WRDQS_SLAVE_DELAY +}; + +#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 +static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY + [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { + _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY +}; + +#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 +static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY + [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { + _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY +}; + +#define _reg_PHY_PAD_TERM_X_NUM 8 +static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { + _reg_PHY_PAD_FDBK_TERM, + _reg_PHY_PAD_DATA_TERM, + _reg_PHY_PAD_DQS_TERM, + _reg_PHY_PAD_ADDR_TERM, + _reg_PHY_PAD_CLK_TERM, + _reg_PHY_PAD_CKE_TERM, + _reg_PHY_PAD_RST_TERM, + _reg_PHY_PAD_CS_TERM +}; + +#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 +static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X + [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { + _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, + _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, + _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, + _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY, + _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY, + _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY, + + _reg_PHY_GRP_SLAVE_DELAY_0, + _reg_PHY_GRP_SLAVE_DELAY_1, + _reg_PHY_GRP_SLAVE_DELAY_2, + _reg_PHY_GRP_SLAVE_DELAY_3 +}; + +/* Prototypes */ +static inline uint32_t vch_nxt(uint32_t pos); +static void cpg_write_32(uint32_t a, uint32_t v); +static void pll3_control(uint32_t high); +static inline void dsb_sev(void); +static void wait_dbcmd(void); +static void send_dbcmd(uint32_t cmd); +static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd); +static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); +static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); +static inline uint32_t ddr_regdef(uint32_t _regdef); +static inline uint32_t ddr_regdef_adr(uint32_t _regdef); +static inline uint32_t ddr_regdef_lsb(uint32_t _regdef); +static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, + uint32_t val); +static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef); +static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); +static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); +static void ddr_setval_ach(uint32_t regdef, uint32_t val); +static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); +static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); +static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p); +static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p); +static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size); +static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); +static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); +static uint32_t ddrphy_regif_chk(void); +static inline void ddrphy_regif_idle(void); +static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, + uint16_t cyc); +static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, + uint16_t *_js2); +static int16_t _f_scale_adj(int16_t ps); +static void ddrtbl_load(void); +static void ddr_config_sub(void); +static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz); +static void ddr_config_sub_h3v1x(void); +static void ddr_config(void); +static void dbsc_regset(void); +static void dbsc_regset_post(void); +static uint32_t dfi_init_start(void); +static void change_lpddr4_en(uint32_t mode); +static uint32_t set_term_code(void); +static void ddr_register_set(void); +static inline uint32_t wait_freqchgreq(uint32_t assert); +static inline void set_freqchgack(uint32_t assert); +static inline void set_dfifrequency(uint32_t freq); +static uint32_t pll3_freq(uint32_t on); +static void update_dly(void); +static uint32_t pi_training_go(void); +static uint32_t init_ddr(void); +static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick); +static uint32_t wdqdm_man1(void); +static uint32_t wdqdm_man(void); +static uint32_t rdqdm_man1(void); +static uint32_t rdqdm_man(void); + +static int32_t _find_change(uint64_t val, uint32_t dir); +static uint32_t _rx_offset_cal_updn(uint32_t code); +static uint32_t rx_offset_cal(void); +static uint32_t rx_offset_cal_hw(void); +static void adjust_rddqs_latency(void); +static void adjust_wpath_latency(void); + +struct ddrt_data { + int32_t init_temp; /* Initial Temperature (do) */ + uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ + uint32_t tcomp_cal[4]; /* Temp. compensated io-code (4 is for H3) */ +}; + +static struct ddrt_data tcal; + +static void pvtcode_update(void); +static void pvtcode_update2(void); +static void ddr_padcal_tcompensate_getinit(uint32_t override); + +/* load board configuration */ +#include "boot_init_dram_config.c" + +#ifndef DDR_FAST_INIT +static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; +static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; +static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; +static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; +static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2]; +static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn); +static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn); + +static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; +static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; +static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; +static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; +static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; +static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn); +static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn); +#endif/* DDR_FAST_INIT */ + +/* macro for channel selection loop */ +static inline uint32_t vch_nxt(uint32_t pos) +{ + uint32_t posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) { + if (ddr_phyvalid & (1U << posn)) + break; + } + return posn; +} + +#define foreach_vch(ch) \ +for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1)) + +#define foreach_ech(ch) \ +for (ch = 0; ch < DRAM_CH_CNT; ch++) + +/* Printing functions */ +#define MSG_LF(...) + +/* clock settings, reset control */ +static void cpg_write_32(uint32_t a, uint32_t v) +{ + mmio_write_32(CPG_CPGWPR, ~v); + mmio_write_32(a, v); +} + +static void pll3_control(uint32_t high) +{ + uint32_t data_l, data_div, data_mul, tmp_div; + + if (high) { + tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / + (brd_clk * ddr_mul) / 2; + data_mul = ((ddr_mul * tmp_div) - 1) << 24; + pll3_mode = 1; + loop_max = 2; + } else { + tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / + (brd_clk * ddr0800_mul) / 2; + data_mul = ((ddr0800_mul * tmp_div) - 1) << 24; + pll3_mode = 0; + loop_max = 8; + } + + switch (tmp_div) { + case 1: + data_div = 0; + break; + case 2: + case 3: + case 4: + data_div = tmp_div; + break; + default: + data_div = 6; + data_mul = (data_mul * tmp_div) / 3; + break; + } + data_mul = data_mul | (brd_clkdiva << 7); + + /* PLL3 disable */ + data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; + cpg_write_32(CPG_PLLECR, data_l); + dsb_sev(); + + if ((prr_product == PRR_PRODUCT_M3) || + ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) { + /* PLL3 DIV resetting(Lowest value:3) */ + data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, data_l); + dsb_sev(); + + /* zb3 clk stop */ + data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); + cpg_write_32(CPG_ZB3CKCR, data_l); + dsb_sev(); + + /* PLL3 enable */ + data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); + cpg_write_32(CPG_PLLECR, data_l); + dsb_sev(); + + do { + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); + dsb_sev(); + + /* PLL3 DIV resetting (Highest value:0) */ + data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, data_l); + dsb_sev(); + + /* DIV SET KICK */ + data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, data_l); + dsb_sev(); + + /* PLL3 multiplie set */ + cpg_write_32(CPG_PLL3CR, data_mul); + dsb_sev(); + + do { + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); + dsb_sev(); + + /* PLL3 DIV resetting(Target value) */ + data_l = (data_div << 16) | data_div | + (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); + cpg_write_32(CPG_FRQCRD, data_l); + dsb_sev(); + + /* DIV SET KICK */ + data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, data_l); + dsb_sev(); + + do { + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); + dsb_sev(); + + /* zb3 clk start */ + data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); + cpg_write_32(CPG_ZB3CKCR, data_l); + dsb_sev(); + + } else { /* H3Ver.3.0/M3N/V3H */ + + /* PLL3 multiplie set */ + cpg_write_32(CPG_PLL3CR, data_mul); + dsb_sev(); + + /* PLL3 DIV set(Target value) */ + data_l = (data_div << 16) | data_div | + (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); + cpg_write_32(CPG_FRQCRD, data_l); + + /* DIV SET KICK */ + data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, data_l); + dsb_sev(); + + /* PLL3 enable */ + data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); + cpg_write_32(CPG_PLLECR, data_l); + dsb_sev(); + + do { + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); + dsb_sev(); + } +} + +/* barrier */ +static inline void dsb_sev(void) +{ + __asm__ __volatile__("dsb sy"); +} + +/* DDR memory register access */ +static void wait_dbcmd(void) +{ + uint32_t data_l; + /* dummy read */ + data_l = mmio_read_32(DBSC_DBCMD); + dsb_sev(); + while (1) { + /* wait DBCMD 1=busy, 0=ready */ + data_l = mmio_read_32(DBSC_DBWAIT); + dsb_sev(); + if ((data_l & 0x00000001) == 0x00) + break; + } +} + +static void send_dbcmd(uint32_t cmd) +{ + /* dummy read */ + wait_dbcmd(); + mmio_write_32(DBSC_DBCMD, cmd); + dsb_sev(); +} + +/* DDRPHY register access (raw) */ +static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) +{ + uint32_t val; + uint32_t loop; + + val = 0; + if ((prr_product != PRR_PRODUCT_M3N) && + (prr_product != PRR_PRODUCT_V3H)) { + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + dsb_sev(); + + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { + dsb_sev(); + } + dsb_sev(); + + for (loop = 0; loop < loop_max; loop++) { + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + dsb_sev(); + } + (void)val; + } else { + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000); + dsb_sev(); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != + (regadd | 0x0000C000)) { + dsb_sev(); + }; + val = mmio_read_32(DBSC_DBPDRGA(phyno)); + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { + dsb_sev(); + }; + dsb_sev(); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { + dsb_sev(); + }; + + dsb_sev(); + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + dsb_sev(); + (void)val; + } + return val; +} + +static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) +{ + uint32_t val; + uint32_t loop; + + if ((prr_product != PRR_PRODUCT_M3N) && + (prr_product != PRR_PRODUCT_V3H)) { + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + dsb_sev(); + for (loop = 0; loop < loop_max; loop++) { + val = mmio_read_32(DBSC_DBPDRGA(phyno)); + dsb_sev(); + } + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + dsb_sev(); + + for (loop = 0; loop < loop_max; loop++) { + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + dsb_sev(); + } + } else { + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + dsb_sev(); + + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { + dsb_sev(); + }; + dsb_sev(); + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + dsb_sev(); + + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != + (regadd | 0x00008000)) { + dsb_sev(); + }; + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); + + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { + dsb_sev(); + }; + dsb_sev(); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + } + (void)val; +} + +static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) +{ + uint32_t ch; + uint32_t val; + uint32_t loop; + + if ((prr_product != PRR_PRODUCT_M3N) && + (prr_product != PRR_PRODUCT_V3H)) { + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDRGA(ch), regadd); + dsb_sev(); + } + + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDRGD(ch), regdata); + dsb_sev(); + } + + for (loop = 0; loop < loop_max; loop++) { + val = mmio_read_32(DBSC_DBPDRGD(0)); + dsb_sev(); + } + (void)val; + } else { + foreach_vch(ch) { + reg_ddrphy_write(ch, regadd, regdata); + dsb_sev(); + } + } +} + +static inline void ddrphy_regif_idle(void) +{ + uint32_t val; + + val = reg_ddrphy_read(0, ddr_regdef_adr(_reg_PI_INT_STATUS)); + dsb_sev(); + (void)val; +} + +/* DDRPHY register access (field modify) */ +static inline uint32_t ddr_regdef(uint32_t _regdef) +{ + return p_ddr_regdef_tbl[_regdef]; +} + +static inline uint32_t ddr_regdef_adr(uint32_t _regdef) +{ + return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]); +} + +static inline uint32_t ddr_regdef_lsb(uint32_t _regdef) +{ + return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]); +} + +static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, + uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + uint32_t regdef; + + regdef = ddr_regdef(_regdef); + adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20) + msk = 0xffffffff; + else + msk = ((1U << len) - 1) << lsb; + + tmp = reg_ddrphy_read(ch, adr); + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + reg_ddrphy_write(ch, adr, tmp); +} + +static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + uint32_t regdef; + + regdef = ddr_regdef(_regdef); + adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20) + msk = 0xffffffff; + else + msk = ((1U << len) - 1); + + tmp = reg_ddrphy_read(ch, adr); + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) +{ + ddr_setval_s(ch, 0, regdef, val); +} + +static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t ch; + + foreach_vch(ch) + ddr_setval_s(ch, slice, regdef, val); +} + +static void ddr_setval_ach(uint32_t regdef, uint32_t val) +{ + ddr_setval_ach_s(0, regdef, val); +} + +static void ddr_setval_ach_as(uint32_t regdef, uint32_t val) +{ + uint32_t slice; + + for (slice = 0; slice < SLICE_CNT; slice++) + ddr_setval_ach_s(slice, regdef, val); +} + +static uint32_t ddr_getval(uint32_t ch, uint32_t regdef) +{ + return ddr_getval_s(ch, 0, regdef); +} + +static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p) +{ + uint32_t ch; + + foreach_vch(ch) + p[ch] = ddr_getval_s(ch, 0, regdef); + return p[0]; +} + +static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p) +{ + uint32_t ch, slice; + uint32_t *pp; + + pp = p; + foreach_vch(ch) + for (slice = 0; slice < SLICE_CNT; slice++) + *pp++ = ddr_getval_s(ch, slice, regdef); + return p[0]; +} + +/* handling functions for setteing ddrphy value table */ +static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size) +{ + uint32_t i; + + for (i = 0; i < size; i++) { + to[i] = from[i]; + } +} + +static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + uint32_t adrmsk; + uint32_t regdef; + + regdef = ddr_regdef(_regdef); + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20) + msk = 0xffffffff; + else + msk = ((1U << len) - 1) << lsb; + + if (adr < 0x400) { + adrmsk = 0xff; + } else { + adrmsk = 0x7f; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + uint32_t adrmsk; + uint32_t regdef; + + regdef = ddr_regdef(_regdef); + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20) + msk = 0xffffffff; + else + msk = ((1U << len) - 1); + + if (adr < 0x400) { + adrmsk = 0xff; + } else { + adrmsk = 0x7f; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +/* DDRPHY register access handling */ +static uint32_t ddrphy_regif_chk(void) +{ + uint32_t tmp_ach[DRAM_CH_CNT]; + uint32_t ch; + uint32_t err; + uint32_t PI_VERSION_CODE; + + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3)) { + PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ + } else { + PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ + } + + ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach); + err = 0; + foreach_vch(ch) { + if (tmp_ach[ch] != PI_VERSION_CODE) + err = 1; + } + return err; +} + +/* functions and parameters for timing setting */ +struct _jedec_spec1 { + uint16_t fx3; + uint8_t rlwodbi; + uint8_t rlwdbi; + uint8_t WL; + uint8_t nwr; + uint8_t nrtp; + uint8_t MR1; + uint8_t MR2; +}; + +#define JS1_USABLEC_SPEC_LO 2 +#define JS1_USABLEC_SPEC_HI 5 +#define JS1_FREQ_TBL_NUM 8 +#define JS1_MR1(f) (0x04 | ((f) << 4)) +#define JS1_MR2(f) (0x00 | ((f) << 3) | (f)) +const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { + /* 533.333Mbps */ + { 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40 }, + /* 1066.666Mbps */ + { 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40 }, + /* 1600.000Mbps */ + { 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40 }, + /* 2133.333Mbps */ + { 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) }, + /* 2666.666Mbps */ + { 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) }, + /* 3200.000Mbps */ + { 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) }, + /* 3733.333Mbps */ + { 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) }, + /* 4266.666Mbps */ + { 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) } +}; + +struct _jedec_spec2 { + uint16_t ps; + uint16_t cyc; +}; + +#define js2_tsr 0 +#define js2_txp 1 +#define js2_trtp 2 +#define js2_trcd 3 +#define js2_trppb 4 +#define js2_trpab 5 +#define js2_tras 6 +#define js2_twr 7 +#define js2_twtr 8 +#define js2_trrd 9 +#define js2_tppd 10 +#define js2_tfaw 11 +#define js2_tdqsck 12 +#define js2_tckehcmd 13 +#define js2_tckelcmd 14 +#define js2_tckelpd 15 +#define js2_tmrr 16 +#define js2_tmrw 17 +#define js2_tmrd 18 +#define js2_tzqcalns 19 +#define js2_tzqlat 20 +#define js2_tiedly 21 +#define JS2_TBLCNT 22 + +#define js2_trcpb (JS2_TBLCNT) +#define js2_trcab (JS2_TBLCNT + 1) +#define js2_trfcab (JS2_TBLCNT + 2) +#define JS2_CNT (JS2_TBLCNT + 3) + +#ifndef JS2_DERATE +#define JS2_DERATE 0 +#endif +const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { + { +/*tSR */ {15000, 3}, +/*tXP */ {7500, 3}, +/*tRTP */ {7500, 8}, +/*tRCD */ {18000, 4}, +/*tRPpb */ {18000, 3}, +/*tRPab */ {21000, 3}, +/*tRAS */ {42000, 3}, +/*tWR */ {18000, 4}, +/*tWTR */ {10000, 8}, +/*tRRD */ {10000, 4}, +/*tPPD */ {0, 0}, +/*tFAW */ {40000, 0}, +/*tDQSCK*/ {3500, 0}, +/*tCKEHCMD*/ {7500, 3}, +/*tCKELCMD*/ {7500, 3}, +/*tCKELPD*/ {7500, 3}, +/*tMRR*/ {0, 8}, +/*tMRW*/ {10000, 10}, +/*tMRD*/ {14000, 10}, +/*tZQCALns*/ {1000 * 10, 0}, +/*tZQLAT*/ {30000, 10}, +/*tIEdly*/ {12500, 0} + }, { +/*tSR */ {15000, 3}, +/*tXP */ {7500, 3}, +/*tRTP */ {7500, 8}, +/*tRCD */ {19875, 4}, +/*tRPpb */ {19875, 3}, +/*tRPab */ {22875, 3}, +/*tRAS */ {43875, 3}, +/*tWR */ {18000, 4}, +/*tWTR */ {10000, 8}, +/*tRRD */ {11875, 4}, +/*tPPD */ {0, 0}, +/*tFAW */ {40000, 0}, +/*tDQSCK*/ {3600, 0}, +/*tCKEHCMD*/ {7500, 3}, +/*tCKELCMD*/ {7500, 3}, +/*tCKELPD*/ {7500, 3}, +/*tMRR*/ {0, 8}, +/*tMRW*/ {10000, 10}, +/*tMRD*/ {14000, 10}, +/*tZQCALns*/ {1000 * 10, 0}, +/*tZQLAT*/ {30000, 10}, +/*tIEdly*/ {12500, 0} + } +}; + +const uint16_t jedec_spec2_trfc_ab[7] = { +/* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */ + 130, 180, 180, 280, 280, 560, 560 +}; + +static uint32_t js1_ind; +static uint16_t js2[JS2_CNT]; +static uint8_t RL; +static uint8_t WL; + +static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, + uint16_t cyc) +{ + uint32_t tmp; + uint32_t div; + + tmp = (((uint32_t)(ps) + 9) / 10) * _ddr_mbps; + div = tmp / (200000 * _ddr_mbpsdiv); + if (tmp != (div * 200000 * _ddr_mbpsdiv)) + div = div + 1; + + if (div > cyc) + return (uint16_t)div; + return cyc; +} + +static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, + uint16_t *_js2) +{ + int i; + + for (i = 0; i < JS2_TBLCNT; i++) { + _js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv, + 1UL * jedec_spec2[JS2_DERATE][i].ps, + jedec_spec2[JS2_DERATE][i].cyc); + } + + _js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb]; + _js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab]; +} + +/* scaler for DELAY value */ +static int16_t _f_scale_adj(int16_t ps) +{ + int32_t tmp; + /* + * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000; + * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125 + * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 + */ + tmp = + (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps / + (int32_t)ddr_mbpsdiv; + tmp = (int32_t)tmp / (int32_t)15625; + + return (int16_t)tmp; +} + +static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = { + { + _reg_PI_MR1_DATA_F0_0, + _reg_PI_MR1_DATA_F0_1, + _reg_PI_MR1_DATA_F0_2, + _reg_PI_MR1_DATA_F0_3}, + { + _reg_PI_MR1_DATA_F1_0, + _reg_PI_MR1_DATA_F1_1, + _reg_PI_MR1_DATA_F1_2, + _reg_PI_MR1_DATA_F1_3} +}; + +static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = { + { + _reg_PI_MR2_DATA_F0_0, + _reg_PI_MR2_DATA_F0_1, + _reg_PI_MR2_DATA_F0_2, + _reg_PI_MR2_DATA_F0_3}, + { + _reg_PI_MR2_DATA_F1_0, + _reg_PI_MR2_DATA_F1_1, + _reg_PI_MR2_DATA_F1_2, + _reg_PI_MR2_DATA_F1_3} +}; + +static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = { + { + _reg_PI_MR3_DATA_F0_0, + _reg_PI_MR3_DATA_F0_1, + _reg_PI_MR3_DATA_F0_2, + _reg_PI_MR3_DATA_F0_3}, + { + _reg_PI_MR3_DATA_F1_0, + _reg_PI_MR3_DATA_F1_1, + _reg_PI_MR3_DATA_F1_2, + _reg_PI_MR3_DATA_F1_3} +}; + +const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = { + { + _reg_PI_MR11_DATA_F0_0, + _reg_PI_MR11_DATA_F0_1, + _reg_PI_MR11_DATA_F0_2, + _reg_PI_MR11_DATA_F0_3}, + { + _reg_PI_MR11_DATA_F1_0, + _reg_PI_MR11_DATA_F1_1, + _reg_PI_MR11_DATA_F1_2, + _reg_PI_MR11_DATA_F1_3} +}; + +const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = { + { + _reg_PI_MR12_DATA_F0_0, + _reg_PI_MR12_DATA_F0_1, + _reg_PI_MR12_DATA_F0_2, + _reg_PI_MR12_DATA_F0_3}, + { + _reg_PI_MR12_DATA_F1_0, + _reg_PI_MR12_DATA_F1_1, + _reg_PI_MR12_DATA_F1_2, + _reg_PI_MR12_DATA_F1_3} +}; + +const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = { + { + _reg_PI_MR14_DATA_F0_0, + _reg_PI_MR14_DATA_F0_1, + _reg_PI_MR14_DATA_F0_2, + _reg_PI_MR14_DATA_F0_3}, + { + _reg_PI_MR14_DATA_F1_0, + _reg_PI_MR14_DATA_F1_1, + _reg_PI_MR14_DATA_F1_2, + _reg_PI_MR14_DATA_F1_3} +}; + +/* + * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA ) + */ +static void regif_pll_wa(void) +{ + uint32_t ch; + + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + // PLL setting for PHY : H3 Ver.1.x + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), + (0x0064U << + ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_PLL_CTRL)); + + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_LP4_BOOT_PLL_CTRL)); + + } else { + /* PLL setting for PHY : M3-W/M3-N/V3H/H3 Ver.2.0 or later */ + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), + (0x5064U << + ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); + + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), + (ddrtbl_getval + (_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_PLL_CTRL_TOP) << 16) | + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_PLL_CTRL)); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_PLL_CTRL_CA)); + + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), + (ddrtbl_getval + (_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) | + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_LP4_BOOT_PLL_CTRL)); + reg_ddrphy_write_a(ddr_regdef_adr + (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL), + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_LP4_BOOT_TOP_PLL_CTRL + )); + } + + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), + _cnf_DDR_PHY_ADR_G_REGSET + [ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - + DDR_PHY_ADR_G_REGSET_OFS]); + + /* protect register interface */ + ddrphy_regif_idle(); + pll3_control(0); + + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + /* non */ + } else { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN), + (0x01U << + ddr_regdef_lsb(_reg_PHY_DLL_RST_EN))); + ddrphy_regif_idle(); + } + + /* init start */ + /* dbdficnt0: + * dfi_dram_clk_disable=1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start =0 + */ + foreach_vch(ch) + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); + dsb_sev(); + + /* dbdficnt0: + * dfi_dram_clk_disable=1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start =1 + */ + foreach_vch(ch) + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); + dsb_sev(); + + foreach_ech(ch) + if ((board_cnf->phyvalid) & BIT(ch)) + while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) + ; + dsb_sev(); +} + +/* load table data into DDR registers */ +static void ddrtbl_load(void) +{ + uint32_t i; + uint32_t slice; + uint32_t csab; + uint32_t adr; + uint32_t data_l; + uint32_t tmp[3]; + uint16_t dataS; + + /* TIMING REGISTERS */ + /* search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) { + if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) + break; + } + if (i > JS1_USABLEC_SPEC_HI) + js1_ind = JS1_USABLEC_SPEC_HI; + else + js1_ind = i; + + if (board_cnf->dbi_en) + RL = js1[js1_ind].rlwdbi; + else + RL = js1[js1_ind].rlwodbi; + + WL = js1[js1_ind].WL; + + /* calculate jedec_spec2 */ + _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); + + /* PREPARE TBL */ + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { + /* H3 Ver.1.x */ + _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_H3, + DDR_PHY_SLICE_REGSET_NUM_H3); + _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_H3, + DDR_PHY_ADR_V_REGSET_NUM_H3); + _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, + DDR_PHY_ADR_I_REGSET_H3, + DDR_PHY_ADR_I_REGSET_NUM_H3); + _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_H3, + DDR_PHY_ADR_G_REGSET_NUM_H3); + _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3, + DDR_PI_REGSET_NUM_H3); + + DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_H3; + DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_H3; + DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_H3; + DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_H3; + DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3; + DDR_PHY_SLICE_REGSET_SIZE = + DDR_PHY_SLICE_REGSET_SIZE_H3; + DDR_PHY_ADR_V_REGSET_SIZE = + DDR_PHY_ADR_V_REGSET_SIZE_H3; + DDR_PHY_ADR_I_REGSET_SIZE = + DDR_PHY_ADR_I_REGSET_SIZE_H3; + DDR_PHY_ADR_G_REGSET_SIZE = + DDR_PHY_ADR_G_REGSET_SIZE_H3; + DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3; + DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_H3; + DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_H3; + DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_H3; + DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_H3; + DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3; + + DDR_PHY_ADR_I_NUM = 1; + } else { + /* H3 Ver.2.0 or later */ + _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_H3VER2, + DDR_PHY_SLICE_REGSET_NUM_H3VER2); + _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_H3VER2, + DDR_PHY_ADR_V_REGSET_NUM_H3VER2); + _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_H3VER2, + DDR_PHY_ADR_G_REGSET_NUM_H3VER2); + _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3VER2, + DDR_PI_REGSET_NUM_H3VER2); + + DDR_PHY_SLICE_REGSET_OFS = + DDR_PHY_SLICE_REGSET_OFS_H3VER2; + DDR_PHY_ADR_V_REGSET_OFS = + DDR_PHY_ADR_V_REGSET_OFS_H3VER2; + DDR_PHY_ADR_G_REGSET_OFS = + DDR_PHY_ADR_G_REGSET_OFS_H3VER2; + DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3VER2; + DDR_PHY_SLICE_REGSET_SIZE = + DDR_PHY_SLICE_REGSET_SIZE_H3VER2; + DDR_PHY_ADR_V_REGSET_SIZE = + DDR_PHY_ADR_V_REGSET_SIZE_H3VER2; + DDR_PHY_ADR_G_REGSET_SIZE = + DDR_PHY_ADR_G_REGSET_SIZE_H3VER2; + DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3VER2; + DDR_PHY_SLICE_REGSET_NUM = + DDR_PHY_SLICE_REGSET_NUM_H3VER2; + DDR_PHY_ADR_V_REGSET_NUM = + DDR_PHY_ADR_V_REGSET_NUM_H3VER2; + DDR_PHY_ADR_G_REGSET_NUM = + DDR_PHY_ADR_G_REGSET_NUM_H3VER2; + DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3VER2; + + DDR_PHY_ADR_I_NUM = 0; + } + } else if (prr_product == PRR_PRODUCT_M3) { + /* M3-W */ + _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3); + _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_M3, DDR_PHY_ADR_V_REGSET_NUM_M3); + _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, + DDR_PHY_ADR_I_REGSET_M3, DDR_PHY_ADR_I_REGSET_NUM_M3); + _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_M3, DDR_PHY_ADR_G_REGSET_NUM_M3); + _tblcopy(_cnf_DDR_PI_REGSET, + DDR_PI_REGSET_M3, DDR_PI_REGSET_NUM_M3); + + DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3; + DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3; + DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3; + DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3; + DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3; + DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3; + DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3; + DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3; + DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3; + DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3; + DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3; + DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3; + DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3; + DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3; + DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3; + + DDR_PHY_ADR_I_NUM = 2; + } else { + /* M3-N/V3H */ + _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_M3N, + DDR_PHY_SLICE_REGSET_NUM_M3N); + _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_M3N, + DDR_PHY_ADR_V_REGSET_NUM_M3N); + _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, DDR_PHY_ADR_I_REGSET_M3N, + DDR_PHY_ADR_I_REGSET_NUM_M3N); + _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_M3N, + DDR_PHY_ADR_G_REGSET_NUM_M3N); + _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_M3N, + DDR_PI_REGSET_NUM_M3N); + + DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3N; + DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3N; + DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3N; + DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3N; + DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3N; + DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3N; + DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3N; + DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3N; + DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3N; + DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3N; + DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3N; + DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3N; + DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3N; + DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3N; + DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3N; + + DDR_PHY_ADR_I_NUM = 2; + } + + /* PLL CODE CHANGE */ + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, + 0x1142); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142); + } + + /* on fly gate adjust */ + if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) { + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_ON_FLY_GATE_ADJUST_EN, 0x00); + } + + /* Adjust PI parameters */ +#ifdef _def_LPDDR4_ODT + for (i = 0; i < 2; i++) { + for (csab = 0; csab < CSAB_CNT; csab++) { + ddrtbl_setval(_cnf_DDR_PI_REGSET, + reg_pi_mr11_data_fx_csx[i][csab], + _def_LPDDR4_ODT); + } + } +#endif /* _def_LPDDR4_ODT */ + +#ifdef _def_LPDDR4_VREFCA + for (i = 0; i < 2; i++) { + for (csab = 0; csab < CSAB_CNT; csab++) { + ddrtbl_setval(_cnf_DDR_PI_REGSET, + reg_pi_mr12_data_fx_csx[i][csab], + _def_LPDDR4_VREFCA); + } + } +#endif /* _def_LPDDR4_VREFCA */ + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; + if (js2[js2_tiedly] > (RL)) + js2[js2_tiedly] = RL; + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) { + js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { + js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); + } + + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + if ((js2[js2_tiedly]) >= 0x1e) + dataS = 0x1e; + else + dataS = js2[js2_tiedly]; + } else { + if ((js2[js2_tiedly]) >= 0x0e) + dataS = 0x0e; + else + dataS = js2[js2_tiedly]; + } + + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, + (dataS - 2)); + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_PHY_RDDATA_EN_OE_DLY, dataS); + } + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS); + + if (ddrtbl_getval + (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) { + data_l = WL - 1; + } else { + data_l = WL; + } + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l); + + if (board_cnf->dbi_en) { + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, + 0x01); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_PHY_WDQLVL_DATADM_MASK, 0x000); + } else { + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, + 0x00); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_PHY_WDQLVL_DATADM_MASK, 0x100); + } + + tmp[0] = js1[js1_ind].MR1; + tmp[1] = js1[js1_ind].MR2; + data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); + if (board_cnf->dbi_en) + tmp[2] = data_l | 0xc0; + else + tmp[2] = data_l & (~0xc0); + + for (i = 0; i < 2; i++) { + for (csab = 0; csab < CSAB_CNT; csab++) { + ddrtbl_setval(_cnf_DDR_PI_REGSET, + reg_pi_mr1_data_fx_csx[i][csab], tmp[0]); + ddrtbl_setval(_cnf_DDR_PI_REGSET, + reg_pi_mr2_data_fx_csx[i][csab], tmp[1]); + ddrtbl_setval(_cnf_DDR_PI_REGSET, + reg_pi_mr3_data_fx_csx[i][csab], tmp[2]); + } + } + + /* DDRPHY INT START */ + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + /* non */ + } else { + regif_pll_wa(); + } + + /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */ + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), + BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); + + /* SET DATA SLICE TABLE */ + for (slice = 0; slice < SLICE_CNT; slice++) { + adr = + DDR_PHY_SLICE_REGSET_OFS + + DDR_PHY_SLICE_REGSET_SIZE * slice; + for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, + _cnf_DDR_PHY_SLICE_REGSET[i]); + } + } + + /* SET ADR SLICE TABLE */ + adr = DDR_PHY_ADR_V_REGSET_OFS; + for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); + } + + if (((prr_product == PRR_PRODUCT_M3) || + (prr_product == PRR_PRODUCT_M3N)) && + ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40)) + != 0x00)) { + adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE; + for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, + _cnf_DDR_PHY_ADR_V_REGSET[i]); + } + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_ADR_DISABLE, 0x02); + DDR_PHY_ADR_I_NUM -= 1; + ddr_phycaslice = 1; + +#ifndef _def_LPDDR4_ODT + for (i = 0; i < 2; i++) { + for (csab = 0; csab < CSAB_CNT; csab++) { + ddrtbl_setval(_cnf_DDR_PI_REGSET, + reg_pi_mr11_data_fx_csx[i][csab], + 0x66); + } + } +#endif/* _def_LPDDR4_ODT */ + } else { + ddr_phycaslice = 0; + } + + if (DDR_PHY_ADR_I_NUM > 0) { + for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) { + adr = + DDR_PHY_ADR_I_REGSET_OFS + + DDR_PHY_ADR_I_REGSET_SIZE * slice; + for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, + _cnf_DDR_PHY_ADR_I_REGSET + [i]); + } + } + } + + /* SET ADRCTRL SLICE TABLE */ + adr = DDR_PHY_ADR_G_REGSET_OFS; + for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); + } + + /* SET PI REGISTERS */ + adr = DDR_PI_REGSET_OFS; + for (i = 0; i < DDR_PI_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); + } +} + +/* CONFIGURE DDR REGISTERS */ +static void ddr_config_sub(void) +{ + uint32_t i; + uint32_t ch, slice; + uint32_t data_l; + uint32_t tmp; + uint8_t high_byte[SLICE_CNT]; + const uint32_t _par_CALVL_DEVICE_MAP = 1; + + foreach_vch(ch) { + /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ + for (slice = 0; slice < SLICE_CNT; slice++) { + high_byte[slice] = + (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2; + ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, + board_cnf->ch[ch].dq_swap[slice]); + ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, + board_cnf->ch[ch].dm_swap[slice]); + if (high_byte[slice]) { + /* HIGHER 16 BYTE */ + ddr_setval_s(ch, slice, + _reg_PHY_CALVL_VREF_DRIVING_SLICE, + 0x00); + } else { + /* LOWER 16 BYTE */ + ddr_setval_s(ch, slice, + _reg_PHY_CALVL_VREF_DRIVING_SLICE, + 0x01); + } + } + + /* BOARD SETTINGS (CA,ADDR_SEL) */ + data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) | + 0x00888888; + + /* --- ADR_CALVL_SWIZZLE --- */ + if (prr_product == PRR_PRODUCT_M3) { + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, + 0x00000000); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, + 0x00000000); + ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, + _par_CALVL_DEVICE_MAP); + } else { + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); + ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, + _par_CALVL_DEVICE_MAP); + } + + /* --- ADR_ADDR_SEL --- */ + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) { + data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; + } else { + data_l = 0; + tmp = board_cnf->ch[ch].ca_swap; + for (i = 0; i < 6; i++) { + data_l |= ((tmp & 0x0f) << (i * 5)); + tmp = tmp >> 4; + } + } + ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l); + if (ddr_phycaslice == 1) { + /* ----------- adr slice2 swap ----------- */ + tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40); + data_l = (tmp & 0x00ffffff) | 0x00888888; + + /* --- ADR_CALVL_SWIZZLE --- */ + if (prr_product == PRR_PRODUCT_M3) { + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE0_0, + data_l); + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE1_0, + 0x00000000); + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE0_1, + data_l); + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE1_1, + 0x00000000); + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_DEVICE_MAP, + _par_CALVL_DEVICE_MAP); + } else { + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE0, + data_l); + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE1, + 0x00000000); + ddr_setval_s(ch, 2, + _reg_PHY_CALVL_DEVICE_MAP, + _par_CALVL_DEVICE_MAP); + } + + /* --- ADR_ADDR_SEL --- */ + data_l = 0; + for (i = 0; i < 6; i++) { + data_l |= ((tmp & 0x0f) << (i * 5)); + tmp = tmp >> 4; + } + + ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l); + } + + /* BOARD SETTINGS (BYTE_ORDER_SEL) */ + if (prr_product == PRR_PRODUCT_M3) { + /* --- DATA_BYTE_SWAP --- */ + data_l = 0; + tmp = board_cnf->ch[ch].dqs_swap; + for (i = 0; i < 4; i++) { + data_l |= ((tmp & 0x03) << (i * 2)); + tmp = tmp >> 4; + } + } else { + /* --- DATA_BYTE_SWAP --- */ + data_l = board_cnf->ch[ch].dqs_swap; + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, + (data_l) & 0x0f); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, + (data_l >> 4 * 1) & 0x0f); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2, + (data_l >> 4 * 2) & 0x0f); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3, + (data_l >> 4 * 3) & 0x0f); + + ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00); + } + ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l); + } +} + +static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) +{ + uint32_t slice; + uint32_t tmp; + uint32_t tgt; + + if (ddr_csn / 2) { + tgt = 3; + } else { + tgt = 1; + } + + for (slice = 0; slice < SLICE_CNT; slice++) { + tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + if (tgt == tmp) + break; + } + tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; + if (slice % 2) + tmp |= 0x00888888; + *p_swz = tmp; +} + +static void ddr_config_sub_h3v1x(void) +{ + uint32_t ch, slice; + uint32_t data_l; + uint32_t tmp; + uint8_t high_byte[SLICE_CNT]; + uint32_t ca_swizzle; + uint32_t ca; + uint32_t csmap; + uint32_t o_inv; + uint32_t inv; + uint32_t bit_soc; + uint32_t bit_mem; + uint32_t j; + + const uint8_t o_mr15 = 0x55; + const uint8_t o_mr20 = 0x55; + const uint16_t o_mr32_mr40 = 0x5a3c; + + foreach_vch(ch) { + /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ + csmap = 0; + for (slice = 0; slice < SLICE_CNT; slice++) { + tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & + 0x0f; + high_byte[slice] = tmp % 2; + if (tmp == 1 && (slice >= 2)) + csmap |= 0x05; + if (tmp == 3 && (slice >= 2)) + csmap |= 0x50; + ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING, + board_cnf->ch[ch].dq_swap[slice]); + if (high_byte[slice]) { + /* HIGHER 16 BYTE */ + ddr_setval_s(ch, slice, + _reg_PHY_CALVL_VREF_DRIVING_SLICE, + 0x00); + } else { + /* LOWER 16 BYTE */ + ddr_setval_s(ch, slice, + _reg_PHY_CALVL_VREF_DRIVING_SLICE, + 0x01); + } + } + /* BOARD SETTINGS (CA,ADDR_SEL) */ + ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; + ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca); + ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap); + + get_ca_swizzle(ch, 0, &ca_swizzle); + + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, ca_swizzle); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, 0x00000000); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); + ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01); + + for (slice = 0; slice < SLICE_CNT; slice++) { + ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM, + 0x01); + ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START, + 0x08); + + if (high_byte[slice]) + o_inv = o_mr20; + else + o_inv = o_mr15; + + tmp = board_cnf->ch[ch].dq_swap[slice]; + inv = 0; + j = 0; + for (bit_soc = 0; bit_soc < 8; bit_soc++) { + bit_mem = (tmp >> (4 * bit_soc)) & 0x0f; + j |= (1U << bit_mem); + if (o_inv & (1U << bit_mem)) + inv |= (1U << bit_soc); + } + data_l = o_mr32_mr40; + if (!high_byte[slice]) + data_l |= (inv << 24); + if (high_byte[slice]) + data_l |= (inv << 16); + ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8, + data_l); + } + } +} + +static void ddr_config(void) +{ + int32_t i; + uint32_t ch, slice; + uint32_t data_l; + uint32_t tmp; + int8_t _adj; + int16_t adj; + uint32_t dq; + union { + uint32_t ui32[4]; + uint8_t ui8[16]; + } patt; + uint16_t patm; + + /* configure ddrphy registers */ + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + ddr_config_sub_h3v1x(); + } else { /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ + ddr_config_sub(); + } + + /* WDQ_USER_PATT */ + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + patm = 0; + for (i = 0; i < 16; i++) { + tmp = board_cnf->ch[ch].wdqlvl_patt[i]; + patt.ui8[i] = tmp & 0xff; + if (tmp & 0x100) + patm |= (1U << i); + } + ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0, + patt.ui32[0]); + ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1, + patt.ui32[1]); + ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2, + patt.ui32[2]); + ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3, + patt.ui32[3]); + ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm); + } + } + + /* CACS DLY */ + data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), + 0x00U); + foreach_vch(ch) { + for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4; i++) { + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); + ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, + _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], + data_l + adj); + reg_ddrphy_write(ch, + ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), + _cnf_DDR_PHY_ADR_V_REGSET + [ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - + DDR_PHY_ADR_V_REGSET_OFS]); + } + + for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); + i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], + data_l + adj); + reg_ddrphy_write(ch, + ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), + _cnf_DDR_PHY_ADR_G_REGSET + [ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - + DDR_PHY_ADR_G_REGSET_OFS]); + } + + if (ddr_phycaslice == 1) { + for (i = 0; i < 6; i++) { + adj = _f_scale_adj + (board_cnf->ch[ch].cacs_adj + [i + + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); + ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, + _reg_PHY_CLK_CACS_SLAVE_DELAY_X + [i], + data_l + adj); + reg_ddrphy_write(ch, + ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + + 0x0100, + _cnf_DDR_PHY_ADR_V_REGSET + [ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - + DDR_PHY_ADR_V_REGSET_OFS]); + } + } + } + + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), + BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + + /* WDQDM DLY */ + data_l = board_cnf->dqdm_dly_w; + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (i = 0; i <= 8; i++) { + dq = slice * 8 + i; + if (i == 8) + _adj = board_cnf->ch[ch].dm_adj_w[slice]; + else + _adj = board_cnf->ch[ch].dq_adj_w[dq]; + adj = _f_scale_adj(_adj); + ddr_setval_s(ch, slice, + _reg_PHY_CLK_WRX_SLAVE_DELAY[i], + data_l + adj); + } + } + } + + /* RDQDM DLY */ + data_l = board_cnf->dqdm_dly_r; + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (i = 0; i <= 8; i++) { + dq = slice * 8 + i; + if (i == 8) + _adj = board_cnf->ch[ch].dm_adj_r[slice]; + else + _adj = board_cnf->ch[ch].dq_adj_r[dq]; + adj = _f_scale_adj(_adj); + ddr_setval_s(ch, slice, + _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY + [i], data_l + adj); + ddr_setval_s(ch, slice, + _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY + [i], data_l + adj); + } + } + } +} + +/* DBSC register setting functions */ +static void dbsc_regset_pre(void) +{ + uint32_t ch, csab; + uint32_t data_l; + + /* PRIMARY SETTINGS */ + /* LPDDR4, BL=16, DFI interface */ + mmio_write_32(DBSC_DBKIND, 0x0000000a); + mmio_write_32(DBSC_DBBL, 0x00000002); + mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); + + /* FREQRATIO=2 */ + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + + /* Chanel map (H3 Ver.1.x) */ + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); + + /* DRAM SIZE REGISTER: + * set all ranks as density=0(4Gb) for PHY initialization + */ + foreach_vch(ch) { + for (csab = 0; csab < 4; csab++) { + mmio_write_32(DBSC_DBMEMCONF(ch, csab), + DBMEMCONF_REGD(0)); + } + } + + if (prr_product == PRR_PRODUCT_M3) { + data_l = 0xe4e4e4e4; + foreach_ech(ch) { + if ((ddr_phyvalid & (1U << ch))) + data_l = (data_l & (~(0x000000FF << (ch * 8)))) + | (((board_cnf->ch[ch].dqs_swap & 0x0003) + | ((board_cnf->ch[ch].dqs_swap & 0x0030) + >> 2) + | ((board_cnf->ch[ch].dqs_swap & 0x0300) + >> 4) + | ((board_cnf->ch[ch].dqs_swap & 0x3000) + >> 6)) << (ch * 8)); + } + mmio_write_32(DBSC_DBBSWAP, data_l); + } +} + +static void dbsc_regset(void) +{ + int32_t i; + uint32_t ch; + uint32_t data_l; + uint32_t data_l2; + uint32_t tmp[4]; + + /* RFC */ + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) && + (max_density == 0)) { + js2[js2_trfcab] = + _f_scale(ddr_mbps, ddr_mbpsdiv, + 1UL * jedec_spec2_trfc_ab[1] * 1000, 0); + } else { + js2[js2_trfcab] = + _f_scale(ddr_mbps, ddr_mbpsdiv, + 1UL * jedec_spec2_trfc_ab[max_density] * + 1000, 0); + } + + /* DBTR0.CL : RL */ + mmio_write_32(DBSC_DBTR(0), RL); + + /* DBTR1.CWL : WL */ + mmio_write_32(DBSC_DBTR(1), WL); + + /* DBTR2.AL : 0 */ + mmio_write_32(DBSC_DBTR(2), 0); + + /* DBTR3.TRCD: tRCD */ + mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]); + + /* DBTR4.TRPA,TRP: tRPab,tRPpb */ + mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]); + + /* DBTR5.TRC : use tRCpb */ + mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]); + + /* DBTR6.TRAS : tRAS */ + mmio_write_32(DBSC_DBTR(6), js2[js2_tras]); + + /* DBTR7.TRRD : tRRD */ + mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]); + + /* DBTR8.TFAW : tFAW */ + mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]); + + /* DBTR9.TRDPR : tRTP */ + mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]); + + /* DBTR10.TWR : nwr */ + mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr); + + /* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */ + mmio_write_32(DBSC_DBTR(11), + RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2); + + /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ + data_l = WL + 1 + (16 / 2) + js2[js2_twtr]; + mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l); + + /* DBTR13.TRFCAB : tRFCab */ + mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab])); + + /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */ + mmio_write_32(DBSC_DBTR(14), + (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd])); + + /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */ + mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd])); + + /* DBTR16 */ + /* WDQL : tphy_wrlat + tphy_wrdata */ + tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1); + /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0 + * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0 + */ + tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1); + /* DQL : tphy_rdlat + trdata_en */ + /* it is not important for dbsc */ + tmp[2] = RL + 16; + /* DQIENLTNCY : trdata_en */ + tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1; + mmio_write_32(DBSC_DBTR(16), + (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR24 */ + /* WRCSLAT = WRLAT -5 */ + tmp[0] -= 5; + /* WRCSGAP = 5 */ + tmp[1] = 5; + /* RDCSLAT = RDLAT_ADJ +2 */ + if (prr_product == PRR_PRODUCT_M3) { + tmp[2] = tmp[3]; + } else { + tmp[2] = tmp[3] + 2; + } + /* RDCSGAP = 6 */ + if (prr_product == PRR_PRODUCT_M3) { + tmp[3] = 4; + } else { + tmp[3] = 6; + } + mmio_write_32(DBSC_DBTR(24), + (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */ + mmio_write_32(DBSC_DBTR(17), + (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16)); + + /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ + mmio_write_32(DBSC_DBTR(18), 0); + + /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */ + mmio_write_32(DBSC_DBTR(19), 0); + + /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ + data_l = js2[js2_trfcab] + js2[js2_tckehcmd]; + mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l); + + /* DBTR21.TCCD */ + /* DBTR23.TCCD */ + /* H3 Ver.1.0 cannot use TBTR23 feature */ + if (ddr_tccd == 8 && + !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10)) + ) { + data_l = 8; + mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); + mmio_write_32(DBSC_DBTR(23), 0x00000002); + } else if (ddr_tccd <= 11) { + data_l = 11; + mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); + mmio_write_32(DBSC_DBTR(23), 0x00000000); + } else { + data_l = ddr_tccd; + mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); + mmio_write_32(DBSC_DBTR(23), 0x00000000); + } + + /* DBTR22.ZQLAT : */ + data_l = js2[js2_tzqcalns] * 100; /* 1000 * 1000 ps */ + data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20); + mmio_write_32(DBSC_DBTR(22), data_l); + + /* DBTR25 : do not use in LPDDR4 */ + mmio_write_32(DBSC_DBTR(25), 0); + + /* DBRNK : */ + /* + * DBSC_DBRNK2 rkrr + * DBSC_DBRNK3 rkrw + * DBSC_DBRNK4 rkwr + * DBSC_DBRNK5 rkww + */ +#define _par_DBRNK_VAL (0x7007) + + for (i = 0; i < 4; i++) { + data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11) && (i == 0)) { + data_l += 1; + } + data_l2 = 0; + foreach_vch(ch) { + data_l2 = data_l2 | (data_l << (4 * ch)); + } + mmio_write_32(DBSC_DBRNK(2 + i), data_l2); + } + mmio_write_32(DBSC_DBADJ0, 0x00000000); + + /* timing registers for Scheduler */ + /* SCFCTST0 */ + /* SCFCTST0 ACT-ACT */ + tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps; + /* SCFCTST0 RDA-ACT */ + tmp[2] = + 1UL * ((16 / 2) + js2[js2_trtp] - 8 + + js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps; + /* SCFCTST0 WRA-ACT */ + tmp[1] = + 1UL * (WL + 1 + (16 / 2) + + js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps; + /* SCFCTST0 PRE-ACT */ + tmp[0] = 1UL * js2[js2_trppb]; + mmio_write_32(DBSC_SCFCTST0, + (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* SCFCTST1 */ + /* SCFCTST1 RD-WR */ + tmp[3] = + 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xff) * 800 * ddr_mbpsdiv / + ddr_mbps; + /* SCFCTST1 WR-RD */ + tmp[2] = + 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv / + ddr_mbps; + /* SCFCTST1 ACT-RD/WR */ + tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps; + /* SCFCTST1 ASYNCOFS */ + tmp[0] = 12; + mmio_write_32(DBSC_SCFCTST1, + (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBSCHRW1 */ + /* DBSCHRW1 SCTRFCAB */ + tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps; + data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) + + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; + if (tmp[0] < data_l) + tmp[0] = data_l; + + if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { + mmio_write_32(DBSC_DBSCHRW1, tmp[0] + + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / + ddr_mbps - 3); + } else { + mmio_write_32(DBSC_DBSCHRW1, tmp[0] + + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / + ddr_mbps); + } + + /* QOS and CAM */ +#ifdef ddr_qos_init_setting /* only for non qos_init */ + /*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */ + mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); + /*0(fillunit),8(dirtymax),4(dirtymin) */ + mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); + /*stop_tolerance */ + mmio_write_32(DBSC_DBSCHRW0, 0x22421111); + /*rd-wr/wr-rd toggle priority */ + mmio_write_32(DBSC_SCFCTST2, 0x012F1123); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037); + + /* QoS Settings */ + mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U); + mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U); + mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U); + mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U); + mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U); + mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U); + mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U); + mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U); + mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U); + mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U); + mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U); + mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U); + mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U); + mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U); + mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U); + mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U); + mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U); + + mmio_write_32(QOSCTRL_RAEN, 0x00000001U); +#endif /* ddr_qos_init_setting */ + /* H3 Ver.1.1 need to set monitor function */ + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { + mmio_write_32(DBSC_DBMONCONF4, 0x00700000); + } + + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut == PRR_PRODUCT_10) { + /* resrdis, simple mode, sc off */ + mmio_write_32(DBSC_DBBCAMDIS, 0x00000007); + } else if (prr_cut == PRR_PRODUCT_11) { + /* resrdis, simple mode */ + mmio_write_32(DBSC_DBBCAMDIS, 0x00000005); + } else if (prr_cut < PRR_PRODUCT_30) { + /* H3 Ver.2.0 */ + /* resrdis */ + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + } else { /* H3 Ver.3.0(include H3N) */ + /* exprespque */ + mmio_write_32(DBSC_DBBCAMDIS, 0x00000010); + } + } else { /* M3-W/M3-N/V3H */ + /* resrdis */ + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + } +} + +static void dbsc_regset_post(void) +{ + uint32_t ch, cs; + uint32_t data_l; + uint32_t slice, rdlat_max, rdlat_min; + + rdlat_max = 0; + rdlat_min = 0xffff; + foreach_vch(ch) { + for (cs = 0; cs < CS_CNT; cs++) { + if ((ch_have_this_cs[cs] & (1U << ch)) != 0) { + for (slice = 0; slice < SLICE_CNT; slice++) { + ddr_setval_s(ch, slice, + _reg_PHY_PER_CS_TRAINING_INDEX, + cs); + data_l = ddr_getval_s(ch, slice, + _reg_PHY_RDDQS_LATENCY_ADJUST); + if (data_l > rdlat_max) + rdlat_max = data_l; + if (data_l < rdlat_min) + rdlat_min = data_l; + } + } + } + } + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) { + mmio_write_32(DBSC_DBTR(24), + ((rdlat_max * 2 - rdlat_min + 4) << 24) + + ((rdlat_min + 2) << 16) + + mmio_read_32(DBSC_DBTR(24))); + } else { + mmio_write_32(DBSC_DBTR(24), + ((rdlat_max + 2) << 24) + + ((rdlat_max + 2) << 16) + + mmio_read_32(DBSC_DBTR(24))); + } + + /* set ddr density information */ + foreach_ech(ch) { + for (cs = 0; cs < CS_CNT; cs++) { + if (ddr_density[ch][cs] == 0xff) { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00); + } else { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), + DBMEMCONF_REGD(ddr_density[ch] + [cs])); + } + } + mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000); + mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000); + } + + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); + + /*set DBI */ + if (board_cnf->dbi_en) + mmio_write_32(DBSC_DBDBICNT, 0x00000003); + + /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */ + if ((((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) && + board_cnf->dbi_en) + reg_ddrphy_write_a(0x00001010, 0x01000000); + + /*set REFCYCLE */ + data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; + mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff)); + mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); + +#ifdef DDR_BACKUPMODE + if (ddr_backup == DRAM_BOOT_STATUS_WARM) { +#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */ + DEBUG(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1); + send_dbcmd(0x08040001); + wait_dbcmd(); + send_dbcmd(0x0A040001); + wait_dbcmd(); + send_dbcmd(0x04040010); + wait_dbcmd(); + + if (prr_product == PRR_PRODUCT_H3) { + send_dbcmd(0x08140001); + wait_dbcmd(); + send_dbcmd(0x0A140001); + wait_dbcmd(); + send_dbcmd(0x04140010); + wait_dbcmd(); + } +#else /* DDR_BACKUPMODE_HALF //for All channels */ + send_dbcmd(0x08840001); + wait_dbcmd(); + send_dbcmd(0x0A840001); + wait_dbcmd(); + + send_dbcmd(0x04840010); + wait_dbcmd(); +#endif /* DDR_BACKUPMODE_HALF */ + } +#endif /* DDR_BACKUPMODE */ + +#if RCAR_REWT_TRAINING != 0 + /* Periodic-WriteDQ Training seeting */ + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut == PRR_PRODUCT_10))) { + /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ + } else { + /* + * H3 Ver.2.0 or later/M3-W Ver.1.1 or + * later/M3-N/V3H -> Periodic-WriteDQ Training seeting + */ + + /* Periodic WriteDQ Training seeting */ + mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000); + + ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04); + ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0F); + ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50); + ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300); + + ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP, + ddrtbl_getval(_cnf_DDR_PI_REGSET, + _reg_PI_WDQLVL_CS_MAP)); + ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); + ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100); + ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01); + ddr_setval_ach(_reg_PI_TREF_F0, 0x0000); + ddr_setval_ach(_reg_PI_TREF_F1, 0x0000); + ddr_setval_ach(_reg_PI_TREF_F2, 0x0000); + + if (prr_product == PRR_PRODUCT_M3) { + ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02); + } else { + ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02); + } + ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01); + + /* DFI_PHYMSTR_ACK , WTmode setting */ + /* DFI_PHYMSTR_ACK: WTmode =b'01 */ + mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); + } +#endif /* RCAR_REWT_TRAINING */ + /* periodic dram zqcal and phy ctrl update enable */ + mmio_write_32(DBSC_DBCALCNF, 0x01000010); + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut < PRR_PRODUCT_30))) { + /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ + } else { +#if RCAR_DRAM_SPLIT == 2 + if ((prr_product == PRR_PRODUCT_H3) && + (board_cnf->phyvalid == 0x05)) + mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); + else + mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); +#else /* RCAR_DRAM_SPLIT == 2 */ + mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); +#endif /* RCAR_DRAM_SPLIT == 2 */ + } + + mmio_write_32(DBSC_DBRFEN, 0x00000001); + /* dram access enable */ + mmio_write_32(DBSC_DBACEN, 0x00000001); + + MSG_LF(__func__ "(done)"); +} + +/* DFI_INIT_START */ +static uint32_t dfi_init_start(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t data_l; + const uint32_t RETRY_MAX = 0x10000; + + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + /* PLL3 Disable */ + /* protect register interface */ + ddrphy_regif_idle(); + + pll3_control(0); + + /* init start */ + /* dbdficnt0: + * dfi_dram_clk_disable=1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start =0 + */ + foreach_vch(ch) + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); + dsb_sev(); + + /* dbdficnt0: + * dfi_dram_clk_disable=1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start =1 + */ + foreach_vch(ch) + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); + dsb_sev(); + + } else { + ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02); + dsb_sev(); + ddrphy_regif_idle(); + } + + /* dll_rst negate */ + foreach_vch(ch) + mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01); + dsb_sev(); + + /* wait init_complete */ + phytrainingok = 0; + retry = 0; + while (retry++ < RETRY_MAX) { + foreach_vch(ch) { + data_l = mmio_read_32(DBSC_DBDFISTAT(ch)); + if (data_l & 0x00000001) + phytrainingok |= (1U << ch); + } + dsb_sev(); + if (phytrainingok == ddr_phyvalid) + break; + if (retry % 256 == 0) + ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); + } + + /* all ch ok? */ + if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) + return 0xff; + + /* dbdficnt0: + * dfi_dram_clk_disable=0 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start =0 + */ + foreach_vch(ch) + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010); + dsb_sev(); + + return 0; +} + +/* drivablity setting : CMOS MODE ON/OFF */ +static void change_lpddr4_en(uint32_t mode) +{ + uint32_t ch; + uint32_t i; + uint32_t data_l; + const uint32_t _reg_PHY_PAD_DRIVE_X[3] = { + _reg_PHY_PAD_ADDR_DRIVE, + _reg_PHY_PAD_CLK_DRIVE, + _reg_PHY_PAD_CS_DRIVE + }; + + foreach_vch(ch) { + for (i = 0; i < 3; i++) { + data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); + if (mode) { + data_l |= (1U << 14); + } else { + data_l &= ~(1U << 14); + } + ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l); + } + } +} + +/* drivablity setting */ +static uint32_t set_term_code(void) +{ + int32_t i; + uint32_t ch, index; + uint32_t data_l; + uint32_t chip_id[2]; + uint32_t term_code; + uint32_t override; + uint32_t pvtr; + uint32_t pvtp; + uint32_t pvtn; + + term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_PAD_DATA_TERM); + override = 0; + for (i = 0; i < 2; i++) + chip_id[i] = mmio_read_32(LIFEC_CHIPID(i)); + + index = 0; + while (1) { + if (termcode_by_sample[index][0] == 0xffffffff) { + break; + } + if ((termcode_by_sample[index][0] == chip_id[0]) && + (termcode_by_sample[index][1] == chip_id[1])) { + term_code = termcode_by_sample[index][2]; + override = 1; + break; + } + index++; + } + + if (override) { + for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { + data_l = + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_PAD_TERM_X[index]); + data_l = (data_l & 0xfffe0000) | term_code; + ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l); + } + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut == PRR_PRODUCT_10)) { + /* non */ + } else { + ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], + (ddrtbl_getval + (_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000)); + ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01); + ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01); + foreach_vch(ch) { + do { + data_l = + ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); + } while (!(data_l & 0x00800000)); + } + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { + foreach_vch(ch) { + data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); + pvtr = (data_l >> 12) & 0x1f; + pvtr += 8; + if (pvtr > 0x1f) + pvtr = 0x1f; + data_l = + ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); + pvtn = (data_l >> 6) & 0x03f; + pvtp = (data_l >> 0) & 0x03f; + + for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; + index++) { + data_l = + ddrtbl_getval + (_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_PAD_TERM_X[index]); + data_l = (data_l & 0xfffe0000) + | (pvtr << 12) + | (pvtn << 6) + | (pvtp); + ddr_setval(ch, + _reg_PHY_PAD_TERM_X[index], + data_l); + } + } + } else { + /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ + foreach_vch(ch) { + for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; + index++) { + data_l = + ddr_getval(ch, + _reg_PHY_PAD_TERM_X + [index]); + ddr_setval(ch, + _reg_PHY_PAD_TERM_X[index], + (data_l & 0xFFFE0FFF) | + 0x00015000); + } + } + } + } + + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + /* non */ + } else { + ddr_padcal_tcompensate_getinit(override); + } + + return 0; +} + +/* DDR mode register setting */ +static void ddr_register_set(void) +{ + int32_t fspwp; + uint32_t tmp; + + for (fspwp = 1; fspwp >= 0; fspwp--) { + /*MR13, fspwp */ + send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6)); + + tmp = + ddrtbl_getval(_cnf_DDR_PI_REGSET, + reg_pi_mr1_data_fx_csx[fspwp][0]); + send_dbcmd(0x0e840100 | tmp); + + tmp = + ddrtbl_getval(_cnf_DDR_PI_REGSET, + reg_pi_mr2_data_fx_csx[fspwp][0]); + send_dbcmd(0x0e840200 | tmp); + + tmp = + ddrtbl_getval(_cnf_DDR_PI_REGSET, + reg_pi_mr3_data_fx_csx[fspwp][0]); + send_dbcmd(0x0e840300 | tmp); + + tmp = + ddrtbl_getval(_cnf_DDR_PI_REGSET, + reg_pi_mr11_data_fx_csx[fspwp][0]); + send_dbcmd(0x0e840b00 | tmp); + + tmp = + ddrtbl_getval(_cnf_DDR_PI_REGSET, + reg_pi_mr12_data_fx_csx[fspwp][0]); + send_dbcmd(0x0e840c00 | tmp); + + tmp = + ddrtbl_getval(_cnf_DDR_PI_REGSET, + reg_pi_mr14_data_fx_csx[fspwp][0]); + send_dbcmd(0x0e840e00 | tmp); + /* MR22 */ + send_dbcmd(0x0e841616); + + /* ZQCAL start */ + send_dbcmd(0x0d84004F); + + /* ZQLAT */ + send_dbcmd(0x0d840051); + } + + /* MR13, fspwp */ + send_dbcmd(0x0e840d08); +} + +/* Training handshake functions */ +static inline uint32_t wait_freqchgreq(uint32_t assert) +{ + uint32_t data_l; + uint32_t count; + uint32_t ch; + + count = 100000; + + /* H3 Ver.1.x cannot see frqchg_req */ + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + return 0; + } + + if (assert) { + do { + data_l = 1; + foreach_vch(ch) { + data_l &= mmio_read_32(DBSC_DBPDSTAT(ch)); + } + count = count - 1; + } while (((data_l & 0x01) != 0x01) & (count != 0)); + } else { + do { + data_l = 0; + foreach_vch(ch) { + data_l |= mmio_read_32(DBSC_DBPDSTAT(ch)); + } + count = count - 1; + } while (((data_l & 0x01) != 0x00) & (count != 0)); + } + + return (count == 0); +} + +static inline void set_freqchgack(uint32_t assert) +{ + uint32_t ch; + uint32_t data_l; + + if (assert) + data_l = 0x0CF20000; + else + data_l = 0x00000000; + + foreach_vch(ch) + mmio_write_32(DBSC_DBPDCNT2(ch), data_l); +} + +static inline void set_dfifrequency(uint32_t freq) +{ + uint32_t ch; + + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + foreach_vch(ch) + mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq); + } else { + foreach_vch(ch) { + mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, + (freq << 24)); + } + } + dsb_sev(); +} + +static uint32_t pll3_freq(uint32_t on) +{ + uint32_t timeout; + + timeout = wait_freqchgreq(1); + + if (timeout) { + return 1; + } + + pll3_control(on); + set_dfifrequency(on); + + set_freqchgack(1); + timeout = wait_freqchgreq(0); + set_freqchgack(0); + + if (timeout) { + FATAL_MSG("BL2: Time out[2]\n"); + return 1; + } + return 0; +} + +/* update dly */ +static void update_dly(void) +{ + ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01); + ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01); +} + +/* training by pi */ +static uint32_t pi_training_go(void) +{ + uint32_t flag; + uint32_t data_l; + uint32_t retry; + const uint32_t RETRY_MAX = 4096 * 16; + uint32_t ch; + + uint32_t mst_ch; + uint32_t cur_frq; + uint32_t complete; + uint32_t frqchg_req; + + /* pi_start */ + ddr_setval_ach(_reg_PI_START, 0x01); + foreach_vch(ch) + ddr_getval(ch, _reg_PI_INT_STATUS); + + /* set dfi_phymstr_ack = 1 */ + mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001); + dsb_sev(); + + /* wait pi_int_status[0] */ + mst_ch = 0; + flag = 0; + complete = 0; + cur_frq = 0; + retry = RETRY_MAX; + do { + frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; + + /* H3 Ver.1.x cannot see frqchg_req */ + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { + if ((retry % 4096) == 1) { + frqchg_req = 1; + } else { + frqchg_req = 0; + } + } + + if (frqchg_req) { + if (cur_frq) { + /* Low frequency */ + flag = pll3_freq(0); + cur_frq = 0; + } else { + /* High frequency */ + flag = pll3_freq(1); + cur_frq = 1; + } + if (flag) + break; + } else { + if (cur_frq) { + foreach_vch(ch) { + if (complete & (1U << ch)) + continue; + data_l = + ddr_getval(ch, _reg_PI_INT_STATUS); + if (data_l & 0x01) { + complete |= (1U << ch); + } + } + if (complete == ddr_phyvalid) + break; + } + } + } while (--retry); + foreach_vch(ch) { + /* dummy read */ + data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); + data_l = ddr_getval(ch, _reg_PI_INT_STATUS); + ddr_setval(ch, _reg_PI_INT_ACK, data_l); + } + if (ddrphy_regif_chk()) { + return 0xfd; + } + return complete; +} + +/* Initialize DDR */ +static uint32_t init_ddr(void) +{ + int32_t i; + uint32_t data_l; + uint32_t phytrainingok; + uint32_t ch, slice; + uint32_t err; + int16_t adj; + + MSG_LF(__func__ ":0\n"); + +#ifdef DDR_BACKUPMODE + rcar_dram_get_boot_status(&ddr_backup); +#endif + + /* unlock phy */ + /* Unlock DDRPHY register(AGAIN) */ + foreach_vch(ch) + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); + dsb_sev(); + + if ((((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) && board_cnf->dbi_en) + reg_ddrphy_write_a(0x00001010, 0x01000001); + else + reg_ddrphy_write_a(0x00001010, 0x00000001); + /* DBSC register pre-setting */ + dbsc_regset_pre(); + + /* load ddrphy registers */ + + ddrtbl_load(); + + /* configure ddrphy registers */ + ddr_config(); + + /* dfi_reset assert */ + foreach_vch(ch) + mmio_write_32(DBSC_DBPDCNT0(ch), 0x01); + dsb_sev(); + + /* dbsc register set */ + dbsc_regset(); + MSG_LF(__func__ ":1\n"); + + /* dfi_reset negate */ + foreach_vch(ch) + mmio_write_32(DBSC_DBPDCNT0(ch), 0x00); + dsb_sev(); + + /* dfi_init_start (start ddrphy) */ + err = dfi_init_start(); + if (err) { + return INITDRAM_ERR_I; + } + MSG_LF(__func__ ":2\n"); + + /* ddr backupmode end */ +#ifdef DDR_BACKUPMODE + if (ddr_backup) { + NOTICE("BL2: [WARM_BOOT]\n"); + } else { + NOTICE("BL2: [COLD_BOOT]\n"); + } + err = rcar_dram_update_boot_status(ddr_backup); + if (err) { + NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); + return INITDRAM_ERR_I; + } +#endif + MSG_LF(__func__ ":3\n"); + + /* override term code after dfi_init_complete */ + err = set_term_code(); + if (err) { + return INITDRAM_ERR_I; + } + MSG_LF(__func__ ":4\n"); + + /* rx offset calibration */ + if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + err = rx_offset_cal_hw(); + } else { + err = rx_offset_cal(); + } + if (err) + return INITDRAM_ERR_O; + MSG_LF(__func__ ":5\n"); + + /* PDX */ + send_dbcmd(0x08840001); + + /* check register i/f is alive */ + err = ddrphy_regif_chk(); + if (err) { + return INITDRAM_ERR_O; + } + MSG_LF(__func__ ":6\n"); + + /* phy initialize end */ + + /* setup DDR mode registers */ + /* CMOS MODE */ + change_lpddr4_en(0); + + /* MRS */ + ddr_register_set(); + + /* Thermal sensor setting */ + /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ + data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; + mmio_write_32(THS1_THCTR, data_l); + + /* LPDDR4 MODE */ + change_lpddr4_en(1); + + MSG_LF(__func__ ":7\n"); + + /* mask CS_MAP if RANKx is not found */ + foreach_vch(ch) { + data_l = ddr_getval(ch, _reg_PI_CS_MAP); + if (!(ch_have_this_cs[1] & (1U << ch))) + data_l = data_l & 0x05; + ddr_setval(ch, _reg_PI_CS_MAP, data_l); + } + + /* exec pi_training */ + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), + BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); + + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); + } else { + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + ddr_setval_s(ch, slice, + _reg_PHY_PER_CS_TRAINING_EN, + ((ch_have_this_cs[1]) >> ch) + & 0x01); + } + } + } + + phytrainingok = pi_training_go(); + + if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) { + return INITDRAM_ERR_T | phytrainingok; + } + + MSG_LF(__func__ ":8\n"); + + /* CACS DLY ADJUST */ + data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); + foreach_vch(ch) { + for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); + ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], + data_l + adj); + } + + if (ddr_phycaslice == 1) { + for (i = 0; i < 6; i++) { + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj + [i + + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); + ddr_setval_s(ch, 2, + _reg_PHY_CLK_CACS_SLAVE_DELAY_X + [i], + data_l + adj + ); + } + } + } + + update_dly(); + MSG_LF(__func__ ":9\n"); + + /* H3 fix rd latency to avoid bug in elasitic buffer */ + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + adjust_rddqs_latency(); + + /* Adjust Write path latency */ + if (ddrtbl_getval + (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) + adjust_wpath_latency(); + + /* RDQLVL Training */ + if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) + ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); + + err = rdqdm_man(); + + if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) + ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00); + + if (err) { + return INITDRAM_ERR_T; + } + update_dly(); + MSG_LF(__func__ ":10\n"); + + /* WDQLVL Training */ + err = wdqdm_man(); + if (err) { + return INITDRAM_ERR_T; + } + update_dly(); + MSG_LF(__func__ ":11\n"); + + /* training complete, setup DBSC */ + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); + ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); + } + + dbsc_regset_post(); + MSG_LF(__func__ ":12\n"); + + return phytrainingok; +} + +/* SW LEVELING COMMON */ +static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) +{ + uint32_t ch; + uint32_t data_l; + uint32_t retry; + uint32_t waiting; + uint32_t err; + + const uint32_t RETRY_MAX = 0x1000; + + err = 0; + /* set EXIT -> OP_DONE is cleared */ + ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); + + /* kick */ + foreach_vch(ch) { + if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) { + ddr_setval(ch, reg_cs, ddr_csn); + ddr_setval(ch, reg_kick, 0x01); + } + } + foreach_vch(ch) { + /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */ + ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); + } + waiting = ch_have_this_cs[ddr_csn % 2]; + dsb_sev(); + retry = RETRY_MAX; + do { + foreach_vch(ch) { + if (!(waiting & (1U << ch))) + continue; + data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); + if (data_l & 0x01) + waiting &= ~(1U << ch); + } + retry--; + } while (waiting && (retry > 0)); + if (retry == 0) { + err = 1; + } + + dsb_sev(); + /* set EXIT -> OP_DONE is cleared */ + ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); + dsb_sev(); + + return err; +} + +/* WDQ TRAINING */ +#ifndef DDR_FAST_INIT +static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) +{ + int32_t i, k; + uint32_t cs, slice; + uint32_t data_l; + + /* clr of training results buffer */ + cs = ddr_csn % 2; + data_l = board_cnf->dqdm_dly_w; + for (slice = 0; slice < SLICE_CNT; slice++) { + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) + continue; + + for (i = 0; i <= 8; i++) { + if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) + wdqdm_dly[ch][cs][slice][i] = + wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; + else + wdqdm_dly[ch][cs][slice][i] = data_l; + wdqdm_le[ch][cs][slice][i] = 0; + wdqdm_te[ch][cs][slice][i] = 0; + } + wdqdm_st[ch][cs][slice] = 0; + wdqdm_win[ch][cs][slice] = 0; + } +} + +static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) +{ + int32_t i, k; + uint32_t cs, slice; + uint32_t data_l; + uint32_t err; + const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0; + + int32_t min_win; + int32_t win; + int8_t _adj; + int16_t adj; + uint32_t dq; + + /* analysis of training results */ + err = 0; + for (slice = 0; slice < SLICE_CNT; slice += 1) { + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) + continue; + + cs = ddr_csn % 2; + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); + for (i = 0; i < 9; i++) { + dq = slice * 8 + i; + if (i == 8) + _adj = board_cnf->ch[ch].dm_adj_w[slice]; + else + _adj = board_cnf->ch[ch].dq_adj_w[dq]; + adj = _f_scale_adj(_adj); + + data_l = + ddr_getval_s(ch, slice, + _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], + data_l); + wdqdm_dly[ch][cs][slice][i] = data_l; + } + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); + data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); + wdqdm_st[ch][cs][slice] = data_l; + min_win = INT_LEAST32_MAX; + for (i = 0; i <= 8; i++) { + ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT, + i); + + data_l = + ddr_getval_s(ch, slice, + _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS); + wdqdm_te[ch][cs][slice][i] = data_l; + data_l = + ddr_getval_s(ch, slice, + _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); + wdqdm_le[ch][cs][slice][i] = data_l; + win = + (int32_t)wdqdm_te[ch][cs][slice][i] - + wdqdm_le[ch][cs][slice][i]; + if (min_win > win) + min_win = win; + if (data_l >= _par_WDQLVL_RETRY_THRES) + err = 2; + } + wdqdm_win[ch][cs][slice] = min_win; + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, + 0x01); + } else { + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, + ((ch_have_this_cs[1]) >> ch) & 0x01); + } + } + return err; +} +#endif/* DDR_FAST_INIT */ + +static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore) +{ + uint32_t i; + uint32_t ch, slice; + uint32_t tgt_cs, src_cs; + uint32_t tmp_r; + + /* copy of training results */ + foreach_vch(ch) { + for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) { + for (slice = 0; slice < SLICE_CNT; slice++) { + ddr_setval_s(ch, slice, + _reg_PHY_PER_CS_TRAINING_INDEX, + tgt_cs); + src_cs = ddr_csn % 2; + if (!(ch_have_this_cs[1] & (1U << ch))) + src_cs = 0; + for (i = 0; i <= 4; i += 4) { + if (restore) + tmp_r = + rdqdm_dly[ch][tgt_cs][slice] + [i]; + else + tmp_r = + rdqdm_dly[ch][src_cs][slice] + [i]; + + ddr_setval_s(ch, slice, + _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY + [i], tmp_r); + } + } + } + } +} + +static uint32_t wdqdm_man1(void) +{ + int32_t k; + uint32_t ch, cs, slice; + uint32_t ddr_csn; + uint32_t data_l; + uint32_t err; + uint32_t high_dq[DRAM_CH_CNT]; + uint32_t mr14_csab0_bak[DRAM_CH_CNT]; +#ifndef DDR_FAST_INIT + uint32_t err_flg; +#endif/* DDR_FAST_INIT */ + + /* manual execution of training */ + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + foreach_vch(ch) { + high_dq[ch] = 0; + for (slice = 0; slice < SLICE_CNT; slice++) { + k = (board_cnf->ch[ch].dqs_swap >> + (4 * slice)) & 0x0f; + if (k >= 2) + high_dq[ch] |= (1U << slice); + } + ddr_setval(ch, _reg_PI_16BIT_DRAM_CONNECT, 0x00); + } + } + err = 0; + /* CLEAR PREV RESULT */ + for (cs = 0; cs < CS_CNT; cs++) { + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, + 0x01); + } else { + ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, + 0x01); + } + } + ddrphy_regif_idle(); + +#ifndef DDR_FAST_INIT + err_flg = 0; +#endif/* DDR_FAST_INIT */ + for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { + foreach_vch(ch) { + data_l = mmio_read_32(DBSC_DBDFICNT(ch)); + data_l &= ~(0x00ffU << 16); + + if (ddr_csn >= 2) + k = (high_dq[ch] ^ 0x0f); + else + k = high_dq[ch]; + data_l |= (k << 16); + mmio_write_32(DBSC_DBDFICNT(ch), data_l); + ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k); + } + } + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut == PRR_PRODUCT_10))) { + wdqdm_cp(ddr_csn, 0); + } + + foreach_vch(ch) { + data_l = + ddr_getval(ch, + reg_pi_mr14_data_fx_csx[1][ddr_csn]); + ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l); + } + + /* KICK WDQLVL */ + err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ); + if (err) + goto err_exit; + + if (ddr_csn == 0) + foreach_vch(ch) { + mr14_csab0_bak[ch] = + ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]); + } else + foreach_vch(ch) { + ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], + mr14_csab0_bak[ch]); + } +#ifndef DDR_FAST_INIT + foreach_vch(ch) { + if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { + wdqdm_clr1(ch, ddr_csn); + continue; + } + err = wdqdm_ana1(ch, ddr_csn); + if (err) + err_flg |= (1U << (ddr_csn * 4 + ch)); + ddrphy_regif_idle(); + } +#endif/* DDR_FAST_INIT */ + } +err_exit: +#ifndef DDR_FAST_INIT + err |= err_flg; +#endif/* DDR_FAST_INIT */ + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01); + foreach_vch(ch) { + data_l = mmio_read_32(DBSC_DBDFICNT(ch)); + data_l &= ~(0x00ffU << 16); + mmio_write_32(DBSC_DBDFICNT(ch), data_l); + ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00); + } + } + return err; +} + +static uint32_t wdqdm_man(void) +{ + uint32_t err, retry_cnt; + const uint32_t retry_max = 0x10; + uint32_t ch, ddr_csn, mr14_bkup[4][4]; + + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, + (mmio_read_32(DBSC_DBTR(11)) & 0xFF) + 19); + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0, + (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, + (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); + } else { + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR, + (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); + } + ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); + ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); + + retry_cnt = 0; + err = 0; + do { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { + err = wdqdm_man1(); + } else { + ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, + 0x01); + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, + 0x0C); + } else { + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C); + } + dsb_sev(); + err = wdqdm_man1(); + foreach_vch(ch) { + for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { + mr14_bkup[ch][ddr_csn] = + ddr_getval(ch, + reg_pi_mr14_data_fx_csx + [1][ddr_csn]); + dsb_sev(); + } + } + + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, + 0x04); + } else { + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04); + } + pvtcode_update(); + err = wdqdm_man1(); + foreach_vch(ch) { + for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { + mr14_bkup[ch][ddr_csn] = + (mr14_bkup[ch][ddr_csn] + + ddr_getval(ch, + reg_pi_mr14_data_fx_csx + [1][ddr_csn])) / 2; + ddr_setval(ch, + reg_pi_mr14_data_fx_csx[1] + [ddr_csn], + mr14_bkup[ch][ddr_csn]); + } + } + + ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, + 0x00); + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, + 0x00); + ddr_setval_ach + (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1, + 0x00); + ddr_setval_ach + (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, + 0x00); + } else { + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x00); + ddr_setval_ach + (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, + 0x00); + ddr_setval_ach + (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, + 0x00); + } + ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, + 0x00); + + pvtcode_update2(); + err = wdqdm_man1(); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); + } + } while (err && (++retry_cnt < retry_max)); + + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) { + wdqdm_cp(0, 1); + } + + return (retry_cnt >= retry_max); +} + +/* RDQ TRAINING */ +#ifndef DDR_FAST_INIT +static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) +{ + int32_t i, k; + uint32_t cs, slice; + uint32_t data_l; + + /* clr of training results buffer */ + cs = ddr_csn % 2; + data_l = board_cnf->dqdm_dly_r; + for (slice = 0; slice < SLICE_CNT; slice++) { + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) + continue; + + for (i = 0; i <= 8; i++) { + if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) { + rdqdm_dly[ch][cs][slice][i] = + rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = + rdqdm_dly[ch][CS_CNT - 1 - cs][slice + + SLICE_CNT] + [i]; + } else { + rdqdm_dly[ch][cs][slice][i] = data_l; + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = + data_l; + } + rdqdm_le[ch][cs][slice][i] = 0; + rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; + rdqdm_te[ch][cs][slice][i] = 0; + rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0; + rdqdm_nw[ch][cs][slice][i] = 0; + rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0; + } + rdqdm_st[ch][cs][slice] = 0; + rdqdm_win[ch][cs][slice] = 0; + } +} + +static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) +{ + int32_t i, k; + uint32_t cs, slice; + uint32_t data_l; + uint32_t err; + int8_t _adj; + int16_t adj; + uint32_t dq; + int32_t min_win; + int32_t win; + uint32_t rdq_status_obs_select; + + /* analysis of training results */ + err = 0; + for (slice = 0; slice < SLICE_CNT; slice++) { + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) + continue; + + cs = ddr_csn % 2; + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); + ddrphy_regif_idle(); + + ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX); + ddrphy_regif_idle(); + + for (i = 0; i <= 8; i++) { + dq = slice * 8 + i; + if (i == 8) + _adj = board_cnf->ch[ch].dm_adj_r[slice]; + else + _adj = board_cnf->ch[ch].dq_adj_r[dq]; + + adj = _f_scale_adj(_adj); + + data_l = + ddr_getval_s(ch, slice, + _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + + adj; + ddr_setval_s(ch, slice, + _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], + data_l); + rdqdm_dly[ch][cs][slice][i] = data_l; + + data_l = + ddr_getval_s(ch, slice, + _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + + adj; + ddr_setval_s(ch, slice, + _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], + data_l); + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l; + } + min_win = INT_LEAST32_MAX; + for (i = 0; i <= 8; i++) { + data_l = + ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS); + rdqdm_st[ch][cs][slice] = data_l; + rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l; + /* k : rise/fall */ + for (k = 0; k < 2; k++) { + if (i == 8) { + rdq_status_obs_select = 16 + 8 * k; + } else { + rdq_status_obs_select = i + k * 8; + } + ddr_setval_s(ch, slice, + _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT, + rdq_status_obs_select); + + data_l = + ddr_getval_s(ch, slice, + _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = + data_l; + + data_l = + ddr_getval_s(ch, slice, + _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = + data_l; + + data_l = + ddr_getval_s(ch, slice, + _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS); + rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = + data_l; + + win = + (int32_t)rdqdm_te[ch][cs][slice + + SLICE_CNT * + k][i] - + rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; + if (i != 8) { + if (min_win > win) + min_win = win; + } + } + } + rdqdm_win[ch][cs][slice] = min_win; + if (min_win <= 0) { + err = 2; + } + } + return err; +} +#endif/* DDR_FAST_INIT */ + +static uint32_t rdqdm_man1(void) +{ + uint32_t ch; + uint32_t ddr_csn; +#ifdef DDR_FAST_INIT + uint32_t slice; + uint32_t i, adj, data_l; +#endif/* DDR_FAST_INIT */ + uint32_t err; + + /* manual execution of training */ + err = 0; + + for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { + /* KICK RDQLVL */ + err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ); + if (err) + goto err_exit; +#ifndef DDR_FAST_INIT + foreach_vch(ch) { + if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { + rdqdm_clr1(ch, ddr_csn); + ddrphy_regif_idle(); + continue; + } + err = rdqdm_ana1(ch, ddr_csn); + ddrphy_regif_idle(); + if (err) + goto err_exit; + } +#else/* DDR_FAST_INIT */ + foreach_vch(ch) { + if (ch_have_this_cs[ddr_csn] & (1U << ch)) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if (ddr_getval_s(ch, slice, + _reg_PHY_RDLVL_STATUS_OBS) != + 0x0D00FFFF) { + err = (1U << ch) | + (0x10U << slice); + goto err_exit; + } + } + } + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut <= PRR_PRODUCT_10))) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (i = 0; i <= 8; i++) { + if (i == 8) + adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]); + else + adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]); + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn); + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l); + rdqdm_dly[ch][ddr_csn][slice][i] = data_l; + rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l; + + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l); + rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l; + rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l; + } + } + } + } + ddrphy_regif_idle(); + +#endif/* DDR_FAST_INIT */ + } + +err_exit: + return err; +} + +static uint32_t rdqdm_man(void) +{ + uint32_t err, retry_cnt; + const uint32_t retry_max = 0x01; + + ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, + 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_PHY_DQ_TSEL_ENABLE)); + ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, + 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_PHY_DQS_TSEL_ENABLE)); + ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, + 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_PHY_DQ_TSEL_SELECT)); + ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, + 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_PHY_DQS_TSEL_SELECT)); + + retry_cnt = 0; + do { + err = rdqdm_man1(); + ddrphy_regif_idle(); + } while (err && (++retry_cnt < retry_max)); + ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, + ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_PHY_DQ_TSEL_ENABLE)); + ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, + ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_PHY_DQS_TSEL_ENABLE)); + ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, + ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_PHY_DQ_TSEL_SELECT)); + ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, + ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, + _reg_PHY_DQS_TSEL_SELECT)); + + return (retry_cnt >= retry_max); +} + +/* rx offset calibration */ +static int32_t _find_change(uint64_t val, uint32_t dir) +{ + int32_t i; + uint32_t startval; + uint32_t curval; + const int32_t VAL_END = 0x3f; + + if (dir == 0) { + startval = (val & 0x01); + for (i = 1; i <= VAL_END; i++) { + curval = (val >> i) & 0x01; + if (curval != startval) + return i; + } + return VAL_END; + } + + startval = (val >> dir) & 0x01; + for (i = dir - 1; i >= 0; i--) { + curval = (val >> i) & 0x01; + if (curval != startval) + return i; + } + return 0; +} + +static uint32_t _rx_offset_cal_updn(uint32_t code) +{ + const uint32_t CODE_MAX = 0x40; + uint32_t tmp; + + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + if (code == 0) + tmp = (1U << 6) | (CODE_MAX - 1); + else if (code <= 0x20) + tmp = + ((CODE_MAX - 1 - + (0x20 - code) * 2) << 6) | (CODE_MAX - 1); + else + tmp = + ((CODE_MAX - 1) << 6) | (CODE_MAX - 1 - + (code - 0x20) * 2); + } else { + if (code == 0) + tmp = (1U << 6) | (CODE_MAX - 1); + else + tmp = (code << 6) | (CODE_MAX - code); + } + return tmp; +} + +static uint32_t rx_offset_cal(void) +{ + uint32_t index; + uint32_t code; + const uint32_t CODE_MAX = 0x40; + const uint32_t CODE_STEP = 2; + uint32_t ch, slice; + uint32_t tmp; + uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; + uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM]; + uint64_t tmpval; + int32_t lsb, msb; + + ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01); + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) + val[ch][slice][index] = 0; + } + } + + for (code = 0; code < CODE_MAX / CODE_STEP; code++) { + tmp = _rx_offset_cal_updn(code * CODE_STEP); + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { + ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp); + } + dsb_sev(); + ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as); + + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + tmp = tmp_ach_as[ch][slice]; + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; + index++) { + if (tmp & (1U << index)) { + val[ch][slice][index] |= + (1ULL << code); + } else { + val[ch][slice][index] &= + ~(1ULL << code); + } + } + } + } + } + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; + index++) { + tmpval = val[ch][slice][index]; + lsb = _find_change(tmpval, 0); + msb = + _find_change(tmpval, + (CODE_MAX / CODE_STEP) - 1); + tmp = (lsb + msb) >> 1; + + tmp = _rx_offset_cal_updn(tmp * CODE_STEP); + ddr_setval_s(ch, slice, + _reg_PHY_RX_CAL_X[index], tmp); + } + } + } + ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); + + return 0; +} + +static uint32_t rx_offset_cal_hw(void) +{ + uint32_t ch, slice; + uint32_t retry; + uint32_t complete; + uint32_t tmp; + uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; + + ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00); + ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); + ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f); + + retry = 0; + while (retry < 4096) { + if ((retry & 0xff) == 0) { + ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); + } + foreach_vch(ch) + for (slice = 0; slice < SLICE_CNT; slice++) + tmp_ach_as[ch][slice] = + ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]); + + complete = 1; + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + tmp = tmp_ach_as[ch][slice]; + tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + if (tmp != 0x3E) + complete = 0; + } else { + if (tmp != 0x40) + complete = 0; + } + } + } + if (complete) + break; + + retry++; + } + + return (complete == 0); +} + +/* adjust rddqs latency */ +static void adjust_rddqs_latency(void) +{ + uint32_t ch, slice; + uint32_t dly; + uint32_t maxlatx2; + uint32_t tmp; + uint32_t rdlat_adjx2[SLICE_CNT]; + + foreach_vch(ch) { + maxlatx2 = 0; + for (slice = 0; slice < SLICE_CNT; slice++) { + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, + 0x00); + + dly = + ddr_getval_s(ch, slice, + _reg_PHY_RDDQS_GATE_SLAVE_DELAY); + tmp = + ddr_getval_s(ch, slice, + _reg_PHY_RDDQS_LATENCY_ADJUST); + /* note gate_slave_delay[9] is always 0 */ + tmp = (tmp << 1) + (dly >> 8); + rdlat_adjx2[slice] = tmp; + if (maxlatx2 < tmp) + maxlatx2 = tmp; + } + maxlatx2 = ((maxlatx2 + 1) >> 1) << 1; + for (slice = 0; slice < SLICE_CNT; slice++) { + tmp = maxlatx2 - rdlat_adjx2[slice]; + tmp = (tmp >> 1); + if (tmp) { + ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE, + ddr_getval_s(ch, slice, + _reg_PHY_RPTR_UPDATE) + + 1); + } + } + } +} + +/* adjust wpath latency */ +static void adjust_wpath_latency(void) +{ + uint32_t ch, cs, slice; + uint32_t dly; + uint32_t wpath_add; + const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180; + + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice += 1) { + for (cs = 0; cs < CS_CNT; cs++) { + ddr_setval_s(ch, slice, + _reg_PHY_PER_CS_TRAINING_INDEX, + cs); + ddr_getval_s(ch, slice, + _reg_PHY_PER_CS_TRAINING_INDEX); + dly = + ddr_getval_s(ch, slice, + _reg_PHY_CLK_WRDQS_SLAVE_DELAY); + if (dly <= _par_EARLY_THRESHOLD_VAL) + continue; + + wpath_add = + ddr_getval_s(ch, slice, + _reg_PHY_WRITE_PATH_LAT_ADD); + ddr_setval_s(ch, slice, + _reg_PHY_WRITE_PATH_LAT_ADD, + wpath_add - 1); + } + } + } +} + +/* DDR Initialize entry */ +int32_t rcar_dram_init(void) +{ + uint32_t ch, cs; + uint32_t data_l; + uint32_t bus_mbps, bus_mbpsdiv; + uint32_t tmp_tccd; + uint32_t failcount; + uint32_t cnf_boardtype; + + /* Thermal sensor setting */ + data_l = mmio_read_32(CPG_MSTPSR5); + if (data_l & BIT(22)) { /* case THS/TSC Standby */ + data_l &= ~BIT(22); + cpg_write_32(CPG_SMSTPCR5, data_l); + while (mmio_read_32(CPG_MSTPSR5) & BIT(22)) + ; /* wait bit=0 */ + } + + /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ + data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; + mmio_write_32(THS1_THCTR, data_l); + + /* Judge product and cut */ +#ifdef RCAR_DDR_FIXED_LSI_TYPE +#if (RCAR_LSI == RCAR_AUTO) + prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; +#else /* RCAR_LSI */ +#ifndef RCAR_LSI_CUT + prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; +#endif /* RCAR_LSI_CUT */ +#endif /* RCAR_LSI */ +#else /* RCAR_DDR_FIXED_LSI_TYPE */ + prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; +#endif /* RCAR_DDR_FIXED_LSI_TYPE */ + + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[0][0]; + } else { + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[2][0]; + } + } else if (prr_product == PRR_PRODUCT_M3) { + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[1][0]; + } else if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[3][0]; + } else { + FATAL_MSG("BL2: DDR:Unknown Product\n"); + return 0xff; + } + + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { + /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ + } else { + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + } + + /* Judge board type */ + cnf_boardtype = boardcnf_get_brd_type(); + if (cnf_boardtype >= BOARDNUM) { + FATAL_MSG("BL2: DDR:Unknown Board\n"); + return 0xff; + } + board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype]; + +/* RCAR_DRAM_SPLIT_2CH (2U) */ +#if RCAR_DRAM_SPLIT == 2 + /* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */ + if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) { + mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); + ddr_phyvalid = 0x03; + } else { + ddr_phyvalid = board_cnf->phyvalid; + } +#else /* RCAR_DRAM_SPLIT_2CH */ + ddr_phyvalid = board_cnf->phyvalid; +#endif /* RCAR_DRAM_SPLIT_2CH */ + + max_density = 0; + + for (cs = 0; cs < CS_CNT; cs++) { + ch_have_this_cs[cs] = 0; + } + + foreach_ech(ch) + for (cs = 0; cs < CS_CNT; cs++) + ddr_density[ch][cs] = 0xff; + + foreach_vch(ch) { + for (cs = 0; cs < CS_CNT; cs++) { + data_l = board_cnf->ch[ch].ddr_density[cs]; + ddr_density[ch][cs] = data_l; + + if (data_l == 0xff) + continue; + if (data_l > max_density) + max_density = data_l; + if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) + continue; + ch_have_this_cs[cs] |= (1U << ch); + } + } + + /* Judge board clock frequency (in MHz) */ + boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv); + if ((brd_clk / brd_clkdiv) > 25) { + brd_clkdiva = 1; + } else { + brd_clkdiva = 0; + } + + /* Judge ddr operating frequency clock(in Mbps) */ + boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv); + + ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); + + ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, + brd_clkdiv * (brd_clkdiva + 1)); + + /* Adjust tccd */ + data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; + bus_mbps = 0; + bus_mbpsdiv = 0; + switch (data_l) { + case 0: + bus_mbps = brd_clk * 0x60 * 2; + bus_mbpsdiv = brd_clkdiv * 1; + break; + case 1: + bus_mbps = brd_clk * 0x50 * 2; + bus_mbpsdiv = brd_clkdiv * 1; + break; + case 2: + bus_mbps = brd_clk * 0x40 * 2; + bus_mbpsdiv = brd_clkdiv * 1; + break; + case 3: + bus_mbps = brd_clk * 0x60 * 2; + bus_mbpsdiv = brd_clkdiv * 2; + break; + default: + bus_mbps = brd_clk * 0x60 * 2; + bus_mbpsdiv = brd_clkdiv * 2; + break; + } + tmp_tccd = CLK_DIV(ddr_mbps * 8, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv); + if (8 * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) + tmp_tccd = tmp_tccd + 1; + + if (tmp_tccd < 8) + ddr_tccd = 8; + else + ddr_tccd = tmp_tccd; + + NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); + + MSG_LF("Start\n"); + + /* PLL Setting */ + pll3_control(1); + + /* initialize DDR */ + data_l = init_ddr(); + if (data_l == ddr_phyvalid) { + failcount = 0; + } else { + failcount = 1; + } + + foreach_vch(ch) + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { + /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ + } else { + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); + } + + if (failcount == 0) { + return INITDRAM_OK; + } else { + return INITDRAM_NG; + } +} + +void pvtcode_update(void) +{ + uint32_t ch; + uint32_t data_l; + uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init; + int32_t pvtp_tmp, pvtn_tmp; + + foreach_vch(ch) { + pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6; + pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0; + + if (8912 * pvtp_init > 44230) { + pvtp_tmp = (5000 + 8912 * pvtp_init - 44230) / 10000; + } else { + pvtp_tmp = + -((-(5000 + 8912 * pvtp_init - 44230)) / 10000); + } + pvtn_tmp = (5000 + 5776 * pvtn_init + 30280) / 10000; + + pvtn[ch] = pvtn_tmp + pvtn_init; + pvtp[ch] = pvtp_tmp + pvtp_init; + + if (pvtn[ch] > 63) { + pvtn[ch] = 63; + pvtp[ch] = + (pvtp_tmp) * (63 - 6 * pvtn_tmp - + pvtn_init) / (pvtn_tmp) + + 6 * pvtp_tmp + pvtp_init; + } + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { + data_l = pvtp[ch] | (pvtn[ch] << 6) | + (tcal.tcomp_cal[ch] & 0xfffff000); + reg_ddrphy_write(ch, + ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), + data_l | 0x00020000); + reg_ddrphy_write(ch, + ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), + data_l); + reg_ddrphy_write(ch, + ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), + data_l); + reg_ddrphy_write(ch, + ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), + data_l); + reg_ddrphy_write(ch, + ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), + data_l); + } else { + data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000; + reg_ddrphy_write(ch, + ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), + data_l | 0x00020000); + reg_ddrphy_write(ch, + ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), + data_l); + reg_ddrphy_write(ch, + ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), + data_l); + reg_ddrphy_write(ch, + ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), + data_l); + reg_ddrphy_write(ch, + ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), + data_l); + } + } +} + +void pvtcode_update2(void) +{ + uint32_t ch; + + foreach_vch(ch) { + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), + tcal.init_cal[ch] | 0x00020000); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), + tcal.init_cal[ch]); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), + tcal.init_cal[ch]); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), + tcal.init_cal[ch]); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), + tcal.init_cal[ch]); + } +} + +void ddr_padcal_tcompensate_getinit(uint32_t override) +{ + uint32_t ch; + uint32_t data_l; + uint32_t pvtp, pvtn; + + tcal.init_temp = 0; + for (ch = 0; ch < 4; ch++) { + tcal.init_cal[ch] = 0; + tcal.tcomp_cal[ch] = 0; + } + + foreach_vch(ch) { + tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); + tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); + } + + if (!override) { + data_l = mmio_read_32(THS1_TEMP); + if (data_l < 2800) { + tcal.init_temp = + (143 * (int32_t)data_l - 359000) / 1000; + } else { + tcal.init_temp = + (121 * (int32_t)data_l - 296300) / 1000; + } + + foreach_vch(ch) { + pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F; + pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F; + if ((int32_t)pvtp > + ((tcal.init_temp * 29 - 3625) / 1000)) + pvtp = + (int32_t)pvtp + + ((3625 - tcal.init_temp * 29) / 1000); + else + pvtp = 0; + + if ((int32_t)pvtn > + ((tcal.init_temp * 54 - 6750) / 1000)) + pvtn = + (int32_t)pvtn + + ((6750 - tcal.init_temp * 54) / 1000); + else + pvtn = 0; + + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { + tcal.init_cal[ch] = + (tcal.init_cal[ch] & 0xfffff000) | + (pvtn << 6) | + pvtp; + } else { + tcal.init_cal[ch] = + 0x00015000 | (pvtn << 6) | pvtp; + } + } + tcal.init_temp = 125; + } +} + +#ifndef ddr_qos_init_setting +/* For QoS init */ +uint8_t get_boardcnf_phyvalid(void) +{ + return ddr_phyvalid; +} +#endif /* ddr_qos_init_setting */ diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c new file mode 100644 index 000000000..f8caade27 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -0,0 +1,1794 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define BOARDNUM 22 +#define BOARD_JUDGE_AUTO + +#ifdef BOARD_JUDGE_AUTO +static uint32_t _board_judge(void); + +static uint32_t boardcnf_get_brd_type(void) +{ + return _board_judge(); +} +#else +static uint32_t boardcnf_get_brd_type(void) +{ + return 1; +} +#endif + +#define DDR_FAST_INIT + +struct _boardcnf_ch { + uint8_t ddr_density[CS_CNT]; + uint64_t ca_swap; + uint16_t dqs_swap; + uint32_t dq_swap[SLICE_CNT]; + uint8_t dm_swap[SLICE_CNT]; + uint16_t wdqlvl_patt[16]; + int8_t cacs_adj[16]; + int8_t dm_adj_w[SLICE_CNT]; + int8_t dq_adj_w[SLICE_CNT * 8]; + int8_t dm_adj_r[SLICE_CNT]; + int8_t dq_adj_r[SLICE_CNT * 8]; +}; + +struct _boardcnf { + uint8_t phyvalid; + uint8_t dbi_en; + uint16_t cacs_dly; + int16_t cacs_dly_adj; + uint16_t dqdm_dly_w; + uint16_t dqdm_dly_r; + struct _boardcnf_ch ch[DRAM_CH_CNT]; +}; + +#define WDQLVL_PAT {\ + 0x00AA,\ + 0x0055,\ + 0x00AA,\ + 0x0155,\ + 0x01CC,\ + 0x0133,\ + 0x00CC,\ + 0x0033,\ + 0x00F0,\ + 0x010F,\ + 0x01F0,\ + 0x010F,\ + 0x00F0,\ + 0x00F0,\ + 0x000F,\ + 0x010F} + +static const struct _boardcnf boardcnfs[BOARDNUM] = { + { +/* boardcnf[0] RENESAS SALVATOR-X board with M3-W/SIP */ + .phyvalid = 0x03, + .dbi_en = 0x01, + .cacs_dly = 0x02c0, + .cacs_dly_adj = 0, + .dqdm_dly_w = 0x0300, + .dqdm_dly_r = 0x00a0, + .ch = { + { + {0x02, 0x02}, + 0x00543210U, + 0x3201U, + {0x70612543, 0x43251670, 0x45326170, 0x10672534}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + + { + {0x02, 0x02}, + 0x00543210, + 0x2310, + {0x01327654, 0x34526107, 0x35421670, 0x70615324}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[1] RENESAS KRIEK board with M3-W/SoC */ + { + 0x03, + 0x01, + 0x2c0, + 0, + 0x300, + 0x0a0, + { + { + {0x02, 0x02}, + 0x00345201, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0x02}, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[2] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 1rank) */ + { + 0x0f, + 0x00, + 0x300, + -320, + 0x300, + 0x0a0, + { + { + {0x02, 0xff}, + 0x00543210, + 0x3210, + {0x20741365, 0x34256107, 0x57460321, 0x70614532}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00543210, + 0x3102, + {0x23547610, 0x34526107, 0x67452310, 0x32106754}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00543210, + 0x0213, + {0x30216754, 0x67453210, 0x70165243, 0x07162345}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00543210, + 0x0213, + {0x01327654, 0x70615432, 0x54760123, 0x07162345}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[3] RENESAS Starter Kit board with M3-W/SIP(8Gbit 1rank) */ + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { + {0x02, 0xFF}, + 0x00543210U, + 0x3201, + {0x70612543, 0x43251670, 0x45326170, 0x10672534}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xFF}, + 0x00543210, + 0x2310, + {0x01327654, 0x34526107, 0x35421670, 0x70615324}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[4] RENESAS SALVATOR-M(1rank) board with H3 Ver.1.x/SoC */ + { + 0x0f, + 0x00, + 0x2c0, + -320, + 0x300, + 0x0a0, + { + { + {0x02, 0xff}, + 0x00315024, + 0x3120, + {0x30671254, 0x26541037, 0x17054623, 0x12307645}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00025143, + 0x3210, + {0x70613542, 0x16245307, 0x30712645, 0x21706354}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00523104, + 0x2301, + {0x70613542, 0x16245307, 0x30712645, 0x21706354}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00153402, + 0x2031, + {0x30671254, 0x26541037, 0x17054623, 0x12307645}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[5] RENESAS KRIEK-1rank board with M3-W/SoC */ + { + 0x03, + 0x01, + 0x2c0, + 0, + 0x300, + 0x0a0, + { + { + {0x02, 0xff}, + 0x00345201, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[6] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 2rank) */ + { + 0x0f, + 0x00, + 0x300, + -320, + 0x300, + 0x0a0, + { + { + {0x02, 0x02}, + 0x00543210, + 0x3210, + {0x20741365, 0x34256107, 0x57460321, 0x70614532}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0x02}, + 0x00543210, + 0x3102, + {0x23547610, 0x34526107, 0x67452310, 0x32106754}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0x02}, + 0x00543210, + 0x0213, + {0x30216754, 0x67453210, 0x70165243, 0x07162345}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0x02}, + 0x00543210, + 0x0213, + {0x01327654, 0x70615432, 0x54760123, 0x07162345}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* + * boardcnf[7] RENESAS SALVATOR-X board with + * H3 Ver.2.0 or later/SIP(8Gbit 1rank) + */ + { + 0x0f, + 0x01, + 0x300, + 0, + 0x300, + 0x0a0, + { + { + {0x02, 0xff}, + 0x00543210, + 0x2310, + {0x70631425, 0x34527016, 0x43527610, 0x32104567}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00105432, + 0x3210, + {0x43256107, 0x07162354, 0x10234567, 0x01235467}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00543210, + 0x2301, + {0x01327654, 0x02316457, 0x10234567, 0x01325467}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00543210, + 0x2301, + {0x12034765, 0x23105467, 0x23017645, 0x32106745}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* + * boardcnf[8] RENESAS SALVATOR-X board with + * H3 Ver.2.0 or later/SIP(8Gbit 2rank) + */ + { +#if RCAR_DRAM_CHANNEL == 5 + 0x05, +#else + 0x0f, +#endif + 0x01, + 0x300, + 0, + 0x300, + 0x0a0, + { + { + {0x02, 0x02}, + 0x00543210, + 0x2310, + {0x70631425, 0x34527016, 0x43527610, 0x32104567}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, +#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2)) + { + {0x02, 0x02}, + 0x00543210, + 0x2301, + {0x01327654, 0x02316457, 0x10234567, 0x01325467}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, +#else + { + {0x02, 0x02}, + 0x00105432, + 0x3210, + {0x43256107, 0x07162354, 0x10234567, 0x01235467}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, +#endif + { + {0x02, 0x02}, + 0x00543210, + 0x2301, + {0x01327654, 0x02316457, 0x10234567, 0x01325467}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0x02}, + 0x00543210, + 0x2301, + {0x12034765, 0x23105467, 0x23017645, 0x32106745}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[9] RENESAS SALVATOR-MS(1rank) board with H3 Ver.2.0 or later/SoC */ + { + 0x0f, + 0x01, + 0x300, + 0, + 0x300, + 0x0a0, + { + { + {0x02, 0xff}, + 0x00543210, + 0x3210, + {0x27645310, 0x75346210, 0x53467210, 0x23674510}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00543210, + 0x2301, + {0x23764510, 0x43257610, 0x43752610, 0x37652401}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {-128, -128, -128, -128, -128, -128, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00452103, + 0x3210, + {0x32764510, 0x43257610, 0x43752610, 0x26573401}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0xff}, + 0x00520413, + 0x2301, + {0x47652301, 0x75346210, 0x53467210, 0x32674501}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {30, 30, 30, 30, 30, 30, 30, 30, + 30, 30}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[10] RENESAS Kriek(2rank) board with M3-N/SoC */ + { + 0x01, + 0x01, + 0x300, + 0, + 0x300, + 0x0a0, + { + { + {0x02, 0x02}, + 0x00345201, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[11] RENESAS SALVATOR-X board with M3-N/SIP(8Gbit 2rank) */ + { + 0x01, + 0x01, + 0x300, + 0, + 0x300, + 0x0a0, + { + { +#if (RCAR_DRAM_LPDDR4_MEMCONF == 2) + {0x04, 0x04}, +#else + {0x02, 0x02}, +#endif + 0x00342501, + 0x3201, + {0x10672534, 0x43257106, 0x34527601, 0x71605243}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[12] RENESAS CONDOR board with V3H/SoC */ + { + 0x01, + 0x1, + 0x300, + 0, + 0x300, + 0x0a0, + { + { + {0x02, 0x02}, + 0x00501342, + 0x3201, + {0x70562134, 0x34526071, 0x23147506, 0x12430567}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[13] RENESAS KRIEK board with PM3/SoC */ + { + 0x05, + 0x00, + 0x2c0, + -320, + 0x300, + 0x0a0, + { + { + {0x02, 0x02}, + 0x00345201, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0x02}, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0x02}, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0xff, 0xff}, + 0, + 0, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[14] SALVATOR-X board with H3 Ver.2.0 or later/SIP(16Gbit 1rank) */ + { +#if RCAR_DRAM_CHANNEL == 5 + 0x05, +#else + 0x0f, +#endif + 0x01, + 0x300, + 0, + 0x300, + 0x0a0, + { + { + {0x04, 0xff}, + 0x00543210, + 0x2310, + {0x70631425, 0x34527016, 0x43527610, 0x32104567}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, +#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2)) + { + {0x04, 0xff}, + 0x00543210, + 0x2301, + {0x01327654, 0x02316457, 0x10234567, 0x01325467}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, +#else + { + {0x04, 0xff}, + 0x00105432, + 0x3210, + {0x43256107, 0x07162354, 0x10234567, 0x01235467}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, +#endif + { + {0x04, 0xff}, + 0x00543210, + 0x2301, + {0x01327654, 0x02316457, 0x10234567, 0x01325467}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x04, 0xff}, + 0x00543210, + 0x2301, + {0x12034765, 0x23105467, 0x23017645, 0x32106745}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[15] RENESAS KRIEK board with H3N */ + { + 0x05, + 0x01, + 0x300, + 0, + 0x300, + 0x0a0, + { + { + {0x02, 0x02}, + 0x00345201, + 0x3201, + {0x01672543, 0x45367012, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0x02}, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x02, 0x02}, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0xff, 0xff}, + 0, + 0, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */ + { + 0x03, + 0x01, + 0x0320, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0x04}, + 0x520314FFFF523041, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x04, 0x04}, + 0x314250FFFF312405, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */ + { + 0x01, + 0x01, + 0x0300, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0x04}, + 0x520314FFFF523041, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) */ + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0x04}, + 0x00543210, + 0x3201, + {0x70612543, 0x43251670, 0x45326170, 0x10672534}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x04, 0x04}, + 0x00543210, + 0x2310, + {0x01327654, 0x34526107, 0x35421670, 0x70615324}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */ + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0xff}, + 0x00543210, + 0x3201, + {0x70612543, 0x43251670, 0x45326170, 0x10672534}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x04, 0xff}, + 0x00543210, + 0x2310, + {0x01327654, 0x34526107, 0x35421670, 0x70615324}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */ + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0x04}, + 0x00345201, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x04, 0x04}, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, +/* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */ + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0xff}, + 0x00345201, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x04, 0xff}, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + } +}; + +void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) +{ + uint32_t md; + + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_10)) { + *clk = 50; + *div = 3; + } else { + md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3; + switch (md) { + case 0x0: + *clk = 50; + *div = 3; + break; + case 0x1: + *clk = 60; + *div = 3; + break; + case 0x2: + *clk = 75; + *div = 3; + break; + case 0x3: + *clk = 100; + *div = 3; + break; + } + } + (void)brd; +} + +void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) +{ + uint32_t md; + + md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5; + md = (md | (md >> 1)) & 0x3; + switch (md) { + case 0x0: + *mbps = 3200; + *div = 1; + break; + case 0x1: + *mbps = 2800; + *div = 1; + break; + case 0x2: + *mbps = 2400; + *div = 1; + break; + case 0x3: + *mbps = 1600; + *div = 1; + break; + } + (void)brd; +} + +#define _def_REFPERIOD 1890 + +#define M3_SAMPLE_TT_A84 0xB866CC10, 0x3B250421 +#define M3_SAMPLE_TT_A85 0xB866CC10, 0x3AA50421 +#define M3_SAMPLE_TT_A86 0xB866CC10, 0x3AA48421 +#define M3_SAMPLE_FF_B45 0xB866CC10, 0x3AB00C21 +#define M3_SAMPLE_FF_B49 0xB866CC10, 0x39B10C21 +#define M3_SAMPLE_FF_B56 0xB866CC10, 0x3AAF8C21 +#define M3_SAMPLE_SS_E24 0xB866CC10, 0x3BA39421 +#define M3_SAMPLE_SS_E28 0xB866CC10, 0x3C231421 +#define M3_SAMPLE_SS_E32 0xB866CC10, 0x3C241421 + +static const uint32_t termcode_by_sample[20][3] = { + {M3_SAMPLE_TT_A84, 0x000158D5}, + {M3_SAMPLE_TT_A85, 0x00015955}, + {M3_SAMPLE_TT_A86, 0x00015955}, + {M3_SAMPLE_FF_B45, 0x00015690}, + {M3_SAMPLE_FF_B49, 0x00015753}, + {M3_SAMPLE_FF_B56, 0x00015793}, + {M3_SAMPLE_SS_E24, 0x00015996}, + {M3_SAMPLE_SS_E28, 0x000159D7}, + {M3_SAMPLE_SS_E32, 0x00015997}, + {0xFFFFFFFF, 0xFFFFFFFF, 0x0001554F} +}; + +#ifdef BOARD_JUDGE_AUTO +/* + * SAMPLE board detect function + */ +#define PFC_PMMR 0xE6060000U +#define PFC_PUEN5 0xE6060414U +#define PFC_PUEN6 0xE6060418U +#define PFC_PUD5 0xE6060454U +#define PFC_PUD6 0xE6060458U +#define GPIO_INDT5 0xE605500CU +#define GPIO_GPSR6 0xE6060118U + +#if (RCAR_GEN3_ULCB == 0) +static void pfc_write_and_poll(uint32_t a, uint32_t v) +{ + mmio_write_32(PFC_PMMR, ~v); + v = ~mmio_read_32(PFC_PMMR); + mmio_write_32(a, v); + while (v != mmio_read_32(a)) + ; + dsb_sev(); +} +#endif + +#ifndef RCAR_GEN3_ULCB +#define RCAR_GEN3_ULCB 0 +#endif + +#if (RCAR_GEN3_ULCB == 0) /* non Starter Kit */ + +static uint32_t opencheck_SSI_WS6(void) +{ + uint32_t dataL, down, up; + uint32_t gpsr6_bak; + uint32_t puen5_bak; + uint32_t pud5_bak; + + gpsr6_bak = mmio_read_32(GPIO_GPSR6); + puen5_bak = mmio_read_32(PFC_PUEN5); + pud5_bak = mmio_read_32(PFC_PUD5); + dsb_sev(); + + dataL = (gpsr6_bak & ~BIT(15)); + pfc_write_and_poll(GPIO_GPSR6, dataL); + + /* Pull-Up/Down Enable (PUEN5[22]=1) */ + dataL = puen5_bak; + dataL |= (BIT(22)); + pfc_write_and_poll(PFC_PUEN5, dataL); + + /* Pull-Down-Enable (PUD5[22]=0, PUEN5[22]=1) */ + dataL = pud5_bak; + dataL &= ~(BIT(22)); + pfc_write_and_poll(PFC_PUD5, dataL); + /* GPSR6[15]=SSI_WS6 */ + rcar_micro_delay(10); + down = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1; + dsb_sev(); + + /* Pull-Up-Enable (PUD5[22]=1, PUEN5[22]=1) */ + dataL = pud5_bak; + dataL |= (BIT(22)); + pfc_write_and_poll(PFC_PUD5, dataL); + + /* GPSR6[15]=SSI_WS6 */ + rcar_micro_delay(10); + up = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1; + + dsb_sev(); + + pfc_write_and_poll(GPIO_GPSR6, gpsr6_bak); + pfc_write_and_poll(PFC_PUEN5, puen5_bak); + pfc_write_and_poll(PFC_PUD5, pud5_bak); + + if (down == up) { + /* Same = Connect */ + return 0; + } + + /* Diff = Open */ + return 1; +} + +#endif + +static uint32_t _board_judge(void) +{ + uint32_t brd; +#if (RCAR_GEN3_ULCB == 1) + /* Starter Kit */ + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { + /* RENESAS Starter Kit(H3 Ver.1.x/SIP) board */ + brd = 2; + } else { + /* RENESAS Starter Kit(H3 Ver.2.0 or later/SIP) board */ +#if (RCAR_DRAM_LPDDR4_MEMCONF == 0) + brd = 7; +#else + brd = 8; +#endif + } + } else if (prr_product == PRR_PRODUCT_M3) { + /* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */ + brd = 3; + } else { + /* RENESAS Starter Kit(M3-N/SIP) board */ + brd = 11; + } +#else + uint32_t usb2_ovc_open; + + usb2_ovc_open = opencheck_SSI_WS6(); + + /* RENESAS Eva-board */ + brd = 99; + if (prr_product == PRR_PRODUCT_V3H) { + /* RENESAS Condor board */ + brd = 12; + } else if (usb2_ovc_open) { + if (prr_product == PRR_PRODUCT_M3N) { + /* RENESAS Kriek board with M3-N */ + brd = 10; + } else if (prr_product == PRR_PRODUCT_M3) { + /* RENESAS Kriek board with M3-W */ + brd = 1; + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { + /* RENESAS Kriek board with PM3 */ + brd = 13; + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_20)) { + /* RENESAS Kriek board with H3N */ + brd = 15; + } + } else { + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { + /* RENESAS SALVATOR-X (H3 Ver.1.x/SIP) */ + brd = 2; + } else if (prr_cut < PRR_PRODUCT_30) { + /* RENESAS SALVATOR-X (H3 Ver.2.0/SIP) */ + brd = 7; // 8Gbit/1rank + } else { + /* RENESAS SALVATOR-X (H3 Ver.3.0/SIP) */ +#if (RCAR_DRAM_LPDDR4_MEMCONF == 0) + brd = 7; +#else + brd = 8; +#endif + } + } else if (prr_product == PRR_PRODUCT_M3N) { + /* RENESAS SALVATOR-X (M3-N/SIP) */ + brd = 11; + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut <= PRR_PRODUCT_20)) { + /* RENESAS SALVATOR-X (M3-W/SIP) */ + brd = 0; + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut < PRR_PRODUCT_30)) { + /* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */ + brd = 19; + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut >= PRR_PRODUCT_30)) { + /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */ + brd = 18; + } + } +#endif + + return brd; +} +#endif diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h new file mode 100644 index 000000000..5047e5cc2 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define RCAR_DDR_VERSION "rev.0.37" +#define DRAM_CH_CNT 0x04 +#define SLICE_CNT 0x04 +#define CS_CNT 0x02 + +/* order : CS0A, CS0B, CS1A, CS1B */ +#define CSAB_CNT (CS_CNT * 2) + +/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */ +#define CHAB_CNT (DRAM_CH_CNT * 2) + +/* pll setting */ +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) +#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) + +/* for ddr deisity setting */ +#define DBMEMCONF_REG(d3, row, bank, col, dw) \ + ((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw)) + +#define DBMEMCONF_REGD(density) \ + (DBMEMCONF_REG((density) % 2, ((density) + 1) / \ + 2 + (29 - 3 - 10 - 2), 3, 10, 2)) + +#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) + +/* refresh mode */ +#define DBSC_REFINTS (0x0) + +/* system registers */ +#define CPG_FRQCRB (CPG_BASE + 0x0004U) + +#define CPG_PLLECR (CPG_BASE + 0x00D0U) +#define CPG_MSTPSR5 (CPG_BASE + 0x003CU) +#define CPG_SRCR4 (CPG_BASE + 0x00BCU) +#define CPG_PLL3CR (CPG_BASE + 0x00DCU) +#define CPG_ZB3CKCR (CPG_BASE + 0x0380U) +#define CPG_FRQCRD (CPG_BASE + 0x00E4U) +#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) +#define CPG_CPGWPR (CPG_BASE + 0x0900U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U) + +#define CPG_FRQCRB_KICK_BIT BIT(31) +#define CPG_PLLECR_PLL3E_BIT BIT(3) +#define CPG_PLLECR_PLL3ST_BIT BIT(11) +#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11) + +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) + +#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x)) + +/* DBSC registers */ +#include "../ddr_regs.h" + +#define DBSC_DBMONCONF4 0xE6793010U + +#define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch)) +#define DBSC_PLL_LOCK_0 0xE6794054U +#define DBSC_PLL_LOCK_1 0xE6794154U +#define DBSC_PLL_LOCK_2 0xE6794254U +#define DBSC_PLL_LOCK_3 0xE6794354U + +/* STAT registers */ +#define MSTAT_SL_INIT 0xE67E8000U +#define MSTAT_REF_ARS 0xE67E8004U +#define MSTATQ_STATQC 0xE67E8008U +#define MSTATQ_WTENABLE 0xE67E8030U +#define MSTATQ_WTREFRESH 0xE67E8034U +#define MSTATQ_WTSETTING0 0xE67E8038U +#define MSTATQ_WTSETTING1 0xE67E803CU + +#define QOS_BASE1 (0xE67F0000U) +#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U) +#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U) +#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U) +#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U) +#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U) +#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U) +#define QOSCTRL_EC (QOS_BASE1 + 0x003CU) +#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U) +#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U) +#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U) +#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U) +#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U) + +/* other module */ +#define THS1_THCTR 0xE6198020U +#define THS1_TEMP 0xE6198028U diff --git a/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk b/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk new file mode 100644 index 000000000..2bcc2922d --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk @@ -0,0 +1,7 @@ +# +# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c diff --git a/drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h new file mode 100644 index 000000000..adf8dab18 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h @@ -0,0 +1,5887 @@ +/* + * Copyright (c) 2018-2019, Renesas Electronics Corporation. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define _reg_PHY_DQ_DM_SWIZZLE0 0x00000000U +#define _reg_PHY_DQ_DM_SWIZZLE1 0x00000001U +#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY 0x00000002U +#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY 0x00000003U +#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE 0x00000004U +#define _reg_PHY_CLK_BYPASS_OVERRIDE 0x00000005U +#define _reg_PHY_SW_WRDQ0_SHIFT 0x00000006U +#define _reg_PHY_SW_WRDQ1_SHIFT 0x00000007U +#define _reg_PHY_SW_WRDQ2_SHIFT 0x00000008U +#define _reg_PHY_SW_WRDQ3_SHIFT 0x00000009U +#define _reg_PHY_SW_WRDQ4_SHIFT 0x0000000aU +#define _reg_PHY_SW_WRDQ5_SHIFT 0x0000000bU +#define _reg_PHY_SW_WRDQ6_SHIFT 0x0000000cU +#define _reg_PHY_SW_WRDQ7_SHIFT 0x0000000dU +#define _reg_PHY_SW_WRDM_SHIFT 0x0000000eU +#define _reg_PHY_SW_WRDQS_SHIFT 0x0000000fU +#define _reg_PHY_DQ_TSEL_ENABLE 0x00000010U +#define _reg_PHY_DQ_TSEL_SELECT 0x00000011U +#define _reg_PHY_DQS_TSEL_ENABLE 0x00000012U +#define _reg_PHY_DQS_TSEL_SELECT 0x00000013U +#define _reg_PHY_TWO_CYC_PREAMBLE 0x00000014U +#define _reg_PHY_DBI_MODE 0x00000015U +#define _reg_PHY_PER_RANK_CS_MAP 0x00000016U +#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN 0x00000017U +#define _reg_PHY_PER_CS_TRAINING_INDEX 0x00000018U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY 0x00000019U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY 0x0000001aU +#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY 0x0000001bU +#define _reg_PHY_LP4_BOOT_RPTR_UPDATE 0x0000001cU +#define _reg_PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY 0x0000001dU +#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST 0x0000001eU +#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE 0x0000001fU +#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY 0x00000020U +#define _reg_PHY_LPBK_CONTROL 0x00000021U +#define _reg_PHY_LPBK_DFX_TIMEOUT_EN 0x00000022U +#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL 0x00000023U +#define _reg_PHY_AUTO_TIMING_MARGIN_OBS 0x00000024U +#define _reg_PHY_SLICE_PWR_RDC_DISABLE 0x00000025U +#define _reg_PHY_PRBS_PATTERN_START 0x00000026U +#define _reg_PHY_PRBS_PATTERN_MASK 0x00000027U +#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY 0x00000028U +#define _reg_PHY_GATE_ERROR_DELAY_SELECT 0x00000029U +#define _reg_SC_PHY_SNAP_OBS_REGS 0x0000002aU +#define _reg_PHY_LPDDR 0x0000002bU +#define _reg_PHY_LPDDR_TYPE 0x0000002cU +#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY 0x0000002dU +#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY 0x0000002eU +#define _reg_ON_FLY_GATE_ADJUST_EN 0x0000002fU +#define _reg_PHY_GATE_TRACKING_OBS 0x00000030U +#define _reg_PHY_DFI40_POLARITY 0x00000031U +#define _reg_PHY_LP4_PST_AMBLE 0x00000032U +#define _reg_PHY_RDLVL_PATT8 0x00000033U +#define _reg_PHY_RDLVL_PATT9 0x00000034U +#define _reg_PHY_RDLVL_PATT10 0x00000035U +#define _reg_PHY_RDLVL_PATT11 0x00000036U +#define _reg_PHY_LP4_RDLVL_PATT8 0x00000037U +#define _reg_PHY_LP4_RDLVL_PATT9 0x00000038U +#define _reg_PHY_LP4_RDLVL_PATT10 0x00000039U +#define _reg_PHY_LP4_RDLVL_PATT11 0x0000003aU +#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE 0x0000003bU +#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE 0x0000003cU +#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT 0x0000003dU +#define _reg_PHY_RDDQ_ENC_OBS_SELECT 0x0000003eU +#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT 0x0000003fU +#define _reg_PHY_WR_ENC_OBS_SELECT 0x00000040U +#define _reg_PHY_WR_SHIFT_OBS_SELECT 0x00000041U +#define _reg_PHY_FIFO_PTR_OBS_SELECT 0x00000042U +#define _reg_PHY_LVL_DEBUG_MODE 0x00000043U +#define _reg_SC_PHY_LVL_DEBUG_CONT 0x00000044U +#define _reg_PHY_WRLVL_CAPTURE_CNT 0x00000045U +#define _reg_PHY_WRLVL_UPDT_WAIT_CNT 0x00000046U +#define _reg_PHY_WRLVL_DQ_MASK 0x00000047U +#define _reg_PHY_GTLVL_CAPTURE_CNT 0x00000048U +#define _reg_PHY_GTLVL_UPDT_WAIT_CNT 0x00000049U +#define _reg_PHY_RDLVL_CAPTURE_CNT 0x0000004aU +#define _reg_PHY_RDLVL_UPDT_WAIT_CNT 0x0000004bU +#define _reg_PHY_RDLVL_OP_MODE 0x0000004cU +#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x0000004dU +#define _reg_PHY_RDLVL_DATA_MASK 0x0000004eU +#define _reg_PHY_RDLVL_DATA_SWIZZLE 0x0000004fU +#define _reg_PHY_WDQLVL_BURST_CNT 0x00000050U +#define _reg_PHY_WDQLVL_PATT 0x00000051U +#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET 0x00000052U +#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT 0x00000053U +#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT 0x00000054U +#define _reg_PHY_WDQLVL_QTR_DLY_STEP 0x00000055U +#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000056U +#define _reg_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000057U +#define _reg_PHY_WDQLVL_DATADM_MASK 0x00000058U +#define _reg_PHY_USER_PATT0 0x00000059U +#define _reg_PHY_USER_PATT1 0x0000005aU +#define _reg_PHY_USER_PATT2 0x0000005bU +#define _reg_PHY_USER_PATT3 0x0000005cU +#define _reg_PHY_USER_PATT4 0x0000005dU +#define _reg_PHY_DQ_SWIZZLING 0x0000005eU +#define _reg_PHY_CALVL_VREF_DRIVING_SLICE 0x0000005fU +#define _reg_SC_PHY_MANUAL_CLEAR 0x00000060U +#define _reg_PHY_FIFO_PTR_OBS 0x00000061U +#define _reg_PHY_LPBK_RESULT_OBS 0x00000062U +#define _reg_PHY_LPBK_ERROR_COUNT_OBS 0x00000063U +#define _reg_PHY_MASTER_DLY_LOCK_OBS 0x00000064U +#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS 0x00000065U +#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS 0x00000066U +#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS 0x00000067U +#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS 0x00000068U +#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS 0x00000069U +#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS 0x0000006aU +#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS 0x0000006bU +#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS 0x0000006cU +#define _reg_PHY_WR_SHIFT_OBS 0x0000006dU +#define _reg_PHY_WRLVL_HARD0_DELAY_OBS 0x0000006eU +#define _reg_PHY_WRLVL_HARD1_DELAY_OBS 0x0000006fU +#define _reg_PHY_WRLVL_STATUS_OBS 0x00000070U +#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS 0x00000071U +#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS 0x00000072U +#define _reg_PHY_WRLVL_ERROR_OBS 0x00000073U +#define _reg_PHY_GTLVL_HARD0_DELAY_OBS 0x00000074U +#define _reg_PHY_GTLVL_HARD1_DELAY_OBS 0x00000075U +#define _reg_PHY_GTLVL_STATUS_OBS 0x00000076U +#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x00000077U +#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x00000078U +#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS 0x00000079U +#define _reg_PHY_RDLVL_STATUS_OBS 0x0000007aU +#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS 0x0000007bU +#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS 0x0000007cU +#define _reg_PHY_WDQLVL_STATUS_OBS 0x0000007dU +#define _reg_PHY_DDL_MODE 0x0000007eU +#define _reg_PHY_DDL_TEST_OBS 0x0000007fU +#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS 0x00000080U +#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD 0x00000081U +#define _reg_PHY_LP4_WDQS_OE_EXTEND 0x00000082U +#define _reg_SC_PHY_RX_CAL_START 0x00000083U +#define _reg_PHY_RX_CAL_OVERRIDE 0x00000084U +#define _reg_PHY_RX_CAL_SAMPLE_WAIT 0x00000085U +#define _reg_PHY_RX_CAL_DQ0 0x00000086U +#define _reg_PHY_RX_CAL_DQ1 0x00000087U +#define _reg_PHY_RX_CAL_DQ2 0x00000088U +#define _reg_PHY_RX_CAL_DQ3 0x00000089U +#define _reg_PHY_RX_CAL_DQ4 0x0000008aU +#define _reg_PHY_RX_CAL_DQ5 0x0000008bU +#define _reg_PHY_RX_CAL_DQ6 0x0000008cU +#define _reg_PHY_RX_CAL_DQ7 0x0000008dU +#define _reg_PHY_RX_CAL_DM 0x0000008eU +#define _reg_PHY_RX_CAL_DQS 0x0000008fU +#define _reg_PHY_RX_CAL_FDBK 0x00000090U +#define _reg_PHY_RX_CAL_OBS 0x00000091U +#define _reg_PHY_RX_CAL_LOCK_OBS 0x00000092U +#define _reg_PHY_RX_CAL_DISABLE 0x00000093U +#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY 0x00000094U +#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY 0x00000095U +#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY 0x00000096U +#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY 0x00000097U +#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY 0x00000098U +#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY 0x00000099U +#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY 0x0000009aU +#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY 0x0000009bU +#define _reg_PHY_CLK_WRDM_SLAVE_DELAY 0x0000009cU +#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY 0x0000009dU +#define _reg_PHY_WRLVL_THRESHOLD_ADJUST 0x0000009eU +#define _reg_PHY_RDDQ0_SLAVE_DELAY 0x0000009fU +#define _reg_PHY_RDDQ1_SLAVE_DELAY 0x000000a0U +#define _reg_PHY_RDDQ2_SLAVE_DELAY 0x000000a1U +#define _reg_PHY_RDDQ3_SLAVE_DELAY 0x000000a2U +#define _reg_PHY_RDDQ4_SLAVE_DELAY 0x000000a3U +#define _reg_PHY_RDDQ5_SLAVE_DELAY 0x000000a4U +#define _reg_PHY_RDDQ6_SLAVE_DELAY 0x000000a5U +#define _reg_PHY_RDDQ7_SLAVE_DELAY 0x000000a6U +#define _reg_PHY_RDDM_SLAVE_DELAY 0x000000a7U +#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY 0x000000a8U +#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY 0x000000a9U +#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY 0x000000aaU +#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY 0x000000abU +#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY 0x000000acU +#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY 0x000000adU +#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY 0x000000aeU +#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY 0x000000afU +#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY 0x000000b0U +#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY 0x000000b1U +#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY 0x000000b2U +#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY 0x000000b3U +#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY 0x000000b4U +#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY 0x000000b5U +#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY 0x000000b6U +#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY 0x000000b7U +#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY 0x000000b8U +#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY 0x000000b9U +#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY 0x000000baU +#define _reg_PHY_RDDQS_LATENCY_ADJUST 0x000000bbU +#define _reg_PHY_WRITE_PATH_LAT_ADD 0x000000bcU +#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD 0x000000bdU +#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD 0x000000beU +#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO 0x000000bfU +#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START 0x000000c0U +#define _reg_PHY_GTLVL_LAT_ADJ_START 0x000000c1U +#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START 0x000000c2U +#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START 0x000000c3U +#define _reg_PHY_FDBK_PWR_CTRL 0x000000c4U +#define _reg_PHY_DQ_OE_TIMING 0x000000c5U +#define _reg_PHY_DQ_TSEL_RD_TIMING 0x000000c6U +#define _reg_PHY_DQ_TSEL_WR_TIMING 0x000000c7U +#define _reg_PHY_DQS_OE_TIMING 0x000000c8U +#define _reg_PHY_DQS_TSEL_RD_TIMING 0x000000c9U +#define _reg_PHY_DQS_OE_RD_TIMING 0x000000caU +#define _reg_PHY_DQS_TSEL_WR_TIMING 0x000000cbU +#define _reg_PHY_PER_CS_TRAINING_EN 0x000000ccU +#define _reg_PHY_DQ_IE_TIMING 0x000000cdU +#define _reg_PHY_DQS_IE_TIMING 0x000000ceU +#define _reg_PHY_RDDATA_EN_IE_DLY 0x000000cfU +#define _reg_PHY_IE_MODE 0x000000d0U +#define _reg_PHY_RDDATA_EN_DLY 0x000000d1U +#define _reg_PHY_RDDATA_EN_TSEL_DLY 0x000000d2U +#define _reg_PHY_RDDATA_EN_OE_DLY 0x000000d3U +#define _reg_PHY_SW_MASTER_MODE 0x000000d4U +#define _reg_PHY_MASTER_DELAY_START 0x000000d5U +#define _reg_PHY_MASTER_DELAY_STEP 0x000000d6U +#define _reg_PHY_MASTER_DELAY_WAIT 0x000000d7U +#define _reg_PHY_MASTER_DELAY_HALF_MEASURE 0x000000d8U +#define _reg_PHY_RPTR_UPDATE 0x000000d9U +#define _reg_PHY_WRLVL_DLY_STEP 0x000000daU +#define _reg_PHY_WRLVL_RESP_WAIT_CNT 0x000000dbU +#define _reg_PHY_GTLVL_DLY_STEP 0x000000dcU +#define _reg_PHY_GTLVL_RESP_WAIT_CNT 0x000000ddU +#define _reg_PHY_GTLVL_BACK_STEP 0x000000deU +#define _reg_PHY_GTLVL_FINAL_STEP 0x000000dfU +#define _reg_PHY_WDQLVL_DLY_STEP 0x000000e0U +#define _reg_PHY_TOGGLE_PRE_SUPPORT 0x000000e1U +#define _reg_PHY_RDLVL_DLY_STEP 0x000000e2U +#define _reg_PHY_WRPATH_GATE_DISABLE 0x000000e3U +#define _reg_PHY_WRPATH_GATE_TIMING 0x000000e4U +#define _reg_PHY_ADR0_SW_WRADDR_SHIFT 0x000000e5U +#define _reg_PHY_ADR1_SW_WRADDR_SHIFT 0x000000e6U +#define _reg_PHY_ADR2_SW_WRADDR_SHIFT 0x000000e7U +#define _reg_PHY_ADR3_SW_WRADDR_SHIFT 0x000000e8U +#define _reg_PHY_ADR4_SW_WRADDR_SHIFT 0x000000e9U +#define _reg_PHY_ADR5_SW_WRADDR_SHIFT 0x000000eaU +#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY 0x000000ebU +#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE 0x000000ecU +#define _reg_SC_PHY_ADR_MANUAL_CLEAR 0x000000edU +#define _reg_PHY_ADR_LPBK_RESULT_OBS 0x000000eeU +#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS 0x000000efU +#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT 0x000000f0U +#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS 0x000000f1U +#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS 0x000000f2U +#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS 0x000000f3U +#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE 0x000000f4U +#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT 0x000000f5U +#define _reg_SC_PHY_ADR_SNAP_OBS_REGS 0x000000f6U +#define _reg_PHY_ADR_TSEL_ENABLE 0x000000f7U +#define _reg_PHY_ADR_LPBK_CONTROL 0x000000f8U +#define _reg_PHY_ADR_PRBS_PATTERN_START 0x000000f9U +#define _reg_PHY_ADR_PRBS_PATTERN_MASK 0x000000faU +#define _reg_PHY_ADR_PWR_RDC_DISABLE 0x000000fbU +#define _reg_PHY_ADR_TYPE 0x000000fcU +#define _reg_PHY_ADR_WRADDR_SHIFT_OBS 0x000000fdU +#define _reg_PHY_ADR_IE_MODE 0x000000feU +#define _reg_PHY_ADR_DDL_MODE 0x000000ffU +#define _reg_PHY_ADR_DDL_TEST_OBS 0x00000100U +#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS 0x00000101U +#define _reg_PHY_ADR_CALVL_START 0x00000102U +#define _reg_PHY_ADR_CALVL_COARSE_DLY 0x00000103U +#define _reg_PHY_ADR_CALVL_QTR 0x00000104U +#define _reg_PHY_ADR_CALVL_SWIZZLE0 0x00000105U +#define _reg_PHY_ADR_CALVL_SWIZZLE1 0x00000106U +#define _reg_PHY_ADR_CALVL_SWIZZLE0_0 0x00000107U +#define _reg_PHY_ADR_CALVL_SWIZZLE1_0 0x00000108U +#define _reg_PHY_ADR_CALVL_SWIZZLE0_1 0x00000109U +#define _reg_PHY_ADR_CALVL_SWIZZLE1_1 0x0000010aU +#define _reg_PHY_ADR_CALVL_DEVICE_MAP 0x0000010bU +#define _reg_PHY_ADR_CALVL_RANK_CTRL 0x0000010cU +#define _reg_PHY_ADR_CALVL_NUM_PATTERNS 0x0000010dU +#define _reg_PHY_ADR_CALVL_CAPTURE_CNT 0x0000010eU +#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT 0x0000010fU +#define _reg_PHY_ADR_CALVL_DEBUG_MODE 0x00000110U +#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT 0x00000111U +#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR 0x00000112U +#define _reg_PHY_ADR_CALVL_OBS_SELECT 0x00000113U +#define _reg_PHY_ADR_CALVL_OBS0 0x00000114U +#define _reg_PHY_ADR_CALVL_OBS1 0x00000115U +#define _reg_PHY_ADR_CALVL_RESULT 0x00000116U +#define _reg_PHY_ADR_CALVL_FG_0 0x00000117U +#define _reg_PHY_ADR_CALVL_BG_0 0x00000118U +#define _reg_PHY_ADR_CALVL_FG_1 0x00000119U +#define _reg_PHY_ADR_CALVL_BG_1 0x0000011aU +#define _reg_PHY_ADR_CALVL_FG_2 0x0000011bU +#define _reg_PHY_ADR_CALVL_BG_2 0x0000011cU +#define _reg_PHY_ADR_CALVL_FG_3 0x0000011dU +#define _reg_PHY_ADR_CALVL_BG_3 0x0000011eU +#define _reg_PHY_ADR_ADDR_SEL 0x0000011fU +#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY 0x00000120U +#define _reg_PHY_ADR_BIT_MASK 0x00000121U +#define _reg_PHY_ADR_SEG_MASK 0x00000122U +#define _reg_PHY_ADR_CALVL_TRAIN_MASK 0x00000123U +#define _reg_PHY_ADR_CSLVL_TRAIN_MASK 0x00000124U +#define _reg_PHY_ADR_SW_TXIO_CTRL 0x00000125U +#define _reg_PHY_ADR_TSEL_SELECT 0x00000126U +#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY 0x00000127U +#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY 0x00000128U +#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY 0x00000129U +#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY 0x0000012aU +#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY 0x0000012bU +#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY 0x0000012cU +#define _reg_PHY_ADR_SW_MASTER_MODE 0x0000012dU +#define _reg_PHY_ADR_MASTER_DELAY_START 0x0000012eU +#define _reg_PHY_ADR_MASTER_DELAY_STEP 0x0000012fU +#define _reg_PHY_ADR_MASTER_DELAY_WAIT 0x00000130U +#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE 0x00000131U +#define _reg_PHY_ADR_CALVL_DLY_STEP 0x00000132U +#define _reg_PHY_FREQ_SEL 0x00000133U +#define _reg_PHY_FREQ_SEL_FROM_REGIF 0x00000134U +#define _reg_PHY_FREQ_SEL_MULTICAST_EN 0x00000135U +#define _reg_PHY_FREQ_SEL_INDEX 0x00000136U +#define _reg_PHY_SW_GRP_SHIFT_0 0x00000137U +#define _reg_PHY_SW_GRP_SHIFT_1 0x00000138U +#define _reg_PHY_SW_GRP_SHIFT_2 0x00000139U +#define _reg_PHY_SW_GRP_SHIFT_3 0x0000013aU +#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY 0x0000013bU +#define _reg_PHY_SW_GRP_BYPASS_SHIFT 0x0000013cU +#define _reg_PHY_GRP_BYPASS_OVERRIDE 0x0000013dU +#define _reg_SC_PHY_MANUAL_UPDATE 0x0000013eU +#define _reg_SC_PHY_MANUAL_UPDATE_PHYUPD_ENABLE 0x0000013fU +#define _reg_PHY_LP4_BOOT_DISABLE 0x00000140U +#define _reg_PHY_CSLVL_ENABLE 0x00000141U +#define _reg_PHY_CSLVL_CS_MAP 0x00000142U +#define _reg_PHY_CSLVL_START 0x00000143U +#define _reg_PHY_CSLVL_QTR 0x00000144U +#define _reg_PHY_CSLVL_COARSE_CHK 0x00000145U +#define _reg_PHY_CSLVL_CAPTURE_CNT 0x00000146U +#define _reg_PHY_CSLVL_COARSE_DLY 0x00000147U +#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT 0x00000148U +#define _reg_PHY_CSLVL_DEBUG_MODE 0x00000149U +#define _reg_SC_PHY_CSLVL_DEBUG_CONT 0x0000014aU +#define _reg_SC_PHY_CSLVL_ERROR_CLR 0x0000014bU +#define _reg_PHY_CSLVL_OBS0 0x0000014cU +#define _reg_PHY_CSLVL_OBS1 0x0000014dU +#define _reg_PHY_CALVL_CS_MAP 0x0000014eU +#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT 0x0000014fU +#define _reg_PHY_GRP_SHIFT_OBS_SELECT 0x00000150U +#define _reg_PHY_GRP_SLV_DLY_ENC_OBS 0x00000151U +#define _reg_PHY_GRP_SHIFT_OBS 0x00000152U +#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE 0x00000153U +#define _reg_PHY_ADRCTL_SNAP_OBS_REGS 0x00000154U +#define _reg_PHY_DFI_PHYUPD_TYPE 0x00000155U +#define _reg_PHY_ADRCTL_LPDDR 0x00000156U +#define _reg_PHY_LP4_ACTIVE 0x00000157U +#define _reg_PHY_LPDDR3_CS 0x00000158U +#define _reg_PHY_CALVL_RESULT_MASK 0x00000159U +#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES 0x0000015aU +#define _reg_PHY_SW_TXIO_CTRL_0 0x0000015bU +#define _reg_PHY_SW_TXIO_CTRL_1 0x0000015cU +#define _reg_PHY_SW_TXIO_CTRL_2 0x0000015dU +#define _reg_PHY_SW_TXIO_CTRL_3 0x0000015eU +#define _reg_PHY_MEMCLK_SW_TXIO_CTRL 0x0000015fU +#define _reg_PHY_CA_SW_TXPWR_CTRL 0x00000160U +#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL 0x00000161U +#define _reg_PHY_USER_DEF_REG_AC_0 0x00000162U +#define _reg_PHY_USER_DEF_REG_AC_1 0x00000163U +#define _reg_PHY_USER_DEF_REG_AC_2 0x00000164U +#define _reg_PHY_USER_DEF_REG_AC_3 0x00000165U +#define _reg_PHY_UPDATE_CLK_CAL_VALUES 0x00000166U +#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE 0x00000167U +#define _reg_PHY_PLL_CTRL 0x00000168U +#define _reg_PHY_PLL_CTRL_TOP 0x00000169U +#define _reg_PHY_PLL_CTRL_CA 0x0000016aU +#define _reg_PHY_PLL_BYPASS 0x0000016bU +#define _reg_PHY_LOW_FREQ_SEL 0x0000016cU +#define _reg_PHY_PAD_VREF_CTRL_DQ_0 0x0000016dU +#define _reg_PHY_PAD_VREF_CTRL_DQ_1 0x0000016eU +#define _reg_PHY_PAD_VREF_CTRL_DQ_2 0x0000016fU +#define _reg_PHY_PAD_VREF_CTRL_DQ_3 0x00000170U +#define _reg_PHY_PAD_VREF_CTRL_AC 0x00000171U +#define _reg_PHY_CSLVL_DLY_STEP 0x00000172U +#define _reg_PHY_SET_DFI_INPUT_0 0x00000173U +#define _reg_PHY_SET_DFI_INPUT_1 0x00000174U +#define _reg_PHY_SET_DFI_INPUT_2 0x00000175U +#define _reg_PHY_SET_DFI_INPUT_3 0x00000176U +#define _reg_PHY_GRP_SLAVE_DELAY_0 0x00000177U +#define _reg_PHY_GRP_SLAVE_DELAY_1 0x00000178U +#define _reg_PHY_GRP_SLAVE_DELAY_2 0x00000179U +#define _reg_PHY_GRP_SLAVE_DELAY_3 0x0000017aU +#define _reg_PHY_CS_ACS_ALLOCATION_0 0x0000017bU +#define _reg_PHY_CS_ACS_ALLOCATION_1 0x0000017cU +#define _reg_PHY_CS_ACS_ALLOCATION_2 0x0000017dU +#define _reg_PHY_CS_ACS_ALLOCATION_3 0x0000017eU +#define _reg_PHY_LP4_BOOT_PLL_CTRL 0x0000017fU +#define _reg_PHY_LP4_BOOT_PLL_CTRL_CA 0x00000180U +#define _reg_PHY_LP4_BOOT_TOP_PLL_CTRL 0x00000181U +#define _reg_PHY_PLL_CTRL_OVERRIDE 0x00000182U +#define _reg_PHY_PLL_WAIT 0x00000183U +#define _reg_PHY_PLL_WAIT_TOP 0x00000184U +#define _reg_PHY_PLL_OBS_0 0x00000185U +#define _reg_PHY_PLL_OBS_1 0x00000186U +#define _reg_PHY_PLL_OBS_2 0x00000187U +#define _reg_PHY_PLL_OBS_3 0x00000188U +#define _reg_PHY_PLL_OBS_4 0x00000189U +#define _reg_PHY_PLL_TESTOUT_SEL 0x0000018aU +#define _reg_PHY_TCKSRE_WAIT 0x0000018bU +#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL 0x0000018cU +#define _reg_PHY_LP_WAKEUP 0x0000018dU +#define _reg_PHY_LS_IDLE_EN 0x0000018eU +#define _reg_PHY_LP_CTRLUPD_CNTR_CFG 0x0000018fU +#define _reg_PHY_TDFI_PHY_WRDELAY 0x00000190U +#define _reg_PHY_PAD_FDBK_DRIVE 0x00000191U +#define _reg_PHY_PAD_DATA_DRIVE 0x00000192U +#define _reg_PHY_PAD_DQS_DRIVE 0x00000193U +#define _reg_PHY_PAD_ADDR_DRIVE 0x00000194U +#define _reg_PHY_PAD_CLK_DRIVE 0x00000195U +#define _reg_PHY_PAD_FDBK_TERM 0x00000196U +#define _reg_PHY_PAD_DATA_TERM 0x00000197U +#define _reg_PHY_PAD_DQS_TERM 0x00000198U +#define _reg_PHY_PAD_ADDR_TERM 0x00000199U +#define _reg_PHY_PAD_CLK_TERM 0x0000019aU +#define _reg_PHY_PAD_CKE_DRIVE 0x0000019bU +#define _reg_PHY_PAD_CKE_TERM 0x0000019cU +#define _reg_PHY_PAD_RST_DRIVE 0x0000019dU +#define _reg_PHY_PAD_RST_TERM 0x0000019eU +#define _reg_PHY_PAD_CS_DRIVE 0x0000019fU +#define _reg_PHY_PAD_CS_TERM 0x000001a0U +#define _reg_PHY_PAD_ODT_DRIVE 0x000001a1U +#define _reg_PHY_PAD_ODT_TERM 0x000001a2U +#define _reg_PHY_ADRCTL_RX_CAL 0x000001a3U +#define _reg_PHY_ADRCTL_LP3_RX_CAL 0x000001a4U +#define _reg_PHY_TST_CLK_PAD_CTRL 0x000001a5U +#define _reg_PHY_TST_CLK_PAD_CTRL2 0x000001a6U +#define _reg_PHY_CAL_MODE_0 0x000001a7U +#define _reg_PHY_CAL_CLEAR_0 0x000001a8U +#define _reg_PHY_CAL_START_0 0x000001a9U +#define _reg_PHY_CAL_INTERVAL_COUNT_0 0x000001aaU +#define _reg_PHY_CAL_SAMPLE_WAIT_0 0x000001abU +#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0 0x000001acU +#define _reg_PHY_CAL_CLK_SELECT_0 0x000001adU +#define _reg_PHY_CAL_RESULT_OBS_0 0x000001aeU +#define _reg_PHY_CAL_RESULT2_OBS_0 0x000001afU +#define _reg_PHY_CAL_CPTR_CNT_0 0x000001b0U +#define _reg_PHY_CAL_SETTLING_PRD_0 0x000001b1U +#define _reg_PHY_CAL_PU_FINE_ADJ_0 0x000001b2U +#define _reg_PHY_CAL_PD_FINE_ADJ_0 0x000001b3U +#define _reg_PHY_CAL_RCV_FINE_ADJ_0 0x000001b4U +#define _reg_PHY_CAL_DBG_CFG_0 0x000001b5U +#define _reg_SC_PHY_PAD_DBG_CONT_0 0x000001b6U +#define _reg_PHY_CAL_RESULT3_OBS_0 0x000001b7U +#define _reg_PHY_ADRCTL_PVT_MAP_0 0x000001b8U +#define _reg_PHY_CAL_SLOPE_ADJ_0 0x000001b9U +#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0 0x000001baU +#define _reg_PHY_CAL_TWO_PASS_CFG_0 0x000001bbU +#define _reg_PHY_CAL_SW_CAL_CFG_0 0x000001bcU +#define _reg_PHY_CAL_RANGE_MIN_0 0x000001bdU +#define _reg_PHY_CAL_RANGE_MAX_0 0x000001beU +#define _reg_PHY_PAD_ATB_CTRL 0x000001bfU +#define _reg_PHY_ADRCTL_MANUAL_UPDATE 0x000001c0U +#define _reg_PHY_AC_LPBK_ERR_CLEAR 0x000001c1U +#define _reg_PHY_AC_LPBK_OBS_SELECT 0x000001c2U +#define _reg_PHY_AC_LPBK_ENABLE 0x000001c3U +#define _reg_PHY_AC_LPBK_CONTROL 0x000001c4U +#define _reg_PHY_AC_PRBS_PATTERN_START 0x000001c5U +#define _reg_PHY_AC_PRBS_PATTERN_MASK 0x000001c6U +#define _reg_PHY_AC_LPBK_RESULT_OBS 0x000001c7U +#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT 0x000001c8U +#define _reg_PHY_AC_CLK_LPBK_ENABLE 0x000001c9U +#define _reg_PHY_AC_CLK_LPBK_CONTROL 0x000001caU +#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS 0x000001cbU +#define _reg_PHY_AC_PWR_RDC_DISABLE 0x000001ccU +#define _reg_PHY_DATA_BYTE_ORDER_SEL 0x000001cdU +#define _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH 0x000001ceU +#define _reg_PHY_LPDDR4_CONNECT 0x000001cfU +#define _reg_PHY_CALVL_DEVICE_MAP 0x000001d0U +#define _reg_PHY_ADR_DISABLE 0x000001d1U +#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL 0x000001d2U +#define _reg_PHY_CS_DLY_UPT_PER_AC_SLICE 0x000001d3U +#define _reg_PHY_DDL_AC_ENABLE 0x000001d4U +#define _reg_PHY_DDL_AC_MODE 0x000001d5U +#define _reg_PHY_PAD_BACKGROUND_CAL 0x000001d6U +#define _reg_PHY_INIT_UPDATE_CONFIG 0x000001d7U +#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC 0x000001d8U +#define _reg_PHY_DLL_RST_EN 0x000001d9U +#define _reg_PHY_AC_INIT_COMPLETE_OBS 0x000001daU +#define _reg_PHY_DS_INIT_COMPLETE_OBS 0x000001dbU +#define _reg_PHY_UPDATE_MASK 0x000001dcU +#define _reg_PHY_PLL_SWITCH_CNT 0x000001ddU +#define _reg_PI_START 0x000001deU +#define _reg_PI_DRAM_CLASS 0x000001dfU +#define _reg_PI_VERSION 0x000001e0U +#define _reg_PI_NORMAL_LVL_SEQ 0x000001e1U +#define _reg_PI_INIT_LVL_EN 0x000001e2U +#define _reg_PI_NOTCARE_PHYUPD 0x000001e3U +#define _reg_PI_ONBUS_MBIST 0x000001e4U +#define _reg_PI_TCMD_GAP 0x000001e5U +#define _reg_PI_MASTER_ACK_DURATION_MIN 0x000001e6U +#define _reg_PI_DFI_VERSION 0x000001e7U +#define _reg_PI_TDFI_PHYMSTR_TYPE0 0x000001e8U +#define _reg_PI_TDFI_PHYMSTR_TYPE1 0x000001e9U +#define _reg_PI_TDFI_PHYMSTR_TYPE2 0x000001eaU +#define _reg_PI_TDFI_PHYMSTR_TYPE3 0x000001ebU +#define _reg_PI_DFI_PHYMSTR_TYPE 0x000001ecU +#define _reg_PI_DFI_PHYMSTR_CS_STATE_R 0x000001edU +#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R 0x000001eeU +#define _reg_PI_TDFI_PHYMSTR_MAX_F0 0x000001efU +#define _reg_PI_TDFI_PHYMSTR_RESP_F0 0x000001f0U +#define _reg_PI_TDFI_PHYMSTR_MAX_F1 0x000001f1U +#define _reg_PI_TDFI_PHYMSTR_RESP_F1 0x000001f2U +#define _reg_PI_TDFI_PHYMSTR_MAX_F2 0x000001f3U +#define _reg_PI_TDFI_PHYMSTR_RESP_F2 0x000001f4U +#define _reg_PI_TDFI_PHYUPD_RESP_F0 0x000001f5U +#define _reg_PI_TDFI_PHYUPD_TYPE0_F0 0x000001f6U +#define _reg_PI_TDFI_PHYUPD_TYPE1_F0 0x000001f7U +#define _reg_PI_TDFI_PHYUPD_TYPE2_F0 0x000001f8U +#define _reg_PI_TDFI_PHYUPD_TYPE3_F0 0x000001f9U +#define _reg_PI_TDFI_PHYUPD_RESP_F1 0x000001faU +#define _reg_PI_TDFI_PHYUPD_TYPE0_F1 0x000001fbU +#define _reg_PI_TDFI_PHYUPD_TYPE1_F1 0x000001fcU +#define _reg_PI_TDFI_PHYUPD_TYPE2_F1 0x000001fdU +#define _reg_PI_TDFI_PHYUPD_TYPE3_F1 0x000001feU +#define _reg_PI_TDFI_PHYUPD_RESP_F2 0x000001ffU +#define _reg_PI_TDFI_PHYUPD_TYPE0_F2 0x00000200U +#define _reg_PI_TDFI_PHYUPD_TYPE1_F2 0x00000201U +#define _reg_PI_TDFI_PHYUPD_TYPE2_F2 0x00000202U +#define _reg_PI_TDFI_PHYUPD_TYPE3_F2 0x00000203U +#define _reg_PI_CONTROL_ERROR_STATUS 0x00000204U +#define _reg_PI_EXIT_AFTER_INIT_CALVL 0x00000205U +#define _reg_PI_FREQ_MAP 0x00000206U +#define _reg_PI_INIT_WORK_FREQ 0x00000207U +#define _reg_PI_INIT_DFS_CALVL_ONLY 0x00000208U +#define _reg_PI_POWER_ON_SEQ_BYPASS_ARRAY 0x00000209U +#define _reg_PI_POWER_ON_SEQ_END_ARRAY 0x0000020aU +#define _reg_PI_SEQ1_PAT 0x0000020bU +#define _reg_PI_SEQ1_PAT_MASK 0x0000020cU +#define _reg_PI_SEQ2_PAT 0x0000020dU +#define _reg_PI_SEQ2_PAT_MASK 0x0000020eU +#define _reg_PI_SEQ3_PAT 0x0000020fU +#define _reg_PI_SEQ3_PAT_MASK 0x00000210U +#define _reg_PI_SEQ4_PAT 0x00000211U +#define _reg_PI_SEQ4_PAT_MASK 0x00000212U +#define _reg_PI_SEQ5_PAT 0x00000213U +#define _reg_PI_SEQ5_PAT_MASK 0x00000214U +#define _reg_PI_SEQ6_PAT 0x00000215U +#define _reg_PI_SEQ6_PAT_MASK 0x00000216U +#define _reg_PI_SEQ7_PAT 0x00000217U +#define _reg_PI_SEQ7_PAT_MASK 0x00000218U +#define _reg_PI_SEQ8_PAT 0x00000219U +#define _reg_PI_SEQ8_PAT_MASK 0x0000021aU +#define _reg_PI_WDT_DISABLE 0x0000021bU +#define _reg_PI_SW_RST_N 0x0000021cU +#define _reg_RESERVED_R0 0x0000021dU +#define _reg_PI_CS_MAP 0x0000021eU +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0 0x0000021fU +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x00000220U +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x00000221U +#define _reg_PI_TMRR 0x00000222U +#define _reg_PI_WRLAT_F0 0x00000223U +#define _reg_PI_ADDITIVE_LAT_F0 0x00000224U +#define _reg_PI_CASLAT_LIN_F0 0x00000225U +#define _reg_PI_WRLAT_F1 0x00000226U +#define _reg_PI_ADDITIVE_LAT_F1 0x00000227U +#define _reg_PI_CASLAT_LIN_F1 0x00000228U +#define _reg_PI_WRLAT_F2 0x00000229U +#define _reg_PI_ADDITIVE_LAT_F2 0x0000022aU +#define _reg_PI_CASLAT_LIN_F2 0x0000022bU +#define _reg_PI_PREAMBLE_SUPPORT 0x0000022cU +#define _reg_PI_AREFRESH 0x0000022dU +#define _reg_PI_MCAREF_FORWARD_ONLY 0x0000022eU +#define _reg_PI_TRFC_F0 0x0000022fU +#define _reg_PI_TREF_F0 0x00000230U +#define _reg_PI_TRFC_F1 0x00000231U +#define _reg_PI_TREF_F1 0x00000232U +#define _reg_PI_TRFC_F2 0x00000233U +#define _reg_PI_TREF_F2 0x00000234U +#define _reg_RESERVED_H3VER2 0x00000235U +#define _reg_PI_TREF_INTERVAL 0x00000236U +#define _reg_PI_FREQ_CHANGE_REG_COPY 0x00000237U +#define _reg_PI_FREQ_SEL_FROM_REGIF 0x00000238U +#define _reg_PI_SWLVL_LOAD 0x00000239U +#define _reg_PI_SWLVL_OP_DONE 0x0000023aU +#define _reg_PI_SW_WRLVL_RESP_0 0x0000023bU +#define _reg_PI_SW_WRLVL_RESP_1 0x0000023cU +#define _reg_PI_SW_WRLVL_RESP_2 0x0000023dU +#define _reg_PI_SW_WRLVL_RESP_3 0x0000023eU +#define _reg_PI_SW_RDLVL_RESP_0 0x0000023fU +#define _reg_PI_SW_RDLVL_RESP_1 0x00000240U +#define _reg_PI_SW_RDLVL_RESP_2 0x00000241U +#define _reg_PI_SW_RDLVL_RESP_3 0x00000242U +#define _reg_PI_SW_CALVL_RESP_0 0x00000243U +#define _reg_PI_SW_LEVELING_MODE 0x00000244U +#define _reg_PI_SWLVL_START 0x00000245U +#define _reg_PI_SWLVL_EXIT 0x00000246U +#define _reg_PI_SWLVL_WR_SLICE_0 0x00000247U +#define _reg_PI_SWLVL_RD_SLICE_0 0x00000248U +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0 0x00000249U +#define _reg_PI_SW_WDQLVL_RESP_0 0x0000024aU +#define _reg_PI_SWLVL_WR_SLICE_1 0x0000024bU +#define _reg_PI_SWLVL_RD_SLICE_1 0x0000024cU +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1 0x0000024dU +#define _reg_PI_SW_WDQLVL_RESP_1 0x0000024eU +#define _reg_PI_SWLVL_WR_SLICE_2 0x0000024fU +#define _reg_PI_SWLVL_RD_SLICE_2 0x00000250U +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_2 0x00000251U +#define _reg_PI_SW_WDQLVL_RESP_2 0x00000252U +#define _reg_PI_SWLVL_WR_SLICE_3 0x00000253U +#define _reg_PI_SWLVL_RD_SLICE_3 0x00000254U +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_3 0x00000255U +#define _reg_PI_SW_WDQLVL_RESP_3 0x00000256U +#define _reg_PI_SW_WDQLVL_VREF 0x00000257U +#define _reg_PI_SWLVL_SM2_START 0x00000258U +#define _reg_PI_SWLVL_SM2_WR 0x00000259U +#define _reg_PI_SWLVL_SM2_RD 0x0000025aU +#define _reg_PI_SEQUENTIAL_LVL_REQ 0x0000025bU +#define _reg_PI_DFS_PERIOD_EN 0x0000025cU +#define _reg_PI_SRE_PERIOD_EN 0x0000025dU +#define _reg_PI_DFI40_POLARITY 0x0000025eU +#define _reg_PI_16BIT_DRAM_CONNECT 0x0000025fU +#define _reg_PI_TDFI_CTRL_DELAY_F0 0x00000260U +#define _reg_PI_TDFI_CTRL_DELAY_F1 0x00000261U +#define _reg_PI_TDFI_CTRL_DELAY_F2 0x00000262U +#define _reg_PI_WRLVL_REQ 0x00000263U +#define _reg_PI_WRLVL_CS 0x00000264U +#define _reg_PI_WLDQSEN 0x00000265U +#define _reg_PI_WLMRD 0x00000266U +#define _reg_PI_WRLVL_EN_F0 0x00000267U +#define _reg_PI_WRLVL_EN_F1 0x00000268U +#define _reg_PI_WRLVL_EN_F2 0x00000269U +#define _reg_PI_WRLVL_EN 0x0000026aU +#define _reg_PI_WRLVL_INTERVAL 0x0000026bU +#define _reg_PI_WRLVL_PERIODIC 0x0000026cU +#define _reg_PI_WRLVL_ON_SREF_EXIT 0x0000026dU +#define _reg_PI_WRLVL_DISABLE_DFS 0x0000026eU +#define _reg_PI_WRLVL_RESP_MASK 0x0000026fU +#define _reg_PI_WRLVL_ROTATE 0x00000270U +#define _reg_PI_WRLVL_CS_MAP 0x00000271U +#define _reg_PI_WRLVL_ERROR_STATUS 0x00000272U +#define _reg_PI_TDFI_WRLVL_EN 0x00000273U +#define _reg_PI_TDFI_WRLVL_WW_F0 0x00000274U +#define _reg_PI_TDFI_WRLVL_WW_F1 0x00000275U +#define _reg_PI_TDFI_WRLVL_WW_F2 0x00000276U +#define _reg_PI_TDFI_WRLVL_WW 0x00000277U +#define _reg_PI_TDFI_WRLVL_RESP 0x00000278U +#define _reg_PI_TDFI_WRLVL_MAX 0x00000279U +#define _reg_PI_WRLVL_STROBE_NUM 0x0000027aU +#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ 0x0000027bU +#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR 0x0000027cU +#define _reg_PI_TODTL_2CMD_F0 0x0000027dU +#define _reg_PI_ODT_EN_F0 0x0000027eU +#define _reg_PI_TODTL_2CMD_F1 0x0000027fU +#define _reg_PI_ODT_EN_F1 0x00000280U +#define _reg_PI_TODTL_2CMD_F2 0x00000281U +#define _reg_PI_ODT_EN_F2 0x00000282U +#define _reg_PI_TODTH_WR 0x00000283U +#define _reg_PI_TODTH_RD 0x00000284U +#define _reg_PI_ODT_RD_MAP_CS0 0x00000285U +#define _reg_PI_ODT_WR_MAP_CS0 0x00000286U +#define _reg_PI_ODT_RD_MAP_CS1 0x00000287U +#define _reg_PI_ODT_WR_MAP_CS1 0x00000288U +#define _reg_PI_ODT_RD_MAP_CS2 0x00000289U +#define _reg_PI_ODT_WR_MAP_CS2 0x0000028aU +#define _reg_PI_ODT_RD_MAP_CS3 0x0000028bU +#define _reg_PI_ODT_WR_MAP_CS3 0x0000028cU +#define _reg_PI_EN_ODT_ASSERT_EXCEPT_RD 0x0000028dU +#define _reg_PI_ODTLON_F0 0x0000028eU +#define _reg_PI_TODTON_MIN_F0 0x0000028fU +#define _reg_PI_ODTLON_F1 0x00000290U +#define _reg_PI_TODTON_MIN_F1 0x00000291U +#define _reg_PI_ODTLON_F2 0x00000292U +#define _reg_PI_TODTON_MIN_F2 0x00000293U +#define _reg_PI_WR_TO_ODTH_F0 0x00000294U +#define _reg_PI_WR_TO_ODTH_F1 0x00000295U +#define _reg_PI_WR_TO_ODTH_F2 0x00000296U +#define _reg_PI_RD_TO_ODTH_F0 0x00000297U +#define _reg_PI_RD_TO_ODTH_F1 0x00000298U +#define _reg_PI_RD_TO_ODTH_F2 0x00000299U +#define _reg_PI_ADDRESS_MIRRORING 0x0000029aU +#define _reg_PI_RDLVL_REQ 0x0000029bU +#define _reg_PI_RDLVL_GATE_REQ 0x0000029cU +#define _reg_PI_RDLVL_CS 0x0000029dU +#define _reg_PI_RDLVL_PAT_0 0x0000029eU +#define _reg_PI_RDLVL_PAT_1 0x0000029fU +#define _reg_PI_RDLVL_PAT_2 0x000002a0U +#define _reg_PI_RDLVL_PAT_3 0x000002a1U +#define _reg_PI_RDLVL_PAT_4 0x000002a2U +#define _reg_PI_RDLVL_PAT_5 0x000002a3U +#define _reg_PI_RDLVL_PAT_6 0x000002a4U +#define _reg_PI_RDLVL_PAT_7 0x000002a5U +#define _reg_PI_RDLVL_SEQ_EN 0x000002a6U +#define _reg_PI_RDLVL_GATE_SEQ_EN 0x000002a7U +#define _reg_PI_RDLVL_PERIODIC 0x000002a8U +#define _reg_PI_RDLVL_ON_SREF_EXIT 0x000002a9U +#define _reg_PI_RDLVL_DISABLE_DFS 0x000002aaU +#define _reg_PI_RDLVL_GATE_PERIODIC 0x000002abU +#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT 0x000002acU +#define _reg_PI_RDLVL_GATE_DISABLE_DFS 0x000002adU +#define _reg_RESERVED_R1 0x000002aeU +#define _reg_PI_RDLVL_ROTATE 0x000002afU +#define _reg_PI_RDLVL_GATE_ROTATE 0x000002b0U +#define _reg_PI_RDLVL_CS_MAP 0x000002b1U +#define _reg_PI_RDLVL_GATE_CS_MAP 0x000002b2U +#define _reg_PI_TDFI_RDLVL_RR 0x000002b3U +#define _reg_PI_TDFI_RDLVL_RESP 0x000002b4U +#define _reg_PI_RDLVL_RESP_MASK 0x000002b5U +#define _reg_PI_TDFI_RDLVL_EN 0x000002b6U +#define _reg_PI_RDLVL_EN_F0 0x000002b7U +#define _reg_PI_RDLVL_GATE_EN_F0 0x000002b8U +#define _reg_PI_RDLVL_EN_F1 0x000002b9U +#define _reg_PI_RDLVL_GATE_EN_F1 0x000002baU +#define _reg_PI_RDLVL_EN_F2 0x000002bbU +#define _reg_PI_RDLVL_GATE_EN_F2 0x000002bcU +#define _reg_PI_RDLVL_EN 0x000002bdU +#define _reg_PI_RDLVL_GATE_EN 0x000002beU +#define _reg_PI_TDFI_RDLVL_MAX 0x000002bfU +#define _reg_PI_RDLVL_ERROR_STATUS 0x000002c0U +#define _reg_PI_RDLVL_INTERVAL 0x000002c1U +#define _reg_PI_RDLVL_GATE_INTERVAL 0x000002c2U +#define _reg_PI_RDLVL_PATTERN_START 0x000002c3U +#define _reg_PI_RDLVL_PATTERN_NUM 0x000002c4U +#define _reg_PI_RDLVL_STROBE_NUM 0x000002c5U +#define _reg_PI_RDLVL_GATE_STROBE_NUM 0x000002c6U +#define _reg_PI_LPDDR4_RDLVL_PATTERN_8 0x000002c7U +#define _reg_PI_LPDDR4_RDLVL_PATTERN_9 0x000002c8U +#define _reg_PI_LPDDR4_RDLVL_PATTERN_10 0x000002c9U +#define _reg_PI_LPDDR4_RDLVL_PATTERN_11 0x000002caU +#define _reg_PI_RD_PREAMBLE_TRAINING_EN 0x000002cbU +#define _reg_PI_REG_DIMM_ENABLE 0x000002ccU +#define _reg_PI_RDLAT_ADJ_F0 0x000002cdU +#define _reg_PI_RDLAT_ADJ_F1 0x000002ceU +#define _reg_PI_RDLAT_ADJ_F2 0x000002cfU +#define _reg_PI_TDFI_RDDATA_EN 0x000002d0U +#define _reg_PI_WRLAT_ADJ_F0 0x000002d1U +#define _reg_PI_WRLAT_ADJ_F1 0x000002d2U +#define _reg_PI_WRLAT_ADJ_F2 0x000002d3U +#define _reg_PI_TDFI_PHY_WRLAT 0x000002d4U +#define _reg_PI_TDFI_WRCSLAT_F0 0x000002d5U +#define _reg_PI_TDFI_WRCSLAT_F1 0x000002d6U +#define _reg_PI_TDFI_WRCSLAT_F2 0x000002d7U +#define _reg_PI_TDFI_RDCSLAT_F0 0x000002d8U +#define _reg_PI_TDFI_RDCSLAT_F1 0x000002d9U +#define _reg_PI_TDFI_RDCSLAT_F2 0x000002daU +#define _reg_PI_TDFI_PHY_WRDATA_F0 0x000002dbU +#define _reg_PI_TDFI_PHY_WRDATA_F1 0x000002dcU +#define _reg_PI_TDFI_PHY_WRDATA_F2 0x000002ddU +#define _reg_PI_TDFI_PHY_WRDATA 0x000002deU +#define _reg_PI_CALVL_REQ 0x000002dfU +#define _reg_PI_CALVL_CS 0x000002e0U +#define _reg_RESERVED_R2 0x000002e1U +#define _reg_RESERVED_R3 0x000002e2U +#define _reg_PI_CALVL_SEQ_EN 0x000002e3U +#define _reg_PI_CALVL_PERIODIC 0x000002e4U +#define _reg_PI_CALVL_ON_SREF_EXIT 0x000002e5U +#define _reg_PI_CALVL_DISABLE_DFS 0x000002e6U +#define _reg_PI_CALVL_ROTATE 0x000002e7U +#define _reg_PI_CALVL_CS_MAP 0x000002e8U +#define _reg_PI_TDFI_CALVL_EN 0x000002e9U +#define _reg_PI_TDFI_CALVL_CC_F0 0x000002eaU +#define _reg_PI_TDFI_CALVL_CAPTURE_F0 0x000002ebU +#define _reg_PI_TDFI_CALVL_CC_F1 0x000002ecU +#define _reg_PI_TDFI_CALVL_CAPTURE_F1 0x000002edU +#define _reg_PI_TDFI_CALVL_CC_F2 0x000002eeU +#define _reg_PI_TDFI_CALVL_CAPTURE_F2 0x000002efU +#define _reg_PI_TDFI_CALVL_RESP 0x000002f0U +#define _reg_PI_TDFI_CALVL_MAX 0x000002f1U +#define _reg_PI_CALVL_RESP_MASK 0x000002f2U +#define _reg_PI_CALVL_EN_F0 0x000002f3U +#define _reg_PI_CALVL_EN_F1 0x000002f4U +#define _reg_PI_CALVL_EN_F2 0x000002f5U +#define _reg_PI_CALVL_EN 0x000002f6U +#define _reg_PI_CALVL_ERROR_STATUS 0x000002f7U +#define _reg_PI_CALVL_INTERVAL 0x000002f8U +#define _reg_PI_TCACKEL 0x000002f9U +#define _reg_PI_TCAMRD 0x000002faU +#define _reg_PI_TCACKEH 0x000002fbU +#define _reg_PI_TMRZ_F0 0x000002fcU +#define _reg_PI_TCAENT_F0 0x000002fdU +#define _reg_PI_TMRZ_F1 0x000002feU +#define _reg_PI_TCAENT_F1 0x000002ffU +#define _reg_PI_TMRZ_F2 0x00000300U +#define _reg_PI_TCAENT_F2 0x00000301U +#define _reg_PI_TCAEXT 0x00000302U +#define _reg_PI_CA_TRAIN_VREF_EN 0x00000303U +#define _reg_PI_TDFI_CACSCA_F0 0x00000304U +#define _reg_PI_TDFI_CASEL_F0 0x00000305U +#define _reg_PI_TVREF_SHORT_F0 0x00000306U +#define _reg_PI_TVREF_LONG_F0 0x00000307U +#define _reg_PI_TDFI_CACSCA_F1 0x00000308U +#define _reg_PI_TDFI_CASEL_F1 0x00000309U +#define _reg_PI_TVREF_SHORT_F1 0x0000030aU +#define _reg_PI_TVREF_LONG_F1 0x0000030bU +#define _reg_PI_TDFI_CACSCA_F2 0x0000030cU +#define _reg_PI_TDFI_CASEL_F2 0x0000030dU +#define _reg_PI_TVREF_SHORT_F2 0x0000030eU +#define _reg_PI_TVREF_LONG_F2 0x0000030fU +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0 0x00000310U +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x00000311U +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1 0x00000312U +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x00000313U +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2 0x00000314U +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x00000315U +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT 0x00000316U +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT 0x00000317U +#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE 0x00000318U +#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE 0x00000319U +#define _reg_PI_CALVL_VREF_DELTA_F0 0x0000031aU +#define _reg_PI_CALVL_VREF_DELTA_F1 0x0000031bU +#define _reg_PI_CALVL_VREF_DELTA_F2 0x0000031cU +#define _reg_PI_CALVL_VREF_DELTA 0x0000031dU +#define _reg_PI_TDFI_INIT_START_MIN 0x0000031eU +#define _reg_PI_TDFI_INIT_COMPLETE_MIN 0x0000031fU +#define _reg_PI_TDFI_CALVL_STROBE_F0 0x00000320U +#define _reg_PI_TXP_F0 0x00000321U +#define _reg_PI_TMRWCKEL_F0 0x00000322U +#define _reg_PI_TCKELCK_F0 0x00000323U +#define _reg_PI_TDFI_CALVL_STROBE_F1 0x00000324U +#define _reg_PI_TXP_F1 0x00000325U +#define _reg_PI_TMRWCKEL_F1 0x00000326U +#define _reg_PI_TCKELCK_F1 0x00000327U +#define _reg_PI_TDFI_CALVL_STROBE_F2 0x00000328U +#define _reg_PI_TXP_F2 0x00000329U +#define _reg_PI_TMRWCKEL_F2 0x0000032aU +#define _reg_PI_TCKELCK_F2 0x0000032bU +#define _reg_PI_TCKCKEH 0x0000032cU +#define _reg_PI_CALVL_STROBE_NUM 0x0000032dU +#define _reg_PI_SW_CA_TRAIN_VREF 0x0000032eU +#define _reg_PI_TDFI_INIT_START_F0 0x0000032fU +#define _reg_PI_TDFI_INIT_COMPLETE_F0 0x00000330U +#define _reg_PI_TDFI_INIT_START_F1 0x00000331U +#define _reg_PI_TDFI_INIT_COMPLETE_F1 0x00000332U +#define _reg_PI_TDFI_INIT_START_F2 0x00000333U +#define _reg_PI_TDFI_INIT_COMPLETE_F2 0x00000334U +#define _reg_PI_CLKDISABLE_2_INIT_START 0x00000335U +#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE 0x00000336U +#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL 0x00000337U +#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE 0x00000338U +#define _reg_PI_TCKEHDQS_F0 0x00000339U +#define _reg_PI_TCKEHDQS_F1 0x0000033aU +#define _reg_PI_TCKEHDQS_F2 0x0000033bU +#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE 0x0000033cU +#define _reg_PI_WDQLVL_VREF_EN 0x0000033dU +#define _reg_PI_WDQLVL_BST_NUM 0x0000033eU +#define _reg_PI_TDFI_WDQLVL_WR_F0 0x0000033fU +#define _reg_PI_TDFI_WDQLVL_WR_F1 0x00000340U +#define _reg_PI_TDFI_WDQLVL_WR_F2 0x00000341U +#define _reg_PI_TDFI_WDQLVL_WR 0x00000342U +#define _reg_PI_TDFI_WDQLVL_RW 0x00000343U +#define _reg_PI_WDQLVL_RESP_MASK 0x00000344U +#define _reg_PI_WDQLVL_ROTATE 0x00000345U +#define _reg_PI_WDQLVL_CS_MAP 0x00000346U +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x00000347U +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x00000348U +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x00000349U +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x0000034aU +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x0000034bU +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x0000034cU +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT 0x0000034dU +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT 0x0000034eU +#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE 0x0000034fU +#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE 0x00000350U +#define _reg_PI_WDQLVL_VREF_DELTA_F0 0x00000351U +#define _reg_PI_WDQLVL_VREF_DELTA_F1 0x00000352U +#define _reg_PI_WDQLVL_VREF_DELTA_F2 0x00000353U +#define _reg_PI_WDQLVL_VREF_DELTA 0x00000354U +#define _reg_PI_WDQLVL_PERIODIC 0x00000355U +#define _reg_PI_WDQLVL_REQ 0x00000356U +#define _reg_PI_WDQLVL_CS 0x00000357U +#define _reg_PI_TDFI_WDQLVL_EN 0x00000358U +#define _reg_PI_TDFI_WDQLVL_RESP 0x00000359U +#define _reg_PI_TDFI_WDQLVL_MAX 0x0000035aU +#define _reg_PI_WDQLVL_INTERVAL 0x0000035bU +#define _reg_PI_WDQLVL_EN_F0 0x0000035cU +#define _reg_PI_WDQLVL_EN_F1 0x0000035dU +#define _reg_PI_WDQLVL_EN_F2 0x0000035eU +#define _reg_PI_WDQLVL_EN 0x0000035fU +#define _reg_PI_WDQLVL_ON_SREF_EXIT 0x00000360U +#define _reg_PI_WDQLVL_DISABLE_DFS 0x00000361U +#define _reg_PI_WDQLVL_ERROR_STATUS 0x00000362U +#define _reg_PI_MR1_DATA_F0_0 0x00000363U +#define _reg_PI_MR2_DATA_F0_0 0x00000364U +#define _reg_PI_MR3_DATA_F0_0 0x00000365U +#define _reg_PI_MR11_DATA_F0_0 0x00000366U +#define _reg_PI_MR12_DATA_F0_0 0x00000367U +#define _reg_PI_MR14_DATA_F0_0 0x00000368U +#define _reg_PI_MR22_DATA_F0_0 0x00000369U +#define _reg_PI_MR1_DATA_F1_0 0x0000036aU +#define _reg_PI_MR2_DATA_F1_0 0x0000036bU +#define _reg_PI_MR3_DATA_F1_0 0x0000036cU +#define _reg_PI_MR11_DATA_F1_0 0x0000036dU +#define _reg_PI_MR12_DATA_F1_0 0x0000036eU +#define _reg_PI_MR14_DATA_F1_0 0x0000036fU +#define _reg_PI_MR22_DATA_F1_0 0x00000370U +#define _reg_PI_MR1_DATA_F2_0 0x00000371U +#define _reg_PI_MR2_DATA_F2_0 0x00000372U +#define _reg_PI_MR3_DATA_F2_0 0x00000373U +#define _reg_PI_MR11_DATA_F2_0 0x00000374U +#define _reg_PI_MR12_DATA_F2_0 0x00000375U +#define _reg_PI_MR14_DATA_F2_0 0x00000376U +#define _reg_PI_MR22_DATA_F2_0 0x00000377U +#define _reg_PI_MR13_DATA_0 0x00000378U +#define _reg_PI_MR1_DATA_F0_1 0x00000379U +#define _reg_PI_MR2_DATA_F0_1 0x0000037aU +#define _reg_PI_MR3_DATA_F0_1 0x0000037bU +#define _reg_PI_MR11_DATA_F0_1 0x0000037cU +#define _reg_PI_MR12_DATA_F0_1 0x0000037dU +#define _reg_PI_MR14_DATA_F0_1 0x0000037eU +#define _reg_PI_MR22_DATA_F0_1 0x0000037fU +#define _reg_PI_MR1_DATA_F1_1 0x00000380U +#define _reg_PI_MR2_DATA_F1_1 0x00000381U +#define _reg_PI_MR3_DATA_F1_1 0x00000382U +#define _reg_PI_MR11_DATA_F1_1 0x00000383U +#define _reg_PI_MR12_DATA_F1_1 0x00000384U +#define _reg_PI_MR14_DATA_F1_1 0x00000385U +#define _reg_PI_MR22_DATA_F1_1 0x00000386U +#define _reg_PI_MR1_DATA_F2_1 0x00000387U +#define _reg_PI_MR2_DATA_F2_1 0x00000388U +#define _reg_PI_MR3_DATA_F2_1 0x00000389U +#define _reg_PI_MR11_DATA_F2_1 0x0000038aU +#define _reg_PI_MR12_DATA_F2_1 0x0000038bU +#define _reg_PI_MR14_DATA_F2_1 0x0000038cU +#define _reg_PI_MR22_DATA_F2_1 0x0000038dU +#define _reg_PI_MR13_DATA_1 0x0000038eU +#define _reg_PI_MR1_DATA_F0_2 0x0000038fU +#define _reg_PI_MR2_DATA_F0_2 0x00000390U +#define _reg_PI_MR3_DATA_F0_2 0x00000391U +#define _reg_PI_MR11_DATA_F0_2 0x00000392U +#define _reg_PI_MR12_DATA_F0_2 0x00000393U +#define _reg_PI_MR14_DATA_F0_2 0x00000394U +#define _reg_PI_MR22_DATA_F0_2 0x00000395U +#define _reg_PI_MR1_DATA_F1_2 0x00000396U +#define _reg_PI_MR2_DATA_F1_2 0x00000397U +#define _reg_PI_MR3_DATA_F1_2 0x00000398U +#define _reg_PI_MR11_DATA_F1_2 0x00000399U +#define _reg_PI_MR12_DATA_F1_2 0x0000039aU +#define _reg_PI_MR14_DATA_F1_2 0x0000039bU +#define _reg_PI_MR22_DATA_F1_2 0x0000039cU +#define _reg_PI_MR1_DATA_F2_2 0x0000039dU +#define _reg_PI_MR2_DATA_F2_2 0x0000039eU +#define _reg_PI_MR3_DATA_F2_2 0x0000039fU +#define _reg_PI_MR11_DATA_F2_2 0x000003a0U +#define _reg_PI_MR12_DATA_F2_2 0x000003a1U +#define _reg_PI_MR14_DATA_F2_2 0x000003a2U +#define _reg_PI_MR22_DATA_F2_2 0x000003a3U +#define _reg_PI_MR13_DATA_2 0x000003a4U +#define _reg_PI_MR1_DATA_F0_3 0x000003a5U +#define _reg_PI_MR2_DATA_F0_3 0x000003a6U +#define _reg_PI_MR3_DATA_F0_3 0x000003a7U +#define _reg_PI_MR11_DATA_F0_3 0x000003a8U +#define _reg_PI_MR12_DATA_F0_3 0x000003a9U +#define _reg_PI_MR14_DATA_F0_3 0x000003aaU +#define _reg_PI_MR22_DATA_F0_3 0x000003abU +#define _reg_PI_MR1_DATA_F1_3 0x000003acU +#define _reg_PI_MR2_DATA_F1_3 0x000003adU +#define _reg_PI_MR3_DATA_F1_3 0x000003aeU +#define _reg_PI_MR11_DATA_F1_3 0x000003afU +#define _reg_PI_MR12_DATA_F1_3 0x000003b0U +#define _reg_PI_MR14_DATA_F1_3 0x000003b1U +#define _reg_PI_MR22_DATA_F1_3 0x000003b2U +#define _reg_PI_MR1_DATA_F2_3 0x000003b3U +#define _reg_PI_MR2_DATA_F2_3 0x000003b4U +#define _reg_PI_MR3_DATA_F2_3 0x000003b5U +#define _reg_PI_MR11_DATA_F2_3 0x000003b6U +#define _reg_PI_MR12_DATA_F2_3 0x000003b7U +#define _reg_PI_MR14_DATA_F2_3 0x000003b8U +#define _reg_PI_MR22_DATA_F2_3 0x000003b9U +#define _reg_PI_MR13_DATA_3 0x000003baU +#define _reg_PI_BANK_DIFF 0x000003bbU +#define _reg_PI_ROW_DIFF 0x000003bcU +#define _reg_PI_TFC_F0 0x000003bdU +#define _reg_PI_TFC_F1 0x000003beU +#define _reg_PI_TFC_F2 0x000003bfU +#define _reg_PI_TCCD 0x000003c0U +#define _reg_PI_TRTP_F0 0x000003c1U +#define _reg_PI_TRP_F0 0x000003c2U +#define _reg_PI_TRCD_F0 0x000003c3U +#define _reg_PI_TWTR_F0 0x000003c4U +#define _reg_PI_TWR_F0 0x000003c5U +#define _reg_PI_TRAS_MAX_F0 0x000003c6U +#define _reg_PI_TRAS_MIN_F0 0x000003c7U +#define _reg_PI_TDQSCK_MAX_F0 0x000003c8U +#define _reg_PI_TCCDMW_F0 0x000003c9U +#define _reg_PI_TSR_F0 0x000003caU +#define _reg_PI_TMRD_F0 0x000003cbU +#define _reg_PI_TMRW_F0 0x000003ccU +#define _reg_PI_TMOD_F0 0x000003cdU +#define _reg_PI_TRTP_F1 0x000003ceU +#define _reg_PI_TRP_F1 0x000003cfU +#define _reg_PI_TRCD_F1 0x000003d0U +#define _reg_PI_TWTR_F1 0x000003d1U +#define _reg_PI_TWR_F1 0x000003d2U +#define _reg_PI_TRAS_MAX_F1 0x000003d3U +#define _reg_PI_TRAS_MIN_F1 0x000003d4U +#define _reg_PI_TDQSCK_MAX_F1 0x000003d5U +#define _reg_PI_TCCDMW_F1 0x000003d6U +#define _reg_PI_TSR_F1 0x000003d7U +#define _reg_PI_TMRD_F1 0x000003d8U +#define _reg_PI_TMRW_F1 0x000003d9U +#define _reg_PI_TMOD_F1 0x000003daU +#define _reg_PI_TRTP_F2 0x000003dbU +#define _reg_PI_TRP_F2 0x000003dcU +#define _reg_PI_TRCD_F2 0x000003ddU +#define _reg_PI_TWTR_F2 0x000003deU +#define _reg_PI_TWR_F2 0x000003dfU +#define _reg_PI_TRAS_MAX_F2 0x000003e0U +#define _reg_PI_TRAS_MIN_F2 0x000003e1U +#define _reg_PI_TDQSCK_MAX_F2 0x000003e2U +#define _reg_PI_TCCDMW_F2 0x000003e3U +#define _reg_PI_TSR_F2 0x000003e4U +#define _reg_PI_TMRD_F2 0x000003e5U +#define _reg_PI_TMRW_F2 0x000003e6U +#define _reg_PI_TMOD_F2 0x000003e7U +#define _reg_RESERVED_R4 0x000003e8U +#define _reg_RESERVED_R5 0x000003e9U +#define _reg_RESERVED_R6 0x000003eaU +#define _reg_RESERVED_R7 0x000003ebU +#define _reg_RESERVED_R8 0x000003ecU +#define _reg_RESERVED_R9 0x000003edU +#define _reg_RESERVED_R10 0x000003eeU +#define _reg_RESERVED_R11 0x000003efU +#define _reg_RESERVED_R12 0x000003f0U +#define _reg_RESERVED_R13 0x000003f1U +#define _reg_RESERVED_R14 0x000003f2U +#define _reg_RESERVED_R15 0x000003f3U +#define _reg_RESERVED_R16 0x000003f4U +#define _reg_RESERVED_R17 0x000003f5U +#define _reg_RESERVED_R18 0x000003f6U +#define _reg_RESERVED_R19 0x000003f7U +#define _reg_RESERVED_R20 0x000003f8U +#define _reg_RESERVED_R21 0x000003f9U +#define _reg_RESERVED_R22 0x000003faU +#define _reg_RESERVED_R23 0x000003fbU +#define _reg_PI_INT_STATUS 0x000003fcU +#define _reg_PI_INT_ACK 0x000003fdU +#define _reg_PI_INT_MASK 0x000003feU +#define _reg_PI_BIST_EXP_DATA_P0 0x000003ffU +#define _reg_PI_BIST_EXP_DATA_P1 0x00000400U +#define _reg_PI_BIST_EXP_DATA_P2 0x00000401U +#define _reg_PI_BIST_EXP_DATA_P3 0x00000402U +#define _reg_PI_BIST_FAIL_DATA_P0 0x00000403U +#define _reg_PI_BIST_FAIL_DATA_P1 0x00000404U +#define _reg_PI_BIST_FAIL_DATA_P2 0x00000405U +#define _reg_PI_BIST_FAIL_DATA_P3 0x00000406U +#define _reg_PI_BIST_FAIL_ADDR_P0 0x00000407U +#define _reg_PI_BIST_FAIL_ADDR_P1 0x00000408U +#define _reg_PI_BSTLEN 0x00000409U +#define _reg_PI_LONG_COUNT_MASK 0x0000040aU +#define _reg_PI_CMD_SWAP_EN 0x0000040bU +#define _reg_PI_CKE_MUX_0 0x0000040cU +#define _reg_PI_CKE_MUX_1 0x0000040dU +#define _reg_PI_CKE_MUX_2 0x0000040eU +#define _reg_PI_CKE_MUX_3 0x0000040fU +#define _reg_PI_CS_MUX_0 0x00000410U +#define _reg_PI_CS_MUX_1 0x00000411U +#define _reg_PI_CS_MUX_2 0x00000412U +#define _reg_PI_CS_MUX_3 0x00000413U +#define _reg_PI_RAS_N_MUX 0x00000414U +#define _reg_PI_CAS_N_MUX 0x00000415U +#define _reg_PI_WE_N_MUX 0x00000416U +#define _reg_PI_BANK_MUX_0 0x00000417U +#define _reg_PI_BANK_MUX_1 0x00000418U +#define _reg_PI_BANK_MUX_2 0x00000419U +#define _reg_PI_ODT_MUX_0 0x0000041aU +#define _reg_PI_ODT_MUX_1 0x0000041bU +#define _reg_PI_ODT_MUX_2 0x0000041cU +#define _reg_PI_ODT_MUX_3 0x0000041dU +#define _reg_PI_RESET_N_MUX_0 0x0000041eU +#define _reg_PI_RESET_N_MUX_1 0x0000041fU +#define _reg_PI_RESET_N_MUX_2 0x00000420U +#define _reg_PI_RESET_N_MUX_3 0x00000421U +#define _reg_PI_DATA_BYTE_SWAP_EN 0x00000422U +#define _reg_PI_DATA_BYTE_SWAP_SLICE0 0x00000423U +#define _reg_PI_DATA_BYTE_SWAP_SLICE1 0x00000424U +#define _reg_PI_DATA_BYTE_SWAP_SLICE2 0x00000425U +#define _reg_PI_DATA_BYTE_SWAP_SLICE3 0x00000426U +#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN 0x00000427U +#define _reg_PI_TDFI_CTRLUPD_MIN 0x00000428U +#define _reg_PI_TDFI_CTRLUPD_MAX_F0 0x00000429U +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0 0x0000042aU +#define _reg_PI_TDFI_CTRLUPD_MAX_F1 0x0000042bU +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1 0x0000042cU +#define _reg_PI_TDFI_CTRLUPD_MAX_F2 0x0000042dU +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2 0x0000042eU +#define _reg_PI_UPDATE_ERROR_STATUS 0x0000042fU +#define _reg_PI_BIST_GO 0x00000430U +#define _reg_PI_BIST_RESULT 0x00000431U +#define _reg_PI_ADDR_SPACE 0x00000432U +#define _reg_PI_BIST_DATA_CHECK 0x00000433U +#define _reg_PI_BIST_ADDR_CHECK 0x00000434U +#define _reg_PI_BIST_START_ADDRESS_P0 0x00000435U +#define _reg_PI_BIST_START_ADDRESS_P1 0x00000436U +#define _reg_PI_BIST_DATA_MASK_P0 0x00000437U +#define _reg_PI_BIST_DATA_MASK_P1 0x00000438U +#define _reg_PI_BIST_ERR_COUNT 0x00000439U +#define _reg_PI_BIST_ERR_STOP 0x0000043aU +#define _reg_PI_BIST_ADDR_MASK_0_P0 0x0000043bU +#define _reg_PI_BIST_ADDR_MASK_0_P1 0x0000043cU +#define _reg_PI_BIST_ADDR_MASK_1_P0 0x0000043dU +#define _reg_PI_BIST_ADDR_MASK_1_P1 0x0000043eU +#define _reg_PI_BIST_ADDR_MASK_2_P0 0x0000043fU +#define _reg_PI_BIST_ADDR_MASK_2_P1 0x00000440U +#define _reg_PI_BIST_ADDR_MASK_3_P0 0x00000441U +#define _reg_PI_BIST_ADDR_MASK_3_P1 0x00000442U +#define _reg_PI_BIST_ADDR_MASK_4_P0 0x00000443U +#define _reg_PI_BIST_ADDR_MASK_4_P1 0x00000444U +#define _reg_PI_BIST_ADDR_MASK_5_P0 0x00000445U +#define _reg_PI_BIST_ADDR_MASK_5_P1 0x00000446U +#define _reg_PI_BIST_ADDR_MASK_6_P0 0x00000447U +#define _reg_PI_BIST_ADDR_MASK_6_P1 0x00000448U +#define _reg_PI_BIST_ADDR_MASK_7_P0 0x00000449U +#define _reg_PI_BIST_ADDR_MASK_7_P1 0x0000044aU +#define _reg_PI_BIST_ADDR_MASK_8_P0 0x0000044bU +#define _reg_PI_BIST_ADDR_MASK_8_P1 0x0000044cU +#define _reg_PI_BIST_ADDR_MASK_9_P0 0x0000044dU +#define _reg_PI_BIST_ADDR_MASK_9_P1 0x0000044eU +#define _reg_PI_BIST_MODE 0x0000044fU +#define _reg_PI_BIST_ADDR_MODE 0x00000450U +#define _reg_PI_BIST_PAT_MODE 0x00000451U +#define _reg_PI_BIST_USER_PAT_P0 0x00000452U +#define _reg_PI_BIST_USER_PAT_P1 0x00000453U +#define _reg_PI_BIST_USER_PAT_P2 0x00000454U +#define _reg_PI_BIST_USER_PAT_P3 0x00000455U +#define _reg_PI_BIST_PAT_NUM 0x00000456U +#define _reg_PI_BIST_STAGE_0 0x00000457U +#define _reg_PI_BIST_STAGE_1 0x00000458U +#define _reg_PI_BIST_STAGE_2 0x00000459U +#define _reg_PI_BIST_STAGE_3 0x0000045aU +#define _reg_PI_BIST_STAGE_4 0x0000045bU +#define _reg_PI_BIST_STAGE_5 0x0000045cU +#define _reg_PI_BIST_STAGE_6 0x0000045dU +#define _reg_PI_BIST_STAGE_7 0x0000045eU +#define _reg_PI_COL_DIFF 0x0000045fU +#define _reg_PI_SELF_REFRESH_EN 0x00000460U +#define _reg_PI_TXSR_F0 0x00000461U +#define _reg_PI_TXSR_F1 0x00000462U +#define _reg_PI_TXSR_F2 0x00000463U +#define _reg_PI_MONITOR_SRC_SEL_0 0x00000464U +#define _reg_PI_MONITOR_CAP_SEL_0 0x00000465U +#define _reg_PI_MONITOR_0 0x00000466U +#define _reg_PI_MONITOR_SRC_SEL_1 0x00000467U +#define _reg_PI_MONITOR_CAP_SEL_1 0x00000468U +#define _reg_PI_MONITOR_1 0x00000469U +#define _reg_PI_MONITOR_SRC_SEL_2 0x0000046aU +#define _reg_PI_MONITOR_CAP_SEL_2 0x0000046bU +#define _reg_PI_MONITOR_2 0x0000046cU +#define _reg_PI_MONITOR_SRC_SEL_3 0x0000046dU +#define _reg_PI_MONITOR_CAP_SEL_3 0x0000046eU +#define _reg_PI_MONITOR_3 0x0000046fU +#define _reg_PI_MONITOR_SRC_SEL_4 0x00000470U +#define _reg_PI_MONITOR_CAP_SEL_4 0x00000471U +#define _reg_PI_MONITOR_4 0x00000472U +#define _reg_PI_MONITOR_SRC_SEL_5 0x00000473U +#define _reg_PI_MONITOR_CAP_SEL_5 0x00000474U +#define _reg_PI_MONITOR_5 0x00000475U +#define _reg_PI_MONITOR_SRC_SEL_6 0x00000476U +#define _reg_PI_MONITOR_CAP_SEL_6 0x00000477U +#define _reg_PI_MONITOR_6 0x00000478U +#define _reg_PI_MONITOR_SRC_SEL_7 0x00000479U +#define _reg_PI_MONITOR_CAP_SEL_7 0x0000047aU +#define _reg_PI_MONITOR_7 0x0000047bU +#define _reg_PI_MONITOR_STROBE 0x0000047cU +#define _reg_PI_DLL_LOCK 0x0000047dU +#define _reg_PI_FREQ_NUMBER_STATUS 0x0000047eU +#define _reg_RESERVED_R24 0x0000047fU +#define _reg_PI_PHYMSTR_TYPE 0x00000480U +#define _reg_PI_POWER_REDUC_EN 0x00000481U +#define _reg_RESERVED_R25 0x00000482U +#define _reg_RESERVED_R26 0x00000483U +#define _reg_RESERVED_R27 0x00000484U +#define _reg_RESERVED_R28 0x00000485U +#define _reg_RESERVED_R29 0x00000486U +#define _reg_RESERVED_R30 0x00000487U +#define _reg_RESERVED_R31 0x00000488U +#define _reg_RESERVED_R32 0x00000489U +#define _reg_RESERVED_R33 0x0000048aU +#define _reg_RESERVED_R34 0x0000048bU +#define _reg_RESERVED_R35 0x0000048cU +#define _reg_RESERVED_R36 0x0000048dU +#define _reg_RESERVED_R37 0x0000048eU +#define _reg_RESERVED_R38 0x0000048fU +#define _reg_RESERVED_R39 0x00000490U +#define _reg_PI_WRLVL_MAX_STROBE_PEND 0x00000491U +#define _reg_PI_TSDO_F0 0x00000492U +#define _reg_PI_TSDO_F1 0x00000493U +#define _reg_PI_TSDO_F2 0x00000494U + +#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffff) +#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xff) +#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xff) + +static const uint32_t DDR_REGDEF_TBL[4][1173] = { + { +/*0000*/ 0xffffffffU, +/*0001*/ 0xffffffffU, +/*0002*/ 0x000b0400U, +/*0003*/ 0xffffffffU, +/*0004*/ 0xffffffffU, +/*0005*/ 0x10010400U, +/*0006*/ 0x18050400U, +/*0007*/ 0x00050401U, +/*0008*/ 0x08050401U, +/*0009*/ 0x10050401U, +/*000a*/ 0x18050401U, +/*000b*/ 0x00050402U, +/*000c*/ 0x08050402U, +/*000d*/ 0x10050402U, +/*000e*/ 0x18050402U, +/*000f*/ 0x00040403U, +/*0010*/ 0x08030403U, +/*0011*/ 0x00180404U, +/*0012*/ 0x18030404U, +/*0013*/ 0x00180405U, +/*0014*/ 0x18020405U, +/*0015*/ 0x00010406U, +/*0016*/ 0x08020406U, +/*0017*/ 0x10010406U, +/*0018*/ 0x18010406U, +/*0019*/ 0x00020407U, +/*001a*/ 0x08040407U, +/*001b*/ 0x10040407U, +/*001c*/ 0x18040407U, +/*001d*/ 0x000a0408U, +/*001e*/ 0x10040408U, +/*001f*/ 0xffffffffU, +/*0020*/ 0xffffffffU, +/*0021*/ 0x18070408U, +/*0022*/ 0xffffffffU, +/*0023*/ 0xffffffffU, +/*0024*/ 0xffffffffU, +/*0025*/ 0xffffffffU, +/*0026*/ 0xffffffffU, +/*0027*/ 0xffffffffU, +/*0028*/ 0x000a0409U, +/*0029*/ 0x10040409U, +/*002a*/ 0x18010409U, +/*002b*/ 0x0001040aU, +/*002c*/ 0x0802040aU, +/*002d*/ 0x1009040aU, +/*002e*/ 0x0009040bU, +/*002f*/ 0x1002040bU, +/*0030*/ 0x0020040cU, +/*0031*/ 0xffffffffU, +/*0032*/ 0x0001040dU, +/*0033*/ 0xffffffffU, +/*0034*/ 0xffffffffU, +/*0035*/ 0xffffffffU, +/*0036*/ 0xffffffffU, +/*0037*/ 0x0020040eU, +/*0038*/ 0x0020040fU, +/*0039*/ 0x00200410U, +/*003a*/ 0x00200411U, +/*003b*/ 0x00030412U, +/*003c*/ 0x08010412U, +/*003d*/ 0x10030412U, +/*003e*/ 0x18030412U, +/*003f*/ 0x00040413U, +/*0040*/ 0x08040413U, +/*0041*/ 0x10040413U, +/*0042*/ 0x18040413U, +/*0043*/ 0x00010414U, +/*0044*/ 0x08010414U, +/*0045*/ 0x10060414U, +/*0046*/ 0x18040414U, +/*0047*/ 0xffffffffU, +/*0048*/ 0x00060415U, +/*0049*/ 0x08040415U, +/*004a*/ 0x10060415U, +/*004b*/ 0x18040415U, +/*004c*/ 0x00020416U, +/*004d*/ 0x08050416U, +/*004e*/ 0x10080416U, +/*004f*/ 0x00200417U, +/*0050*/ 0x00060418U, +/*0051*/ 0x08030418U, +/*0052*/ 0x100b0418U, +/*0053*/ 0x00040419U, +/*0054*/ 0x08040419U, +/*0055*/ 0x10040419U, +/*0056*/ 0xffffffffU, +/*0057*/ 0x18010419U, +/*0058*/ 0x0009041aU, +/*0059*/ 0x0020041bU, +/*005a*/ 0x0020041cU, +/*005b*/ 0x0020041dU, +/*005c*/ 0x0020041eU, +/*005d*/ 0x0010041fU, +/*005e*/ 0x00200420U, +/*005f*/ 0x00010421U, +/*0060*/ 0x08060421U, +/*0061*/ 0x10080421U, +/*0062*/ 0x00200422U, +/*0063*/ 0xffffffffU, +/*0064*/ 0x000a0423U, +/*0065*/ 0x10060423U, +/*0066*/ 0x18070423U, +/*0067*/ 0x00080424U, +/*0068*/ 0x08080424U, +/*0069*/ 0x100a0424U, +/*006a*/ 0x00070425U, +/*006b*/ 0x08080425U, +/*006c*/ 0x10080425U, +/*006d*/ 0x18030425U, +/*006e*/ 0x000a0426U, +/*006f*/ 0x100a0426U, +/*0070*/ 0x00110427U, +/*0071*/ 0x00090428U, +/*0072*/ 0x10090428U, +/*0073*/ 0x00100429U, +/*0074*/ 0x100e0429U, +/*0075*/ 0x000e042aU, +/*0076*/ 0x100c042aU, +/*0077*/ 0x000a042bU, +/*0078*/ 0x100a042bU, +/*0079*/ 0x0002042cU, +/*007a*/ 0x0020042dU, +/*007b*/ 0x000b042eU, +/*007c*/ 0x100b042eU, +/*007d*/ 0x0020042fU, +/*007e*/ 0x00120430U, +/*007f*/ 0x00200431U, +/*0080*/ 0x00200432U, +/*0081*/ 0xffffffffU, +/*0082*/ 0xffffffffU, +/*0083*/ 0x00010433U, +/*0084*/ 0x08010433U, +/*0085*/ 0x10080433U, +/*0086*/ 0x000c0434U, +/*0087*/ 0x100c0434U, +/*0088*/ 0x000c0435U, +/*0089*/ 0x100c0435U, +/*008a*/ 0x000c0436U, +/*008b*/ 0x100c0436U, +/*008c*/ 0x000c0437U, +/*008d*/ 0x100c0437U, +/*008e*/ 0x000c0438U, +/*008f*/ 0x100c0438U, +/*0090*/ 0x000c0439U, +/*0091*/ 0x100b0439U, +/*0092*/ 0xffffffffU, +/*0093*/ 0xffffffffU, +/*0094*/ 0x000b043aU, +/*0095*/ 0x100b043aU, +/*0096*/ 0x000b043bU, +/*0097*/ 0x100b043bU, +/*0098*/ 0x000b043cU, +/*0099*/ 0x100b043cU, +/*009a*/ 0x000b043dU, +/*009b*/ 0x100b043dU, +/*009c*/ 0x000b043eU, +/*009d*/ 0x100a043eU, +/*009e*/ 0xffffffffU, +/*009f*/ 0x000a043fU, +/*00a0*/ 0x100a043fU, +/*00a1*/ 0x000a0440U, +/*00a2*/ 0x100a0440U, +/*00a3*/ 0x000a0441U, +/*00a4*/ 0x100a0441U, +/*00a5*/ 0x000a0442U, +/*00a6*/ 0x100a0442U, +/*00a7*/ 0xffffffffU, +/*00a8*/ 0x000a0443U, +/*00a9*/ 0x100a0443U, +/*00aa*/ 0x000a0444U, +/*00ab*/ 0x100a0444U, +/*00ac*/ 0x000a0445U, +/*00ad*/ 0x100a0445U, +/*00ae*/ 0x000a0446U, +/*00af*/ 0x100a0446U, +/*00b0*/ 0x000a0447U, +/*00b1*/ 0x100a0447U, +/*00b2*/ 0x000a0448U, +/*00b3*/ 0x100a0448U, +/*00b4*/ 0x000a0449U, +/*00b5*/ 0x100a0449U, +/*00b6*/ 0x000a044aU, +/*00b7*/ 0x100a044aU, +/*00b8*/ 0x000a044bU, +/*00b9*/ 0x100a044bU, +/*00ba*/ 0x000a044cU, +/*00bb*/ 0x1004044cU, +/*00bc*/ 0x1803044cU, +/*00bd*/ 0x000a044dU, +/*00be*/ 0x100a044dU, +/*00bf*/ 0x0001044eU, +/*00c0*/ 0x080a044eU, +/*00c1*/ 0x1804044eU, +/*00c2*/ 0x000b044fU, +/*00c3*/ 0x100a044fU, +/*00c4*/ 0xffffffffU, +/*00c5*/ 0x00080450U, +/*00c6*/ 0x08080450U, +/*00c7*/ 0x10080450U, +/*00c8*/ 0x18080450U, +/*00c9*/ 0x00080451U, +/*00ca*/ 0xffffffffU, +/*00cb*/ 0x08080451U, +/*00cc*/ 0x10010451U, +/*00cd*/ 0x18080451U, +/*00ce*/ 0x00080452U, +/*00cf*/ 0x08020452U, +/*00d0*/ 0x10020452U, +/*00d1*/ 0x18040452U, +/*00d2*/ 0x00040453U, +/*00d3*/ 0xffffffffU, +/*00d4*/ 0x08040453U, +/*00d5*/ 0x100a0453U, +/*00d6*/ 0x00060454U, +/*00d7*/ 0x08080454U, +/*00d8*/ 0xffffffffU, +/*00d9*/ 0x10040454U, +/*00da*/ 0x18040454U, +/*00db*/ 0x00050455U, +/*00dc*/ 0x08040455U, +/*00dd*/ 0x10050455U, +/*00de*/ 0x000a0456U, +/*00df*/ 0x100a0456U, +/*00e0*/ 0x00080457U, +/*00e1*/ 0xffffffffU, +/*00e2*/ 0x08040457U, +/*00e3*/ 0xffffffffU, +/*00e4*/ 0xffffffffU, +/*00e5*/ 0x00050600U, +/*00e6*/ 0x08050600U, +/*00e7*/ 0x10050600U, +/*00e8*/ 0x18050600U, +/*00e9*/ 0x00050601U, +/*00ea*/ 0x08050601U, +/*00eb*/ 0x100b0601U, +/*00ec*/ 0x00010602U, +/*00ed*/ 0x08030602U, +/*00ee*/ 0x00200603U, +/*00ef*/ 0xffffffffU, +/*00f0*/ 0x00030604U, +/*00f1*/ 0x080a0604U, +/*00f2*/ 0xffffffffU, +/*00f3*/ 0xffffffffU, +/*00f4*/ 0x18030604U, +/*00f5*/ 0x00030605U, +/*00f6*/ 0x08010605U, +/*00f7*/ 0x10010605U, +/*00f8*/ 0x18060605U, +/*00f9*/ 0xffffffffU, +/*00fa*/ 0xffffffffU, +/*00fb*/ 0xffffffffU, +/*00fc*/ 0x00020606U, +/*00fd*/ 0x08030606U, +/*00fe*/ 0x10010606U, +/*00ff*/ 0x000f0607U, +/*0100*/ 0x00200608U, +/*0101*/ 0x00200609U, +/*0102*/ 0x000b060aU, +/*0103*/ 0x100b060aU, +/*0104*/ 0x000b060bU, +/*0105*/ 0xffffffffU, +/*0106*/ 0xffffffffU, +/*0107*/ 0x0018060cU, +/*0108*/ 0x0018060dU, +/*0109*/ 0x0018060eU, +/*010a*/ 0x0018060fU, +/*010b*/ 0x1804060fU, +/*010c*/ 0x00050610U, +/*010d*/ 0x08020610U, +/*010e*/ 0x10040610U, +/*010f*/ 0x18040610U, +/*0110*/ 0x00010611U, +/*0111*/ 0x08010611U, +/*0112*/ 0x10010611U, +/*0113*/ 0x18030611U, +/*0114*/ 0x00200612U, +/*0115*/ 0x00200613U, +/*0116*/ 0x00010614U, +/*0117*/ 0x08140614U, +/*0118*/ 0x00140615U, +/*0119*/ 0x00140616U, +/*011a*/ 0x00140617U, +/*011b*/ 0x00140618U, +/*011c*/ 0x00140619U, +/*011d*/ 0x0014061aU, +/*011e*/ 0x0014061bU, +/*011f*/ 0x0018061cU, +/*0120*/ 0x000a061dU, +/*0121*/ 0x1006061dU, +/*0122*/ 0x1806061dU, +/*0123*/ 0x0006061eU, +/*0124*/ 0xffffffffU, +/*0125*/ 0xffffffffU, +/*0126*/ 0x0008061fU, +/*0127*/ 0x080b061fU, +/*0128*/ 0x000b0620U, +/*0129*/ 0x100b0620U, +/*012a*/ 0x000b0621U, +/*012b*/ 0x100b0621U, +/*012c*/ 0x000b0622U, +/*012d*/ 0x10040622U, +/*012e*/ 0x000a0623U, +/*012f*/ 0x10060623U, +/*0130*/ 0x18080623U, +/*0131*/ 0xffffffffU, +/*0132*/ 0x00040624U, +/*0133*/ 0xffffffffU, +/*0134*/ 0xffffffffU, +/*0135*/ 0x00010700U, +/*0136*/ 0x08020700U, +/*0137*/ 0x10050700U, +/*0138*/ 0x18050700U, +/*0139*/ 0x00050701U, +/*013a*/ 0x08050701U, +/*013b*/ 0x100b0701U, +/*013c*/ 0x00050702U, +/*013d*/ 0x08010702U, +/*013e*/ 0x10010702U, +/*013f*/ 0xffffffffU, +/*0140*/ 0x18010702U, +/*0141*/ 0x00010703U, +/*0142*/ 0x08040703U, +/*0143*/ 0x100b0703U, +/*0144*/ 0x000b0704U, +/*0145*/ 0xffffffffU, +/*0146*/ 0x10040704U, +/*0147*/ 0x000b0705U, +/*0148*/ 0x10040705U, +/*0149*/ 0x18010705U, +/*014a*/ 0x00010706U, +/*014b*/ 0x08010706U, +/*014c*/ 0x00200707U, +/*014d*/ 0x00200708U, +/*014e*/ 0x00080709U, +/*014f*/ 0x080a0709U, +/*0150*/ 0x18050709U, +/*0151*/ 0x000a070aU, +/*0152*/ 0x1003070aU, +/*0153*/ 0x1803070aU, +/*0154*/ 0x0001070bU, +/*0155*/ 0x0802070bU, +/*0156*/ 0x1001070bU, +/*0157*/ 0x1801070bU, +/*0158*/ 0x0001070cU, +/*0159*/ 0x0802070cU, +/*015a*/ 0xffffffffU, +/*015b*/ 0xffffffffU, +/*015c*/ 0xffffffffU, +/*015d*/ 0xffffffffU, +/*015e*/ 0xffffffffU, +/*015f*/ 0xffffffffU, +/*0160*/ 0xffffffffU, +/*0161*/ 0xffffffffU, +/*0162*/ 0xffffffffU, +/*0163*/ 0xffffffffU, +/*0164*/ 0xffffffffU, +/*0165*/ 0xffffffffU, +/*0166*/ 0x1001070cU, +/*0167*/ 0x1801070cU, +/*0168*/ 0x000d070dU, +/*0169*/ 0xffffffffU, +/*016a*/ 0xffffffffU, +/*016b*/ 0x0005070eU, +/*016c*/ 0x0001070fU, +/*016d*/ 0x080e070fU, +/*016e*/ 0x000e0710U, +/*016f*/ 0x100e0710U, +/*0170*/ 0x000e0711U, +/*0171*/ 0x100e0711U, +/*0172*/ 0x00040712U, +/*0173*/ 0xffffffffU, +/*0174*/ 0xffffffffU, +/*0175*/ 0xffffffffU, +/*0176*/ 0xffffffffU, +/*0177*/ 0x080b0712U, +/*0178*/ 0x000b0713U, +/*0179*/ 0x100b0713U, +/*017a*/ 0x000b0714U, +/*017b*/ 0xffffffffU, +/*017c*/ 0xffffffffU, +/*017d*/ 0xffffffffU, +/*017e*/ 0xffffffffU, +/*017f*/ 0x000d0715U, +/*0180*/ 0xffffffffU, +/*0181*/ 0xffffffffU, +/*0182*/ 0x10100715U, +/*0183*/ 0x00080716U, +/*0184*/ 0xffffffffU, +/*0185*/ 0x08100716U, +/*0186*/ 0x00100717U, +/*0187*/ 0x10100717U, +/*0188*/ 0x00100718U, +/*0189*/ 0x10100718U, +/*018a*/ 0x00030719U, +/*018b*/ 0x08040719U, +/*018c*/ 0x10010719U, +/*018d*/ 0x18040719U, +/*018e*/ 0xffffffffU, +/*018f*/ 0xffffffffU, +/*0190*/ 0x0001071aU, +/*0191*/ 0x0812071aU, +/*0192*/ 0x000a071bU, +/*0193*/ 0x100c071bU, +/*0194*/ 0x0012071cU, +/*0195*/ 0x0014071dU, +/*0196*/ 0x0012071eU, +/*0197*/ 0x0011071fU, +/*0198*/ 0x00110720U, +/*0199*/ 0x00120721U, +/*019a*/ 0x00120722U, +/*019b*/ 0x00120723U, +/*019c*/ 0x00120724U, +/*019d*/ 0x00120725U, +/*019e*/ 0x00120726U, +/*019f*/ 0x00120727U, +/*01a0*/ 0x00120728U, +/*01a1*/ 0xffffffffU, +/*01a2*/ 0xffffffffU, +/*01a3*/ 0x00190729U, +/*01a4*/ 0x0019072aU, +/*01a5*/ 0x0020072bU, +/*01a6*/ 0x0017072cU, +/*01a7*/ 0x1808072cU, +/*01a8*/ 0x0001072dU, +/*01a9*/ 0x0801072dU, +/*01aa*/ 0x0020072eU, +/*01ab*/ 0x0008072fU, +/*01ac*/ 0xffffffffU, +/*01ad*/ 0x0803072fU, +/*01ae*/ 0x00180730U, +/*01af*/ 0x00180731U, +/*01b0*/ 0xffffffffU, +/*01b1*/ 0xffffffffU, +/*01b2*/ 0xffffffffU, +/*01b3*/ 0xffffffffU, +/*01b4*/ 0xffffffffU, +/*01b5*/ 0xffffffffU, +/*01b6*/ 0xffffffffU, +/*01b7*/ 0xffffffffU, +/*01b8*/ 0xffffffffU, +/*01b9*/ 0xffffffffU, +/*01ba*/ 0xffffffffU, +/*01bb*/ 0xffffffffU, +/*01bc*/ 0xffffffffU, +/*01bd*/ 0xffffffffU, +/*01be*/ 0xffffffffU, +/*01bf*/ 0x00100732U, +/*01c0*/ 0x10010732U, +/*01c1*/ 0x18010732U, +/*01c2*/ 0x00050733U, +/*01c3*/ 0x00200734U, +/*01c4*/ 0x00090735U, +/*01c5*/ 0xffffffffU, +/*01c6*/ 0xffffffffU, +/*01c7*/ 0x00200736U, +/*01c8*/ 0x00040737U, +/*01c9*/ 0x08100737U, +/*01ca*/ 0x18060737U, +/*01cb*/ 0x00100738U, +/*01cc*/ 0xffffffffU, +/*01cd*/ 0xffffffffU, +/*01ce*/ 0xffffffffU, +/*01cf*/ 0xffffffffU, +/*01d0*/ 0xffffffffU, +/*01d1*/ 0xffffffffU, +/*01d2*/ 0xffffffffU, +/*01d3*/ 0xffffffffU, +/*01d4*/ 0x00200739U, +/*01d5*/ 0x000b073aU, +/*01d6*/ 0xffffffffU, +/*01d7*/ 0xffffffffU, +/*01d8*/ 0xffffffffU, +/*01d9*/ 0xffffffffU, +/*01da*/ 0xffffffffU, +/*01db*/ 0xffffffffU, +/*01dc*/ 0xffffffffU, +/*01dd*/ 0xffffffffU, +/*01de*/ 0x00010200U, +/*01df*/ 0x08040200U, +/*01e0*/ 0x10100200U, +/*01e1*/ 0x00010201U, +/*01e2*/ 0x08010201U, +/*01e3*/ 0xffffffffU, +/*01e4*/ 0xffffffffU, +/*01e5*/ 0x10100201U, +/*01e6*/ 0xffffffffU, +/*01e7*/ 0xffffffffU, +/*01e8*/ 0xffffffffU, +/*01e9*/ 0xffffffffU, +/*01ea*/ 0xffffffffU, +/*01eb*/ 0xffffffffU, +/*01ec*/ 0xffffffffU, +/*01ed*/ 0xffffffffU, +/*01ee*/ 0xffffffffU, +/*01ef*/ 0x00200202U, +/*01f0*/ 0x00100203U, +/*01f1*/ 0x00200204U, +/*01f2*/ 0x00100205U, +/*01f3*/ 0x00200206U, +/*01f4*/ 0x00100207U, +/*01f5*/ 0x10100207U, +/*01f6*/ 0x00200208U, +/*01f7*/ 0x00200209U, +/*01f8*/ 0x0020020aU, +/*01f9*/ 0x0020020bU, +/*01fa*/ 0x0010020cU, +/*01fb*/ 0x0020020dU, +/*01fc*/ 0x0020020eU, +/*01fd*/ 0x0020020fU, +/*01fe*/ 0x00200210U, +/*01ff*/ 0x00100211U, +/*0200*/ 0x00200212U, +/*0201*/ 0x00200213U, +/*0202*/ 0x00200214U, +/*0203*/ 0x00200215U, +/*0204*/ 0x00090216U, +/*0205*/ 0x10010216U, +/*0206*/ 0x00200217U, +/*0207*/ 0x00050218U, +/*0208*/ 0x08010218U, +/*0209*/ 0x10080218U, +/*020a*/ 0x18080218U, +/*020b*/ 0x001c0219U, +/*020c*/ 0x001c021aU, +/*020d*/ 0x001c021bU, +/*020e*/ 0x001c021cU, +/*020f*/ 0x001c021dU, +/*0210*/ 0x001c021eU, +/*0211*/ 0x001c021fU, +/*0212*/ 0x001c0220U, +/*0213*/ 0x001c0221U, +/*0214*/ 0x001c0222U, +/*0215*/ 0x001c0223U, +/*0216*/ 0x001c0224U, +/*0217*/ 0x001c0225U, +/*0218*/ 0x001c0226U, +/*0219*/ 0x001c0227U, +/*021a*/ 0x001c0228U, +/*021b*/ 0x00010229U, +/*021c*/ 0x08010229U, +/*021d*/ 0x10010229U, +/*021e*/ 0x18040229U, +/*021f*/ 0x0008022aU, +/*0220*/ 0x0808022aU, +/*0221*/ 0x1008022aU, +/*0222*/ 0x1804022aU, +/*0223*/ 0x0006022bU, +/*0224*/ 0xffffffffU, +/*0225*/ 0x0807022bU, +/*0226*/ 0x1006022bU, +/*0227*/ 0xffffffffU, +/*0228*/ 0x1807022bU, +/*0229*/ 0x0006022cU, +/*022a*/ 0xffffffffU, +/*022b*/ 0x0807022cU, +/*022c*/ 0x1002022cU, +/*022d*/ 0x1801022cU, +/*022e*/ 0xffffffffU, +/*022f*/ 0x000a022dU, +/*0230*/ 0x1010022dU, +/*0231*/ 0x000a022eU, +/*0232*/ 0x1010022eU, +/*0233*/ 0x000a022fU, +/*0234*/ 0x1010022fU, +/*0235*/ 0xffffffffU, +/*0236*/ 0x00100230U, +/*0237*/ 0xffffffffU, +/*0238*/ 0xffffffffU, +/*0239*/ 0x10010230U, +/*023a*/ 0x18010230U, +/*023b*/ 0x00010231U, +/*023c*/ 0x08010231U, +/*023d*/ 0x10010231U, +/*023e*/ 0x18010231U, +/*023f*/ 0x00020232U, +/*0240*/ 0x08020232U, +/*0241*/ 0x10020232U, +/*0242*/ 0x18020232U, +/*0243*/ 0x00020233U, +/*0244*/ 0x08030233U, +/*0245*/ 0x10010233U, +/*0246*/ 0x18010233U, +/*0247*/ 0x00010234U, +/*0248*/ 0x08010234U, +/*0249*/ 0xffffffffU, +/*024a*/ 0x10020234U, +/*024b*/ 0x18010234U, +/*024c*/ 0x00010235U, +/*024d*/ 0xffffffffU, +/*024e*/ 0x08020235U, +/*024f*/ 0x10010235U, +/*0250*/ 0x18010235U, +/*0251*/ 0xffffffffU, +/*0252*/ 0x00020236U, +/*0253*/ 0x08010236U, +/*0254*/ 0x10010236U, +/*0255*/ 0xffffffffU, +/*0256*/ 0x18020236U, +/*0257*/ 0x00070237U, +/*0258*/ 0x08010237U, +/*0259*/ 0x10010237U, +/*025a*/ 0x18010237U, +/*025b*/ 0x00010238U, +/*025c*/ 0x08010238U, +/*025d*/ 0x10010238U, +/*025e*/ 0xffffffffU, +/*025f*/ 0x18010238U, +/*0260*/ 0x00040239U, +/*0261*/ 0x08040239U, +/*0262*/ 0x10040239U, +/*0263*/ 0x18010239U, +/*0264*/ 0x0002023aU, +/*0265*/ 0x0806023aU, +/*0266*/ 0x1006023aU, +/*0267*/ 0xffffffffU, +/*0268*/ 0xffffffffU, +/*0269*/ 0xffffffffU, +/*026a*/ 0x1802023aU, +/*026b*/ 0x0010023bU, +/*026c*/ 0x1001023bU, +/*026d*/ 0x1801023bU, +/*026e*/ 0xffffffffU, +/*026f*/ 0x0004023cU, +/*0270*/ 0x0801023cU, +/*0271*/ 0x1004023cU, +/*0272*/ 0x1802023cU, +/*0273*/ 0x0008023dU, +/*0274*/ 0xffffffffU, +/*0275*/ 0xffffffffU, +/*0276*/ 0xffffffffU, +/*0277*/ 0x080a023dU, +/*0278*/ 0x0020023eU, +/*0279*/ 0x0020023fU, +/*027a*/ 0x00050240U, +/*027b*/ 0x08010240U, +/*027c*/ 0x10050240U, +/*027d*/ 0x18080240U, +/*027e*/ 0x00010241U, +/*027f*/ 0x08080241U, +/*0280*/ 0x10010241U, +/*0281*/ 0x18080241U, +/*0282*/ 0x00010242U, +/*0283*/ 0x08040242U, +/*0284*/ 0x10040242U, +/*0285*/ 0x18040242U, +/*0286*/ 0x00040243U, +/*0287*/ 0x08040243U, +/*0288*/ 0x10040243U, +/*0289*/ 0x18040243U, +/*028a*/ 0x00040244U, +/*028b*/ 0x08040244U, +/*028c*/ 0x10040244U, +/*028d*/ 0x18010244U, +/*028e*/ 0x00040245U, +/*028f*/ 0x08040245U, +/*0290*/ 0x10040245U, +/*0291*/ 0x18040245U, +/*0292*/ 0x00040246U, +/*0293*/ 0x08040246U, +/*0294*/ 0x10060246U, +/*0295*/ 0x18060246U, +/*0296*/ 0x00060247U, +/*0297*/ 0x08060247U, +/*0298*/ 0x10060247U, +/*0299*/ 0x18060247U, +/*029a*/ 0xffffffffU, +/*029b*/ 0x00010248U, +/*029c*/ 0x08010248U, +/*029d*/ 0x10020248U, +/*029e*/ 0xffffffffU, +/*029f*/ 0xffffffffU, +/*02a0*/ 0xffffffffU, +/*02a1*/ 0xffffffffU, +/*02a2*/ 0xffffffffU, +/*02a3*/ 0xffffffffU, +/*02a4*/ 0xffffffffU, +/*02a5*/ 0xffffffffU, +/*02a6*/ 0x18040248U, +/*02a7*/ 0x00040249U, +/*02a8*/ 0x08010249U, +/*02a9*/ 0x10010249U, +/*02aa*/ 0xffffffffU, +/*02ab*/ 0x18010249U, +/*02ac*/ 0x0001024aU, +/*02ad*/ 0xffffffffU, +/*02ae*/ 0x0801024aU, +/*02af*/ 0x1001024aU, +/*02b0*/ 0x1801024aU, +/*02b1*/ 0x0004024bU, +/*02b2*/ 0x0804024bU, +/*02b3*/ 0x100a024bU, +/*02b4*/ 0x0020024cU, +/*02b5*/ 0x0004024dU, +/*02b6*/ 0x0808024dU, +/*02b7*/ 0xffffffffU, +/*02b8*/ 0xffffffffU, +/*02b9*/ 0xffffffffU, +/*02ba*/ 0xffffffffU, +/*02bb*/ 0xffffffffU, +/*02bc*/ 0xffffffffU, +/*02bd*/ 0x1002024dU, +/*02be*/ 0x1802024dU, +/*02bf*/ 0x0020024eU, +/*02c0*/ 0x0002024fU, +/*02c1*/ 0x0810024fU, +/*02c2*/ 0x00100250U, +/*02c3*/ 0x10040250U, +/*02c4*/ 0x18040250U, +/*02c5*/ 0x00050251U, +/*02c6*/ 0x08050251U, +/*02c7*/ 0xffffffffU, +/*02c8*/ 0xffffffffU, +/*02c9*/ 0xffffffffU, +/*02ca*/ 0xffffffffU, +/*02cb*/ 0x10010251U, +/*02cc*/ 0x18010251U, +/*02cd*/ 0x00070252U, +/*02ce*/ 0x08070252U, +/*02cf*/ 0x10070252U, +/*02d0*/ 0x18070252U, +/*02d1*/ 0x00070253U, +/*02d2*/ 0x08070253U, +/*02d3*/ 0x10070253U, +/*02d4*/ 0x18070253U, +/*02d5*/ 0x00070254U, +/*02d6*/ 0x08070254U, +/*02d7*/ 0x10070254U, +/*02d8*/ 0xffffffffU, +/*02d9*/ 0xffffffffU, +/*02da*/ 0xffffffffU, +/*02db*/ 0xffffffffU, +/*02dc*/ 0xffffffffU, +/*02dd*/ 0xffffffffU, +/*02de*/ 0x18030254U, +/*02df*/ 0x00010255U, +/*02e0*/ 0x08020255U, +/*02e1*/ 0x10010255U, +/*02e2*/ 0x18040255U, +/*02e3*/ 0x00020256U, +/*02e4*/ 0x08010256U, +/*02e5*/ 0x10010256U, +/*02e6*/ 0xffffffffU, +/*02e7*/ 0x18010256U, +/*02e8*/ 0x00040257U, +/*02e9*/ 0x08080257U, +/*02ea*/ 0x100a0257U, +/*02eb*/ 0x000a0258U, +/*02ec*/ 0x100a0258U, +/*02ed*/ 0x000a0259U, +/*02ee*/ 0x100a0259U, +/*02ef*/ 0x000a025aU, +/*02f0*/ 0x0020025bU, +/*02f1*/ 0x0020025cU, +/*02f2*/ 0x0001025dU, +/*02f3*/ 0xffffffffU, +/*02f4*/ 0xffffffffU, +/*02f5*/ 0xffffffffU, +/*02f6*/ 0x0802025dU, +/*02f7*/ 0x1002025dU, +/*02f8*/ 0x0010025eU, +/*02f9*/ 0x1005025eU, +/*02fa*/ 0x1806025eU, +/*02fb*/ 0x0005025fU, +/*02fc*/ 0x0805025fU, +/*02fd*/ 0x100e025fU, +/*02fe*/ 0x00050260U, +/*02ff*/ 0x080e0260U, +/*0300*/ 0x18050260U, +/*0301*/ 0x000e0261U, +/*0302*/ 0x10050261U, +/*0303*/ 0x18010261U, +/*0304*/ 0x00050262U, +/*0305*/ 0x08050262U, +/*0306*/ 0x100a0262U, +/*0307*/ 0x000a0263U, +/*0308*/ 0x10050263U, +/*0309*/ 0x18050263U, +/*030a*/ 0x000a0264U, +/*030b*/ 0x100a0264U, +/*030c*/ 0x00050265U, +/*030d*/ 0x08050265U, +/*030e*/ 0x100a0265U, +/*030f*/ 0x000a0266U, +/*0310*/ 0xffffffffU, +/*0311*/ 0xffffffffU, +/*0312*/ 0xffffffffU, +/*0313*/ 0xffffffffU, +/*0314*/ 0xffffffffU, +/*0315*/ 0xffffffffU, +/*0316*/ 0x10070266U, +/*0317*/ 0x18070266U, +/*0318*/ 0x00040267U, +/*0319*/ 0x08040267U, +/*031a*/ 0xffffffffU, +/*031b*/ 0xffffffffU, +/*031c*/ 0xffffffffU, +/*031d*/ 0x10040267U, +/*031e*/ 0x18080267U, +/*031f*/ 0x00080268U, +/*0320*/ 0x08040268U, +/*0321*/ 0xffffffffU, +/*0322*/ 0xffffffffU, +/*0323*/ 0xffffffffU, +/*0324*/ 0x10040268U, +/*0325*/ 0xffffffffU, +/*0326*/ 0xffffffffU, +/*0327*/ 0xffffffffU, +/*0328*/ 0x18040268U, +/*0329*/ 0xffffffffU, +/*032a*/ 0xffffffffU, +/*032b*/ 0xffffffffU, +/*032c*/ 0x00040269U, +/*032d*/ 0x08050269U, +/*032e*/ 0x10070269U, +/*032f*/ 0x18080269U, +/*0330*/ 0x0010026aU, +/*0331*/ 0x1008026aU, +/*0332*/ 0x0010026bU, +/*0333*/ 0x1008026bU, +/*0334*/ 0x0010026cU, +/*0335*/ 0x1008026cU, +/*0336*/ 0x1808026cU, +/*0337*/ 0x0001026dU, +/*0338*/ 0x0801026dU, +/*0339*/ 0x1006026dU, +/*033a*/ 0x1806026dU, +/*033b*/ 0x0006026eU, +/*033c*/ 0xffffffffU, +/*033d*/ 0x0801026eU, +/*033e*/ 0x1003026eU, +/*033f*/ 0xffffffffU, +/*0340*/ 0xffffffffU, +/*0341*/ 0xffffffffU, +/*0342*/ 0x000a026fU, +/*0343*/ 0x100a026fU, +/*0344*/ 0x00040270U, +/*0345*/ 0x08010270U, +/*0346*/ 0x10040270U, +/*0347*/ 0xffffffffU, +/*0348*/ 0xffffffffU, +/*0349*/ 0xffffffffU, +/*034a*/ 0xffffffffU, +/*034b*/ 0xffffffffU, +/*034c*/ 0xffffffffU, +/*034d*/ 0x18070270U, +/*034e*/ 0x00070271U, +/*034f*/ 0x08050271U, +/*0350*/ 0x10050271U, +/*0351*/ 0xffffffffU, +/*0352*/ 0xffffffffU, +/*0353*/ 0xffffffffU, +/*0354*/ 0x18040271U, +/*0355*/ 0x00010272U, +/*0356*/ 0x08010272U, +/*0357*/ 0x10020272U, +/*0358*/ 0x18080272U, +/*0359*/ 0x00200273U, +/*035a*/ 0x00200274U, +/*035b*/ 0x00100275U, +/*035c*/ 0xffffffffU, +/*035d*/ 0xffffffffU, +/*035e*/ 0xffffffffU, +/*035f*/ 0x10020275U, +/*0360*/ 0x18010275U, +/*0361*/ 0xffffffffU, +/*0362*/ 0x00020276U, +/*0363*/ 0x08080276U, +/*0364*/ 0x10080276U, +/*0365*/ 0x18080276U, +/*0366*/ 0x00080277U, +/*0367*/ 0x08080277U, +/*0368*/ 0x10080277U, +/*0369*/ 0xffffffffU, +/*036a*/ 0x18080277U, +/*036b*/ 0x00080278U, +/*036c*/ 0x08080278U, +/*036d*/ 0x10080278U, +/*036e*/ 0x18080278U, +/*036f*/ 0x00080279U, +/*0370*/ 0xffffffffU, +/*0371*/ 0x08080279U, +/*0372*/ 0x10080279U, +/*0373*/ 0x18080279U, +/*0374*/ 0x0008027aU, +/*0375*/ 0x0808027aU, +/*0376*/ 0x1008027aU, +/*0377*/ 0xffffffffU, +/*0378*/ 0x1808027aU, +/*0379*/ 0x0008027bU, +/*037a*/ 0x0808027bU, +/*037b*/ 0x1008027bU, +/*037c*/ 0x1808027bU, +/*037d*/ 0x0008027cU, +/*037e*/ 0x0808027cU, +/*037f*/ 0xffffffffU, +/*0380*/ 0x1008027cU, +/*0381*/ 0x1808027cU, +/*0382*/ 0x0008027dU, +/*0383*/ 0x0808027dU, +/*0384*/ 0x1008027dU, +/*0385*/ 0x1808027dU, +/*0386*/ 0xffffffffU, +/*0387*/ 0x0008027eU, +/*0388*/ 0x0808027eU, +/*0389*/ 0x1008027eU, +/*038a*/ 0x1808027eU, +/*038b*/ 0x0008027fU, +/*038c*/ 0x0808027fU, +/*038d*/ 0xffffffffU, +/*038e*/ 0x1008027fU, +/*038f*/ 0x1808027fU, +/*0390*/ 0x00080280U, +/*0391*/ 0x08080280U, +/*0392*/ 0x10080280U, +/*0393*/ 0x18080280U, +/*0394*/ 0x00080281U, +/*0395*/ 0xffffffffU, +/*0396*/ 0x08080281U, +/*0397*/ 0x10080281U, +/*0398*/ 0x18080281U, +/*0399*/ 0x00080282U, +/*039a*/ 0x08080282U, +/*039b*/ 0x10080282U, +/*039c*/ 0xffffffffU, +/*039d*/ 0x18080282U, +/*039e*/ 0x00080283U, +/*039f*/ 0x08080283U, +/*03a0*/ 0x10080283U, +/*03a1*/ 0x18080283U, +/*03a2*/ 0x00080284U, +/*03a3*/ 0xffffffffU, +/*03a4*/ 0x08080284U, +/*03a5*/ 0x10080284U, +/*03a6*/ 0x18080284U, +/*03a7*/ 0x00080285U, +/*03a8*/ 0x08080285U, +/*03a9*/ 0x10080285U, +/*03aa*/ 0x18080285U, +/*03ab*/ 0xffffffffU, +/*03ac*/ 0x00080286U, +/*03ad*/ 0x08080286U, +/*03ae*/ 0x10080286U, +/*03af*/ 0x18080286U, +/*03b0*/ 0x00080287U, +/*03b1*/ 0x08080287U, +/*03b2*/ 0xffffffffU, +/*03b3*/ 0x10080287U, +/*03b4*/ 0x18080287U, +/*03b5*/ 0x00080288U, +/*03b6*/ 0x08080288U, +/*03b7*/ 0x10080288U, +/*03b8*/ 0x18080288U, +/*03b9*/ 0xffffffffU, +/*03ba*/ 0x00080289U, +/*03bb*/ 0x08020289U, +/*03bc*/ 0x10030289U, +/*03bd*/ 0x000a028aU, +/*03be*/ 0x100a028aU, +/*03bf*/ 0x000a028bU, +/*03c0*/ 0x1005028bU, +/*03c1*/ 0x1804028bU, +/*03c2*/ 0x0008028cU, +/*03c3*/ 0x0808028cU, +/*03c4*/ 0x1006028cU, +/*03c5*/ 0x1806028cU, +/*03c6*/ 0x0011028dU, +/*03c7*/ 0x1808028dU, +/*03c8*/ 0x0004028eU, +/*03c9*/ 0x0806028eU, +/*03ca*/ 0xffffffffU, +/*03cb*/ 0x1006028eU, +/*03cc*/ 0x1808028eU, +/*03cd*/ 0xffffffffU, +/*03ce*/ 0x0004028fU, +/*03cf*/ 0x0808028fU, +/*03d0*/ 0x1008028fU, +/*03d1*/ 0x1806028fU, +/*03d2*/ 0x00060290U, +/*03d3*/ 0x08110290U, +/*03d4*/ 0x00080291U, +/*03d5*/ 0x08040291U, +/*03d6*/ 0x10060291U, +/*03d7*/ 0xffffffffU, +/*03d8*/ 0x18060291U, +/*03d9*/ 0x00080292U, +/*03da*/ 0xffffffffU, +/*03db*/ 0x08040292U, +/*03dc*/ 0x10080292U, +/*03dd*/ 0x18080292U, +/*03de*/ 0x00060293U, +/*03df*/ 0x08060293U, +/*03e0*/ 0x00110294U, +/*03e1*/ 0x18080294U, +/*03e2*/ 0x00040295U, +/*03e3*/ 0x08060295U, +/*03e4*/ 0xffffffffU, +/*03e5*/ 0x10060295U, +/*03e6*/ 0x18080295U, +/*03e7*/ 0xffffffffU, +/*03e8*/ 0x00040296U, +/*03e9*/ 0x08040296U, +/*03ea*/ 0x10040296U, +/*03eb*/ 0x18040296U, +/*03ec*/ 0x00040297U, +/*03ed*/ 0x08040297U, +/*03ee*/ 0x10040297U, +/*03ef*/ 0x18040297U, +/*03f0*/ 0x00040298U, +/*03f1*/ 0x08040298U, +/*03f2*/ 0x10040298U, +/*03f3*/ 0x18040298U, +/*03f4*/ 0x00040299U, +/*03f5*/ 0x08040299U, +/*03f6*/ 0x10040299U, +/*03f7*/ 0x18040299U, +/*03f8*/ 0x0004029aU, +/*03f9*/ 0x0804029aU, +/*03fa*/ 0x1004029aU, +/*03fb*/ 0x1804029aU, +/*03fc*/ 0x0011029bU, +/*03fd*/ 0x0010029cU, +/*03fe*/ 0x0011029dU, +/*03ff*/ 0x0020029eU, +/*0400*/ 0x0020029fU, +/*0401*/ 0x002002a0U, +/*0402*/ 0x002002a1U, +/*0403*/ 0x002002a2U, +/*0404*/ 0x002002a3U, +/*0405*/ 0x002002a4U, +/*0406*/ 0x002002a5U, +/*0407*/ 0x002002a6U, +/*0408*/ 0x000202a7U, +/*0409*/ 0x080502a7U, +/*040a*/ 0x100502a7U, +/*040b*/ 0xffffffffU, +/*040c*/ 0xffffffffU, +/*040d*/ 0xffffffffU, +/*040e*/ 0xffffffffU, +/*040f*/ 0xffffffffU, +/*0410*/ 0xffffffffU, +/*0411*/ 0xffffffffU, +/*0412*/ 0xffffffffU, +/*0413*/ 0xffffffffU, +/*0414*/ 0xffffffffU, +/*0415*/ 0xffffffffU, +/*0416*/ 0xffffffffU, +/*0417*/ 0xffffffffU, +/*0418*/ 0xffffffffU, +/*0419*/ 0xffffffffU, +/*041a*/ 0xffffffffU, +/*041b*/ 0xffffffffU, +/*041c*/ 0xffffffffU, +/*041d*/ 0xffffffffU, +/*041e*/ 0xffffffffU, +/*041f*/ 0xffffffffU, +/*0420*/ 0xffffffffU, +/*0421*/ 0xffffffffU, +/*0422*/ 0xffffffffU, +/*0423*/ 0xffffffffU, +/*0424*/ 0xffffffffU, +/*0425*/ 0xffffffffU, +/*0426*/ 0xffffffffU, +/*0427*/ 0x180102a7U, +/*0428*/ 0x000402a8U, +/*0429*/ 0x081002a8U, +/*042a*/ 0x002002a9U, +/*042b*/ 0x001002aaU, +/*042c*/ 0x002002abU, +/*042d*/ 0x001002acU, +/*042e*/ 0x002002adU, +/*042f*/ 0x000702aeU, +/*0430*/ 0x080102aeU, +/*0431*/ 0x100202aeU, +/*0432*/ 0x180602aeU, +/*0433*/ 0x000102afU, +/*0434*/ 0x080102afU, +/*0435*/ 0x002002b0U, +/*0436*/ 0x000202b1U, +/*0437*/ 0x002002b2U, +/*0438*/ 0x002002b3U, +/*0439*/ 0xffffffffU, +/*043a*/ 0xffffffffU, +/*043b*/ 0xffffffffU, +/*043c*/ 0xffffffffU, +/*043d*/ 0xffffffffU, +/*043e*/ 0xffffffffU, +/*043f*/ 0xffffffffU, +/*0440*/ 0xffffffffU, +/*0441*/ 0xffffffffU, +/*0442*/ 0xffffffffU, +/*0443*/ 0xffffffffU, +/*0444*/ 0xffffffffU, +/*0445*/ 0xffffffffU, +/*0446*/ 0xffffffffU, +/*0447*/ 0xffffffffU, +/*0448*/ 0xffffffffU, +/*0449*/ 0xffffffffU, +/*044a*/ 0xffffffffU, +/*044b*/ 0xffffffffU, +/*044c*/ 0xffffffffU, +/*044d*/ 0xffffffffU, +/*044e*/ 0xffffffffU, +/*044f*/ 0xffffffffU, +/*0450*/ 0xffffffffU, +/*0451*/ 0xffffffffU, +/*0452*/ 0xffffffffU, +/*0453*/ 0xffffffffU, +/*0454*/ 0xffffffffU, +/*0455*/ 0xffffffffU, +/*0456*/ 0xffffffffU, +/*0457*/ 0xffffffffU, +/*0458*/ 0xffffffffU, +/*0459*/ 0xffffffffU, +/*045a*/ 0xffffffffU, +/*045b*/ 0xffffffffU, +/*045c*/ 0xffffffffU, +/*045d*/ 0xffffffffU, +/*045e*/ 0xffffffffU, +/*045f*/ 0x000402b4U, +/*0460*/ 0xffffffffU, +/*0461*/ 0xffffffffU, +/*0462*/ 0xffffffffU, +/*0463*/ 0xffffffffU, +/*0464*/ 0xffffffffU, +/*0465*/ 0xffffffffU, +/*0466*/ 0xffffffffU, +/*0467*/ 0xffffffffU, +/*0468*/ 0xffffffffU, +/*0469*/ 0xffffffffU, +/*046a*/ 0xffffffffU, +/*046b*/ 0xffffffffU, +/*046c*/ 0xffffffffU, +/*046d*/ 0xffffffffU, +/*046e*/ 0xffffffffU, +/*046f*/ 0xffffffffU, +/*0470*/ 0xffffffffU, +/*0471*/ 0xffffffffU, +/*0472*/ 0xffffffffU, +/*0473*/ 0xffffffffU, +/*0474*/ 0xffffffffU, +/*0475*/ 0xffffffffU, +/*0476*/ 0xffffffffU, +/*0477*/ 0xffffffffU, +/*0478*/ 0xffffffffU, +/*0479*/ 0xffffffffU, +/*047a*/ 0xffffffffU, +/*047b*/ 0xffffffffU, +/*047c*/ 0xffffffffU, +/*047d*/ 0xffffffffU, +/*047e*/ 0xffffffffU, +/*047f*/ 0xffffffffU, +/*0480*/ 0xffffffffU, +/*0481*/ 0xffffffffU, +/*0482*/ 0xffffffffU, +/*0483*/ 0xffffffffU, +/*0484*/ 0xffffffffU, +/*0485*/ 0xffffffffU, +/*0486*/ 0xffffffffU, +/*0487*/ 0xffffffffU, +/*0488*/ 0xffffffffU, +/*0489*/ 0xffffffffU, +/*048a*/ 0xffffffffU, +/*048b*/ 0xffffffffU, +/*048c*/ 0xffffffffU, +/*048d*/ 0xffffffffU, +/*048e*/ 0xffffffffU, +/*048f*/ 0xffffffffU, +/*0490*/ 0xffffffffU, +/*0491*/ 0xffffffffU, +/*0492*/ 0xffffffffU, +/*0493*/ 0xffffffffU, +/*0494*/ 0xffffffffU, + }, + { +/*0000*/ 0x00200800U, +/*0001*/ 0x00040801U, +/*0002*/ 0x080b0801U, +/*0003*/ 0xffffffffU, +/*0004*/ 0xffffffffU, +/*0005*/ 0x18010801U, +/*0006*/ 0x00050802U, +/*0007*/ 0x08050802U, +/*0008*/ 0x10050802U, +/*0009*/ 0x18050802U, +/*000a*/ 0x00050803U, +/*000b*/ 0x08050803U, +/*000c*/ 0x10050803U, +/*000d*/ 0x18050803U, +/*000e*/ 0x00050804U, +/*000f*/ 0x08040804U, +/*0010*/ 0x10030804U, +/*0011*/ 0x00180805U, +/*0012*/ 0x18030805U, +/*0013*/ 0x00180806U, +/*0014*/ 0x18020806U, +/*0015*/ 0x00010807U, +/*0016*/ 0x08020807U, +/*0017*/ 0x10010807U, +/*0018*/ 0x18010807U, +/*0019*/ 0x00020808U, +/*001a*/ 0x08040808U, +/*001b*/ 0x10040808U, +/*001c*/ 0x18040808U, +/*001d*/ 0x000a0809U, +/*001e*/ 0x10040809U, +/*001f*/ 0xffffffffU, +/*0020*/ 0xffffffffU, +/*0021*/ 0x18070809U, +/*0022*/ 0xffffffffU, +/*0023*/ 0xffffffffU, +/*0024*/ 0xffffffffU, +/*0025*/ 0xffffffffU, +/*0026*/ 0xffffffffU, +/*0027*/ 0xffffffffU, +/*0028*/ 0x000a080aU, +/*0029*/ 0x1005080aU, +/*002a*/ 0x1801080aU, +/*002b*/ 0x0001080bU, +/*002c*/ 0x0802080bU, +/*002d*/ 0x1009080bU, +/*002e*/ 0x0009080cU, +/*002f*/ 0x1002080cU, +/*0030*/ 0x0020080dU, +/*0031*/ 0xffffffffU, +/*0032*/ 0x0001080eU, +/*0033*/ 0xffffffffU, +/*0034*/ 0xffffffffU, +/*0035*/ 0xffffffffU, +/*0036*/ 0xffffffffU, +/*0037*/ 0x0020080fU, +/*0038*/ 0x00200810U, +/*0039*/ 0x00200811U, +/*003a*/ 0x00200812U, +/*003b*/ 0x00030813U, +/*003c*/ 0x08010813U, +/*003d*/ 0x10030813U, +/*003e*/ 0x18030813U, +/*003f*/ 0x00040814U, +/*0040*/ 0x08040814U, +/*0041*/ 0x10040814U, +/*0042*/ 0x18040814U, +/*0043*/ 0x00010815U, +/*0044*/ 0x08010815U, +/*0045*/ 0x10060815U, +/*0046*/ 0x18040815U, +/*0047*/ 0xffffffffU, +/*0048*/ 0x00060816U, +/*0049*/ 0x08040816U, +/*004a*/ 0x10060816U, +/*004b*/ 0x18040816U, +/*004c*/ 0x00020817U, +/*004d*/ 0x08050817U, +/*004e*/ 0x10080817U, +/*004f*/ 0x00200818U, +/*0050*/ 0x00060819U, +/*0051*/ 0x08030819U, +/*0052*/ 0x100b0819U, +/*0053*/ 0x0004081aU, +/*0054*/ 0x0804081aU, +/*0055*/ 0x1004081aU, +/*0056*/ 0xffffffffU, +/*0057*/ 0x1801081aU, +/*0058*/ 0x0009081bU, +/*0059*/ 0x0020081cU, +/*005a*/ 0x0020081dU, +/*005b*/ 0x0020081eU, +/*005c*/ 0x0020081fU, +/*005d*/ 0x00100820U, +/*005e*/ 0xffffffffU, +/*005f*/ 0x10010820U, +/*0060*/ 0x18060820U, +/*0061*/ 0x00080821U, +/*0062*/ 0x00200822U, +/*0063*/ 0xffffffffU, +/*0064*/ 0x000a0823U, +/*0065*/ 0x10060823U, +/*0066*/ 0x18070823U, +/*0067*/ 0x00080824U, +/*0068*/ 0x08080824U, +/*0069*/ 0x100a0824U, +/*006a*/ 0x00070825U, +/*006b*/ 0x08080825U, +/*006c*/ 0x10080825U, +/*006d*/ 0x18030825U, +/*006e*/ 0x000a0826U, +/*006f*/ 0x100a0826U, +/*0070*/ 0x00110827U, +/*0071*/ 0x00090828U, +/*0072*/ 0x10090828U, +/*0073*/ 0x00100829U, +/*0074*/ 0x100e0829U, +/*0075*/ 0x000e082aU, +/*0076*/ 0x100c082aU, +/*0077*/ 0x000a082bU, +/*0078*/ 0x100a082bU, +/*0079*/ 0x0002082cU, +/*007a*/ 0x0020082dU, +/*007b*/ 0x000b082eU, +/*007c*/ 0x100b082eU, +/*007d*/ 0x0020082fU, +/*007e*/ 0x00120830U, +/*007f*/ 0x00200831U, +/*0080*/ 0x00200832U, +/*0081*/ 0xffffffffU, +/*0082*/ 0xffffffffU, +/*0083*/ 0x00010833U, +/*0084*/ 0x08010833U, +/*0085*/ 0x10080833U, +/*0086*/ 0x000c0834U, +/*0087*/ 0x100c0834U, +/*0088*/ 0x000c0835U, +/*0089*/ 0x100c0835U, +/*008a*/ 0x000c0836U, +/*008b*/ 0x100c0836U, +/*008c*/ 0x000c0837U, +/*008d*/ 0x100c0837U, +/*008e*/ 0x000c0838U, +/*008f*/ 0x100c0838U, +/*0090*/ 0x000c0839U, +/*0091*/ 0x100b0839U, +/*0092*/ 0xffffffffU, +/*0093*/ 0xffffffffU, +/*0094*/ 0x000b083aU, +/*0095*/ 0x100b083aU, +/*0096*/ 0x000b083bU, +/*0097*/ 0x100b083bU, +/*0098*/ 0x000b083cU, +/*0099*/ 0x100b083cU, +/*009a*/ 0x000b083dU, +/*009b*/ 0x100b083dU, +/*009c*/ 0x000b083eU, +/*009d*/ 0x100a083eU, +/*009e*/ 0xffffffffU, +/*009f*/ 0x000a083fU, +/*00a0*/ 0x100a083fU, +/*00a1*/ 0x000a0840U, +/*00a2*/ 0x100a0840U, +/*00a3*/ 0x000a0841U, +/*00a4*/ 0x100a0841U, +/*00a5*/ 0x000a0842U, +/*00a6*/ 0x100a0842U, +/*00a7*/ 0x000a0843U, +/*00a8*/ 0x100a0843U, +/*00a9*/ 0x000a0844U, +/*00aa*/ 0x100a0844U, +/*00ab*/ 0x000a0845U, +/*00ac*/ 0x100a0845U, +/*00ad*/ 0x000a0846U, +/*00ae*/ 0x100a0846U, +/*00af*/ 0x000a0847U, +/*00b0*/ 0x100a0847U, +/*00b1*/ 0x000a0848U, +/*00b2*/ 0x100a0848U, +/*00b3*/ 0x000a0849U, +/*00b4*/ 0x100a0849U, +/*00b5*/ 0x000a084aU, +/*00b6*/ 0x100a084aU, +/*00b7*/ 0x000a084bU, +/*00b8*/ 0x100a084bU, +/*00b9*/ 0x000a084cU, +/*00ba*/ 0x100a084cU, +/*00bb*/ 0x0004084dU, +/*00bc*/ 0x0803084dU, +/*00bd*/ 0x100a084dU, +/*00be*/ 0x000a084eU, +/*00bf*/ 0x1001084eU, +/*00c0*/ 0x000a084fU, +/*00c1*/ 0x1004084fU, +/*00c2*/ 0x000b0850U, +/*00c3*/ 0x100a0850U, +/*00c4*/ 0xffffffffU, +/*00c5*/ 0x00080851U, +/*00c6*/ 0x08080851U, +/*00c7*/ 0x10080851U, +/*00c8*/ 0x18080851U, +/*00c9*/ 0x00080852U, +/*00ca*/ 0xffffffffU, +/*00cb*/ 0x08080852U, +/*00cc*/ 0x10010852U, +/*00cd*/ 0x18080852U, +/*00ce*/ 0x00080853U, +/*00cf*/ 0x08020853U, +/*00d0*/ 0x10020853U, +/*00d1*/ 0x18040853U, +/*00d2*/ 0x00040854U, +/*00d3*/ 0xffffffffU, +/*00d4*/ 0x08040854U, +/*00d5*/ 0x100a0854U, +/*00d6*/ 0x00060855U, +/*00d7*/ 0x08080855U, +/*00d8*/ 0xffffffffU, +/*00d9*/ 0x10040855U, +/*00da*/ 0x18040855U, +/*00db*/ 0x00050856U, +/*00dc*/ 0x08040856U, +/*00dd*/ 0x10050856U, +/*00de*/ 0x000a0857U, +/*00df*/ 0x100a0857U, +/*00e0*/ 0x00080858U, +/*00e1*/ 0xffffffffU, +/*00e2*/ 0x08040858U, +/*00e3*/ 0xffffffffU, +/*00e4*/ 0xffffffffU, +/*00e5*/ 0x00050a00U, +/*00e6*/ 0x08050a00U, +/*00e7*/ 0x10050a00U, +/*00e8*/ 0x18050a00U, +/*00e9*/ 0x00050a01U, +/*00ea*/ 0x08050a01U, +/*00eb*/ 0x100b0a01U, +/*00ec*/ 0x00010a02U, +/*00ed*/ 0x08030a02U, +/*00ee*/ 0x00200a03U, +/*00ef*/ 0xffffffffU, +/*00f0*/ 0x00030a04U, +/*00f1*/ 0x080a0a04U, +/*00f2*/ 0xffffffffU, +/*00f3*/ 0xffffffffU, +/*00f4*/ 0x18030a04U, +/*00f5*/ 0x00030a05U, +/*00f6*/ 0x08010a05U, +/*00f7*/ 0x10010a05U, +/*00f8*/ 0x18060a05U, +/*00f9*/ 0xffffffffU, +/*00fa*/ 0xffffffffU, +/*00fb*/ 0xffffffffU, +/*00fc*/ 0x00020a06U, +/*00fd*/ 0x08030a06U, +/*00fe*/ 0x10010a06U, +/*00ff*/ 0x000f0a07U, +/*0100*/ 0x00200a08U, +/*0101*/ 0x00200a09U, +/*0102*/ 0x000b0a0aU, +/*0103*/ 0x100b0a0aU, +/*0104*/ 0x000b0a0bU, +/*0105*/ 0xffffffffU, +/*0106*/ 0xffffffffU, +/*0107*/ 0x00180a0cU, +/*0108*/ 0x00180a0dU, +/*0109*/ 0x00180a0eU, +/*010a*/ 0x00180a0fU, +/*010b*/ 0x18040a0fU, +/*010c*/ 0x00020a10U, +/*010d*/ 0x08020a10U, +/*010e*/ 0x10040a10U, +/*010f*/ 0x18040a10U, +/*0110*/ 0x00010a11U, +/*0111*/ 0x08010a11U, +/*0112*/ 0x10010a11U, +/*0113*/ 0x18030a11U, +/*0114*/ 0x00200a12U, +/*0115*/ 0x00200a13U, +/*0116*/ 0xffffffffU, +/*0117*/ 0x00140a14U, +/*0118*/ 0x00140a15U, +/*0119*/ 0x00140a16U, +/*011a*/ 0x00140a17U, +/*011b*/ 0x00140a18U, +/*011c*/ 0x00140a19U, +/*011d*/ 0x00140a1aU, +/*011e*/ 0x00140a1bU, +/*011f*/ 0x001e0a1cU, +/*0120*/ 0x000a0a1dU, +/*0121*/ 0x10060a1dU, +/*0122*/ 0x18060a1dU, +/*0123*/ 0x00060a1eU, +/*0124*/ 0xffffffffU, +/*0125*/ 0x08060a1eU, +/*0126*/ 0x00080a1fU, +/*0127*/ 0x080b0a1fU, +/*0128*/ 0x000b0a20U, +/*0129*/ 0x100b0a20U, +/*012a*/ 0x000b0a21U, +/*012b*/ 0x100b0a21U, +/*012c*/ 0x000b0a22U, +/*012d*/ 0x10040a22U, +/*012e*/ 0x000a0a23U, +/*012f*/ 0x10060a23U, +/*0130*/ 0x18080a23U, +/*0131*/ 0xffffffffU, +/*0132*/ 0x00040a24U, +/*0133*/ 0xffffffffU, +/*0134*/ 0xffffffffU, +/*0135*/ 0x00010b80U, +/*0136*/ 0x08020b80U, +/*0137*/ 0x10050b80U, +/*0138*/ 0x18050b80U, +/*0139*/ 0x00050b81U, +/*013a*/ 0x08050b81U, +/*013b*/ 0x100b0b81U, +/*013c*/ 0x00050b82U, +/*013d*/ 0x08010b82U, +/*013e*/ 0x10010b82U, +/*013f*/ 0xffffffffU, +/*0140*/ 0x18010b82U, +/*0141*/ 0x00010b83U, +/*0142*/ 0x08040b83U, +/*0143*/ 0x100b0b83U, +/*0144*/ 0x000b0b84U, +/*0145*/ 0xffffffffU, +/*0146*/ 0x10040b84U, +/*0147*/ 0x000b0b85U, +/*0148*/ 0x10040b85U, +/*0149*/ 0x18010b85U, +/*014a*/ 0x00010b86U, +/*014b*/ 0x08010b86U, +/*014c*/ 0x00200b87U, +/*014d*/ 0x00200b88U, +/*014e*/ 0x00080b89U, +/*014f*/ 0x080a0b89U, +/*0150*/ 0x18050b89U, +/*0151*/ 0x000a0b8aU, +/*0152*/ 0x10030b8aU, +/*0153*/ 0x18030b8aU, +/*0154*/ 0x00010b8bU, +/*0155*/ 0x08020b8bU, +/*0156*/ 0x10010b8bU, +/*0157*/ 0x18010b8bU, +/*0158*/ 0x00010b8cU, +/*0159*/ 0x08030b8cU, +/*015a*/ 0xffffffffU, +/*015b*/ 0x10040b8cU, +/*015c*/ 0x18040b8cU, +/*015d*/ 0x00040b8dU, +/*015e*/ 0x08040b8dU, +/*015f*/ 0xffffffffU, +/*0160*/ 0xffffffffU, +/*0161*/ 0xffffffffU, +/*0162*/ 0xffffffffU, +/*0163*/ 0xffffffffU, +/*0164*/ 0xffffffffU, +/*0165*/ 0xffffffffU, +/*0166*/ 0xffffffffU, +/*0167*/ 0xffffffffU, +/*0168*/ 0x000d0b8eU, +/*0169*/ 0x100d0b8eU, +/*016a*/ 0x000d0b8fU, +/*016b*/ 0x00050b90U, +/*016c*/ 0x00010b91U, +/*016d*/ 0x080e0b91U, +/*016e*/ 0x000e0b92U, +/*016f*/ 0x100e0b92U, +/*0170*/ 0x000e0b93U, +/*0171*/ 0x100e0b93U, +/*0172*/ 0x00040b94U, +/*0173*/ 0x08040b94U, +/*0174*/ 0x10040b94U, +/*0175*/ 0x18040b94U, +/*0176*/ 0x00040b95U, +/*0177*/ 0x080b0b95U, +/*0178*/ 0x000b0b96U, +/*0179*/ 0x100b0b96U, +/*017a*/ 0x000b0b97U, +/*017b*/ 0xffffffffU, +/*017c*/ 0xffffffffU, +/*017d*/ 0xffffffffU, +/*017e*/ 0xffffffffU, +/*017f*/ 0x000d0b98U, +/*0180*/ 0x100d0b98U, +/*0181*/ 0x000d0b99U, +/*0182*/ 0x10100b99U, +/*0183*/ 0x10080b8dU, +/*0184*/ 0x18080b8dU, +/*0185*/ 0x00100b9aU, +/*0186*/ 0x10100b9aU, +/*0187*/ 0x00100b9bU, +/*0188*/ 0x10100b9bU, +/*0189*/ 0x00100b9cU, +/*018a*/ 0x10030b9cU, +/*018b*/ 0x18040b9cU, +/*018c*/ 0x00010b9dU, +/*018d*/ 0x08040b9dU, +/*018e*/ 0xffffffffU, +/*018f*/ 0xffffffffU, +/*0190*/ 0x10010b9dU, +/*0191*/ 0x00140b9eU, +/*0192*/ 0x000a0b9fU, +/*0193*/ 0x100c0b9fU, +/*0194*/ 0x00120ba0U, +/*0195*/ 0x00140ba1U, +/*0196*/ 0x00120ba2U, +/*0197*/ 0x00110ba3U, +/*0198*/ 0x00110ba4U, +/*0199*/ 0x00120ba5U, +/*019a*/ 0x00120ba6U, +/*019b*/ 0x00120ba7U, +/*019c*/ 0x00120ba8U, +/*019d*/ 0x00120ba9U, +/*019e*/ 0x00120baaU, +/*019f*/ 0x00120babU, +/*01a0*/ 0x00120bacU, +/*01a1*/ 0xffffffffU, +/*01a2*/ 0xffffffffU, +/*01a3*/ 0x00190badU, +/*01a4*/ 0x00190baeU, +/*01a5*/ 0x00200bafU, +/*01a6*/ 0x00170bb0U, +/*01a7*/ 0x18080bb0U, +/*01a8*/ 0x00010bb1U, +/*01a9*/ 0x08010bb1U, +/*01aa*/ 0x00200bb2U, +/*01ab*/ 0x00080bb3U, +/*01ac*/ 0xffffffffU, +/*01ad*/ 0x08030bb3U, +/*01ae*/ 0x00180bb4U, +/*01af*/ 0x00180bb5U, +/*01b0*/ 0xffffffffU, +/*01b1*/ 0xffffffffU, +/*01b2*/ 0xffffffffU, +/*01b3*/ 0xffffffffU, +/*01b4*/ 0xffffffffU, +/*01b5*/ 0xffffffffU, +/*01b6*/ 0xffffffffU, +/*01b7*/ 0xffffffffU, +/*01b8*/ 0xffffffffU, +/*01b9*/ 0xffffffffU, +/*01ba*/ 0xffffffffU, +/*01bb*/ 0xffffffffU, +/*01bc*/ 0xffffffffU, +/*01bd*/ 0xffffffffU, +/*01be*/ 0xffffffffU, +/*01bf*/ 0x00100bb6U, +/*01c0*/ 0x10010bb6U, +/*01c1*/ 0x18010bb6U, +/*01c2*/ 0x00050bb7U, +/*01c3*/ 0x00200bb8U, +/*01c4*/ 0x00090bb9U, +/*01c5*/ 0xffffffffU, +/*01c6*/ 0xffffffffU, +/*01c7*/ 0x00200bbaU, +/*01c8*/ 0x00040bbbU, +/*01c9*/ 0x08100bbbU, +/*01ca*/ 0x18060bbbU, +/*01cb*/ 0x00100bbcU, +/*01cc*/ 0xffffffffU, +/*01cd*/ 0x10080bbcU, +/*01ce*/ 0xffffffffU, +/*01cf*/ 0xffffffffU, +/*01d0*/ 0xffffffffU, +/*01d1*/ 0x18030bbcU, +/*01d2*/ 0x00020bbdU, +/*01d3*/ 0xffffffffU, +/*01d4*/ 0x00200bbeU, +/*01d5*/ 0x000b0bbfU, +/*01d6*/ 0xffffffffU, +/*01d7*/ 0xffffffffU, +/*01d8*/ 0xffffffffU, +/*01d9*/ 0x10020bbfU, +/*01da*/ 0xffffffffU, +/*01db*/ 0xffffffffU, +/*01dc*/ 0xffffffffU, +/*01dd*/ 0xffffffffU, +/*01de*/ 0x00010200U, +/*01df*/ 0x08040200U, +/*01e0*/ 0x10100200U, +/*01e1*/ 0x00010201U, +/*01e2*/ 0x08010201U, +/*01e3*/ 0xffffffffU, +/*01e4*/ 0xffffffffU, +/*01e5*/ 0x10100201U, +/*01e6*/ 0xffffffffU, +/*01e7*/ 0xffffffffU, +/*01e8*/ 0xffffffffU, +/*01e9*/ 0xffffffffU, +/*01ea*/ 0xffffffffU, +/*01eb*/ 0xffffffffU, +/*01ec*/ 0xffffffffU, +/*01ed*/ 0xffffffffU, +/*01ee*/ 0xffffffffU, +/*01ef*/ 0x00200202U, +/*01f0*/ 0x00100203U, +/*01f1*/ 0x00200204U, +/*01f2*/ 0x00100205U, +/*01f3*/ 0x00200206U, +/*01f4*/ 0x00100207U, +/*01f5*/ 0x10100207U, +/*01f6*/ 0x00200208U, +/*01f7*/ 0x00200209U, +/*01f8*/ 0x0020020aU, +/*01f9*/ 0x0020020bU, +/*01fa*/ 0x0010020cU, +/*01fb*/ 0x0020020dU, +/*01fc*/ 0x0020020eU, +/*01fd*/ 0x0020020fU, +/*01fe*/ 0x00200210U, +/*01ff*/ 0x00100211U, +/*0200*/ 0x00200212U, +/*0201*/ 0x00200213U, +/*0202*/ 0x00200214U, +/*0203*/ 0x00200215U, +/*0204*/ 0x00090216U, +/*0205*/ 0x10010216U, +/*0206*/ 0x00200217U, +/*0207*/ 0x00050218U, +/*0208*/ 0x08010218U, +/*0209*/ 0x10080218U, +/*020a*/ 0x18080218U, +/*020b*/ 0x001e0219U, +/*020c*/ 0x001e021aU, +/*020d*/ 0x001e021bU, +/*020e*/ 0x001e021cU, +/*020f*/ 0x001e021dU, +/*0210*/ 0x001e021eU, +/*0211*/ 0x001e021fU, +/*0212*/ 0x001e0220U, +/*0213*/ 0x001e0221U, +/*0214*/ 0x001e0222U, +/*0215*/ 0x001e0223U, +/*0216*/ 0x001e0224U, +/*0217*/ 0x001e0225U, +/*0218*/ 0x001e0226U, +/*0219*/ 0x001e0227U, +/*021a*/ 0x001e0228U, +/*021b*/ 0x00010229U, +/*021c*/ 0x08010229U, +/*021d*/ 0x10010229U, +/*021e*/ 0x18040229U, +/*021f*/ 0x0008022aU, +/*0220*/ 0x0808022aU, +/*0221*/ 0x1008022aU, +/*0222*/ 0x1804022aU, +/*0223*/ 0x0005022bU, +/*0224*/ 0x0806022bU, +/*0225*/ 0x1007022bU, +/*0226*/ 0x1805022bU, +/*0227*/ 0x0006022cU, +/*0228*/ 0x0807022cU, +/*0229*/ 0x1005022cU, +/*022a*/ 0x1806022cU, +/*022b*/ 0x0007022dU, +/*022c*/ 0x0802022dU, +/*022d*/ 0x1001022dU, +/*022e*/ 0xffffffffU, +/*022f*/ 0x000a022eU, +/*0230*/ 0x1010022eU, +/*0231*/ 0x000a022fU, +/*0232*/ 0x1010022fU, +/*0233*/ 0x000a0230U, +/*0234*/ 0x10100230U, +/*0235*/ 0xffffffffU, +/*0236*/ 0x00100231U, +/*0237*/ 0xffffffffU, +/*0238*/ 0xffffffffU, +/*0239*/ 0x10010231U, +/*023a*/ 0x18010231U, +/*023b*/ 0x00010232U, +/*023c*/ 0x08010232U, +/*023d*/ 0x10010232U, +/*023e*/ 0x18010232U, +/*023f*/ 0x00020233U, +/*0240*/ 0x08020233U, +/*0241*/ 0x10020233U, +/*0242*/ 0x18020233U, +/*0243*/ 0x00020234U, +/*0244*/ 0x08030234U, +/*0245*/ 0x10010234U, +/*0246*/ 0x18010234U, +/*0247*/ 0x00010235U, +/*0248*/ 0x08010235U, +/*0249*/ 0xffffffffU, +/*024a*/ 0x10020235U, +/*024b*/ 0x18010235U, +/*024c*/ 0x00010236U, +/*024d*/ 0xffffffffU, +/*024e*/ 0x08020236U, +/*024f*/ 0x10010236U, +/*0250*/ 0x18010236U, +/*0251*/ 0xffffffffU, +/*0252*/ 0x00020237U, +/*0253*/ 0x08010237U, +/*0254*/ 0x10010237U, +/*0255*/ 0xffffffffU, +/*0256*/ 0x18020237U, +/*0257*/ 0x00070238U, +/*0258*/ 0x08010238U, +/*0259*/ 0x10010238U, +/*025a*/ 0x18010238U, +/*025b*/ 0x00010239U, +/*025c*/ 0x08010239U, +/*025d*/ 0x10010239U, +/*025e*/ 0xffffffffU, +/*025f*/ 0x18010239U, +/*0260*/ 0x0004023aU, +/*0261*/ 0x0804023aU, +/*0262*/ 0x1004023aU, +/*0263*/ 0x1801023aU, +/*0264*/ 0x0002023bU, +/*0265*/ 0x0806023bU, +/*0266*/ 0x1006023bU, +/*0267*/ 0xffffffffU, +/*0268*/ 0xffffffffU, +/*0269*/ 0xffffffffU, +/*026a*/ 0x1802023bU, +/*026b*/ 0x0010023cU, +/*026c*/ 0x1001023cU, +/*026d*/ 0x1801023cU, +/*026e*/ 0xffffffffU, +/*026f*/ 0x0004023dU, +/*0270*/ 0x0801023dU, +/*0271*/ 0x1004023dU, +/*0272*/ 0x1802023dU, +/*0273*/ 0x0008023eU, +/*0274*/ 0xffffffffU, +/*0275*/ 0xffffffffU, +/*0276*/ 0xffffffffU, +/*0277*/ 0x080a023eU, +/*0278*/ 0x0020023fU, +/*0279*/ 0x00200240U, +/*027a*/ 0x00050241U, +/*027b*/ 0x08010241U, +/*027c*/ 0x10050241U, +/*027d*/ 0x18080241U, +/*027e*/ 0x00010242U, +/*027f*/ 0x08080242U, +/*0280*/ 0x10010242U, +/*0281*/ 0x18080242U, +/*0282*/ 0x00010243U, +/*0283*/ 0x08040243U, +/*0284*/ 0x10040243U, +/*0285*/ 0x18040243U, +/*0286*/ 0x00040244U, +/*0287*/ 0x08040244U, +/*0288*/ 0x10040244U, +/*0289*/ 0x18040244U, +/*028a*/ 0x00040245U, +/*028b*/ 0x08040245U, +/*028c*/ 0x10040245U, +/*028d*/ 0x18010245U, +/*028e*/ 0x00040246U, +/*028f*/ 0x08040246U, +/*0290*/ 0x10040246U, +/*0291*/ 0x18040246U, +/*0292*/ 0x00040247U, +/*0293*/ 0x08040247U, +/*0294*/ 0x10060247U, +/*0295*/ 0x18060247U, +/*0296*/ 0x00060248U, +/*0297*/ 0x08060248U, +/*0298*/ 0x10060248U, +/*0299*/ 0x18060248U, +/*029a*/ 0x00040249U, +/*029b*/ 0x08010249U, +/*029c*/ 0x10010249U, +/*029d*/ 0x18020249U, +/*029e*/ 0xffffffffU, +/*029f*/ 0xffffffffU, +/*02a0*/ 0xffffffffU, +/*02a1*/ 0xffffffffU, +/*02a2*/ 0xffffffffU, +/*02a3*/ 0xffffffffU, +/*02a4*/ 0xffffffffU, +/*02a5*/ 0xffffffffU, +/*02a6*/ 0x0004024aU, +/*02a7*/ 0x0804024aU, +/*02a8*/ 0x1001024aU, +/*02a9*/ 0x1801024aU, +/*02aa*/ 0xffffffffU, +/*02ab*/ 0x0001024bU, +/*02ac*/ 0x0801024bU, +/*02ad*/ 0xffffffffU, +/*02ae*/ 0x1001024bU, +/*02af*/ 0x1801024bU, +/*02b0*/ 0x0001024cU, +/*02b1*/ 0x0804024cU, +/*02b2*/ 0x1004024cU, +/*02b3*/ 0x000a024dU, +/*02b4*/ 0x0020024eU, +/*02b5*/ 0x0004024fU, +/*02b6*/ 0x0808024fU, +/*02b7*/ 0xffffffffU, +/*02b8*/ 0xffffffffU, +/*02b9*/ 0xffffffffU, +/*02ba*/ 0xffffffffU, +/*02bb*/ 0xffffffffU, +/*02bc*/ 0xffffffffU, +/*02bd*/ 0x1002024fU, +/*02be*/ 0x1802024fU, +/*02bf*/ 0x00200250U, +/*02c0*/ 0x00020251U, +/*02c1*/ 0x08100251U, +/*02c2*/ 0x00100252U, +/*02c3*/ 0x10040252U, +/*02c4*/ 0x18040252U, +/*02c5*/ 0x00050253U, +/*02c6*/ 0x08050253U, +/*02c7*/ 0xffffffffU, +/*02c8*/ 0xffffffffU, +/*02c9*/ 0xffffffffU, +/*02ca*/ 0xffffffffU, +/*02cb*/ 0x10010253U, +/*02cc*/ 0x18010253U, +/*02cd*/ 0x00080254U, +/*02ce*/ 0x08080254U, +/*02cf*/ 0x10080254U, +/*02d0*/ 0x18080254U, +/*02d1*/ 0x00080255U, +/*02d2*/ 0x08080255U, +/*02d3*/ 0x10080255U, +/*02d4*/ 0x18080255U, +/*02d5*/ 0x00080256U, +/*02d6*/ 0x08080256U, +/*02d7*/ 0x10080256U, +/*02d8*/ 0xffffffffU, +/*02d9*/ 0xffffffffU, +/*02da*/ 0xffffffffU, +/*02db*/ 0xffffffffU, +/*02dc*/ 0xffffffffU, +/*02dd*/ 0xffffffffU, +/*02de*/ 0x18030256U, +/*02df*/ 0x00010257U, +/*02e0*/ 0x08020257U, +/*02e1*/ 0x10010257U, +/*02e2*/ 0x18040257U, +/*02e3*/ 0x00020258U, +/*02e4*/ 0x08010258U, +/*02e5*/ 0x10010258U, +/*02e6*/ 0xffffffffU, +/*02e7*/ 0x18010258U, +/*02e8*/ 0x00040259U, +/*02e9*/ 0x08080259U, +/*02ea*/ 0x100a0259U, +/*02eb*/ 0x000a025aU, +/*02ec*/ 0x100a025aU, +/*02ed*/ 0x000a025bU, +/*02ee*/ 0x100a025bU, +/*02ef*/ 0x000a025cU, +/*02f0*/ 0x0020025dU, +/*02f1*/ 0x0020025eU, +/*02f2*/ 0x0001025fU, +/*02f3*/ 0xffffffffU, +/*02f4*/ 0xffffffffU, +/*02f5*/ 0xffffffffU, +/*02f6*/ 0x0802025fU, +/*02f7*/ 0x1002025fU, +/*02f8*/ 0x00100260U, +/*02f9*/ 0x10050260U, +/*02fa*/ 0x18060260U, +/*02fb*/ 0x00050261U, +/*02fc*/ 0x08050261U, +/*02fd*/ 0x100e0261U, +/*02fe*/ 0x00050262U, +/*02ff*/ 0x080e0262U, +/*0300*/ 0x18050262U, +/*0301*/ 0x000e0263U, +/*0302*/ 0x10050263U, +/*0303*/ 0x18010263U, +/*0304*/ 0x00050264U, +/*0305*/ 0x08050264U, +/*0306*/ 0x100a0264U, +/*0307*/ 0x000a0265U, +/*0308*/ 0x10050265U, +/*0309*/ 0x18050265U, +/*030a*/ 0x000a0266U, +/*030b*/ 0x100a0266U, +/*030c*/ 0x00050267U, +/*030d*/ 0x08050267U, +/*030e*/ 0x100a0267U, +/*030f*/ 0x000a0268U, +/*0310*/ 0xffffffffU, +/*0311*/ 0xffffffffU, +/*0312*/ 0xffffffffU, +/*0313*/ 0xffffffffU, +/*0314*/ 0xffffffffU, +/*0315*/ 0xffffffffU, +/*0316*/ 0x10070268U, +/*0317*/ 0x18070268U, +/*0318*/ 0x00040269U, +/*0319*/ 0x08040269U, +/*031a*/ 0xffffffffU, +/*031b*/ 0xffffffffU, +/*031c*/ 0xffffffffU, +/*031d*/ 0x10040269U, +/*031e*/ 0x18080269U, +/*031f*/ 0x0008026aU, +/*0320*/ 0x0804026aU, +/*0321*/ 0xffffffffU, +/*0322*/ 0xffffffffU, +/*0323*/ 0xffffffffU, +/*0324*/ 0x1004026aU, +/*0325*/ 0xffffffffU, +/*0326*/ 0xffffffffU, +/*0327*/ 0xffffffffU, +/*0328*/ 0x1804026aU, +/*0329*/ 0xffffffffU, +/*032a*/ 0xffffffffU, +/*032b*/ 0xffffffffU, +/*032c*/ 0x0004026bU, +/*032d*/ 0x0805026bU, +/*032e*/ 0x1007026bU, +/*032f*/ 0x1808026bU, +/*0330*/ 0x0010026cU, +/*0331*/ 0x1008026cU, +/*0332*/ 0x0010026dU, +/*0333*/ 0x1008026dU, +/*0334*/ 0x0010026eU, +/*0335*/ 0x1008026eU, +/*0336*/ 0x1808026eU, +/*0337*/ 0x0001026fU, +/*0338*/ 0x0801026fU, +/*0339*/ 0x1006026fU, +/*033a*/ 0x1806026fU, +/*033b*/ 0x00060270U, +/*033c*/ 0xffffffffU, +/*033d*/ 0x08010270U, +/*033e*/ 0x10030270U, +/*033f*/ 0xffffffffU, +/*0340*/ 0xffffffffU, +/*0341*/ 0xffffffffU, +/*0342*/ 0x000a0271U, +/*0343*/ 0x100a0271U, +/*0344*/ 0x00040272U, +/*0345*/ 0x08010272U, +/*0346*/ 0x10040272U, +/*0347*/ 0xffffffffU, +/*0348*/ 0xffffffffU, +/*0349*/ 0xffffffffU, +/*034a*/ 0xffffffffU, +/*034b*/ 0xffffffffU, +/*034c*/ 0xffffffffU, +/*034d*/ 0x18070272U, +/*034e*/ 0x00070273U, +/*034f*/ 0x08050273U, +/*0350*/ 0x10050273U, +/*0351*/ 0xffffffffU, +/*0352*/ 0xffffffffU, +/*0353*/ 0xffffffffU, +/*0354*/ 0x18040273U, +/*0355*/ 0x00010274U, +/*0356*/ 0x08010274U, +/*0357*/ 0x10020274U, +/*0358*/ 0x18080274U, +/*0359*/ 0x00200275U, +/*035a*/ 0x00200276U, +/*035b*/ 0x00100277U, +/*035c*/ 0xffffffffU, +/*035d*/ 0xffffffffU, +/*035e*/ 0xffffffffU, +/*035f*/ 0x10020277U, +/*0360*/ 0x18010277U, +/*0361*/ 0xffffffffU, +/*0362*/ 0x00020278U, +/*0363*/ 0x08100278U, +/*0364*/ 0x00100279U, +/*0365*/ 0x10100279U, +/*0366*/ 0x0008027aU, +/*0367*/ 0x0808027aU, +/*0368*/ 0x1008027aU, +/*0369*/ 0xffffffffU, +/*036a*/ 0x0010027bU, +/*036b*/ 0x1010027bU, +/*036c*/ 0x0010027cU, +/*036d*/ 0x1008027cU, +/*036e*/ 0x1808027cU, +/*036f*/ 0x0008027dU, +/*0370*/ 0xffffffffU, +/*0371*/ 0x0810027dU, +/*0372*/ 0x0010027eU, +/*0373*/ 0x1010027eU, +/*0374*/ 0x0008027fU, +/*0375*/ 0x0808027fU, +/*0376*/ 0x1008027fU, +/*0377*/ 0xffffffffU, +/*0378*/ 0x1808027fU, +/*0379*/ 0x00100280U, +/*037a*/ 0x10100280U, +/*037b*/ 0x00100281U, +/*037c*/ 0x10080281U, +/*037d*/ 0x18080281U, +/*037e*/ 0x00080282U, +/*037f*/ 0xffffffffU, +/*0380*/ 0x08100282U, +/*0381*/ 0x00100283U, +/*0382*/ 0x10100283U, +/*0383*/ 0x00080284U, +/*0384*/ 0x08080284U, +/*0385*/ 0x10080284U, +/*0386*/ 0xffffffffU, +/*0387*/ 0x00100285U, +/*0388*/ 0x10100285U, +/*0389*/ 0x00100286U, +/*038a*/ 0x10080286U, +/*038b*/ 0x18080286U, +/*038c*/ 0x00080287U, +/*038d*/ 0xffffffffU, +/*038e*/ 0x08080287U, +/*038f*/ 0x10100287U, +/*0390*/ 0x00100288U, +/*0391*/ 0x10100288U, +/*0392*/ 0x00080289U, +/*0393*/ 0x08080289U, +/*0394*/ 0x10080289U, +/*0395*/ 0xffffffffU, +/*0396*/ 0x0010028aU, +/*0397*/ 0x1010028aU, +/*0398*/ 0x0010028bU, +/*0399*/ 0x1008028bU, +/*039a*/ 0x1808028bU, +/*039b*/ 0x0008028cU, +/*039c*/ 0xffffffffU, +/*039d*/ 0x0810028cU, +/*039e*/ 0x0010028dU, +/*039f*/ 0x1010028dU, +/*03a0*/ 0x0008028eU, +/*03a1*/ 0x0808028eU, +/*03a2*/ 0x1008028eU, +/*03a3*/ 0xffffffffU, +/*03a4*/ 0x1808028eU, +/*03a5*/ 0x0010028fU, +/*03a6*/ 0x1010028fU, +/*03a7*/ 0x00100290U, +/*03a8*/ 0x10080290U, +/*03a9*/ 0x18080290U, +/*03aa*/ 0x00080291U, +/*03ab*/ 0xffffffffU, +/*03ac*/ 0x08100291U, +/*03ad*/ 0x00100292U, +/*03ae*/ 0x10100292U, +/*03af*/ 0x00080293U, +/*03b0*/ 0x08080293U, +/*03b1*/ 0x10080293U, +/*03b2*/ 0xffffffffU, +/*03b3*/ 0x00100294U, +/*03b4*/ 0x10100294U, +/*03b5*/ 0x00100295U, +/*03b6*/ 0x10080295U, +/*03b7*/ 0x18080295U, +/*03b8*/ 0x00080296U, +/*03b9*/ 0xffffffffU, +/*03ba*/ 0x08080296U, +/*03bb*/ 0x10020296U, +/*03bc*/ 0x18030296U, +/*03bd*/ 0x000a0297U, +/*03be*/ 0x100a0297U, +/*03bf*/ 0x000a0298U, +/*03c0*/ 0x10050298U, +/*03c1*/ 0x18040298U, +/*03c2*/ 0x00080299U, +/*03c3*/ 0x08080299U, +/*03c4*/ 0x10060299U, +/*03c5*/ 0x18060299U, +/*03c6*/ 0x0011029aU, +/*03c7*/ 0x1808029aU, +/*03c8*/ 0x0004029bU, +/*03c9*/ 0x0806029bU, +/*03ca*/ 0xffffffffU, +/*03cb*/ 0x1006029bU, +/*03cc*/ 0x1808029bU, +/*03cd*/ 0x0008029cU, +/*03ce*/ 0x0804029cU, +/*03cf*/ 0x1008029cU, +/*03d0*/ 0x1808029cU, +/*03d1*/ 0x0006029dU, +/*03d2*/ 0x0806029dU, +/*03d3*/ 0x0011029eU, +/*03d4*/ 0x1808029eU, +/*03d5*/ 0x0004029fU, +/*03d6*/ 0x0806029fU, +/*03d7*/ 0xffffffffU, +/*03d8*/ 0x1006029fU, +/*03d9*/ 0x1808029fU, +/*03da*/ 0x000802a0U, +/*03db*/ 0x080402a0U, +/*03dc*/ 0x100802a0U, +/*03dd*/ 0x180802a0U, +/*03de*/ 0x000602a1U, +/*03df*/ 0x080602a1U, +/*03e0*/ 0x001102a2U, +/*03e1*/ 0x180802a2U, +/*03e2*/ 0x000402a3U, +/*03e3*/ 0x080602a3U, +/*03e4*/ 0xffffffffU, +/*03e5*/ 0x100602a3U, +/*03e6*/ 0x180802a3U, +/*03e7*/ 0x000802a4U, +/*03e8*/ 0x080402a4U, +/*03e9*/ 0x100402a4U, +/*03ea*/ 0x180402a4U, +/*03eb*/ 0x000402a5U, +/*03ec*/ 0x080402a5U, +/*03ed*/ 0x100402a5U, +/*03ee*/ 0x180402a5U, +/*03ef*/ 0x000402a6U, +/*03f0*/ 0x080402a6U, +/*03f1*/ 0x100402a6U, +/*03f2*/ 0x180402a6U, +/*03f3*/ 0x000402a7U, +/*03f4*/ 0x080402a7U, +/*03f5*/ 0x100402a7U, +/*03f6*/ 0x180402a7U, +/*03f7*/ 0x000402a8U, +/*03f8*/ 0x080402a8U, +/*03f9*/ 0x100402a8U, +/*03fa*/ 0x180402a8U, +/*03fb*/ 0x000402a9U, +/*03fc*/ 0x081202a9U, +/*03fd*/ 0x001102aaU, +/*03fe*/ 0x001202abU, +/*03ff*/ 0x002002acU, +/*0400*/ 0x002002adU, +/*0401*/ 0x002002aeU, +/*0402*/ 0x002002afU, +/*0403*/ 0x002002b0U, +/*0404*/ 0x002002b1U, +/*0405*/ 0x002002b2U, +/*0406*/ 0x002002b3U, +/*0407*/ 0x002002b4U, +/*0408*/ 0x000302b5U, +/*0409*/ 0x080502b5U, +/*040a*/ 0x100502b5U, +/*040b*/ 0x180102b5U, +/*040c*/ 0x000502b6U, +/*040d*/ 0x080502b6U, +/*040e*/ 0x100502b6U, +/*040f*/ 0x180502b6U, +/*0410*/ 0x000502b7U, +/*0411*/ 0x080502b7U, +/*0412*/ 0x100502b7U, +/*0413*/ 0x180502b7U, +/*0414*/ 0x000502b8U, +/*0415*/ 0x080502b8U, +/*0416*/ 0x100502b8U, +/*0417*/ 0x180502b8U, +/*0418*/ 0x000502b9U, +/*0419*/ 0x080502b9U, +/*041a*/ 0x100502b9U, +/*041b*/ 0x180502b9U, +/*041c*/ 0x000502baU, +/*041d*/ 0x080502baU, +/*041e*/ 0x100502baU, +/*041f*/ 0x180502baU, +/*0420*/ 0x000502bbU, +/*0421*/ 0x080502bbU, +/*0422*/ 0x100102bbU, +/*0423*/ 0x180202bbU, +/*0424*/ 0x000202bcU, +/*0425*/ 0x080202bcU, +/*0426*/ 0x100202bcU, +/*0427*/ 0x180102bcU, +/*0428*/ 0x000402bdU, +/*0429*/ 0x081002bdU, +/*042a*/ 0x002002beU, +/*042b*/ 0x001002bfU, +/*042c*/ 0x002002c0U, +/*042d*/ 0x001002c1U, +/*042e*/ 0x002002c2U, +/*042f*/ 0x000702c3U, +/*0430*/ 0x080102c3U, +/*0431*/ 0x100202c3U, +/*0432*/ 0x180602c3U, +/*0433*/ 0x000102c4U, +/*0434*/ 0x080102c4U, +/*0435*/ 0x002002c5U, +/*0436*/ 0x000302c6U, +/*0437*/ 0x002002c7U, +/*0438*/ 0x002002c8U, +/*0439*/ 0xffffffffU, +/*043a*/ 0xffffffffU, +/*043b*/ 0xffffffffU, +/*043c*/ 0xffffffffU, +/*043d*/ 0xffffffffU, +/*043e*/ 0xffffffffU, +/*043f*/ 0xffffffffU, +/*0440*/ 0xffffffffU, +/*0441*/ 0xffffffffU, +/*0442*/ 0xffffffffU, +/*0443*/ 0xffffffffU, +/*0444*/ 0xffffffffU, +/*0445*/ 0xffffffffU, +/*0446*/ 0xffffffffU, +/*0447*/ 0xffffffffU, +/*0448*/ 0xffffffffU, +/*0449*/ 0xffffffffU, +/*044a*/ 0xffffffffU, +/*044b*/ 0xffffffffU, +/*044c*/ 0xffffffffU, +/*044d*/ 0xffffffffU, +/*044e*/ 0xffffffffU, +/*044f*/ 0xffffffffU, +/*0450*/ 0xffffffffU, +/*0451*/ 0xffffffffU, +/*0452*/ 0xffffffffU, +/*0453*/ 0xffffffffU, +/*0454*/ 0xffffffffU, +/*0455*/ 0xffffffffU, +/*0456*/ 0xffffffffU, +/*0457*/ 0xffffffffU, +/*0458*/ 0xffffffffU, +/*0459*/ 0xffffffffU, +/*045a*/ 0xffffffffU, +/*045b*/ 0xffffffffU, +/*045c*/ 0xffffffffU, +/*045d*/ 0xffffffffU, +/*045e*/ 0xffffffffU, +/*045f*/ 0x000402c9U, +/*0460*/ 0xffffffffU, +/*0461*/ 0xffffffffU, +/*0462*/ 0xffffffffU, +/*0463*/ 0xffffffffU, +/*0464*/ 0xffffffffU, +/*0465*/ 0xffffffffU, +/*0466*/ 0xffffffffU, +/*0467*/ 0xffffffffU, +/*0468*/ 0xffffffffU, +/*0469*/ 0xffffffffU, +/*046a*/ 0xffffffffU, +/*046b*/ 0xffffffffU, +/*046c*/ 0xffffffffU, +/*046d*/ 0xffffffffU, +/*046e*/ 0xffffffffU, +/*046f*/ 0xffffffffU, +/*0470*/ 0xffffffffU, +/*0471*/ 0xffffffffU, +/*0472*/ 0xffffffffU, +/*0473*/ 0xffffffffU, +/*0474*/ 0xffffffffU, +/*0475*/ 0xffffffffU, +/*0476*/ 0xffffffffU, +/*0477*/ 0xffffffffU, +/*0478*/ 0xffffffffU, +/*0479*/ 0xffffffffU, +/*047a*/ 0xffffffffU, +/*047b*/ 0xffffffffU, +/*047c*/ 0xffffffffU, +/*047d*/ 0xffffffffU, +/*047e*/ 0xffffffffU, +/*047f*/ 0xffffffffU, +/*0480*/ 0xffffffffU, +/*0481*/ 0xffffffffU, +/*0482*/ 0xffffffffU, +/*0483*/ 0xffffffffU, +/*0484*/ 0xffffffffU, +/*0485*/ 0xffffffffU, +/*0486*/ 0xffffffffU, +/*0487*/ 0xffffffffU, +/*0488*/ 0xffffffffU, +/*0489*/ 0xffffffffU, +/*048a*/ 0xffffffffU, +/*048b*/ 0xffffffffU, +/*048c*/ 0xffffffffU, +/*048d*/ 0xffffffffU, +/*048e*/ 0xffffffffU, +/*048f*/ 0xffffffffU, +/*0490*/ 0xffffffffU, +/*0491*/ 0xffffffffU, +/*0492*/ 0xffffffffU, +/*0493*/ 0xffffffffU, +/*0494*/ 0xffffffffU, + }, + { +/*0000*/ 0x00200400U, +/*0001*/ 0x00040401U, +/*0002*/ 0x080b0401U, +/*0003*/ 0x000a0402U, +/*0004*/ 0x10020402U, +/*0005*/ 0x18010402U, +/*0006*/ 0x00050403U, +/*0007*/ 0x08050403U, +/*0008*/ 0x10050403U, +/*0009*/ 0x18050403U, +/*000a*/ 0x00050404U, +/*000b*/ 0x08050404U, +/*000c*/ 0x10050404U, +/*000d*/ 0x18050404U, +/*000e*/ 0x00050405U, +/*000f*/ 0x08040405U, +/*0010*/ 0x10030405U, +/*0011*/ 0x00180406U, +/*0012*/ 0x18030406U, +/*0013*/ 0x00180407U, +/*0014*/ 0x18020407U, +/*0015*/ 0x00010408U, +/*0016*/ 0x08020408U, +/*0017*/ 0x10010408U, +/*0018*/ 0x18010408U, +/*0019*/ 0x00020409U, +/*001a*/ 0x08040409U, +/*001b*/ 0x10040409U, +/*001c*/ 0x18040409U, +/*001d*/ 0xffffffffU, +/*001e*/ 0x0004040aU, +/*001f*/ 0xffffffffU, +/*0020*/ 0xffffffffU, +/*0021*/ 0x0809040aU, +/*0022*/ 0x1801040aU, +/*0023*/ 0x0020040bU, +/*0024*/ 0x001c040cU, +/*0025*/ 0x0001040dU, +/*0026*/ 0x0807040dU, +/*0027*/ 0x1009040dU, +/*0028*/ 0x000a040eU, +/*0029*/ 0x1005040eU, +/*002a*/ 0x1801040eU, +/*002b*/ 0x1001040fU, +/*002c*/ 0x1802040fU, +/*002d*/ 0x0009040fU, +/*002e*/ 0x00090410U, +/*002f*/ 0x10020410U, +/*0030*/ 0x00200411U, +/*0031*/ 0x00010412U, +/*0032*/ 0x08020412U, +/*0033*/ 0xffffffffU, +/*0034*/ 0xffffffffU, +/*0035*/ 0xffffffffU, +/*0036*/ 0xffffffffU, +/*0037*/ 0x00200413U, +/*0038*/ 0x00200414U, +/*0039*/ 0x00200415U, +/*003a*/ 0x00200416U, +/*003b*/ 0x00030417U, +/*003c*/ 0x08010417U, +/*003d*/ 0x10040417U, +/*003e*/ 0x18030417U, +/*003f*/ 0x00040418U, +/*0040*/ 0x08040418U, +/*0041*/ 0x10040418U, +/*0042*/ 0x18040418U, +/*0043*/ 0x00010419U, +/*0044*/ 0x08010419U, +/*0045*/ 0x10060419U, +/*0046*/ 0x18040419U, +/*0047*/ 0xffffffffU, +/*0048*/ 0x0006041aU, +/*0049*/ 0x0804041aU, +/*004a*/ 0x1006041aU, +/*004b*/ 0x1804041aU, +/*004c*/ 0x0002041bU, +/*004d*/ 0x0805041bU, +/*004e*/ 0x1008041bU, +/*004f*/ 0xffffffffU, +/*0050*/ 0x1806041bU, +/*0051*/ 0x0003041cU, +/*0052*/ 0x080b041cU, +/*0053*/ 0x1804041cU, +/*0054*/ 0x0004041dU, +/*0055*/ 0x0804041dU, +/*0056*/ 0x1001041dU, +/*0057*/ 0xffffffffU, +/*0058*/ 0x0009041eU, +/*0059*/ 0x0020041fU, +/*005a*/ 0x00200420U, +/*005b*/ 0x00200421U, +/*005c*/ 0x00200422U, +/*005d*/ 0x00100423U, +/*005e*/ 0xffffffffU, +/*005f*/ 0x10010423U, +/*0060*/ 0x18060423U, +/*0061*/ 0x00080424U, +/*0062*/ 0x00200425U, +/*0063*/ 0x00100426U, +/*0064*/ 0x100a0426U, +/*0065*/ 0x00060427U, +/*0066*/ 0x08070427U, +/*0067*/ 0x10080427U, +/*0068*/ 0x18080427U, +/*0069*/ 0x000a0428U, +/*006a*/ 0x10070428U, +/*006b*/ 0x18080428U, +/*006c*/ 0x00080429U, +/*006d*/ 0x08030429U, +/*006e*/ 0x100a0429U, +/*006f*/ 0x000a042aU, +/*0070*/ 0x0011042bU, +/*0071*/ 0x0009042cU, +/*0072*/ 0x1009042cU, +/*0073*/ 0x0010042dU, +/*0074*/ 0x100e042dU, +/*0075*/ 0x000e042eU, +/*0076*/ 0x0012042fU, +/*0077*/ 0x000a0430U, +/*0078*/ 0x100a0430U, +/*0079*/ 0x00020431U, +/*007a*/ 0x00200432U, +/*007b*/ 0x000b0433U, +/*007c*/ 0x100b0433U, +/*007d*/ 0x00200434U, +/*007e*/ 0x00120435U, +/*007f*/ 0x00200436U, +/*0080*/ 0x00200437U, +/*0081*/ 0x00080438U, +/*0082*/ 0x08010438U, +/*0083*/ 0x10010438U, +/*0084*/ 0x18010438U, +/*0085*/ 0x00080439U, +/*0086*/ 0x080c0439U, +/*0087*/ 0x000c043aU, +/*0088*/ 0x100c043aU, +/*0089*/ 0x000c043bU, +/*008a*/ 0x100c043bU, +/*008b*/ 0x000c043cU, +/*008c*/ 0x100c043cU, +/*008d*/ 0x000c043dU, +/*008e*/ 0x100c043dU, +/*008f*/ 0x000c043eU, +/*0090*/ 0x100c043eU, +/*0091*/ 0x000b043fU, +/*0092*/ 0x1009043fU, +/*0093*/ 0x00010440U, +/*0094*/ 0x000b0441U, +/*0095*/ 0x100b0441U, +/*0096*/ 0x000b0442U, +/*0097*/ 0x100b0442U, +/*0098*/ 0x000b0443U, +/*0099*/ 0x100b0443U, +/*009a*/ 0x000b0444U, +/*009b*/ 0x100b0444U, +/*009c*/ 0x000b0445U, +/*009d*/ 0x100a0445U, +/*009e*/ 0x00020446U, +/*009f*/ 0x080a0446U, +/*00a0*/ 0x000a0447U, +/*00a1*/ 0x100a0447U, +/*00a2*/ 0x000a0448U, +/*00a3*/ 0x100a0448U, +/*00a4*/ 0x000a0449U, +/*00a5*/ 0x100a0449U, +/*00a6*/ 0x000a044aU, +/*00a7*/ 0x100a044aU, +/*00a8*/ 0x000a044bU, +/*00a9*/ 0x100a044bU, +/*00aa*/ 0x000a044cU, +/*00ab*/ 0x100a044cU, +/*00ac*/ 0x000a044dU, +/*00ad*/ 0x100a044dU, +/*00ae*/ 0x000a044eU, +/*00af*/ 0x100a044eU, +/*00b0*/ 0x000a044fU, +/*00b1*/ 0x100a044fU, +/*00b2*/ 0x000a0450U, +/*00b3*/ 0x100a0450U, +/*00b4*/ 0x000a0451U, +/*00b5*/ 0x100a0451U, +/*00b6*/ 0x000a0452U, +/*00b7*/ 0x100a0452U, +/*00b8*/ 0x000a0453U, +/*00b9*/ 0x100a0453U, +/*00ba*/ 0x000a0454U, +/*00bb*/ 0x10040454U, +/*00bc*/ 0x18030454U, +/*00bd*/ 0x000a0455U, +/*00be*/ 0x100a0455U, +/*00bf*/ 0x00010456U, +/*00c0*/ 0x080a0456U, +/*00c1*/ 0x18040456U, +/*00c2*/ 0x000b0457U, +/*00c3*/ 0x100a0457U, +/*00c4*/ 0x00030458U, +/*00c5*/ 0x00080459U, +/*00c6*/ 0x08080459U, +/*00c7*/ 0x10080459U, +/*00c8*/ 0x18080459U, +/*00c9*/ 0x0008045aU, +/*00ca*/ 0xffffffffU, +/*00cb*/ 0x0808045aU, +/*00cc*/ 0x1001045aU, +/*00cd*/ 0x1808045aU, +/*00ce*/ 0x0008045bU, +/*00cf*/ 0x0802045bU, +/*00d0*/ 0x1002045bU, +/*00d1*/ 0x1805045bU, +/*00d2*/ 0x0005045cU, +/*00d3*/ 0xffffffffU, +/*00d4*/ 0x0804045cU, +/*00d5*/ 0x100a045cU, +/*00d6*/ 0x0006045dU, +/*00d7*/ 0x0808045dU, +/*00d8*/ 0x1008045dU, +/*00d9*/ 0x1804045dU, +/*00da*/ 0x0004045eU, +/*00db*/ 0x0805045eU, +/*00dc*/ 0x1004045eU, +/*00dd*/ 0x1805045eU, +/*00de*/ 0x000a045fU, +/*00df*/ 0x100a045fU, +/*00e0*/ 0x00080460U, +/*00e1*/ 0xffffffffU, +/*00e2*/ 0x08040460U, +/*00e3*/ 0xffffffffU, +/*00e4*/ 0xffffffffU, +/*00e5*/ 0x00050600U, +/*00e6*/ 0x08050600U, +/*00e7*/ 0x10050600U, +/*00e8*/ 0x18050600U, +/*00e9*/ 0x00050601U, +/*00ea*/ 0x08050601U, +/*00eb*/ 0x100b0601U, +/*00ec*/ 0x00010602U, +/*00ed*/ 0x08030602U, +/*00ee*/ 0x00200603U, +/*00ef*/ 0x00100604U, +/*00f0*/ 0x10040604U, +/*00f1*/ 0x000a0605U, +/*00f2*/ 0x10090605U, +/*00f3*/ 0x00080606U, +/*00f4*/ 0x08030606U, +/*00f5*/ 0x10030606U, +/*00f6*/ 0x18010606U, +/*00f7*/ 0x00010607U, +/*00f8*/ 0x08070607U, +/*00f9*/ 0x10070607U, +/*00fa*/ 0x18050607U, +/*00fb*/ 0x00010608U, +/*00fc*/ 0x08020608U, +/*00fd*/ 0x10030608U, +/*00fe*/ 0x18010608U, +/*00ff*/ 0x000f0609U, +/*0100*/ 0x0020060aU, +/*0101*/ 0x0020060bU, +/*0102*/ 0x000b060cU, +/*0103*/ 0x100b060cU, +/*0104*/ 0x000b060dU, +/*0105*/ 0x0018060eU, +/*0106*/ 0x0018060fU, +/*0107*/ 0xffffffffU, +/*0108*/ 0xffffffffU, +/*0109*/ 0xffffffffU, +/*010a*/ 0xffffffffU, +/*010b*/ 0xffffffffU, +/*010c*/ 0x1802060fU, +/*010d*/ 0x00020610U, +/*010e*/ 0x08040610U, +/*010f*/ 0x10040610U, +/*0110*/ 0x18010610U, +/*0111*/ 0x00010611U, +/*0112*/ 0x08010611U, +/*0113*/ 0x10030611U, +/*0114*/ 0x00200612U, +/*0115*/ 0x00200613U, +/*0116*/ 0xffffffffU, +/*0117*/ 0x00140614U, +/*0118*/ 0x00140615U, +/*0119*/ 0x00140616U, +/*011a*/ 0x00140617U, +/*011b*/ 0x00140618U, +/*011c*/ 0x00140619U, +/*011d*/ 0x0014061aU, +/*011e*/ 0x0014061bU, +/*011f*/ 0x0018061cU, +/*0120*/ 0x000a061dU, +/*0121*/ 0x1006061dU, +/*0122*/ 0x1806061dU, +/*0123*/ 0x0006061eU, +/*0124*/ 0xffffffffU, +/*0125*/ 0x0806061eU, +/*0126*/ 0x0008061fU, +/*0127*/ 0x080b061fU, +/*0128*/ 0x000b0620U, +/*0129*/ 0x100b0620U, +/*012a*/ 0x000b0621U, +/*012b*/ 0x100b0621U, +/*012c*/ 0x000b0622U, +/*012d*/ 0x10040622U, +/*012e*/ 0x000a0623U, +/*012f*/ 0x10060623U, +/*0130*/ 0x18080623U, +/*0131*/ 0x00080624U, +/*0132*/ 0x08040624U, +/*0133*/ 0x00020680U, +/*0134*/ 0x00010681U, +/*0135*/ 0x08010681U, +/*0136*/ 0x10020681U, +/*0137*/ 0x18050681U, +/*0138*/ 0x00050682U, +/*0139*/ 0x08050682U, +/*013a*/ 0x10050682U, +/*013b*/ 0x000b0683U, +/*013c*/ 0x10050683U, +/*013d*/ 0x18010683U, +/*013e*/ 0x00010684U, +/*013f*/ 0xffffffffU, +/*0140*/ 0x08010684U, +/*0141*/ 0x10010684U, +/*0142*/ 0x18040684U, +/*0143*/ 0x000b0685U, +/*0144*/ 0x100b0685U, +/*0145*/ 0x000b0686U, +/*0146*/ 0x10040686U, +/*0147*/ 0x000b0687U, +/*0148*/ 0x10040687U, +/*0149*/ 0x18010687U, +/*014a*/ 0x00010688U, +/*014b*/ 0x08010688U, +/*014c*/ 0x00200689U, +/*014d*/ 0x0020068aU, +/*014e*/ 0x0008068bU, +/*014f*/ 0x080a068bU, +/*0150*/ 0x1805068bU, +/*0151*/ 0x000a068cU, +/*0152*/ 0x1003068cU, +/*0153*/ 0x1803068cU, +/*0154*/ 0x0001068dU, +/*0155*/ 0x0802068dU, +/*0156*/ 0x1001068dU, +/*0157*/ 0x1801068dU, +/*0158*/ 0x0001068eU, +/*0159*/ 0x0802068eU, +/*015a*/ 0x1001068eU, +/*015b*/ 0x0004068fU, +/*015c*/ 0x0804068fU, +/*015d*/ 0x1004068fU, +/*015e*/ 0x1804068fU, +/*015f*/ 0x00010690U, +/*0160*/ 0x08010690U, +/*0161*/ 0x10010690U, +/*0162*/ 0x00200691U, +/*0163*/ 0x00200692U, +/*0164*/ 0x00200693U, +/*0165*/ 0x00200694U, +/*0166*/ 0xffffffffU, +/*0167*/ 0x1801068eU, +/*0168*/ 0x000d0696U, +/*0169*/ 0x100d0696U, +/*016a*/ 0x000d0697U, +/*016b*/ 0x00050698U, +/*016c*/ 0x00010699U, +/*016d*/ 0x080e0699U, +/*016e*/ 0x000e069aU, +/*016f*/ 0x100e069aU, +/*0170*/ 0x000e069bU, +/*0171*/ 0x100e069bU, +/*0172*/ 0x0004069cU, +/*0173*/ 0x0804069cU, +/*0174*/ 0x1004069cU, +/*0175*/ 0x1804069cU, +/*0176*/ 0x0004069dU, +/*0177*/ 0x080b069dU, +/*0178*/ 0x000b069eU, +/*0179*/ 0x100b069eU, +/*017a*/ 0x000b069fU, +/*017b*/ 0xffffffffU, +/*017c*/ 0xffffffffU, +/*017d*/ 0xffffffffU, +/*017e*/ 0xffffffffU, +/*017f*/ 0x000d06a0U, +/*0180*/ 0x100d06a0U, +/*0181*/ 0x000d06a1U, +/*0182*/ 0x101006a1U, +/*0183*/ 0x00080695U, +/*0184*/ 0x08080695U, +/*0185*/ 0x001006a2U, +/*0186*/ 0x101006a2U, +/*0187*/ 0x001006a3U, +/*0188*/ 0x101006a3U, +/*0189*/ 0x001006a4U, +/*018a*/ 0x100306a4U, +/*018b*/ 0x180406a4U, +/*018c*/ 0x000106a5U, +/*018d*/ 0x080806a5U, +/*018e*/ 0x100106a5U, +/*018f*/ 0x180506a5U, +/*0190*/ 0x000106a6U, +/*0191*/ 0x081406a6U, +/*0192*/ 0x000a06a7U, +/*0193*/ 0x100c06a7U, +/*0194*/ 0x001206a8U, +/*0195*/ 0x001406a9U, +/*0196*/ 0x001206aaU, +/*0197*/ 0x001106abU, +/*0198*/ 0x001106acU, +/*0199*/ 0x001206adU, +/*019a*/ 0x001206aeU, +/*019b*/ 0x001206afU, +/*019c*/ 0x001206b0U, +/*019d*/ 0x001206b1U, +/*019e*/ 0x001206b2U, +/*019f*/ 0x001206b3U, +/*01a0*/ 0x001206b4U, +/*01a1*/ 0x001206b5U, +/*01a2*/ 0x001206b6U, +/*01a3*/ 0x000e06b7U, +/*01a4*/ 0x100d06b7U, +/*01a5*/ 0x002006b8U, +/*01a6*/ 0x001706b9U, +/*01a7*/ 0x000906baU, +/*01a8*/ 0x100106baU, +/*01a9*/ 0x180106baU, +/*01aa*/ 0x002006bbU, +/*01ab*/ 0x000806bcU, +/*01ac*/ 0x080306bcU, +/*01ad*/ 0x100306bcU, +/*01ae*/ 0x001806bdU, +/*01af*/ 0x001806beU, +/*01b0*/ 0x180706beU, +/*01b1*/ 0x000506bfU, +/*01b2*/ 0x080806bfU, +/*01b3*/ 0x100806bfU, +/*01b4*/ 0x180806bfU, +/*01b5*/ 0x000106c0U, +/*01b6*/ 0x080106c0U, +/*01b7*/ 0x002006c1U, +/*01b8*/ 0xffffffffU, +/*01b9*/ 0xffffffffU, +/*01ba*/ 0xffffffffU, +/*01bb*/ 0xffffffffU, +/*01bc*/ 0xffffffffU, +/*01bd*/ 0xffffffffU, +/*01be*/ 0xffffffffU, +/*01bf*/ 0x001006c2U, +/*01c0*/ 0x100106c2U, +/*01c1*/ 0x180106c2U, +/*01c2*/ 0x000206c3U, +/*01c3*/ 0x080406c3U, +/*01c4*/ 0x100906c3U, +/*01c5*/ 0x000706c4U, +/*01c6*/ 0x080406c4U, +/*01c7*/ 0x002006c5U, +/*01c8*/ 0x000106c6U, +/*01c9*/ 0x080206c6U, +/*01ca*/ 0x100606c6U, +/*01cb*/ 0x001006c7U, +/*01cc*/ 0x100106c7U, +/*01cd*/ 0x002006c8U, +/*01ce*/ 0x000806c9U, +/*01cf*/ 0x080106c9U, +/*01d0*/ 0x100506c9U, +/*01d1*/ 0xffffffffU, +/*01d2*/ 0x180206c9U, +/*01d3*/ 0x000106caU, +/*01d4*/ 0x002006cbU, +/*01d5*/ 0x000b06ccU, +/*01d6*/ 0x100106ccU, +/*01d7*/ 0x180306ccU, +/*01d8*/ 0x000806cdU, +/*01d9*/ 0x080206cdU, +/*01da*/ 0x100c06cdU, +/*01db*/ 0x000406ceU, +/*01dc*/ 0x080106ceU, +/*01dd*/ 0xffffffffU, +/*01de*/ 0x00010200U, +/*01df*/ 0x08040200U, +/*01e0*/ 0x10100200U, +/*01e1*/ 0x00010201U, +/*01e2*/ 0x08010201U, +/*01e3*/ 0x10010201U, +/*01e4*/ 0xffffffffU, +/*01e5*/ 0x00100202U, +/*01e6*/ 0x10080202U, +/*01e7*/ 0xffffffffU, +/*01e8*/ 0xffffffffU, +/*01e9*/ 0xffffffffU, +/*01ea*/ 0xffffffffU, +/*01eb*/ 0xffffffffU, +/*01ec*/ 0xffffffffU, +/*01ed*/ 0xffffffffU, +/*01ee*/ 0xffffffffU, +/*01ef*/ 0x00200203U, +/*01f0*/ 0x00100204U, +/*01f1*/ 0x00200205U, +/*01f2*/ 0x00100206U, +/*01f3*/ 0x00200207U, +/*01f4*/ 0x00100208U, +/*01f5*/ 0x00140209U, +/*01f6*/ 0x0020020aU, +/*01f7*/ 0x0020020bU, +/*01f8*/ 0x0020020cU, +/*01f9*/ 0x0020020dU, +/*01fa*/ 0x0014020eU, +/*01fb*/ 0x0020020fU, +/*01fc*/ 0x00200210U, +/*01fd*/ 0x00200211U, +/*01fe*/ 0x00200212U, +/*01ff*/ 0x00140213U, +/*0200*/ 0x00200214U, +/*0201*/ 0x00200215U, +/*0202*/ 0x00200216U, +/*0203*/ 0x00200217U, +/*0204*/ 0x00090218U, +/*0205*/ 0x10010218U, +/*0206*/ 0x00200219U, +/*0207*/ 0x0005021aU, +/*0208*/ 0x0801021aU, +/*0209*/ 0x1008021aU, +/*020a*/ 0x1808021aU, +/*020b*/ 0x001c021bU, +/*020c*/ 0x001c021cU, +/*020d*/ 0x001c021dU, +/*020e*/ 0x001c021eU, +/*020f*/ 0x001c021fU, +/*0210*/ 0x001c0220U, +/*0211*/ 0x001c0221U, +/*0212*/ 0x001c0222U, +/*0213*/ 0x001c0223U, +/*0214*/ 0x001c0224U, +/*0215*/ 0x001c0225U, +/*0216*/ 0x001c0226U, +/*0217*/ 0x001c0227U, +/*0218*/ 0x001c0228U, +/*0219*/ 0x001c0229U, +/*021a*/ 0x001c022aU, +/*021b*/ 0x0001022bU, +/*021c*/ 0x0801022bU, +/*021d*/ 0x1001022bU, +/*021e*/ 0x1804022bU, +/*021f*/ 0x0008022cU, +/*0220*/ 0x0808022cU, +/*0221*/ 0x1008022cU, +/*0222*/ 0x1804022cU, +/*0223*/ 0x0007022dU, +/*0224*/ 0xffffffffU, +/*0225*/ 0x0807022dU, +/*0226*/ 0x1007022dU, +/*0227*/ 0xffffffffU, +/*0228*/ 0x1807022dU, +/*0229*/ 0x0007022eU, +/*022a*/ 0xffffffffU, +/*022b*/ 0x0807022eU, +/*022c*/ 0x1002022eU, +/*022d*/ 0x1801022eU, +/*022e*/ 0x0001022fU, +/*022f*/ 0x080a022fU, +/*0230*/ 0x00140230U, +/*0231*/ 0x000a0231U, +/*0232*/ 0x00140232U, +/*0233*/ 0x000a0233U, +/*0234*/ 0x00140234U, +/*0235*/ 0x18010234U, +/*0236*/ 0x00100235U, +/*0237*/ 0x10050235U, +/*0238*/ 0x18010235U, +/*0239*/ 0x00010236U, +/*023a*/ 0x08010236U, +/*023b*/ 0x10010236U, +/*023c*/ 0x18010236U, +/*023d*/ 0x00010237U, +/*023e*/ 0x08010237U, +/*023f*/ 0x10020237U, +/*0240*/ 0x18020237U, +/*0241*/ 0x00020238U, +/*0242*/ 0x08020238U, +/*0243*/ 0x10020238U, +/*0244*/ 0x18030238U, +/*0245*/ 0x00010239U, +/*0246*/ 0x08010239U, +/*0247*/ 0x10010239U, +/*0248*/ 0x18010239U, +/*0249*/ 0xffffffffU, +/*024a*/ 0x0002023aU, +/*024b*/ 0x0801023aU, +/*024c*/ 0x1001023aU, +/*024d*/ 0xffffffffU, +/*024e*/ 0x1802023aU, +/*024f*/ 0x0001023bU, +/*0250*/ 0x0801023bU, +/*0251*/ 0xffffffffU, +/*0252*/ 0x1002023bU, +/*0253*/ 0x1801023bU, +/*0254*/ 0x0001023cU, +/*0255*/ 0xffffffffU, +/*0256*/ 0x0802023cU, +/*0257*/ 0x1007023cU, +/*0258*/ 0x1801023cU, +/*0259*/ 0x0001023dU, +/*025a*/ 0x0801023dU, +/*025b*/ 0x1001023dU, +/*025c*/ 0x1801023dU, +/*025d*/ 0x0001023eU, +/*025e*/ 0x0801023eU, +/*025f*/ 0x1001023eU, +/*0260*/ 0x1804023eU, +/*0261*/ 0x0004023fU, +/*0262*/ 0x0804023fU, +/*0263*/ 0x1001023fU, +/*0264*/ 0x1802023fU, +/*0265*/ 0x00060240U, +/*0266*/ 0x08060240U, +/*0267*/ 0x10020240U, +/*0268*/ 0x18020240U, +/*0269*/ 0x00020241U, +/*026a*/ 0xffffffffU, +/*026b*/ 0x08100241U, +/*026c*/ 0x18010241U, +/*026d*/ 0x00010242U, +/*026e*/ 0x08010242U, +/*026f*/ 0x10040242U, +/*0270*/ 0x18010242U, +/*0271*/ 0x00040243U, +/*0272*/ 0x08020243U, +/*0273*/ 0x10080243U, +/*0274*/ 0xffffffffU, +/*0275*/ 0xffffffffU, +/*0276*/ 0xffffffffU, +/*0277*/ 0x000a0244U, +/*0278*/ 0x00200245U, +/*0279*/ 0x00200246U, +/*027a*/ 0x00050247U, +/*027b*/ 0x08010247U, +/*027c*/ 0x10050247U, +/*027d*/ 0x18080247U, +/*027e*/ 0x00010248U, +/*027f*/ 0x08080248U, +/*0280*/ 0x10010248U, +/*0281*/ 0x18080248U, +/*0282*/ 0x00010249U, +/*0283*/ 0x08040249U, +/*0284*/ 0x10040249U, +/*0285*/ 0x18040249U, +/*0286*/ 0x0004024aU, +/*0287*/ 0x0804024aU, +/*0288*/ 0x1004024aU, +/*0289*/ 0x1804024aU, +/*028a*/ 0x0004024bU, +/*028b*/ 0x0804024bU, +/*028c*/ 0x1004024bU, +/*028d*/ 0x1801024bU, +/*028e*/ 0x0004024cU, +/*028f*/ 0x0804024cU, +/*0290*/ 0x1004024cU, +/*0291*/ 0x1804024cU, +/*0292*/ 0x0004024dU, +/*0293*/ 0x0804024dU, +/*0294*/ 0x1006024dU, +/*0295*/ 0x1806024dU, +/*0296*/ 0x0006024eU, +/*0297*/ 0x0806024eU, +/*0298*/ 0x1006024eU, +/*0299*/ 0x1806024eU, +/*029a*/ 0xffffffffU, +/*029b*/ 0x0001024fU, +/*029c*/ 0x0801024fU, +/*029d*/ 0x1002024fU, +/*029e*/ 0xffffffffU, +/*029f*/ 0xffffffffU, +/*02a0*/ 0xffffffffU, +/*02a1*/ 0xffffffffU, +/*02a2*/ 0xffffffffU, +/*02a3*/ 0xffffffffU, +/*02a4*/ 0xffffffffU, +/*02a5*/ 0xffffffffU, +/*02a6*/ 0x1804024fU, +/*02a7*/ 0x00040250U, +/*02a8*/ 0x08010250U, +/*02a9*/ 0x10010250U, +/*02aa*/ 0x18010250U, +/*02ab*/ 0x00010251U, +/*02ac*/ 0x08010251U, +/*02ad*/ 0x10010251U, +/*02ae*/ 0x18010251U, +/*02af*/ 0x00010252U, +/*02b0*/ 0x08010252U, +/*02b1*/ 0x10040252U, +/*02b2*/ 0x18040252U, +/*02b3*/ 0x000a0253U, +/*02b4*/ 0x00200254U, +/*02b5*/ 0x00040255U, +/*02b6*/ 0x08080255U, +/*02b7*/ 0x10020255U, +/*02b8*/ 0x18020255U, +/*02b9*/ 0x00020256U, +/*02ba*/ 0x08020256U, +/*02bb*/ 0x10020256U, +/*02bc*/ 0x18020256U, +/*02bd*/ 0xffffffffU, +/*02be*/ 0xffffffffU, +/*02bf*/ 0x00200257U, +/*02c0*/ 0x00020258U, +/*02c1*/ 0x08100258U, +/*02c2*/ 0x00100259U, +/*02c3*/ 0x10040259U, +/*02c4*/ 0x18040259U, +/*02c5*/ 0x0005025aU, +/*02c6*/ 0x0805025aU, +/*02c7*/ 0x0020025bU, +/*02c8*/ 0x0020025cU, +/*02c9*/ 0x0020025dU, +/*02ca*/ 0x0020025eU, +/*02cb*/ 0x0001025fU, +/*02cc*/ 0x0801025fU, +/*02cd*/ 0x1007025fU, +/*02ce*/ 0x1807025fU, +/*02cf*/ 0x00070260U, +/*02d0*/ 0x08070260U, +/*02d1*/ 0x10070260U, +/*02d2*/ 0x18070260U, +/*02d3*/ 0x00070261U, +/*02d4*/ 0x08070261U, +/*02d5*/ 0x10070261U, +/*02d6*/ 0x18070261U, +/*02d7*/ 0x00070262U, +/*02d8*/ 0x08070262U, +/*02d9*/ 0x10070262U, +/*02da*/ 0x18070262U, +/*02db*/ 0x00030263U, +/*02dc*/ 0x08030263U, +/*02dd*/ 0x10030263U, +/*02de*/ 0xffffffffU, +/*02df*/ 0x18010263U, +/*02e0*/ 0x00020264U, +/*02e1*/ 0x08010264U, +/*02e2*/ 0x10040264U, +/*02e3*/ 0x18020264U, +/*02e4*/ 0x00010265U, +/*02e5*/ 0x08010265U, +/*02e6*/ 0x10010265U, +/*02e7*/ 0x18010265U, +/*02e8*/ 0x00040266U, +/*02e9*/ 0x08080266U, +/*02ea*/ 0x100a0266U, +/*02eb*/ 0x000a0267U, +/*02ec*/ 0x100a0267U, +/*02ed*/ 0x000a0268U, +/*02ee*/ 0x100a0268U, +/*02ef*/ 0x000a0269U, +/*02f0*/ 0x0020026aU, +/*02f1*/ 0x0020026bU, +/*02f2*/ 0x0001026cU, +/*02f3*/ 0x0802026cU, +/*02f4*/ 0x1002026cU, +/*02f5*/ 0x1802026cU, +/*02f6*/ 0xffffffffU, +/*02f7*/ 0x0002026dU, +/*02f8*/ 0x0810026dU, +/*02f9*/ 0x1805026dU, +/*02fa*/ 0x0006026eU, +/*02fb*/ 0x0805026eU, +/*02fc*/ 0x1005026eU, +/*02fd*/ 0x000e026fU, +/*02fe*/ 0x1005026fU, +/*02ff*/ 0x000e0270U, +/*0300*/ 0x10050270U, +/*0301*/ 0x000e0271U, +/*0302*/ 0x10050271U, +/*0303*/ 0x18010271U, +/*0304*/ 0x00050272U, +/*0305*/ 0x08050272U, +/*0306*/ 0x100a0272U, +/*0307*/ 0x000a0273U, +/*0308*/ 0x10050273U, +/*0309*/ 0x18050273U, +/*030a*/ 0x000a0274U, +/*030b*/ 0x100a0274U, +/*030c*/ 0x00050275U, +/*030d*/ 0x08050275U, +/*030e*/ 0x100a0275U, +/*030f*/ 0x000a0276U, +/*0310*/ 0xffffffffU, +/*0311*/ 0xffffffffU, +/*0312*/ 0xffffffffU, +/*0313*/ 0xffffffffU, +/*0314*/ 0xffffffffU, +/*0315*/ 0xffffffffU, +/*0316*/ 0x10070276U, +/*0317*/ 0x18070276U, +/*0318*/ 0x00040277U, +/*0319*/ 0x08040277U, +/*031a*/ 0xffffffffU, +/*031b*/ 0xffffffffU, +/*031c*/ 0xffffffffU, +/*031d*/ 0x10040277U, +/*031e*/ 0x18080277U, +/*031f*/ 0x00080278U, +/*0320*/ 0x08040278U, +/*0321*/ 0xffffffffU, +/*0322*/ 0xffffffffU, +/*0323*/ 0xffffffffU, +/*0324*/ 0x10040278U, +/*0325*/ 0xffffffffU, +/*0326*/ 0xffffffffU, +/*0327*/ 0xffffffffU, +/*0328*/ 0x18040278U, +/*0329*/ 0xffffffffU, +/*032a*/ 0xffffffffU, +/*032b*/ 0xffffffffU, +/*032c*/ 0x00040279U, +/*032d*/ 0x08050279U, +/*032e*/ 0x10070279U, +/*032f*/ 0x18080279U, +/*0330*/ 0x0010027aU, +/*0331*/ 0x1008027aU, +/*0332*/ 0x0010027bU, +/*0333*/ 0x1008027bU, +/*0334*/ 0x0010027cU, +/*0335*/ 0x1008027cU, +/*0336*/ 0x1808027cU, +/*0337*/ 0x0001027dU, +/*0338*/ 0x0801027dU, +/*0339*/ 0x1006027dU, +/*033a*/ 0x1806027dU, +/*033b*/ 0x0006027eU, +/*033c*/ 0x0801027eU, +/*033d*/ 0x1001027eU, +/*033e*/ 0x1803027eU, +/*033f*/ 0x000a027fU, +/*0340*/ 0x100a027fU, +/*0341*/ 0x000a0280U, +/*0342*/ 0xffffffffU, +/*0343*/ 0x100a0280U, +/*0344*/ 0x00040281U, +/*0345*/ 0x08010281U, +/*0346*/ 0x10040281U, +/*0347*/ 0xffffffffU, +/*0348*/ 0xffffffffU, +/*0349*/ 0xffffffffU, +/*034a*/ 0xffffffffU, +/*034b*/ 0xffffffffU, +/*034c*/ 0xffffffffU, +/*034d*/ 0x18070281U, +/*034e*/ 0x00070282U, +/*034f*/ 0x08050282U, +/*0350*/ 0x10050282U, +/*0351*/ 0xffffffffU, +/*0352*/ 0xffffffffU, +/*0353*/ 0xffffffffU, +/*0354*/ 0x18040282U, +/*0355*/ 0x00010283U, +/*0356*/ 0x08010283U, +/*0357*/ 0x10020283U, +/*0358*/ 0x18080283U, +/*0359*/ 0x00200284U, +/*035a*/ 0x00200285U, +/*035b*/ 0x00100286U, +/*035c*/ 0x10020286U, +/*035d*/ 0x18020286U, +/*035e*/ 0x00020287U, +/*035f*/ 0xffffffffU, +/*0360*/ 0x08010287U, +/*0361*/ 0x10010287U, +/*0362*/ 0x18020287U, +/*0363*/ 0x00080288U, +/*0364*/ 0x08080288U, +/*0365*/ 0x10080288U, +/*0366*/ 0x18080288U, +/*0367*/ 0x00080289U, +/*0368*/ 0x08080289U, +/*0369*/ 0xffffffffU, +/*036a*/ 0x10080289U, +/*036b*/ 0x18080289U, +/*036c*/ 0x0008028aU, +/*036d*/ 0x0808028aU, +/*036e*/ 0x1008028aU, +/*036f*/ 0x1808028aU, +/*0370*/ 0xffffffffU, +/*0371*/ 0x0008028bU, +/*0372*/ 0x0808028bU, +/*0373*/ 0x1008028bU, +/*0374*/ 0x1808028bU, +/*0375*/ 0x0008028cU, +/*0376*/ 0x0808028cU, +/*0377*/ 0xffffffffU, +/*0378*/ 0x1008028cU, +/*0379*/ 0x1808028cU, +/*037a*/ 0x0008028dU, +/*037b*/ 0x0808028dU, +/*037c*/ 0x1008028dU, +/*037d*/ 0x1808028dU, +/*037e*/ 0x0008028eU, +/*037f*/ 0xffffffffU, +/*0380*/ 0x0808028eU, +/*0381*/ 0x1008028eU, +/*0382*/ 0x1808028eU, +/*0383*/ 0x0008028fU, +/*0384*/ 0x0808028fU, +/*0385*/ 0x1008028fU, +/*0386*/ 0xffffffffU, +/*0387*/ 0x1808028fU, +/*0388*/ 0x00080290U, +/*0389*/ 0x08080290U, +/*038a*/ 0x10080290U, +/*038b*/ 0x18080290U, +/*038c*/ 0x00080291U, +/*038d*/ 0xffffffffU, +/*038e*/ 0x08080291U, +/*038f*/ 0x10080291U, +/*0390*/ 0x18080291U, +/*0391*/ 0x00080292U, +/*0392*/ 0x08080292U, +/*0393*/ 0x10080292U, +/*0394*/ 0x18080292U, +/*0395*/ 0xffffffffU, +/*0396*/ 0x00080293U, +/*0397*/ 0x08080293U, +/*0398*/ 0x10080293U, +/*0399*/ 0x18080293U, +/*039a*/ 0x00080294U, +/*039b*/ 0x08080294U, +/*039c*/ 0xffffffffU, +/*039d*/ 0x10080294U, +/*039e*/ 0x18080294U, +/*039f*/ 0x00080295U, +/*03a0*/ 0x08080295U, +/*03a1*/ 0x10080295U, +/*03a2*/ 0x18080295U, +/*03a3*/ 0xffffffffU, +/*03a4*/ 0x00080296U, +/*03a5*/ 0x08080296U, +/*03a6*/ 0x10080296U, +/*03a7*/ 0x18080296U, +/*03a8*/ 0x00080297U, +/*03a9*/ 0x08080297U, +/*03aa*/ 0x10080297U, +/*03ab*/ 0xffffffffU, +/*03ac*/ 0x18080297U, +/*03ad*/ 0x00080298U, +/*03ae*/ 0x08080298U, +/*03af*/ 0x10080298U, +/*03b0*/ 0x18080298U, +/*03b1*/ 0x00080299U, +/*03b2*/ 0xffffffffU, +/*03b3*/ 0x08080299U, +/*03b4*/ 0x10080299U, +/*03b5*/ 0x18080299U, +/*03b6*/ 0x0008029aU, +/*03b7*/ 0x0808029aU, +/*03b8*/ 0x1008029aU, +/*03b9*/ 0xffffffffU, +/*03ba*/ 0x1808029aU, +/*03bb*/ 0x0002029bU, +/*03bc*/ 0x0803029bU, +/*03bd*/ 0x100a029bU, +/*03be*/ 0x000a029cU, +/*03bf*/ 0x100a029cU, +/*03c0*/ 0x0005029dU, +/*03c1*/ 0x0808029dU, +/*03c2*/ 0x1008029dU, +/*03c3*/ 0x1808029dU, +/*03c4*/ 0x0006029eU, +/*03c5*/ 0x0806029eU, +/*03c6*/ 0x0011029fU, +/*03c7*/ 0x1808029fU, +/*03c8*/ 0x000402a0U, +/*03c9*/ 0x080602a0U, +/*03ca*/ 0xffffffffU, +/*03cb*/ 0x100602a0U, +/*03cc*/ 0x180802a0U, +/*03cd*/ 0xffffffffU, +/*03ce*/ 0x000802a1U, +/*03cf*/ 0x080802a1U, +/*03d0*/ 0x100802a1U, +/*03d1*/ 0x180602a1U, +/*03d2*/ 0x000602a2U, +/*03d3*/ 0x081102a2U, +/*03d4*/ 0x000802a3U, +/*03d5*/ 0x080402a3U, +/*03d6*/ 0x100602a3U, +/*03d7*/ 0xffffffffU, +/*03d8*/ 0x180602a3U, +/*03d9*/ 0x000802a4U, +/*03da*/ 0xffffffffU, +/*03db*/ 0x080802a4U, +/*03dc*/ 0x100802a4U, +/*03dd*/ 0x180802a4U, +/*03de*/ 0x000602a5U, +/*03df*/ 0x080602a5U, +/*03e0*/ 0x001102a6U, +/*03e1*/ 0x180802a6U, +/*03e2*/ 0x000402a7U, +/*03e3*/ 0x080602a7U, +/*03e4*/ 0xffffffffU, +/*03e5*/ 0x100602a7U, +/*03e6*/ 0x180802a7U, +/*03e7*/ 0xffffffffU, +/*03e8*/ 0x000402a8U, +/*03e9*/ 0x080402a8U, +/*03ea*/ 0x100402a8U, +/*03eb*/ 0x180402a8U, +/*03ec*/ 0x000402a9U, +/*03ed*/ 0x080402a9U, +/*03ee*/ 0x100402a9U, +/*03ef*/ 0x180402a9U, +/*03f0*/ 0x000402aaU, +/*03f1*/ 0x080402aaU, +/*03f2*/ 0x100402aaU, +/*03f3*/ 0x180402aaU, +/*03f4*/ 0x000402abU, +/*03f5*/ 0x080402abU, +/*03f6*/ 0x100402abU, +/*03f7*/ 0x180402abU, +/*03f8*/ 0x000402acU, +/*03f9*/ 0x080402acU, +/*03fa*/ 0x100402acU, +/*03fb*/ 0x180402acU, +/*03fc*/ 0x001202adU, +/*03fd*/ 0x001102aeU, +/*03fe*/ 0x001202afU, +/*03ff*/ 0x002002b0U, +/*0400*/ 0x002002b1U, +/*0401*/ 0x002002b2U, +/*0402*/ 0x002002b3U, +/*0403*/ 0x002002b4U, +/*0404*/ 0x002002b5U, +/*0405*/ 0x002002b6U, +/*0406*/ 0x002002b7U, +/*0407*/ 0x002002b8U, +/*0408*/ 0x000202b9U, +/*0409*/ 0x080502b9U, +/*040a*/ 0x100502b9U, +/*040b*/ 0x180102b9U, +/*040c*/ 0x000402baU, +/*040d*/ 0x080402baU, +/*040e*/ 0x100402baU, +/*040f*/ 0x180402baU, +/*0410*/ 0x000402bbU, +/*0411*/ 0x080402bbU, +/*0412*/ 0x100402bbU, +/*0413*/ 0x180402bbU, +/*0414*/ 0xffffffffU, +/*0415*/ 0xffffffffU, +/*0416*/ 0xffffffffU, +/*0417*/ 0xffffffffU, +/*0418*/ 0xffffffffU, +/*0419*/ 0xffffffffU, +/*041a*/ 0x000402bcU, +/*041b*/ 0x080402bcU, +/*041c*/ 0x100402bcU, +/*041d*/ 0x180402bcU, +/*041e*/ 0x000402bdU, +/*041f*/ 0x080402bdU, +/*0420*/ 0x100402bdU, +/*0421*/ 0x180402bdU, +/*0422*/ 0x000102beU, +/*0423*/ 0x080202beU, +/*0424*/ 0x100202beU, +/*0425*/ 0x180202beU, +/*0426*/ 0x000202bfU, +/*0427*/ 0x080102bfU, +/*0428*/ 0x100402bfU, +/*0429*/ 0x001002c0U, +/*042a*/ 0x002002c1U, +/*042b*/ 0x001002c2U, +/*042c*/ 0x002002c3U, +/*042d*/ 0x001002c4U, +/*042e*/ 0x002002c5U, +/*042f*/ 0x000702c6U, +/*0430*/ 0x080102c6U, +/*0431*/ 0x100202c6U, +/*0432*/ 0x180602c6U, +/*0433*/ 0x000102c7U, +/*0434*/ 0x080102c7U, +/*0435*/ 0x002002c8U, +/*0436*/ 0x000202c9U, +/*0437*/ 0x002002caU, +/*0438*/ 0x002002cbU, +/*0439*/ 0x000c02ccU, +/*043a*/ 0x100c02ccU, +/*043b*/ 0x002002cdU, +/*043c*/ 0x000302ceU, +/*043d*/ 0x002002cfU, +/*043e*/ 0x000302d0U, +/*043f*/ 0x002002d1U, +/*0440*/ 0x000302d2U, +/*0441*/ 0x002002d3U, +/*0442*/ 0x000302d4U, +/*0443*/ 0x002002d5U, +/*0444*/ 0x000302d6U, +/*0445*/ 0x002002d7U, +/*0446*/ 0x000302d8U, +/*0447*/ 0x002002d9U, +/*0448*/ 0x000302daU, +/*0449*/ 0x002002dbU, +/*044a*/ 0x000302dcU, +/*044b*/ 0x002002ddU, +/*044c*/ 0x000302deU, +/*044d*/ 0x002002dfU, +/*044e*/ 0x000302e0U, +/*044f*/ 0x080302e0U, +/*0450*/ 0x100202e0U, +/*0451*/ 0x180202e0U, +/*0452*/ 0x002002e1U, +/*0453*/ 0x002002e2U, +/*0454*/ 0x002002e3U, +/*0455*/ 0x002002e4U, +/*0456*/ 0x000402e5U, +/*0457*/ 0x001e02e6U, +/*0458*/ 0x001e02e7U, +/*0459*/ 0x001e02e8U, +/*045a*/ 0x001e02e9U, +/*045b*/ 0x001e02eaU, +/*045c*/ 0x001e02ebU, +/*045d*/ 0x001e02ecU, +/*045e*/ 0x001e02edU, +/*045f*/ 0x000402eeU, +/*0460*/ 0xffffffffU, +/*0461*/ 0xffffffffU, +/*0462*/ 0xffffffffU, +/*0463*/ 0xffffffffU, +/*0464*/ 0x080402eeU, +/*0465*/ 0x100102eeU, +/*0466*/ 0x180802eeU, +/*0467*/ 0x000402efU, +/*0468*/ 0x080102efU, +/*0469*/ 0x100802efU, +/*046a*/ 0x180402efU, +/*046b*/ 0x000102f0U, +/*046c*/ 0x080802f0U, +/*046d*/ 0x100402f0U, +/*046e*/ 0x180102f0U, +/*046f*/ 0x000802f1U, +/*0470*/ 0x080402f1U, +/*0471*/ 0x100102f1U, +/*0472*/ 0x180802f1U, +/*0473*/ 0x000402f2U, +/*0474*/ 0x080102f2U, +/*0475*/ 0x100802f2U, +/*0476*/ 0x180402f2U, +/*0477*/ 0x000102f3U, +/*0478*/ 0x080802f3U, +/*0479*/ 0x100402f3U, +/*047a*/ 0x180102f3U, +/*047b*/ 0x000802f4U, +/*047c*/ 0x080802f4U, +/*047d*/ 0x100102f4U, +/*047e*/ 0x180502f4U, +/*047f*/ 0xffffffffU, +/*0480*/ 0xffffffffU, +/*0481*/ 0xffffffffU, +/*0482*/ 0xffffffffU, +/*0483*/ 0xffffffffU, +/*0484*/ 0xffffffffU, +/*0485*/ 0xffffffffU, +/*0486*/ 0xffffffffU, +/*0487*/ 0xffffffffU, +/*0488*/ 0xffffffffU, +/*0489*/ 0xffffffffU, +/*048a*/ 0xffffffffU, +/*048b*/ 0xffffffffU, +/*048c*/ 0xffffffffU, +/*048d*/ 0xffffffffU, +/*048e*/ 0xffffffffU, +/*048f*/ 0xffffffffU, +/*0490*/ 0xffffffffU, +/*0491*/ 0xffffffffU, +/*0492*/ 0xffffffffU, +/*0493*/ 0xffffffffU, +/*0494*/ 0xffffffffU, + }, + { +/*0000*/ 0x00200800U, +/*0001*/ 0x00040801U, +/*0002*/ 0x080b0801U, +/*0003*/ 0x000a0802U, +/*0004*/ 0x10020802U, +/*0005*/ 0x18010802U, +/*0006*/ 0x00060803U, +/*0007*/ 0x08060803U, +/*0008*/ 0x10060803U, +/*0009*/ 0x18060803U, +/*000a*/ 0x00060804U, +/*000b*/ 0x08060804U, +/*000c*/ 0x10050804U, +/*000d*/ 0x18060804U, +/*000e*/ 0x00060805U, +/*000f*/ 0x08040805U, +/*0010*/ 0x10030805U, +/*0011*/ 0x00180806U, +/*0012*/ 0x18030806U, +/*0013*/ 0x00180807U, +/*0014*/ 0x18020807U, +/*0015*/ 0x0801085eU, +/*0016*/ 0x00020808U, +/*0017*/ 0x08010808U, +/*0018*/ 0x10010808U, +/*0019*/ 0x18020808U, +/*001a*/ 0x00050809U, +/*001b*/ 0x08050809U, +/*001c*/ 0x10040809U, +/*001d*/ 0xffffffffU, +/*001e*/ 0x18040809U, +/*001f*/ 0x0002080aU, +/*0020*/ 0x0805080aU, +/*0021*/ 0x1009080aU, +/*0022*/ 0x0001080bU, +/*0023*/ 0x0020080cU, +/*0024*/ 0x001c080dU, +/*0025*/ 0x0001080eU, +/*0026*/ 0x0807080eU, +/*0027*/ 0x1009080eU, +/*0028*/ 0x000a080fU, +/*0029*/ 0x1005080fU, +/*002a*/ 0x1801080fU, +/*002b*/ 0x10010810U, +/*002c*/ 0x18020810U, +/*002d*/ 0x00090810U, +/*002e*/ 0x00090811U, +/*002f*/ 0x10020811U, +/*0030*/ 0x00200812U, +/*0031*/ 0x00010813U, +/*0032*/ 0x08020813U, +/*0033*/ 0x00200814U, +/*0034*/ 0x00200815U, +/*0035*/ 0x00200816U, +/*0036*/ 0x00200817U, +/*0037*/ 0xffffffffU, +/*0038*/ 0xffffffffU, +/*0039*/ 0xffffffffU, +/*003a*/ 0xffffffffU, +/*003b*/ 0x00030818U, +/*003c*/ 0x08010818U, +/*003d*/ 0x10040818U, +/*003e*/ 0x18030818U, +/*003f*/ 0x00040819U, +/*0040*/ 0x08040819U, +/*0041*/ 0x10040819U, +/*0042*/ 0x18040819U, +/*0043*/ 0x0001081aU, +/*0044*/ 0x0801081aU, +/*0045*/ 0x1006081aU, +/*0046*/ 0x1804081aU, +/*0047*/ 0x0008081bU, +/*0048*/ 0x0806081bU, +/*0049*/ 0x1004081bU, +/*004a*/ 0x1806081bU, +/*004b*/ 0x0004081cU, +/*004c*/ 0x0802081cU, +/*004d*/ 0x1005081cU, +/*004e*/ 0x1808081cU, +/*004f*/ 0xffffffffU, +/*0050*/ 0x0006081dU, +/*0051*/ 0x0803081dU, +/*0052*/ 0x100b081dU, +/*0053*/ 0x0004081eU, +/*0054*/ 0x0804081eU, +/*0055*/ 0x1004081eU, +/*0056*/ 0x1801081eU, +/*0057*/ 0xffffffffU, +/*0058*/ 0x0009081fU, +/*0059*/ 0x00200820U, +/*005a*/ 0x00200821U, +/*005b*/ 0x00200822U, +/*005c*/ 0x00200823U, +/*005d*/ 0x00100824U, +/*005e*/ 0xffffffffU, +/*005f*/ 0x10010824U, +/*0060*/ 0x18060824U, +/*0061*/ 0x00080825U, +/*0062*/ 0x00200826U, +/*0063*/ 0x00100827U, +/*0064*/ 0x100b0827U, +/*0065*/ 0x00070828U, +/*0066*/ 0x08070828U, +/*0067*/ 0x10090828U, +/*0068*/ 0x00090829U, +/*0069*/ 0x100b0829U, +/*006a*/ 0x0007082aU, +/*006b*/ 0x0808082aU, +/*006c*/ 0x1009082aU, +/*006d*/ 0x0003082bU, +/*006e*/ 0x080a082bU, +/*006f*/ 0x000a082cU, +/*0070*/ 0x0011082dU, +/*0071*/ 0x000a082eU, +/*0072*/ 0x100a082eU, +/*0073*/ 0x0010082fU, +/*0074*/ 0x100e082fU, +/*0075*/ 0x000e0830U, +/*0076*/ 0x00120831U, +/*0077*/ 0x000a0832U, +/*0078*/ 0x100a0832U, +/*0079*/ 0x00020833U, +/*007a*/ 0x00200834U, +/*007b*/ 0x000b0835U, +/*007c*/ 0x100b0835U, +/*007d*/ 0x00200836U, +/*007e*/ 0x00130837U, +/*007f*/ 0x00200838U, +/*0080*/ 0x00200839U, +/*0081*/ 0x0008083aU, +/*0082*/ 0x0801083aU, +/*0083*/ 0x1001083aU, +/*0084*/ 0x1801083aU, +/*0085*/ 0x0008083bU, +/*0086*/ 0x080c083bU, +/*0087*/ 0x000c083cU, +/*0088*/ 0x100c083cU, +/*0089*/ 0x000c083dU, +/*008a*/ 0x100c083dU, +/*008b*/ 0x000c083eU, +/*008c*/ 0x100c083eU, +/*008d*/ 0x000c083fU, +/*008e*/ 0x100c083fU, +/*008f*/ 0x000c0840U, +/*0090*/ 0x100c0840U, +/*0091*/ 0x000b0841U, +/*0092*/ 0x10090841U, +/*0093*/ 0x00010842U, +/*0094*/ 0x000b0843U, +/*0095*/ 0x100b0843U, +/*0096*/ 0x000b0844U, +/*0097*/ 0x100b0844U, +/*0098*/ 0x000b0845U, +/*0099*/ 0x100b0845U, +/*009a*/ 0x000b0846U, +/*009b*/ 0x100b0846U, +/*009c*/ 0x000b0847U, +/*009d*/ 0x100a0847U, +/*009e*/ 0x00020848U, +/*009f*/ 0x080a0848U, +/*00a0*/ 0x000a0849U, +/*00a1*/ 0x100a0849U, +/*00a2*/ 0x000a084aU, +/*00a3*/ 0x100a084aU, +/*00a4*/ 0x000a084bU, +/*00a5*/ 0x100a084bU, +/*00a6*/ 0x000a084cU, +/*00a7*/ 0x100a084cU, +/*00a8*/ 0x000a084dU, +/*00a9*/ 0x100a084dU, +/*00aa*/ 0x000a084eU, +/*00ab*/ 0x100a084eU, +/*00ac*/ 0x000a084fU, +/*00ad*/ 0x100a084fU, +/*00ae*/ 0x000a0850U, +/*00af*/ 0x100a0850U, +/*00b0*/ 0x000a0851U, +/*00b1*/ 0x100a0851U, +/*00b2*/ 0x000a0852U, +/*00b3*/ 0x100a0852U, +/*00b4*/ 0x000a0853U, +/*00b5*/ 0x100a0853U, +/*00b6*/ 0x000a0854U, +/*00b7*/ 0x100a0854U, +/*00b8*/ 0x000a0855U, +/*00b9*/ 0x100a0855U, +/*00ba*/ 0x000a0856U, +/*00bb*/ 0x10040856U, +/*00bc*/ 0x18030856U, +/*00bd*/ 0x000a0857U, +/*00be*/ 0x100a0857U, +/*00bf*/ 0x00010858U, +/*00c0*/ 0x080a0858U, +/*00c1*/ 0x18040858U, +/*00c2*/ 0x000b0859U, +/*00c3*/ 0x100a0859U, +/*00c4*/ 0x0003085aU, +/*00c5*/ 0x0008085bU, +/*00c6*/ 0x0808085bU, +/*00c7*/ 0x1008085bU, +/*00c8*/ 0x1808085bU, +/*00c9*/ 0x0008085cU, +/*00ca*/ 0x0808085cU, +/*00cb*/ 0x1008085cU, +/*00cc*/ 0x1801085cU, +/*00cd*/ 0x0008085dU, +/*00ce*/ 0x0808085dU, +/*00cf*/ 0x1002085dU, +/*00d0*/ 0x1802085dU, +/*00d1*/ 0x0005085eU, +/*00d2*/ 0x1005085eU, +/*00d3*/ 0x1805085eU, +/*00d4*/ 0x0004085fU, +/*00d5*/ 0x080b085fU, +/*00d6*/ 0x1806085fU, +/*00d7*/ 0x00080860U, +/*00d8*/ 0x08080860U, +/*00d9*/ 0x10040860U, +/*00da*/ 0x18040860U, +/*00db*/ 0x00060861U, +/*00dc*/ 0x08040861U, +/*00dd*/ 0x10050861U, +/*00de*/ 0x000a0862U, +/*00df*/ 0x100a0862U, +/*00e0*/ 0x00080863U, +/*00e1*/ 0x08010863U, +/*00e2*/ 0x10040863U, +/*00e3*/ 0x00020864U, +/*00e4*/ 0x08030864U, +/*00e5*/ 0x00050a00U, +/*00e6*/ 0x08050a00U, +/*00e7*/ 0x10050a00U, +/*00e8*/ 0x18050a00U, +/*00e9*/ 0x00050a01U, +/*00ea*/ 0x08050a01U, +/*00eb*/ 0x100b0a01U, +/*00ec*/ 0x00010a02U, +/*00ed*/ 0x08030a02U, +/*00ee*/ 0x00200a03U, +/*00ef*/ 0x00100a04U, +/*00f0*/ 0x10040a04U, +/*00f1*/ 0x000b0a05U, +/*00f2*/ 0x10070a05U, +/*00f3*/ 0x00090a06U, +/*00f4*/ 0x10030a06U, +/*00f5*/ 0x18030a06U, +/*00f6*/ 0x00010a07U, +/*00f7*/ 0x08010a07U, +/*00f8*/ 0x10070a07U, +/*00f9*/ 0x18070a07U, +/*00fa*/ 0x00050a08U, +/*00fb*/ 0x08010a08U, +/*00fc*/ 0x10020a08U, +/*00fd*/ 0x18030a08U, +/*00fe*/ 0x00010a09U, +/*00ff*/ 0x080f0a09U, +/*0100*/ 0x00200a0aU, +/*0101*/ 0x00200a0bU, +/*0102*/ 0x000b0a0cU, +/*0103*/ 0x100b0a0cU, +/*0104*/ 0x000b0a0dU, +/*0105*/ 0x00180a0eU, +/*0106*/ 0x00180a0fU, +/*0107*/ 0xffffffffU, +/*0108*/ 0xffffffffU, +/*0109*/ 0xffffffffU, +/*010a*/ 0xffffffffU, +/*010b*/ 0xffffffffU, +/*010c*/ 0x18020a0fU, +/*010d*/ 0x00020a10U, +/*010e*/ 0x08040a10U, +/*010f*/ 0x10040a10U, +/*0110*/ 0x18010a10U, +/*0111*/ 0x00010a11U, +/*0112*/ 0x08010a11U, +/*0113*/ 0x10030a11U, +/*0114*/ 0x00200a12U, +/*0115*/ 0x00200a13U, +/*0116*/ 0xffffffffU, +/*0117*/ 0x00140a14U, +/*0118*/ 0x00140a15U, +/*0119*/ 0x00140a16U, +/*011a*/ 0x00140a17U, +/*011b*/ 0x00140a18U, +/*011c*/ 0x00140a19U, +/*011d*/ 0x00140a1aU, +/*011e*/ 0x00140a1bU, +/*011f*/ 0x001e0a1cU, +/*0120*/ 0x000a0a1dU, +/*0121*/ 0x10060a1dU, +/*0122*/ 0x18060a1dU, +/*0123*/ 0x00060a1eU, +/*0124*/ 0x08060a1eU, +/*0125*/ 0x10060a1eU, +/*0126*/ 0x00080a1fU, +/*0127*/ 0x080b0a1fU, +/*0128*/ 0x000b0a20U, +/*0129*/ 0x100b0a20U, +/*012a*/ 0x000b0a21U, +/*012b*/ 0x100b0a21U, +/*012c*/ 0x000b0a22U, +/*012d*/ 0x10040a22U, +/*012e*/ 0x000b0a23U, +/*012f*/ 0x10060a23U, +/*0130*/ 0x18080a23U, +/*0131*/ 0x00080a24U, +/*0132*/ 0x08040a24U, +/*0133*/ 0x00020b80U, +/*0134*/ 0x00010b81U, +/*0135*/ 0x08010b81U, +/*0136*/ 0x10020b81U, +/*0137*/ 0x18050b81U, +/*0138*/ 0x00050b82U, +/*0139*/ 0x08050b82U, +/*013a*/ 0x10050b82U, +/*013b*/ 0x000b0b83U, +/*013c*/ 0x10050b83U, +/*013d*/ 0x18010b83U, +/*013e*/ 0x00010b84U, +/*013f*/ 0x08010b84U, +/*0140*/ 0x10010b84U, +/*0141*/ 0x18010b84U, +/*0142*/ 0x00040b85U, +/*0143*/ 0x080b0b85U, +/*0144*/ 0x000b0b86U, +/*0145*/ 0x100b0b86U, +/*0146*/ 0x00040b87U, +/*0147*/ 0x080b0b87U, +/*0148*/ 0x18040b87U, +/*0149*/ 0x00010b88U, +/*014a*/ 0x08010b88U, +/*014b*/ 0x10010b88U, +/*014c*/ 0x00200b89U, +/*014d*/ 0x00200b8aU, +/*014e*/ 0x00080b8bU, +/*014f*/ 0x080a0b8bU, +/*0150*/ 0x18050b8bU, +/*0151*/ 0x000b0b8cU, +/*0152*/ 0x10030b8cU, +/*0153*/ 0x18030b8cU, +/*0154*/ 0x00010b8dU, +/*0155*/ 0x08020b8dU, +/*0156*/ 0x10010b8dU, +/*0157*/ 0x18010b8dU, +/*0158*/ 0x00010b8eU, +/*0159*/ 0xffffffffU, +/*015a*/ 0x08010b8eU, +/*015b*/ 0x18040b8eU, +/*015c*/ 0x00040b8fU, +/*015d*/ 0x08040b8fU, +/*015e*/ 0x10040b8fU, +/*015f*/ 0x18010b8fU, +/*0160*/ 0x00010b90U, +/*0161*/ 0x08010b90U, +/*0162*/ 0x00200b91U, +/*0163*/ 0x00200b92U, +/*0164*/ 0x00200b93U, +/*0165*/ 0x00200b94U, +/*0166*/ 0xffffffffU, +/*0167*/ 0x10010b8eU, +/*0168*/ 0x000d0b96U, +/*0169*/ 0x100d0b96U, +/*016a*/ 0x000d0b97U, +/*016b*/ 0x00050b98U, +/*016c*/ 0x00010b99U, +/*016d*/ 0x080e0b99U, +/*016e*/ 0x000e0b9aU, +/*016f*/ 0x100e0b9aU, +/*0170*/ 0x000e0b9bU, +/*0171*/ 0x100e0b9bU, +/*0172*/ 0x00040b9cU, +/*0173*/ 0x08040b9cU, +/*0174*/ 0x10040b9cU, +/*0175*/ 0x18040b9cU, +/*0176*/ 0x00040b9dU, +/*0177*/ 0x080b0b9dU, +/*0178*/ 0x000b0b9eU, +/*0179*/ 0x100b0b9eU, +/*017a*/ 0x000b0b9fU, +/*017b*/ 0x00040ba0U, +/*017c*/ 0x08040ba0U, +/*017d*/ 0x10040ba0U, +/*017e*/ 0x18040ba0U, +/*017f*/ 0x000d0ba1U, +/*0180*/ 0x100d0ba1U, +/*0181*/ 0x000d0ba2U, +/*0182*/ 0x10100ba2U, +/*0183*/ 0x00080b95U, +/*0184*/ 0x08080b95U, +/*0185*/ 0x00100ba3U, +/*0186*/ 0x10100ba3U, +/*0187*/ 0x00100ba4U, +/*0188*/ 0x10100ba4U, +/*0189*/ 0x00100ba5U, +/*018a*/ 0x10030ba5U, +/*018b*/ 0x18040ba5U, +/*018c*/ 0x00010ba6U, +/*018d*/ 0x08080ba6U, +/*018e*/ 0x10010ba6U, +/*018f*/ 0x000a0ba7U, +/*0190*/ 0x10010ba7U, +/*0191*/ 0x00140ba8U, +/*0192*/ 0x000b0ba9U, +/*0193*/ 0x100c0ba9U, +/*0194*/ 0x00120baaU, +/*0195*/ 0x00140babU, +/*0196*/ 0x00120bacU, +/*0197*/ 0x00110badU, +/*0198*/ 0x00110baeU, +/*0199*/ 0x00120bafU, +/*019a*/ 0x00120bb0U, +/*019b*/ 0x00120bb1U, +/*019c*/ 0x00120bb2U, +/*019d*/ 0x00120bb3U, +/*019e*/ 0x00120bb4U, +/*019f*/ 0x00120bb5U, +/*01a0*/ 0x00120bb6U, +/*01a1*/ 0x00120bb7U, +/*01a2*/ 0x00120bb8U, +/*01a3*/ 0x000e0bb9U, +/*01a4*/ 0x100d0bb9U, +/*01a5*/ 0x00200bbaU, +/*01a6*/ 0x00170bbbU, +/*01a7*/ 0x000d0bbcU, +/*01a8*/ 0x10010bbcU, +/*01a9*/ 0x18010bbcU, +/*01aa*/ 0x00200bbdU, +/*01ab*/ 0x00080bbeU, +/*01ac*/ 0x08030bbeU, +/*01ad*/ 0x10030bbeU, +/*01ae*/ 0x00180bbfU, +/*01af*/ 0x00180bc0U, +/*01b0*/ 0x18070bc0U, +/*01b1*/ 0x00070bc1U, +/*01b2*/ 0x08080bc1U, +/*01b3*/ 0x10080bc1U, +/*01b4*/ 0x18080bc1U, +/*01b5*/ 0x00010bc2U, +/*01b6*/ 0x08010bc2U, +/*01b7*/ 0x00200bc3U, +/*01b8*/ 0x00070bc4U, +/*01b9*/ 0x08140bc4U, +/*01ba*/ 0x00140bc5U, +/*01bb*/ 0x00190bc6U, +/*01bc*/ 0x00170bc7U, +/*01bd*/ 0x00110bc8U, +/*01be*/ 0x00110bc9U, +/*01bf*/ 0x00100bcaU, +/*01c0*/ 0x10010bcaU, +/*01c1*/ 0x18010bcaU, +/*01c2*/ 0x00020bcbU, +/*01c3*/ 0x08040bcbU, +/*01c4*/ 0x10090bcbU, +/*01c5*/ 0x00070bccU, +/*01c6*/ 0x08040bccU, +/*01c7*/ 0x00200bcdU, +/*01c8*/ 0x00010bceU, +/*01c9*/ 0x08020bceU, +/*01ca*/ 0x10060bceU, +/*01cb*/ 0x00100bcfU, +/*01cc*/ 0x10010bcfU, +/*01cd*/ 0x00200bd0U, +/*01ce*/ 0x00080bd1U, +/*01cf*/ 0x08010bd1U, +/*01d0*/ 0x10050bd1U, +/*01d1*/ 0x18030bd1U, +/*01d2*/ 0x00020bd2U, +/*01d3*/ 0xffffffffU, +/*01d4*/ 0x00200bd3U, +/*01d5*/ 0x000b0bd4U, +/*01d6*/ 0xffffffffU, +/*01d7*/ 0x10030bd4U, +/*01d8*/ 0x18080bd4U, +/*01d9*/ 0x00020bd5U, +/*01da*/ 0x080c0bd5U, +/*01db*/ 0x18040bd5U, +/*01dc*/ 0x00010bd6U, +/*01dd*/ 0x08050bd6U, +/*01de*/ 0x00010200U, +/*01df*/ 0x08040200U, +/*01e0*/ 0x10100200U, +/*01e1*/ 0x00010201U, +/*01e2*/ 0x08010201U, +/*01e3*/ 0x10010201U, +/*01e4*/ 0x18010201U, +/*01e5*/ 0x00100202U, +/*01e6*/ 0x10080202U, +/*01e7*/ 0x18010202U, +/*01e8*/ 0x00200203U, +/*01e9*/ 0x00200204U, +/*01ea*/ 0x00200205U, +/*01eb*/ 0x00200206U, +/*01ec*/ 0x00020207U, +/*01ed*/ 0x08010207U, +/*01ee*/ 0x10010207U, +/*01ef*/ 0x00200208U, +/*01f0*/ 0x00140209U, +/*01f1*/ 0x0020020aU, +/*01f2*/ 0x0014020bU, +/*01f3*/ 0x0020020cU, +/*01f4*/ 0x0014020dU, +/*01f5*/ 0x0014020eU, +/*01f6*/ 0x0020020fU, +/*01f7*/ 0x00200210U, +/*01f8*/ 0x00200211U, +/*01f9*/ 0x00200212U, +/*01fa*/ 0x00140213U, +/*01fb*/ 0x00200214U, +/*01fc*/ 0x00200215U, +/*01fd*/ 0x00200216U, +/*01fe*/ 0x00200217U, +/*01ff*/ 0x00140218U, +/*0200*/ 0x00200219U, +/*0201*/ 0x0020021aU, +/*0202*/ 0x0020021bU, +/*0203*/ 0x0020021cU, +/*0204*/ 0x0009021dU, +/*0205*/ 0x1001021dU, +/*0206*/ 0x0020021eU, +/*0207*/ 0x0005021fU, +/*0208*/ 0x0801021fU, +/*0209*/ 0x1008021fU, +/*020a*/ 0x1808021fU, +/*020b*/ 0x001e0220U, +/*020c*/ 0x001e0221U, +/*020d*/ 0x001e0222U, +/*020e*/ 0x001e0223U, +/*020f*/ 0x001e0224U, +/*0210*/ 0x001e0225U, +/*0211*/ 0x001e0226U, +/*0212*/ 0x001e0227U, +/*0213*/ 0x001e0228U, +/*0214*/ 0x001e0229U, +/*0215*/ 0x001e022aU, +/*0216*/ 0x001e022bU, +/*0217*/ 0x001e022cU, +/*0218*/ 0x001e022dU, +/*0219*/ 0x001e022eU, +/*021a*/ 0x001e022fU, +/*021b*/ 0x00010230U, +/*021c*/ 0x08010230U, +/*021d*/ 0x10010230U, +/*021e*/ 0x18040230U, +/*021f*/ 0x00080231U, +/*0220*/ 0x08080231U, +/*0221*/ 0x10080231U, +/*0222*/ 0x18040231U, +/*0223*/ 0x00070232U, +/*0224*/ 0x08060232U, +/*0225*/ 0x10070232U, +/*0226*/ 0x18070232U, +/*0227*/ 0x00060233U, +/*0228*/ 0x08070233U, +/*0229*/ 0x10070233U, +/*022a*/ 0x18060233U, +/*022b*/ 0x00070234U, +/*022c*/ 0x08020234U, +/*022d*/ 0x10010234U, +/*022e*/ 0x18010234U, +/*022f*/ 0x000a0235U, +/*0230*/ 0x00140236U, +/*0231*/ 0x000a0237U, +/*0232*/ 0x00140238U, +/*0233*/ 0x000a0239U, +/*0234*/ 0x0014023aU, +/*0235*/ 0xffffffffU, +/*0236*/ 0xffffffffU, +/*0237*/ 0x0005023bU, +/*0238*/ 0x0001023cU, +/*0239*/ 0x1001023cU, +/*023a*/ 0x1801023cU, +/*023b*/ 0x0001023dU, +/*023c*/ 0x0801023dU, +/*023d*/ 0x1001023dU, +/*023e*/ 0x1801023dU, +/*023f*/ 0x0002023eU, +/*0240*/ 0x0802023eU, +/*0241*/ 0x1002023eU, +/*0242*/ 0x1802023eU, +/*0243*/ 0x0002023fU, +/*0244*/ 0x0803023fU, +/*0245*/ 0x1001023fU, +/*0246*/ 0x1801023fU, +/*0247*/ 0x00010240U, +/*0248*/ 0x08010240U, +/*0249*/ 0x10010240U, +/*024a*/ 0x18020240U, +/*024b*/ 0x00010241U, +/*024c*/ 0x08010241U, +/*024d*/ 0x10010241U, +/*024e*/ 0x18020241U, +/*024f*/ 0x00010242U, +/*0250*/ 0x08010242U, +/*0251*/ 0x10010242U, +/*0252*/ 0x18020242U, +/*0253*/ 0x00010243U, +/*0254*/ 0x08010243U, +/*0255*/ 0x10010243U, +/*0256*/ 0x18020243U, +/*0257*/ 0xffffffffU, +/*0258*/ 0x00010244U, +/*0259*/ 0x08010244U, +/*025a*/ 0x10010244U, +/*025b*/ 0x18010244U, +/*025c*/ 0x00010245U, +/*025d*/ 0x08010245U, +/*025e*/ 0x10010245U, +/*025f*/ 0x18010245U, +/*0260*/ 0x00040246U, +/*0261*/ 0x08040246U, +/*0262*/ 0x10040246U, +/*0263*/ 0x18010246U, +/*0264*/ 0x00020247U, +/*0265*/ 0x08060247U, +/*0266*/ 0x10060247U, +/*0267*/ 0x18020247U, +/*0268*/ 0x00020248U, +/*0269*/ 0x08020248U, +/*026a*/ 0xffffffffU, +/*026b*/ 0x10100248U, +/*026c*/ 0x00010249U, +/*026d*/ 0x08010249U, +/*026e*/ 0x10010249U, +/*026f*/ 0x18040249U, +/*0270*/ 0x0001024aU, +/*0271*/ 0x0804024aU, +/*0272*/ 0x1003024aU, +/*0273*/ 0x1808024aU, +/*0274*/ 0x000a024bU, +/*0275*/ 0x100a024bU, +/*0276*/ 0x000a024cU, +/*0277*/ 0xffffffffU, +/*0278*/ 0x0020024dU, +/*0279*/ 0x0020024eU, +/*027a*/ 0x0005024fU, +/*027b*/ 0x1801023aU, +/*027c*/ 0x0805023cU, +/*027d*/ 0x0808024fU, +/*027e*/ 0x1001024fU, +/*027f*/ 0x1808024fU, +/*0280*/ 0x00010250U, +/*0281*/ 0x08080250U, +/*0282*/ 0x10010250U, +/*0283*/ 0x18040250U, +/*0284*/ 0x00040251U, +/*0285*/ 0x08040251U, +/*0286*/ 0x10040251U, +/*0287*/ 0x18040251U, +/*0288*/ 0x00040252U, +/*0289*/ 0x08040252U, +/*028a*/ 0x10040252U, +/*028b*/ 0x18040252U, +/*028c*/ 0x00040253U, +/*028d*/ 0x08010253U, +/*028e*/ 0x10040253U, +/*028f*/ 0x18040253U, +/*0290*/ 0x00040254U, +/*0291*/ 0x08040254U, +/*0292*/ 0x10040254U, +/*0293*/ 0x18040254U, +/*0294*/ 0x00060255U, +/*0295*/ 0x08060255U, +/*0296*/ 0x10060255U, +/*0297*/ 0x18060255U, +/*0298*/ 0x00060256U, +/*0299*/ 0x08060256U, +/*029a*/ 0x10040256U, +/*029b*/ 0x18010256U, +/*029c*/ 0x00010257U, +/*029d*/ 0x08020257U, +/*029e*/ 0x00200258U, +/*029f*/ 0x00200259U, +/*02a0*/ 0x0020025aU, +/*02a1*/ 0x0020025bU, +/*02a2*/ 0x0020025cU, +/*02a3*/ 0x0020025dU, +/*02a4*/ 0x0020025eU, +/*02a5*/ 0x0020025fU, +/*02a6*/ 0x00040260U, +/*02a7*/ 0x08040260U, +/*02a8*/ 0x10010260U, +/*02a9*/ 0x18010260U, +/*02aa*/ 0x00010261U, +/*02ab*/ 0x08010261U, +/*02ac*/ 0x10010261U, +/*02ad*/ 0x18010261U, +/*02ae*/ 0x00010262U, +/*02af*/ 0x08010262U, +/*02b0*/ 0x10010262U, +/*02b1*/ 0x18040262U, +/*02b2*/ 0x00040263U, +/*02b3*/ 0x080a0263U, +/*02b4*/ 0x00200264U, +/*02b5*/ 0x00040265U, +/*02b6*/ 0x08080265U, +/*02b7*/ 0x10020265U, +/*02b8*/ 0x18020265U, +/*02b9*/ 0x00020266U, +/*02ba*/ 0x08020266U, +/*02bb*/ 0x10020266U, +/*02bc*/ 0x18020266U, +/*02bd*/ 0xffffffffU, +/*02be*/ 0xffffffffU, +/*02bf*/ 0x00200267U, +/*02c0*/ 0x00030268U, +/*02c1*/ 0x08100268U, +/*02c2*/ 0x00100269U, +/*02c3*/ 0x10040269U, +/*02c4*/ 0x18040269U, +/*02c5*/ 0x0005026aU, +/*02c6*/ 0x0805026aU, +/*02c7*/ 0xffffffffU, +/*02c8*/ 0xffffffffU, +/*02c9*/ 0xffffffffU, +/*02ca*/ 0xffffffffU, +/*02cb*/ 0x1001026aU, +/*02cc*/ 0x1801026aU, +/*02cd*/ 0x0008026bU, +/*02ce*/ 0x0808026bU, +/*02cf*/ 0x1008026bU, +/*02d0*/ 0x1808026bU, +/*02d1*/ 0x0008026cU, +/*02d2*/ 0x0808026cU, +/*02d3*/ 0x1008026cU, +/*02d4*/ 0x1808026cU, +/*02d5*/ 0x0008026dU, +/*02d6*/ 0x0808026dU, +/*02d7*/ 0x1008026dU, +/*02d8*/ 0x1808026dU, +/*02d9*/ 0x0008026eU, +/*02da*/ 0x0808026eU, +/*02db*/ 0x1003026eU, +/*02dc*/ 0x1803026eU, +/*02dd*/ 0x0003026fU, +/*02de*/ 0xffffffffU, +/*02df*/ 0x0801026fU, +/*02e0*/ 0x1002026fU, +/*02e1*/ 0x1801026fU, +/*02e2*/ 0x00040270U, +/*02e3*/ 0x08020270U, +/*02e4*/ 0x10010270U, +/*02e5*/ 0x18010270U, +/*02e6*/ 0x00010271U, +/*02e7*/ 0x08010271U, +/*02e8*/ 0x10040271U, +/*02e9*/ 0x18080271U, +/*02ea*/ 0x000a0272U, +/*02eb*/ 0x100a0272U, +/*02ec*/ 0x000a0273U, +/*02ed*/ 0x100a0273U, +/*02ee*/ 0x000a0274U, +/*02ef*/ 0x100a0274U, +/*02f0*/ 0x00200275U, +/*02f1*/ 0x00200276U, +/*02f2*/ 0x00010277U, +/*02f3*/ 0x08020277U, +/*02f4*/ 0x10020277U, +/*02f5*/ 0x18020277U, +/*02f6*/ 0xffffffffU, +/*02f7*/ 0x00020278U, +/*02f8*/ 0x08100278U, +/*02f9*/ 0x18050278U, +/*02fa*/ 0x00060279U, +/*02fb*/ 0x08050279U, +/*02fc*/ 0x10050279U, +/*02fd*/ 0x000e027aU, +/*02fe*/ 0x1005027aU, +/*02ff*/ 0x000e027bU, +/*0300*/ 0x1005027bU, +/*0301*/ 0x000e027cU, +/*0302*/ 0x1005027cU, +/*0303*/ 0x1801027cU, +/*0304*/ 0x0005027dU, +/*0305*/ 0x0805027dU, +/*0306*/ 0x100a027dU, +/*0307*/ 0x000a027eU, +/*0308*/ 0x1005027eU, +/*0309*/ 0x1805027eU, +/*030a*/ 0x000a027fU, +/*030b*/ 0x100a027fU, +/*030c*/ 0x00050280U, +/*030d*/ 0x08050280U, +/*030e*/ 0x100a0280U, +/*030f*/ 0x000a0281U, +/*0310*/ 0x10070281U, +/*0311*/ 0x18070281U, +/*0312*/ 0x00070282U, +/*0313*/ 0x08070282U, +/*0314*/ 0x10070282U, +/*0315*/ 0x18070282U, +/*0316*/ 0xffffffffU, +/*0317*/ 0xffffffffU, +/*0318*/ 0x00040283U, +/*0319*/ 0x08040283U, +/*031a*/ 0x10040283U, +/*031b*/ 0x18040283U, +/*031c*/ 0x00040284U, +/*031d*/ 0xffffffffU, +/*031e*/ 0x08080284U, +/*031f*/ 0x10080284U, +/*0320*/ 0x18040284U, +/*0321*/ 0x00050285U, +/*0322*/ 0x08080285U, +/*0323*/ 0x10050285U, +/*0324*/ 0x18040285U, +/*0325*/ 0x00050286U, +/*0326*/ 0x08080286U, +/*0327*/ 0x10050286U, +/*0328*/ 0x18040286U, +/*0329*/ 0x00050287U, +/*032a*/ 0x08080287U, +/*032b*/ 0x10050287U, +/*032c*/ 0x18040287U, +/*032d*/ 0x00050288U, +/*032e*/ 0x08070288U, +/*032f*/ 0x10080288U, +/*0330*/ 0x00100289U, +/*0331*/ 0x10080289U, +/*0332*/ 0x0010028aU, +/*0333*/ 0x1008028aU, +/*0334*/ 0x0010028bU, +/*0335*/ 0x1008028bU, +/*0336*/ 0x1808028bU, +/*0337*/ 0x0001028cU, +/*0338*/ 0x0801028cU, +/*0339*/ 0x1006028cU, +/*033a*/ 0x1806028cU, +/*033b*/ 0x0006028dU, +/*033c*/ 0x0801028dU, +/*033d*/ 0x1001028dU, +/*033e*/ 0x1803028dU, +/*033f*/ 0x000a028eU, +/*0340*/ 0x100a028eU, +/*0341*/ 0x000a028fU, +/*0342*/ 0xffffffffU, +/*0343*/ 0x100a028fU, +/*0344*/ 0x00040290U, +/*0345*/ 0x08010290U, +/*0346*/ 0x10040290U, +/*0347*/ 0x18070290U, +/*0348*/ 0x00070291U, +/*0349*/ 0x08070291U, +/*034a*/ 0x10070291U, +/*034b*/ 0x18070291U, +/*034c*/ 0x00070292U, +/*034d*/ 0xffffffffU, +/*034e*/ 0xffffffffU, +/*034f*/ 0x08050292U, +/*0350*/ 0x10050292U, +/*0351*/ 0x18040292U, +/*0352*/ 0x00040293U, +/*0353*/ 0x08040293U, +/*0354*/ 0xffffffffU, +/*0355*/ 0x10010293U, +/*0356*/ 0x18010293U, +/*0357*/ 0x00020294U, +/*0358*/ 0x08080294U, +/*0359*/ 0x00200295U, +/*035a*/ 0x00200296U, +/*035b*/ 0x00100297U, +/*035c*/ 0x10020297U, +/*035d*/ 0x18020297U, +/*035e*/ 0x00020298U, +/*035f*/ 0xffffffffU, +/*0360*/ 0x08010298U, +/*0361*/ 0x10010298U, +/*0362*/ 0x18020298U, +/*0363*/ 0x00100299U, +/*0364*/ 0x10100299U, +/*0365*/ 0x0010029aU, +/*0366*/ 0x1008029aU, +/*0367*/ 0x1808029aU, +/*0368*/ 0x0008029bU, +/*0369*/ 0x0808029bU, +/*036a*/ 0x1010029bU, +/*036b*/ 0x0010029cU, +/*036c*/ 0x1010029cU, +/*036d*/ 0x0008029dU, +/*036e*/ 0x0808029dU, +/*036f*/ 0x1008029dU, +/*0370*/ 0x1808029dU, +/*0371*/ 0x0010029eU, +/*0372*/ 0x1010029eU, +/*0373*/ 0x0010029fU, +/*0374*/ 0x1008029fU, +/*0375*/ 0x1808029fU, +/*0376*/ 0x000802a0U, +/*0377*/ 0x080802a0U, +/*0378*/ 0x100802a0U, +/*0379*/ 0x001002a1U, +/*037a*/ 0x101002a1U, +/*037b*/ 0x001002a2U, +/*037c*/ 0x100802a2U, +/*037d*/ 0x180802a2U, +/*037e*/ 0x000802a3U, +/*037f*/ 0x080802a3U, +/*0380*/ 0x101002a3U, +/*0381*/ 0x001002a4U, +/*0382*/ 0x101002a4U, +/*0383*/ 0x000802a5U, +/*0384*/ 0x080802a5U, +/*0385*/ 0x100802a5U, +/*0386*/ 0x180802a5U, +/*0387*/ 0x001002a6U, +/*0388*/ 0x101002a6U, +/*0389*/ 0x001002a7U, +/*038a*/ 0x100802a7U, +/*038b*/ 0x180802a7U, +/*038c*/ 0x000802a8U, +/*038d*/ 0x080802a8U, +/*038e*/ 0x100802a8U, +/*038f*/ 0x001002a9U, +/*0390*/ 0x101002a9U, +/*0391*/ 0x001002aaU, +/*0392*/ 0x100802aaU, +/*0393*/ 0x180802aaU, +/*0394*/ 0x000802abU, +/*0395*/ 0x080802abU, +/*0396*/ 0x101002abU, +/*0397*/ 0x001002acU, +/*0398*/ 0x101002acU, +/*0399*/ 0x000802adU, +/*039a*/ 0x080802adU, +/*039b*/ 0x100802adU, +/*039c*/ 0x180802adU, +/*039d*/ 0x001002aeU, +/*039e*/ 0x101002aeU, +/*039f*/ 0x001002afU, +/*03a0*/ 0x100802afU, +/*03a1*/ 0x180802afU, +/*03a2*/ 0x000802b0U, +/*03a3*/ 0x080802b0U, +/*03a4*/ 0x100802b0U, +/*03a5*/ 0x001002b1U, +/*03a6*/ 0x101002b1U, +/*03a7*/ 0x001002b2U, +/*03a8*/ 0x100802b2U, +/*03a9*/ 0x180802b2U, +/*03aa*/ 0x000802b3U, +/*03ab*/ 0x080802b3U, +/*03ac*/ 0x101002b3U, +/*03ad*/ 0x001002b4U, +/*03ae*/ 0x101002b4U, +/*03af*/ 0x000802b5U, +/*03b0*/ 0x080802b5U, +/*03b1*/ 0x100802b5U, +/*03b2*/ 0x180802b5U, +/*03b3*/ 0x001002b6U, +/*03b4*/ 0x101002b6U, +/*03b5*/ 0x001002b7U, +/*03b6*/ 0x100802b7U, +/*03b7*/ 0x180802b7U, +/*03b8*/ 0x000802b8U, +/*03b9*/ 0x080802b8U, +/*03ba*/ 0x100802b8U, +/*03bb*/ 0x180202b8U, +/*03bc*/ 0x000302b9U, +/*03bd*/ 0x080a02b9U, +/*03be*/ 0x000a02baU, +/*03bf*/ 0x100a02baU, +/*03c0*/ 0x000502bbU, +/*03c1*/ 0x080802bbU, +/*03c2*/ 0x100802bbU, +/*03c3*/ 0x180802bbU, +/*03c4*/ 0x000602bcU, +/*03c5*/ 0x080602bcU, +/*03c6*/ 0x001102bdU, +/*03c7*/ 0x180802bdU, +/*03c8*/ 0x000402beU, +/*03c9*/ 0x080602beU, +/*03ca*/ 0x100802beU, +/*03cb*/ 0x180802beU, +/*03cc*/ 0x000802bfU, +/*03cd*/ 0x080802bfU, +/*03ce*/ 0x100802bfU, +/*03cf*/ 0x180802bfU, +/*03d0*/ 0x000802c0U, +/*03d1*/ 0x080602c0U, +/*03d2*/ 0x100602c0U, +/*03d3*/ 0x001102c1U, +/*03d4*/ 0x180802c1U, +/*03d5*/ 0x000402c2U, +/*03d6*/ 0x080602c2U, +/*03d7*/ 0x100802c2U, +/*03d8*/ 0x180802c2U, +/*03d9*/ 0x000802c3U, +/*03da*/ 0x080802c3U, +/*03db*/ 0x100802c3U, +/*03dc*/ 0x180802c3U, +/*03dd*/ 0x000802c4U, +/*03de*/ 0x080602c4U, +/*03df*/ 0x100602c4U, +/*03e0*/ 0x001102c5U, +/*03e1*/ 0x180802c5U, +/*03e2*/ 0x000402c6U, +/*03e3*/ 0x080602c6U, +/*03e4*/ 0x100802c6U, +/*03e5*/ 0x180802c6U, +/*03e6*/ 0x000802c7U, +/*03e7*/ 0x080802c7U, +/*03e8*/ 0x100402c7U, +/*03e9*/ 0x180402c7U, +/*03ea*/ 0x000402c8U, +/*03eb*/ 0x080402c8U, +/*03ec*/ 0x100402c8U, +/*03ed*/ 0x180402c8U, +/*03ee*/ 0x000402c9U, +/*03ef*/ 0x080402c9U, +/*03f0*/ 0x100402c9U, +/*03f1*/ 0x180402c9U, +/*03f2*/ 0x000402caU, +/*03f3*/ 0x080402caU, +/*03f4*/ 0x100402caU, +/*03f5*/ 0x180402caU, +/*03f6*/ 0x000402cbU, +/*03f7*/ 0x080402cbU, +/*03f8*/ 0x100402cbU, +/*03f9*/ 0x180402cbU, +/*03fa*/ 0x000402ccU, +/*03fb*/ 0x080402ccU, +/*03fc*/ 0x001702cdU, +/*03fd*/ 0x001602ceU, +/*03fe*/ 0x001702cfU, +/*03ff*/ 0x002002d0U, +/*0400*/ 0x002002d1U, +/*0401*/ 0x002002d2U, +/*0402*/ 0x002002d3U, +/*0403*/ 0x002002d4U, +/*0404*/ 0x002002d5U, +/*0405*/ 0x002002d6U, +/*0406*/ 0x002002d7U, +/*0407*/ 0x002002d8U, +/*0408*/ 0x000202d9U, +/*0409*/ 0x080502d9U, +/*040a*/ 0x100502d9U, +/*040b*/ 0x180102d9U, +/*040c*/ 0x000502daU, +/*040d*/ 0x080502daU, +/*040e*/ 0x100502daU, +/*040f*/ 0x180502daU, +/*0410*/ 0x000502dbU, +/*0411*/ 0x080502dbU, +/*0412*/ 0x100502dbU, +/*0413*/ 0x180502dbU, +/*0414*/ 0x000502dcU, +/*0415*/ 0x080502dcU, +/*0416*/ 0x100502dcU, +/*0417*/ 0x180502dcU, +/*0418*/ 0x000502ddU, +/*0419*/ 0x080502ddU, +/*041a*/ 0x100502ddU, +/*041b*/ 0x180502ddU, +/*041c*/ 0x000502deU, +/*041d*/ 0x080502deU, +/*041e*/ 0x100502deU, +/*041f*/ 0x180502deU, +/*0420*/ 0x000502dfU, +/*0421*/ 0x080502dfU, +/*0422*/ 0x100102dfU, +/*0423*/ 0x180202dfU, +/*0424*/ 0x000202e0U, +/*0425*/ 0x080202e0U, +/*0426*/ 0x100202e0U, +/*0427*/ 0x180102e0U, +/*0428*/ 0x000802e1U, +/*0429*/ 0x081502e1U, +/*042a*/ 0x002002e2U, +/*042b*/ 0x001502e3U, +/*042c*/ 0x002002e4U, +/*042d*/ 0x001502e5U, +/*042e*/ 0x002002e6U, +/*042f*/ 0x000702e7U, +/*0430*/ 0x080102e7U, +/*0431*/ 0x100202e7U, +/*0432*/ 0x180602e7U, +/*0433*/ 0x000102e8U, +/*0434*/ 0x080102e8U, +/*0435*/ 0x002002e9U, +/*0436*/ 0x000202eaU, +/*0437*/ 0x002002ebU, +/*0438*/ 0x002002ecU, +/*0439*/ 0x000c02edU, +/*043a*/ 0x100c02edU, +/*043b*/ 0x002002eeU, +/*043c*/ 0x000302efU, +/*043d*/ 0x002002f0U, +/*043e*/ 0x000302f1U, +/*043f*/ 0x002002f2U, +/*0440*/ 0x000302f3U, +/*0441*/ 0x002002f4U, +/*0442*/ 0x000302f5U, +/*0443*/ 0x002002f6U, +/*0444*/ 0x000302f7U, +/*0445*/ 0x002002f8U, +/*0446*/ 0x000302f9U, +/*0447*/ 0x002002faU, +/*0448*/ 0x000302fbU, +/*0449*/ 0x002002fcU, +/*044a*/ 0x000302fdU, +/*044b*/ 0x002002feU, +/*044c*/ 0x000302ffU, +/*044d*/ 0x00200300U, +/*044e*/ 0x00030301U, +/*044f*/ 0x08030301U, +/*0450*/ 0x10020301U, +/*0451*/ 0x18020301U, +/*0452*/ 0x00200302U, +/*0453*/ 0x00200303U, +/*0454*/ 0x00200304U, +/*0455*/ 0x00200305U, +/*0456*/ 0x00040306U, +/*0457*/ 0x001e0307U, +/*0458*/ 0x001e0308U, +/*0459*/ 0x001e0309U, +/*045a*/ 0x001e030aU, +/*045b*/ 0x001e030bU, +/*045c*/ 0x001e030cU, +/*045d*/ 0x001e030dU, +/*045e*/ 0x001e030eU, +/*045f*/ 0x0004030fU, +/*0460*/ 0x0801030fU, +/*0461*/ 0x1010030fU, +/*0462*/ 0x00100310U, +/*0463*/ 0x10100310U, +/*0464*/ 0x00040311U, +/*0465*/ 0x08010311U, +/*0466*/ 0x10080311U, +/*0467*/ 0x18040311U, +/*0468*/ 0x00010312U, +/*0469*/ 0x08080312U, +/*046a*/ 0x10040312U, +/*046b*/ 0x18010312U, +/*046c*/ 0x00080313U, +/*046d*/ 0x08040313U, +/*046e*/ 0x10010313U, +/*046f*/ 0x18080313U, +/*0470*/ 0x00040314U, +/*0471*/ 0x08010314U, +/*0472*/ 0x10080314U, +/*0473*/ 0x18040314U, +/*0474*/ 0x00010315U, +/*0475*/ 0x08080315U, +/*0476*/ 0x10040315U, +/*0477*/ 0x18010315U, +/*0478*/ 0x00080316U, +/*0479*/ 0x08040316U, +/*047a*/ 0x10010316U, +/*047b*/ 0x18080316U, +/*047c*/ 0x00080317U, +/*047d*/ 0x00010318U, +/*047e*/ 0x08050318U, +/*047f*/ 0x10010318U, +/*0480*/ 0x18020318U, +/*0481*/ 0x00010319U, +/*0482*/ 0x08010319U, +/*0483*/ 0x10010319U, +/*0484*/ 0x18010319U, +/*0485*/ 0x0001031aU, +/*0486*/ 0x0801031aU, +/*0487*/ 0x1001031aU, +/*0488*/ 0x1801031aU, +/*0489*/ 0x0001031bU, +/*048a*/ 0x0801031bU, +/*048b*/ 0x1001031bU, +/*048c*/ 0x1801031bU, +/*048d*/ 0x0001031cU, +/*048e*/ 0x0801031cU, +/*048f*/ 0x1001031cU, +/*0490*/ 0x1801031cU, +/*0491*/ 0x0008031dU, +/*0492*/ 0x0808031dU, +/*0493*/ 0x1008031dU, +/*0494*/ 0x1808031dU, + } +}; diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h new file mode 100644 index 000000000..357f8bad0 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h @@ -0,0 +1,441 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define DDR_PHY_SLICE_REGSET_OFS_H3 0x0400 +#define DDR_PHY_ADR_V_REGSET_OFS_H3 0x0600 +#define DDR_PHY_ADR_I_REGSET_OFS_H3 0x0680 +#define DDR_PHY_ADR_G_REGSET_OFS_H3 0x0700 +#define DDR_PI_REGSET_OFS_H3 0x0200 + +#define DDR_PHY_SLICE_REGSET_SIZE_H3 0x80 +#define DDR_PHY_ADR_V_REGSET_SIZE_H3 0x80 +#define DDR_PHY_ADR_I_REGSET_SIZE_H3 0x80 +#define DDR_PHY_ADR_G_REGSET_SIZE_H3 0x80 +#define DDR_PI_REGSET_SIZE_H3 0x100 + +#define DDR_PHY_SLICE_REGSET_NUM_H3 88 +#define DDR_PHY_ADR_V_REGSET_NUM_H3 37 +#define DDR_PHY_ADR_I_REGSET_NUM_H3 37 +#define DDR_PHY_ADR_G_REGSET_NUM_H3 59 +#define DDR_PI_REGSET_NUM_H3 181 + +static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = { + /*0400*/ 0x000004f0, + /*0401*/ 0x00000000, + /*0402*/ 0x00000000, + /*0403*/ 0x00000100, + /*0404*/ 0x01003c0c, + /*0405*/ 0x02003c0c, + /*0406*/ 0x00010300, + /*0407*/ 0x04000100, + /*0408*/ 0x00000300, + /*0409*/ 0x000700c0, + /*040a*/ 0x00b00201, + /*040b*/ 0x00000020, + /*040c*/ 0x00000000, + /*040d*/ 0x00000000, + /*040e*/ 0x00000000, + /*040f*/ 0x00000000, + /*0410*/ 0x00000000, + /*0411*/ 0x00000000, + /*0412*/ 0x00000000, + /*0413*/ 0x09000000, + /*0414*/ 0x04080000, + /*0415*/ 0x04080400, + /*0416*/ 0x00000000, + /*0417*/ 0x32103210, + /*0418*/ 0x00800708, + /*0419*/ 0x000f000c, + /*041a*/ 0x00000100, + /*041b*/ 0x55aa55aa, + /*041c*/ 0x33cc33cc, + /*041d*/ 0x0ff00ff0, + /*041e*/ 0x0f0ff0f0, + /*041f*/ 0x00008e38, + /*0420*/ 0x76543210, + /*0421*/ 0x00000001, + /*0422*/ 0x00000000, + /*0423*/ 0x00000000, + /*0424*/ 0x00000000, + /*0425*/ 0x00000000, + /*0426*/ 0x00000000, + /*0427*/ 0x00000000, + /*0428*/ 0x00000000, + /*0429*/ 0x00000000, + /*042a*/ 0x00000000, + /*042b*/ 0x00000000, + /*042c*/ 0x00000000, + /*042d*/ 0x00000000, + /*042e*/ 0x00000000, + /*042f*/ 0x00000000, + /*0430*/ 0x00000000, + /*0431*/ 0x00000000, + /*0432*/ 0x00000000, + /*0433*/ 0x00200000, + /*0434*/ 0x08200820, + /*0435*/ 0x08200820, + /*0436*/ 0x08200820, + /*0437*/ 0x08200820, + /*0438*/ 0x08200820, + /*0439*/ 0x00000820, + /*043a*/ 0x03000300, + /*043b*/ 0x03000300, + /*043c*/ 0x03000300, + /*043d*/ 0x03000300, + /*043e*/ 0x00000300, + /*043f*/ 0x00000000, + /*0440*/ 0x00000000, + /*0441*/ 0x00000000, + /*0442*/ 0x00000000, + /*0443*/ 0x00a000a0, + /*0444*/ 0x00a000a0, + /*0445*/ 0x00a000a0, + /*0446*/ 0x00a000a0, + /*0447*/ 0x00a000a0, + /*0448*/ 0x00a000a0, + /*0449*/ 0x00a000a0, + /*044a*/ 0x00a000a0, + /*044b*/ 0x00a000a0, + /*044c*/ 0x01040109, + /*044d*/ 0x00000200, + /*044e*/ 0x01000000, + /*044f*/ 0x00000200, + /*0450*/ 0x4041a151, + /*0451*/ 0xc00141a0, + /*0452*/ 0x0e0100c0, + /*0453*/ 0x0010000c, + /*0454*/ 0x0c064208, + /*0455*/ 0x000f0c18, + /*0456*/ 0x00e00140, + /*0457*/ 0x00000c20 +}; + +static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = { + /*0600*/ 0x00000000, + /*0601*/ 0x00000000, + /*0602*/ 0x00000000, + /*0603*/ 0x00000000, + /*0604*/ 0x00000000, + /*0605*/ 0x00000000, + /*0606*/ 0x00000002, + /*0607*/ 0x00000000, + /*0608*/ 0x00000000, + /*0609*/ 0x00000000, + /*060a*/ 0x00400320, + /*060b*/ 0x00000040, + /*060c*/ 0x00dcba98, + /*060d*/ 0x00000000, + /*060e*/ 0x00dcba98, + /*060f*/ 0x01000000, + /*0610*/ 0x00020003, + /*0611*/ 0x00000000, + /*0612*/ 0x00000000, + /*0613*/ 0x00000000, + /*0614*/ 0x00002a01, + /*0615*/ 0x00000015, + /*0616*/ 0x00000015, + /*0617*/ 0x0000002a, + /*0618*/ 0x00000033, + /*0619*/ 0x0000000c, + /*061a*/ 0x0000000c, + /*061b*/ 0x00000033, + /*061c*/ 0x00418820, + /*061d*/ 0x003f0000, + /*061e*/ 0x0000003f, + /*061f*/ 0x0002006e, + /*0620*/ 0x02000200, + /*0621*/ 0x02000200, + /*0622*/ 0x00000200, + /*0623*/ 0x42080010, + /*0624*/ 0x00000003 +}; + +static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = { + /*0680*/ 0x04040404, + /*0681*/ 0x00000404, + /*0682*/ 0x00000000, + /*0683*/ 0x00000000, + /*0684*/ 0x00000000, + /*0685*/ 0x00000000, + /*0686*/ 0x00000002, + /*0687*/ 0x00000000, + /*0688*/ 0x00000000, + /*0689*/ 0x00000000, + /*068a*/ 0x00400320, + /*068b*/ 0x00000040, + /*068c*/ 0x00000000, + /*068d*/ 0x00000000, + /*068e*/ 0x00000000, + /*068f*/ 0x01000000, + /*0690*/ 0x00020003, + /*0691*/ 0x00000000, + /*0692*/ 0x00000000, + /*0693*/ 0x00000000, + /*0694*/ 0x00002a01, + /*0695*/ 0x00000015, + /*0696*/ 0x00000015, + /*0697*/ 0x0000002a, + /*0698*/ 0x00000033, + /*0699*/ 0x0000000c, + /*069a*/ 0x0000000c, + /*069b*/ 0x00000033, + /*069c*/ 0x00000000, + /*069d*/ 0x00000000, + /*069e*/ 0x00000000, + /*069f*/ 0x0002006e, + /*06a0*/ 0x02000200, + /*06a1*/ 0x02000200, + /*06a2*/ 0x00000200, + /*06a3*/ 0x42080010, + /*06a4*/ 0x00000003 +}; + +static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = { + /*0700*/ 0x00000001, + /*0701*/ 0x00000000, + /*0702*/ 0x00000005, + /*0703*/ 0x04000f00, + /*0704*/ 0x00020080, + /*0705*/ 0x00020055, + /*0706*/ 0x00000000, + /*0707*/ 0x00000000, + /*0708*/ 0x00000000, + /*0709*/ 0x00000050, + /*070a*/ 0x00000000, + /*070b*/ 0x01010100, + /*070c*/ 0x00000200, + /*070d*/ 0x00001102, + /*070e*/ 0x00000000, + /*070f*/ 0x000f1f00, + /*0710*/ 0x0f1f0f1f, + /*0711*/ 0x0f1f0f1f, + /*0712*/ 0x00020003, + /*0713*/ 0x02000200, + /*0714*/ 0x00000200, + /*0715*/ 0x00001102, + /*0716*/ 0x00000064, + /*0717*/ 0x00000000, + /*0718*/ 0x00000000, + /*0719*/ 0x00000502, + /*071a*/ 0x027f6e00, + /*071b*/ 0x007f007f, + /*071c*/ 0x00007f3c, + /*071d*/ 0x00047f6e, + /*071e*/ 0x0003154f, + /*071f*/ 0x0001154f, + /*0720*/ 0x0001154f, + /*0721*/ 0x0001154f, + /*0722*/ 0x0001154f, + /*0723*/ 0x00003fee, + /*0724*/ 0x0001154f, + /*0725*/ 0x00003fee, + /*0726*/ 0x0001154f, + /*0727*/ 0x00007f3c, + /*0728*/ 0x0001154f, + /*0729*/ 0x00000000, + /*072a*/ 0x00000000, + /*072b*/ 0x00000000, + /*072c*/ 0x65000000, + /*072d*/ 0x00000000, + /*072e*/ 0x00000000, + /*072f*/ 0x00000201, + /*0730*/ 0x00000000, + /*0731*/ 0x00000000, + /*0732*/ 0x00000000, + /*0733*/ 0x00000000, + /*0734*/ 0x00000000, + /*0735*/ 0x00000000, + /*0736*/ 0x00000000, + /*0737*/ 0x00000000, + /*0738*/ 0x00000000, + /*0739*/ 0x00000000, + /*073a*/ 0x00000000 +}; + +static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = { + /*0200*/ 0x00000b00, + /*0201*/ 0x00000100, + /*0202*/ 0x00000000, + /*0203*/ 0x0000ffff, + /*0204*/ 0x00000000, + /*0205*/ 0x0000ffff, + /*0206*/ 0x00000000, + /*0207*/ 0x304cffff, + /*0208*/ 0x00000200, + /*0209*/ 0x00000200, + /*020a*/ 0x00000200, + /*020b*/ 0x00000200, + /*020c*/ 0x0000304c, + /*020d*/ 0x00000200, + /*020e*/ 0x00000200, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x0000304c, + /*0212*/ 0x00000200, + /*0213*/ 0x00000200, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00010000, + /*0217*/ 0x00000003, + /*0218*/ 0x01000001, + /*0219*/ 0x00000000, + /*021a*/ 0x00000000, + /*021b*/ 0x00000000, + /*021c*/ 0x00000000, + /*021d*/ 0x00000000, + /*021e*/ 0x00000000, + /*021f*/ 0x00000000, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x0f000101, + /*022a*/ 0x08492d25, + /*022b*/ 0x500e0c04, + /*022c*/ 0x0002500e, + /*022d*/ 0x00460003, + /*022e*/ 0x182600cf, + /*022f*/ 0x182600cf, + /*0230*/ 0x00000005, + /*0231*/ 0x00000000, + /*0232*/ 0x00000000, + /*0233*/ 0x00000000, + /*0234*/ 0x00000000, + /*0235*/ 0x00000000, + /*0236*/ 0x00000000, + /*0237*/ 0x00000000, + /*0238*/ 0x01000000, + /*0239*/ 0x00040404, + /*023a*/ 0x01280a00, + /*023b*/ 0x00000000, + /*023c*/ 0x000f0000, + /*023d*/ 0x00001803, + /*023e*/ 0x00000000, + /*023f*/ 0x00000000, + /*0240*/ 0x00060002, + /*0241*/ 0x00010001, + /*0242*/ 0x01000101, + /*0243*/ 0x04020201, + /*0244*/ 0x00080804, + /*0245*/ 0x00000000, + /*0246*/ 0x08030000, + /*0247*/ 0x15150408, + /*0248*/ 0x00000000, + /*0249*/ 0x00000000, + /*024a*/ 0x00000000, + /*024b*/ 0x001e0f0f, + /*024c*/ 0x00000000, + /*024d*/ 0x01000300, + /*024e*/ 0x00000000, + /*024f*/ 0x00000000, + /*0250*/ 0x01000000, + /*0251*/ 0x00010101, + /*0252*/ 0x000e0e0e, + /*0253*/ 0x000c0c0c, + /*0254*/ 0x02060601, + /*0255*/ 0x00000000, + /*0256*/ 0x00000003, + /*0257*/ 0x00181703, + /*0258*/ 0x00280006, + /*0259*/ 0x00280016, + /*025a*/ 0x00000016, + /*025b*/ 0x00000000, + /*025c*/ 0x00000000, + /*025d*/ 0x00000000, + /*025e*/ 0x140a0000, + /*025f*/ 0x0005010a, + /*0260*/ 0x03018d03, + /*0261*/ 0x000a018d, + /*0262*/ 0x00060100, + /*0263*/ 0x01000006, + /*0264*/ 0x018e018e, + /*0265*/ 0x018e0100, + /*0266*/ 0x1111018e, + /*0267*/ 0x10010204, + /*0268*/ 0x09090650, + /*0269*/ 0x20110202, + /*026a*/ 0x00201000, + /*026b*/ 0x00201000, + /*026c*/ 0x04041000, + /*026d*/ 0x18020100, + /*026e*/ 0x00010118, + /*026f*/ 0x004b004a, + /*0270*/ 0x050f0000, + /*0271*/ 0x0c01021e, + /*0272*/ 0x34000000, + /*0273*/ 0x00000000, + /*0274*/ 0x00000000, + /*0275*/ 0x00000000, + /*0276*/ 0x312ed400, + /*0277*/ 0xd4111132, + /*0278*/ 0x1132312e, + /*0279*/ 0x312ed411, + /*027a*/ 0x00111132, + /*027b*/ 0x32312ed4, + /*027c*/ 0x2ed41111, + /*027d*/ 0x11113231, + /*027e*/ 0x32312ed4, + /*027f*/ 0xd4001111, + /*0280*/ 0x1132312e, + /*0281*/ 0x312ed411, + /*0282*/ 0xd4111132, + /*0283*/ 0x1132312e, + /*0284*/ 0x2ed40011, + /*0285*/ 0x11113231, + /*0286*/ 0x32312ed4, + /*0287*/ 0x2ed41111, + /*0288*/ 0x11113231, + /*0289*/ 0x00020000, + /*028a*/ 0x018d018d, + /*028b*/ 0x0c08018d, + /*028c*/ 0x1f121d22, + /*028d*/ 0x4301b344, + /*028e*/ 0x10172006, + /*028f*/ 0x121d220c, + /*0290*/ 0x01b3441f, + /*0291*/ 0x17200643, + /*0292*/ 0x1d220c10, + /*0293*/ 0x00001f12, + /*0294*/ 0x4301b344, + /*0295*/ 0x10172006, + /*0296*/ 0x00020002, + /*0297*/ 0x00020002, + /*0298*/ 0x00020002, + /*0299*/ 0x00020002, + /*029a*/ 0x00020002, + /*029b*/ 0x00000000, + /*029c*/ 0x00000000, + /*029d*/ 0x00000000, + /*029e*/ 0x00000000, + /*029f*/ 0x00000000, + /*02a0*/ 0x00000000, + /*02a1*/ 0x00000000, + /*02a2*/ 0x00000000, + /*02a3*/ 0x00000000, + /*02a4*/ 0x00000000, + /*02a5*/ 0x00000000, + /*02a6*/ 0x00000000, + /*02a7*/ 0x01000400, + /*02a8*/ 0x00304c00, + /*02a9*/ 0x0001e2f8, + /*02aa*/ 0x0000304c, + /*02ab*/ 0x0001e2f8, + /*02ac*/ 0x0000304c, + /*02ad*/ 0x0001e2f8, + /*02ae*/ 0x08000000, + /*02af*/ 0x00000100, + /*02b0*/ 0x00000000, + /*02b1*/ 0x00000000, + /*02b2*/ 0x00000000, + /*02b3*/ 0x00000000, + /*02b4*/ 0x00000002 +}; diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h new file mode 100644 index 000000000..e5258af6c --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h @@ -0,0 +1,538 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define DDR_PHY_SLICE_REGSET_OFS_H3VER2 0x0400 +#define DDR_PHY_ADR_V_REGSET_OFS_H3VER2 0x0600 +#define DDR_PHY_ADR_I_REGSET_OFS_H3VER2 0x0640 +#define DDR_PHY_ADR_G_REGSET_OFS_H3VER2 0x0680 +#define DDR_PI_REGSET_OFS_H3VER2 0x0200 + +#define DDR_PHY_SLICE_REGSET_SIZE_H3VER2 0x80 +#define DDR_PHY_ADR_V_REGSET_SIZE_H3VER2 0x40 +#define DDR_PHY_ADR_I_REGSET_SIZE_H3VER2 0x40 +#define DDR_PHY_ADR_G_REGSET_SIZE_H3VER2 0x80 +#define DDR_PI_REGSET_SIZE_H3VER2 0x100 + +#define DDR_PHY_SLICE_REGSET_NUM_H3VER2 97 +#define DDR_PHY_ADR_V_REGSET_NUM_H3VER2 37 +#define DDR_PHY_ADR_I_REGSET_NUM_H3VER2 37 +#define DDR_PHY_ADR_G_REGSET_NUM_H3VER2 79 +#define DDR_PI_REGSET_NUM_H3VER2 245 + +static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2 + [DDR_PHY_SLICE_REGSET_NUM_H3VER2] = { + /*0400*/ 0x76543210, + /*0401*/ 0x0004f008, + /*0402*/ 0x00020133, + /*0403*/ 0x00000000, + /*0404*/ 0x00000000, + /*0405*/ 0x00010000, + /*0406*/ 0x016e6e0e, + /*0407*/ 0x026e6e0e, + /*0408*/ 0x00010300, + /*0409*/ 0x04000100, + /*040a*/ 0x01000000, + /*040b*/ 0x00000000, + /*040c*/ 0x00000000, + /*040d*/ 0x00000100, + /*040e*/ 0x001700c0, + /*040f*/ 0x020100b0, + /*0410*/ 0x00030020, + /*0411*/ 0x00000000, + /*0412*/ 0x00000000, + /*0413*/ 0x00000000, + /*0414*/ 0x00000000, + /*0415*/ 0x00000000, + /*0416*/ 0x00000000, + /*0417*/ 0x00000000, + /*0418*/ 0x09000000, + /*0419*/ 0x04080000, + /*041a*/ 0x04080400, + /*041b*/ 0x08000000, + /*041c*/ 0x0c008007, + /*041d*/ 0x00000f00, + /*041e*/ 0x00000100, + /*041f*/ 0x55aa55aa, + /*0420*/ 0x33cc33cc, + /*0421*/ 0x0ff00ff0, + /*0422*/ 0x0f0ff0f0, + /*0423*/ 0x00018e38, + /*0424*/ 0x00000000, + /*0425*/ 0x00000000, + /*0426*/ 0x00000000, + /*0427*/ 0x00000000, + /*0428*/ 0x00000000, + /*0429*/ 0x00000000, + /*042a*/ 0x00000000, + /*042b*/ 0x00000000, + /*042c*/ 0x00000000, + /*042d*/ 0x00000000, + /*042e*/ 0x00000000, + /*042f*/ 0x00000000, + /*0430*/ 0x00000000, + /*0431*/ 0x00000000, + /*0432*/ 0x00000000, + /*0433*/ 0x00000000, + /*0434*/ 0x00000000, + /*0435*/ 0x00000000, + /*0436*/ 0x00000000, + /*0437*/ 0x00000000, + /*0438*/ 0x00000104, + /*0439*/ 0x00082020, + /*043a*/ 0x08200820, + /*043b*/ 0x08200820, + /*043c*/ 0x08200820, + /*043d*/ 0x08200820, + /*043e*/ 0x08200820, + /*043f*/ 0x00000000, + /*0440*/ 0x00000000, + /*0441*/ 0x03000300, + /*0442*/ 0x03000300, + /*0443*/ 0x03000300, + /*0444*/ 0x03000300, + /*0445*/ 0x00000300, + /*0446*/ 0x00000000, + /*0447*/ 0x00000000, + /*0448*/ 0x00000000, + /*0449*/ 0x00000000, + /*044a*/ 0x00000000, + /*044b*/ 0x00a000a0, + /*044c*/ 0x00a000a0, + /*044d*/ 0x00a000a0, + /*044e*/ 0x00a000a0, + /*044f*/ 0x00a000a0, + /*0450*/ 0x00a000a0, + /*0451*/ 0x00a000a0, + /*0452*/ 0x00a000a0, + /*0453*/ 0x00a000a0, + /*0454*/ 0x01040109, + /*0455*/ 0x00000200, + /*0456*/ 0x01000000, + /*0457*/ 0x00000200, + /*0458*/ 0x00000004, + /*0459*/ 0x4041a151, + /*045a*/ 0xc00141a0, + /*045b*/ 0x0e0000c0, + /*045c*/ 0x0010000c, + /*045d*/ 0x063e4208, + /*045e*/ 0x0f0c180c, + /*045f*/ 0x00e00140, + /*0460*/ 0x00000c20 +}; + +static const uint32_t + DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = { + /*0600*/ 0x00000000, + /*0601*/ 0x00000000, + /*0602*/ 0x00000000, + /*0603*/ 0x00000000, + /*0604*/ 0x00000000, + /*0605*/ 0x00000000, + /*0606*/ 0x00000000, + /*0607*/ 0x00010000, + /*0608*/ 0x00000200, + /*0609*/ 0x00000000, + /*060a*/ 0x00000000, + /*060b*/ 0x00000000, + /*060c*/ 0x00400320, + /*060d*/ 0x00000040, + /*060e*/ 0x00dcba98, + /*060f*/ 0x03000000, + /*0610*/ 0x00000200, + /*0611*/ 0x00000000, + /*0612*/ 0x00000000, + /*0613*/ 0x00000000, + /*0614*/ 0x0000002a, + /*0615*/ 0x00000015, + /*0616*/ 0x00000015, + /*0617*/ 0x0000002a, + /*0618*/ 0x00000033, + /*0619*/ 0x0000000c, + /*061a*/ 0x0000000c, + /*061b*/ 0x00000033, + /*061c*/ 0x00418820, + /*061d*/ 0x003f0000, + /*061e*/ 0x0000003f, + /*061f*/ 0x0002c06e, + /*0620*/ 0x02c002c0, + /*0621*/ 0x02c002c0, + /*0622*/ 0x000002c0, + /*0623*/ 0x42080010, + /*0624*/ 0x0000033e +}; + +static const uint32_t + DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = { + /*0640*/ 0x00000000, + /*0641*/ 0x00000000, + /*0642*/ 0x00000000, + /*0643*/ 0x00000000, + /*0644*/ 0x00000000, + /*0645*/ 0x00000000, + /*0646*/ 0x00000000, + /*0647*/ 0x00000000, + /*0648*/ 0x00000000, + /*0649*/ 0x00000000, + /*064a*/ 0x00000000, + /*064b*/ 0x00000000, + /*064c*/ 0x00000000, + /*064d*/ 0x00000000, + /*064e*/ 0x00000000, + /*064f*/ 0x00000000, + /*0650*/ 0x00000000, + /*0651*/ 0x00000000, + /*0652*/ 0x00000000, + /*0653*/ 0x00000000, + /*0654*/ 0x00000000, + /*0655*/ 0x00000000, + /*0656*/ 0x00000000, + /*0657*/ 0x00000000, + /*0658*/ 0x00000000, + /*0659*/ 0x00000000, + /*065a*/ 0x00000000, + /*065b*/ 0x00000000, + /*065c*/ 0x00000000, + /*065d*/ 0x00000000, + /*065e*/ 0x00000000, + /*065f*/ 0x00000000, + /*0660*/ 0x00000000, + /*0661*/ 0x00000000, + /*0662*/ 0x00000000, + /*0663*/ 0x00000000, + /*0664*/ 0x00000000 +}; + +static const uint32_t + DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = { + /*0680*/ 0x00000000, + /*0681*/ 0x00000100, + /*0682*/ 0x00000000, + /*0683*/ 0x00050000, + /*0684*/ 0x0f000000, + /*0685*/ 0x00800400, + /*0686*/ 0x00020032, + /*0687*/ 0x00020055, + /*0688*/ 0x00000000, + /*0689*/ 0x00000000, + /*068a*/ 0x00000000, + /*068b*/ 0x00000050, + /*068c*/ 0x00000000, + /*068d*/ 0x01010100, + /*068e*/ 0x01000200, + /*068f*/ 0x00000000, + /*0690*/ 0x00010100, + /*0691*/ 0x00000000, + /*0692*/ 0x00000000, + /*0693*/ 0x00000000, + /*0694*/ 0x00000000, + /*0695*/ 0x00005064, + /*0696*/ 0x01421142, + /*0697*/ 0x00000142, + /*0698*/ 0x00000000, + /*0699*/ 0x000f1100, + /*069a*/ 0x0f110f11, + /*069b*/ 0x09000f11, + /*069c*/ 0x00000003, + /*069d*/ 0x0002c000, + /*069e*/ 0x02c002c0, + /*069f*/ 0x000002c0, + /*06a0*/ 0x03421342, + /*06a1*/ 0x00000342, + /*06a2*/ 0x00000000, + /*06a3*/ 0x00000000, + /*06a4*/ 0x05020000, + /*06a5*/ 0x14000000, + /*06a6*/ 0x027f6e00, + /*06a7*/ 0x047f027f, + /*06a8*/ 0x00027f6e, + /*06a9*/ 0x00047f6e, + /*06aa*/ 0x0003554f, + /*06ab*/ 0x0001554f, + /*06ac*/ 0x0001554f, + /*06ad*/ 0x0001554f, + /*06ae*/ 0x0001554f, + /*06af*/ 0x00003fee, + /*06b0*/ 0x0001554f, + /*06b1*/ 0x00003fee, + /*06b2*/ 0x0001554f, + /*06b3*/ 0x00027f6e, + /*06b4*/ 0x0001554f, + /*06b5*/ 0x00004011, + /*06b6*/ 0x00004410, + /*06b7*/ 0x00000000, + /*06b8*/ 0x00000000, + /*06b9*/ 0x00000000, + /*06ba*/ 0x00000065, + /*06bb*/ 0x00000000, + /*06bc*/ 0x00020201, + /*06bd*/ 0x00000000, + /*06be*/ 0x03000000, + /*06bf*/ 0x00000008, + /*06c0*/ 0x00000000, + /*06c1*/ 0x00000000, + /*06c2*/ 0x00000000, + /*06c3*/ 0x00000000, + /*06c4*/ 0x00000001, + /*06c5*/ 0x00000000, + /*06c6*/ 0x00000000, + /*06c7*/ 0x00000000, + /*06c8*/ 0x000000e4, + /*06c9*/ 0x00010198, + /*06ca*/ 0x00000000, + /*06cb*/ 0x00000000, + /*06cc*/ 0x07010000, + /*06cd*/ 0x00000104, + /*06ce*/ 0x00000000 +}; + +static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = { + /*0200*/ 0x00000b00, + /*0201*/ 0x00000100, + /*0202*/ 0x00640000, + /*0203*/ 0x00000000, + /*0204*/ 0x0000ffff, + /*0205*/ 0x00000000, + /*0206*/ 0x0000ffff, + /*0207*/ 0x00000000, + /*0208*/ 0x0000ffff, + /*0209*/ 0x0000304c, + /*020a*/ 0x00000200, + /*020b*/ 0x00000200, + /*020c*/ 0x00000200, + /*020d*/ 0x00000200, + /*020e*/ 0x0000304c, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x00000200, + /*0212*/ 0x00000200, + /*0213*/ 0x0000304c, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00000200, + /*0217*/ 0x00000200, + /*0218*/ 0x00010000, + /*0219*/ 0x00000003, + /*021a*/ 0x01000001, + /*021b*/ 0x00000000, + /*021c*/ 0x00000000, + /*021d*/ 0x00000000, + /*021e*/ 0x00000000, + /*021f*/ 0x00000000, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x00000000, + /*022a*/ 0x00000000, + /*022b*/ 0x0f000101, + /*022c*/ 0x08492d25, + /*022d*/ 0x500e0c04, + /*022e*/ 0x0002500e, + /*022f*/ 0x00000301, + /*0230*/ 0x00000046, + /*0231*/ 0x000000cf, + /*0232*/ 0x00001826, + /*0233*/ 0x000000cf, + /*0234*/ 0x00001826, + /*0235*/ 0x00000005, + /*0236*/ 0x00000000, + /*0237*/ 0x00000000, + /*0238*/ 0x00000000, + /*0239*/ 0x00000000, + /*023a*/ 0x00000000, + /*023b*/ 0x00000000, + /*023c*/ 0x00000000, + /*023d*/ 0x00000000, + /*023e*/ 0x04010000, + /*023f*/ 0x00000404, + /*0240*/ 0x0101280a, + /*0241*/ 0x00000000, + /*0242*/ 0x00000000, + /*0243*/ 0x0003000f, + /*0244*/ 0x00000018, + /*0245*/ 0x00000000, + /*0246*/ 0x00000000, + /*0247*/ 0x00060002, + /*0248*/ 0x00010001, + /*0249*/ 0x01000101, + /*024a*/ 0x04020201, + /*024b*/ 0x00080804, + /*024c*/ 0x00000000, + /*024d*/ 0x08030000, + /*024e*/ 0x15150408, + /*024f*/ 0x00000000, + /*0250*/ 0x00000000, + /*0251*/ 0x00000000, + /*0252*/ 0x0f0f0000, + /*0253*/ 0x0000001e, + /*0254*/ 0x00000000, + /*0255*/ 0x01000300, + /*0256*/ 0x00000100, + /*0257*/ 0x00000000, + /*0258*/ 0x00000000, + /*0259*/ 0x01000000, + /*025a*/ 0x00000101, + /*025b*/ 0x55555a5a, + /*025c*/ 0x55555a5a, + /*025d*/ 0x55555a5a, + /*025e*/ 0x55555a5a, + /*025f*/ 0x0e0e0001, + /*0260*/ 0x0c0c000e, + /*0261*/ 0x0601000c, + /*0262*/ 0x17170106, + /*0263*/ 0x00020202, + /*0264*/ 0x03000000, + /*0265*/ 0x00000000, + /*0266*/ 0x00181703, + /*0267*/ 0x00280006, + /*0268*/ 0x00280016, + /*0269*/ 0x00000016, + /*026a*/ 0x00000000, + /*026b*/ 0x00000000, + /*026c*/ 0x00000000, + /*026d*/ 0x0a000000, + /*026e*/ 0x00010a14, + /*026f*/ 0x00030005, + /*0270*/ 0x0003018d, + /*0271*/ 0x000a018d, + /*0272*/ 0x00060100, + /*0273*/ 0x01000006, + /*0274*/ 0x018e018e, + /*0275*/ 0x018e0100, + /*0276*/ 0x1111018e, + /*0277*/ 0x10010204, + /*0278*/ 0x09090650, + /*0279*/ 0xff110202, + /*027a*/ 0x00ff1000, + /*027b*/ 0x00ff1000, + /*027c*/ 0x04041000, + /*027d*/ 0x18020100, + /*027e*/ 0x01010018, + /*027f*/ 0x004a004a, + /*0280*/ 0x004b004a, + /*0281*/ 0x050f0000, + /*0282*/ 0x0c01021e, + /*0283*/ 0x34000000, + /*0284*/ 0x00000000, + /*0285*/ 0x00000000, + /*0286*/ 0x00000000, + /*0287*/ 0x00000000, + /*0288*/ 0x36312ed4, + /*0289*/ 0x2ed41111, + /*028a*/ 0x11113631, + /*028b*/ 0x36312ed4, + /*028c*/ 0xd4001111, + /*028d*/ 0x1136312e, + /*028e*/ 0x312ed411, + /*028f*/ 0xd4111136, + /*0290*/ 0x1136312e, + /*0291*/ 0x2ed40011, + /*0292*/ 0x11113631, + /*0293*/ 0x36312ed4, + /*0294*/ 0x2ed41111, + /*0295*/ 0x11113631, + /*0296*/ 0x312ed400, + /*0297*/ 0xd4111136, + /*0298*/ 0x1136312e, + /*0299*/ 0x312ed411, + /*029a*/ 0x00111136, + /*029b*/ 0x018d0200, + /*029c*/ 0x018d018d, + /*029d*/ 0x1d220c08, + /*029e*/ 0x00001f12, + /*029f*/ 0x4301b344, + /*02a0*/ 0x10172006, + /*02a1*/ 0x121d220c, + /*02a2*/ 0x01b3441f, + /*02a3*/ 0x17200643, + /*02a4*/ 0x1d220c10, + /*02a5*/ 0x00001f12, + /*02a6*/ 0x4301b344, + /*02a7*/ 0x10172006, + /*02a8*/ 0x00020002, + /*02a9*/ 0x00020002, + /*02aa*/ 0x00020002, + /*02ab*/ 0x00020002, + /*02ac*/ 0x00020002, + /*02ad*/ 0x00000000, + /*02ae*/ 0x00000000, + /*02af*/ 0x00000000, + /*02b0*/ 0x00000000, + /*02b1*/ 0x00000000, + /*02b2*/ 0x00000000, + /*02b3*/ 0x00000000, + /*02b4*/ 0x00000000, + /*02b5*/ 0x00000000, + /*02b6*/ 0x00000000, + /*02b7*/ 0x00000000, + /*02b8*/ 0x00000000, + /*02b9*/ 0x00000400, + /*02ba*/ 0x05040302, + /*02bb*/ 0x01000f0e, + /*02bc*/ 0x07060504, + /*02bd*/ 0x03020100, + /*02be*/ 0x02010000, + /*02bf*/ 0x00000103, + /*02c0*/ 0x0000304c, + /*02c1*/ 0x0001e2f8, + /*02c2*/ 0x0000304c, + /*02c3*/ 0x0001e2f8, + /*02c4*/ 0x0000304c, + /*02c5*/ 0x0001e2f8, + /*02c6*/ 0x08000000, + /*02c7*/ 0x00000100, + /*02c8*/ 0x00000000, + /*02c9*/ 0x00000000, + /*02ca*/ 0x00000000, + /*02cb*/ 0x00000000, + /*02cc*/ 0x00010000, + /*02cd*/ 0x00000000, + /*02ce*/ 0x00000000, + /*02cf*/ 0x00000000, + /*02d0*/ 0x00000000, + /*02d1*/ 0x00000000, + /*02d2*/ 0x00000000, + /*02d3*/ 0x00000000, + /*02d4*/ 0x00000000, + /*02d5*/ 0x00000000, + /*02d6*/ 0x00000000, + /*02d7*/ 0x00000000, + /*02d8*/ 0x00000000, + /*02d9*/ 0x00000000, + /*02da*/ 0x00000000, + /*02db*/ 0x00000000, + /*02dc*/ 0x00000000, + /*02dd*/ 0x00000000, + /*02de*/ 0x00000000, + /*02df*/ 0x00000000, + /*02e0*/ 0x00000000, + /*02e1*/ 0x00000000, + /*02e2*/ 0x00000000, + /*02e3*/ 0x00000000, + /*02e4*/ 0x00000000, + /*02e5*/ 0x00000000, + /*02e6*/ 0x00000000, + /*02e7*/ 0x00000000, + /*02e8*/ 0x00000000, + /*02e9*/ 0x00000000, + /*02ea*/ 0x00000000, + /*02eb*/ 0x00000000, + /*02ec*/ 0x00000000, + /*02ed*/ 0x00000000, + /*02ee*/ 0x00000002, + /*02ef*/ 0x00000000, + /*02f0*/ 0x00000000, + /*02f1*/ 0x00000000, + /*02f2*/ 0x00000000, + /*02f3*/ 0x00000000, + /*02f4*/ 0x00000000 +}; diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h new file mode 100644 index 000000000..b491f0e91 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h @@ -0,0 +1,468 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define DDR_PHY_SLICE_REGSET_OFS_M3 0x0800 +#define DDR_PHY_ADR_V_REGSET_OFS_M3 0x0a00 +#define DDR_PHY_ADR_I_REGSET_OFS_M3 0x0a80 +#define DDR_PHY_ADR_G_REGSET_OFS_M3 0x0b80 +#define DDR_PI_REGSET_OFS_M3 0x0200 + +#define DDR_PHY_SLICE_REGSET_SIZE_M3 0x80 +#define DDR_PHY_ADR_V_REGSET_SIZE_M3 0x80 +#define DDR_PHY_ADR_I_REGSET_SIZE_M3 0x80 +#define DDR_PHY_ADR_G_REGSET_SIZE_M3 0x80 +#define DDR_PI_REGSET_SIZE_M3 0x100 + +#define DDR_PHY_SLICE_REGSET_NUM_M3 89 +#define DDR_PHY_ADR_V_REGSET_NUM_M3 37 +#define DDR_PHY_ADR_I_REGSET_NUM_M3 37 +#define DDR_PHY_ADR_G_REGSET_NUM_M3 64 +#define DDR_PI_REGSET_NUM_M3 202 + +static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = { + /*0800*/ 0x76543210, + /*0801*/ 0x0004f008, + /*0802*/ 0x00000000, + /*0803*/ 0x00000000, + /*0804*/ 0x00010000, + /*0805*/ 0x036e6e0e, + /*0806*/ 0x026e6e0e, + /*0807*/ 0x00010300, + /*0808*/ 0x04000100, + /*0809*/ 0x00000300, + /*080a*/ 0x001700c0, + /*080b*/ 0x00b00201, + /*080c*/ 0x00030020, + /*080d*/ 0x00000000, + /*080e*/ 0x00000000, + /*080f*/ 0x00000000, + /*0810*/ 0x00000000, + /*0811*/ 0x00000000, + /*0812*/ 0x00000000, + /*0813*/ 0x00000000, + /*0814*/ 0x09000000, + /*0815*/ 0x04080000, + /*0816*/ 0x04080400, + /*0817*/ 0x00000000, + /*0818*/ 0x32103210, + /*0819*/ 0x00800708, + /*081a*/ 0x000f000c, + /*081b*/ 0x00000100, + /*081c*/ 0x55aa55aa, + /*081d*/ 0x33cc33cc, + /*081e*/ 0x0ff00ff0, + /*081f*/ 0x0f0ff0f0, + /*0820*/ 0x00018e38, + /*0821*/ 0x00000000, + /*0822*/ 0x00000000, + /*0823*/ 0x00000000, + /*0824*/ 0x00000000, + /*0825*/ 0x00000000, + /*0826*/ 0x00000000, + /*0827*/ 0x00000000, + /*0828*/ 0x00000000, + /*0829*/ 0x00000000, + /*082a*/ 0x00000000, + /*082b*/ 0x00000000, + /*082c*/ 0x00000000, + /*082d*/ 0x00000000, + /*082e*/ 0x00000000, + /*082f*/ 0x00000000, + /*0830*/ 0x00000000, + /*0831*/ 0x00000000, + /*0832*/ 0x00000000, + /*0833*/ 0x00200000, + /*0834*/ 0x08200820, + /*0835*/ 0x08200820, + /*0836*/ 0x08200820, + /*0837*/ 0x08200820, + /*0838*/ 0x08200820, + /*0839*/ 0x00000820, + /*083a*/ 0x03000300, + /*083b*/ 0x03000300, + /*083c*/ 0x03000300, + /*083d*/ 0x03000300, + /*083e*/ 0x00000300, + /*083f*/ 0x00000000, + /*0840*/ 0x00000000, + /*0841*/ 0x00000000, + /*0842*/ 0x00000000, + /*0843*/ 0x00a00000, + /*0844*/ 0x00a000a0, + /*0845*/ 0x00a000a0, + /*0846*/ 0x00a000a0, + /*0847*/ 0x00a000a0, + /*0848*/ 0x00a000a0, + /*0849*/ 0x00a000a0, + /*084a*/ 0x00a000a0, + /*084b*/ 0x00a000a0, + /*084c*/ 0x010900a0, + /*084d*/ 0x02000104, + /*084e*/ 0x00000000, + /*084f*/ 0x00010000, + /*0850*/ 0x00000200, + /*0851*/ 0x4041a151, + /*0852*/ 0xc00141a0, + /*0853*/ 0x0e0100c0, + /*0854*/ 0x0010000c, + /*0855*/ 0x0c064208, + /*0856*/ 0x000f0c18, + /*0857*/ 0x00e00140, + /*0858*/ 0x00000c20 +}; + +static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = { + /*0a00*/ 0x00000000, + /*0a01*/ 0x00000000, + /*0a02*/ 0x00000000, + /*0a03*/ 0x00000000, + /*0a04*/ 0x00000000, + /*0a05*/ 0x00000000, + /*0a06*/ 0x00000002, + /*0a07*/ 0x00000000, + /*0a08*/ 0x00000000, + /*0a09*/ 0x00000000, + /*0a0a*/ 0x00400320, + /*0a0b*/ 0x00000040, + /*0a0c*/ 0x00dcba98, + /*0a0d*/ 0x00000000, + /*0a0e*/ 0x00dcba98, + /*0a0f*/ 0x01000000, + /*0a10*/ 0x00020003, + /*0a11*/ 0x00000000, + /*0a12*/ 0x00000000, + /*0a13*/ 0x00000000, + /*0a14*/ 0x0000002a, + /*0a15*/ 0x00000015, + /*0a16*/ 0x00000015, + /*0a17*/ 0x0000002a, + /*0a18*/ 0x00000033, + /*0a19*/ 0x0000000c, + /*0a1a*/ 0x0000000c, + /*0a1b*/ 0x00000033, + /*0a1c*/ 0x0a418820, + /*0a1d*/ 0x003f0000, + /*0a1e*/ 0x0000003f, + /*0a1f*/ 0x0002c06e, + /*0a20*/ 0x02c002c0, + /*0a21*/ 0x02c002c0, + /*0a22*/ 0x000002c0, + /*0a23*/ 0x42080010, + /*0a24*/ 0x00000003 +}; + +static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = { + /*0a80*/ 0x04040404, + /*0a81*/ 0x00000404, + /*0a82*/ 0x00000000, + /*0a83*/ 0x00000000, + /*0a84*/ 0x00000000, + /*0a85*/ 0x00000000, + /*0a86*/ 0x00000002, + /*0a87*/ 0x00000000, + /*0a88*/ 0x00000000, + /*0a89*/ 0x00000000, + /*0a8a*/ 0x00400320, + /*0a8b*/ 0x00000040, + /*0a8c*/ 0x00000000, + /*0a8d*/ 0x00000000, + /*0a8e*/ 0x00000000, + /*0a8f*/ 0x01000000, + /*0a90*/ 0x00020003, + /*0a91*/ 0x00000000, + /*0a92*/ 0x00000000, + /*0a93*/ 0x00000000, + /*0a94*/ 0x0000002a, + /*0a95*/ 0x00000015, + /*0a96*/ 0x00000015, + /*0a97*/ 0x0000002a, + /*0a98*/ 0x00000033, + /*0a99*/ 0x0000000c, + /*0a9a*/ 0x0000000c, + /*0a9b*/ 0x00000033, + /*0a9c*/ 0x00000000, + /*0a9d*/ 0x00000000, + /*0a9e*/ 0x00000000, + /*0a9f*/ 0x0002c06e, + /*0aa0*/ 0x02c002c0, + /*0aa1*/ 0x02c002c0, + /*0aa2*/ 0x000002c0, + /*0aa3*/ 0x42080010, + /*0aa4*/ 0x00000003 +}; + +static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = { + /*0b80*/ 0x00000001, + /*0b81*/ 0x00000000, + /*0b82*/ 0x00000005, + /*0b83*/ 0x04000f00, + /*0b84*/ 0x00020080, + /*0b85*/ 0x00020055, + /*0b86*/ 0x00000000, + /*0b87*/ 0x00000000, + /*0b88*/ 0x00000000, + /*0b89*/ 0x00000050, + /*0b8a*/ 0x00000000, + /*0b8b*/ 0x01010100, + /*0b8c*/ 0x00000600, + /*0b8d*/ 0x50640000, + /*0b8e*/ 0x01421142, + /*0b8f*/ 0x00000142, + /*0b90*/ 0x00000000, + /*0b91*/ 0x000f1600, + /*0b92*/ 0x0f160f16, + /*0b93*/ 0x0f160f16, + /*0b94*/ 0x00000003, + /*0b95*/ 0x0002c000, + /*0b96*/ 0x02c002c0, + /*0b97*/ 0x000002c0, + /*0b98*/ 0x03421342, + /*0b99*/ 0x00000342, + /*0b9a*/ 0x00000000, + /*0b9b*/ 0x00000000, + /*0b9c*/ 0x05020000, + /*0b9d*/ 0x00000000, + /*0b9e*/ 0x00027f6e, + /*0b9f*/ 0x047f027f, + /*0ba0*/ 0x00027f6e, + /*0ba1*/ 0x00047f6e, + /*0ba2*/ 0x0003554f, + /*0ba3*/ 0x0001554f, + /*0ba4*/ 0x0001554f, + /*0ba5*/ 0x0001554f, + /*0ba6*/ 0x0001554f, + /*0ba7*/ 0x00003fee, + /*0ba8*/ 0x0001554f, + /*0ba9*/ 0x00003fee, + /*0baa*/ 0x0001554f, + /*0bab*/ 0x00027f6e, + /*0bac*/ 0x0001554f, + /*0bad*/ 0x00000000, + /*0bae*/ 0x00000000, + /*0baf*/ 0x00000000, + /*0bb0*/ 0x65000000, + /*0bb1*/ 0x00000000, + /*0bb2*/ 0x00000000, + /*0bb3*/ 0x00000201, + /*0bb4*/ 0x00000000, + /*0bb5*/ 0x00000000, + /*0bb6*/ 0x00000000, + /*0bb7*/ 0x00000000, + /*0bb8*/ 0x00000000, + /*0bb9*/ 0x00000000, + /*0bba*/ 0x00000000, + /*0bbb*/ 0x00000000, + /*0bbc*/ 0x06e40000, + /*0bbd*/ 0x00000000, + /*0bbe*/ 0x00000000, + /*0bbf*/ 0x00010000 +}; + +static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = { + /*0200*/ 0x00000b00, + /*0201*/ 0x00000100, + /*0202*/ 0x00000000, + /*0203*/ 0x0000ffff, + /*0204*/ 0x00000000, + /*0205*/ 0x0000ffff, + /*0206*/ 0x00000000, + /*0207*/ 0x304cffff, + /*0208*/ 0x00000200, + /*0209*/ 0x00000200, + /*020a*/ 0x00000200, + /*020b*/ 0x00000200, + /*020c*/ 0x0000304c, + /*020d*/ 0x00000200, + /*020e*/ 0x00000200, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x0000304c, + /*0212*/ 0x00000200, + /*0213*/ 0x00000200, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00010000, + /*0217*/ 0x00000003, + /*0218*/ 0x01000001, + /*0219*/ 0x00000000, + /*021a*/ 0x00000000, + /*021b*/ 0x00000000, + /*021c*/ 0x00000000, + /*021d*/ 0x00000000, + /*021e*/ 0x00000000, + /*021f*/ 0x00000000, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x0f000101, + /*022a*/ 0x08492d25, + /*022b*/ 0x0e0c0004, + /*022c*/ 0x000e5000, + /*022d*/ 0x00000250, + /*022e*/ 0x00460003, + /*022f*/ 0x182600cf, + /*0230*/ 0x182600cf, + /*0231*/ 0x00000005, + /*0232*/ 0x00000000, + /*0233*/ 0x00000000, + /*0234*/ 0x00000000, + /*0235*/ 0x00000000, + /*0236*/ 0x00000000, + /*0237*/ 0x00000000, + /*0238*/ 0x00000000, + /*0239*/ 0x01000000, + /*023a*/ 0x00040404, + /*023b*/ 0x01280a00, + /*023c*/ 0x00000000, + /*023d*/ 0x000f0000, + /*023e*/ 0x00001803, + /*023f*/ 0x00000000, + /*0240*/ 0x00000000, + /*0241*/ 0x00060002, + /*0242*/ 0x00010001, + /*0243*/ 0x01000101, + /*0244*/ 0x04020201, + /*0245*/ 0x00080804, + /*0246*/ 0x00000000, + /*0247*/ 0x08030000, + /*0248*/ 0x15150408, + /*0249*/ 0x00000000, + /*024a*/ 0x00000000, + /*024b*/ 0x00000000, + /*024c*/ 0x000f0f00, + /*024d*/ 0x0000001e, + /*024e*/ 0x00000000, + /*024f*/ 0x01000300, + /*0250*/ 0x00000000, + /*0251*/ 0x00000000, + /*0252*/ 0x01000000, + /*0253*/ 0x00010101, + /*0254*/ 0x000e0e0e, + /*0255*/ 0x000c0c0c, + /*0256*/ 0x02060601, + /*0257*/ 0x00000000, + /*0258*/ 0x00000003, + /*0259*/ 0x00181703, + /*025a*/ 0x00280006, + /*025b*/ 0x00280016, + /*025c*/ 0x00000016, + /*025d*/ 0x00000000, + /*025e*/ 0x00000000, + /*025f*/ 0x00000000, + /*0260*/ 0x140a0000, + /*0261*/ 0x0005010a, + /*0262*/ 0x03018d03, + /*0263*/ 0x000a018d, + /*0264*/ 0x00060100, + /*0265*/ 0x01000006, + /*0266*/ 0x018e018e, + /*0267*/ 0x018e0100, + /*0268*/ 0x1111018e, + /*0269*/ 0x10010204, + /*026a*/ 0x09090650, + /*026b*/ 0x20110202, + /*026c*/ 0x00201000, + /*026d*/ 0x00201000, + /*026e*/ 0x04041000, + /*026f*/ 0x18020100, + /*0270*/ 0x00010118, + /*0271*/ 0x004b004a, + /*0272*/ 0x050f0000, + /*0273*/ 0x0c01021e, + /*0274*/ 0x34000000, + /*0275*/ 0x00000000, + /*0276*/ 0x00000000, + /*0277*/ 0x00000000, + /*0278*/ 0x0000d400, + /*0279*/ 0x0031002e, + /*027a*/ 0x00111136, + /*027b*/ 0x002e00d4, + /*027c*/ 0x11360031, + /*027d*/ 0x0000d411, + /*027e*/ 0x0031002e, + /*027f*/ 0x00111136, + /*0280*/ 0x002e00d4, + /*0281*/ 0x11360031, + /*0282*/ 0x0000d411, + /*0283*/ 0x0031002e, + /*0284*/ 0x00111136, + /*0285*/ 0x002e00d4, + /*0286*/ 0x11360031, + /*0287*/ 0x00d40011, + /*0288*/ 0x0031002e, + /*0289*/ 0x00111136, + /*028a*/ 0x002e00d4, + /*028b*/ 0x11360031, + /*028c*/ 0x0000d411, + /*028d*/ 0x0031002e, + /*028e*/ 0x00111136, + /*028f*/ 0x002e00d4, + /*0290*/ 0x11360031, + /*0291*/ 0x0000d411, + /*0292*/ 0x0031002e, + /*0293*/ 0x00111136, + /*0294*/ 0x002e00d4, + /*0295*/ 0x11360031, + /*0296*/ 0x02000011, + /*0297*/ 0x018d018d, + /*0298*/ 0x0c08018d, + /*0299*/ 0x1f121d22, + /*029a*/ 0x4301b344, + /*029b*/ 0x10172006, + /*029c*/ 0x1d220c10, + /*029d*/ 0x00001f12, + /*029e*/ 0x4301b344, + /*029f*/ 0x10172006, + /*02a0*/ 0x1d220c10, + /*02a1*/ 0x00001f12, + /*02a2*/ 0x4301b344, + /*02a3*/ 0x10172006, + /*02a4*/ 0x02000210, + /*02a5*/ 0x02000200, + /*02a6*/ 0x02000200, + /*02a7*/ 0x02000200, + /*02a8*/ 0x02000200, + /*02a9*/ 0x00000000, + /*02aa*/ 0x00000000, + /*02ab*/ 0x00000000, + /*02ac*/ 0x00000000, + /*02ad*/ 0x00000000, + /*02ae*/ 0x00000000, + /*02af*/ 0x00000000, + /*02b0*/ 0x00000000, + /*02b1*/ 0x00000000, + /*02b2*/ 0x00000000, + /*02b3*/ 0x00000000, + /*02b4*/ 0x00000000, + /*02b5*/ 0x00000400, + /*02b6*/ 0x15141312, + /*02b7*/ 0x11100f0e, + /*02b8*/ 0x080b0c0d, + /*02b9*/ 0x05040a09, + /*02ba*/ 0x01000706, + /*02bb*/ 0x00000302, + /*02bc*/ 0x01030201, + /*02bd*/ 0x00304c00, + /*02be*/ 0x0001e2f8, + /*02bf*/ 0x0000304c, + /*02c0*/ 0x0001e2f8, + /*02c1*/ 0x0000304c, + /*02c2*/ 0x0001e2f8, + /*02c3*/ 0x08000000, + /*02c4*/ 0x00000100, + /*02c5*/ 0x00000000, + /*02c6*/ 0x00000000, + /*02c7*/ 0x00000000, + /*02c8*/ 0x00000000, + /*02c9*/ 0x00000002 +}; diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h new file mode 100644 index 000000000..8d80842fd --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h @@ -0,0 +1,587 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define DDR_PHY_SLICE_REGSET_OFS_M3N 0x0800 +#define DDR_PHY_ADR_V_REGSET_OFS_M3N 0x0a00 +#define DDR_PHY_ADR_I_REGSET_OFS_M3N 0x0a80 +#define DDR_PHY_ADR_G_REGSET_OFS_M3N 0x0b80 +#define DDR_PI_REGSET_OFS_M3N 0x0200 + +#define DDR_PHY_SLICE_REGSET_SIZE_M3N 0x80 +#define DDR_PHY_ADR_V_REGSET_SIZE_M3N 0x80 +#define DDR_PHY_ADR_I_REGSET_SIZE_M3N 0x80 +#define DDR_PHY_ADR_G_REGSET_SIZE_M3N 0x80 +#define DDR_PI_REGSET_SIZE_M3N 0x100 + +#define DDR_PHY_SLICE_REGSET_NUM_M3N 101 +#define DDR_PHY_ADR_V_REGSET_NUM_M3N 37 +#define DDR_PHY_ADR_I_REGSET_NUM_M3N 37 +#define DDR_PHY_ADR_G_REGSET_NUM_M3N 87 +#define DDR_PI_REGSET_NUM_M3N 286 + +static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = { + /*0800*/ 0x76543210, + /*0801*/ 0x0004f008, + /*0802*/ 0x00020200, + /*0803*/ 0x00000000, + /*0804*/ 0x00000000, + /*0805*/ 0x00010000, + /*0806*/ 0x036e6e0e, + /*0807*/ 0x026e6e0e, + /*0808*/ 0x00000103, + /*0809*/ 0x00040001, + /*080a*/ 0x00000103, + /*080b*/ 0x00000001, + /*080c*/ 0x00000000, + /*080d*/ 0x00000000, + /*080e*/ 0x00000100, + /*080f*/ 0x001800c0, + /*0810*/ 0x020100b0, + /*0811*/ 0x00030020, + /*0812*/ 0x00000000, + /*0813*/ 0x00000000, + /*0814*/ 0x0000aaaa, + /*0815*/ 0x00005555, + /*0816*/ 0x0000b5b5, + /*0817*/ 0x00004a4a, + /*0818*/ 0x00000000, + /*0819*/ 0x09000000, + /*081a*/ 0x04080000, + /*081b*/ 0x08040000, + /*081c*/ 0x00000004, + /*081d*/ 0x00800710, + /*081e*/ 0x000f000c, + /*081f*/ 0x00000100, + /*0820*/ 0x55aa55aa, + /*0821*/ 0x33cc33cc, + /*0822*/ 0x0ff00ff0, + /*0823*/ 0x0f0ff0f0, + /*0824*/ 0x00018e38, + /*0825*/ 0x00000000, + /*0826*/ 0x00000000, + /*0827*/ 0x00000000, + /*0828*/ 0x00000000, + /*0829*/ 0x00000000, + /*082a*/ 0x00000000, + /*082b*/ 0x00000000, + /*082c*/ 0x00000000, + /*082d*/ 0x00000000, + /*082e*/ 0x00000000, + /*082f*/ 0x00000000, + /*0830*/ 0x00000000, + /*0831*/ 0x00000000, + /*0832*/ 0x00000000, + /*0833*/ 0x00000000, + /*0834*/ 0x00000000, + /*0835*/ 0x00000000, + /*0836*/ 0x00000000, + /*0837*/ 0x00000000, + /*0838*/ 0x00000000, + /*0839*/ 0x00000000, + /*083a*/ 0x00000104, + /*083b*/ 0x00082020, + /*083c*/ 0x08200820, + /*083d*/ 0x08200820, + /*083e*/ 0x08200820, + /*083f*/ 0x08200820, + /*0840*/ 0x08200820, + /*0841*/ 0x00000000, + /*0842*/ 0x00000000, + /*0843*/ 0x03000300, + /*0844*/ 0x03000300, + /*0845*/ 0x03000300, + /*0846*/ 0x03000300, + /*0847*/ 0x00000300, + /*0848*/ 0x00000000, + /*0849*/ 0x00000000, + /*084a*/ 0x00000000, + /*084b*/ 0x00000000, + /*084c*/ 0x00000000, + /*084d*/ 0x00a000a0, + /*084e*/ 0x00a000a0, + /*084f*/ 0x00a000a0, + /*0850*/ 0x00a000a0, + /*0851*/ 0x00a000a0, + /*0852*/ 0x00a000a0, + /*0853*/ 0x00a000a0, + /*0854*/ 0x00a000a0, + /*0855*/ 0x00a000a0, + /*0856*/ 0x01040119, + /*0857*/ 0x00000200, + /*0858*/ 0x01000000, + /*0859*/ 0x00000200, + /*085a*/ 0x00000004, + /*085b*/ 0x4041a151, + /*085c*/ 0x0141c0a0, + /*085d*/ 0x0000c0c0, + /*085e*/ 0x0e0c000e, + /*085f*/ 0x10001000, + /*0860*/ 0x0c073e42, + /*0861*/ 0x000f0c28, + /*0862*/ 0x00e00140, + /*0863*/ 0x000c0020, + /*0864*/ 0x00000203 +}; + +static const uint32_t DDR_PHY_ADR_V_REGSET_M3N[DDR_PHY_ADR_V_REGSET_NUM_M3N] = { + /*0a00*/ 0x00000000, + /*0a01*/ 0x00000000, + /*0a02*/ 0x00000000, + /*0a03*/ 0x00000000, + /*0a04*/ 0x00000000, + /*0a05*/ 0x00000000, + /*0a06*/ 0x00000000, + /*0a07*/ 0x01000000, + /*0a08*/ 0x00020000, + /*0a09*/ 0x00000000, + /*0a0a*/ 0x00000000, + /*0a0b*/ 0x00000000, + /*0a0c*/ 0x00400000, + /*0a0d*/ 0x00000080, + /*0a0e*/ 0x00dcba98, + /*0a0f*/ 0x03000000, + /*0a10*/ 0x00000200, + /*0a11*/ 0x00000000, + /*0a12*/ 0x00000000, + /*0a13*/ 0x00000000, + /*0a14*/ 0x0000002a, + /*0a15*/ 0x00000015, + /*0a16*/ 0x00000015, + /*0a17*/ 0x0000002a, + /*0a18*/ 0x00000033, + /*0a19*/ 0x0000000c, + /*0a1a*/ 0x0000000c, + /*0a1b*/ 0x00000033, + /*0a1c*/ 0x0a418820, + /*0a1d*/ 0x003f0000, + /*0a1e*/ 0x0000013f, + /*0a1f*/ 0x0002c06e, + /*0a20*/ 0x02c002c0, + /*0a21*/ 0x02c002c0, + /*0a22*/ 0x000002c0, + /*0a23*/ 0x42080010, + /*0a24*/ 0x0000033e +}; + +static const uint32_t DDR_PHY_ADR_I_REGSET_M3N[DDR_PHY_ADR_I_REGSET_NUM_M3N] = { + /*0a80*/ 0x00000000, + /*0a81*/ 0x00000000, + /*0a82*/ 0x00000000, + /*0a83*/ 0x00000000, + /*0a84*/ 0x00000000, + /*0a85*/ 0x00000000, + /*0a86*/ 0x00000000, + /*0a87*/ 0x01000000, + /*0a88*/ 0x00020000, + /*0a89*/ 0x00000000, + /*0a8a*/ 0x00000000, + /*0a8b*/ 0x00000000, + /*0a8c*/ 0x00400000, + /*0a8d*/ 0x00000080, + /*0a8e*/ 0x00000000, + /*0a8f*/ 0x03000000, + /*0a90*/ 0x00000200, + /*0a91*/ 0x00000000, + /*0a92*/ 0x00000000, + /*0a93*/ 0x00000000, + /*0a94*/ 0x0000002a, + /*0a95*/ 0x00000015, + /*0a96*/ 0x00000015, + /*0a97*/ 0x0000002a, + /*0a98*/ 0x00000033, + /*0a99*/ 0x0000000c, + /*0a9a*/ 0x0000000c, + /*0a9b*/ 0x00000033, + /*0a9c*/ 0x00000000, + /*0a9d*/ 0x00000000, + /*0a9e*/ 0x00000000, + /*0a9f*/ 0x0002c06e, + /*0aa0*/ 0x02c002c0, + /*0aa1*/ 0x02c002c0, + /*0aa2*/ 0x000002c0, + /*0aa3*/ 0x42080010, + /*0aa4*/ 0x0000033e +}; + +static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = { + /*0b80*/ 0x00000000, + /*0b81*/ 0x00000100, + /*0b82*/ 0x00000000, + /*0b83*/ 0x00050000, + /*0b84*/ 0x00000000, + /*0b85*/ 0x0004000f, + /*0b86*/ 0x00280080, + /*0b87*/ 0x02005502, + /*0b88*/ 0x00000000, + /*0b89*/ 0x00000000, + /*0b8a*/ 0x00000000, + /*0b8b*/ 0x00000050, + /*0b8c*/ 0x00000000, + /*0b8d*/ 0x01010100, + /*0b8e*/ 0x00010000, + /*0b8f*/ 0x00000000, + /*0b90*/ 0x00000101, + /*0b91*/ 0x00000000, + /*0b92*/ 0x00000000, + /*0b93*/ 0x00000000, + /*0b94*/ 0x00000000, + /*0b95*/ 0x00005064, + /*0b96*/ 0x01421142, + /*0b97*/ 0x00000142, + /*0b98*/ 0x00000000, + /*0b99*/ 0x000f1600, + /*0b9a*/ 0x0f160f16, + /*0b9b*/ 0x0f160f16, + /*0b9c*/ 0x00000003, + /*0b9d*/ 0x0002c000, + /*0b9e*/ 0x02c002c0, + /*0b9f*/ 0x000002c0, + /*0ba0*/ 0x08040201, + /*0ba1*/ 0x03421342, + /*0ba2*/ 0x00000342, + /*0ba3*/ 0x00000000, + /*0ba4*/ 0x00000000, + /*0ba5*/ 0x05030000, + /*0ba6*/ 0x00010700, + /*0ba7*/ 0x00000014, + /*0ba8*/ 0x00027f6e, + /*0ba9*/ 0x047f027f, + /*0baa*/ 0x00027f6e, + /*0bab*/ 0x00047f6e, + /*0bac*/ 0x0003554f, + /*0bad*/ 0x0001554f, + /*0bae*/ 0x0001554f, + /*0baf*/ 0x0001554f, + /*0bb0*/ 0x0001554f, + /*0bb1*/ 0x00003fee, + /*0bb2*/ 0x0001554f, + /*0bb3*/ 0x00003fee, + /*0bb4*/ 0x0001554f, + /*0bb5*/ 0x00027f6e, + /*0bb6*/ 0x0001554f, + /*0bb7*/ 0x00004011, + /*0bb8*/ 0x00004410, + /*0bb9*/ 0x00000000, + /*0bba*/ 0x00000000, + /*0bbb*/ 0x00000000, + /*0bbc*/ 0x00000265, + /*0bbd*/ 0x00000000, + /*0bbe*/ 0x00040401, + /*0bbf*/ 0x00000000, + /*0bc0*/ 0x03000000, + /*0bc1*/ 0x00000020, + /*0bc2*/ 0x00000000, + /*0bc3*/ 0x00000000, + /*0bc4*/ 0x04102006, + /*0bc5*/ 0x00041020, + /*0bc6*/ 0x01c98c98, + /*0bc7*/ 0x00400000, + /*0bc8*/ 0x00000000, + /*0bc9*/ 0x0001ffff, + /*0bca*/ 0x00000000, + /*0bcb*/ 0x00000000, + /*0bcc*/ 0x00000001, + /*0bcd*/ 0x00000000, + /*0bce*/ 0x00000000, + /*0bcf*/ 0x00000000, + /*0bd0*/ 0x76543210, + /*0bd1*/ 0x06010198, + /*0bd2*/ 0x00000000, + /*0bd3*/ 0x00000000, + /*0bd4*/ 0x04070000, + /*0bd5*/ 0x00000001, + /*0bd6*/ 0x00000f00 +}; + +static const uint32_t DDR_PI_REGSET_M3N[DDR_PI_REGSET_NUM_M3N] = { + /*0200*/ 0x00000b00, + /*0201*/ 0x00000101, + /*0202*/ 0x01640000, + /*0203*/ 0x00000014, + /*0204*/ 0x00000014, + /*0205*/ 0x00000014, + /*0206*/ 0x00000014, + /*0207*/ 0x00000000, + /*0208*/ 0x00000000, + /*0209*/ 0x0000ffff, + /*020a*/ 0x00000000, + /*020b*/ 0x0000ffff, + /*020c*/ 0x00000000, + /*020d*/ 0x0000ffff, + /*020e*/ 0x0000304c, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x00000200, + /*0212*/ 0x00000200, + /*0213*/ 0x0000304c, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00000200, + /*0217*/ 0x00000200, + /*0218*/ 0x0000304c, + /*0219*/ 0x00000200, + /*021a*/ 0x00000200, + /*021b*/ 0x00000200, + /*021c*/ 0x00000200, + /*021d*/ 0x00010000, + /*021e*/ 0x00000003, + /*021f*/ 0x01000001, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x00000000, + /*022a*/ 0x00000000, + /*022b*/ 0x00000000, + /*022c*/ 0x00000000, + /*022d*/ 0x00000000, + /*022e*/ 0x00000000, + /*022f*/ 0x00000000, + /*0230*/ 0x0f000101, + /*0231*/ 0x084d3129, + /*0232*/ 0x0e0c0004, + /*0233*/ 0x000e5000, + /*0234*/ 0x01000250, + /*0235*/ 0x00000003, + /*0236*/ 0x00000046, + /*0237*/ 0x000000cf, + /*0238*/ 0x00001826, + /*0239*/ 0x000000cf, + /*023a*/ 0x00001826, + /*023b*/ 0x00000000, + /*023c*/ 0x00000000, + /*023d*/ 0x00000000, + /*023e*/ 0x00000000, + /*023f*/ 0x00000000, + /*0240*/ 0x00000000, + /*0241*/ 0x00000000, + /*0242*/ 0x00000000, + /*0243*/ 0x00000000, + /*0244*/ 0x00000000, + /*0245*/ 0x01000000, + /*0246*/ 0x00040404, + /*0247*/ 0x01280a00, + /*0248*/ 0x00000001, + /*0249*/ 0x00000000, + /*024a*/ 0x03000f00, + /*024b*/ 0x00200020, + /*024c*/ 0x00000020, + /*024d*/ 0x00000000, + /*024e*/ 0x00000000, + /*024f*/ 0x00010002, + /*0250*/ 0x01010001, + /*0251*/ 0x02010100, + /*0252*/ 0x08040402, + /*0253*/ 0x00000008, + /*0254*/ 0x00000000, + /*0255*/ 0x04080803, + /*0256*/ 0x00001515, + /*0257*/ 0x00000000, + /*0258*/ 0x000000aa, + /*0259*/ 0x00000055, + /*025a*/ 0x000000b5, + /*025b*/ 0x0000004a, + /*025c*/ 0x00000056, + /*025d*/ 0x000000a9, + /*025e*/ 0x000000a9, + /*025f*/ 0x000000b5, + /*0260*/ 0x00000000, + /*0261*/ 0x00000000, + /*0262*/ 0x0f000000, + /*0263*/ 0x00001e0f, + /*0264*/ 0x000007d0, + /*0265*/ 0x01000300, + /*0266*/ 0x00000100, + /*0267*/ 0x00000000, + /*0268*/ 0x00000000, + /*0269*/ 0x01000000, + /*026a*/ 0x00010101, + /*026b*/ 0x000e0e0e, + /*026c*/ 0x000c0c0c, + /*026d*/ 0x01060601, + /*026e*/ 0x04041717, + /*026f*/ 0x00000004, + /*0270*/ 0x00000300, + /*0271*/ 0x17030000, + /*0272*/ 0x00060018, + /*0273*/ 0x00160028, + /*0274*/ 0x00160028, + /*0275*/ 0x00000000, + /*0276*/ 0x00000000, + /*0277*/ 0x00000000, + /*0278*/ 0x0a000000, + /*0279*/ 0x00010a14, + /*027a*/ 0x00030005, + /*027b*/ 0x0003018d, + /*027c*/ 0x000a018d, + /*027d*/ 0x00060100, + /*027e*/ 0x01000006, + /*027f*/ 0x018e018e, + /*0280*/ 0x018e0100, + /*0281*/ 0x1e1a018e, + /*0282*/ 0x1e1a1e1a, + /*0283*/ 0x01010204, + /*0284*/ 0x06501001, + /*0285*/ 0x090d0a07, + /*0286*/ 0x090d0a07, + /*0287*/ 0x0811180f, + /*0288*/ 0x00ff1102, + /*0289*/ 0x00ff1000, + /*028a*/ 0x00ff1000, + /*028b*/ 0x04041000, + /*028c*/ 0x18020100, + /*028d*/ 0x01010018, + /*028e*/ 0x005f005f, + /*028f*/ 0x005f005f, + /*0290*/ 0x050f0000, + /*0291*/ 0x051e051e, + /*0292*/ 0x0c01021e, + /*0293*/ 0x00000c0c, + /*0294*/ 0x00003400, + /*0295*/ 0x00000000, + /*0296*/ 0x00000000, + /*0297*/ 0x00000000, + /*0298*/ 0x00000000, + /*0299*/ 0x002e00d4, + /*029a*/ 0x11360031, + /*029b*/ 0x00d41611, + /*029c*/ 0x0031002e, + /*029d*/ 0x16111136, + /*029e*/ 0x002e00d4, + /*029f*/ 0x11360031, + /*02a0*/ 0x00001611, + /*02a1*/ 0x002e00d4, + /*02a2*/ 0x11360031, + /*02a3*/ 0x00d41611, + /*02a4*/ 0x0031002e, + /*02a5*/ 0x16111136, + /*02a6*/ 0x002e00d4, + /*02a7*/ 0x11360031, + /*02a8*/ 0x00001611, + /*02a9*/ 0x002e00d4, + /*02aa*/ 0x11360031, + /*02ab*/ 0x00d41611, + /*02ac*/ 0x0031002e, + /*02ad*/ 0x16111136, + /*02ae*/ 0x002e00d4, + /*02af*/ 0x11360031, + /*02b0*/ 0x00001611, + /*02b1*/ 0x002e00d4, + /*02b2*/ 0x11360031, + /*02b3*/ 0x00d41611, + /*02b4*/ 0x0031002e, + /*02b5*/ 0x16111136, + /*02b6*/ 0x002e00d4, + /*02b7*/ 0x11360031, + /*02b8*/ 0x00001611, + /*02b9*/ 0x00018d00, + /*02ba*/ 0x018d018d, + /*02bb*/ 0x1d220c08, + /*02bc*/ 0x00001f12, + /*02bd*/ 0x4301b344, + /*02be*/ 0x17032006, + /*02bf*/ 0x220c1010, + /*02c0*/ 0x001f121d, + /*02c1*/ 0x4301b344, + /*02c2*/ 0x17062006, + /*02c3*/ 0x220c1010, + /*02c4*/ 0x001f121d, + /*02c5*/ 0x4301b344, + /*02c6*/ 0x17182006, + /*02c7*/ 0x00021010, + /*02c8*/ 0x00020002, + /*02c9*/ 0x00020002, + /*02ca*/ 0x00020002, + /*02cb*/ 0x00020002, + /*02cc*/ 0x00000002, + /*02cd*/ 0x00000000, + /*02ce*/ 0x00000000, + /*02cf*/ 0x00000000, + /*02d0*/ 0x00000000, + /*02d1*/ 0x00000000, + /*02d2*/ 0x00000000, + /*02d3*/ 0x00000000, + /*02d4*/ 0x00000000, + /*02d5*/ 0x00000000, + /*02d6*/ 0x00000000, + /*02d7*/ 0x00000000, + /*02d8*/ 0x00000000, + /*02d9*/ 0x00000400, + /*02da*/ 0x15141312, + /*02db*/ 0x11100f0e, + /*02dc*/ 0x080b0c0d, + /*02dd*/ 0x05040a09, + /*02de*/ 0x01000706, + /*02df*/ 0x00000302, + /*02e0*/ 0x01030201, + /*02e1*/ 0x00304c08, + /*02e2*/ 0x0001e2f8, + /*02e3*/ 0x0000304c, + /*02e4*/ 0x0001e2f8, + /*02e5*/ 0x0000304c, + /*02e6*/ 0x0001e2f8, + /*02e7*/ 0x08000000, + /*02e8*/ 0x00000100, + /*02e9*/ 0x00000000, + /*02ea*/ 0x00000000, + /*02eb*/ 0x00000000, + /*02ec*/ 0x00000000, + /*02ed*/ 0x00010000, + /*02ee*/ 0x00000000, + /*02ef*/ 0x00000000, + /*02f0*/ 0x00000000, + /*02f1*/ 0x00000000, + /*02f2*/ 0x00000000, + /*02f3*/ 0x00000000, + /*02f4*/ 0x00000000, + /*02f5*/ 0x00000000, + /*02f6*/ 0x00000000, + /*02f7*/ 0x00000000, + /*02f8*/ 0x00000000, + /*02f9*/ 0x00000000, + /*02fa*/ 0x00000000, + /*02fb*/ 0x00000000, + /*02fc*/ 0x00000000, + /*02fd*/ 0x00000000, + /*02fe*/ 0x00000000, + /*02ff*/ 0x00000000, + /*0300*/ 0x00000000, + /*0301*/ 0x00000000, + /*0302*/ 0x00000000, + /*0303*/ 0x00000000, + /*0304*/ 0x00000000, + /*0305*/ 0x00000000, + /*0306*/ 0x00000000, + /*0307*/ 0x00000000, + /*0308*/ 0x00000000, + /*0309*/ 0x00000000, + /*030a*/ 0x00000000, + /*030b*/ 0x00000000, + /*030c*/ 0x00000000, + /*030d*/ 0x00000000, + /*030e*/ 0x00000000, + /*030f*/ 0x00050002, + /*0310*/ 0x015c0057, + /*0311*/ 0x01000100, + /*0312*/ 0x01020001, + /*0313*/ 0x00010300, + /*0314*/ 0x05000104, + /*0315*/ 0x01060001, + /*0316*/ 0x00010700, + /*0317*/ 0x00000000, + /*0318*/ 0x00000000, + /*0319*/ 0x00000001, + /*031a*/ 0x00000000, + /*031b*/ 0x00000000, + /*031c*/ 0x00000000, + /*031d*/ 0x20080101 +}; diff --git a/drivers/renesas/rcar/ddr/ddr_regs.h b/drivers/renesas/rcar/ddr/ddr_regs.h new file mode 100644 index 000000000..ba26c69c8 --- /dev/null +++ b/drivers/renesas/rcar/ddr/ddr_regs.h @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOOT_INIT_DRAM_REGDEF_H_ +#define BOOT_INIT_DRAM_REGDEF_H_ + +/* DBSC registers */ +#define DBSC_DBSYSCONF0 0xE6790000U +#define DBSC_DBSYSCONF1 0xE6790004U +#define DBSC_DBPHYCONF0 0xE6790010U +#define DBSC_DBKIND 0xE6790020U +#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) +#define DBSC_DBMEMCONF_0_0 0xE6790030U +#define DBSC_DBMEMCONF_0_1 0xE6790034U +#define DBSC_DBMEMCONF_0_2 0xE6790038U +#define DBSC_DBMEMCONF_0_3 0xE679003CU +#define DBSC_DBMEMCONF_1_2 0xE6790048U +#define DBSC_DBMEMCONF_1_3 0xE679004CU +#define DBSC_DBMEMCONF_1_0 0xE6790040U +#define DBSC_DBMEMCONF_1_1 0xE6790044U +#define DBSC_DBMEMCONF_2_0 0xE6790050U +#define DBSC_DBMEMCONF_2_1 0xE6790054U +#define DBSC_DBMEMCONF_2_2 0xE6790058U +#define DBSC_DBMEMCONF_2_3 0xE679005CU +#define DBSC_DBMEMCONF_3_0 0xE6790060U +#define DBSC_DBMEMCONF_3_1 0xE6790064U +#define DBSC_DBMEMCONF_3_2 0xE6790068U +#define DBSC_DBMEMCONF_3_3 0xE679006CU +#define DBSC_DBSYSCNT0 0xE6790100U +#define DBSC_DBSVCR1 0xE6790104U +#define DBSC_DBSTATE0 0xE6790108U +#define DBSC_DBSTATE1 0xE679010CU +#define DBSC_DBINTEN 0xE6790180U +#define DBSC_DBINTSTAT0 0xE6790184U +#define DBSC_DBACEN 0xE6790200U +#define DBSC_DBRFEN 0xE6790204U +#define DBSC_DBCMD 0xE6790208U +#define DBSC_DBWAIT 0xE6790210U +#define DBSC_DBSYSCTRL0 0xE6790280U +#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x)) +#define DBSC_DBTR0 0xE6790300U +#define DBSC_DBTR1 0xE6790304U +#define DBSC_DBTR2 0xE6790308U +#define DBSC_DBTR3 0xE679030CU +#define DBSC_DBTR4 0xE6790310U +#define DBSC_DBTR5 0xE6790314U +#define DBSC_DBTR6 0xE6790318U +#define DBSC_DBTR7 0xE679031CU +#define DBSC_DBTR8 0xE6790320U +#define DBSC_DBTR9 0xE6790324U +#define DBSC_DBTR10 0xE6790328U +#define DBSC_DBTR11 0xE679032CU +#define DBSC_DBTR12 0xE6790330U +#define DBSC_DBTR13 0xE6790334U +#define DBSC_DBTR14 0xE6790338U +#define DBSC_DBTR15 0xE679033CU +#define DBSC_DBTR16 0xE6790340U +#define DBSC_DBTR17 0xE6790344U +#define DBSC_DBTR18 0xE6790348U +#define DBSC_DBTR19 0xE679034CU +#define DBSC_DBTR20 0xE6790350U +#define DBSC_DBTR21 0xE6790354U +#define DBSC_DBTR22 0xE6790358U +#define DBSC_DBTR23 0xE679035CU +#define DBSC_DBTR24 0xE6790360U +#define DBSC_DBTR25 0xE6790364U +#define DBSC_DBTR26 0xE6790368U +#define DBSC_DBBL 0xE6790400U +#define DBSC_DBRFCNF1 0xE6790414U +#define DBSC_DBRFCNF2 0xE6790418U +#define DBSC_DBTSPCNF 0xE6790420U +#define DBSC_DBCALCNF 0xE6790424U +#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x)) +#define DBSC_DBRNK2 0xE6790438U +#define DBSC_DBRNK3 0xE679043CU +#define DBSC_DBRNK4 0xE6790440U +#define DBSC_DBRNK5 0xE6790444U +#define DBSC_DBPDNCNF 0xE6790450U +#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x)) +#define DBSC_DBODT0 0xE6790460U +#define DBSC_DBODT1 0xE6790464U +#define DBSC_DBODT2 0xE6790468U +#define DBSC_DBODT3 0xE679046CU +#define DBSC_DBODT4 0xE6790470U +#define DBSC_DBODT5 0xE6790474U +#define DBSC_DBODT6 0xE6790478U +#define DBSC_DBODT7 0xE679047CU +#define DBSC_DBADJ0 0xE6790500U +#define DBSC_DBDBICNT 0xE6790518U +#define DBSC_DBDFIPMSTRCNF 0xE6790520U +#define DBSC_DBDFICUPDCNF 0xE679052CU +#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch)) +#define DBSC_DBDFISTAT_0 0xE6790600U +#define DBSC_DBDFISTAT_1 0xE6790640U +#define DBSC_DBDFISTAT_2 0xE6790680U +#define DBSC_DBDFISTAT_3 0xE67906C0U +#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch)) +#define DBSC_DBDFICNT_0 0xE6790604U +#define DBSC_DBDFICNT_1 0xE6790644U +#define DBSC_DBDFICNT_2 0xE6790684U +#define DBSC_DBDFICNT_3 0xE67906C4U +#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch)) +#define DBSC_DBPDCNT0_0 0xE6790610U +#define DBSC_DBPDCNT0_1 0xE6790650U +#define DBSC_DBPDCNT0_2 0xE6790690U +#define DBSC_DBPDCNT0_3 0xE67906D0U +#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch)) +#define DBSC_DBPDCNT1_0 0xE6790614U +#define DBSC_DBPDCNT1_1 0xE6790654U +#define DBSC_DBPDCNT1_2 0xE6790694U +#define DBSC_DBPDCNT1_3 0xE67906D4U +#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch)) +#define DBSC_DBPDCNT2_0 0xE6790618U +#define DBSC_DBPDCNT2_1 0xE6790658U +#define DBSC_DBPDCNT2_2 0xE6790698U +#define DBSC_DBPDCNT2_3 0xE67906D8U +#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch)) +#define DBSC_DBPDCNT3_0 0xE679061CU +#define DBSC_DBPDCNT3_1 0xE679065CU +#define DBSC_DBPDCNT3_2 0xE679069CU +#define DBSC_DBPDCNT3_3 0xE67906DCU +#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch)) +#define DBSC_DBPDLK_0 0xE6790620U +#define DBSC_DBPDLK_1 0xE6790660U +#define DBSC_DBPDLK_2 0xE67906a0U +#define DBSC_DBPDLK_3 0xE67906e0U +#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch)) +#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch)) +#define DBSC_DBPDRGA_0 0xE6790624U +#define DBSC_DBPDRGD_0 0xE6790628U +#define DBSC_DBPDRGA_1 0xE6790664U +#define DBSC_DBPDRGD_1 0xE6790668U +#define DBSC_DBPDRGA_2 0xE67906A4U +#define DBSC_DBPDRGD_2 0xE67906A8U +#define DBSC_DBPDRGA_3 0xE67906E4U +#define DBSC_DBPDRGD_3 0xE67906E8U +#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch)) +#define DBSC_DBPDSTAT_0 0xE6790630U +#define DBSC_DBPDSTAT_1 0xE6790670U +#define DBSC_DBPDSTAT_2 0xE67906B0U +#define DBSC_DBPDSTAT_3 0xE67906F0U +#define DBSC_DBBUS0CNF0 0xE6790800U +#define DBSC_DBBUS0CNF1 0xE6790804U +#define DBSC_DBCAM0CNF1 0xE6790904U +#define DBSC_DBCAM0CNF2 0xE6790908U +#define DBSC_DBCAM0CNF3 0xE679090CU +#define DBSC_DBBSWAP 0xE67909F0U +#define DBSC_DBBCAMDIS 0xE67909FCU +#define DBSC_DBSCHCNT0 0xE6791000U +#define DBSC_DBSCHCNT1 0xE6791004U +#define DBSC_DBSCHSZ0 0xE6791010U +#define DBSC_DBSCHRW0 0xE6791020U +#define DBSC_DBSCHRW1 0xE6791024U +#define DBSC_DBSCHQOS_0(x) (0xE6791030U + 0x10U * (x)) +#define DBSC_DBSCHQOS_1(x) (0xE6791034U + 0x10U * (x)) +#define DBSC_DBSCHQOS_2(x) (0xE6791038U + 0x10U * (x)) +#define DBSC_DBSCHQOS_3(x) (0xE679103CU + 0x10U * (x)) +#define DBSC_DBSCHQOS00 0xE6791030U +#define DBSC_DBSCHQOS01 0xE6791034U +#define DBSC_DBSCHQOS02 0xE6791038U +#define DBSC_DBSCHQOS03 0xE679103CU +#define DBSC_DBSCHQOS10 0xE6791040U +#define DBSC_DBSCHQOS11 0xE6791044U +#define DBSC_DBSCHQOS12 0xE6791048U +#define DBSC_DBSCHQOS13 0xE679104CU +#define DBSC_DBSCHQOS20 0xE6791050U +#define DBSC_DBSCHQOS21 0xE6791054U +#define DBSC_DBSCHQOS22 0xE6791058U +#define DBSC_DBSCHQOS23 0xE679105CU +#define DBSC_DBSCHQOS30 0xE6791060U +#define DBSC_DBSCHQOS31 0xE6791064U +#define DBSC_DBSCHQOS32 0xE6791068U +#define DBSC_DBSCHQOS33 0xE679106CU +#define DBSC_DBSCHQOS40 0xE6791070U +#define DBSC_DBSCHQOS41 0xE6791074U +#define DBSC_DBSCHQOS42 0xE6791078U +#define DBSC_DBSCHQOS43 0xE679107CU +#define DBSC_DBSCHQOS50 0xE6791080U +#define DBSC_DBSCHQOS51 0xE6791084U +#define DBSC_DBSCHQOS52 0xE6791088U +#define DBSC_DBSCHQOS53 0xE679108CU +#define DBSC_DBSCHQOS60 0xE6791090U +#define DBSC_DBSCHQOS61 0xE6791094U +#define DBSC_DBSCHQOS62 0xE6791098U +#define DBSC_DBSCHQOS63 0xE679109CU +#define DBSC_DBSCHQOS70 0xE67910A0U +#define DBSC_DBSCHQOS71 0xE67910A4U +#define DBSC_DBSCHQOS72 0xE67910A8U +#define DBSC_DBSCHQOS73 0xE67910ACU +#define DBSC_DBSCHQOS80 0xE67910B0U +#define DBSC_DBSCHQOS81 0xE67910B4U +#define DBSC_DBSCHQOS82 0xE67910B8U +#define DBSC_DBSCHQOS83 0xE67910BCU +#define DBSC_DBSCHQOS90 0xE67910C0U +#define DBSC_DBSCHQOS91 0xE67910C4U +#define DBSC_DBSCHQOS92 0xE67910C8U +#define DBSC_DBSCHQOS93 0xE67910CCU +#define DBSC_DBSCHQOS100 0xE67910D0U +#define DBSC_DBSCHQOS101 0xE67910D4U +#define DBSC_DBSCHQOS102 0xE67910D8U +#define DBSC_DBSCHQOS103 0xE67910DCU +#define DBSC_DBSCHQOS110 0xE67910E0U +#define DBSC_DBSCHQOS111 0xE67910E4U +#define DBSC_DBSCHQOS112 0xE67910E8U +#define DBSC_DBSCHQOS113 0xE67910ECU +#define DBSC_DBSCHQOS120 0xE67910F0U +#define DBSC_DBSCHQOS121 0xE67910F4U +#define DBSC_DBSCHQOS122 0xE67910F8U +#define DBSC_DBSCHQOS123 0xE67910FCU +#define DBSC_DBSCHQOS130 0xE6791100U +#define DBSC_DBSCHQOS131 0xE6791104U +#define DBSC_DBSCHQOS132 0xE6791108U +#define DBSC_DBSCHQOS133 0xE679110CU +#define DBSC_DBSCHQOS140 0xE6791110U +#define DBSC_DBSCHQOS141 0xE6791114U +#define DBSC_DBSCHQOS142 0xE6791118U +#define DBSC_DBSCHQOS143 0xE679111CU +#define DBSC_DBSCHQOS150 0xE6791120U +#define DBSC_DBSCHQOS151 0xE6791124U +#define DBSC_DBSCHQOS152 0xE6791128U +#define DBSC_DBSCHQOS153 0xE679112CU +#define DBSC_DBSCTR0 0xE6791700U +#define DBSC_DBSCTR1 0xE6791708U +#define DBSC_DBSCHRW2 0xE679170CU +#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x)) +#define DBSC_SCFCTST0 0xE6791700U +#define DBSC_SCFCTST1 0xE6791708U +#define DBSC_SCFCTST2 0xE679170CU +#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab)) +#define DBSC_DBMRRDR_0 0xE6791800U +#define DBSC_DBMRRDR_1 0xE6791804U +#define DBSC_DBMRRDR_2 0xE6791808U +#define DBSC_DBMRRDR_3 0xE679180CU +#define DBSC_DBMRRDR_4 0xE6791810U +#define DBSC_DBMRRDR_5 0xE6791814U +#define DBSC_DBMRRDR_6 0xE6791818U +#define DBSC_DBMRRDR_7 0xE679181CU +#define DBSC_DBMEMSWAPCONF0 0xE6792000U + +/* CPG registers */ +#define CPG_BASE 0xE6150000U +#define CPG_FRQCRB (CPG_BASE + 0x0004U) +#define CPG_PLLECR (CPG_BASE + 0x00D0U) +#define CPG_MSTPSR5 (CPG_BASE + 0x003CU) +#define CPG_SRCR4 (CPG_BASE + 0x00BCU) +#define CPG_PLL3CR (CPG_BASE + 0x00DCU) +#define CPG_ZB3CKCR (CPG_BASE + 0x0380U) +#define CPG_FRQCRD (CPG_BASE + 0x00E4U) +#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) +#define CPG_CPGWPR (CPG_BASE + 0x0900U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U) + +#endif /* BOOT_INIT_DRAM_REGDEF_H_*/ diff --git a/drivers/renesas/rcar/ddr/dram_sub_func.c b/drivers/renesas/rcar/ddr/dram_sub_func.c new file mode 100644 index 000000000..ab8eabbc6 --- /dev/null +++ b/drivers/renesas/rcar/ddr/dram_sub_func.c @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include "dram_sub_func.h" +#include "rcar_def.h" + +#if RCAR_SYSTEM_SUSPEND +/* Local defines */ +#define DRAM_BACKUP_GPIO_USE 0 +#include "iic_dvfs.h" +#if PMIC_ROHM_BD9571 +#define PMIC_SLAVE_ADDR 0x30U +#define PMIC_BKUP_MODE_CNT 0x20U +#define PMIC_QLLM_CNT 0x27U +#define BIT_BKUP_CTRL_OUT BIT(4) +#define BIT_QLLM_DDR0_EN BIT(0) +#define BIT_QLLM_DDR1_EN BIT(1) +#endif + +#define GPIO_BKUP_REQB_SHIFT_SALVATOR 9U /* GP1_9 (BKUP_REQB) */ +#define GPIO_BKUP_TRG_SHIFT_SALVATOR 8U /* GP1_8 (BKUP_TRG) */ +#define GPIO_BKUP_REQB_SHIFT_EBISU 14U /* GP6_14(BKUP_REQB) */ +#define GPIO_BKUP_TRG_SHIFT_EBISU 13U /* GP6_13(BKUP_TRG) */ +#define GPIO_BKUP_REQB_SHIFT_CONDOR 1U /* GP3_1 (BKUP_REQB) */ +#define GPIO_BKUP_TRG_SHIFT_CONDOR 0U /* GP3_0 (BKUP_TRG) */ + +#define DRAM_BKUP_TRG_LOOP_CNT 1000U +#endif + +void rcar_dram_get_boot_status(uint32_t *status) +{ +#if RCAR_SYSTEM_SUSPEND + uint32_t reg_data; + uint32_t product; + uint32_t shift; + uint32_t gpio; + + product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + if (product == PRR_PRODUCT_V3H) { + shift = GPIO_BKUP_TRG_SHIFT_CONDOR; + gpio = GPIO_INDT3; + } else if (product == PRR_PRODUCT_E3) { + shift = GPIO_BKUP_TRG_SHIFT_EBISU; + gpio = GPIO_INDT6; + } else { + shift = GPIO_BKUP_TRG_SHIFT_SALVATOR; + gpio = GPIO_INDT1; + } + + reg_data = mmio_read_32(gpio); + if (reg_data & BIT(shift)) + *status = DRAM_BOOT_STATUS_WARM; + else + *status = DRAM_BOOT_STATUS_COLD; +#else /* RCAR_SYSTEM_SUSPEND */ + *status = DRAM_BOOT_STATUS_COLD; +#endif /* RCAR_SYSTEM_SUSPEND */ +} + +int32_t rcar_dram_update_boot_status(uint32_t status) +{ + int32_t ret = 0; +#if RCAR_SYSTEM_SUSPEND + uint32_t reg_data; +#if PMIC_ROHM_BD9571 +#if DRAM_BACKUP_GPIO_USE == 0 + uint8_t bkup_mode_cnt = 0U; +#else + uint32_t reqb, outd; +#endif + uint8_t qllm_cnt = 0U; + int32_t i2c_dvfs_ret = -1; +#endif + uint32_t loop_count; + uint32_t product; + uint32_t trg; + uint32_t gpio; + + product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + if (product == PRR_PRODUCT_V3H) { +#if DRAM_BACKUP_GPIO_USE == 1 + reqb = GPIO_BKUP_REQB_SHIFT_CONDOR; + outd = GPIO_OUTDT3; +#endif + trg = GPIO_BKUP_TRG_SHIFT_CONDOR; + gpio = GPIO_INDT3; + } else if (product == PRR_PRODUCT_E3) { +#if DRAM_BACKUP_GPIO_USE == 1 + reqb = GPIO_BKUP_REQB_SHIFT_EBISU; + outd = GPIO_OUTDT6; +#endif + trg = GPIO_BKUP_TRG_SHIFT_EBISU; + gpio = GPIO_INDT6; + } else { +#if DRAM_BACKUP_GPIO_USE == 1 + reqb = GPIO_BKUP_REQB_SHIFT_SALVATOR; + outd = GPIO_OUTDT1; +#endif + trg = GPIO_BKUP_TRG_SHIFT_SALVATOR; + gpio = GPIO_INDT1; + } + + if (status == DRAM_BOOT_STATUS_WARM) { +#if DRAM_BACKUP_GPIO_USE == 1 + mmio_setbits_32(outd, BIT(reqb)); +#else +#if PMIC_ROHM_BD9571 + /* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */ + i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR, + PMIC_BKUP_MODE_CNT, + &bkup_mode_cnt); + if (i2c_dvfs_ret) { + ERROR("BKUP mode cnt READ ERROR.\n"); + ret = DRAM_UPDATE_STATUS_ERR; + } else { + bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT; + i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR, + PMIC_BKUP_MODE_CNT, + bkup_mode_cnt); + if (i2c_dvfs_ret) { + ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", + bkup_mode_cnt); + ret = DRAM_UPDATE_STATUS_ERR; + } + } +#endif /* PMIC_ROHM_BD9571 */ +#endif /* DRAM_BACKUP_GPIO_USE == 1 */ + /* Wait BKUP_TRG=Low */ + loop_count = DRAM_BKUP_TRG_LOOP_CNT; + while (loop_count > 0) { + reg_data = mmio_read_32(gpio); + if (!(reg_data & BIT(trg))) + break; + loop_count--; + } + + if (!loop_count) { + ERROR("\nWarm booting...\n" + " The potential of BKUP_TRG did not switch to Low.\n" + " If you expect the operation of cold boot,\n" + " check the board configuration (ex, Dip-SW) and/or the H/W failure.\n"); + ret = DRAM_UPDATE_STATUS_ERR; + } + } +#if PMIC_ROHM_BD9571 + if (!ret) { + qllm_cnt = BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN; + i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR, + PMIC_QLLM_CNT, + qllm_cnt); + if (i2c_dvfs_ret) { + ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm_cnt); + ret = DRAM_UPDATE_STATUS_ERR; + } + } +#endif +#endif + return ret; +} diff --git a/drivers/renesas/rcar/ddr/dram_sub_func.h b/drivers/renesas/rcar/ddr/dram_sub_func.h new file mode 100644 index 000000000..69c4d8605 --- /dev/null +++ b/drivers/renesas/rcar/ddr/dram_sub_func.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRAM_SUB_FUNC_H +#define DRAM_SUB_FUNC_H + +#define DRAM_UPDATE_STATUS_ERR -1 +#define DRAM_BOOT_STATUS_COLD 0 +#define DRAM_BOOT_STATUS_WARM 1 + +int32_t rcar_dram_update_boot_status(uint32_t status); +void rcar_dram_get_boot_status(uint32_t *status); + +#endif /* DRAM_SUB_FUNC_H */ diff --git a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h b/drivers/staging/renesas/rcar/ddr/boot_init_dram.h deleted file mode 100644 index ac237b2ef..000000000 --- a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef BOOT_INIT_DRAM_H -#define BOOT_INIT_DRAM_H - -extern int32_t rcar_dram_init(void); - -#define INITDRAM_OK 0 -#define INITDRAM_NG 0xffffffff -#define INITDRAM_ERR_I 0xffffffff -#define INITDRAM_ERR_O 0xfffffffe -#define INITDRAM_ERR_T 0xfffffff0 - -#endif /* BOOT_INIT_DRAM_H */ diff --git a/drivers/staging/renesas/rcar/ddr/ddr.mk b/drivers/staging/renesas/rcar/ddr/ddr.mk deleted file mode 100644 index ed7adc339..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -ifeq (${RCAR_LSI},${RCAR_E3}) - include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk - BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c -else ifeq (${RCAR_LSI},${RCAR_D3}) - include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk -else ifeq (${RCAR_LSI},${RCAR_V3M}) - include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk -else - include drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk - BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c -endif diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h deleted file mode 100644 index 0f89b4350..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "../ddr_regs.h" diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk deleted file mode 100644 index aee27a59a..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -ifeq (${RCAR_LSI},${RCAR_E3}) -BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c -else ifeq (${RCAR_LSI},${RCAR_D3}) -BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c -else -BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c -endif diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c deleted file mode 100644 index a49510ed5..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c +++ /dev/null @@ -1,699 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include "rcar_def.h" -#include "../ddr_regs.h" - -#define RCAR_DDR_VERSION "rev.0.01" - -#if RCAR_LSI != RCAR_D3 -#error "Don't have DDR initialize routine." -#endif - -static void init_ddr_d3_1866(void) -{ - uint32_t i, r2, r3, r5, r6, r7, r12; - - mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); - mmio_write_32(DBSC_DBKIND, 0x00000007); - mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); - mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); - mmio_write_32(DBSC_DBTR0, 0x0000000D); - mmio_write_32(DBSC_DBTR1, 0x00000009); - mmio_write_32(DBSC_DBTR2, 0x00000000); - mmio_write_32(DBSC_DBTR3, 0x0000000D); - mmio_write_32(DBSC_DBTR4, 0x000D000D); - mmio_write_32(DBSC_DBTR5, 0x0000002D); - mmio_write_32(DBSC_DBTR6, 0x00000020); - mmio_write_32(DBSC_DBTR7, 0x00060006); - mmio_write_32(DBSC_DBTR8, 0x00000021); - mmio_write_32(DBSC_DBTR9, 0x00000007); - mmio_write_32(DBSC_DBTR10, 0x0000000E); - mmio_write_32(DBSC_DBTR11, 0x0000000C); - mmio_write_32(DBSC_DBTR12, 0x00140014); - mmio_write_32(DBSC_DBTR13, 0x000000F2); - mmio_write_32(DBSC_DBTR14, 0x00170006); - mmio_write_32(DBSC_DBTR15, 0x00060005); - mmio_write_32(DBSC_DBTR16, 0x09210507); - mmio_write_32(DBSC_DBTR17, 0x040E0000); - mmio_write_32(DBSC_DBTR18, 0x00000200); - mmio_write_32(DBSC_DBTR19, 0x012B004B); - mmio_write_32(DBSC_DBTR20, 0x020000FB); - mmio_write_32(DBSC_DBTR21, 0x00040004); - mmio_write_32(DBSC_DBBL, 0x00000000); - mmio_write_32(DBSC_DBODT0, 0x00000001); - mmio_write_32(DBSC_DBADJ0, 0x00000001); - mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); - mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); - mmio_write_32(DBSC_DBSCHRW1, 0x00000046); - mmio_write_32(DBSC_SCFCTST0, 0x0D020D04); - mmio_write_32(DBSC_SCFCTST1, 0x0306040C); - - mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); - mmio_write_32(DBSC_DBCMD, 0x01000001); - mmio_write_32(DBSC_DBCMD, 0x08000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); - mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); - mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); - mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); - mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - - mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E); - r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9; - r3 = (r2 << 16) + (r2 << 8) + r2; - r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; - mmio_write_32(DBSC_DBPDRGA_0, 0x00000011); - mmio_write_32(DBSC_DBPDRGD_0, r3); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000012); - mmio_write_32(DBSC_DBPDRGD_0, r3); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000016); - mmio_write_32(DBSC_DBPDRGD_0, r6); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000017); - mmio_write_32(DBSC_DBPDRGD_0, r6); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000018); - mmio_write_32(DBSC_DBPDRGD_0, r6); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000019); - mmio_write_32(DBSC_DBPDRGD_0, r6); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); - mmio_write_32(DBSC_DBCMD, 0x08000001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; - - if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); - - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | - ((r6 + (r5 << 1)) & 0xFF)); - } - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); - r2 = mmio_read_32(DBSC_DBPDRGD_0); - mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); - r2 = mmio_read_32(DBSC_DBPDRGD_0); - mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); - r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); - mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - - mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; - r12 = (r5 >> 0x2); - - if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | - ((r6 + r5 + - (r5 >> 1) + r12) & 0xFF)); - } - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) - ; - mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); - - mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); - mmio_write_32(DBSC_DBCALCNF, 0x0100401B); - mmio_write_32(DBSC_DBRFCNF1, 0x00080E23); - mmio_write_32(DBSC_DBRFCNF2, 0x00010000); - mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); - mmio_write_32(DBSC_DBRFEN, 0x00000001); - mmio_write_32(DBSC_DBACEN, 0x00000001); - mmio_write_32(DBSC_DBPDLK_0, 0x00000000); - mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); - -#ifdef ddr_qos_init_setting // only for non qos_init - mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); - mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); - mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); - mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); - mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); - mmio_write_32(DBSC_DBSCHRW0, 0x22421111); - mmio_write_32(DBSC_SCFCTST2, 0x012F1123); - mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); - mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); - mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); - mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); - mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); - mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); - mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); - mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS90, 0x00000300); - mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0); - mmio_write_32(DBSC_DBSCHQOS92, 0x00000200); - mmio_write_32(DBSC_DBSCHQOS93, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); - mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); - mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); - mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); - mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); - mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); - mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); - mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); - mmio_write_32(0xE67F0018, 0x00000001); - mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); -#endif -} - -static void init_ddr_d3_1600(void) -{ - uint32_t i, r2, r3, r5, r6, r7, r12; - - mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); - mmio_write_32(DBSC_DBKIND, 0x00000007); - mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); - mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); - mmio_write_32(DBSC_DBTR0, 0x0000000B); - mmio_write_32(DBSC_DBTR1, 0x00000008); - mmio_write_32(DBSC_DBTR2, 0x00000000); - mmio_write_32(DBSC_DBTR3, 0x0000000B); - mmio_write_32(DBSC_DBTR4, 0x000B000B); - mmio_write_32(DBSC_DBTR5, 0x00000027); - mmio_write_32(DBSC_DBTR6, 0x0000001C); - mmio_write_32(DBSC_DBTR7, 0x00060006); - mmio_write_32(DBSC_DBTR8, 0x00000020); - mmio_write_32(DBSC_DBTR9, 0x00000006); - mmio_write_32(DBSC_DBTR10, 0x0000000C); - mmio_write_32(DBSC_DBTR11, 0x0000000A); - mmio_write_32(DBSC_DBTR12, 0x00120012); - mmio_write_32(DBSC_DBTR13, 0x000000D0); - mmio_write_32(DBSC_DBTR14, 0x00140005); - mmio_write_32(DBSC_DBTR15, 0x00050004); - mmio_write_32(DBSC_DBTR16, 0x071F0305); - mmio_write_32(DBSC_DBTR17, 0x040C0000); - mmio_write_32(DBSC_DBTR18, 0x00000200); - mmio_write_32(DBSC_DBTR19, 0x01000040); - mmio_write_32(DBSC_DBTR20, 0x020000D8); - mmio_write_32(DBSC_DBTR21, 0x00040004); - mmio_write_32(DBSC_DBBL, 0x00000000); - mmio_write_32(DBSC_DBODT0, 0x00000001); - mmio_write_32(DBSC_DBADJ0, 0x00000001); - mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); - mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); - mmio_write_32(DBSC_DBSCHRW1, 0x00000046); - mmio_write_32(DBSC_SCFCTST0, 0x0D020C04); - mmio_write_32(DBSC_SCFCTST1, 0x0305040C); - - mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); - mmio_write_32(DBSC_DBCMD, 0x01000001); - mmio_write_32(DBSC_DBCMD, 0x08000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); - mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); - mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); - mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); - mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000098); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - - mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E); - r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9; - r3 = (r2 << 16) + (r2 << 8) + r2; - r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; - mmio_write_32(DBSC_DBPDRGA_0, 0x00000011); - mmio_write_32(DBSC_DBPDRGD_0, r3); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000012); - mmio_write_32(DBSC_DBPDRGD_0, r3); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000016); - mmio_write_32(DBSC_DBPDRGD_0, r6); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000017); - mmio_write_32(DBSC_DBPDRGD_0, r6); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000018); - mmio_write_32(DBSC_DBPDRGD_0, r6); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000019); - mmio_write_32(DBSC_DBPDRGD_0, r6); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); - mmio_write_32(DBSC_DBCMD, 0x08000001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; - if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); - - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | - ((r6 + (r5 << 1)) & 0xFF)); - } - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); - r2 = mmio_read_32(DBSC_DBPDRGD_0); - mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); - r2 = mmio_read_32(DBSC_DBPDRGD_0); - mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - - mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; - r12 = (r5 >> 0x2); - - if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | - ((r6 + r5 + - (r5 >> 1) + r12) & 0xFF)); - } - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) - ; - mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); - - mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); - mmio_write_32(DBSC_DBCALCNF, 0x0100401B); - mmio_write_32(DBSC_DBRFCNF1, 0x00080C30); - mmio_write_32(DBSC_DBRFCNF2, 0x00010000); - mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); - mmio_write_32(DBSC_DBRFEN, 0x00000001); - mmio_write_32(DBSC_DBACEN, 0x00000001); - mmio_write_32(DBSC_DBPDLK_0, 0x00000000); - mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); - -#ifdef ddr_qos_init_setting // only for non qos_init - mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); - mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); - mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); - mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); - mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); - mmio_write_32(DBSC_DBSCHRW0, 0x22421111); - mmio_write_32(DBSC_SCFCTST2, 0x012F1123); - mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); - mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); - mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); - mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); - mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); - mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); - mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); - mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS90, 0x00000300); - mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0); - mmio_write_32(DBSC_DBSCHQOS92, 0x00000200); - mmio_write_32(DBSC_DBSCHQOS93, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); - mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); - mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); - mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); - mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); - mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); - mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); - mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); - mmio_write_32(0xE67F0018, 0x00000001); - mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); -#endif -} - -#define PRR 0xFFF00044U -#define PRR_PRODUCT_MASK 0x00007F00U -#define PRR_PRODUCT_D3 0x00005800U - -#define MODEMR_MD19 BIT(19) - -int32_t rcar_dram_init(void) -{ - uint32_t reg; - uint32_t ddr_mbps; - - reg = mmio_read_32(PRR); - if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_D3) { - ERROR("LSI Product ID (PRR=0x%x) DDR initialize not supported.\n", - reg); - panic(); - } - - reg = mmio_read_32(RST_MODEMR); - if (reg & MODEMR_MD19) { - init_ddr_d3_1866(); - ddr_mbps = 1866; - } else { - init_ddr_d3_1600(); - ddr_mbps = 1600; - } - - NOTICE("BL2: DDR%d\n", ddr_mbps); - - return 0; -} diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c deleted file mode 100644 index fc278ef57..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c +++ /dev/null @@ -1,1712 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include "boot_init_dram.h" -#include "rcar_def.h" -#include "../ddr_regs.h" - -#include "../dram_sub_func.h" - -#define RCAR_E3_DDR_VERSION "rev.0.12" - -/* Average periodic refresh interval[ns]. Support 3900,7800 */ -#ifdef ddr_qos_init_setting -#define REFRESH_RATE 3900U -#else -#if RCAR_REF_INT == 1 -#define REFRESH_RATE 7800U -#else -#define REFRESH_RATE 3900U -#endif -#endif - -/* - * Initialize ddr - */ -uint32_t init_ddr(void) -{ - uint32_t i, r2, r5, r6, r7, r12; - uint32_t ddr_md; - uint32_t regval, j; - uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4; - uint32_t bdlcount_0c_div8, bdlcount_0c_div16; - uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; - uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; - uint32_t pdr_ctl; - uint32_t byp_ctl; - - if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) { - pdqsr_ctl = 1; - lcdl_ctl = 1; - pdr_ctl = 1; - byp_ctl = 1; - } else { - pdqsr_ctl = 0; - lcdl_ctl = 0; - pdr_ctl = 0; - byp_ctl = 0; - } - - /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ - ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0); - - /* 1584Mbps setting */ - if (ddr_md == 0) { - mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); - mmio_write_32(CPG_CPGWPCR, 0xA5A50000); - - mmio_write_32(CPG_SRCR4, 0x20000000); - - mmio_write_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ - while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) - ; - - mmio_write_32(CPG_SRSTCLR4, 0x20000000); - - mmio_write_32(CPG_CPGWPCR, 0xA5A50001); - } - - mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); - mmio_write_32(DBSC_DBKIND, 0x00000007); - -#if RCAR_DRAM_DDR3L_MEMCONF == 0 - mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); /* 1GB */ -#else - mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); /* 2GB(default) */ -#endif - -#if RCAR_DRAM_DDR3L_MEMDUAL == 1 - r2 = mmio_read_32(0xE6790614); - mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */ -#endif - - mmio_write_32(DBSC_DBPHYCONF0, 0x1); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBTR0, 0xB); - mmio_write_32(DBSC_DBTR1, 0x8); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBTR0, 0xD); - mmio_write_32(DBSC_DBTR1, 0x9); - } - - mmio_write_32(DBSC_DBTR2, 0x00000000); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBTR3, 0x0000000B); - mmio_write_32(DBSC_DBTR4, 0x000B000B); - mmio_write_32(DBSC_DBTR5, 0x00000027); - mmio_write_32(DBSC_DBTR6, 0x0000001C); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBTR3, 0x0000000D); - mmio_write_32(DBSC_DBTR4, 0x000D000D); - mmio_write_32(DBSC_DBTR5, 0x0000002D); - mmio_write_32(DBSC_DBTR6, 0x00000020); - } - - mmio_write_32(DBSC_DBTR7, 0x00060006); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBTR8, 0x00000020); - mmio_write_32(DBSC_DBTR9, 0x00000006); - mmio_write_32(DBSC_DBTR10, 0x0000000C); - mmio_write_32(DBSC_DBTR11, 0x0000000A); - mmio_write_32(DBSC_DBTR12, 0x00120012); - mmio_write_32(DBSC_DBTR13, 0x000000CE); - mmio_write_32(DBSC_DBTR14, 0x00140005); - mmio_write_32(DBSC_DBTR15, 0x00050004); - mmio_write_32(DBSC_DBTR16, 0x071F0305); - mmio_write_32(DBSC_DBTR17, 0x040C0000); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBTR8, 0x00000021); - mmio_write_32(DBSC_DBTR9, 0x00000007); - mmio_write_32(DBSC_DBTR10, 0x0000000E); - mmio_write_32(DBSC_DBTR11, 0x0000000C); - mmio_write_32(DBSC_DBTR12, 0x00140014); - mmio_write_32(DBSC_DBTR13, 0x000000F2); - mmio_write_32(DBSC_DBTR14, 0x00170006); - mmio_write_32(DBSC_DBTR15, 0x00060005); - mmio_write_32(DBSC_DBTR16, 0x09210507); - mmio_write_32(DBSC_DBTR17, 0x040E0000); - } - - mmio_write_32(DBSC_DBTR18, 0x00000200); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBTR19, 0x01000040); - mmio_write_32(DBSC_DBTR20, 0x020000D6); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBTR19, 0x0129004B); - mmio_write_32(DBSC_DBTR20, 0x020000FB); - } - - mmio_write_32(DBSC_DBTR21, 0x00040004); - mmio_write_32(DBSC_DBBL, 0x00000000); - mmio_write_32(DBSC_DBODT0, 0x00000001); - mmio_write_32(DBSC_DBADJ0, 0x00000001); - mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); - mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); - mmio_write_32(DBSC_DBSCHRW1, 0x00000046); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_SCFCTST0, 0x0D050B03); - mmio_write_32(DBSC_SCFCTST1, 0x0306030C); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_SCFCTST0, 0x0C050B03); - mmio_write_32(DBSC_SCFCTST1, 0x0305030C); - } - - /* - * Initial_Step0( INITBYP ) - */ - mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); - mmio_write_32(DBSC_DBCMD, 0x01840001); - mmio_write_32(DBSC_DBCMD, 0x08840000); - NOTICE("BL2: [COLD_BOOT]\n"); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - /* - * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training ) - */ - mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - /* - * Initial_Step2( DRAMRST/DRAMINT training ) - */ - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); - if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720); - else - mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) - - 400 + 0x08B00000); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) - - 400 + 0x0A300000); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - if (REFRESH_RATE > 3900) /* [7]SRT=0 */ - mmio_write_32(DBSC_DBPDRGD_0, 0x18); - else /* [7]SRT=1 */ - mmio_write_32(DBSC_DBPDRGD_0, 0x98); - } else { /* 1856Mbps */ - if (REFRESH_RATE > 3900) /* [7]SRT=0 */ - mmio_write_32(DBSC_DBPDRGD_0, 0x20); - else /* [7]SRT=1 */ - mmio_write_32(DBSC_DBPDRGD_0, 0xA0); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); - mmio_write_32(DBSC_DBCMD, 0x08840001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - /* - * Initial_Step3( WL/QSG training ) - */ - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; - - if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | - ((r6 + ((r5) << 1)) & - 0xFF)); - } - } - - /* - * Initial_Step4( WLADJ training ) - */ - mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); - - if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - } - - /* PDR always off */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - /* - * Initial_Step5(Read Data Bit Deskew) - */ - mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00011001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - } - - /* PDR dynamic */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - } - - /* - * Initial_Step6(Write Data Bit Deskew) - */ - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00012001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - /* - * Initial_Step7(Read Data Eye Training) - */ - if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - } - - /* PDR always off */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00014001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - } - - /* PDR dynamic */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - } - - /* - * Initial_Step8(Write Data Eye Training) - */ - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00018001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - /* - * Initial_Step3_2( DQS Gate Training ) - */ - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); - r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); - mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; - r12 = (r5 >> 0x2); - if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + - (r5 >> 1) + r12) & 0xFF)); - } - } - - /* - * Initial_Step5-2_7-2( Rd bit Rd eye ) - */ - if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - } - - /* PDR always off */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - if (lcdl_ctl == 1) { - for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); - bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> - 8; - bdlcount_0c_div2 = bdlcount_0c >> 1; - bdlcount_0c_div4 = bdlcount_0c >> 2; - bdlcount_0c_div8 = bdlcount_0c >> 3; - bdlcount_0c_div16 = bdlcount_0c >> 4; - - if (ddr_md == 0) { /* 1584Mbps */ - lcdl_judge1 = bdlcount_0c_div2 + - bdlcount_0c_div4 + - bdlcount_0c_div8; - lcdl_judge2 = bdlcount_0c + - bdlcount_0c_div4 + - bdlcount_0c_div16; - } else { /* 1856Mbps */ - lcdl_judge1 = bdlcount_0c_div2 + - bdlcount_0c_div4; - lcdl_judge2 = bdlcount_0c + - bdlcount_0c_div4; - } - - if (dqsgd_0c <= lcdl_judge1) - continue; - - if (dqsgd_0c <= lcdl_judge2) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD_0) & - 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD_0, - (dqsgd_0c - bdlcount_0c_div8) | - regval); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD_0) & - 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD_0, regval); - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD_0) & - 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGD_0, regval | - (gatesl_0c + 1)); - mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD_0)); - rdqsd_0c = (regval & 0xFF00) >> 8; - rdqsnd_0c = (regval & 0xFF0000) >> 16; - mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, - (regval & 0xFF0000FF) | - ((rdqsd_0c + - bdlcount_0c_div4) << 8) | - ((rdqsnd_0c + - bdlcount_0c_div4) << 16)); - mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD_0)); - rbd_0c[0] = (regval) & 0x1f; - rbd_0c[1] = (regval >> 8) & 0x1f; - rbd_0c[2] = (regval >> 16) & 0x1f; - rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD_0) & - 0xE0E0E0E0; - for (j = 0; j < 4; j++) { - rbd_0c[j] = rbd_0c[j] + - bdlcount_0c_div4; - if (rbd_0c[j] > 0x1F) - rbd_0c[j] = 0x1F; - regval = regval | (rbd_0c[j] << 8 * j); - } - mmio_write_32(DBSC_DBPDRGD_0, regval); - mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD_0)); - rbd_0c[0] = (regval) & 0x1f; - rbd_0c[1] = (regval >> 8) & 0x1f; - rbd_0c[2] = (regval >> 16) & 0x1f; - rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD_0) & - 0xE0E0E0E0; - for (j = 0; j < 4; j++) { - rbd_0c[j] = rbd_0c[j] + - bdlcount_0c_div4; - if (rbd_0c[j] > 0x1F) - rbd_0c[j] = 0x1F; - regval = regval | (rbd_0c[j] << 8 * j); - } - mmio_write_32(DBSC_DBPDRGD_0, regval); - } - } - mmio_write_32(DBSC_DBPDRGA_0, 0x2); - mmio_write_32(DBSC_DBPDRGD_0, 0x7D81E37); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); - if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720); - else - mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); - - mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); - mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000); - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBRFCNF1, - (REFRESH_RATE * 99 / 125) + 0x00080000); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBRFCNF1, - (REFRESH_RATE * 116 / 125) + 0x00080000); - } - - mmio_write_32(DBSC_DBRFCNF2, 0x00010000); - mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); - mmio_write_32(DBSC_DBRFEN, 0x00000001); - mmio_write_32(DBSC_DBACEN, 0x00000001); - - if (pdqsr_ctl == 1) { - mmio_write_32(0xE67F0018, 0x00000001); - regval = mmio_read_32(0x40000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGD_0, regval); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - } - - /* PDR dynamic */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - } - - /* - * Initial_Step9( Initial End ) - */ - mmio_write_32(DBSC_DBPDLK_0, 0x00000000); - mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); - -#ifdef ddr_qos_init_setting /* only for non qos_init */ - mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); - mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); - mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); - mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); - mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); - mmio_write_32(DBSC_DBSCHRW0, 0x22421111); - mmio_write_32(DBSC_SCFCTST2, 0x012F1123); - mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); - mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); - mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); - mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); - mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); - mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); - mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); - mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS90, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0); - mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0); - mmio_write_32(DBSC_DBSCHQOS93, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); - mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); - mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); - mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); - mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); - mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); - mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); - mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); - - if (pdqsr_ctl == 0) - mmio_write_32(0xE67F0018, 0x00000001); - - mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); -#endif - - return 1; -} - -static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) -{ - /* - * recovery_Step0(DBSC Setting 1) / same "init_ddr" - */ - uint32_t r2, r5, r6, r7, r12, i; - uint32_t ddr_md; - uint32_t err; - uint32_t regval, j; - uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4; - uint32_t bdlcount_0c_div8, bdlcount_0c_div16; - uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; - uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; - uint32_t pdr_ctl; - uint32_t byp_ctl; - - if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) { - pdqsr_ctl = 1; - lcdl_ctl = 1; - pdr_ctl = 1; - byp_ctl = 1; - } else { - pdqsr_ctl = 0; - lcdl_ctl = 0; - pdr_ctl = 0; - byp_ctl = 0; - } - - /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ - ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0); - - /* 1584Mbps setting */ - if (ddr_md == 0) { - mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); - mmio_write_32(CPG_CPGWPCR, 0xA5A50000); - - mmio_write_32(CPG_SRCR4, 0x20000000); - - mmio_write_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ - while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) - ; - - mmio_write_32(CPG_SRSTCLR4, 0x20000000); - - mmio_write_32(CPG_CPGWPCR, 0xA5A50001); - } - - mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); - mmio_write_32(DBSC_DBKIND, 0x00000007); - -#if RCAR_DRAM_DDR3L_MEMCONF == 0 - mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); -#else - mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); -#endif - -#if RCAR_DRAM_DDR3L_MEMDUAL == 1 - r2 = mmio_read_32(0xE6790614); - mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */ -#endif - - mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBTR0, 0x0000000B); - mmio_write_32(DBSC_DBTR1, 0x00000008); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBTR0, 0x0000000D); - mmio_write_32(DBSC_DBTR1, 0x00000009); - } - - mmio_write_32(DBSC_DBTR2, 0x00000000); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBTR3, 0x0000000B); - mmio_write_32(DBSC_DBTR4, 0x000B000B); - mmio_write_32(DBSC_DBTR5, 0x00000027); - mmio_write_32(DBSC_DBTR6, 0x0000001C); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBTR3, 0x0000000D); - mmio_write_32(DBSC_DBTR4, 0x000D000D); - mmio_write_32(DBSC_DBTR5, 0x0000002D); - mmio_write_32(DBSC_DBTR6, 0x00000020); - } - - mmio_write_32(DBSC_DBTR7, 0x00060006); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBTR8, 0x00000020); - mmio_write_32(DBSC_DBTR9, 0x00000006); - mmio_write_32(DBSC_DBTR10, 0x0000000C); - mmio_write_32(DBSC_DBTR11, 0x0000000A); - mmio_write_32(DBSC_DBTR12, 0x00120012); - mmio_write_32(DBSC_DBTR13, 0x000000CE); - mmio_write_32(DBSC_DBTR14, 0x00140005); - mmio_write_32(DBSC_DBTR15, 0x00050004); - mmio_write_32(DBSC_DBTR16, 0x071F0305); - mmio_write_32(DBSC_DBTR17, 0x040C0000); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBTR8, 0x00000021); - mmio_write_32(DBSC_DBTR9, 0x00000007); - mmio_write_32(DBSC_DBTR10, 0x0000000E); - mmio_write_32(DBSC_DBTR11, 0x0000000C); - mmio_write_32(DBSC_DBTR12, 0x00140014); - mmio_write_32(DBSC_DBTR13, 0x000000F2); - mmio_write_32(DBSC_DBTR14, 0x00170006); - mmio_write_32(DBSC_DBTR15, 0x00060005); - mmio_write_32(DBSC_DBTR16, 0x09210507); - mmio_write_32(DBSC_DBTR17, 0x040E0000); - } - - mmio_write_32(DBSC_DBTR18, 0x00000200); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBTR19, 0x01000040); - mmio_write_32(DBSC_DBTR20, 0x020000D6); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBTR19, 0x0129004B); - mmio_write_32(DBSC_DBTR20, 0x020000FB); - } - - mmio_write_32(DBSC_DBTR21, 0x00040004); - mmio_write_32(DBSC_DBBL, 0x00000000); - mmio_write_32(DBSC_DBODT0, 0x00000001); - mmio_write_32(DBSC_DBADJ0, 0x00000001); - mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); - mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); - mmio_write_32(DBSC_DBSCHRW1, 0x00000046); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_SCFCTST0, 0x0D050B03); - mmio_write_32(DBSC_SCFCTST1, 0x0306030C); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_SCFCTST0, 0x0C050B03); - mmio_write_32(DBSC_SCFCTST1, 0x0305030C); - } - - /* - * recovery_Step1(PHY setting 1) - */ - mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); - mmio_write_32(DBSC_DBCMD, 0x01840001); - mmio_write_32(DBSC_DBCMD, 0x0A840000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); /* DDR_PLLCR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); /* DDR_PGCR1 */ - if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720); - else - mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); /* DDR_DXCCR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); /* DDR_ACIOCR0 */ - mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) - - 400 + 0x08B00000); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) - - 400 + 0x0A300000); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - if (REFRESH_RATE > 3900) - mmio_write_32(DBSC_DBPDRGD_0, 0x18); /* [7]SRT=0 */ - else - mmio_write_32(DBSC_DBPDRGD_0, 0x98); /* [7]SRT=1 */ - } else { /* 1856Mbps */ - if (REFRESH_RATE > 3900) - mmio_write_32(DBSC_DBPDRGD_0, 0x20); /* [7]SRT=0 */ - else - mmio_write_32(DBSC_DBPDRGD_0, 0xA0); /* [7]SRT=1 */ - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); /* DDR_DSGCR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x40010000); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000092); /* DDR_ZQ0DR */ - mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000096); /* DDR_ZQ1DR */ - mmio_write_32(DBSC_DBPDRGD_0, 0xC4285FBF); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A); /* DDR_ZQ2DR */ - mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x00050001); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - /* ddr backupmode end */ - if (ddr_backup) - NOTICE("BL2: [WARM_BOOT]\n"); - else - NOTICE("BL2: [COLD_BOOT]\n"); - - err = rcar_dram_update_boot_status(ddr_backup); - if (err) { - NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); - return INITDRAM_ERR_I; - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000092); /* DDR_ZQ0DR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000096); /* DDR_ZQ1DR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x04285FBF); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A); /* DDR_ZQ2DR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x08000000); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x00000003); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ - - /* Select setting value in bps */ - if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); - else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - - mmio_write_32(DBSC_DBPDRGA_0, 0x0000000C); - mmio_write_32(DBSC_DBPDRGD_0, 0x18000040); - - /* - * recovery_Step2(PHY setting 2) - */ - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - - mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000); - mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBRFCNF1, - (REFRESH_RATE * 99 / 125) + 0x00080000); - } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBRFCNF1, - (REFRESH_RATE * 116 / 125) + 0x00080000); - } - - mmio_write_32(DBSC_DBRFCNF2, 0x00010000); - mmio_write_32(DBSC_DBRFEN, 0x00000001); - mmio_write_32(DBSC_DBCMD, 0x0A840001); - while (mmio_read_32(DBSC_DBWAIT) & BIT(0)) - ; - - mmio_write_32(DBSC_DBCMD, 0x00000000); - - mmio_write_32(DBSC_DBCMD, 0x04840010); - while (mmio_read_32(DBSC_DBWAIT) & BIT(0)) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD_0, 0x00010701); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; - - if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, - r2 | ((r6 + (r5 << 1)) & 0xFF)); - } - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); - - if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - } - - /* PDR always off */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00011001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - } - - /* PDR dynamic */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00012001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - } - - /* PDR always off */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00014001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - } - - /* PDR dynamic */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00018001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); - r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); - mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; - r12 = r5 >> 0x2; - - if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, - r2 | - ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); - } - } - - if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - } - - /* PDR always off */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - if (lcdl_ctl == 1) { - for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000B0 + i * 0x20); - dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x000000FF; - mmio_write_32(DBSC_DBPDRGA_0, 0x000000B1 + i * 0x20); - bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) & - 0x0000FF00) >> 8; - bdlcount_0c_div2 = (bdlcount_0c >> 1); - bdlcount_0c_div4 = (bdlcount_0c >> 2); - bdlcount_0c_div8 = (bdlcount_0c >> 3); - bdlcount_0c_div16 = (bdlcount_0c >> 4); - - if (ddr_md == 0) { /* 1584Mbps */ - lcdl_judge1 = bdlcount_0c_div2 + - bdlcount_0c_div4 + - bdlcount_0c_div8; - lcdl_judge2 = bdlcount_0c + - bdlcount_0c_div4 + - bdlcount_0c_div16; - } else { /* 1856Mbps */ - lcdl_judge1 = bdlcount_0c_div2 + - bdlcount_0c_div4; - lcdl_judge2 = bdlcount_0c + - bdlcount_0c_div4; - } - - if (dqsgd_0c <= lcdl_judge1) - continue; - - if (dqsgd_0c <= lcdl_judge2) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD_0) & - 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD_0, - (dqsgd_0c - bdlcount_0c_div8) | - regval); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD_0) & - 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD_0, regval); - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD_0) & - 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGD_0, - regval | (gatesl_0c + 1)); - mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD_0); - rdqsd_0c = (regval & 0xFF00) >> 8; - rdqsnd_0c = (regval & 0xFF0000) >> 16; - mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, - (regval & 0xFF0000FF) | - ((rdqsd_0c + - bdlcount_0c_div4) << 8) | - ((rdqsnd_0c + - bdlcount_0c_div4) << 16)); - mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD_0)); - rbd_0c[0] = (regval) & 0x1f; - rbd_0c[1] = (regval >> 8) & 0x1f; - rbd_0c[2] = (regval >> 16) & 0x1f; - rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD_0) & - 0xE0E0E0E0; - for (j = 0; j < 4; j++) { - rbd_0c[j] = rbd_0c[j] + - bdlcount_0c_div4; - if (rbd_0c[j] > 0x1F) - rbd_0c[j] = 0x1F; - regval = regval | (rbd_0c[j] << 8 * j); - } - mmio_write_32(DBSC_DBPDRGD_0, regval); - mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD_0)); - rbd_0c[0] = regval & 0x1f; - rbd_0c[1] = (regval >> 8) & 0x1f; - rbd_0c[2] = (regval >> 16) & 0x1f; - rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD_0) & - 0xE0E0E0E0; - for (j = 0; j < 4; j++) { - rbd_0c[j] = rbd_0c[j] + - bdlcount_0c_div4; - if (rbd_0c[j] > 0x1F) - rbd_0c[j] = 0x1F; - regval = regval | (rbd_0c[j] << 8 * j); - } - mmio_write_32(DBSC_DBPDRGD_0, regval); - } - } - mmio_write_32(DBSC_DBPDRGA_0, 0x00000002); - mmio_write_32(DBSC_DBPDRGD_0, 0x07D81E37); - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); - if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720); - else - mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) - ; - mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); - - /* - * recovery_Step3(DBSC Setting 2) - */ - mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); - mmio_write_32(DBSC_DBACEN, 0x00000001); - - if (pdqsr_ctl == 1) { - mmio_write_32(0xE67F0018, 0x00000001); - regval = mmio_read_32(0x40000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGD_0, regval); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - } - - /* PDR dynamic */ - if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); - } - - mmio_write_32(DBSC_DBPDLK_0, 0x00000000); - mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); - -#ifdef ddr_qos_init_setting /* only for non qos_init */ - mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); - mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); - mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); - mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); - mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); - mmio_write_32(DBSC_DBSCHRW0, 0x22421111); - mmio_write_32(DBSC_SCFCTST2, 0x012F1123); - mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); - mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); - mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); - mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); - mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); - mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); - mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); - mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS90, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0); - mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0); - mmio_write_32(DBSC_DBSCHQOS93, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); - mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); - mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); - mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); - mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); - mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); - mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); - mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); - - if (pdqsr_ctl == 0) - mmio_write_32(0xE67F0018, 0x00000001); - - mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); -#endif - - return 1; - -} /* recovery_from_backup_mode */ - -/* - * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps - */ - -/* - * DDR Initialize entry for IPL - */ -int32_t rcar_dram_init(void) -{ - uint32_t dataL; - uint32_t failcount; - uint32_t md = 0; - uint32_t ddr = 0; - uint32_t ddr_backup; - - md = *((volatile uint32_t*)RST_MODEMR); - ddr = (md & 0x00080000) >> 19; - if (ddr == 0x0) - NOTICE("BL2: DDR1584(%s)\n", RCAR_E3_DDR_VERSION); - else if (ddr == 0x1) - NOTICE("BL2: DDR1856(%s)\n", RCAR_E3_DDR_VERSION); - - rcar_dram_get_boot_status(&ddr_backup); - - if (ddr_backup == DRAM_BOOT_STATUS_WARM) - dataL = recovery_from_backup_mode(ddr_backup); /* WARM boot */ - else - dataL = init_ddr(); /* COLD boot */ - - if (dataL == 1) - failcount = 0; - else - failcount = 1; - - if (failcount == 0) - return INITDRAM_OK; - else - return INITDRAM_NG; - -} diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c deleted file mode 100644 index 5410771c9..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include "boot_init_dram.h" -#include "rcar_def.h" -#include "../ddr_regs.h" - -static uint32_t init_ddr_v3m_1600(void) -{ - uint32_t i, r2, r5, r6, r7, r12; - - mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); - mmio_write_32(DBSC_DBKIND, 0x00000007); -#if RCAR_DRAM_DDR3L_MEMCONF == 0 - mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); // 1GB: Eagle -#else - mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); // 2GB: V3MSK -#endif - mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); - mmio_write_32(DBSC_DBTR0, 0x0000000B); - mmio_write_32(DBSC_DBTR1, 0x00000008); - mmio_write_32(DBSC_DBTR3, 0x0000000B); - mmio_write_32(DBSC_DBTR4, 0x000B000B); - mmio_write_32(DBSC_DBTR5, 0x00000027); - mmio_write_32(DBSC_DBTR6, 0x0000001C); - mmio_write_32(DBSC_DBTR7, 0x00060006); - mmio_write_32(DBSC_DBTR8, 0x00000020); - mmio_write_32(DBSC_DBTR9, 0x00000006); - mmio_write_32(DBSC_DBTR10, 0x0000000C); - mmio_write_32(DBSC_DBTR11, 0x0000000B); - mmio_write_32(DBSC_DBTR12, 0x00120012); - mmio_write_32(DBSC_DBTR13, 0x01180118); - mmio_write_32(DBSC_DBTR14, 0x00140005); - mmio_write_32(DBSC_DBTR15, 0x00050004); - mmio_write_32(DBSC_DBTR16, 0x071D0305); - mmio_write_32(DBSC_DBTR17, 0x040C0010); - mmio_write_32(DBSC_DBTR18, 0x00000200); - mmio_write_32(DBSC_DBTR19, 0x01000040); - mmio_write_32(DBSC_DBTR20, 0x02000120); - mmio_write_32(DBSC_DBTR21, 0x00040004); - mmio_write_32(DBSC_DBBL, 0x00000000); - mmio_write_32(DBSC_DBODT0, 0x00000001); - mmio_write_32(DBSC_DBADJ0, 0x00000001); - mmio_write_32(DBSC_DBCAM0CNF1, 0x00082010); - mmio_write_32(DBSC_DBCAM0CNF2, 0x00002000); - mmio_write_32(DBSC_DBSCHCNT0, 0x080f003f); - mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); - mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); - mmio_write_32(DBSC_DBSCHRW0, 0x00000200); - mmio_write_32(DBSC_DBSCHRW1, 0x00000040); - mmio_write_32(DBSC_DBSCHQOS40, 0x00000600); - mmio_write_32(DBSC_DBSCHQOS41, 0x00000480); - mmio_write_32(DBSC_DBSCHQOS42, 0x00000300); - mmio_write_32(DBSC_DBSCHQOS43, 0x00000180); - mmio_write_32(DBSC_DBSCHQOS90, 0x00000400); - mmio_write_32(DBSC_DBSCHQOS91, 0x00000300); - mmio_write_32(DBSC_DBSCHQOS92, 0x00000200); - mmio_write_32(DBSC_DBSCHQOS93, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS130, 0x00000300); - mmio_write_32(DBSC_DBSCHQOS131, 0x00000240); - mmio_write_32(DBSC_DBSCHQOS132, 0x00000180); - mmio_write_32(DBSC_DBSCHQOS133, 0x000000c0); - mmio_write_32(DBSC_DBSCHQOS140, 0x00000200); - mmio_write_32(DBSC_DBSCHQOS141, 0x00000180); - mmio_write_32(DBSC_DBSCHQOS142, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS143, 0x00000080); - mmio_write_32(DBSC_DBSCHQOS150, 0x00000100); - mmio_write_32(DBSC_DBSCHQOS151, 0x000000c0); - mmio_write_32(DBSC_DBSCHQOS152, 0x00000080); - mmio_write_32(DBSC_DBSCHQOS153, 0x00000040); - mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBCAM0CNF1, 0x00040C04); - mmio_write_32(DBSC_DBCAM0CNF2, 0x000001c4); - mmio_write_32(DBSC_DBSCHSZ0, 0x00000003); - mmio_write_32(DBSC_DBSCHRW1, 0x001a0080); - mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); - - mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); - mmio_write_32(DBSC_DBCMD, 0x01000001); - mmio_write_32(DBSC_DBCMD, 0x08000000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD_0, 0x08C0C170); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); - mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); - mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); - mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); - mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000004); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000018); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD_0, 0x13C03C10); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); - mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); - mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); - mmio_write_32(DBSC_DBCMD, 0x08000001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; - - if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); - - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); - - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | - (((r5 << 1) + r6) & 0xFF)); - } - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00A0); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00B8); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; - mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); - r6 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF); - - mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); - r7 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x7); - r12 = (r5 >> 2); - if (r6 - r12 > 0) { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); - - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); - - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, ((r6 - r12) & 0xFF) | r2); - } else { - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); - mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, (r7 & 0x7) | r2); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); - mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD_0, r2 | - ((r6 + r5 + - (r5 >> 1) + r12) & 0xFF)); - } - } - - mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) - ; - - mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) - ; - mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); - - mmio_write_32(DBSC_DBBUS0CNF1, 0x00000000); - mmio_write_32(DBSC_DBBUS0CNF0, 0x00010001); - mmio_write_32(DBSC_DBCALCNF, 0x0100200E); - mmio_write_32(DBSC_DBRFCNF1, 0x00081860); - mmio_write_32(DBSC_DBRFCNF2, 0x00010000); - mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); - mmio_write_32(DBSC_DBRFEN, 0x00000001); - mmio_write_32(DBSC_DBACEN, 0x00000001); - mmio_write_32(DBSC_DBPDLK_0, 0x00000000); - mmio_write_32(0xE67F0024, 0x00000001); - mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); - - return INITDRAM_OK; -} - -int32_t rcar_dram_init(void) -{ - return init_ddr_v3m_1600(); -} diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c deleted file mode 100644 index 1d6e83a2c..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ /dev/null @@ -1,4442 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include -#include - -#include "ddr_regdef.h" -#include "init_dram_tbl_h3.h" -#include "init_dram_tbl_m3.h" -#include "init_dram_tbl_h3ver2.h" -#include "init_dram_tbl_m3n.h" -#include "boot_init_dram_regdef.h" -#include "boot_init_dram.h" -#include "dram_sub_func.h" -#include "micro_delay.h" -#include "rcar_def.h" - -#define DDR_BACKUPMODE -#define FATAL_MSG(x) NOTICE(x) - -/* variables */ -#ifdef RCAR_DDR_FIXED_LSI_TYPE -#ifndef RCAR_AUTO -#define RCAR_AUTO 99 -#define RCAR_H3 0 -#define RCAR_M3 1 -#define RCAR_M3N 2 -#define RCAR_E3 3 /* NON */ -#define RCAR_H3N 4 - -#define RCAR_CUT_10 0 -#define RCAR_CUT_11 1 -#define RCAR_CUT_20 10 -#define RCAR_CUT_30 20 -#endif -#ifndef RCAR_LSI -#define RCAR_LSI RCAR_AUTO -#endif - -#if (RCAR_LSI == RCAR_AUTO) -static uint32_t prr_product; -static uint32_t prr_cut; -#else -#if (RCAR_LSI == RCAR_H3) -static const uint32_t prr_product = PRR_PRODUCT_H3; -#elif(RCAR_LSI == RCAR_M3) -static const uint32_t prr_product = PRR_PRODUCT_M3; -#elif(RCAR_LSI == RCAR_M3N) -static const uint32_t prr_product = PRR_PRODUCT_M3N; -#elif(RCAR_LSI == RCAR_H3N) -static const uint32_t prr_product = PRR_PRODUCT_H3; -#endif /* RCAR_LSI */ - -#ifndef RCAR_LSI_CUT -static uint32_t prr_cut; -#else /* RCAR_LSI_CUT */ -#if (RCAR_LSI_CUT == RCAR_CUT_10) -static const uint32_t prr_cut = PRR_PRODUCT_10; -#elif(RCAR_LSI_CUT == RCAR_CUT_11) -static const uint32_t prr_cut = PRR_PRODUCT_11; -#elif(RCAR_LSI_CUT == RCAR_CUT_20) -static const uint32_t prr_cut = PRR_PRODUCT_20; -#elif(RCAR_LSI_CUT == RCAR_CUT_30) -static const uint32_t prr_cut = PRR_PRODUCT_30; -#endif /* RCAR_LSI_CUT */ -#endif /* RCAR_LSI_CUT */ -#endif /* RCAR_AUTO_NON */ -#else /* RCAR_DDR_FIXED_LSI_TYPE */ -static uint32_t prr_product; -static uint32_t prr_cut; -#endif /* RCAR_DDR_FIXED_LSI_TYPE */ - -static const uint32_t *p_ddr_regdef_tbl; -static uint32_t brd_clk; -static uint32_t brd_clkdiv; -static uint32_t brd_clkdiva; -static uint32_t ddr_mbps; -static uint32_t ddr_mbpsdiv; -static uint32_t ddr_tccd; -static uint32_t ddr_phycaslice; -static const struct _boardcnf *board_cnf; -static uint32_t ddr_phyvalid; -static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; -static uint32_t ch_have_this_cs[CS_CNT] __aligned(64); -static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9]; -static uint32_t max_density; -static uint32_t ddr0800_mul; -static uint32_t ddr_mul; -static uint32_t DDR_PHY_SLICE_REGSET_OFS; -static uint32_t DDR_PHY_ADR_V_REGSET_OFS; -static uint32_t DDR_PHY_ADR_I_REGSET_OFS; -static uint32_t DDR_PHY_ADR_G_REGSET_OFS; -static uint32_t DDR_PI_REGSET_OFS; -static uint32_t DDR_PHY_SLICE_REGSET_SIZE; -static uint32_t DDR_PHY_ADR_V_REGSET_SIZE; -static uint32_t DDR_PHY_ADR_I_REGSET_SIZE; -static uint32_t DDR_PHY_ADR_G_REGSET_SIZE; -static uint32_t DDR_PI_REGSET_SIZE; -static uint32_t DDR_PHY_SLICE_REGSET_NUM; -static uint32_t DDR_PHY_ADR_V_REGSET_NUM; -static uint32_t DDR_PHY_ADR_I_REGSET_NUM; -static uint32_t DDR_PHY_ADR_G_REGSET_NUM; -static uint32_t DDR_PI_REGSET_NUM; -static uint32_t DDR_PHY_ADR_I_NUM; -#define DDR_PHY_REGSET_MAX 128 -#define DDR_PI_REGSET_MAX 320 -static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; -static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; -static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX]; -static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; -static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; -static uint32_t pll3_mode; -static uint32_t loop_max; -#ifdef DDR_BACKUPMODE -uint32_t ddr_backup; -/* #define DDR_BACKUPMODE_HALF //for Half channel(ch0,1 only) */ -#endif - -#ifdef ddr_qos_init_setting /* only for non qos_init */ -#define OPERATING_FREQ (400U) /* Mhz */ -#define BASE_SUB_SLOT_NUM (0x6U) -#define SUB_SLOT_CYCLE (0x7EU) /* 126 */ -#define QOSWT_WTSET0_CYCLE \ - ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \ - OPERATING_FREQ) /* unit:ns */ - -uint32_t get_refperiod(void) -{ - return QOSWT_WTSET0_CYCLE; -} -#else /* ddr_qos_init_setting // only for non qos_init */ -extern uint32_t get_refperiod(void); -#endif /* ddr_qos_init_setting // only for non qos_init */ - -#define _reg_PHY_RX_CAL_X_NUM 11 -static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { - _reg_PHY_RX_CAL_DQ0, - _reg_PHY_RX_CAL_DQ1, - _reg_PHY_RX_CAL_DQ2, - _reg_PHY_RX_CAL_DQ3, - _reg_PHY_RX_CAL_DQ4, - _reg_PHY_RX_CAL_DQ5, - _reg_PHY_RX_CAL_DQ6, - _reg_PHY_RX_CAL_DQ7, - _reg_PHY_RX_CAL_DM, - _reg_PHY_RX_CAL_DQS, - _reg_PHY_RX_CAL_FDBK -}; - -#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 -static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY - [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { - _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ3_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ4_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ5_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ6_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ7_SLAVE_DELAY, - _reg_PHY_CLK_WRDM_SLAVE_DELAY, - _reg_PHY_CLK_WRDQS_SLAVE_DELAY -}; - -#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 -static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY - [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { - _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY -}; - -#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 -static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY - [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { - _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY -}; - -#define _reg_PHY_PAD_TERM_X_NUM 8 -static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { - _reg_PHY_PAD_FDBK_TERM, - _reg_PHY_PAD_DATA_TERM, - _reg_PHY_PAD_DQS_TERM, - _reg_PHY_PAD_ADDR_TERM, - _reg_PHY_PAD_CLK_TERM, - _reg_PHY_PAD_CKE_TERM, - _reg_PHY_PAD_RST_TERM, - _reg_PHY_PAD_CS_TERM -}; - -#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 -static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X - [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { - _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, - _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, - _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, - _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY, - _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY, - _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY, - - _reg_PHY_GRP_SLAVE_DELAY_0, - _reg_PHY_GRP_SLAVE_DELAY_1, - _reg_PHY_GRP_SLAVE_DELAY_2, - _reg_PHY_GRP_SLAVE_DELAY_3 -}; - -/* Prototypes */ -static inline uint32_t vch_nxt(uint32_t pos); -static void cpg_write_32(uint32_t a, uint32_t v); -static void pll3_control(uint32_t high); -static inline void dsb_sev(void); -static void wait_dbcmd(void); -static void send_dbcmd(uint32_t cmd); -static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd); -static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); -static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); -static inline uint32_t ddr_regdef(uint32_t _regdef); -static inline uint32_t ddr_regdef_adr(uint32_t _regdef); -static inline uint32_t ddr_regdef_lsb(uint32_t _regdef); -static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, - uint32_t val); -static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef); -static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); -static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); -static void ddr_setval_ach(uint32_t regdef, uint32_t val); -static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); -static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); -static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p); -static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p); -static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size); -static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); -static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); -static uint32_t ddrphy_regif_chk(void); -static inline void ddrphy_regif_idle(void); -static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, - uint16_t cyc); -static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, - uint16_t *_js2); -static int16_t _f_scale_adj(int16_t ps); -static void ddrtbl_load(void); -static void ddr_config_sub(void); -static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz); -static void ddr_config_sub_h3v1x(void); -static void ddr_config(void); -static void dbsc_regset(void); -static void dbsc_regset_post(void); -static uint32_t dfi_init_start(void); -static void change_lpddr4_en(uint32_t mode); -static uint32_t set_term_code(void); -static void ddr_register_set(void); -static inline uint32_t wait_freqchgreq(uint32_t assert); -static inline void set_freqchgack(uint32_t assert); -static inline void set_dfifrequency(uint32_t freq); -static uint32_t pll3_freq(uint32_t on); -static void update_dly(void); -static uint32_t pi_training_go(void); -static uint32_t init_ddr(void); -static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick); -static uint32_t wdqdm_man1(void); -static uint32_t wdqdm_man(void); -static uint32_t rdqdm_man1(void); -static uint32_t rdqdm_man(void); - -static int32_t _find_change(uint64_t val, uint32_t dir); -static uint32_t _rx_offset_cal_updn(uint32_t code); -static uint32_t rx_offset_cal(void); -static uint32_t rx_offset_cal_hw(void); -static void adjust_rddqs_latency(void); -static void adjust_wpath_latency(void); - -struct ddrt_data { - int32_t init_temp; /* Initial Temperature (do) */ - uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ - uint32_t tcomp_cal[4]; /* Temp. compensated io-code (4 is for H3) */ -}; - -static struct ddrt_data tcal; - -static void pvtcode_update(void); -static void pvtcode_update2(void); -static void ddr_padcal_tcompensate_getinit(uint32_t override); - -/* load board configuration */ -#include "boot_init_dram_config.c" - -#ifndef DDR_FAST_INIT -static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; -static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; -static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; -static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; -static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2]; -static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn); -static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn); - -static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; -static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; -static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; -static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; -static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; -static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn); -static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn); -#endif/* DDR_FAST_INIT */ - -/* macro for channel selection loop */ -static inline uint32_t vch_nxt(uint32_t pos) -{ - uint32_t posn; - - for (posn = pos; posn < DRAM_CH_CNT; posn++) { - if (ddr_phyvalid & (1U << posn)) - break; - } - return posn; -} - -#define foreach_vch(ch) \ -for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1)) - -#define foreach_ech(ch) \ -for (ch = 0; ch < DRAM_CH_CNT; ch++) - -/* Printing functions */ -#define MSG_LF(...) - -/* clock settings, reset control */ -static void cpg_write_32(uint32_t a, uint32_t v) -{ - mmio_write_32(CPG_CPGWPR, ~v); - mmio_write_32(a, v); -} - -static void pll3_control(uint32_t high) -{ - uint32_t data_l, data_div, data_mul, tmp_div; - - if (high) { - tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / - (brd_clk * ddr_mul) / 2; - data_mul = ((ddr_mul * tmp_div) - 1) << 24; - pll3_mode = 1; - loop_max = 2; - } else { - tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / - (brd_clk * ddr0800_mul) / 2; - data_mul = ((ddr0800_mul * tmp_div) - 1) << 24; - pll3_mode = 0; - loop_max = 8; - } - - switch (tmp_div) { - case 1: - data_div = 0; - break; - case 2: - case 3: - case 4: - data_div = tmp_div; - break; - default: - data_div = 6; - data_mul = (data_mul * tmp_div) / 3; - break; - } - data_mul = data_mul | (brd_clkdiva << 7); - - /* PLL3 disable */ - data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; - cpg_write_32(CPG_PLLECR, data_l); - dsb_sev(); - - if ((prr_product == PRR_PRODUCT_M3) || - ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) { - /* PLL3 DIV resetting(Lowest value:3) */ - data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, data_l); - dsb_sev(); - - /* zb3 clk stop */ - data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); - cpg_write_32(CPG_ZB3CKCR, data_l); - dsb_sev(); - - /* PLL3 enable */ - data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); - cpg_write_32(CPG_PLLECR, data_l); - dsb_sev(); - - do { - data_l = mmio_read_32(CPG_PLLECR); - } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); - dsb_sev(); - - /* PLL3 DIV resetting (Highest value:0) */ - data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, data_l); - dsb_sev(); - - /* DIV SET KICK */ - data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, data_l); - dsb_sev(); - - /* PLL3 multiplie set */ - cpg_write_32(CPG_PLL3CR, data_mul); - dsb_sev(); - - do { - data_l = mmio_read_32(CPG_PLLECR); - } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); - dsb_sev(); - - /* PLL3 DIV resetting(Target value) */ - data_l = (data_div << 16) | data_div | - (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); - cpg_write_32(CPG_FRQCRD, data_l); - dsb_sev(); - - /* DIV SET KICK */ - data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, data_l); - dsb_sev(); - - do { - data_l = mmio_read_32(CPG_PLLECR); - } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); - dsb_sev(); - - /* zb3 clk start */ - data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); - cpg_write_32(CPG_ZB3CKCR, data_l); - dsb_sev(); - - } else { /* H3Ver.3.0/M3N/V3H */ - - /* PLL3 multiplie set */ - cpg_write_32(CPG_PLL3CR, data_mul); - dsb_sev(); - - /* PLL3 DIV set(Target value) */ - data_l = (data_div << 16) | data_div | - (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); - cpg_write_32(CPG_FRQCRD, data_l); - - /* DIV SET KICK */ - data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, data_l); - dsb_sev(); - - /* PLL3 enable */ - data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); - cpg_write_32(CPG_PLLECR, data_l); - dsb_sev(); - - do { - data_l = mmio_read_32(CPG_PLLECR); - } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); - dsb_sev(); - } -} - -/* barrier */ -static inline void dsb_sev(void) -{ - __asm__ __volatile__("dsb sy"); -} - -/* DDR memory register access */ -static void wait_dbcmd(void) -{ - uint32_t data_l; - /* dummy read */ - data_l = mmio_read_32(DBSC_DBCMD); - dsb_sev(); - while (1) { - /* wait DBCMD 1=busy, 0=ready */ - data_l = mmio_read_32(DBSC_DBWAIT); - dsb_sev(); - if ((data_l & 0x00000001) == 0x00) - break; - } -} - -static void send_dbcmd(uint32_t cmd) -{ - /* dummy read */ - wait_dbcmd(); - mmio_write_32(DBSC_DBCMD, cmd); - dsb_sev(); -} - -/* DDRPHY register access (raw) */ -static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) -{ - uint32_t val; - uint32_t loop; - - val = 0; - if ((prr_product != PRR_PRODUCT_M3N) && - (prr_product != PRR_PRODUCT_V3H)) { - mmio_write_32(DBSC_DBPDRGA(phyno), regadd); - dsb_sev(); - - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { - dsb_sev(); - } - dsb_sev(); - - for (loop = 0; loop < loop_max; loop++) { - val = mmio_read_32(DBSC_DBPDRGD(phyno)); - dsb_sev(); - } - (void)val; - } else { - mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000); - dsb_sev(); - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != - (regadd | 0x0000C000)) { - dsb_sev(); - }; - val = mmio_read_32(DBSC_DBPDRGA(phyno)); - mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { - dsb_sev(); - }; - dsb_sev(); - - mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { - dsb_sev(); - }; - - dsb_sev(); - val = mmio_read_32(DBSC_DBPDRGD(phyno)); - dsb_sev(); - (void)val; - } - return val; -} - -static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) -{ - uint32_t val; - uint32_t loop; - - if ((prr_product != PRR_PRODUCT_M3N) && - (prr_product != PRR_PRODUCT_V3H)) { - mmio_write_32(DBSC_DBPDRGA(phyno), regadd); - dsb_sev(); - for (loop = 0; loop < loop_max; loop++) { - val = mmio_read_32(DBSC_DBPDRGA(phyno)); - dsb_sev(); - } - mmio_write_32(DBSC_DBPDRGD(phyno), regdata); - dsb_sev(); - - for (loop = 0; loop < loop_max; loop++) { - val = mmio_read_32(DBSC_DBPDRGD(phyno)); - dsb_sev(); - } - } else { - mmio_write_32(DBSC_DBPDRGA(phyno), regadd); - dsb_sev(); - - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { - dsb_sev(); - }; - dsb_sev(); - - mmio_write_32(DBSC_DBPDRGD(phyno), regdata); - dsb_sev(); - - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != - (regadd | 0x00008000)) { - dsb_sev(); - }; - mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); - - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) { - dsb_sev(); - }; - dsb_sev(); - - mmio_write_32(DBSC_DBPDRGA(phyno), regadd); - } - (void)val; -} - -static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) -{ - uint32_t ch; - uint32_t val; - uint32_t loop; - - if ((prr_product != PRR_PRODUCT_M3N) && - (prr_product != PRR_PRODUCT_V3H)) { - foreach_vch(ch) { - mmio_write_32(DBSC_DBPDRGA(ch), regadd); - dsb_sev(); - } - - foreach_vch(ch) { - mmio_write_32(DBSC_DBPDRGD(ch), regdata); - dsb_sev(); - } - - for (loop = 0; loop < loop_max; loop++) { - val = mmio_read_32(DBSC_DBPDRGD(0)); - dsb_sev(); - } - (void)val; - } else { - foreach_vch(ch) { - reg_ddrphy_write(ch, regadd, regdata); - dsb_sev(); - } - } -} - -static inline void ddrphy_regif_idle(void) -{ - uint32_t val; - - val = reg_ddrphy_read(0, ddr_regdef_adr(_reg_PI_INT_STATUS)); - dsb_sev(); - (void)val; -} - -/* DDRPHY register access (field modify) */ -static inline uint32_t ddr_regdef(uint32_t _regdef) -{ - return p_ddr_regdef_tbl[_regdef]; -} - -static inline uint32_t ddr_regdef_adr(uint32_t _regdef) -{ - return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]); -} - -static inline uint32_t ddr_regdef_lsb(uint32_t _regdef) -{ - return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]); -} - -static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, - uint32_t val) -{ - uint32_t adr; - uint32_t lsb; - uint32_t len; - uint32_t msk; - uint32_t tmp; - uint32_t regdef; - - regdef = ddr_regdef(_regdef); - adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; - len = DDR_REGDEF_LEN(regdef); - lsb = DDR_REGDEF_LSB(regdef); - if (len == 0x20) - msk = 0xffffffff; - else - msk = ((1U << len) - 1) << lsb; - - tmp = reg_ddrphy_read(ch, adr); - tmp = (tmp & (~msk)) | ((val << lsb) & msk); - reg_ddrphy_write(ch, adr, tmp); -} - -static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef) -{ - uint32_t adr; - uint32_t lsb; - uint32_t len; - uint32_t msk; - uint32_t tmp; - uint32_t regdef; - - regdef = ddr_regdef(_regdef); - adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; - len = DDR_REGDEF_LEN(regdef); - lsb = DDR_REGDEF_LSB(regdef); - if (len == 0x20) - msk = 0xffffffff; - else - msk = ((1U << len) - 1); - - tmp = reg_ddrphy_read(ch, adr); - tmp = (tmp >> lsb) & msk; - - return tmp; -} - -static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) -{ - ddr_setval_s(ch, 0, regdef, val); -} - -static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) -{ - uint32_t ch; - - foreach_vch(ch) - ddr_setval_s(ch, slice, regdef, val); -} - -static void ddr_setval_ach(uint32_t regdef, uint32_t val) -{ - ddr_setval_ach_s(0, regdef, val); -} - -static void ddr_setval_ach_as(uint32_t regdef, uint32_t val) -{ - uint32_t slice; - - for (slice = 0; slice < SLICE_CNT; slice++) - ddr_setval_ach_s(slice, regdef, val); -} - -static uint32_t ddr_getval(uint32_t ch, uint32_t regdef) -{ - return ddr_getval_s(ch, 0, regdef); -} - -static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p) -{ - uint32_t ch; - - foreach_vch(ch) - p[ch] = ddr_getval_s(ch, 0, regdef); - return p[0]; -} - -static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p) -{ - uint32_t ch, slice; - uint32_t *pp; - - pp = p; - foreach_vch(ch) - for (slice = 0; slice < SLICE_CNT; slice++) - *pp++ = ddr_getval_s(ch, slice, regdef); - return p[0]; -} - -/* handling functions for setteing ddrphy value table */ -static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size) -{ - uint32_t i; - - for (i = 0; i < size; i++) { - to[i] = from[i]; - } -} - -static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val) -{ - uint32_t adr; - uint32_t lsb; - uint32_t len; - uint32_t msk; - uint32_t tmp; - uint32_t adrmsk; - uint32_t regdef; - - regdef = ddr_regdef(_regdef); - adr = DDR_REGDEF_ADR(regdef); - len = DDR_REGDEF_LEN(regdef); - lsb = DDR_REGDEF_LSB(regdef); - if (len == 0x20) - msk = 0xffffffff; - else - msk = ((1U << len) - 1) << lsb; - - if (adr < 0x400) { - adrmsk = 0xff; - } else { - adrmsk = 0x7f; - } - - tmp = tbl[adr & adrmsk]; - tmp = (tmp & (~msk)) | ((val << lsb) & msk); - tbl[adr & adrmsk] = tmp; -} - -static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef) -{ - uint32_t adr; - uint32_t lsb; - uint32_t len; - uint32_t msk; - uint32_t tmp; - uint32_t adrmsk; - uint32_t regdef; - - regdef = ddr_regdef(_regdef); - adr = DDR_REGDEF_ADR(regdef); - len = DDR_REGDEF_LEN(regdef); - lsb = DDR_REGDEF_LSB(regdef); - if (len == 0x20) - msk = 0xffffffff; - else - msk = ((1U << len) - 1); - - if (adr < 0x400) { - adrmsk = 0xff; - } else { - adrmsk = 0x7f; - } - - tmp = tbl[adr & adrmsk]; - tmp = (tmp >> lsb) & msk; - - return tmp; -} - -/* DDRPHY register access handling */ -static uint32_t ddrphy_regif_chk(void) -{ - uint32_t tmp_ach[DRAM_CH_CNT]; - uint32_t ch; - uint32_t err; - uint32_t PI_VERSION_CODE; - - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || - (prr_product == PRR_PRODUCT_M3)) { - PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ - } else { - PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ - } - - ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach); - err = 0; - foreach_vch(ch) { - if (tmp_ach[ch] != PI_VERSION_CODE) - err = 1; - } - return err; -} - -/* functions and parameters for timing setting */ -struct _jedec_spec1 { - uint16_t fx3; - uint8_t rlwodbi; - uint8_t rlwdbi; - uint8_t WL; - uint8_t nwr; - uint8_t nrtp; - uint8_t MR1; - uint8_t MR2; -}; - -#define JS1_USABLEC_SPEC_LO 2 -#define JS1_USABLEC_SPEC_HI 5 -#define JS1_FREQ_TBL_NUM 8 -#define JS1_MR1(f) (0x04 | ((f) << 4)) -#define JS1_MR2(f) (0x00 | ((f) << 3) | (f)) -const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { - /* 533.333Mbps */ - { 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40 }, - /* 1066.666Mbps */ - { 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40 }, - /* 1600.000Mbps */ - { 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40 }, - /* 2133.333Mbps */ - { 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) }, - /* 2666.666Mbps */ - { 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) }, - /* 3200.000Mbps */ - { 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) }, - /* 3733.333Mbps */ - { 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) }, - /* 4266.666Mbps */ - { 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) } -}; - -struct _jedec_spec2 { - uint16_t ps; - uint16_t cyc; -}; - -#define js2_tsr 0 -#define js2_txp 1 -#define js2_trtp 2 -#define js2_trcd 3 -#define js2_trppb 4 -#define js2_trpab 5 -#define js2_tras 6 -#define js2_twr 7 -#define js2_twtr 8 -#define js2_trrd 9 -#define js2_tppd 10 -#define js2_tfaw 11 -#define js2_tdqsck 12 -#define js2_tckehcmd 13 -#define js2_tckelcmd 14 -#define js2_tckelpd 15 -#define js2_tmrr 16 -#define js2_tmrw 17 -#define js2_tmrd 18 -#define js2_tzqcalns 19 -#define js2_tzqlat 20 -#define js2_tiedly 21 -#define JS2_TBLCNT 22 - -#define js2_trcpb (JS2_TBLCNT) -#define js2_trcab (JS2_TBLCNT + 1) -#define js2_trfcab (JS2_TBLCNT + 2) -#define JS2_CNT (JS2_TBLCNT + 3) - -#ifndef JS2_DERATE -#define JS2_DERATE 0 -#endif -const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { - { -/*tSR */ {15000, 3}, -/*tXP */ {7500, 3}, -/*tRTP */ {7500, 8}, -/*tRCD */ {18000, 4}, -/*tRPpb */ {18000, 3}, -/*tRPab */ {21000, 3}, -/*tRAS */ {42000, 3}, -/*tWR */ {18000, 4}, -/*tWTR */ {10000, 8}, -/*tRRD */ {10000, 4}, -/*tPPD */ {0, 0}, -/*tFAW */ {40000, 0}, -/*tDQSCK*/ {3500, 0}, -/*tCKEHCMD*/ {7500, 3}, -/*tCKELCMD*/ {7500, 3}, -/*tCKELPD*/ {7500, 3}, -/*tMRR*/ {0, 8}, -/*tMRW*/ {10000, 10}, -/*tMRD*/ {14000, 10}, -/*tZQCALns*/ {1000 * 10, 0}, -/*tZQLAT*/ {30000, 10}, -/*tIEdly*/ {12500, 0} - }, { -/*tSR */ {15000, 3}, -/*tXP */ {7500, 3}, -/*tRTP */ {7500, 8}, -/*tRCD */ {19875, 4}, -/*tRPpb */ {19875, 3}, -/*tRPab */ {22875, 3}, -/*tRAS */ {43875, 3}, -/*tWR */ {18000, 4}, -/*tWTR */ {10000, 8}, -/*tRRD */ {11875, 4}, -/*tPPD */ {0, 0}, -/*tFAW */ {40000, 0}, -/*tDQSCK*/ {3600, 0}, -/*tCKEHCMD*/ {7500, 3}, -/*tCKELCMD*/ {7500, 3}, -/*tCKELPD*/ {7500, 3}, -/*tMRR*/ {0, 8}, -/*tMRW*/ {10000, 10}, -/*tMRD*/ {14000, 10}, -/*tZQCALns*/ {1000 * 10, 0}, -/*tZQLAT*/ {30000, 10}, -/*tIEdly*/ {12500, 0} - } -}; - -const uint16_t jedec_spec2_trfc_ab[7] = { -/* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */ - 130, 180, 180, 280, 280, 560, 560 -}; - -static uint32_t js1_ind; -static uint16_t js2[JS2_CNT]; -static uint8_t RL; -static uint8_t WL; - -static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps, - uint16_t cyc) -{ - uint32_t tmp; - uint32_t div; - - tmp = (((uint32_t)(ps) + 9) / 10) * _ddr_mbps; - div = tmp / (200000 * _ddr_mbpsdiv); - if (tmp != (div * 200000 * _ddr_mbpsdiv)) - div = div + 1; - - if (div > cyc) - return (uint16_t)div; - return cyc; -} - -static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, - uint16_t *_js2) -{ - int i; - - for (i = 0; i < JS2_TBLCNT; i++) { - _js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv, - 1UL * jedec_spec2[JS2_DERATE][i].ps, - jedec_spec2[JS2_DERATE][i].cyc); - } - - _js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb]; - _js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab]; -} - -/* scaler for DELAY value */ -static int16_t _f_scale_adj(int16_t ps) -{ - int32_t tmp; - /* - * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000; - * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125 - * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 - */ - tmp = - (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps / - (int32_t)ddr_mbpsdiv; - tmp = (int32_t)tmp / (int32_t)15625; - - return (int16_t)tmp; -} - -static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = { - { - _reg_PI_MR1_DATA_F0_0, - _reg_PI_MR1_DATA_F0_1, - _reg_PI_MR1_DATA_F0_2, - _reg_PI_MR1_DATA_F0_3}, - { - _reg_PI_MR1_DATA_F1_0, - _reg_PI_MR1_DATA_F1_1, - _reg_PI_MR1_DATA_F1_2, - _reg_PI_MR1_DATA_F1_3} -}; - -static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = { - { - _reg_PI_MR2_DATA_F0_0, - _reg_PI_MR2_DATA_F0_1, - _reg_PI_MR2_DATA_F0_2, - _reg_PI_MR2_DATA_F0_3}, - { - _reg_PI_MR2_DATA_F1_0, - _reg_PI_MR2_DATA_F1_1, - _reg_PI_MR2_DATA_F1_2, - _reg_PI_MR2_DATA_F1_3} -}; - -static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = { - { - _reg_PI_MR3_DATA_F0_0, - _reg_PI_MR3_DATA_F0_1, - _reg_PI_MR3_DATA_F0_2, - _reg_PI_MR3_DATA_F0_3}, - { - _reg_PI_MR3_DATA_F1_0, - _reg_PI_MR3_DATA_F1_1, - _reg_PI_MR3_DATA_F1_2, - _reg_PI_MR3_DATA_F1_3} -}; - -const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = { - { - _reg_PI_MR11_DATA_F0_0, - _reg_PI_MR11_DATA_F0_1, - _reg_PI_MR11_DATA_F0_2, - _reg_PI_MR11_DATA_F0_3}, - { - _reg_PI_MR11_DATA_F1_0, - _reg_PI_MR11_DATA_F1_1, - _reg_PI_MR11_DATA_F1_2, - _reg_PI_MR11_DATA_F1_3} -}; - -const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = { - { - _reg_PI_MR12_DATA_F0_0, - _reg_PI_MR12_DATA_F0_1, - _reg_PI_MR12_DATA_F0_2, - _reg_PI_MR12_DATA_F0_3}, - { - _reg_PI_MR12_DATA_F1_0, - _reg_PI_MR12_DATA_F1_1, - _reg_PI_MR12_DATA_F1_2, - _reg_PI_MR12_DATA_F1_3} -}; - -const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = { - { - _reg_PI_MR14_DATA_F0_0, - _reg_PI_MR14_DATA_F0_1, - _reg_PI_MR14_DATA_F0_2, - _reg_PI_MR14_DATA_F0_3}, - { - _reg_PI_MR14_DATA_F1_0, - _reg_PI_MR14_DATA_F1_1, - _reg_PI_MR14_DATA_F1_2, - _reg_PI_MR14_DATA_F1_3} -}; - -/* - * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA ) - */ -static void regif_pll_wa(void) -{ - uint32_t ch; - - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - // PLL setting for PHY : H3 Ver.1.x - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), - (0x0064U << - ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), - ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_PLL_CTRL)); - - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), - ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_LP4_BOOT_PLL_CTRL)); - - } else { - /* PLL setting for PHY : M3-W/M3-N/V3H/H3 Ver.2.0 or later */ - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), - (0x5064U << - ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); - - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), - (ddrtbl_getval - (_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_PLL_CTRL_TOP) << 16) | - ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_PLL_CTRL)); - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), - ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_PLL_CTRL_CA)); - - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), - (ddrtbl_getval - (_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) | - ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_LP4_BOOT_PLL_CTRL)); - reg_ddrphy_write_a(ddr_regdef_adr - (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL), - ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_LP4_BOOT_TOP_PLL_CTRL - )); - } - - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), - _cnf_DDR_PHY_ADR_G_REGSET - [ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - - DDR_PHY_ADR_G_REGSET_OFS]); - - /* protect register interface */ - ddrphy_regif_idle(); - pll3_control(0); - - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - /* non */ - } else { - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN), - (0x01U << - ddr_regdef_lsb(_reg_PHY_DLL_RST_EN))); - ddrphy_regif_idle(); - } - - /* init start */ - /* dbdficnt0: - * dfi_dram_clk_disable=1 - * dfi_frequency = 0 - * freq_ratio = 01 (2:1) - * init_start =0 - */ - foreach_vch(ch) - mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); - dsb_sev(); - - /* dbdficnt0: - * dfi_dram_clk_disable=1 - * dfi_frequency = 0 - * freq_ratio = 01 (2:1) - * init_start =1 - */ - foreach_vch(ch) - mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); - dsb_sev(); - - foreach_ech(ch) - if ((board_cnf->phyvalid) & BIT(ch)) - while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) - ; - dsb_sev(); -} - -/* load table data into DDR registers */ -static void ddrtbl_load(void) -{ - uint32_t i; - uint32_t slice; - uint32_t csab; - uint32_t adr; - uint32_t data_l; - uint32_t tmp[3]; - uint16_t dataS; - - /* TIMING REGISTERS */ - /* search jedec_spec1 index */ - for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) { - if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) - break; - } - if (i > JS1_USABLEC_SPEC_HI) - js1_ind = JS1_USABLEC_SPEC_HI; - else - js1_ind = i; - - if (board_cnf->dbi_en) - RL = js1[js1_ind].rlwdbi; - else - RL = js1[js1_ind].rlwodbi; - - WL = js1[js1_ind].WL; - - /* calculate jedec_spec2 */ - _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); - - /* PREPARE TBL */ - if (prr_product == PRR_PRODUCT_H3) { - if (prr_cut <= PRR_PRODUCT_11) { - /* H3 Ver.1.x */ - _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, - DDR_PHY_SLICE_REGSET_H3, - DDR_PHY_SLICE_REGSET_NUM_H3); - _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, - DDR_PHY_ADR_V_REGSET_H3, - DDR_PHY_ADR_V_REGSET_NUM_H3); - _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, - DDR_PHY_ADR_I_REGSET_H3, - DDR_PHY_ADR_I_REGSET_NUM_H3); - _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, - DDR_PHY_ADR_G_REGSET_H3, - DDR_PHY_ADR_G_REGSET_NUM_H3); - _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3, - DDR_PI_REGSET_NUM_H3); - - DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_H3; - DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_H3; - DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_H3; - DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_H3; - DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3; - DDR_PHY_SLICE_REGSET_SIZE = - DDR_PHY_SLICE_REGSET_SIZE_H3; - DDR_PHY_ADR_V_REGSET_SIZE = - DDR_PHY_ADR_V_REGSET_SIZE_H3; - DDR_PHY_ADR_I_REGSET_SIZE = - DDR_PHY_ADR_I_REGSET_SIZE_H3; - DDR_PHY_ADR_G_REGSET_SIZE = - DDR_PHY_ADR_G_REGSET_SIZE_H3; - DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3; - DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_H3; - DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_H3; - DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_H3; - DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_H3; - DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3; - - DDR_PHY_ADR_I_NUM = 1; - } else { - /* H3 Ver.2.0 or later */ - _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, - DDR_PHY_SLICE_REGSET_H3VER2, - DDR_PHY_SLICE_REGSET_NUM_H3VER2); - _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, - DDR_PHY_ADR_V_REGSET_H3VER2, - DDR_PHY_ADR_V_REGSET_NUM_H3VER2); - _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, - DDR_PHY_ADR_G_REGSET_H3VER2, - DDR_PHY_ADR_G_REGSET_NUM_H3VER2); - _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3VER2, - DDR_PI_REGSET_NUM_H3VER2); - - DDR_PHY_SLICE_REGSET_OFS = - DDR_PHY_SLICE_REGSET_OFS_H3VER2; - DDR_PHY_ADR_V_REGSET_OFS = - DDR_PHY_ADR_V_REGSET_OFS_H3VER2; - DDR_PHY_ADR_G_REGSET_OFS = - DDR_PHY_ADR_G_REGSET_OFS_H3VER2; - DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3VER2; - DDR_PHY_SLICE_REGSET_SIZE = - DDR_PHY_SLICE_REGSET_SIZE_H3VER2; - DDR_PHY_ADR_V_REGSET_SIZE = - DDR_PHY_ADR_V_REGSET_SIZE_H3VER2; - DDR_PHY_ADR_G_REGSET_SIZE = - DDR_PHY_ADR_G_REGSET_SIZE_H3VER2; - DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3VER2; - DDR_PHY_SLICE_REGSET_NUM = - DDR_PHY_SLICE_REGSET_NUM_H3VER2; - DDR_PHY_ADR_V_REGSET_NUM = - DDR_PHY_ADR_V_REGSET_NUM_H3VER2; - DDR_PHY_ADR_G_REGSET_NUM = - DDR_PHY_ADR_G_REGSET_NUM_H3VER2; - DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3VER2; - - DDR_PHY_ADR_I_NUM = 0; - } - } else if (prr_product == PRR_PRODUCT_M3) { - /* M3-W */ - _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, - DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3); - _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, - DDR_PHY_ADR_V_REGSET_M3, DDR_PHY_ADR_V_REGSET_NUM_M3); - _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, - DDR_PHY_ADR_I_REGSET_M3, DDR_PHY_ADR_I_REGSET_NUM_M3); - _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, - DDR_PHY_ADR_G_REGSET_M3, DDR_PHY_ADR_G_REGSET_NUM_M3); - _tblcopy(_cnf_DDR_PI_REGSET, - DDR_PI_REGSET_M3, DDR_PI_REGSET_NUM_M3); - - DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3; - DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3; - DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3; - DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3; - DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3; - DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3; - DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3; - DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3; - DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3; - DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3; - DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3; - DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3; - DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3; - DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3; - DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3; - - DDR_PHY_ADR_I_NUM = 2; - } else { - /* M3-N/V3H */ - _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, - DDR_PHY_SLICE_REGSET_M3N, - DDR_PHY_SLICE_REGSET_NUM_M3N); - _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_M3N, - DDR_PHY_ADR_V_REGSET_NUM_M3N); - _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, DDR_PHY_ADR_I_REGSET_M3N, - DDR_PHY_ADR_I_REGSET_NUM_M3N); - _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_M3N, - DDR_PHY_ADR_G_REGSET_NUM_M3N); - _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_M3N, - DDR_PI_REGSET_NUM_M3N); - - DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3N; - DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3N; - DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3N; - DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3N; - DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3N; - DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3N; - DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3N; - DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3N; - DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3N; - DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3N; - DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3N; - DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3N; - DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3N; - DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3N; - DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3N; - - DDR_PHY_ADR_I_NUM = 2; - } - - /* PLL CODE CHANGE */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { - ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, - 0x1142); - ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142); - } - - /* on fly gate adjust */ - if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) { - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_ON_FLY_GATE_ADJUST_EN, 0x00); - } - - /* Adjust PI parameters */ -#ifdef _def_LPDDR4_ODT - for (i = 0; i < 2; i++) { - for (csab = 0; csab < CSAB_CNT; csab++) { - ddrtbl_setval(_cnf_DDR_PI_REGSET, - reg_pi_mr11_data_fx_csx[i][csab], - _def_LPDDR4_ODT); - } - } -#endif /* _def_LPDDR4_ODT */ - -#ifdef _def_LPDDR4_VREFCA - for (i = 0; i < 2; i++) { - for (csab = 0; csab < CSAB_CNT; csab++) { - ddrtbl_setval(_cnf_DDR_PI_REGSET, - reg_pi_mr12_data_fx_csx[i][csab], - _def_LPDDR4_VREFCA); - } - } -#endif /* _def_LPDDR4_VREFCA */ - if ((prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; - if (js2[js2_tiedly] > (RL)) - js2[js2_tiedly] = RL; - } else if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut > PRR_PRODUCT_11)) { - js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; - } else if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) { - js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); - } - - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || - (prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - if ((js2[js2_tiedly]) >= 0x1e) - dataS = 0x1e; - else - dataS = js2[js2_tiedly]; - } else { - if ((js2[js2_tiedly]) >= 0x0e) - dataS = 0x0e; - else - dataS = js2[js2_tiedly]; - } - - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, - (dataS - 2)); - if ((prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_PHY_RDDATA_EN_OE_DLY, dataS); - } - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS); - - if (ddrtbl_getval - (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) { - data_l = WL - 1; - } else { - data_l = WL; - } - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2); - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l); - - if (board_cnf->dbi_en) { - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, - 0x01); - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_PHY_WDQLVL_DATADM_MASK, 0x000); - } else { - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, - 0x00); - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_PHY_WDQLVL_DATADM_MASK, 0x100); - } - - tmp[0] = js1[js1_ind].MR1; - tmp[1] = js1[js1_ind].MR2; - data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); - if (board_cnf->dbi_en) - tmp[2] = data_l | 0xc0; - else - tmp[2] = data_l & (~0xc0); - - for (i = 0; i < 2; i++) { - for (csab = 0; csab < CSAB_CNT; csab++) { - ddrtbl_setval(_cnf_DDR_PI_REGSET, - reg_pi_mr1_data_fx_csx[i][csab], tmp[0]); - ddrtbl_setval(_cnf_DDR_PI_REGSET, - reg_pi_mr2_data_fx_csx[i][csab], tmp[1]); - ddrtbl_setval(_cnf_DDR_PI_REGSET, - reg_pi_mr3_data_fx_csx[i][csab], tmp[2]); - } - } - - /* DDRPHY INT START */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - /* non */ - } else { - regif_pll_wa(); - } - - /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */ - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); - ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); - - /* SET DATA SLICE TABLE */ - for (slice = 0; slice < SLICE_CNT; slice++) { - adr = - DDR_PHY_SLICE_REGSET_OFS + - DDR_PHY_SLICE_REGSET_SIZE * slice; - for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) { - reg_ddrphy_write_a(adr + i, - _cnf_DDR_PHY_SLICE_REGSET[i]); - } - } - - /* SET ADR SLICE TABLE */ - adr = DDR_PHY_ADR_V_REGSET_OFS; - for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { - reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); - } - - if (((prr_product == PRR_PRODUCT_M3) || - (prr_product == PRR_PRODUCT_M3N)) && - ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40)) - != 0x00)) { - adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE; - for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { - reg_ddrphy_write_a(adr + i, - _cnf_DDR_PHY_ADR_V_REGSET[i]); - } - ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_ADR_DISABLE, 0x02); - DDR_PHY_ADR_I_NUM -= 1; - ddr_phycaslice = 1; - -#ifndef _def_LPDDR4_ODT - for (i = 0; i < 2; i++) { - for (csab = 0; csab < CSAB_CNT; csab++) { - ddrtbl_setval(_cnf_DDR_PI_REGSET, - reg_pi_mr11_data_fx_csx[i][csab], - 0x66); - } - } -#endif/* _def_LPDDR4_ODT */ - } else { - ddr_phycaslice = 0; - } - - if (DDR_PHY_ADR_I_NUM > 0) { - for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) { - adr = - DDR_PHY_ADR_I_REGSET_OFS + - DDR_PHY_ADR_I_REGSET_SIZE * slice; - for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) { - reg_ddrphy_write_a(adr + i, - _cnf_DDR_PHY_ADR_I_REGSET - [i]); - } - } - } - - /* SET ADRCTRL SLICE TABLE */ - adr = DDR_PHY_ADR_G_REGSET_OFS; - for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) { - reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); - } - - /* SET PI REGISTERS */ - adr = DDR_PI_REGSET_OFS; - for (i = 0; i < DDR_PI_REGSET_NUM; i++) { - reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); - } -} - -/* CONFIGURE DDR REGISTERS */ -static void ddr_config_sub(void) -{ - uint32_t i; - uint32_t ch, slice; - uint32_t data_l; - uint32_t tmp; - uint8_t high_byte[SLICE_CNT]; - const uint32_t _par_CALVL_DEVICE_MAP = 1; - - foreach_vch(ch) { - /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ - for (slice = 0; slice < SLICE_CNT; slice++) { - high_byte[slice] = - (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2; - ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, - board_cnf->ch[ch].dq_swap[slice]); - ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, - board_cnf->ch[ch].dm_swap[slice]); - if (high_byte[slice]) { - /* HIGHER 16 BYTE */ - ddr_setval_s(ch, slice, - _reg_PHY_CALVL_VREF_DRIVING_SLICE, - 0x00); - } else { - /* LOWER 16 BYTE */ - ddr_setval_s(ch, slice, - _reg_PHY_CALVL_VREF_DRIVING_SLICE, - 0x01); - } - } - - /* BOARD SETTINGS (CA,ADDR_SEL) */ - data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) | - 0x00888888; - - /* --- ADR_CALVL_SWIZZLE --- */ - if (prr_product == PRR_PRODUCT_M3) { - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, - 0x00000000); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, - 0x00000000); - ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, - _par_CALVL_DEVICE_MAP); - } else { - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); - ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, - _par_CALVL_DEVICE_MAP); - } - - /* --- ADR_ADDR_SEL --- */ - if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut > PRR_PRODUCT_11)) { - data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; - } else { - data_l = 0; - tmp = board_cnf->ch[ch].ca_swap; - for (i = 0; i < 6; i++) { - data_l |= ((tmp & 0x0f) << (i * 5)); - tmp = tmp >> 4; - } - } - ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l); - if (ddr_phycaslice == 1) { - /* ----------- adr slice2 swap ----------- */ - tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40); - data_l = (tmp & 0x00ffffff) | 0x00888888; - - /* --- ADR_CALVL_SWIZZLE --- */ - if (prr_product == PRR_PRODUCT_M3) { - ddr_setval_s(ch, 2, - _reg_PHY_ADR_CALVL_SWIZZLE0_0, - data_l); - ddr_setval_s(ch, 2, - _reg_PHY_ADR_CALVL_SWIZZLE1_0, - 0x00000000); - ddr_setval_s(ch, 2, - _reg_PHY_ADR_CALVL_SWIZZLE0_1, - data_l); - ddr_setval_s(ch, 2, - _reg_PHY_ADR_CALVL_SWIZZLE1_1, - 0x00000000); - ddr_setval_s(ch, 2, - _reg_PHY_ADR_CALVL_DEVICE_MAP, - _par_CALVL_DEVICE_MAP); - } else { - ddr_setval_s(ch, 2, - _reg_PHY_ADR_CALVL_SWIZZLE0, - data_l); - ddr_setval_s(ch, 2, - _reg_PHY_ADR_CALVL_SWIZZLE1, - 0x00000000); - ddr_setval_s(ch, 2, - _reg_PHY_CALVL_DEVICE_MAP, - _par_CALVL_DEVICE_MAP); - } - - /* --- ADR_ADDR_SEL --- */ - data_l = 0; - for (i = 0; i < 6; i++) { - data_l |= ((tmp & 0x0f) << (i * 5)); - tmp = tmp >> 4; - } - - ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l); - } - - /* BOARD SETTINGS (BYTE_ORDER_SEL) */ - if (prr_product == PRR_PRODUCT_M3) { - /* --- DATA_BYTE_SWAP --- */ - data_l = 0; - tmp = board_cnf->ch[ch].dqs_swap; - for (i = 0; i < 4; i++) { - data_l |= ((tmp & 0x03) << (i * 2)); - tmp = tmp >> 4; - } - } else { - /* --- DATA_BYTE_SWAP --- */ - data_l = board_cnf->ch[ch].dqs_swap; - ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01); - ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, - (data_l) & 0x0f); - ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, - (data_l >> 4 * 1) & 0x0f); - ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2, - (data_l >> 4 * 2) & 0x0f); - ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3, - (data_l >> 4 * 3) & 0x0f); - - ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00); - } - ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l); - } -} - -static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) -{ - uint32_t slice; - uint32_t tmp; - uint32_t tgt; - - if (ddr_csn / 2) { - tgt = 3; - } else { - tgt = 1; - } - - for (slice = 0; slice < SLICE_CNT; slice++) { - tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; - if (tgt == tmp) - break; - } - tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; - if (slice % 2) - tmp |= 0x00888888; - *p_swz = tmp; -} - -static void ddr_config_sub_h3v1x(void) -{ - uint32_t ch, slice; - uint32_t data_l; - uint32_t tmp; - uint8_t high_byte[SLICE_CNT]; - uint32_t ca_swizzle; - uint32_t ca; - uint32_t csmap; - uint32_t o_inv; - uint32_t inv; - uint32_t bit_soc; - uint32_t bit_mem; - uint32_t j; - - const uint8_t o_mr15 = 0x55; - const uint8_t o_mr20 = 0x55; - const uint16_t o_mr32_mr40 = 0x5a3c; - - foreach_vch(ch) { - /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ - csmap = 0; - for (slice = 0; slice < SLICE_CNT; slice++) { - tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & - 0x0f; - high_byte[slice] = tmp % 2; - if (tmp == 1 && (slice >= 2)) - csmap |= 0x05; - if (tmp == 3 && (slice >= 2)) - csmap |= 0x50; - ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING, - board_cnf->ch[ch].dq_swap[slice]); - if (high_byte[slice]) { - /* HIGHER 16 BYTE */ - ddr_setval_s(ch, slice, - _reg_PHY_CALVL_VREF_DRIVING_SLICE, - 0x00); - } else { - /* LOWER 16 BYTE */ - ddr_setval_s(ch, slice, - _reg_PHY_CALVL_VREF_DRIVING_SLICE, - 0x01); - } - } - /* BOARD SETTINGS (CA,ADDR_SEL) */ - ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; - ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca); - ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap); - - get_ca_swizzle(ch, 0, &ca_swizzle); - - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, ca_swizzle); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, 0x00000000); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); - ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01); - - for (slice = 0; slice < SLICE_CNT; slice++) { - ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM, - 0x01); - ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START, - 0x08); - - if (high_byte[slice]) - o_inv = o_mr20; - else - o_inv = o_mr15; - - tmp = board_cnf->ch[ch].dq_swap[slice]; - inv = 0; - j = 0; - for (bit_soc = 0; bit_soc < 8; bit_soc++) { - bit_mem = (tmp >> (4 * bit_soc)) & 0x0f; - j |= (1U << bit_mem); - if (o_inv & (1U << bit_mem)) - inv |= (1U << bit_soc); - } - data_l = o_mr32_mr40; - if (!high_byte[slice]) - data_l |= (inv << 24); - if (high_byte[slice]) - data_l |= (inv << 16); - ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8, - data_l); - } - } -} - -static void ddr_config(void) -{ - int32_t i; - uint32_t ch, slice; - uint32_t data_l; - uint32_t tmp; - int8_t _adj; - int16_t adj; - uint32_t dq; - union { - uint32_t ui32[4]; - uint8_t ui8[16]; - } patt; - uint16_t patm; - - /* configure ddrphy registers */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - ddr_config_sub_h3v1x(); - } else { /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ - ddr_config_sub(); - } - - /* WDQ_USER_PATT */ - foreach_vch(ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - patm = 0; - for (i = 0; i < 16; i++) { - tmp = board_cnf->ch[ch].wdqlvl_patt[i]; - patt.ui8[i] = tmp & 0xff; - if (tmp & 0x100) - patm |= (1U << i); - } - ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0, - patt.ui32[0]); - ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1, - patt.ui32[1]); - ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2, - patt.ui32[2]); - ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3, - patt.ui32[3]); - ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm); - } - } - - /* CACS DLY */ - data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - 0x00U); - foreach_vch(ch) { - for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4; i++) { - adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); - ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - data_l + adj); - reg_ddrphy_write(ch, - ddr_regdef_adr - (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), - _cnf_DDR_PHY_ADR_V_REGSET - [ddr_regdef_adr - (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - - DDR_PHY_ADR_V_REGSET_OFS]); - } - - for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); - i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { - adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); - ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - data_l + adj); - reg_ddrphy_write(ch, - ddr_regdef_adr - (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), - _cnf_DDR_PHY_ADR_G_REGSET - [ddr_regdef_adr - (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - - DDR_PHY_ADR_G_REGSET_OFS]); - } - - if (ddr_phycaslice == 1) { - for (i = 0; i < 6; i++) { - adj = _f_scale_adj - (board_cnf->ch[ch].cacs_adj - [i + - _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); - ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, - _reg_PHY_CLK_CACS_SLAVE_DELAY_X - [i], - data_l + adj); - reg_ddrphy_write(ch, - ddr_regdef_adr - (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + - 0x0100, - _cnf_DDR_PHY_ADR_V_REGSET - [ddr_regdef_adr - (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - - DDR_PHY_ADR_V_REGSET_OFS]); - } - } - } - - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); - - /* WDQDM DLY */ - data_l = board_cnf->dqdm_dly_w; - foreach_vch(ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - for (i = 0; i <= 8; i++) { - dq = slice * 8 + i; - if (i == 8) - _adj = board_cnf->ch[ch].dm_adj_w[slice]; - else - _adj = board_cnf->ch[ch].dq_adj_w[dq]; - adj = _f_scale_adj(_adj); - ddr_setval_s(ch, slice, - _reg_PHY_CLK_WRX_SLAVE_DELAY[i], - data_l + adj); - } - } - } - - /* RDQDM DLY */ - data_l = board_cnf->dqdm_dly_r; - foreach_vch(ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - for (i = 0; i <= 8; i++) { - dq = slice * 8 + i; - if (i == 8) - _adj = board_cnf->ch[ch].dm_adj_r[slice]; - else - _adj = board_cnf->ch[ch].dq_adj_r[dq]; - adj = _f_scale_adj(_adj); - ddr_setval_s(ch, slice, - _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY - [i], data_l + adj); - ddr_setval_s(ch, slice, - _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY - [i], data_l + adj); - } - } - } -} - -/* DBSC register setting functions */ -static void dbsc_regset_pre(void) -{ - uint32_t ch, csab; - uint32_t data_l; - - /* PRIMARY SETTINGS */ - /* LPDDR4, BL=16, DFI interface */ - mmio_write_32(DBSC_DBKIND, 0x0000000a); - mmio_write_32(DBSC_DBBL, 0x00000002); - mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); - - /* FREQRATIO=2 */ - mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - - /* Chanel map (H3 Ver.1.x) */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); - - /* DRAM SIZE REGISTER: - * set all ranks as density=0(4Gb) for PHY initialization - */ - foreach_vch(ch) { - for (csab = 0; csab < 4; csab++) { - mmio_write_32(DBSC_DBMEMCONF(ch, csab), - DBMEMCONF_REGD(0)); - } - } - - if (prr_product == PRR_PRODUCT_M3) { - data_l = 0xe4e4e4e4; - foreach_ech(ch) { - if ((ddr_phyvalid & (1U << ch))) - data_l = (data_l & (~(0x000000FF << (ch * 8)))) - | (((board_cnf->ch[ch].dqs_swap & 0x0003) - | ((board_cnf->ch[ch].dqs_swap & 0x0030) - >> 2) - | ((board_cnf->ch[ch].dqs_swap & 0x0300) - >> 4) - | ((board_cnf->ch[ch].dqs_swap & 0x3000) - >> 6)) << (ch * 8)); - } - mmio_write_32(DBSC_DBBSWAP, data_l); - } -} - -static void dbsc_regset(void) -{ - int32_t i; - uint32_t ch; - uint32_t data_l; - uint32_t data_l2; - uint32_t tmp[4]; - - /* RFC */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) && - (max_density == 0)) { - js2[js2_trfcab] = - _f_scale(ddr_mbps, ddr_mbpsdiv, - 1UL * jedec_spec2_trfc_ab[1] * 1000, 0); - } else { - js2[js2_trfcab] = - _f_scale(ddr_mbps, ddr_mbpsdiv, - 1UL * jedec_spec2_trfc_ab[max_density] * - 1000, 0); - } - - /* DBTR0.CL : RL */ - mmio_write_32(DBSC_DBTR(0), RL); - - /* DBTR1.CWL : WL */ - mmio_write_32(DBSC_DBTR(1), WL); - - /* DBTR2.AL : 0 */ - mmio_write_32(DBSC_DBTR(2), 0); - - /* DBTR3.TRCD: tRCD */ - mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]); - - /* DBTR4.TRPA,TRP: tRPab,tRPpb */ - mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]); - - /* DBTR5.TRC : use tRCpb */ - mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]); - - /* DBTR6.TRAS : tRAS */ - mmio_write_32(DBSC_DBTR(6), js2[js2_tras]); - - /* DBTR7.TRRD : tRRD */ - mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]); - - /* DBTR8.TFAW : tFAW */ - mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]); - - /* DBTR9.TRDPR : tRTP */ - mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]); - - /* DBTR10.TWR : nwr */ - mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr); - - /* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */ - mmio_write_32(DBSC_DBTR(11), - RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2); - - /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ - data_l = WL + 1 + (16 / 2) + js2[js2_twtr]; - mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l); - - /* DBTR13.TRFCAB : tRFCab */ - mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab])); - - /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */ - mmio_write_32(DBSC_DBTR(14), - (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd])); - - /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */ - mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd])); - - /* DBTR16 */ - /* WDQL : tphy_wrlat + tphy_wrdata */ - tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1); - /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0 - * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0 - */ - tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1); - /* DQL : tphy_rdlat + trdata_en */ - /* it is not important for dbsc */ - tmp[2] = RL + 16; - /* DQIENLTNCY : trdata_en */ - tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1; - mmio_write_32(DBSC_DBTR(16), - (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); - - /* DBTR24 */ - /* WRCSLAT = WRLAT -5 */ - tmp[0] -= 5; - /* WRCSGAP = 5 */ - tmp[1] = 5; - /* RDCSLAT = RDLAT_ADJ +2 */ - if (prr_product == PRR_PRODUCT_M3) { - tmp[2] = tmp[3]; - } else { - tmp[2] = tmp[3] + 2; - } - /* RDCSGAP = 6 */ - if (prr_product == PRR_PRODUCT_M3) { - tmp[3] = 4; - } else { - tmp[3] = 6; - } - mmio_write_32(DBSC_DBTR(24), - (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); - - /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */ - mmio_write_32(DBSC_DBTR(17), - (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16)); - - /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ - mmio_write_32(DBSC_DBTR(18), 0); - - /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */ - mmio_write_32(DBSC_DBTR(19), 0); - - /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ - data_l = js2[js2_trfcab] + js2[js2_tckehcmd]; - mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l); - - /* DBTR21.TCCD */ - /* DBTR23.TCCD */ - /* H3 Ver.1.0 cannot use TBTR23 feature */ - if (ddr_tccd == 8 && - !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10)) - ) { - data_l = 8; - mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); - mmio_write_32(DBSC_DBTR(23), 0x00000002); - } else if (ddr_tccd <= 11) { - data_l = 11; - mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); - mmio_write_32(DBSC_DBTR(23), 0x00000000); - } else { - data_l = ddr_tccd; - mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); - mmio_write_32(DBSC_DBTR(23), 0x00000000); - } - - /* DBTR22.ZQLAT : */ - data_l = js2[js2_tzqcalns] * 100; /* 1000 * 1000 ps */ - data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20); - mmio_write_32(DBSC_DBTR(22), data_l); - - /* DBTR25 : do not use in LPDDR4 */ - mmio_write_32(DBSC_DBTR(25), 0); - - /* DBRNK : */ - /* - * DBSC_DBRNK2 rkrr - * DBSC_DBRNK3 rkrw - * DBSC_DBRNK4 rkwr - * DBSC_DBRNK5 rkww - */ -#define _par_DBRNK_VAL (0x7007) - - for (i = 0; i < 4; i++) { - data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; - if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut > PRR_PRODUCT_11) && (i == 0)) { - data_l += 1; - } - data_l2 = 0; - foreach_vch(ch) { - data_l2 = data_l2 | (data_l << (4 * ch)); - } - mmio_write_32(DBSC_DBRNK(2 + i), data_l2); - } - mmio_write_32(DBSC_DBADJ0, 0x00000000); - - /* timing registers for Scheduler */ - /* SCFCTST0 */ - /* SCFCTST0 ACT-ACT */ - tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps; - /* SCFCTST0 RDA-ACT */ - tmp[2] = - 1UL * ((16 / 2) + js2[js2_trtp] - 8 + - js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps; - /* SCFCTST0 WRA-ACT */ - tmp[1] = - 1UL * (WL + 1 + (16 / 2) + - js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps; - /* SCFCTST0 PRE-ACT */ - tmp[0] = 1UL * js2[js2_trppb]; - mmio_write_32(DBSC_SCFCTST0, - (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); - - /* SCFCTST1 */ - /* SCFCTST1 RD-WR */ - tmp[3] = - 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xff) * 800 * ddr_mbpsdiv / - ddr_mbps; - /* SCFCTST1 WR-RD */ - tmp[2] = - 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv / - ddr_mbps; - /* SCFCTST1 ACT-RD/WR */ - tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps; - /* SCFCTST1 ASYNCOFS */ - tmp[0] = 12; - mmio_write_32(DBSC_SCFCTST1, - (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); - - /* DBSCHRW1 */ - /* DBSCHRW1 SCTRFCAB */ - tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps; - data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) - + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; - if (tmp[0] < data_l) - tmp[0] = data_l; - - if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { - mmio_write_32(DBSC_DBSCHRW1, tmp[0] - + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / - ddr_mbps - 3); - } else { - mmio_write_32(DBSC_DBSCHRW1, tmp[0] - + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / - ddr_mbps); - } - - /* QOS and CAM */ -#ifdef ddr_qos_init_setting /* only for non qos_init */ - /*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */ - mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); - /*0(fillunit),8(dirtymax),4(dirtymin) */ - mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); - /*stop_tolerance */ - mmio_write_32(DBSC_DBSCHRW0, 0x22421111); - /*rd-wr/wr-rd toggle priority */ - mmio_write_32(DBSC_SCFCTST2, 0x012F1123); - mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); - mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037); - - /* QoS Settings */ - mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U); - mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U); - mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U); - mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U); - mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U); - mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U); - mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U); - mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U); - mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U); - mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U); - mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U); - mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U); - mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U); - mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U); - mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U); - mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U); - mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U); - mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U); - mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U); - mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U); - mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U); - mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U); - mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U); - mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U); - mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U); - mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U); - mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U); - mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U); - - mmio_write_32(QOSCTRL_RAEN, 0x00000001U); -#endif /* ddr_qos_init_setting */ - /* H3 Ver.1.1 need to set monitor function */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { - mmio_write_32(DBSC_DBMONCONF4, 0x00700000); - } - - if (prr_product == PRR_PRODUCT_H3) { - if (prr_cut == PRR_PRODUCT_10) { - /* resrdis, simple mode, sc off */ - mmio_write_32(DBSC_DBBCAMDIS, 0x00000007); - } else if (prr_cut == PRR_PRODUCT_11) { - /* resrdis, simple mode */ - mmio_write_32(DBSC_DBBCAMDIS, 0x00000005); - } else if (prr_cut < PRR_PRODUCT_30) { - /* H3 Ver.2.0 */ - /* resrdis */ - mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); - } else { /* H3 Ver.3.0(include H3N) */ - /* exprespque */ - mmio_write_32(DBSC_DBBCAMDIS, 0x00000010); - } - } else { /* M3-W/M3-N/V3H */ - /* resrdis */ - mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); - } -} - -static void dbsc_regset_post(void) -{ - uint32_t ch, cs; - uint32_t data_l; - uint32_t slice, rdlat_max, rdlat_min; - - rdlat_max = 0; - rdlat_min = 0xffff; - foreach_vch(ch) { - for (cs = 0; cs < CS_CNT; cs++) { - if ((ch_have_this_cs[cs] & (1U << ch)) != 0) { - for (slice = 0; slice < SLICE_CNT; slice++) { - ddr_setval_s(ch, slice, - _reg_PHY_PER_CS_TRAINING_INDEX, - cs); - data_l = ddr_getval_s(ch, slice, - _reg_PHY_RDDQS_LATENCY_ADJUST); - if (data_l > rdlat_max) - rdlat_max = data_l; - if (data_l < rdlat_min) - rdlat_min = data_l; - } - } - } - } - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) { - mmio_write_32(DBSC_DBTR(24), - ((rdlat_max * 2 - rdlat_min + 4) << 24) + - ((rdlat_min + 2) << 16) + - mmio_read_32(DBSC_DBTR(24))); - } else { - mmio_write_32(DBSC_DBTR(24), - ((rdlat_max + 2) << 24) + - ((rdlat_max + 2) << 16) + - mmio_read_32(DBSC_DBTR(24))); - } - - /* set ddr density information */ - foreach_ech(ch) { - for (cs = 0; cs < CS_CNT; cs++) { - if (ddr_density[ch][cs] == 0xff) { - mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00); - } else { - mmio_write_32(DBSC_DBMEMCONF(ch, cs), - DBMEMCONF_REGD(ddr_density[ch] - [cs])); - } - } - mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000); - mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000); - } - - mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); - - /*set DBI */ - if (board_cnf->dbi_en) - mmio_write_32(DBSC_DBDBICNT, 0x00000003); - - /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */ - if ((((prr_product == PRR_PRODUCT_H3) && - (prr_cut > PRR_PRODUCT_11)) || - (prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) && - board_cnf->dbi_en) - reg_ddrphy_write_a(0x00001010, 0x01000000); - - /*set REFCYCLE */ - data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; - mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff)); - mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); - -#ifdef DDR_BACKUPMODE - if (ddr_backup == DRAM_BOOT_STATUS_WARM) { -#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */ - DEBUG(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1); - send_dbcmd(0x08040001); - wait_dbcmd(); - send_dbcmd(0x0A040001); - wait_dbcmd(); - send_dbcmd(0x04040010); - wait_dbcmd(); - - if (prr_product == PRR_PRODUCT_H3) { - send_dbcmd(0x08140001); - wait_dbcmd(); - send_dbcmd(0x0A140001); - wait_dbcmd(); - send_dbcmd(0x04140010); - wait_dbcmd(); - } -#else /* DDR_BACKUPMODE_HALF //for All channels */ - send_dbcmd(0x08840001); - wait_dbcmd(); - send_dbcmd(0x0A840001); - wait_dbcmd(); - - send_dbcmd(0x04840010); - wait_dbcmd(); -#endif /* DDR_BACKUPMODE_HALF */ - } -#endif /* DDR_BACKUPMODE */ - -#if RCAR_REWT_TRAINING != 0 - /* Periodic-WriteDQ Training seeting */ - if (((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) || - ((prr_product == PRR_PRODUCT_M3) && - (prr_cut == PRR_PRODUCT_10))) { - /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ - } else { - /* - * H3 Ver.2.0 or later/M3-W Ver.1.1 or - * later/M3-N/V3H -> Periodic-WriteDQ Training seeting - */ - - /* Periodic WriteDQ Training seeting */ - mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000); - - ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04); - ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0F); - ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50); - ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300); - - ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP, - ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_WDQLVL_CS_MAP)); - ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f); - ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); - ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100); - ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01); - ddr_setval_ach(_reg_PI_TREF_F0, 0x0000); - ddr_setval_ach(_reg_PI_TREF_F1, 0x0000); - ddr_setval_ach(_reg_PI_TREF_F2, 0x0000); - - if (prr_product == PRR_PRODUCT_M3) { - ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02); - } else { - ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02); - } - ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01); - - /* DFI_PHYMSTR_ACK , WTmode setting */ - /* DFI_PHYMSTR_ACK: WTmode =b'01 */ - mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); - } -#endif /* RCAR_REWT_TRAINING */ - /* periodic dram zqcal and phy ctrl update enable */ - mmio_write_32(DBSC_DBCALCNF, 0x01000010); - if (((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) || - ((prr_product == PRR_PRODUCT_M3) && - (prr_cut < PRR_PRODUCT_30))) { - /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ - } else { -#if RCAR_DRAM_SPLIT == 2 - if ((prr_product == PRR_PRODUCT_H3) && - (board_cnf->phyvalid == 0x05)) - mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); - else - mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); -#else /* RCAR_DRAM_SPLIT == 2 */ - mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); -#endif /* RCAR_DRAM_SPLIT == 2 */ - } - - mmio_write_32(DBSC_DBRFEN, 0x00000001); - /* dram access enable */ - mmio_write_32(DBSC_DBACEN, 0x00000001); - - MSG_LF(__func__ "(done)"); -} - -/* DFI_INIT_START */ -static uint32_t dfi_init_start(void) -{ - uint32_t ch; - uint32_t phytrainingok; - uint32_t retry; - uint32_t data_l; - const uint32_t RETRY_MAX = 0x10000; - - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - /* PLL3 Disable */ - /* protect register interface */ - ddrphy_regif_idle(); - - pll3_control(0); - - /* init start */ - /* dbdficnt0: - * dfi_dram_clk_disable=1 - * dfi_frequency = 0 - * freq_ratio = 01 (2:1) - * init_start =0 - */ - foreach_vch(ch) - mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); - dsb_sev(); - - /* dbdficnt0: - * dfi_dram_clk_disable=1 - * dfi_frequency = 0 - * freq_ratio = 01 (2:1) - * init_start =1 - */ - foreach_vch(ch) - mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); - dsb_sev(); - - } else { - ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02); - dsb_sev(); - ddrphy_regif_idle(); - } - - /* dll_rst negate */ - foreach_vch(ch) - mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01); - dsb_sev(); - - /* wait init_complete */ - phytrainingok = 0; - retry = 0; - while (retry++ < RETRY_MAX) { - foreach_vch(ch) { - data_l = mmio_read_32(DBSC_DBDFISTAT(ch)); - if (data_l & 0x00000001) - phytrainingok |= (1U << ch); - } - dsb_sev(); - if (phytrainingok == ddr_phyvalid) - break; - if (retry % 256 == 0) - ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); - } - - /* all ch ok? */ - if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) - return 0xff; - - /* dbdficnt0: - * dfi_dram_clk_disable=0 - * dfi_frequency = 0 - * freq_ratio = 01 (2:1) - * init_start =0 - */ - foreach_vch(ch) - mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010); - dsb_sev(); - - return 0; -} - -/* drivablity setting : CMOS MODE ON/OFF */ -static void change_lpddr4_en(uint32_t mode) -{ - uint32_t ch; - uint32_t i; - uint32_t data_l; - const uint32_t _reg_PHY_PAD_DRIVE_X[3] = { - _reg_PHY_PAD_ADDR_DRIVE, - _reg_PHY_PAD_CLK_DRIVE, - _reg_PHY_PAD_CS_DRIVE - }; - - foreach_vch(ch) { - for (i = 0; i < 3; i++) { - data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); - if (mode) { - data_l |= (1U << 14); - } else { - data_l &= ~(1U << 14); - } - ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l); - } - } -} - -/* drivablity setting */ -static uint32_t set_term_code(void) -{ - int32_t i; - uint32_t ch, index; - uint32_t data_l; - uint32_t chip_id[2]; - uint32_t term_code; - uint32_t override; - uint32_t pvtr; - uint32_t pvtp; - uint32_t pvtn; - - term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_PAD_DATA_TERM); - override = 0; - for (i = 0; i < 2; i++) - chip_id[i] = mmio_read_32(LIFEC_CHIPID(i)); - - index = 0; - while (1) { - if (termcode_by_sample[index][0] == 0xffffffff) { - break; - } - if ((termcode_by_sample[index][0] == chip_id[0]) && - (termcode_by_sample[index][1] == chip_id[1])) { - term_code = termcode_by_sample[index][2]; - override = 1; - break; - } - index++; - } - - if (override) { - for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { - data_l = - ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_PAD_TERM_X[index]); - data_l = (data_l & 0xfffe0000) | term_code; - ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l); - } - } else if ((prr_product == PRR_PRODUCT_M3) && - (prr_cut == PRR_PRODUCT_10)) { - /* non */ - } else { - ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], - (ddrtbl_getval - (_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000)); - ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01); - ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01); - foreach_vch(ch) { - do { - data_l = - ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); - } while (!(data_l & 0x00800000)); - } - if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) { - foreach_vch(ch) { - data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); - pvtr = (data_l >> 12) & 0x1f; - pvtr += 8; - if (pvtr > 0x1f) - pvtr = 0x1f; - data_l = - ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); - pvtn = (data_l >> 6) & 0x03f; - pvtp = (data_l >> 0) & 0x03f; - - for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; - index++) { - data_l = - ddrtbl_getval - (_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_PAD_TERM_X[index]); - data_l = (data_l & 0xfffe0000) - | (pvtr << 12) - | (pvtn << 6) - | (pvtp); - ddr_setval(ch, - _reg_PHY_PAD_TERM_X[index], - data_l); - } - } - } else { - /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ - foreach_vch(ch) { - for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; - index++) { - data_l = - ddr_getval(ch, - _reg_PHY_PAD_TERM_X - [index]); - ddr_setval(ch, - _reg_PHY_PAD_TERM_X[index], - (data_l & 0xFFFE0FFF) | - 0x00015000); - } - } - } - } - - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - /* non */ - } else { - ddr_padcal_tcompensate_getinit(override); - } - - return 0; -} - -/* DDR mode register setting */ -static void ddr_register_set(void) -{ - int32_t fspwp; - uint32_t tmp; - - for (fspwp = 1; fspwp >= 0; fspwp--) { - /*MR13, fspwp */ - send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6)); - - tmp = - ddrtbl_getval(_cnf_DDR_PI_REGSET, - reg_pi_mr1_data_fx_csx[fspwp][0]); - send_dbcmd(0x0e840100 | tmp); - - tmp = - ddrtbl_getval(_cnf_DDR_PI_REGSET, - reg_pi_mr2_data_fx_csx[fspwp][0]); - send_dbcmd(0x0e840200 | tmp); - - tmp = - ddrtbl_getval(_cnf_DDR_PI_REGSET, - reg_pi_mr3_data_fx_csx[fspwp][0]); - send_dbcmd(0x0e840300 | tmp); - - tmp = - ddrtbl_getval(_cnf_DDR_PI_REGSET, - reg_pi_mr11_data_fx_csx[fspwp][0]); - send_dbcmd(0x0e840b00 | tmp); - - tmp = - ddrtbl_getval(_cnf_DDR_PI_REGSET, - reg_pi_mr12_data_fx_csx[fspwp][0]); - send_dbcmd(0x0e840c00 | tmp); - - tmp = - ddrtbl_getval(_cnf_DDR_PI_REGSET, - reg_pi_mr14_data_fx_csx[fspwp][0]); - send_dbcmd(0x0e840e00 | tmp); - /* MR22 */ - send_dbcmd(0x0e841616); - - /* ZQCAL start */ - send_dbcmd(0x0d84004F); - - /* ZQLAT */ - send_dbcmd(0x0d840051); - } - - /* MR13, fspwp */ - send_dbcmd(0x0e840d08); -} - -/* Training handshake functions */ -static inline uint32_t wait_freqchgreq(uint32_t assert) -{ - uint32_t data_l; - uint32_t count; - uint32_t ch; - - count = 100000; - - /* H3 Ver.1.x cannot see frqchg_req */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - return 0; - } - - if (assert) { - do { - data_l = 1; - foreach_vch(ch) { - data_l &= mmio_read_32(DBSC_DBPDSTAT(ch)); - } - count = count - 1; - } while (((data_l & 0x01) != 0x01) & (count != 0)); - } else { - do { - data_l = 0; - foreach_vch(ch) { - data_l |= mmio_read_32(DBSC_DBPDSTAT(ch)); - } - count = count - 1; - } while (((data_l & 0x01) != 0x00) & (count != 0)); - } - - return (count == 0); -} - -static inline void set_freqchgack(uint32_t assert) -{ - uint32_t ch; - uint32_t data_l; - - if (assert) - data_l = 0x0CF20000; - else - data_l = 0x00000000; - - foreach_vch(ch) - mmio_write_32(DBSC_DBPDCNT2(ch), data_l); -} - -static inline void set_dfifrequency(uint32_t freq) -{ - uint32_t ch; - - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - foreach_vch(ch) - mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq); - } else { - foreach_vch(ch) { - mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, - (freq << 24)); - } - } - dsb_sev(); -} - -static uint32_t pll3_freq(uint32_t on) -{ - uint32_t timeout; - - timeout = wait_freqchgreq(1); - - if (timeout) { - return 1; - } - - pll3_control(on); - set_dfifrequency(on); - - set_freqchgack(1); - timeout = wait_freqchgreq(0); - set_freqchgack(0); - - if (timeout) { - FATAL_MSG("BL2: Time out[2]\n"); - return 1; - } - return 0; -} - -/* update dly */ -static void update_dly(void) -{ - ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01); - ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01); -} - -/* training by pi */ -static uint32_t pi_training_go(void) -{ - uint32_t flag; - uint32_t data_l; - uint32_t retry; - const uint32_t RETRY_MAX = 4096 * 16; - uint32_t ch; - - uint32_t mst_ch; - uint32_t cur_frq; - uint32_t complete; - uint32_t frqchg_req; - - /* pi_start */ - ddr_setval_ach(_reg_PI_START, 0x01); - foreach_vch(ch) - ddr_getval(ch, _reg_PI_INT_STATUS); - - /* set dfi_phymstr_ack = 1 */ - mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001); - dsb_sev(); - - /* wait pi_int_status[0] */ - mst_ch = 0; - flag = 0; - complete = 0; - cur_frq = 0; - retry = RETRY_MAX; - do { - frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; - - /* H3 Ver.1.x cannot see frqchg_req */ - if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) { - if ((retry % 4096) == 1) { - frqchg_req = 1; - } else { - frqchg_req = 0; - } - } - - if (frqchg_req) { - if (cur_frq) { - /* Low frequency */ - flag = pll3_freq(0); - cur_frq = 0; - } else { - /* High frequency */ - flag = pll3_freq(1); - cur_frq = 1; - } - if (flag) - break; - } else { - if (cur_frq) { - foreach_vch(ch) { - if (complete & (1U << ch)) - continue; - data_l = - ddr_getval(ch, _reg_PI_INT_STATUS); - if (data_l & 0x01) { - complete |= (1U << ch); - } - } - if (complete == ddr_phyvalid) - break; - } - } - } while (--retry); - foreach_vch(ch) { - /* dummy read */ - data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); - data_l = ddr_getval(ch, _reg_PI_INT_STATUS); - ddr_setval(ch, _reg_PI_INT_ACK, data_l); - } - if (ddrphy_regif_chk()) { - return 0xfd; - } - return complete; -} - -/* Initialize DDR */ -static uint32_t init_ddr(void) -{ - int32_t i; - uint32_t data_l; - uint32_t phytrainingok; - uint32_t ch, slice; - uint32_t err; - int16_t adj; - - MSG_LF(__func__ ":0\n"); - -#ifdef DDR_BACKUPMODE - rcar_dram_get_boot_status(&ddr_backup); -#endif - - /* unlock phy */ - /* Unlock DDRPHY register(AGAIN) */ - foreach_vch(ch) - mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); - dsb_sev(); - - if ((((prr_product == PRR_PRODUCT_H3) && - (prr_cut > PRR_PRODUCT_11)) || - (prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) && board_cnf->dbi_en) - reg_ddrphy_write_a(0x00001010, 0x01000001); - else - reg_ddrphy_write_a(0x00001010, 0x00000001); - /* DBSC register pre-setting */ - dbsc_regset_pre(); - - /* load ddrphy registers */ - - ddrtbl_load(); - - /* configure ddrphy registers */ - ddr_config(); - - /* dfi_reset assert */ - foreach_vch(ch) - mmio_write_32(DBSC_DBPDCNT0(ch), 0x01); - dsb_sev(); - - /* dbsc register set */ - dbsc_regset(); - MSG_LF(__func__ ":1\n"); - - /* dfi_reset negate */ - foreach_vch(ch) - mmio_write_32(DBSC_DBPDCNT0(ch), 0x00); - dsb_sev(); - - /* dfi_init_start (start ddrphy) */ - err = dfi_init_start(); - if (err) { - return INITDRAM_ERR_I; - } - MSG_LF(__func__ ":2\n"); - - /* ddr backupmode end */ -#ifdef DDR_BACKUPMODE - if (ddr_backup) { - NOTICE("BL2: [WARM_BOOT]\n"); - } else { - NOTICE("BL2: [COLD_BOOT]\n"); - } - err = rcar_dram_update_boot_status(ddr_backup); - if (err) { - NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); - return INITDRAM_ERR_I; - } -#endif - MSG_LF(__func__ ":3\n"); - - /* override term code after dfi_init_complete */ - err = set_term_code(); - if (err) { - return INITDRAM_ERR_I; - } - MSG_LF(__func__ ":4\n"); - - /* rx offset calibration */ - if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - err = rx_offset_cal_hw(); - } else { - err = rx_offset_cal(); - } - if (err) - return INITDRAM_ERR_O; - MSG_LF(__func__ ":5\n"); - - /* PDX */ - send_dbcmd(0x08840001); - - /* check register i/f is alive */ - err = ddrphy_regif_chk(); - if (err) { - return INITDRAM_ERR_O; - } - MSG_LF(__func__ ":6\n"); - - /* phy initialize end */ - - /* setup DDR mode registers */ - /* CMOS MODE */ - change_lpddr4_en(0); - - /* MRS */ - ddr_register_set(); - - /* Thermal sensor setting */ - /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ - data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; - mmio_write_32(THS1_THCTR, data_l); - - /* LPDDR4 MODE */ - change_lpddr4_en(1); - - MSG_LF(__func__ ":7\n"); - - /* mask CS_MAP if RANKx is not found */ - foreach_vch(ch) { - data_l = ddr_getval(ch, _reg_PI_CS_MAP); - if (!(ch_have_this_cs[1] & (1U << ch))) - data_l = data_l & 0x05; - ddr_setval(ch, _reg_PI_CS_MAP, data_l); - } - - /* exec pi_training */ - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); - ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); - - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); - } else { - foreach_vch(ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - ddr_setval_s(ch, slice, - _reg_PHY_PER_CS_TRAINING_EN, - ((ch_have_this_cs[1]) >> ch) - & 0x01); - } - } - } - - phytrainingok = pi_training_go(); - - if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) { - return INITDRAM_ERR_T | phytrainingok; - } - - MSG_LF(__func__ ":8\n"); - - /* CACS DLY ADJUST */ - data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); - foreach_vch(ch) { - for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { - adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); - ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - data_l + adj); - } - - if (ddr_phycaslice == 1) { - for (i = 0; i < 6; i++) { - adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj - [i + - _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); - ddr_setval_s(ch, 2, - _reg_PHY_CLK_CACS_SLAVE_DELAY_X - [i], - data_l + adj - ); - } - } - } - - update_dly(); - MSG_LF(__func__ ":9\n"); - - /* H3 fix rd latency to avoid bug in elasitic buffer */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - adjust_rddqs_latency(); - - /* Adjust Write path latency */ - if (ddrtbl_getval - (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) - adjust_wpath_latency(); - - /* RDQLVL Training */ - if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) - ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); - - err = rdqdm_man(); - - if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) - ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00); - - if (err) { - return INITDRAM_ERR_T; - } - update_dly(); - MSG_LF(__func__ ":10\n"); - - /* WDQLVL Training */ - err = wdqdm_man(); - if (err) { - return INITDRAM_ERR_T; - } - update_dly(); - MSG_LF(__func__ ":11\n"); - - /* training complete, setup DBSC */ - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || - (prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); - ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); - } - - dbsc_regset_post(); - MSG_LF(__func__ ":12\n"); - - return phytrainingok; -} - -/* SW LEVELING COMMON */ -static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) -{ - uint32_t ch; - uint32_t data_l; - uint32_t retry; - uint32_t waiting; - uint32_t err; - - const uint32_t RETRY_MAX = 0x1000; - - err = 0; - /* set EXIT -> OP_DONE is cleared */ - ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); - - /* kick */ - foreach_vch(ch) { - if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) { - ddr_setval(ch, reg_cs, ddr_csn); - ddr_setval(ch, reg_kick, 0x01); - } - } - foreach_vch(ch) { - /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */ - ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); - } - waiting = ch_have_this_cs[ddr_csn % 2]; - dsb_sev(); - retry = RETRY_MAX; - do { - foreach_vch(ch) { - if (!(waiting & (1U << ch))) - continue; - data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); - if (data_l & 0x01) - waiting &= ~(1U << ch); - } - retry--; - } while (waiting && (retry > 0)); - if (retry == 0) { - err = 1; - } - - dsb_sev(); - /* set EXIT -> OP_DONE is cleared */ - ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); - dsb_sev(); - - return err; -} - -/* WDQ TRAINING */ -#ifndef DDR_FAST_INIT -static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) -{ - int32_t i, k; - uint32_t cs, slice; - uint32_t data_l; - - /* clr of training results buffer */ - cs = ddr_csn % 2; - data_l = board_cnf->dqdm_dly_w; - for (slice = 0; slice < SLICE_CNT; slice++) { - k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; - if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) - continue; - - for (i = 0; i <= 8; i++) { - if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) - wdqdm_dly[ch][cs][slice][i] = - wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; - else - wdqdm_dly[ch][cs][slice][i] = data_l; - wdqdm_le[ch][cs][slice][i] = 0; - wdqdm_te[ch][cs][slice][i] = 0; - } - wdqdm_st[ch][cs][slice] = 0; - wdqdm_win[ch][cs][slice] = 0; - } -} - -static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) -{ - int32_t i, k; - uint32_t cs, slice; - uint32_t data_l; - uint32_t err; - const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0; - - int32_t min_win; - int32_t win; - int8_t _adj; - int16_t adj; - uint32_t dq; - - /* analysis of training results */ - err = 0; - for (slice = 0; slice < SLICE_CNT; slice += 1) { - k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; - if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) - continue; - - cs = ddr_csn % 2; - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); - for (i = 0; i < 9; i++) { - dq = slice * 8 + i; - if (i == 8) - _adj = board_cnf->ch[ch].dm_adj_w[slice]; - else - _adj = board_cnf->ch[ch].dq_adj_w[dq]; - adj = _f_scale_adj(_adj); - - data_l = - ddr_getval_s(ch, slice, - _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], - data_l); - wdqdm_dly[ch][cs][slice][i] = data_l; - } - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); - data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); - wdqdm_st[ch][cs][slice] = data_l; - min_win = INT_LEAST32_MAX; - for (i = 0; i <= 8; i++) { - ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT, - i); - - data_l = - ddr_getval_s(ch, slice, - _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS); - wdqdm_te[ch][cs][slice][i] = data_l; - data_l = - ddr_getval_s(ch, slice, - _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); - wdqdm_le[ch][cs][slice][i] = data_l; - win = - (int32_t)wdqdm_te[ch][cs][slice][i] - - wdqdm_le[ch][cs][slice][i]; - if (min_win > win) - min_win = win; - if (data_l >= _par_WDQLVL_RETRY_THRES) - err = 2; - } - wdqdm_win[ch][cs][slice] = min_win; - if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) { - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, - 0x01); - } else { - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, - ((ch_have_this_cs[1]) >> ch) & 0x01); - } - } - return err; -} -#endif/* DDR_FAST_INIT */ - -static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore) -{ - uint32_t i; - uint32_t ch, slice; - uint32_t tgt_cs, src_cs; - uint32_t tmp_r; - - /* copy of training results */ - foreach_vch(ch) { - for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) { - for (slice = 0; slice < SLICE_CNT; slice++) { - ddr_setval_s(ch, slice, - _reg_PHY_PER_CS_TRAINING_INDEX, - tgt_cs); - src_cs = ddr_csn % 2; - if (!(ch_have_this_cs[1] & (1U << ch))) - src_cs = 0; - for (i = 0; i <= 4; i += 4) { - if (restore) - tmp_r = - rdqdm_dly[ch][tgt_cs][slice] - [i]; - else - tmp_r = - rdqdm_dly[ch][src_cs][slice] - [i]; - - ddr_setval_s(ch, slice, - _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY - [i], tmp_r); - } - } - } - } -} - -static uint32_t wdqdm_man1(void) -{ - int32_t k; - uint32_t ch, cs, slice; - uint32_t ddr_csn; - uint32_t data_l; - uint32_t err; - uint32_t high_dq[DRAM_CH_CNT]; - uint32_t mr14_csab0_bak[DRAM_CH_CNT]; -#ifndef DDR_FAST_INIT - uint32_t err_flg; -#endif/* DDR_FAST_INIT */ - - /* manual execution of training */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - foreach_vch(ch) { - high_dq[ch] = 0; - for (slice = 0; slice < SLICE_CNT; slice++) { - k = (board_cnf->ch[ch].dqs_swap >> - (4 * slice)) & 0x0f; - if (k >= 2) - high_dq[ch] |= (1U << slice); - } - ddr_setval(ch, _reg_PI_16BIT_DRAM_CONNECT, 0x00); - } - } - err = 0; - /* CLEAR PREV RESULT */ - for (cs = 0; cs < CS_CNT; cs++) { - ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); - if (((prr_product == PRR_PRODUCT_H3) && - (prr_cut > PRR_PRODUCT_11)) || - (prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, - 0x01); - } else { - ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, - 0x01); - } - } - ddrphy_regif_idle(); - -#ifndef DDR_FAST_INIT - err_flg = 0; -#endif/* DDR_FAST_INIT */ - for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { - if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) { - foreach_vch(ch) { - data_l = mmio_read_32(DBSC_DBDFICNT(ch)); - data_l &= ~(0x00ffU << 16); - - if (ddr_csn >= 2) - k = (high_dq[ch] ^ 0x0f); - else - k = high_dq[ch]; - data_l |= (k << 16); - mmio_write_32(DBSC_DBDFICNT(ch), data_l); - ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k); - } - } - if (((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) || - ((prr_product == PRR_PRODUCT_M3) && - (prr_cut == PRR_PRODUCT_10))) { - wdqdm_cp(ddr_csn, 0); - } - - foreach_vch(ch) { - data_l = - ddr_getval(ch, - reg_pi_mr14_data_fx_csx[1][ddr_csn]); - ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l); - } - - /* KICK WDQLVL */ - err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ); - if (err) - goto err_exit; - - if (ddr_csn == 0) - foreach_vch(ch) { - mr14_csab0_bak[ch] = - ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]); - } else - foreach_vch(ch) { - ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], - mr14_csab0_bak[ch]); - } -#ifndef DDR_FAST_INIT - foreach_vch(ch) { - if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { - wdqdm_clr1(ch, ddr_csn); - continue; - } - err = wdqdm_ana1(ch, ddr_csn); - if (err) - err_flg |= (1U << (ddr_csn * 4 + ch)); - ddrphy_regif_idle(); - } -#endif/* DDR_FAST_INIT */ - } -err_exit: -#ifndef DDR_FAST_INIT - err |= err_flg; -#endif/* DDR_FAST_INIT */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01); - foreach_vch(ch) { - data_l = mmio_read_32(DBSC_DBDFICNT(ch)); - data_l &= ~(0x00ffU << 16); - mmio_write_32(DBSC_DBDFICNT(ch), data_l); - ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00); - } - } - return err; -} - -static uint32_t wdqdm_man(void) -{ - uint32_t err, retry_cnt; - const uint32_t retry_max = 0x10; - uint32_t ch, ddr_csn, mr14_bkup[4][4]; - - ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, - (mmio_read_32(DBSC_DBTR(11)) & 0xFF) + 19); - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || - (prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0, - (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); - ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, - (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); - } else { - ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR, - (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); - } - ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); - ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); - - retry_cnt = 0; - err = 0; - do { - if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) { - err = wdqdm_man1(); - } else { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); - ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, - 0x01); - if ((prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, - 0x0C); - } else { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C); - } - dsb_sev(); - err = wdqdm_man1(); - foreach_vch(ch) { - for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { - mr14_bkup[ch][ddr_csn] = - ddr_getval(ch, - reg_pi_mr14_data_fx_csx - [1][ddr_csn]); - dsb_sev(); - } - } - - if ((prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, - 0x04); - } else { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04); - } - pvtcode_update(); - err = wdqdm_man1(); - foreach_vch(ch) { - for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { - mr14_bkup[ch][ddr_csn] = - (mr14_bkup[ch][ddr_csn] + - ddr_getval(ch, - reg_pi_mr14_data_fx_csx - [1][ddr_csn])) / 2; - ddr_setval(ch, - reg_pi_mr14_data_fx_csx[1] - [ddr_csn], - mr14_bkup[ch][ddr_csn]); - } - } - - ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, - 0x00); - if ((prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, - 0x00); - ddr_setval_ach - (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1, - 0x00); - ddr_setval_ach - (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, - 0x00); - } else { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x00); - ddr_setval_ach - (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, - 0x00); - ddr_setval_ach - (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, - 0x00); - } - ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, - 0x00); - - pvtcode_update2(); - err = wdqdm_man1(); - ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); - } - } while (err && (++retry_cnt < retry_max)); - - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || - ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) { - wdqdm_cp(0, 1); - } - - return (retry_cnt >= retry_max); -} - -/* RDQ TRAINING */ -#ifndef DDR_FAST_INIT -static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) -{ - int32_t i, k; - uint32_t cs, slice; - uint32_t data_l; - - /* clr of training results buffer */ - cs = ddr_csn % 2; - data_l = board_cnf->dqdm_dly_r; - for (slice = 0; slice < SLICE_CNT; slice++) { - k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; - if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) - continue; - - for (i = 0; i <= 8; i++) { - if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) { - rdqdm_dly[ch][cs][slice][i] = - rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = - rdqdm_dly[ch][CS_CNT - 1 - cs][slice + - SLICE_CNT] - [i]; - } else { - rdqdm_dly[ch][cs][slice][i] = data_l; - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = - data_l; - } - rdqdm_le[ch][cs][slice][i] = 0; - rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; - rdqdm_te[ch][cs][slice][i] = 0; - rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0; - rdqdm_nw[ch][cs][slice][i] = 0; - rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0; - } - rdqdm_st[ch][cs][slice] = 0; - rdqdm_win[ch][cs][slice] = 0; - } -} - -static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) -{ - int32_t i, k; - uint32_t cs, slice; - uint32_t data_l; - uint32_t err; - int8_t _adj; - int16_t adj; - uint32_t dq; - int32_t min_win; - int32_t win; - uint32_t rdq_status_obs_select; - - /* analysis of training results */ - err = 0; - for (slice = 0; slice < SLICE_CNT; slice++) { - k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; - if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) - continue; - - cs = ddr_csn % 2; - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); - ddrphy_regif_idle(); - - ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX); - ddrphy_regif_idle(); - - for (i = 0; i <= 8; i++) { - dq = slice * 8 + i; - if (i == 8) - _adj = board_cnf->ch[ch].dm_adj_r[slice]; - else - _adj = board_cnf->ch[ch].dq_adj_r[dq]; - - adj = _f_scale_adj(_adj); - - data_l = - ddr_getval_s(ch, slice, - _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + - adj; - ddr_setval_s(ch, slice, - _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], - data_l); - rdqdm_dly[ch][cs][slice][i] = data_l; - - data_l = - ddr_getval_s(ch, slice, - _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + - adj; - ddr_setval_s(ch, slice, - _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], - data_l); - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l; - } - min_win = INT_LEAST32_MAX; - for (i = 0; i <= 8; i++) { - data_l = - ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS); - rdqdm_st[ch][cs][slice] = data_l; - rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l; - /* k : rise/fall */ - for (k = 0; k < 2; k++) { - if (i == 8) { - rdq_status_obs_select = 16 + 8 * k; - } else { - rdq_status_obs_select = i + k * 8; - } - ddr_setval_s(ch, slice, - _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT, - rdq_status_obs_select); - - data_l = - ddr_getval_s(ch, slice, - _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); - rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = - data_l; - - data_l = - ddr_getval_s(ch, slice, - _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); - rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = - data_l; - - data_l = - ddr_getval_s(ch, slice, - _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS); - rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = - data_l; - - win = - (int32_t)rdqdm_te[ch][cs][slice + - SLICE_CNT * - k][i] - - rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; - if (i != 8) { - if (min_win > win) - min_win = win; - } - } - } - rdqdm_win[ch][cs][slice] = min_win; - if (min_win <= 0) { - err = 2; - } - } - return err; -} -#endif/* DDR_FAST_INIT */ - -static uint32_t rdqdm_man1(void) -{ - uint32_t ch; - uint32_t ddr_csn; -#ifdef DDR_FAST_INIT - uint32_t slice; - uint32_t i, adj, data_l; -#endif/* DDR_FAST_INIT */ - uint32_t err; - - /* manual execution of training */ - err = 0; - - for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { - /* KICK RDQLVL */ - err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ); - if (err) - goto err_exit; -#ifndef DDR_FAST_INIT - foreach_vch(ch) { - if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { - rdqdm_clr1(ch, ddr_csn); - ddrphy_regif_idle(); - continue; - } - err = rdqdm_ana1(ch, ddr_csn); - ddrphy_regif_idle(); - if (err) - goto err_exit; - } -#else/* DDR_FAST_INIT */ - foreach_vch(ch) { - if (ch_have_this_cs[ddr_csn] & (1U << ch)) { - for (slice = 0; slice < SLICE_CNT; slice++) { - if (ddr_getval_s(ch, slice, - _reg_PHY_RDLVL_STATUS_OBS) != - 0x0D00FFFF) { - err = (1U << ch) | - (0x10U << slice); - goto err_exit; - } - } - } - if (((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) || - ((prr_product == PRR_PRODUCT_M3) && - (prr_cut <= PRR_PRODUCT_10))) { - for (slice = 0; slice < SLICE_CNT; slice++) { - for (i = 0; i <= 8; i++) { - if (i == 8) - adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]); - else - adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]); - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn); - data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l); - rdqdm_dly[ch][ddr_csn][slice][i] = data_l; - rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l; - - data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l); - rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l; - rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l; - } - } - } - } - ddrphy_regif_idle(); - -#endif/* DDR_FAST_INIT */ - } - -err_exit: - return err; -} - -static uint32_t rdqdm_man(void) -{ - uint32_t err, retry_cnt; - const uint32_t retry_max = 0x01; - - ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, - 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_PHY_DQ_TSEL_ENABLE)); - ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, - 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_PHY_DQS_TSEL_ENABLE)); - ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, - 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_PHY_DQ_TSEL_SELECT)); - ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, - 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_PHY_DQS_TSEL_SELECT)); - - retry_cnt = 0; - do { - err = rdqdm_man1(); - ddrphy_regif_idle(); - } while (err && (++retry_cnt < retry_max)); - ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, - ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_PHY_DQ_TSEL_ENABLE)); - ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, - ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_PHY_DQS_TSEL_ENABLE)); - ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, - ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_PHY_DQ_TSEL_SELECT)); - ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, - ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, - _reg_PHY_DQS_TSEL_SELECT)); - - return (retry_cnt >= retry_max); -} - -/* rx offset calibration */ -static int32_t _find_change(uint64_t val, uint32_t dir) -{ - int32_t i; - uint32_t startval; - uint32_t curval; - const int32_t VAL_END = 0x3f; - - if (dir == 0) { - startval = (val & 0x01); - for (i = 1; i <= VAL_END; i++) { - curval = (val >> i) & 0x01; - if (curval != startval) - return i; - } - return VAL_END; - } - - startval = (val >> dir) & 0x01; - for (i = dir - 1; i >= 0; i--) { - curval = (val >> i) & 0x01; - if (curval != startval) - return i; - } - return 0; -} - -static uint32_t _rx_offset_cal_updn(uint32_t code) -{ - const uint32_t CODE_MAX = 0x40; - uint32_t tmp; - - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - if (code == 0) - tmp = (1U << 6) | (CODE_MAX - 1); - else if (code <= 0x20) - tmp = - ((CODE_MAX - 1 - - (0x20 - code) * 2) << 6) | (CODE_MAX - 1); - else - tmp = - ((CODE_MAX - 1) << 6) | (CODE_MAX - 1 - - (code - 0x20) * 2); - } else { - if (code == 0) - tmp = (1U << 6) | (CODE_MAX - 1); - else - tmp = (code << 6) | (CODE_MAX - code); - } - return tmp; -} - -static uint32_t rx_offset_cal(void) -{ - uint32_t index; - uint32_t code; - const uint32_t CODE_MAX = 0x40; - const uint32_t CODE_STEP = 2; - uint32_t ch, slice; - uint32_t tmp; - uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; - uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM]; - uint64_t tmpval; - int32_t lsb, msb; - - ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01); - foreach_vch(ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) - val[ch][slice][index] = 0; - } - } - - for (code = 0; code < CODE_MAX / CODE_STEP; code++) { - tmp = _rx_offset_cal_updn(code * CODE_STEP); - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { - ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp); - } - dsb_sev(); - ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as); - - foreach_vch(ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - tmp = tmp_ach_as[ch][slice]; - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; - index++) { - if (tmp & (1U << index)) { - val[ch][slice][index] |= - (1ULL << code); - } else { - val[ch][slice][index] &= - ~(1ULL << code); - } - } - } - } - } - foreach_vch(ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; - index++) { - tmpval = val[ch][slice][index]; - lsb = _find_change(tmpval, 0); - msb = - _find_change(tmpval, - (CODE_MAX / CODE_STEP) - 1); - tmp = (lsb + msb) >> 1; - - tmp = _rx_offset_cal_updn(tmp * CODE_STEP); - ddr_setval_s(ch, slice, - _reg_PHY_RX_CAL_X[index], tmp); - } - } - } - ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); - - return 0; -} - -static uint32_t rx_offset_cal_hw(void) -{ - uint32_t ch, slice; - uint32_t retry; - uint32_t complete; - uint32_t tmp; - uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; - - ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00); - ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); - ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f); - - retry = 0; - while (retry < 4096) { - if ((retry & 0xff) == 0) { - ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); - } - foreach_vch(ch) - for (slice = 0; slice < SLICE_CNT; slice++) - tmp_ach_as[ch][slice] = - ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]); - - complete = 1; - foreach_vch(ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - tmp = tmp_ach_as[ch][slice]; - tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); - if (((prr_product == PRR_PRODUCT_H3) && - (prr_cut > PRR_PRODUCT_11)) || - (prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - if (tmp != 0x3E) - complete = 0; - } else { - if (tmp != 0x40) - complete = 0; - } - } - } - if (complete) - break; - - retry++; - } - - return (complete == 0); -} - -/* adjust rddqs latency */ -static void adjust_rddqs_latency(void) -{ - uint32_t ch, slice; - uint32_t dly; - uint32_t maxlatx2; - uint32_t tmp; - uint32_t rdlat_adjx2[SLICE_CNT]; - - foreach_vch(ch) { - maxlatx2 = 0; - for (slice = 0; slice < SLICE_CNT; slice++) { - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, - 0x00); - - dly = - ddr_getval_s(ch, slice, - _reg_PHY_RDDQS_GATE_SLAVE_DELAY); - tmp = - ddr_getval_s(ch, slice, - _reg_PHY_RDDQS_LATENCY_ADJUST); - /* note gate_slave_delay[9] is always 0 */ - tmp = (tmp << 1) + (dly >> 8); - rdlat_adjx2[slice] = tmp; - if (maxlatx2 < tmp) - maxlatx2 = tmp; - } - maxlatx2 = ((maxlatx2 + 1) >> 1) << 1; - for (slice = 0; slice < SLICE_CNT; slice++) { - tmp = maxlatx2 - rdlat_adjx2[slice]; - tmp = (tmp >> 1); - if (tmp) { - ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE, - ddr_getval_s(ch, slice, - _reg_PHY_RPTR_UPDATE) - + 1); - } - } - } -} - -/* adjust wpath latency */ -static void adjust_wpath_latency(void) -{ - uint32_t ch, cs, slice; - uint32_t dly; - uint32_t wpath_add; - const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180; - - foreach_vch(ch) { - for (slice = 0; slice < SLICE_CNT; slice += 1) { - for (cs = 0; cs < CS_CNT; cs++) { - ddr_setval_s(ch, slice, - _reg_PHY_PER_CS_TRAINING_INDEX, - cs); - ddr_getval_s(ch, slice, - _reg_PHY_PER_CS_TRAINING_INDEX); - dly = - ddr_getval_s(ch, slice, - _reg_PHY_CLK_WRDQS_SLAVE_DELAY); - if (dly <= _par_EARLY_THRESHOLD_VAL) - continue; - - wpath_add = - ddr_getval_s(ch, slice, - _reg_PHY_WRITE_PATH_LAT_ADD); - ddr_setval_s(ch, slice, - _reg_PHY_WRITE_PATH_LAT_ADD, - wpath_add - 1); - } - } - } -} - -/* DDR Initialize entry */ -int32_t rcar_dram_init(void) -{ - uint32_t ch, cs; - uint32_t data_l; - uint32_t bus_mbps, bus_mbpsdiv; - uint32_t tmp_tccd; - uint32_t failcount; - uint32_t cnf_boardtype; - - /* Thermal sensor setting */ - data_l = mmio_read_32(CPG_MSTPSR5); - if (data_l & BIT(22)) { /* case THS/TSC Standby */ - data_l &= ~BIT(22); - cpg_write_32(CPG_SMSTPCR5, data_l); - while (mmio_read_32(CPG_MSTPSR5) & BIT(22)) - ; /* wait bit=0 */ - } - - /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ - data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; - mmio_write_32(THS1_THCTR, data_l); - - /* Judge product and cut */ -#ifdef RCAR_DDR_FIXED_LSI_TYPE -#if (RCAR_LSI == RCAR_AUTO) - prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; - prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; -#else /* RCAR_LSI */ -#ifndef RCAR_LSI_CUT - prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; -#endif /* RCAR_LSI_CUT */ -#endif /* RCAR_LSI */ -#else /* RCAR_DDR_FIXED_LSI_TYPE */ - prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; - prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; -#endif /* RCAR_DDR_FIXED_LSI_TYPE */ - - if (prr_product == PRR_PRODUCT_H3) { - if (prr_cut <= PRR_PRODUCT_11) { - p_ddr_regdef_tbl = - (const uint32_t *)&DDR_REGDEF_TBL[0][0]; - } else { - p_ddr_regdef_tbl = - (const uint32_t *)&DDR_REGDEF_TBL[2][0]; - } - } else if (prr_product == PRR_PRODUCT_M3) { - p_ddr_regdef_tbl = - (const uint32_t *)&DDR_REGDEF_TBL[1][0]; - } else if ((prr_product == PRR_PRODUCT_M3N) || - (prr_product == PRR_PRODUCT_V3H)) { - p_ddr_regdef_tbl = - (const uint32_t *)&DDR_REGDEF_TBL[3][0]; - } else { - FATAL_MSG("BL2: DDR:Unknown Product\n"); - return 0xff; - } - - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || - ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { - /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ - } else { - mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); - } - - /* Judge board type */ - cnf_boardtype = boardcnf_get_brd_type(); - if (cnf_boardtype >= BOARDNUM) { - FATAL_MSG("BL2: DDR:Unknown Board\n"); - return 0xff; - } - board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype]; - -/* RCAR_DRAM_SPLIT_2CH (2U) */ -#if RCAR_DRAM_SPLIT == 2 - /* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */ - if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) { - mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); - ddr_phyvalid = 0x03; - } else { - ddr_phyvalid = board_cnf->phyvalid; - } -#else /* RCAR_DRAM_SPLIT_2CH */ - ddr_phyvalid = board_cnf->phyvalid; -#endif /* RCAR_DRAM_SPLIT_2CH */ - - max_density = 0; - - for (cs = 0; cs < CS_CNT; cs++) { - ch_have_this_cs[cs] = 0; - } - - foreach_ech(ch) - for (cs = 0; cs < CS_CNT; cs++) - ddr_density[ch][cs] = 0xff; - - foreach_vch(ch) { - for (cs = 0; cs < CS_CNT; cs++) { - data_l = board_cnf->ch[ch].ddr_density[cs]; - ddr_density[ch][cs] = data_l; - - if (data_l == 0xff) - continue; - if (data_l > max_density) - max_density = data_l; - if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) - continue; - ch_have_this_cs[cs] |= (1U << ch); - } - } - - /* Judge board clock frequency (in MHz) */ - boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv); - if ((brd_clk / brd_clkdiv) > 25) { - brd_clkdiva = 1; - } else { - brd_clkdiva = 0; - } - - /* Judge ddr operating frequency clock(in Mbps) */ - boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv); - - ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); - - ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, - brd_clkdiv * (brd_clkdiva + 1)); - - /* Adjust tccd */ - data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; - bus_mbps = 0; - bus_mbpsdiv = 0; - switch (data_l) { - case 0: - bus_mbps = brd_clk * 0x60 * 2; - bus_mbpsdiv = brd_clkdiv * 1; - break; - case 1: - bus_mbps = brd_clk * 0x50 * 2; - bus_mbpsdiv = brd_clkdiv * 1; - break; - case 2: - bus_mbps = brd_clk * 0x40 * 2; - bus_mbpsdiv = brd_clkdiv * 1; - break; - case 3: - bus_mbps = brd_clk * 0x60 * 2; - bus_mbpsdiv = brd_clkdiv * 2; - break; - default: - bus_mbps = brd_clk * 0x60 * 2; - bus_mbpsdiv = brd_clkdiv * 2; - break; - } - tmp_tccd = CLK_DIV(ddr_mbps * 8, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv); - if (8 * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) - tmp_tccd = tmp_tccd + 1; - - if (tmp_tccd < 8) - ddr_tccd = 8; - else - ddr_tccd = tmp_tccd; - - NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); - - MSG_LF("Start\n"); - - /* PLL Setting */ - pll3_control(1); - - /* initialize DDR */ - data_l = init_ddr(); - if (data_l == ddr_phyvalid) { - failcount = 0; - } else { - failcount = 1; - } - - foreach_vch(ch) - mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || - ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { - /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ - } else { - mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); - } - - if (failcount == 0) { - return INITDRAM_OK; - } else { - return INITDRAM_NG; - } -} - -void pvtcode_update(void) -{ - uint32_t ch; - uint32_t data_l; - uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init; - int32_t pvtp_tmp, pvtn_tmp; - - foreach_vch(ch) { - pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6; - pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0; - - if (8912 * pvtp_init > 44230) { - pvtp_tmp = (5000 + 8912 * pvtp_init - 44230) / 10000; - } else { - pvtp_tmp = - -((-(5000 + 8912 * pvtp_init - 44230)) / 10000); - } - pvtn_tmp = (5000 + 5776 * pvtn_init + 30280) / 10000; - - pvtn[ch] = pvtn_tmp + pvtn_init; - pvtp[ch] = pvtp_tmp + pvtp_init; - - if (pvtn[ch] > 63) { - pvtn[ch] = 63; - pvtp[ch] = - (pvtp_tmp) * (63 - 6 * pvtn_tmp - - pvtn_init) / (pvtn_tmp) + - 6 * pvtp_tmp + pvtp_init; - } - if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) { - data_l = pvtp[ch] | (pvtn[ch] << 6) | - (tcal.tcomp_cal[ch] & 0xfffff000); - reg_ddrphy_write(ch, - ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), - data_l | 0x00020000); - reg_ddrphy_write(ch, - ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), - data_l); - reg_ddrphy_write(ch, - ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), - data_l); - reg_ddrphy_write(ch, - ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), - data_l); - reg_ddrphy_write(ch, - ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), - data_l); - } else { - data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000; - reg_ddrphy_write(ch, - ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), - data_l | 0x00020000); - reg_ddrphy_write(ch, - ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), - data_l); - reg_ddrphy_write(ch, - ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), - data_l); - reg_ddrphy_write(ch, - ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), - data_l); - reg_ddrphy_write(ch, - ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), - data_l); - } - } -} - -void pvtcode_update2(void) -{ - uint32_t ch; - - foreach_vch(ch) { - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), - tcal.init_cal[ch] | 0x00020000); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), - tcal.init_cal[ch]); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), - tcal.init_cal[ch]); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), - tcal.init_cal[ch]); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), - tcal.init_cal[ch]); - } -} - -void ddr_padcal_tcompensate_getinit(uint32_t override) -{ - uint32_t ch; - uint32_t data_l; - uint32_t pvtp, pvtn; - - tcal.init_temp = 0; - for (ch = 0; ch < 4; ch++) { - tcal.init_cal[ch] = 0; - tcal.tcomp_cal[ch] = 0; - } - - foreach_vch(ch) { - tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); - tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); - } - - if (!override) { - data_l = mmio_read_32(THS1_TEMP); - if (data_l < 2800) { - tcal.init_temp = - (143 * (int32_t)data_l - 359000) / 1000; - } else { - tcal.init_temp = - (121 * (int32_t)data_l - 296300) / 1000; - } - - foreach_vch(ch) { - pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F; - pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F; - if ((int32_t)pvtp > - ((tcal.init_temp * 29 - 3625) / 1000)) - pvtp = - (int32_t)pvtp + - ((3625 - tcal.init_temp * 29) / 1000); - else - pvtp = 0; - - if ((int32_t)pvtn > - ((tcal.init_temp * 54 - 6750) / 1000)) - pvtn = - (int32_t)pvtn + - ((6750 - tcal.init_temp * 54) / 1000); - else - pvtn = 0; - - if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) { - tcal.init_cal[ch] = - (tcal.init_cal[ch] & 0xfffff000) | - (pvtn << 6) | - pvtp; - } else { - tcal.init_cal[ch] = - 0x00015000 | (pvtn << 6) | pvtp; - } - } - tcal.init_temp = 125; - } -} - -#ifndef ddr_qos_init_setting -/* For QoS init */ -uint8_t get_boardcnf_phyvalid(void) -{ - return ddr_phyvalid; -} -#endif /* ddr_qos_init_setting */ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c deleted file mode 100644 index f8caade27..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ /dev/null @@ -1,1794 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define BOARDNUM 22 -#define BOARD_JUDGE_AUTO - -#ifdef BOARD_JUDGE_AUTO -static uint32_t _board_judge(void); - -static uint32_t boardcnf_get_brd_type(void) -{ - return _board_judge(); -} -#else -static uint32_t boardcnf_get_brd_type(void) -{ - return 1; -} -#endif - -#define DDR_FAST_INIT - -struct _boardcnf_ch { - uint8_t ddr_density[CS_CNT]; - uint64_t ca_swap; - uint16_t dqs_swap; - uint32_t dq_swap[SLICE_CNT]; - uint8_t dm_swap[SLICE_CNT]; - uint16_t wdqlvl_patt[16]; - int8_t cacs_adj[16]; - int8_t dm_adj_w[SLICE_CNT]; - int8_t dq_adj_w[SLICE_CNT * 8]; - int8_t dm_adj_r[SLICE_CNT]; - int8_t dq_adj_r[SLICE_CNT * 8]; -}; - -struct _boardcnf { - uint8_t phyvalid; - uint8_t dbi_en; - uint16_t cacs_dly; - int16_t cacs_dly_adj; - uint16_t dqdm_dly_w; - uint16_t dqdm_dly_r; - struct _boardcnf_ch ch[DRAM_CH_CNT]; -}; - -#define WDQLVL_PAT {\ - 0x00AA,\ - 0x0055,\ - 0x00AA,\ - 0x0155,\ - 0x01CC,\ - 0x0133,\ - 0x00CC,\ - 0x0033,\ - 0x00F0,\ - 0x010F,\ - 0x01F0,\ - 0x010F,\ - 0x00F0,\ - 0x00F0,\ - 0x000F,\ - 0x010F} - -static const struct _boardcnf boardcnfs[BOARDNUM] = { - { -/* boardcnf[0] RENESAS SALVATOR-X board with M3-W/SIP */ - .phyvalid = 0x03, - .dbi_en = 0x01, - .cacs_dly = 0x02c0, - .cacs_dly_adj = 0, - .dqdm_dly_w = 0x0300, - .dqdm_dly_r = 0x00a0, - .ch = { - { - {0x02, 0x02}, - 0x00543210U, - 0x3201U, - {0x70612543, 0x43251670, 0x45326170, 0x10672534}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - - { - {0x02, 0x02}, - 0x00543210, - 0x2310, - {0x01327654, 0x34526107, 0x35421670, 0x70615324}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[1] RENESAS KRIEK board with M3-W/SoC */ - { - 0x03, - 0x01, - 0x2c0, - 0, - 0x300, - 0x0a0, - { - { - {0x02, 0x02}, - 0x00345201, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0x02}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[2] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 1rank) */ - { - 0x0f, - 0x00, - 0x300, - -320, - 0x300, - 0x0a0, - { - { - {0x02, 0xff}, - 0x00543210, - 0x3210, - {0x20741365, 0x34256107, 0x57460321, 0x70614532}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00543210, - 0x3102, - {0x23547610, 0x34526107, 0x67452310, 0x32106754}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00543210, - 0x0213, - {0x30216754, 0x67453210, 0x70165243, 0x07162345}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00543210, - 0x0213, - {0x01327654, 0x70615432, 0x54760123, 0x07162345}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[3] RENESAS Starter Kit board with M3-W/SIP(8Gbit 1rank) */ - { - 0x03, - 0x01, - 0x02c0, - 0, - 0x0300, - 0x00a0, - { - { - {0x02, 0xFF}, - 0x00543210U, - 0x3201, - {0x70612543, 0x43251670, 0x45326170, 0x10672534}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xFF}, - 0x00543210, - 0x2310, - {0x01327654, 0x34526107, 0x35421670, 0x70615324}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[4] RENESAS SALVATOR-M(1rank) board with H3 Ver.1.x/SoC */ - { - 0x0f, - 0x00, - 0x2c0, - -320, - 0x300, - 0x0a0, - { - { - {0x02, 0xff}, - 0x00315024, - 0x3120, - {0x30671254, 0x26541037, 0x17054623, 0x12307645}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00025143, - 0x3210, - {0x70613542, 0x16245307, 0x30712645, 0x21706354}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00523104, - 0x2301, - {0x70613542, 0x16245307, 0x30712645, 0x21706354}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00153402, - 0x2031, - {0x30671254, 0x26541037, 0x17054623, 0x12307645}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[5] RENESAS KRIEK-1rank board with M3-W/SoC */ - { - 0x03, - 0x01, - 0x2c0, - 0, - 0x300, - 0x0a0, - { - { - {0x02, 0xff}, - 0x00345201, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[6] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 2rank) */ - { - 0x0f, - 0x00, - 0x300, - -320, - 0x300, - 0x0a0, - { - { - {0x02, 0x02}, - 0x00543210, - 0x3210, - {0x20741365, 0x34256107, 0x57460321, 0x70614532}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0x02}, - 0x00543210, - 0x3102, - {0x23547610, 0x34526107, 0x67452310, 0x32106754}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0x02}, - 0x00543210, - 0x0213, - {0x30216754, 0x67453210, 0x70165243, 0x07162345}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0x02}, - 0x00543210, - 0x0213, - {0x01327654, 0x70615432, 0x54760123, 0x07162345}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* - * boardcnf[7] RENESAS SALVATOR-X board with - * H3 Ver.2.0 or later/SIP(8Gbit 1rank) - */ - { - 0x0f, - 0x01, - 0x300, - 0, - 0x300, - 0x0a0, - { - { - {0x02, 0xff}, - 0x00543210, - 0x2310, - {0x70631425, 0x34527016, 0x43527610, 0x32104567}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00105432, - 0x3210, - {0x43256107, 0x07162354, 0x10234567, 0x01235467}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00543210, - 0x2301, - {0x01327654, 0x02316457, 0x10234567, 0x01325467}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00543210, - 0x2301, - {0x12034765, 0x23105467, 0x23017645, 0x32106745}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* - * boardcnf[8] RENESAS SALVATOR-X board with - * H3 Ver.2.0 or later/SIP(8Gbit 2rank) - */ - { -#if RCAR_DRAM_CHANNEL == 5 - 0x05, -#else - 0x0f, -#endif - 0x01, - 0x300, - 0, - 0x300, - 0x0a0, - { - { - {0x02, 0x02}, - 0x00543210, - 0x2310, - {0x70631425, 0x34527016, 0x43527610, 0x32104567}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, -#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2)) - { - {0x02, 0x02}, - 0x00543210, - 0x2301, - {0x01327654, 0x02316457, 0x10234567, 0x01325467}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, -#else - { - {0x02, 0x02}, - 0x00105432, - 0x3210, - {0x43256107, 0x07162354, 0x10234567, 0x01235467}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, -#endif - { - {0x02, 0x02}, - 0x00543210, - 0x2301, - {0x01327654, 0x02316457, 0x10234567, 0x01325467}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0x02}, - 0x00543210, - 0x2301, - {0x12034765, 0x23105467, 0x23017645, 0x32106745}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[9] RENESAS SALVATOR-MS(1rank) board with H3 Ver.2.0 or later/SoC */ - { - 0x0f, - 0x01, - 0x300, - 0, - 0x300, - 0x0a0, - { - { - {0x02, 0xff}, - 0x00543210, - 0x3210, - {0x27645310, 0x75346210, 0x53467210, 0x23674510}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00543210, - 0x2301, - {0x23764510, 0x43257610, 0x43752610, 0x37652401}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {-128, -128, -128, -128, -128, -128, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00452103, - 0x3210, - {0x32764510, 0x43257610, 0x43752610, 0x26573401}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0xff}, - 0x00520413, - 0x2301, - {0x47652301, 0x75346210, 0x53467210, 0x32674501}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {30, 30, 30, 30, 30, 30, 30, 30, - 30, 30}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[10] RENESAS Kriek(2rank) board with M3-N/SoC */ - { - 0x01, - 0x01, - 0x300, - 0, - 0x300, - 0x0a0, - { - { - {0x02, 0x02}, - 0x00345201, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[11] RENESAS SALVATOR-X board with M3-N/SIP(8Gbit 2rank) */ - { - 0x01, - 0x01, - 0x300, - 0, - 0x300, - 0x0a0, - { - { -#if (RCAR_DRAM_LPDDR4_MEMCONF == 2) - {0x04, 0x04}, -#else - {0x02, 0x02}, -#endif - 0x00342501, - 0x3201, - {0x10672534, 0x43257106, 0x34527601, 0x71605243}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[12] RENESAS CONDOR board with V3H/SoC */ - { - 0x01, - 0x1, - 0x300, - 0, - 0x300, - 0x0a0, - { - { - {0x02, 0x02}, - 0x00501342, - 0x3201, - {0x70562134, 0x34526071, 0x23147506, 0x12430567}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[13] RENESAS KRIEK board with PM3/SoC */ - { - 0x05, - 0x00, - 0x2c0, - -320, - 0x300, - 0x0a0, - { - { - {0x02, 0x02}, - 0x00345201, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0x02}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0x02}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0xff, 0xff}, - 0, - 0, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[14] SALVATOR-X board with H3 Ver.2.0 or later/SIP(16Gbit 1rank) */ - { -#if RCAR_DRAM_CHANNEL == 5 - 0x05, -#else - 0x0f, -#endif - 0x01, - 0x300, - 0, - 0x300, - 0x0a0, - { - { - {0x04, 0xff}, - 0x00543210, - 0x2310, - {0x70631425, 0x34527016, 0x43527610, 0x32104567}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, -#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2)) - { - {0x04, 0xff}, - 0x00543210, - 0x2301, - {0x01327654, 0x02316457, 0x10234567, 0x01325467}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, -#else - { - {0x04, 0xff}, - 0x00105432, - 0x3210, - {0x43256107, 0x07162354, 0x10234567, 0x01235467}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, -#endif - { - {0x04, 0xff}, - 0x00543210, - 0x2301, - {0x01327654, 0x02316457, 0x10234567, 0x01325467}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x04, 0xff}, - 0x00543210, - 0x2301, - {0x12034765, 0x23105467, 0x23017645, 0x32106745}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[15] RENESAS KRIEK board with H3N */ - { - 0x05, - 0x01, - 0x300, - 0, - 0x300, - 0x0a0, - { - { - {0x02, 0x02}, - 0x00345201, - 0x3201, - {0x01672543, 0x45367012, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0x02}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x02, 0x02}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0xff, 0xff}, - 0, - 0, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */ - { - 0x03, - 0x01, - 0x0320, - 0, - 0x0300, - 0x00a0, - { - { - {0x04, 0x04}, - 0x520314FFFF523041, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x04, 0x04}, - 0x314250FFFF312405, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */ - { - 0x01, - 0x01, - 0x0300, - 0, - 0x0300, - 0x00a0, - { - { - {0x04, 0x04}, - 0x520314FFFF523041, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) */ - { - 0x03, - 0x01, - 0x02c0, - 0, - 0x0300, - 0x00a0, - { - { - {0x04, 0x04}, - 0x00543210, - 0x3201, - {0x70612543, 0x43251670, 0x45326170, 0x10672534}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x04, 0x04}, - 0x00543210, - 0x2310, - {0x01327654, 0x34526107, 0x35421670, 0x70615324}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */ - { - 0x03, - 0x01, - 0x02c0, - 0, - 0x0300, - 0x00a0, - { - { - {0x04, 0xff}, - 0x00543210, - 0x3201, - {0x70612543, 0x43251670, 0x45326170, 0x10672534}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x04, 0xff}, - 0x00543210, - 0x2310, - {0x01327654, 0x34526107, 0x35421670, 0x70615324}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */ - { - 0x03, - 0x01, - 0x02c0, - 0, - 0x0300, - 0x00a0, - { - { - {0x04, 0x04}, - 0x00345201, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x04, 0x04}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, -/* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */ - { - 0x03, - 0x01, - 0x02c0, - 0, - 0x0300, - 0x00a0, - { - { - {0x04, 0xff}, - 0x00345201, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x04, 0xff}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - } -}; - -void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) -{ - uint32_t md; - - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_10)) { - *clk = 50; - *div = 3; - } else { - md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3; - switch (md) { - case 0x0: - *clk = 50; - *div = 3; - break; - case 0x1: - *clk = 60; - *div = 3; - break; - case 0x2: - *clk = 75; - *div = 3; - break; - case 0x3: - *clk = 100; - *div = 3; - break; - } - } - (void)brd; -} - -void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) -{ - uint32_t md; - - md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5; - md = (md | (md >> 1)) & 0x3; - switch (md) { - case 0x0: - *mbps = 3200; - *div = 1; - break; - case 0x1: - *mbps = 2800; - *div = 1; - break; - case 0x2: - *mbps = 2400; - *div = 1; - break; - case 0x3: - *mbps = 1600; - *div = 1; - break; - } - (void)brd; -} - -#define _def_REFPERIOD 1890 - -#define M3_SAMPLE_TT_A84 0xB866CC10, 0x3B250421 -#define M3_SAMPLE_TT_A85 0xB866CC10, 0x3AA50421 -#define M3_SAMPLE_TT_A86 0xB866CC10, 0x3AA48421 -#define M3_SAMPLE_FF_B45 0xB866CC10, 0x3AB00C21 -#define M3_SAMPLE_FF_B49 0xB866CC10, 0x39B10C21 -#define M3_SAMPLE_FF_B56 0xB866CC10, 0x3AAF8C21 -#define M3_SAMPLE_SS_E24 0xB866CC10, 0x3BA39421 -#define M3_SAMPLE_SS_E28 0xB866CC10, 0x3C231421 -#define M3_SAMPLE_SS_E32 0xB866CC10, 0x3C241421 - -static const uint32_t termcode_by_sample[20][3] = { - {M3_SAMPLE_TT_A84, 0x000158D5}, - {M3_SAMPLE_TT_A85, 0x00015955}, - {M3_SAMPLE_TT_A86, 0x00015955}, - {M3_SAMPLE_FF_B45, 0x00015690}, - {M3_SAMPLE_FF_B49, 0x00015753}, - {M3_SAMPLE_FF_B56, 0x00015793}, - {M3_SAMPLE_SS_E24, 0x00015996}, - {M3_SAMPLE_SS_E28, 0x000159D7}, - {M3_SAMPLE_SS_E32, 0x00015997}, - {0xFFFFFFFF, 0xFFFFFFFF, 0x0001554F} -}; - -#ifdef BOARD_JUDGE_AUTO -/* - * SAMPLE board detect function - */ -#define PFC_PMMR 0xE6060000U -#define PFC_PUEN5 0xE6060414U -#define PFC_PUEN6 0xE6060418U -#define PFC_PUD5 0xE6060454U -#define PFC_PUD6 0xE6060458U -#define GPIO_INDT5 0xE605500CU -#define GPIO_GPSR6 0xE6060118U - -#if (RCAR_GEN3_ULCB == 0) -static void pfc_write_and_poll(uint32_t a, uint32_t v) -{ - mmio_write_32(PFC_PMMR, ~v); - v = ~mmio_read_32(PFC_PMMR); - mmio_write_32(a, v); - while (v != mmio_read_32(a)) - ; - dsb_sev(); -} -#endif - -#ifndef RCAR_GEN3_ULCB -#define RCAR_GEN3_ULCB 0 -#endif - -#if (RCAR_GEN3_ULCB == 0) /* non Starter Kit */ - -static uint32_t opencheck_SSI_WS6(void) -{ - uint32_t dataL, down, up; - uint32_t gpsr6_bak; - uint32_t puen5_bak; - uint32_t pud5_bak; - - gpsr6_bak = mmio_read_32(GPIO_GPSR6); - puen5_bak = mmio_read_32(PFC_PUEN5); - pud5_bak = mmio_read_32(PFC_PUD5); - dsb_sev(); - - dataL = (gpsr6_bak & ~BIT(15)); - pfc_write_and_poll(GPIO_GPSR6, dataL); - - /* Pull-Up/Down Enable (PUEN5[22]=1) */ - dataL = puen5_bak; - dataL |= (BIT(22)); - pfc_write_and_poll(PFC_PUEN5, dataL); - - /* Pull-Down-Enable (PUD5[22]=0, PUEN5[22]=1) */ - dataL = pud5_bak; - dataL &= ~(BIT(22)); - pfc_write_and_poll(PFC_PUD5, dataL); - /* GPSR6[15]=SSI_WS6 */ - rcar_micro_delay(10); - down = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1; - dsb_sev(); - - /* Pull-Up-Enable (PUD5[22]=1, PUEN5[22]=1) */ - dataL = pud5_bak; - dataL |= (BIT(22)); - pfc_write_and_poll(PFC_PUD5, dataL); - - /* GPSR6[15]=SSI_WS6 */ - rcar_micro_delay(10); - up = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1; - - dsb_sev(); - - pfc_write_and_poll(GPIO_GPSR6, gpsr6_bak); - pfc_write_and_poll(PFC_PUEN5, puen5_bak); - pfc_write_and_poll(PFC_PUD5, pud5_bak); - - if (down == up) { - /* Same = Connect */ - return 0; - } - - /* Diff = Open */ - return 1; -} - -#endif - -static uint32_t _board_judge(void) -{ - uint32_t brd; -#if (RCAR_GEN3_ULCB == 1) - /* Starter Kit */ - if (prr_product == PRR_PRODUCT_H3) { - if (prr_cut <= PRR_PRODUCT_11) { - /* RENESAS Starter Kit(H3 Ver.1.x/SIP) board */ - brd = 2; - } else { - /* RENESAS Starter Kit(H3 Ver.2.0 or later/SIP) board */ -#if (RCAR_DRAM_LPDDR4_MEMCONF == 0) - brd = 7; -#else - brd = 8; -#endif - } - } else if (prr_product == PRR_PRODUCT_M3) { - /* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */ - brd = 3; - } else { - /* RENESAS Starter Kit(M3-N/SIP) board */ - brd = 11; - } -#else - uint32_t usb2_ovc_open; - - usb2_ovc_open = opencheck_SSI_WS6(); - - /* RENESAS Eva-board */ - brd = 99; - if (prr_product == PRR_PRODUCT_V3H) { - /* RENESAS Condor board */ - brd = 12; - } else if (usb2_ovc_open) { - if (prr_product == PRR_PRODUCT_M3N) { - /* RENESAS Kriek board with M3-N */ - brd = 10; - } else if (prr_product == PRR_PRODUCT_M3) { - /* RENESAS Kriek board with M3-W */ - brd = 1; - } else if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut <= PRR_PRODUCT_11)) { - /* RENESAS Kriek board with PM3 */ - brd = 13; - } else if ((prr_product == PRR_PRODUCT_H3) && - (prr_cut > PRR_PRODUCT_20)) { - /* RENESAS Kriek board with H3N */ - brd = 15; - } - } else { - if (prr_product == PRR_PRODUCT_H3) { - if (prr_cut <= PRR_PRODUCT_11) { - /* RENESAS SALVATOR-X (H3 Ver.1.x/SIP) */ - brd = 2; - } else if (prr_cut < PRR_PRODUCT_30) { - /* RENESAS SALVATOR-X (H3 Ver.2.0/SIP) */ - brd = 7; // 8Gbit/1rank - } else { - /* RENESAS SALVATOR-X (H3 Ver.3.0/SIP) */ -#if (RCAR_DRAM_LPDDR4_MEMCONF == 0) - brd = 7; -#else - brd = 8; -#endif - } - } else if (prr_product == PRR_PRODUCT_M3N) { - /* RENESAS SALVATOR-X (M3-N/SIP) */ - brd = 11; - } else if ((prr_product == PRR_PRODUCT_M3) && - (prr_cut <= PRR_PRODUCT_20)) { - /* RENESAS SALVATOR-X (M3-W/SIP) */ - brd = 0; - } else if ((prr_product == PRR_PRODUCT_M3) && - (prr_cut < PRR_PRODUCT_30)) { - /* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */ - brd = 19; - } else if ((prr_product == PRR_PRODUCT_M3) && - (prr_cut >= PRR_PRODUCT_30)) { - /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */ - brd = 18; - } - } -#endif - - return brd; -} -#endif diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h deleted file mode 100644 index 5047e5cc2..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define RCAR_DDR_VERSION "rev.0.37" -#define DRAM_CH_CNT 0x04 -#define SLICE_CNT 0x04 -#define CS_CNT 0x02 - -/* order : CS0A, CS0B, CS1A, CS1B */ -#define CSAB_CNT (CS_CNT * 2) - -/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */ -#define CHAB_CNT (DRAM_CH_CNT * 2) - -/* pll setting */ -#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) -#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) - -/* for ddr deisity setting */ -#define DBMEMCONF_REG(d3, row, bank, col, dw) \ - ((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw)) - -#define DBMEMCONF_REGD(density) \ - (DBMEMCONF_REG((density) % 2, ((density) + 1) / \ - 2 + (29 - 3 - 10 - 2), 3, 10, 2)) - -#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) - -/* refresh mode */ -#define DBSC_REFINTS (0x0) - -/* system registers */ -#define CPG_FRQCRB (CPG_BASE + 0x0004U) - -#define CPG_PLLECR (CPG_BASE + 0x00D0U) -#define CPG_MSTPSR5 (CPG_BASE + 0x003CU) -#define CPG_SRCR4 (CPG_BASE + 0x00BCU) -#define CPG_PLL3CR (CPG_BASE + 0x00DCU) -#define CPG_ZB3CKCR (CPG_BASE + 0x0380U) -#define CPG_FRQCRD (CPG_BASE + 0x00E4U) -#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) -#define CPG_CPGWPR (CPG_BASE + 0x0900U) -#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U) - -#define CPG_FRQCRB_KICK_BIT BIT(31) -#define CPG_PLLECR_PLL3E_BIT BIT(3) -#define CPG_PLLECR_PLL3ST_BIT BIT(11) -#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11) - -#define RST_BASE (0xE6160000U) -#define RST_MODEMR (RST_BASE + 0x0060U) - -#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x)) - -/* DBSC registers */ -#include "../ddr_regs.h" - -#define DBSC_DBMONCONF4 0xE6793010U - -#define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch)) -#define DBSC_PLL_LOCK_0 0xE6794054U -#define DBSC_PLL_LOCK_1 0xE6794154U -#define DBSC_PLL_LOCK_2 0xE6794254U -#define DBSC_PLL_LOCK_3 0xE6794354U - -/* STAT registers */ -#define MSTAT_SL_INIT 0xE67E8000U -#define MSTAT_REF_ARS 0xE67E8004U -#define MSTATQ_STATQC 0xE67E8008U -#define MSTATQ_WTENABLE 0xE67E8030U -#define MSTATQ_WTREFRESH 0xE67E8034U -#define MSTATQ_WTSETTING0 0xE67E8038U -#define MSTATQ_WTSETTING1 0xE67E803CU - -#define QOS_BASE1 (0xE67F0000U) -#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U) -#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U) -#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U) -#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U) -#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U) -#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U) -#define QOSCTRL_EC (QOS_BASE1 + 0x003CU) -#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U) -#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U) -#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U) -#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U) -#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U) - -/* other module */ -#define THS1_THCTR 0xE6198020U -#define THS1_TEMP 0xE6198028U diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk deleted file mode 100644 index 875f95339..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h deleted file mode 100644 index adf8dab18..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h +++ /dev/null @@ -1,5887 +0,0 @@ -/* - * Copyright (c) 2018-2019, Renesas Electronics Corporation. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define _reg_PHY_DQ_DM_SWIZZLE0 0x00000000U -#define _reg_PHY_DQ_DM_SWIZZLE1 0x00000001U -#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY 0x00000002U -#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY 0x00000003U -#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE 0x00000004U -#define _reg_PHY_CLK_BYPASS_OVERRIDE 0x00000005U -#define _reg_PHY_SW_WRDQ0_SHIFT 0x00000006U -#define _reg_PHY_SW_WRDQ1_SHIFT 0x00000007U -#define _reg_PHY_SW_WRDQ2_SHIFT 0x00000008U -#define _reg_PHY_SW_WRDQ3_SHIFT 0x00000009U -#define _reg_PHY_SW_WRDQ4_SHIFT 0x0000000aU -#define _reg_PHY_SW_WRDQ5_SHIFT 0x0000000bU -#define _reg_PHY_SW_WRDQ6_SHIFT 0x0000000cU -#define _reg_PHY_SW_WRDQ7_SHIFT 0x0000000dU -#define _reg_PHY_SW_WRDM_SHIFT 0x0000000eU -#define _reg_PHY_SW_WRDQS_SHIFT 0x0000000fU -#define _reg_PHY_DQ_TSEL_ENABLE 0x00000010U -#define _reg_PHY_DQ_TSEL_SELECT 0x00000011U -#define _reg_PHY_DQS_TSEL_ENABLE 0x00000012U -#define _reg_PHY_DQS_TSEL_SELECT 0x00000013U -#define _reg_PHY_TWO_CYC_PREAMBLE 0x00000014U -#define _reg_PHY_DBI_MODE 0x00000015U -#define _reg_PHY_PER_RANK_CS_MAP 0x00000016U -#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN 0x00000017U -#define _reg_PHY_PER_CS_TRAINING_INDEX 0x00000018U -#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY 0x00000019U -#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY 0x0000001aU -#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY 0x0000001bU -#define _reg_PHY_LP4_BOOT_RPTR_UPDATE 0x0000001cU -#define _reg_PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY 0x0000001dU -#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST 0x0000001eU -#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE 0x0000001fU -#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY 0x00000020U -#define _reg_PHY_LPBK_CONTROL 0x00000021U -#define _reg_PHY_LPBK_DFX_TIMEOUT_EN 0x00000022U -#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL 0x00000023U -#define _reg_PHY_AUTO_TIMING_MARGIN_OBS 0x00000024U -#define _reg_PHY_SLICE_PWR_RDC_DISABLE 0x00000025U -#define _reg_PHY_PRBS_PATTERN_START 0x00000026U -#define _reg_PHY_PRBS_PATTERN_MASK 0x00000027U -#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY 0x00000028U -#define _reg_PHY_GATE_ERROR_DELAY_SELECT 0x00000029U -#define _reg_SC_PHY_SNAP_OBS_REGS 0x0000002aU -#define _reg_PHY_LPDDR 0x0000002bU -#define _reg_PHY_LPDDR_TYPE 0x0000002cU -#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY 0x0000002dU -#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY 0x0000002eU -#define _reg_ON_FLY_GATE_ADJUST_EN 0x0000002fU -#define _reg_PHY_GATE_TRACKING_OBS 0x00000030U -#define _reg_PHY_DFI40_POLARITY 0x00000031U -#define _reg_PHY_LP4_PST_AMBLE 0x00000032U -#define _reg_PHY_RDLVL_PATT8 0x00000033U -#define _reg_PHY_RDLVL_PATT9 0x00000034U -#define _reg_PHY_RDLVL_PATT10 0x00000035U -#define _reg_PHY_RDLVL_PATT11 0x00000036U -#define _reg_PHY_LP4_RDLVL_PATT8 0x00000037U -#define _reg_PHY_LP4_RDLVL_PATT9 0x00000038U -#define _reg_PHY_LP4_RDLVL_PATT10 0x00000039U -#define _reg_PHY_LP4_RDLVL_PATT11 0x0000003aU -#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE 0x0000003bU -#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE 0x0000003cU -#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT 0x0000003dU -#define _reg_PHY_RDDQ_ENC_OBS_SELECT 0x0000003eU -#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT 0x0000003fU -#define _reg_PHY_WR_ENC_OBS_SELECT 0x00000040U -#define _reg_PHY_WR_SHIFT_OBS_SELECT 0x00000041U -#define _reg_PHY_FIFO_PTR_OBS_SELECT 0x00000042U -#define _reg_PHY_LVL_DEBUG_MODE 0x00000043U -#define _reg_SC_PHY_LVL_DEBUG_CONT 0x00000044U -#define _reg_PHY_WRLVL_CAPTURE_CNT 0x00000045U -#define _reg_PHY_WRLVL_UPDT_WAIT_CNT 0x00000046U -#define _reg_PHY_WRLVL_DQ_MASK 0x00000047U -#define _reg_PHY_GTLVL_CAPTURE_CNT 0x00000048U -#define _reg_PHY_GTLVL_UPDT_WAIT_CNT 0x00000049U -#define _reg_PHY_RDLVL_CAPTURE_CNT 0x0000004aU -#define _reg_PHY_RDLVL_UPDT_WAIT_CNT 0x0000004bU -#define _reg_PHY_RDLVL_OP_MODE 0x0000004cU -#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x0000004dU -#define _reg_PHY_RDLVL_DATA_MASK 0x0000004eU -#define _reg_PHY_RDLVL_DATA_SWIZZLE 0x0000004fU -#define _reg_PHY_WDQLVL_BURST_CNT 0x00000050U -#define _reg_PHY_WDQLVL_PATT 0x00000051U -#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET 0x00000052U -#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT 0x00000053U -#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT 0x00000054U -#define _reg_PHY_WDQLVL_QTR_DLY_STEP 0x00000055U -#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000056U -#define _reg_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000057U -#define _reg_PHY_WDQLVL_DATADM_MASK 0x00000058U -#define _reg_PHY_USER_PATT0 0x00000059U -#define _reg_PHY_USER_PATT1 0x0000005aU -#define _reg_PHY_USER_PATT2 0x0000005bU -#define _reg_PHY_USER_PATT3 0x0000005cU -#define _reg_PHY_USER_PATT4 0x0000005dU -#define _reg_PHY_DQ_SWIZZLING 0x0000005eU -#define _reg_PHY_CALVL_VREF_DRIVING_SLICE 0x0000005fU -#define _reg_SC_PHY_MANUAL_CLEAR 0x00000060U -#define _reg_PHY_FIFO_PTR_OBS 0x00000061U -#define _reg_PHY_LPBK_RESULT_OBS 0x00000062U -#define _reg_PHY_LPBK_ERROR_COUNT_OBS 0x00000063U -#define _reg_PHY_MASTER_DLY_LOCK_OBS 0x00000064U -#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS 0x00000065U -#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS 0x00000066U -#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS 0x00000067U -#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS 0x00000068U -#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS 0x00000069U -#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS 0x0000006aU -#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS 0x0000006bU -#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS 0x0000006cU -#define _reg_PHY_WR_SHIFT_OBS 0x0000006dU -#define _reg_PHY_WRLVL_HARD0_DELAY_OBS 0x0000006eU -#define _reg_PHY_WRLVL_HARD1_DELAY_OBS 0x0000006fU -#define _reg_PHY_WRLVL_STATUS_OBS 0x00000070U -#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS 0x00000071U -#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS 0x00000072U -#define _reg_PHY_WRLVL_ERROR_OBS 0x00000073U -#define _reg_PHY_GTLVL_HARD0_DELAY_OBS 0x00000074U -#define _reg_PHY_GTLVL_HARD1_DELAY_OBS 0x00000075U -#define _reg_PHY_GTLVL_STATUS_OBS 0x00000076U -#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x00000077U -#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x00000078U -#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS 0x00000079U -#define _reg_PHY_RDLVL_STATUS_OBS 0x0000007aU -#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS 0x0000007bU -#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS 0x0000007cU -#define _reg_PHY_WDQLVL_STATUS_OBS 0x0000007dU -#define _reg_PHY_DDL_MODE 0x0000007eU -#define _reg_PHY_DDL_TEST_OBS 0x0000007fU -#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS 0x00000080U -#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD 0x00000081U -#define _reg_PHY_LP4_WDQS_OE_EXTEND 0x00000082U -#define _reg_SC_PHY_RX_CAL_START 0x00000083U -#define _reg_PHY_RX_CAL_OVERRIDE 0x00000084U -#define _reg_PHY_RX_CAL_SAMPLE_WAIT 0x00000085U -#define _reg_PHY_RX_CAL_DQ0 0x00000086U -#define _reg_PHY_RX_CAL_DQ1 0x00000087U -#define _reg_PHY_RX_CAL_DQ2 0x00000088U -#define _reg_PHY_RX_CAL_DQ3 0x00000089U -#define _reg_PHY_RX_CAL_DQ4 0x0000008aU -#define _reg_PHY_RX_CAL_DQ5 0x0000008bU -#define _reg_PHY_RX_CAL_DQ6 0x0000008cU -#define _reg_PHY_RX_CAL_DQ7 0x0000008dU -#define _reg_PHY_RX_CAL_DM 0x0000008eU -#define _reg_PHY_RX_CAL_DQS 0x0000008fU -#define _reg_PHY_RX_CAL_FDBK 0x00000090U -#define _reg_PHY_RX_CAL_OBS 0x00000091U -#define _reg_PHY_RX_CAL_LOCK_OBS 0x00000092U -#define _reg_PHY_RX_CAL_DISABLE 0x00000093U -#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY 0x00000094U -#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY 0x00000095U -#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY 0x00000096U -#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY 0x00000097U -#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY 0x00000098U -#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY 0x00000099U -#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY 0x0000009aU -#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY 0x0000009bU -#define _reg_PHY_CLK_WRDM_SLAVE_DELAY 0x0000009cU -#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY 0x0000009dU -#define _reg_PHY_WRLVL_THRESHOLD_ADJUST 0x0000009eU -#define _reg_PHY_RDDQ0_SLAVE_DELAY 0x0000009fU -#define _reg_PHY_RDDQ1_SLAVE_DELAY 0x000000a0U -#define _reg_PHY_RDDQ2_SLAVE_DELAY 0x000000a1U -#define _reg_PHY_RDDQ3_SLAVE_DELAY 0x000000a2U -#define _reg_PHY_RDDQ4_SLAVE_DELAY 0x000000a3U -#define _reg_PHY_RDDQ5_SLAVE_DELAY 0x000000a4U -#define _reg_PHY_RDDQ6_SLAVE_DELAY 0x000000a5U -#define _reg_PHY_RDDQ7_SLAVE_DELAY 0x000000a6U -#define _reg_PHY_RDDM_SLAVE_DELAY 0x000000a7U -#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY 0x000000a8U -#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY 0x000000a9U -#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY 0x000000aaU -#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY 0x000000abU -#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY 0x000000acU -#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY 0x000000adU -#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY 0x000000aeU -#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY 0x000000afU -#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY 0x000000b0U -#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY 0x000000b1U -#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY 0x000000b2U -#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY 0x000000b3U -#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY 0x000000b4U -#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY 0x000000b5U -#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY 0x000000b6U -#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY 0x000000b7U -#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY 0x000000b8U -#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY 0x000000b9U -#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY 0x000000baU -#define _reg_PHY_RDDQS_LATENCY_ADJUST 0x000000bbU -#define _reg_PHY_WRITE_PATH_LAT_ADD 0x000000bcU -#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD 0x000000bdU -#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD 0x000000beU -#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO 0x000000bfU -#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START 0x000000c0U -#define _reg_PHY_GTLVL_LAT_ADJ_START 0x000000c1U -#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START 0x000000c2U -#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START 0x000000c3U -#define _reg_PHY_FDBK_PWR_CTRL 0x000000c4U -#define _reg_PHY_DQ_OE_TIMING 0x000000c5U -#define _reg_PHY_DQ_TSEL_RD_TIMING 0x000000c6U -#define _reg_PHY_DQ_TSEL_WR_TIMING 0x000000c7U -#define _reg_PHY_DQS_OE_TIMING 0x000000c8U -#define _reg_PHY_DQS_TSEL_RD_TIMING 0x000000c9U -#define _reg_PHY_DQS_OE_RD_TIMING 0x000000caU -#define _reg_PHY_DQS_TSEL_WR_TIMING 0x000000cbU -#define _reg_PHY_PER_CS_TRAINING_EN 0x000000ccU -#define _reg_PHY_DQ_IE_TIMING 0x000000cdU -#define _reg_PHY_DQS_IE_TIMING 0x000000ceU -#define _reg_PHY_RDDATA_EN_IE_DLY 0x000000cfU -#define _reg_PHY_IE_MODE 0x000000d0U -#define _reg_PHY_RDDATA_EN_DLY 0x000000d1U -#define _reg_PHY_RDDATA_EN_TSEL_DLY 0x000000d2U -#define _reg_PHY_RDDATA_EN_OE_DLY 0x000000d3U -#define _reg_PHY_SW_MASTER_MODE 0x000000d4U -#define _reg_PHY_MASTER_DELAY_START 0x000000d5U -#define _reg_PHY_MASTER_DELAY_STEP 0x000000d6U -#define _reg_PHY_MASTER_DELAY_WAIT 0x000000d7U -#define _reg_PHY_MASTER_DELAY_HALF_MEASURE 0x000000d8U -#define _reg_PHY_RPTR_UPDATE 0x000000d9U -#define _reg_PHY_WRLVL_DLY_STEP 0x000000daU -#define _reg_PHY_WRLVL_RESP_WAIT_CNT 0x000000dbU -#define _reg_PHY_GTLVL_DLY_STEP 0x000000dcU -#define _reg_PHY_GTLVL_RESP_WAIT_CNT 0x000000ddU -#define _reg_PHY_GTLVL_BACK_STEP 0x000000deU -#define _reg_PHY_GTLVL_FINAL_STEP 0x000000dfU -#define _reg_PHY_WDQLVL_DLY_STEP 0x000000e0U -#define _reg_PHY_TOGGLE_PRE_SUPPORT 0x000000e1U -#define _reg_PHY_RDLVL_DLY_STEP 0x000000e2U -#define _reg_PHY_WRPATH_GATE_DISABLE 0x000000e3U -#define _reg_PHY_WRPATH_GATE_TIMING 0x000000e4U -#define _reg_PHY_ADR0_SW_WRADDR_SHIFT 0x000000e5U -#define _reg_PHY_ADR1_SW_WRADDR_SHIFT 0x000000e6U -#define _reg_PHY_ADR2_SW_WRADDR_SHIFT 0x000000e7U -#define _reg_PHY_ADR3_SW_WRADDR_SHIFT 0x000000e8U -#define _reg_PHY_ADR4_SW_WRADDR_SHIFT 0x000000e9U -#define _reg_PHY_ADR5_SW_WRADDR_SHIFT 0x000000eaU -#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY 0x000000ebU -#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE 0x000000ecU -#define _reg_SC_PHY_ADR_MANUAL_CLEAR 0x000000edU -#define _reg_PHY_ADR_LPBK_RESULT_OBS 0x000000eeU -#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS 0x000000efU -#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT 0x000000f0U -#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS 0x000000f1U -#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS 0x000000f2U -#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS 0x000000f3U -#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE 0x000000f4U -#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT 0x000000f5U -#define _reg_SC_PHY_ADR_SNAP_OBS_REGS 0x000000f6U -#define _reg_PHY_ADR_TSEL_ENABLE 0x000000f7U -#define _reg_PHY_ADR_LPBK_CONTROL 0x000000f8U -#define _reg_PHY_ADR_PRBS_PATTERN_START 0x000000f9U -#define _reg_PHY_ADR_PRBS_PATTERN_MASK 0x000000faU -#define _reg_PHY_ADR_PWR_RDC_DISABLE 0x000000fbU -#define _reg_PHY_ADR_TYPE 0x000000fcU -#define _reg_PHY_ADR_WRADDR_SHIFT_OBS 0x000000fdU -#define _reg_PHY_ADR_IE_MODE 0x000000feU -#define _reg_PHY_ADR_DDL_MODE 0x000000ffU -#define _reg_PHY_ADR_DDL_TEST_OBS 0x00000100U -#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS 0x00000101U -#define _reg_PHY_ADR_CALVL_START 0x00000102U -#define _reg_PHY_ADR_CALVL_COARSE_DLY 0x00000103U -#define _reg_PHY_ADR_CALVL_QTR 0x00000104U -#define _reg_PHY_ADR_CALVL_SWIZZLE0 0x00000105U -#define _reg_PHY_ADR_CALVL_SWIZZLE1 0x00000106U -#define _reg_PHY_ADR_CALVL_SWIZZLE0_0 0x00000107U -#define _reg_PHY_ADR_CALVL_SWIZZLE1_0 0x00000108U -#define _reg_PHY_ADR_CALVL_SWIZZLE0_1 0x00000109U -#define _reg_PHY_ADR_CALVL_SWIZZLE1_1 0x0000010aU -#define _reg_PHY_ADR_CALVL_DEVICE_MAP 0x0000010bU -#define _reg_PHY_ADR_CALVL_RANK_CTRL 0x0000010cU -#define _reg_PHY_ADR_CALVL_NUM_PATTERNS 0x0000010dU -#define _reg_PHY_ADR_CALVL_CAPTURE_CNT 0x0000010eU -#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT 0x0000010fU -#define _reg_PHY_ADR_CALVL_DEBUG_MODE 0x00000110U -#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT 0x00000111U -#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR 0x00000112U -#define _reg_PHY_ADR_CALVL_OBS_SELECT 0x00000113U -#define _reg_PHY_ADR_CALVL_OBS0 0x00000114U -#define _reg_PHY_ADR_CALVL_OBS1 0x00000115U -#define _reg_PHY_ADR_CALVL_RESULT 0x00000116U -#define _reg_PHY_ADR_CALVL_FG_0 0x00000117U -#define _reg_PHY_ADR_CALVL_BG_0 0x00000118U -#define _reg_PHY_ADR_CALVL_FG_1 0x00000119U -#define _reg_PHY_ADR_CALVL_BG_1 0x0000011aU -#define _reg_PHY_ADR_CALVL_FG_2 0x0000011bU -#define _reg_PHY_ADR_CALVL_BG_2 0x0000011cU -#define _reg_PHY_ADR_CALVL_FG_3 0x0000011dU -#define _reg_PHY_ADR_CALVL_BG_3 0x0000011eU -#define _reg_PHY_ADR_ADDR_SEL 0x0000011fU -#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY 0x00000120U -#define _reg_PHY_ADR_BIT_MASK 0x00000121U -#define _reg_PHY_ADR_SEG_MASK 0x00000122U -#define _reg_PHY_ADR_CALVL_TRAIN_MASK 0x00000123U -#define _reg_PHY_ADR_CSLVL_TRAIN_MASK 0x00000124U -#define _reg_PHY_ADR_SW_TXIO_CTRL 0x00000125U -#define _reg_PHY_ADR_TSEL_SELECT 0x00000126U -#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY 0x00000127U -#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY 0x00000128U -#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY 0x00000129U -#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY 0x0000012aU -#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY 0x0000012bU -#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY 0x0000012cU -#define _reg_PHY_ADR_SW_MASTER_MODE 0x0000012dU -#define _reg_PHY_ADR_MASTER_DELAY_START 0x0000012eU -#define _reg_PHY_ADR_MASTER_DELAY_STEP 0x0000012fU -#define _reg_PHY_ADR_MASTER_DELAY_WAIT 0x00000130U -#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE 0x00000131U -#define _reg_PHY_ADR_CALVL_DLY_STEP 0x00000132U -#define _reg_PHY_FREQ_SEL 0x00000133U -#define _reg_PHY_FREQ_SEL_FROM_REGIF 0x00000134U -#define _reg_PHY_FREQ_SEL_MULTICAST_EN 0x00000135U -#define _reg_PHY_FREQ_SEL_INDEX 0x00000136U -#define _reg_PHY_SW_GRP_SHIFT_0 0x00000137U -#define _reg_PHY_SW_GRP_SHIFT_1 0x00000138U -#define _reg_PHY_SW_GRP_SHIFT_2 0x00000139U -#define _reg_PHY_SW_GRP_SHIFT_3 0x0000013aU -#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY 0x0000013bU -#define _reg_PHY_SW_GRP_BYPASS_SHIFT 0x0000013cU -#define _reg_PHY_GRP_BYPASS_OVERRIDE 0x0000013dU -#define _reg_SC_PHY_MANUAL_UPDATE 0x0000013eU -#define _reg_SC_PHY_MANUAL_UPDATE_PHYUPD_ENABLE 0x0000013fU -#define _reg_PHY_LP4_BOOT_DISABLE 0x00000140U -#define _reg_PHY_CSLVL_ENABLE 0x00000141U -#define _reg_PHY_CSLVL_CS_MAP 0x00000142U -#define _reg_PHY_CSLVL_START 0x00000143U -#define _reg_PHY_CSLVL_QTR 0x00000144U -#define _reg_PHY_CSLVL_COARSE_CHK 0x00000145U -#define _reg_PHY_CSLVL_CAPTURE_CNT 0x00000146U -#define _reg_PHY_CSLVL_COARSE_DLY 0x00000147U -#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT 0x00000148U -#define _reg_PHY_CSLVL_DEBUG_MODE 0x00000149U -#define _reg_SC_PHY_CSLVL_DEBUG_CONT 0x0000014aU -#define _reg_SC_PHY_CSLVL_ERROR_CLR 0x0000014bU -#define _reg_PHY_CSLVL_OBS0 0x0000014cU -#define _reg_PHY_CSLVL_OBS1 0x0000014dU -#define _reg_PHY_CALVL_CS_MAP 0x0000014eU -#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT 0x0000014fU -#define _reg_PHY_GRP_SHIFT_OBS_SELECT 0x00000150U -#define _reg_PHY_GRP_SLV_DLY_ENC_OBS 0x00000151U -#define _reg_PHY_GRP_SHIFT_OBS 0x00000152U -#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE 0x00000153U -#define _reg_PHY_ADRCTL_SNAP_OBS_REGS 0x00000154U -#define _reg_PHY_DFI_PHYUPD_TYPE 0x00000155U -#define _reg_PHY_ADRCTL_LPDDR 0x00000156U -#define _reg_PHY_LP4_ACTIVE 0x00000157U -#define _reg_PHY_LPDDR3_CS 0x00000158U -#define _reg_PHY_CALVL_RESULT_MASK 0x00000159U -#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES 0x0000015aU -#define _reg_PHY_SW_TXIO_CTRL_0 0x0000015bU -#define _reg_PHY_SW_TXIO_CTRL_1 0x0000015cU -#define _reg_PHY_SW_TXIO_CTRL_2 0x0000015dU -#define _reg_PHY_SW_TXIO_CTRL_3 0x0000015eU -#define _reg_PHY_MEMCLK_SW_TXIO_CTRL 0x0000015fU -#define _reg_PHY_CA_SW_TXPWR_CTRL 0x00000160U -#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL 0x00000161U -#define _reg_PHY_USER_DEF_REG_AC_0 0x00000162U -#define _reg_PHY_USER_DEF_REG_AC_1 0x00000163U -#define _reg_PHY_USER_DEF_REG_AC_2 0x00000164U -#define _reg_PHY_USER_DEF_REG_AC_3 0x00000165U -#define _reg_PHY_UPDATE_CLK_CAL_VALUES 0x00000166U -#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE 0x00000167U -#define _reg_PHY_PLL_CTRL 0x00000168U -#define _reg_PHY_PLL_CTRL_TOP 0x00000169U -#define _reg_PHY_PLL_CTRL_CA 0x0000016aU -#define _reg_PHY_PLL_BYPASS 0x0000016bU -#define _reg_PHY_LOW_FREQ_SEL 0x0000016cU -#define _reg_PHY_PAD_VREF_CTRL_DQ_0 0x0000016dU -#define _reg_PHY_PAD_VREF_CTRL_DQ_1 0x0000016eU -#define _reg_PHY_PAD_VREF_CTRL_DQ_2 0x0000016fU -#define _reg_PHY_PAD_VREF_CTRL_DQ_3 0x00000170U -#define _reg_PHY_PAD_VREF_CTRL_AC 0x00000171U -#define _reg_PHY_CSLVL_DLY_STEP 0x00000172U -#define _reg_PHY_SET_DFI_INPUT_0 0x00000173U -#define _reg_PHY_SET_DFI_INPUT_1 0x00000174U -#define _reg_PHY_SET_DFI_INPUT_2 0x00000175U -#define _reg_PHY_SET_DFI_INPUT_3 0x00000176U -#define _reg_PHY_GRP_SLAVE_DELAY_0 0x00000177U -#define _reg_PHY_GRP_SLAVE_DELAY_1 0x00000178U -#define _reg_PHY_GRP_SLAVE_DELAY_2 0x00000179U -#define _reg_PHY_GRP_SLAVE_DELAY_3 0x0000017aU -#define _reg_PHY_CS_ACS_ALLOCATION_0 0x0000017bU -#define _reg_PHY_CS_ACS_ALLOCATION_1 0x0000017cU -#define _reg_PHY_CS_ACS_ALLOCATION_2 0x0000017dU -#define _reg_PHY_CS_ACS_ALLOCATION_3 0x0000017eU -#define _reg_PHY_LP4_BOOT_PLL_CTRL 0x0000017fU -#define _reg_PHY_LP4_BOOT_PLL_CTRL_CA 0x00000180U -#define _reg_PHY_LP4_BOOT_TOP_PLL_CTRL 0x00000181U -#define _reg_PHY_PLL_CTRL_OVERRIDE 0x00000182U -#define _reg_PHY_PLL_WAIT 0x00000183U -#define _reg_PHY_PLL_WAIT_TOP 0x00000184U -#define _reg_PHY_PLL_OBS_0 0x00000185U -#define _reg_PHY_PLL_OBS_1 0x00000186U -#define _reg_PHY_PLL_OBS_2 0x00000187U -#define _reg_PHY_PLL_OBS_3 0x00000188U -#define _reg_PHY_PLL_OBS_4 0x00000189U -#define _reg_PHY_PLL_TESTOUT_SEL 0x0000018aU -#define _reg_PHY_TCKSRE_WAIT 0x0000018bU -#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL 0x0000018cU -#define _reg_PHY_LP_WAKEUP 0x0000018dU -#define _reg_PHY_LS_IDLE_EN 0x0000018eU -#define _reg_PHY_LP_CTRLUPD_CNTR_CFG 0x0000018fU -#define _reg_PHY_TDFI_PHY_WRDELAY 0x00000190U -#define _reg_PHY_PAD_FDBK_DRIVE 0x00000191U -#define _reg_PHY_PAD_DATA_DRIVE 0x00000192U -#define _reg_PHY_PAD_DQS_DRIVE 0x00000193U -#define _reg_PHY_PAD_ADDR_DRIVE 0x00000194U -#define _reg_PHY_PAD_CLK_DRIVE 0x00000195U -#define _reg_PHY_PAD_FDBK_TERM 0x00000196U -#define _reg_PHY_PAD_DATA_TERM 0x00000197U -#define _reg_PHY_PAD_DQS_TERM 0x00000198U -#define _reg_PHY_PAD_ADDR_TERM 0x00000199U -#define _reg_PHY_PAD_CLK_TERM 0x0000019aU -#define _reg_PHY_PAD_CKE_DRIVE 0x0000019bU -#define _reg_PHY_PAD_CKE_TERM 0x0000019cU -#define _reg_PHY_PAD_RST_DRIVE 0x0000019dU -#define _reg_PHY_PAD_RST_TERM 0x0000019eU -#define _reg_PHY_PAD_CS_DRIVE 0x0000019fU -#define _reg_PHY_PAD_CS_TERM 0x000001a0U -#define _reg_PHY_PAD_ODT_DRIVE 0x000001a1U -#define _reg_PHY_PAD_ODT_TERM 0x000001a2U -#define _reg_PHY_ADRCTL_RX_CAL 0x000001a3U -#define _reg_PHY_ADRCTL_LP3_RX_CAL 0x000001a4U -#define _reg_PHY_TST_CLK_PAD_CTRL 0x000001a5U -#define _reg_PHY_TST_CLK_PAD_CTRL2 0x000001a6U -#define _reg_PHY_CAL_MODE_0 0x000001a7U -#define _reg_PHY_CAL_CLEAR_0 0x000001a8U -#define _reg_PHY_CAL_START_0 0x000001a9U -#define _reg_PHY_CAL_INTERVAL_COUNT_0 0x000001aaU -#define _reg_PHY_CAL_SAMPLE_WAIT_0 0x000001abU -#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0 0x000001acU -#define _reg_PHY_CAL_CLK_SELECT_0 0x000001adU -#define _reg_PHY_CAL_RESULT_OBS_0 0x000001aeU -#define _reg_PHY_CAL_RESULT2_OBS_0 0x000001afU -#define _reg_PHY_CAL_CPTR_CNT_0 0x000001b0U -#define _reg_PHY_CAL_SETTLING_PRD_0 0x000001b1U -#define _reg_PHY_CAL_PU_FINE_ADJ_0 0x000001b2U -#define _reg_PHY_CAL_PD_FINE_ADJ_0 0x000001b3U -#define _reg_PHY_CAL_RCV_FINE_ADJ_0 0x000001b4U -#define _reg_PHY_CAL_DBG_CFG_0 0x000001b5U -#define _reg_SC_PHY_PAD_DBG_CONT_0 0x000001b6U -#define _reg_PHY_CAL_RESULT3_OBS_0 0x000001b7U -#define _reg_PHY_ADRCTL_PVT_MAP_0 0x000001b8U -#define _reg_PHY_CAL_SLOPE_ADJ_0 0x000001b9U -#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0 0x000001baU -#define _reg_PHY_CAL_TWO_PASS_CFG_0 0x000001bbU -#define _reg_PHY_CAL_SW_CAL_CFG_0 0x000001bcU -#define _reg_PHY_CAL_RANGE_MIN_0 0x000001bdU -#define _reg_PHY_CAL_RANGE_MAX_0 0x000001beU -#define _reg_PHY_PAD_ATB_CTRL 0x000001bfU -#define _reg_PHY_ADRCTL_MANUAL_UPDATE 0x000001c0U -#define _reg_PHY_AC_LPBK_ERR_CLEAR 0x000001c1U -#define _reg_PHY_AC_LPBK_OBS_SELECT 0x000001c2U -#define _reg_PHY_AC_LPBK_ENABLE 0x000001c3U -#define _reg_PHY_AC_LPBK_CONTROL 0x000001c4U -#define _reg_PHY_AC_PRBS_PATTERN_START 0x000001c5U -#define _reg_PHY_AC_PRBS_PATTERN_MASK 0x000001c6U -#define _reg_PHY_AC_LPBK_RESULT_OBS 0x000001c7U -#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT 0x000001c8U -#define _reg_PHY_AC_CLK_LPBK_ENABLE 0x000001c9U -#define _reg_PHY_AC_CLK_LPBK_CONTROL 0x000001caU -#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS 0x000001cbU -#define _reg_PHY_AC_PWR_RDC_DISABLE 0x000001ccU -#define _reg_PHY_DATA_BYTE_ORDER_SEL 0x000001cdU -#define _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH 0x000001ceU -#define _reg_PHY_LPDDR4_CONNECT 0x000001cfU -#define _reg_PHY_CALVL_DEVICE_MAP 0x000001d0U -#define _reg_PHY_ADR_DISABLE 0x000001d1U -#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL 0x000001d2U -#define _reg_PHY_CS_DLY_UPT_PER_AC_SLICE 0x000001d3U -#define _reg_PHY_DDL_AC_ENABLE 0x000001d4U -#define _reg_PHY_DDL_AC_MODE 0x000001d5U -#define _reg_PHY_PAD_BACKGROUND_CAL 0x000001d6U -#define _reg_PHY_INIT_UPDATE_CONFIG 0x000001d7U -#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC 0x000001d8U -#define _reg_PHY_DLL_RST_EN 0x000001d9U -#define _reg_PHY_AC_INIT_COMPLETE_OBS 0x000001daU -#define _reg_PHY_DS_INIT_COMPLETE_OBS 0x000001dbU -#define _reg_PHY_UPDATE_MASK 0x000001dcU -#define _reg_PHY_PLL_SWITCH_CNT 0x000001ddU -#define _reg_PI_START 0x000001deU -#define _reg_PI_DRAM_CLASS 0x000001dfU -#define _reg_PI_VERSION 0x000001e0U -#define _reg_PI_NORMAL_LVL_SEQ 0x000001e1U -#define _reg_PI_INIT_LVL_EN 0x000001e2U -#define _reg_PI_NOTCARE_PHYUPD 0x000001e3U -#define _reg_PI_ONBUS_MBIST 0x000001e4U -#define _reg_PI_TCMD_GAP 0x000001e5U -#define _reg_PI_MASTER_ACK_DURATION_MIN 0x000001e6U -#define _reg_PI_DFI_VERSION 0x000001e7U -#define _reg_PI_TDFI_PHYMSTR_TYPE0 0x000001e8U -#define _reg_PI_TDFI_PHYMSTR_TYPE1 0x000001e9U -#define _reg_PI_TDFI_PHYMSTR_TYPE2 0x000001eaU -#define _reg_PI_TDFI_PHYMSTR_TYPE3 0x000001ebU -#define _reg_PI_DFI_PHYMSTR_TYPE 0x000001ecU -#define _reg_PI_DFI_PHYMSTR_CS_STATE_R 0x000001edU -#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R 0x000001eeU -#define _reg_PI_TDFI_PHYMSTR_MAX_F0 0x000001efU -#define _reg_PI_TDFI_PHYMSTR_RESP_F0 0x000001f0U -#define _reg_PI_TDFI_PHYMSTR_MAX_F1 0x000001f1U -#define _reg_PI_TDFI_PHYMSTR_RESP_F1 0x000001f2U -#define _reg_PI_TDFI_PHYMSTR_MAX_F2 0x000001f3U -#define _reg_PI_TDFI_PHYMSTR_RESP_F2 0x000001f4U -#define _reg_PI_TDFI_PHYUPD_RESP_F0 0x000001f5U -#define _reg_PI_TDFI_PHYUPD_TYPE0_F0 0x000001f6U -#define _reg_PI_TDFI_PHYUPD_TYPE1_F0 0x000001f7U -#define _reg_PI_TDFI_PHYUPD_TYPE2_F0 0x000001f8U -#define _reg_PI_TDFI_PHYUPD_TYPE3_F0 0x000001f9U -#define _reg_PI_TDFI_PHYUPD_RESP_F1 0x000001faU -#define _reg_PI_TDFI_PHYUPD_TYPE0_F1 0x000001fbU -#define _reg_PI_TDFI_PHYUPD_TYPE1_F1 0x000001fcU -#define _reg_PI_TDFI_PHYUPD_TYPE2_F1 0x000001fdU -#define _reg_PI_TDFI_PHYUPD_TYPE3_F1 0x000001feU -#define _reg_PI_TDFI_PHYUPD_RESP_F2 0x000001ffU -#define _reg_PI_TDFI_PHYUPD_TYPE0_F2 0x00000200U -#define _reg_PI_TDFI_PHYUPD_TYPE1_F2 0x00000201U -#define _reg_PI_TDFI_PHYUPD_TYPE2_F2 0x00000202U -#define _reg_PI_TDFI_PHYUPD_TYPE3_F2 0x00000203U -#define _reg_PI_CONTROL_ERROR_STATUS 0x00000204U -#define _reg_PI_EXIT_AFTER_INIT_CALVL 0x00000205U -#define _reg_PI_FREQ_MAP 0x00000206U -#define _reg_PI_INIT_WORK_FREQ 0x00000207U -#define _reg_PI_INIT_DFS_CALVL_ONLY 0x00000208U -#define _reg_PI_POWER_ON_SEQ_BYPASS_ARRAY 0x00000209U -#define _reg_PI_POWER_ON_SEQ_END_ARRAY 0x0000020aU -#define _reg_PI_SEQ1_PAT 0x0000020bU -#define _reg_PI_SEQ1_PAT_MASK 0x0000020cU -#define _reg_PI_SEQ2_PAT 0x0000020dU -#define _reg_PI_SEQ2_PAT_MASK 0x0000020eU -#define _reg_PI_SEQ3_PAT 0x0000020fU -#define _reg_PI_SEQ3_PAT_MASK 0x00000210U -#define _reg_PI_SEQ4_PAT 0x00000211U -#define _reg_PI_SEQ4_PAT_MASK 0x00000212U -#define _reg_PI_SEQ5_PAT 0x00000213U -#define _reg_PI_SEQ5_PAT_MASK 0x00000214U -#define _reg_PI_SEQ6_PAT 0x00000215U -#define _reg_PI_SEQ6_PAT_MASK 0x00000216U -#define _reg_PI_SEQ7_PAT 0x00000217U -#define _reg_PI_SEQ7_PAT_MASK 0x00000218U -#define _reg_PI_SEQ8_PAT 0x00000219U -#define _reg_PI_SEQ8_PAT_MASK 0x0000021aU -#define _reg_PI_WDT_DISABLE 0x0000021bU -#define _reg_PI_SW_RST_N 0x0000021cU -#define _reg_RESERVED_R0 0x0000021dU -#define _reg_PI_CS_MAP 0x0000021eU -#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0 0x0000021fU -#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x00000220U -#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x00000221U -#define _reg_PI_TMRR 0x00000222U -#define _reg_PI_WRLAT_F0 0x00000223U -#define _reg_PI_ADDITIVE_LAT_F0 0x00000224U -#define _reg_PI_CASLAT_LIN_F0 0x00000225U -#define _reg_PI_WRLAT_F1 0x00000226U -#define _reg_PI_ADDITIVE_LAT_F1 0x00000227U -#define _reg_PI_CASLAT_LIN_F1 0x00000228U -#define _reg_PI_WRLAT_F2 0x00000229U -#define _reg_PI_ADDITIVE_LAT_F2 0x0000022aU -#define _reg_PI_CASLAT_LIN_F2 0x0000022bU -#define _reg_PI_PREAMBLE_SUPPORT 0x0000022cU -#define _reg_PI_AREFRESH 0x0000022dU -#define _reg_PI_MCAREF_FORWARD_ONLY 0x0000022eU -#define _reg_PI_TRFC_F0 0x0000022fU -#define _reg_PI_TREF_F0 0x00000230U -#define _reg_PI_TRFC_F1 0x00000231U -#define _reg_PI_TREF_F1 0x00000232U -#define _reg_PI_TRFC_F2 0x00000233U -#define _reg_PI_TREF_F2 0x00000234U -#define _reg_RESERVED_H3VER2 0x00000235U -#define _reg_PI_TREF_INTERVAL 0x00000236U -#define _reg_PI_FREQ_CHANGE_REG_COPY 0x00000237U -#define _reg_PI_FREQ_SEL_FROM_REGIF 0x00000238U -#define _reg_PI_SWLVL_LOAD 0x00000239U -#define _reg_PI_SWLVL_OP_DONE 0x0000023aU -#define _reg_PI_SW_WRLVL_RESP_0 0x0000023bU -#define _reg_PI_SW_WRLVL_RESP_1 0x0000023cU -#define _reg_PI_SW_WRLVL_RESP_2 0x0000023dU -#define _reg_PI_SW_WRLVL_RESP_3 0x0000023eU -#define _reg_PI_SW_RDLVL_RESP_0 0x0000023fU -#define _reg_PI_SW_RDLVL_RESP_1 0x00000240U -#define _reg_PI_SW_RDLVL_RESP_2 0x00000241U -#define _reg_PI_SW_RDLVL_RESP_3 0x00000242U -#define _reg_PI_SW_CALVL_RESP_0 0x00000243U -#define _reg_PI_SW_LEVELING_MODE 0x00000244U -#define _reg_PI_SWLVL_START 0x00000245U -#define _reg_PI_SWLVL_EXIT 0x00000246U -#define _reg_PI_SWLVL_WR_SLICE_0 0x00000247U -#define _reg_PI_SWLVL_RD_SLICE_0 0x00000248U -#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0 0x00000249U -#define _reg_PI_SW_WDQLVL_RESP_0 0x0000024aU -#define _reg_PI_SWLVL_WR_SLICE_1 0x0000024bU -#define _reg_PI_SWLVL_RD_SLICE_1 0x0000024cU -#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1 0x0000024dU -#define _reg_PI_SW_WDQLVL_RESP_1 0x0000024eU -#define _reg_PI_SWLVL_WR_SLICE_2 0x0000024fU -#define _reg_PI_SWLVL_RD_SLICE_2 0x00000250U -#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_2 0x00000251U -#define _reg_PI_SW_WDQLVL_RESP_2 0x00000252U -#define _reg_PI_SWLVL_WR_SLICE_3 0x00000253U -#define _reg_PI_SWLVL_RD_SLICE_3 0x00000254U -#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_3 0x00000255U -#define _reg_PI_SW_WDQLVL_RESP_3 0x00000256U -#define _reg_PI_SW_WDQLVL_VREF 0x00000257U -#define _reg_PI_SWLVL_SM2_START 0x00000258U -#define _reg_PI_SWLVL_SM2_WR 0x00000259U -#define _reg_PI_SWLVL_SM2_RD 0x0000025aU -#define _reg_PI_SEQUENTIAL_LVL_REQ 0x0000025bU -#define _reg_PI_DFS_PERIOD_EN 0x0000025cU -#define _reg_PI_SRE_PERIOD_EN 0x0000025dU -#define _reg_PI_DFI40_POLARITY 0x0000025eU -#define _reg_PI_16BIT_DRAM_CONNECT 0x0000025fU -#define _reg_PI_TDFI_CTRL_DELAY_F0 0x00000260U -#define _reg_PI_TDFI_CTRL_DELAY_F1 0x00000261U -#define _reg_PI_TDFI_CTRL_DELAY_F2 0x00000262U -#define _reg_PI_WRLVL_REQ 0x00000263U -#define _reg_PI_WRLVL_CS 0x00000264U -#define _reg_PI_WLDQSEN 0x00000265U -#define _reg_PI_WLMRD 0x00000266U -#define _reg_PI_WRLVL_EN_F0 0x00000267U -#define _reg_PI_WRLVL_EN_F1 0x00000268U -#define _reg_PI_WRLVL_EN_F2 0x00000269U -#define _reg_PI_WRLVL_EN 0x0000026aU -#define _reg_PI_WRLVL_INTERVAL 0x0000026bU -#define _reg_PI_WRLVL_PERIODIC 0x0000026cU -#define _reg_PI_WRLVL_ON_SREF_EXIT 0x0000026dU -#define _reg_PI_WRLVL_DISABLE_DFS 0x0000026eU -#define _reg_PI_WRLVL_RESP_MASK 0x0000026fU -#define _reg_PI_WRLVL_ROTATE 0x00000270U -#define _reg_PI_WRLVL_CS_MAP 0x00000271U -#define _reg_PI_WRLVL_ERROR_STATUS 0x00000272U -#define _reg_PI_TDFI_WRLVL_EN 0x00000273U -#define _reg_PI_TDFI_WRLVL_WW_F0 0x00000274U -#define _reg_PI_TDFI_WRLVL_WW_F1 0x00000275U -#define _reg_PI_TDFI_WRLVL_WW_F2 0x00000276U -#define _reg_PI_TDFI_WRLVL_WW 0x00000277U -#define _reg_PI_TDFI_WRLVL_RESP 0x00000278U -#define _reg_PI_TDFI_WRLVL_MAX 0x00000279U -#define _reg_PI_WRLVL_STROBE_NUM 0x0000027aU -#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ 0x0000027bU -#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR 0x0000027cU -#define _reg_PI_TODTL_2CMD_F0 0x0000027dU -#define _reg_PI_ODT_EN_F0 0x0000027eU -#define _reg_PI_TODTL_2CMD_F1 0x0000027fU -#define _reg_PI_ODT_EN_F1 0x00000280U -#define _reg_PI_TODTL_2CMD_F2 0x00000281U -#define _reg_PI_ODT_EN_F2 0x00000282U -#define _reg_PI_TODTH_WR 0x00000283U -#define _reg_PI_TODTH_RD 0x00000284U -#define _reg_PI_ODT_RD_MAP_CS0 0x00000285U -#define _reg_PI_ODT_WR_MAP_CS0 0x00000286U -#define _reg_PI_ODT_RD_MAP_CS1 0x00000287U -#define _reg_PI_ODT_WR_MAP_CS1 0x00000288U -#define _reg_PI_ODT_RD_MAP_CS2 0x00000289U -#define _reg_PI_ODT_WR_MAP_CS2 0x0000028aU -#define _reg_PI_ODT_RD_MAP_CS3 0x0000028bU -#define _reg_PI_ODT_WR_MAP_CS3 0x0000028cU -#define _reg_PI_EN_ODT_ASSERT_EXCEPT_RD 0x0000028dU -#define _reg_PI_ODTLON_F0 0x0000028eU -#define _reg_PI_TODTON_MIN_F0 0x0000028fU -#define _reg_PI_ODTLON_F1 0x00000290U -#define _reg_PI_TODTON_MIN_F1 0x00000291U -#define _reg_PI_ODTLON_F2 0x00000292U -#define _reg_PI_TODTON_MIN_F2 0x00000293U -#define _reg_PI_WR_TO_ODTH_F0 0x00000294U -#define _reg_PI_WR_TO_ODTH_F1 0x00000295U -#define _reg_PI_WR_TO_ODTH_F2 0x00000296U -#define _reg_PI_RD_TO_ODTH_F0 0x00000297U -#define _reg_PI_RD_TO_ODTH_F1 0x00000298U -#define _reg_PI_RD_TO_ODTH_F2 0x00000299U -#define _reg_PI_ADDRESS_MIRRORING 0x0000029aU -#define _reg_PI_RDLVL_REQ 0x0000029bU -#define _reg_PI_RDLVL_GATE_REQ 0x0000029cU -#define _reg_PI_RDLVL_CS 0x0000029dU -#define _reg_PI_RDLVL_PAT_0 0x0000029eU -#define _reg_PI_RDLVL_PAT_1 0x0000029fU -#define _reg_PI_RDLVL_PAT_2 0x000002a0U -#define _reg_PI_RDLVL_PAT_3 0x000002a1U -#define _reg_PI_RDLVL_PAT_4 0x000002a2U -#define _reg_PI_RDLVL_PAT_5 0x000002a3U -#define _reg_PI_RDLVL_PAT_6 0x000002a4U -#define _reg_PI_RDLVL_PAT_7 0x000002a5U -#define _reg_PI_RDLVL_SEQ_EN 0x000002a6U -#define _reg_PI_RDLVL_GATE_SEQ_EN 0x000002a7U -#define _reg_PI_RDLVL_PERIODIC 0x000002a8U -#define _reg_PI_RDLVL_ON_SREF_EXIT 0x000002a9U -#define _reg_PI_RDLVL_DISABLE_DFS 0x000002aaU -#define _reg_PI_RDLVL_GATE_PERIODIC 0x000002abU -#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT 0x000002acU -#define _reg_PI_RDLVL_GATE_DISABLE_DFS 0x000002adU -#define _reg_RESERVED_R1 0x000002aeU -#define _reg_PI_RDLVL_ROTATE 0x000002afU -#define _reg_PI_RDLVL_GATE_ROTATE 0x000002b0U -#define _reg_PI_RDLVL_CS_MAP 0x000002b1U -#define _reg_PI_RDLVL_GATE_CS_MAP 0x000002b2U -#define _reg_PI_TDFI_RDLVL_RR 0x000002b3U -#define _reg_PI_TDFI_RDLVL_RESP 0x000002b4U -#define _reg_PI_RDLVL_RESP_MASK 0x000002b5U -#define _reg_PI_TDFI_RDLVL_EN 0x000002b6U -#define _reg_PI_RDLVL_EN_F0 0x000002b7U -#define _reg_PI_RDLVL_GATE_EN_F0 0x000002b8U -#define _reg_PI_RDLVL_EN_F1 0x000002b9U -#define _reg_PI_RDLVL_GATE_EN_F1 0x000002baU -#define _reg_PI_RDLVL_EN_F2 0x000002bbU -#define _reg_PI_RDLVL_GATE_EN_F2 0x000002bcU -#define _reg_PI_RDLVL_EN 0x000002bdU -#define _reg_PI_RDLVL_GATE_EN 0x000002beU -#define _reg_PI_TDFI_RDLVL_MAX 0x000002bfU -#define _reg_PI_RDLVL_ERROR_STATUS 0x000002c0U -#define _reg_PI_RDLVL_INTERVAL 0x000002c1U -#define _reg_PI_RDLVL_GATE_INTERVAL 0x000002c2U -#define _reg_PI_RDLVL_PATTERN_START 0x000002c3U -#define _reg_PI_RDLVL_PATTERN_NUM 0x000002c4U -#define _reg_PI_RDLVL_STROBE_NUM 0x000002c5U -#define _reg_PI_RDLVL_GATE_STROBE_NUM 0x000002c6U -#define _reg_PI_LPDDR4_RDLVL_PATTERN_8 0x000002c7U -#define _reg_PI_LPDDR4_RDLVL_PATTERN_9 0x000002c8U -#define _reg_PI_LPDDR4_RDLVL_PATTERN_10 0x000002c9U -#define _reg_PI_LPDDR4_RDLVL_PATTERN_11 0x000002caU -#define _reg_PI_RD_PREAMBLE_TRAINING_EN 0x000002cbU -#define _reg_PI_REG_DIMM_ENABLE 0x000002ccU -#define _reg_PI_RDLAT_ADJ_F0 0x000002cdU -#define _reg_PI_RDLAT_ADJ_F1 0x000002ceU -#define _reg_PI_RDLAT_ADJ_F2 0x000002cfU -#define _reg_PI_TDFI_RDDATA_EN 0x000002d0U -#define _reg_PI_WRLAT_ADJ_F0 0x000002d1U -#define _reg_PI_WRLAT_ADJ_F1 0x000002d2U -#define _reg_PI_WRLAT_ADJ_F2 0x000002d3U -#define _reg_PI_TDFI_PHY_WRLAT 0x000002d4U -#define _reg_PI_TDFI_WRCSLAT_F0 0x000002d5U -#define _reg_PI_TDFI_WRCSLAT_F1 0x000002d6U -#define _reg_PI_TDFI_WRCSLAT_F2 0x000002d7U -#define _reg_PI_TDFI_RDCSLAT_F0 0x000002d8U -#define _reg_PI_TDFI_RDCSLAT_F1 0x000002d9U -#define _reg_PI_TDFI_RDCSLAT_F2 0x000002daU -#define _reg_PI_TDFI_PHY_WRDATA_F0 0x000002dbU -#define _reg_PI_TDFI_PHY_WRDATA_F1 0x000002dcU -#define _reg_PI_TDFI_PHY_WRDATA_F2 0x000002ddU -#define _reg_PI_TDFI_PHY_WRDATA 0x000002deU -#define _reg_PI_CALVL_REQ 0x000002dfU -#define _reg_PI_CALVL_CS 0x000002e0U -#define _reg_RESERVED_R2 0x000002e1U -#define _reg_RESERVED_R3 0x000002e2U -#define _reg_PI_CALVL_SEQ_EN 0x000002e3U -#define _reg_PI_CALVL_PERIODIC 0x000002e4U -#define _reg_PI_CALVL_ON_SREF_EXIT 0x000002e5U -#define _reg_PI_CALVL_DISABLE_DFS 0x000002e6U -#define _reg_PI_CALVL_ROTATE 0x000002e7U -#define _reg_PI_CALVL_CS_MAP 0x000002e8U -#define _reg_PI_TDFI_CALVL_EN 0x000002e9U -#define _reg_PI_TDFI_CALVL_CC_F0 0x000002eaU -#define _reg_PI_TDFI_CALVL_CAPTURE_F0 0x000002ebU -#define _reg_PI_TDFI_CALVL_CC_F1 0x000002ecU -#define _reg_PI_TDFI_CALVL_CAPTURE_F1 0x000002edU -#define _reg_PI_TDFI_CALVL_CC_F2 0x000002eeU -#define _reg_PI_TDFI_CALVL_CAPTURE_F2 0x000002efU -#define _reg_PI_TDFI_CALVL_RESP 0x000002f0U -#define _reg_PI_TDFI_CALVL_MAX 0x000002f1U -#define _reg_PI_CALVL_RESP_MASK 0x000002f2U -#define _reg_PI_CALVL_EN_F0 0x000002f3U -#define _reg_PI_CALVL_EN_F1 0x000002f4U -#define _reg_PI_CALVL_EN_F2 0x000002f5U -#define _reg_PI_CALVL_EN 0x000002f6U -#define _reg_PI_CALVL_ERROR_STATUS 0x000002f7U -#define _reg_PI_CALVL_INTERVAL 0x000002f8U -#define _reg_PI_TCACKEL 0x000002f9U -#define _reg_PI_TCAMRD 0x000002faU -#define _reg_PI_TCACKEH 0x000002fbU -#define _reg_PI_TMRZ_F0 0x000002fcU -#define _reg_PI_TCAENT_F0 0x000002fdU -#define _reg_PI_TMRZ_F1 0x000002feU -#define _reg_PI_TCAENT_F1 0x000002ffU -#define _reg_PI_TMRZ_F2 0x00000300U -#define _reg_PI_TCAENT_F2 0x00000301U -#define _reg_PI_TCAEXT 0x00000302U -#define _reg_PI_CA_TRAIN_VREF_EN 0x00000303U -#define _reg_PI_TDFI_CACSCA_F0 0x00000304U -#define _reg_PI_TDFI_CASEL_F0 0x00000305U -#define _reg_PI_TVREF_SHORT_F0 0x00000306U -#define _reg_PI_TVREF_LONG_F0 0x00000307U -#define _reg_PI_TDFI_CACSCA_F1 0x00000308U -#define _reg_PI_TDFI_CASEL_F1 0x00000309U -#define _reg_PI_TVREF_SHORT_F1 0x0000030aU -#define _reg_PI_TVREF_LONG_F1 0x0000030bU -#define _reg_PI_TDFI_CACSCA_F2 0x0000030cU -#define _reg_PI_TDFI_CASEL_F2 0x0000030dU -#define _reg_PI_TVREF_SHORT_F2 0x0000030eU -#define _reg_PI_TVREF_LONG_F2 0x0000030fU -#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0 0x00000310U -#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x00000311U -#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1 0x00000312U -#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x00000313U -#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2 0x00000314U -#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x00000315U -#define _reg_PI_CALVL_VREF_INITIAL_START_POINT 0x00000316U -#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT 0x00000317U -#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE 0x00000318U -#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE 0x00000319U -#define _reg_PI_CALVL_VREF_DELTA_F0 0x0000031aU -#define _reg_PI_CALVL_VREF_DELTA_F1 0x0000031bU -#define _reg_PI_CALVL_VREF_DELTA_F2 0x0000031cU -#define _reg_PI_CALVL_VREF_DELTA 0x0000031dU -#define _reg_PI_TDFI_INIT_START_MIN 0x0000031eU -#define _reg_PI_TDFI_INIT_COMPLETE_MIN 0x0000031fU -#define _reg_PI_TDFI_CALVL_STROBE_F0 0x00000320U -#define _reg_PI_TXP_F0 0x00000321U -#define _reg_PI_TMRWCKEL_F0 0x00000322U -#define _reg_PI_TCKELCK_F0 0x00000323U -#define _reg_PI_TDFI_CALVL_STROBE_F1 0x00000324U -#define _reg_PI_TXP_F1 0x00000325U -#define _reg_PI_TMRWCKEL_F1 0x00000326U -#define _reg_PI_TCKELCK_F1 0x00000327U -#define _reg_PI_TDFI_CALVL_STROBE_F2 0x00000328U -#define _reg_PI_TXP_F2 0x00000329U -#define _reg_PI_TMRWCKEL_F2 0x0000032aU -#define _reg_PI_TCKELCK_F2 0x0000032bU -#define _reg_PI_TCKCKEH 0x0000032cU -#define _reg_PI_CALVL_STROBE_NUM 0x0000032dU -#define _reg_PI_SW_CA_TRAIN_VREF 0x0000032eU -#define _reg_PI_TDFI_INIT_START_F0 0x0000032fU -#define _reg_PI_TDFI_INIT_COMPLETE_F0 0x00000330U -#define _reg_PI_TDFI_INIT_START_F1 0x00000331U -#define _reg_PI_TDFI_INIT_COMPLETE_F1 0x00000332U -#define _reg_PI_TDFI_INIT_START_F2 0x00000333U -#define _reg_PI_TDFI_INIT_COMPLETE_F2 0x00000334U -#define _reg_PI_CLKDISABLE_2_INIT_START 0x00000335U -#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE 0x00000336U -#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL 0x00000337U -#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE 0x00000338U -#define _reg_PI_TCKEHDQS_F0 0x00000339U -#define _reg_PI_TCKEHDQS_F1 0x0000033aU -#define _reg_PI_TCKEHDQS_F2 0x0000033bU -#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE 0x0000033cU -#define _reg_PI_WDQLVL_VREF_EN 0x0000033dU -#define _reg_PI_WDQLVL_BST_NUM 0x0000033eU -#define _reg_PI_TDFI_WDQLVL_WR_F0 0x0000033fU -#define _reg_PI_TDFI_WDQLVL_WR_F1 0x00000340U -#define _reg_PI_TDFI_WDQLVL_WR_F2 0x00000341U -#define _reg_PI_TDFI_WDQLVL_WR 0x00000342U -#define _reg_PI_TDFI_WDQLVL_RW 0x00000343U -#define _reg_PI_WDQLVL_RESP_MASK 0x00000344U -#define _reg_PI_WDQLVL_ROTATE 0x00000345U -#define _reg_PI_WDQLVL_CS_MAP 0x00000346U -#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x00000347U -#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x00000348U -#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x00000349U -#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x0000034aU -#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x0000034bU -#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x0000034cU -#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT 0x0000034dU -#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT 0x0000034eU -#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE 0x0000034fU -#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE 0x00000350U -#define _reg_PI_WDQLVL_VREF_DELTA_F0 0x00000351U -#define _reg_PI_WDQLVL_VREF_DELTA_F1 0x00000352U -#define _reg_PI_WDQLVL_VREF_DELTA_F2 0x00000353U -#define _reg_PI_WDQLVL_VREF_DELTA 0x00000354U -#define _reg_PI_WDQLVL_PERIODIC 0x00000355U -#define _reg_PI_WDQLVL_REQ 0x00000356U -#define _reg_PI_WDQLVL_CS 0x00000357U -#define _reg_PI_TDFI_WDQLVL_EN 0x00000358U -#define _reg_PI_TDFI_WDQLVL_RESP 0x00000359U -#define _reg_PI_TDFI_WDQLVL_MAX 0x0000035aU -#define _reg_PI_WDQLVL_INTERVAL 0x0000035bU -#define _reg_PI_WDQLVL_EN_F0 0x0000035cU -#define _reg_PI_WDQLVL_EN_F1 0x0000035dU -#define _reg_PI_WDQLVL_EN_F2 0x0000035eU -#define _reg_PI_WDQLVL_EN 0x0000035fU -#define _reg_PI_WDQLVL_ON_SREF_EXIT 0x00000360U -#define _reg_PI_WDQLVL_DISABLE_DFS 0x00000361U -#define _reg_PI_WDQLVL_ERROR_STATUS 0x00000362U -#define _reg_PI_MR1_DATA_F0_0 0x00000363U -#define _reg_PI_MR2_DATA_F0_0 0x00000364U -#define _reg_PI_MR3_DATA_F0_0 0x00000365U -#define _reg_PI_MR11_DATA_F0_0 0x00000366U -#define _reg_PI_MR12_DATA_F0_0 0x00000367U -#define _reg_PI_MR14_DATA_F0_0 0x00000368U -#define _reg_PI_MR22_DATA_F0_0 0x00000369U -#define _reg_PI_MR1_DATA_F1_0 0x0000036aU -#define _reg_PI_MR2_DATA_F1_0 0x0000036bU -#define _reg_PI_MR3_DATA_F1_0 0x0000036cU -#define _reg_PI_MR11_DATA_F1_0 0x0000036dU -#define _reg_PI_MR12_DATA_F1_0 0x0000036eU -#define _reg_PI_MR14_DATA_F1_0 0x0000036fU -#define _reg_PI_MR22_DATA_F1_0 0x00000370U -#define _reg_PI_MR1_DATA_F2_0 0x00000371U -#define _reg_PI_MR2_DATA_F2_0 0x00000372U -#define _reg_PI_MR3_DATA_F2_0 0x00000373U -#define _reg_PI_MR11_DATA_F2_0 0x00000374U -#define _reg_PI_MR12_DATA_F2_0 0x00000375U -#define _reg_PI_MR14_DATA_F2_0 0x00000376U -#define _reg_PI_MR22_DATA_F2_0 0x00000377U -#define _reg_PI_MR13_DATA_0 0x00000378U -#define _reg_PI_MR1_DATA_F0_1 0x00000379U -#define _reg_PI_MR2_DATA_F0_1 0x0000037aU -#define _reg_PI_MR3_DATA_F0_1 0x0000037bU -#define _reg_PI_MR11_DATA_F0_1 0x0000037cU -#define _reg_PI_MR12_DATA_F0_1 0x0000037dU -#define _reg_PI_MR14_DATA_F0_1 0x0000037eU -#define _reg_PI_MR22_DATA_F0_1 0x0000037fU -#define _reg_PI_MR1_DATA_F1_1 0x00000380U -#define _reg_PI_MR2_DATA_F1_1 0x00000381U -#define _reg_PI_MR3_DATA_F1_1 0x00000382U -#define _reg_PI_MR11_DATA_F1_1 0x00000383U -#define _reg_PI_MR12_DATA_F1_1 0x00000384U -#define _reg_PI_MR14_DATA_F1_1 0x00000385U -#define _reg_PI_MR22_DATA_F1_1 0x00000386U -#define _reg_PI_MR1_DATA_F2_1 0x00000387U -#define _reg_PI_MR2_DATA_F2_1 0x00000388U -#define _reg_PI_MR3_DATA_F2_1 0x00000389U -#define _reg_PI_MR11_DATA_F2_1 0x0000038aU -#define _reg_PI_MR12_DATA_F2_1 0x0000038bU -#define _reg_PI_MR14_DATA_F2_1 0x0000038cU -#define _reg_PI_MR22_DATA_F2_1 0x0000038dU -#define _reg_PI_MR13_DATA_1 0x0000038eU -#define _reg_PI_MR1_DATA_F0_2 0x0000038fU -#define _reg_PI_MR2_DATA_F0_2 0x00000390U -#define _reg_PI_MR3_DATA_F0_2 0x00000391U -#define _reg_PI_MR11_DATA_F0_2 0x00000392U -#define _reg_PI_MR12_DATA_F0_2 0x00000393U -#define _reg_PI_MR14_DATA_F0_2 0x00000394U -#define _reg_PI_MR22_DATA_F0_2 0x00000395U -#define _reg_PI_MR1_DATA_F1_2 0x00000396U -#define _reg_PI_MR2_DATA_F1_2 0x00000397U -#define _reg_PI_MR3_DATA_F1_2 0x00000398U -#define _reg_PI_MR11_DATA_F1_2 0x00000399U -#define _reg_PI_MR12_DATA_F1_2 0x0000039aU -#define _reg_PI_MR14_DATA_F1_2 0x0000039bU -#define _reg_PI_MR22_DATA_F1_2 0x0000039cU -#define _reg_PI_MR1_DATA_F2_2 0x0000039dU -#define _reg_PI_MR2_DATA_F2_2 0x0000039eU -#define _reg_PI_MR3_DATA_F2_2 0x0000039fU -#define _reg_PI_MR11_DATA_F2_2 0x000003a0U -#define _reg_PI_MR12_DATA_F2_2 0x000003a1U -#define _reg_PI_MR14_DATA_F2_2 0x000003a2U -#define _reg_PI_MR22_DATA_F2_2 0x000003a3U -#define _reg_PI_MR13_DATA_2 0x000003a4U -#define _reg_PI_MR1_DATA_F0_3 0x000003a5U -#define _reg_PI_MR2_DATA_F0_3 0x000003a6U -#define _reg_PI_MR3_DATA_F0_3 0x000003a7U -#define _reg_PI_MR11_DATA_F0_3 0x000003a8U -#define _reg_PI_MR12_DATA_F0_3 0x000003a9U -#define _reg_PI_MR14_DATA_F0_3 0x000003aaU -#define _reg_PI_MR22_DATA_F0_3 0x000003abU -#define _reg_PI_MR1_DATA_F1_3 0x000003acU -#define _reg_PI_MR2_DATA_F1_3 0x000003adU -#define _reg_PI_MR3_DATA_F1_3 0x000003aeU -#define _reg_PI_MR11_DATA_F1_3 0x000003afU -#define _reg_PI_MR12_DATA_F1_3 0x000003b0U -#define _reg_PI_MR14_DATA_F1_3 0x000003b1U -#define _reg_PI_MR22_DATA_F1_3 0x000003b2U -#define _reg_PI_MR1_DATA_F2_3 0x000003b3U -#define _reg_PI_MR2_DATA_F2_3 0x000003b4U -#define _reg_PI_MR3_DATA_F2_3 0x000003b5U -#define _reg_PI_MR11_DATA_F2_3 0x000003b6U -#define _reg_PI_MR12_DATA_F2_3 0x000003b7U -#define _reg_PI_MR14_DATA_F2_3 0x000003b8U -#define _reg_PI_MR22_DATA_F2_3 0x000003b9U -#define _reg_PI_MR13_DATA_3 0x000003baU -#define _reg_PI_BANK_DIFF 0x000003bbU -#define _reg_PI_ROW_DIFF 0x000003bcU -#define _reg_PI_TFC_F0 0x000003bdU -#define _reg_PI_TFC_F1 0x000003beU -#define _reg_PI_TFC_F2 0x000003bfU -#define _reg_PI_TCCD 0x000003c0U -#define _reg_PI_TRTP_F0 0x000003c1U -#define _reg_PI_TRP_F0 0x000003c2U -#define _reg_PI_TRCD_F0 0x000003c3U -#define _reg_PI_TWTR_F0 0x000003c4U -#define _reg_PI_TWR_F0 0x000003c5U -#define _reg_PI_TRAS_MAX_F0 0x000003c6U -#define _reg_PI_TRAS_MIN_F0 0x000003c7U -#define _reg_PI_TDQSCK_MAX_F0 0x000003c8U -#define _reg_PI_TCCDMW_F0 0x000003c9U -#define _reg_PI_TSR_F0 0x000003caU -#define _reg_PI_TMRD_F0 0x000003cbU -#define _reg_PI_TMRW_F0 0x000003ccU -#define _reg_PI_TMOD_F0 0x000003cdU -#define _reg_PI_TRTP_F1 0x000003ceU -#define _reg_PI_TRP_F1 0x000003cfU -#define _reg_PI_TRCD_F1 0x000003d0U -#define _reg_PI_TWTR_F1 0x000003d1U -#define _reg_PI_TWR_F1 0x000003d2U -#define _reg_PI_TRAS_MAX_F1 0x000003d3U -#define _reg_PI_TRAS_MIN_F1 0x000003d4U -#define _reg_PI_TDQSCK_MAX_F1 0x000003d5U -#define _reg_PI_TCCDMW_F1 0x000003d6U -#define _reg_PI_TSR_F1 0x000003d7U -#define _reg_PI_TMRD_F1 0x000003d8U -#define _reg_PI_TMRW_F1 0x000003d9U -#define _reg_PI_TMOD_F1 0x000003daU -#define _reg_PI_TRTP_F2 0x000003dbU -#define _reg_PI_TRP_F2 0x000003dcU -#define _reg_PI_TRCD_F2 0x000003ddU -#define _reg_PI_TWTR_F2 0x000003deU -#define _reg_PI_TWR_F2 0x000003dfU -#define _reg_PI_TRAS_MAX_F2 0x000003e0U -#define _reg_PI_TRAS_MIN_F2 0x000003e1U -#define _reg_PI_TDQSCK_MAX_F2 0x000003e2U -#define _reg_PI_TCCDMW_F2 0x000003e3U -#define _reg_PI_TSR_F2 0x000003e4U -#define _reg_PI_TMRD_F2 0x000003e5U -#define _reg_PI_TMRW_F2 0x000003e6U -#define _reg_PI_TMOD_F2 0x000003e7U -#define _reg_RESERVED_R4 0x000003e8U -#define _reg_RESERVED_R5 0x000003e9U -#define _reg_RESERVED_R6 0x000003eaU -#define _reg_RESERVED_R7 0x000003ebU -#define _reg_RESERVED_R8 0x000003ecU -#define _reg_RESERVED_R9 0x000003edU -#define _reg_RESERVED_R10 0x000003eeU -#define _reg_RESERVED_R11 0x000003efU -#define _reg_RESERVED_R12 0x000003f0U -#define _reg_RESERVED_R13 0x000003f1U -#define _reg_RESERVED_R14 0x000003f2U -#define _reg_RESERVED_R15 0x000003f3U -#define _reg_RESERVED_R16 0x000003f4U -#define _reg_RESERVED_R17 0x000003f5U -#define _reg_RESERVED_R18 0x000003f6U -#define _reg_RESERVED_R19 0x000003f7U -#define _reg_RESERVED_R20 0x000003f8U -#define _reg_RESERVED_R21 0x000003f9U -#define _reg_RESERVED_R22 0x000003faU -#define _reg_RESERVED_R23 0x000003fbU -#define _reg_PI_INT_STATUS 0x000003fcU -#define _reg_PI_INT_ACK 0x000003fdU -#define _reg_PI_INT_MASK 0x000003feU -#define _reg_PI_BIST_EXP_DATA_P0 0x000003ffU -#define _reg_PI_BIST_EXP_DATA_P1 0x00000400U -#define _reg_PI_BIST_EXP_DATA_P2 0x00000401U -#define _reg_PI_BIST_EXP_DATA_P3 0x00000402U -#define _reg_PI_BIST_FAIL_DATA_P0 0x00000403U -#define _reg_PI_BIST_FAIL_DATA_P1 0x00000404U -#define _reg_PI_BIST_FAIL_DATA_P2 0x00000405U -#define _reg_PI_BIST_FAIL_DATA_P3 0x00000406U -#define _reg_PI_BIST_FAIL_ADDR_P0 0x00000407U -#define _reg_PI_BIST_FAIL_ADDR_P1 0x00000408U -#define _reg_PI_BSTLEN 0x00000409U -#define _reg_PI_LONG_COUNT_MASK 0x0000040aU -#define _reg_PI_CMD_SWAP_EN 0x0000040bU -#define _reg_PI_CKE_MUX_0 0x0000040cU -#define _reg_PI_CKE_MUX_1 0x0000040dU -#define _reg_PI_CKE_MUX_2 0x0000040eU -#define _reg_PI_CKE_MUX_3 0x0000040fU -#define _reg_PI_CS_MUX_0 0x00000410U -#define _reg_PI_CS_MUX_1 0x00000411U -#define _reg_PI_CS_MUX_2 0x00000412U -#define _reg_PI_CS_MUX_3 0x00000413U -#define _reg_PI_RAS_N_MUX 0x00000414U -#define _reg_PI_CAS_N_MUX 0x00000415U -#define _reg_PI_WE_N_MUX 0x00000416U -#define _reg_PI_BANK_MUX_0 0x00000417U -#define _reg_PI_BANK_MUX_1 0x00000418U -#define _reg_PI_BANK_MUX_2 0x00000419U -#define _reg_PI_ODT_MUX_0 0x0000041aU -#define _reg_PI_ODT_MUX_1 0x0000041bU -#define _reg_PI_ODT_MUX_2 0x0000041cU -#define _reg_PI_ODT_MUX_3 0x0000041dU -#define _reg_PI_RESET_N_MUX_0 0x0000041eU -#define _reg_PI_RESET_N_MUX_1 0x0000041fU -#define _reg_PI_RESET_N_MUX_2 0x00000420U -#define _reg_PI_RESET_N_MUX_3 0x00000421U -#define _reg_PI_DATA_BYTE_SWAP_EN 0x00000422U -#define _reg_PI_DATA_BYTE_SWAP_SLICE0 0x00000423U -#define _reg_PI_DATA_BYTE_SWAP_SLICE1 0x00000424U -#define _reg_PI_DATA_BYTE_SWAP_SLICE2 0x00000425U -#define _reg_PI_DATA_BYTE_SWAP_SLICE3 0x00000426U -#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN 0x00000427U -#define _reg_PI_TDFI_CTRLUPD_MIN 0x00000428U -#define _reg_PI_TDFI_CTRLUPD_MAX_F0 0x00000429U -#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0 0x0000042aU -#define _reg_PI_TDFI_CTRLUPD_MAX_F1 0x0000042bU -#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1 0x0000042cU -#define _reg_PI_TDFI_CTRLUPD_MAX_F2 0x0000042dU -#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2 0x0000042eU -#define _reg_PI_UPDATE_ERROR_STATUS 0x0000042fU -#define _reg_PI_BIST_GO 0x00000430U -#define _reg_PI_BIST_RESULT 0x00000431U -#define _reg_PI_ADDR_SPACE 0x00000432U -#define _reg_PI_BIST_DATA_CHECK 0x00000433U -#define _reg_PI_BIST_ADDR_CHECK 0x00000434U -#define _reg_PI_BIST_START_ADDRESS_P0 0x00000435U -#define _reg_PI_BIST_START_ADDRESS_P1 0x00000436U -#define _reg_PI_BIST_DATA_MASK_P0 0x00000437U -#define _reg_PI_BIST_DATA_MASK_P1 0x00000438U -#define _reg_PI_BIST_ERR_COUNT 0x00000439U -#define _reg_PI_BIST_ERR_STOP 0x0000043aU -#define _reg_PI_BIST_ADDR_MASK_0_P0 0x0000043bU -#define _reg_PI_BIST_ADDR_MASK_0_P1 0x0000043cU -#define _reg_PI_BIST_ADDR_MASK_1_P0 0x0000043dU -#define _reg_PI_BIST_ADDR_MASK_1_P1 0x0000043eU -#define _reg_PI_BIST_ADDR_MASK_2_P0 0x0000043fU -#define _reg_PI_BIST_ADDR_MASK_2_P1 0x00000440U -#define _reg_PI_BIST_ADDR_MASK_3_P0 0x00000441U -#define _reg_PI_BIST_ADDR_MASK_3_P1 0x00000442U -#define _reg_PI_BIST_ADDR_MASK_4_P0 0x00000443U -#define _reg_PI_BIST_ADDR_MASK_4_P1 0x00000444U -#define _reg_PI_BIST_ADDR_MASK_5_P0 0x00000445U -#define _reg_PI_BIST_ADDR_MASK_5_P1 0x00000446U -#define _reg_PI_BIST_ADDR_MASK_6_P0 0x00000447U -#define _reg_PI_BIST_ADDR_MASK_6_P1 0x00000448U -#define _reg_PI_BIST_ADDR_MASK_7_P0 0x00000449U -#define _reg_PI_BIST_ADDR_MASK_7_P1 0x0000044aU -#define _reg_PI_BIST_ADDR_MASK_8_P0 0x0000044bU -#define _reg_PI_BIST_ADDR_MASK_8_P1 0x0000044cU -#define _reg_PI_BIST_ADDR_MASK_9_P0 0x0000044dU -#define _reg_PI_BIST_ADDR_MASK_9_P1 0x0000044eU -#define _reg_PI_BIST_MODE 0x0000044fU -#define _reg_PI_BIST_ADDR_MODE 0x00000450U -#define _reg_PI_BIST_PAT_MODE 0x00000451U -#define _reg_PI_BIST_USER_PAT_P0 0x00000452U -#define _reg_PI_BIST_USER_PAT_P1 0x00000453U -#define _reg_PI_BIST_USER_PAT_P2 0x00000454U -#define _reg_PI_BIST_USER_PAT_P3 0x00000455U -#define _reg_PI_BIST_PAT_NUM 0x00000456U -#define _reg_PI_BIST_STAGE_0 0x00000457U -#define _reg_PI_BIST_STAGE_1 0x00000458U -#define _reg_PI_BIST_STAGE_2 0x00000459U -#define _reg_PI_BIST_STAGE_3 0x0000045aU -#define _reg_PI_BIST_STAGE_4 0x0000045bU -#define _reg_PI_BIST_STAGE_5 0x0000045cU -#define _reg_PI_BIST_STAGE_6 0x0000045dU -#define _reg_PI_BIST_STAGE_7 0x0000045eU -#define _reg_PI_COL_DIFF 0x0000045fU -#define _reg_PI_SELF_REFRESH_EN 0x00000460U -#define _reg_PI_TXSR_F0 0x00000461U -#define _reg_PI_TXSR_F1 0x00000462U -#define _reg_PI_TXSR_F2 0x00000463U -#define _reg_PI_MONITOR_SRC_SEL_0 0x00000464U -#define _reg_PI_MONITOR_CAP_SEL_0 0x00000465U -#define _reg_PI_MONITOR_0 0x00000466U -#define _reg_PI_MONITOR_SRC_SEL_1 0x00000467U -#define _reg_PI_MONITOR_CAP_SEL_1 0x00000468U -#define _reg_PI_MONITOR_1 0x00000469U -#define _reg_PI_MONITOR_SRC_SEL_2 0x0000046aU -#define _reg_PI_MONITOR_CAP_SEL_2 0x0000046bU -#define _reg_PI_MONITOR_2 0x0000046cU -#define _reg_PI_MONITOR_SRC_SEL_3 0x0000046dU -#define _reg_PI_MONITOR_CAP_SEL_3 0x0000046eU -#define _reg_PI_MONITOR_3 0x0000046fU -#define _reg_PI_MONITOR_SRC_SEL_4 0x00000470U -#define _reg_PI_MONITOR_CAP_SEL_4 0x00000471U -#define _reg_PI_MONITOR_4 0x00000472U -#define _reg_PI_MONITOR_SRC_SEL_5 0x00000473U -#define _reg_PI_MONITOR_CAP_SEL_5 0x00000474U -#define _reg_PI_MONITOR_5 0x00000475U -#define _reg_PI_MONITOR_SRC_SEL_6 0x00000476U -#define _reg_PI_MONITOR_CAP_SEL_6 0x00000477U -#define _reg_PI_MONITOR_6 0x00000478U -#define _reg_PI_MONITOR_SRC_SEL_7 0x00000479U -#define _reg_PI_MONITOR_CAP_SEL_7 0x0000047aU -#define _reg_PI_MONITOR_7 0x0000047bU -#define _reg_PI_MONITOR_STROBE 0x0000047cU -#define _reg_PI_DLL_LOCK 0x0000047dU -#define _reg_PI_FREQ_NUMBER_STATUS 0x0000047eU -#define _reg_RESERVED_R24 0x0000047fU -#define _reg_PI_PHYMSTR_TYPE 0x00000480U -#define _reg_PI_POWER_REDUC_EN 0x00000481U -#define _reg_RESERVED_R25 0x00000482U -#define _reg_RESERVED_R26 0x00000483U -#define _reg_RESERVED_R27 0x00000484U -#define _reg_RESERVED_R28 0x00000485U -#define _reg_RESERVED_R29 0x00000486U -#define _reg_RESERVED_R30 0x00000487U -#define _reg_RESERVED_R31 0x00000488U -#define _reg_RESERVED_R32 0x00000489U -#define _reg_RESERVED_R33 0x0000048aU -#define _reg_RESERVED_R34 0x0000048bU -#define _reg_RESERVED_R35 0x0000048cU -#define _reg_RESERVED_R36 0x0000048dU -#define _reg_RESERVED_R37 0x0000048eU -#define _reg_RESERVED_R38 0x0000048fU -#define _reg_RESERVED_R39 0x00000490U -#define _reg_PI_WRLVL_MAX_STROBE_PEND 0x00000491U -#define _reg_PI_TSDO_F0 0x00000492U -#define _reg_PI_TSDO_F1 0x00000493U -#define _reg_PI_TSDO_F2 0x00000494U - -#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffff) -#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xff) -#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xff) - -static const uint32_t DDR_REGDEF_TBL[4][1173] = { - { -/*0000*/ 0xffffffffU, -/*0001*/ 0xffffffffU, -/*0002*/ 0x000b0400U, -/*0003*/ 0xffffffffU, -/*0004*/ 0xffffffffU, -/*0005*/ 0x10010400U, -/*0006*/ 0x18050400U, -/*0007*/ 0x00050401U, -/*0008*/ 0x08050401U, -/*0009*/ 0x10050401U, -/*000a*/ 0x18050401U, -/*000b*/ 0x00050402U, -/*000c*/ 0x08050402U, -/*000d*/ 0x10050402U, -/*000e*/ 0x18050402U, -/*000f*/ 0x00040403U, -/*0010*/ 0x08030403U, -/*0011*/ 0x00180404U, -/*0012*/ 0x18030404U, -/*0013*/ 0x00180405U, -/*0014*/ 0x18020405U, -/*0015*/ 0x00010406U, -/*0016*/ 0x08020406U, -/*0017*/ 0x10010406U, -/*0018*/ 0x18010406U, -/*0019*/ 0x00020407U, -/*001a*/ 0x08040407U, -/*001b*/ 0x10040407U, -/*001c*/ 0x18040407U, -/*001d*/ 0x000a0408U, -/*001e*/ 0x10040408U, -/*001f*/ 0xffffffffU, -/*0020*/ 0xffffffffU, -/*0021*/ 0x18070408U, -/*0022*/ 0xffffffffU, -/*0023*/ 0xffffffffU, -/*0024*/ 0xffffffffU, -/*0025*/ 0xffffffffU, -/*0026*/ 0xffffffffU, -/*0027*/ 0xffffffffU, -/*0028*/ 0x000a0409U, -/*0029*/ 0x10040409U, -/*002a*/ 0x18010409U, -/*002b*/ 0x0001040aU, -/*002c*/ 0x0802040aU, -/*002d*/ 0x1009040aU, -/*002e*/ 0x0009040bU, -/*002f*/ 0x1002040bU, -/*0030*/ 0x0020040cU, -/*0031*/ 0xffffffffU, -/*0032*/ 0x0001040dU, -/*0033*/ 0xffffffffU, -/*0034*/ 0xffffffffU, -/*0035*/ 0xffffffffU, -/*0036*/ 0xffffffffU, -/*0037*/ 0x0020040eU, -/*0038*/ 0x0020040fU, -/*0039*/ 0x00200410U, -/*003a*/ 0x00200411U, -/*003b*/ 0x00030412U, -/*003c*/ 0x08010412U, -/*003d*/ 0x10030412U, -/*003e*/ 0x18030412U, -/*003f*/ 0x00040413U, -/*0040*/ 0x08040413U, -/*0041*/ 0x10040413U, -/*0042*/ 0x18040413U, -/*0043*/ 0x00010414U, -/*0044*/ 0x08010414U, -/*0045*/ 0x10060414U, -/*0046*/ 0x18040414U, -/*0047*/ 0xffffffffU, -/*0048*/ 0x00060415U, -/*0049*/ 0x08040415U, -/*004a*/ 0x10060415U, -/*004b*/ 0x18040415U, -/*004c*/ 0x00020416U, -/*004d*/ 0x08050416U, -/*004e*/ 0x10080416U, -/*004f*/ 0x00200417U, -/*0050*/ 0x00060418U, -/*0051*/ 0x08030418U, -/*0052*/ 0x100b0418U, -/*0053*/ 0x00040419U, -/*0054*/ 0x08040419U, -/*0055*/ 0x10040419U, -/*0056*/ 0xffffffffU, -/*0057*/ 0x18010419U, -/*0058*/ 0x0009041aU, -/*0059*/ 0x0020041bU, -/*005a*/ 0x0020041cU, -/*005b*/ 0x0020041dU, -/*005c*/ 0x0020041eU, -/*005d*/ 0x0010041fU, -/*005e*/ 0x00200420U, -/*005f*/ 0x00010421U, -/*0060*/ 0x08060421U, -/*0061*/ 0x10080421U, -/*0062*/ 0x00200422U, -/*0063*/ 0xffffffffU, -/*0064*/ 0x000a0423U, -/*0065*/ 0x10060423U, -/*0066*/ 0x18070423U, -/*0067*/ 0x00080424U, -/*0068*/ 0x08080424U, -/*0069*/ 0x100a0424U, -/*006a*/ 0x00070425U, -/*006b*/ 0x08080425U, -/*006c*/ 0x10080425U, -/*006d*/ 0x18030425U, -/*006e*/ 0x000a0426U, -/*006f*/ 0x100a0426U, -/*0070*/ 0x00110427U, -/*0071*/ 0x00090428U, -/*0072*/ 0x10090428U, -/*0073*/ 0x00100429U, -/*0074*/ 0x100e0429U, -/*0075*/ 0x000e042aU, -/*0076*/ 0x100c042aU, -/*0077*/ 0x000a042bU, -/*0078*/ 0x100a042bU, -/*0079*/ 0x0002042cU, -/*007a*/ 0x0020042dU, -/*007b*/ 0x000b042eU, -/*007c*/ 0x100b042eU, -/*007d*/ 0x0020042fU, -/*007e*/ 0x00120430U, -/*007f*/ 0x00200431U, -/*0080*/ 0x00200432U, -/*0081*/ 0xffffffffU, -/*0082*/ 0xffffffffU, -/*0083*/ 0x00010433U, -/*0084*/ 0x08010433U, -/*0085*/ 0x10080433U, -/*0086*/ 0x000c0434U, -/*0087*/ 0x100c0434U, -/*0088*/ 0x000c0435U, -/*0089*/ 0x100c0435U, -/*008a*/ 0x000c0436U, -/*008b*/ 0x100c0436U, -/*008c*/ 0x000c0437U, -/*008d*/ 0x100c0437U, -/*008e*/ 0x000c0438U, -/*008f*/ 0x100c0438U, -/*0090*/ 0x000c0439U, -/*0091*/ 0x100b0439U, -/*0092*/ 0xffffffffU, -/*0093*/ 0xffffffffU, -/*0094*/ 0x000b043aU, -/*0095*/ 0x100b043aU, -/*0096*/ 0x000b043bU, -/*0097*/ 0x100b043bU, -/*0098*/ 0x000b043cU, -/*0099*/ 0x100b043cU, -/*009a*/ 0x000b043dU, -/*009b*/ 0x100b043dU, -/*009c*/ 0x000b043eU, -/*009d*/ 0x100a043eU, -/*009e*/ 0xffffffffU, -/*009f*/ 0x000a043fU, -/*00a0*/ 0x100a043fU, -/*00a1*/ 0x000a0440U, -/*00a2*/ 0x100a0440U, -/*00a3*/ 0x000a0441U, -/*00a4*/ 0x100a0441U, -/*00a5*/ 0x000a0442U, -/*00a6*/ 0x100a0442U, -/*00a7*/ 0xffffffffU, -/*00a8*/ 0x000a0443U, -/*00a9*/ 0x100a0443U, -/*00aa*/ 0x000a0444U, -/*00ab*/ 0x100a0444U, -/*00ac*/ 0x000a0445U, -/*00ad*/ 0x100a0445U, -/*00ae*/ 0x000a0446U, -/*00af*/ 0x100a0446U, -/*00b0*/ 0x000a0447U, -/*00b1*/ 0x100a0447U, -/*00b2*/ 0x000a0448U, -/*00b3*/ 0x100a0448U, -/*00b4*/ 0x000a0449U, -/*00b5*/ 0x100a0449U, -/*00b6*/ 0x000a044aU, -/*00b7*/ 0x100a044aU, -/*00b8*/ 0x000a044bU, -/*00b9*/ 0x100a044bU, -/*00ba*/ 0x000a044cU, -/*00bb*/ 0x1004044cU, -/*00bc*/ 0x1803044cU, -/*00bd*/ 0x000a044dU, -/*00be*/ 0x100a044dU, -/*00bf*/ 0x0001044eU, -/*00c0*/ 0x080a044eU, -/*00c1*/ 0x1804044eU, -/*00c2*/ 0x000b044fU, -/*00c3*/ 0x100a044fU, -/*00c4*/ 0xffffffffU, -/*00c5*/ 0x00080450U, -/*00c6*/ 0x08080450U, -/*00c7*/ 0x10080450U, -/*00c8*/ 0x18080450U, -/*00c9*/ 0x00080451U, -/*00ca*/ 0xffffffffU, -/*00cb*/ 0x08080451U, -/*00cc*/ 0x10010451U, -/*00cd*/ 0x18080451U, -/*00ce*/ 0x00080452U, -/*00cf*/ 0x08020452U, -/*00d0*/ 0x10020452U, -/*00d1*/ 0x18040452U, -/*00d2*/ 0x00040453U, -/*00d3*/ 0xffffffffU, -/*00d4*/ 0x08040453U, -/*00d5*/ 0x100a0453U, -/*00d6*/ 0x00060454U, -/*00d7*/ 0x08080454U, -/*00d8*/ 0xffffffffU, -/*00d9*/ 0x10040454U, -/*00da*/ 0x18040454U, -/*00db*/ 0x00050455U, -/*00dc*/ 0x08040455U, -/*00dd*/ 0x10050455U, -/*00de*/ 0x000a0456U, -/*00df*/ 0x100a0456U, -/*00e0*/ 0x00080457U, -/*00e1*/ 0xffffffffU, -/*00e2*/ 0x08040457U, -/*00e3*/ 0xffffffffU, -/*00e4*/ 0xffffffffU, -/*00e5*/ 0x00050600U, -/*00e6*/ 0x08050600U, -/*00e7*/ 0x10050600U, -/*00e8*/ 0x18050600U, -/*00e9*/ 0x00050601U, -/*00ea*/ 0x08050601U, -/*00eb*/ 0x100b0601U, -/*00ec*/ 0x00010602U, -/*00ed*/ 0x08030602U, -/*00ee*/ 0x00200603U, -/*00ef*/ 0xffffffffU, -/*00f0*/ 0x00030604U, -/*00f1*/ 0x080a0604U, -/*00f2*/ 0xffffffffU, -/*00f3*/ 0xffffffffU, -/*00f4*/ 0x18030604U, -/*00f5*/ 0x00030605U, -/*00f6*/ 0x08010605U, -/*00f7*/ 0x10010605U, -/*00f8*/ 0x18060605U, -/*00f9*/ 0xffffffffU, -/*00fa*/ 0xffffffffU, -/*00fb*/ 0xffffffffU, -/*00fc*/ 0x00020606U, -/*00fd*/ 0x08030606U, -/*00fe*/ 0x10010606U, -/*00ff*/ 0x000f0607U, -/*0100*/ 0x00200608U, -/*0101*/ 0x00200609U, -/*0102*/ 0x000b060aU, -/*0103*/ 0x100b060aU, -/*0104*/ 0x000b060bU, -/*0105*/ 0xffffffffU, -/*0106*/ 0xffffffffU, -/*0107*/ 0x0018060cU, -/*0108*/ 0x0018060dU, -/*0109*/ 0x0018060eU, -/*010a*/ 0x0018060fU, -/*010b*/ 0x1804060fU, -/*010c*/ 0x00050610U, -/*010d*/ 0x08020610U, -/*010e*/ 0x10040610U, -/*010f*/ 0x18040610U, -/*0110*/ 0x00010611U, -/*0111*/ 0x08010611U, -/*0112*/ 0x10010611U, -/*0113*/ 0x18030611U, -/*0114*/ 0x00200612U, -/*0115*/ 0x00200613U, -/*0116*/ 0x00010614U, -/*0117*/ 0x08140614U, -/*0118*/ 0x00140615U, -/*0119*/ 0x00140616U, -/*011a*/ 0x00140617U, -/*011b*/ 0x00140618U, -/*011c*/ 0x00140619U, -/*011d*/ 0x0014061aU, -/*011e*/ 0x0014061bU, -/*011f*/ 0x0018061cU, -/*0120*/ 0x000a061dU, -/*0121*/ 0x1006061dU, -/*0122*/ 0x1806061dU, -/*0123*/ 0x0006061eU, -/*0124*/ 0xffffffffU, -/*0125*/ 0xffffffffU, -/*0126*/ 0x0008061fU, -/*0127*/ 0x080b061fU, -/*0128*/ 0x000b0620U, -/*0129*/ 0x100b0620U, -/*012a*/ 0x000b0621U, -/*012b*/ 0x100b0621U, -/*012c*/ 0x000b0622U, -/*012d*/ 0x10040622U, -/*012e*/ 0x000a0623U, -/*012f*/ 0x10060623U, -/*0130*/ 0x18080623U, -/*0131*/ 0xffffffffU, -/*0132*/ 0x00040624U, -/*0133*/ 0xffffffffU, -/*0134*/ 0xffffffffU, -/*0135*/ 0x00010700U, -/*0136*/ 0x08020700U, -/*0137*/ 0x10050700U, -/*0138*/ 0x18050700U, -/*0139*/ 0x00050701U, -/*013a*/ 0x08050701U, -/*013b*/ 0x100b0701U, -/*013c*/ 0x00050702U, -/*013d*/ 0x08010702U, -/*013e*/ 0x10010702U, -/*013f*/ 0xffffffffU, -/*0140*/ 0x18010702U, -/*0141*/ 0x00010703U, -/*0142*/ 0x08040703U, -/*0143*/ 0x100b0703U, -/*0144*/ 0x000b0704U, -/*0145*/ 0xffffffffU, -/*0146*/ 0x10040704U, -/*0147*/ 0x000b0705U, -/*0148*/ 0x10040705U, -/*0149*/ 0x18010705U, -/*014a*/ 0x00010706U, -/*014b*/ 0x08010706U, -/*014c*/ 0x00200707U, -/*014d*/ 0x00200708U, -/*014e*/ 0x00080709U, -/*014f*/ 0x080a0709U, -/*0150*/ 0x18050709U, -/*0151*/ 0x000a070aU, -/*0152*/ 0x1003070aU, -/*0153*/ 0x1803070aU, -/*0154*/ 0x0001070bU, -/*0155*/ 0x0802070bU, -/*0156*/ 0x1001070bU, -/*0157*/ 0x1801070bU, -/*0158*/ 0x0001070cU, -/*0159*/ 0x0802070cU, -/*015a*/ 0xffffffffU, -/*015b*/ 0xffffffffU, -/*015c*/ 0xffffffffU, -/*015d*/ 0xffffffffU, -/*015e*/ 0xffffffffU, -/*015f*/ 0xffffffffU, -/*0160*/ 0xffffffffU, -/*0161*/ 0xffffffffU, -/*0162*/ 0xffffffffU, -/*0163*/ 0xffffffffU, -/*0164*/ 0xffffffffU, -/*0165*/ 0xffffffffU, -/*0166*/ 0x1001070cU, -/*0167*/ 0x1801070cU, -/*0168*/ 0x000d070dU, -/*0169*/ 0xffffffffU, -/*016a*/ 0xffffffffU, -/*016b*/ 0x0005070eU, -/*016c*/ 0x0001070fU, -/*016d*/ 0x080e070fU, -/*016e*/ 0x000e0710U, -/*016f*/ 0x100e0710U, -/*0170*/ 0x000e0711U, -/*0171*/ 0x100e0711U, -/*0172*/ 0x00040712U, -/*0173*/ 0xffffffffU, -/*0174*/ 0xffffffffU, -/*0175*/ 0xffffffffU, -/*0176*/ 0xffffffffU, -/*0177*/ 0x080b0712U, -/*0178*/ 0x000b0713U, -/*0179*/ 0x100b0713U, -/*017a*/ 0x000b0714U, -/*017b*/ 0xffffffffU, -/*017c*/ 0xffffffffU, -/*017d*/ 0xffffffffU, -/*017e*/ 0xffffffffU, -/*017f*/ 0x000d0715U, -/*0180*/ 0xffffffffU, -/*0181*/ 0xffffffffU, -/*0182*/ 0x10100715U, -/*0183*/ 0x00080716U, -/*0184*/ 0xffffffffU, -/*0185*/ 0x08100716U, -/*0186*/ 0x00100717U, -/*0187*/ 0x10100717U, -/*0188*/ 0x00100718U, -/*0189*/ 0x10100718U, -/*018a*/ 0x00030719U, -/*018b*/ 0x08040719U, -/*018c*/ 0x10010719U, -/*018d*/ 0x18040719U, -/*018e*/ 0xffffffffU, -/*018f*/ 0xffffffffU, -/*0190*/ 0x0001071aU, -/*0191*/ 0x0812071aU, -/*0192*/ 0x000a071bU, -/*0193*/ 0x100c071bU, -/*0194*/ 0x0012071cU, -/*0195*/ 0x0014071dU, -/*0196*/ 0x0012071eU, -/*0197*/ 0x0011071fU, -/*0198*/ 0x00110720U, -/*0199*/ 0x00120721U, -/*019a*/ 0x00120722U, -/*019b*/ 0x00120723U, -/*019c*/ 0x00120724U, -/*019d*/ 0x00120725U, -/*019e*/ 0x00120726U, -/*019f*/ 0x00120727U, -/*01a0*/ 0x00120728U, -/*01a1*/ 0xffffffffU, -/*01a2*/ 0xffffffffU, -/*01a3*/ 0x00190729U, -/*01a4*/ 0x0019072aU, -/*01a5*/ 0x0020072bU, -/*01a6*/ 0x0017072cU, -/*01a7*/ 0x1808072cU, -/*01a8*/ 0x0001072dU, -/*01a9*/ 0x0801072dU, -/*01aa*/ 0x0020072eU, -/*01ab*/ 0x0008072fU, -/*01ac*/ 0xffffffffU, -/*01ad*/ 0x0803072fU, -/*01ae*/ 0x00180730U, -/*01af*/ 0x00180731U, -/*01b0*/ 0xffffffffU, -/*01b1*/ 0xffffffffU, -/*01b2*/ 0xffffffffU, -/*01b3*/ 0xffffffffU, -/*01b4*/ 0xffffffffU, -/*01b5*/ 0xffffffffU, -/*01b6*/ 0xffffffffU, -/*01b7*/ 0xffffffffU, -/*01b8*/ 0xffffffffU, -/*01b9*/ 0xffffffffU, -/*01ba*/ 0xffffffffU, -/*01bb*/ 0xffffffffU, -/*01bc*/ 0xffffffffU, -/*01bd*/ 0xffffffffU, -/*01be*/ 0xffffffffU, -/*01bf*/ 0x00100732U, -/*01c0*/ 0x10010732U, -/*01c1*/ 0x18010732U, -/*01c2*/ 0x00050733U, -/*01c3*/ 0x00200734U, -/*01c4*/ 0x00090735U, -/*01c5*/ 0xffffffffU, -/*01c6*/ 0xffffffffU, -/*01c7*/ 0x00200736U, -/*01c8*/ 0x00040737U, -/*01c9*/ 0x08100737U, -/*01ca*/ 0x18060737U, -/*01cb*/ 0x00100738U, -/*01cc*/ 0xffffffffU, -/*01cd*/ 0xffffffffU, -/*01ce*/ 0xffffffffU, -/*01cf*/ 0xffffffffU, -/*01d0*/ 0xffffffffU, -/*01d1*/ 0xffffffffU, -/*01d2*/ 0xffffffffU, -/*01d3*/ 0xffffffffU, -/*01d4*/ 0x00200739U, -/*01d5*/ 0x000b073aU, -/*01d6*/ 0xffffffffU, -/*01d7*/ 0xffffffffU, -/*01d8*/ 0xffffffffU, -/*01d9*/ 0xffffffffU, -/*01da*/ 0xffffffffU, -/*01db*/ 0xffffffffU, -/*01dc*/ 0xffffffffU, -/*01dd*/ 0xffffffffU, -/*01de*/ 0x00010200U, -/*01df*/ 0x08040200U, -/*01e0*/ 0x10100200U, -/*01e1*/ 0x00010201U, -/*01e2*/ 0x08010201U, -/*01e3*/ 0xffffffffU, -/*01e4*/ 0xffffffffU, -/*01e5*/ 0x10100201U, -/*01e6*/ 0xffffffffU, -/*01e7*/ 0xffffffffU, -/*01e8*/ 0xffffffffU, -/*01e9*/ 0xffffffffU, -/*01ea*/ 0xffffffffU, -/*01eb*/ 0xffffffffU, -/*01ec*/ 0xffffffffU, -/*01ed*/ 0xffffffffU, -/*01ee*/ 0xffffffffU, -/*01ef*/ 0x00200202U, -/*01f0*/ 0x00100203U, -/*01f1*/ 0x00200204U, -/*01f2*/ 0x00100205U, -/*01f3*/ 0x00200206U, -/*01f4*/ 0x00100207U, -/*01f5*/ 0x10100207U, -/*01f6*/ 0x00200208U, -/*01f7*/ 0x00200209U, -/*01f8*/ 0x0020020aU, -/*01f9*/ 0x0020020bU, -/*01fa*/ 0x0010020cU, -/*01fb*/ 0x0020020dU, -/*01fc*/ 0x0020020eU, -/*01fd*/ 0x0020020fU, -/*01fe*/ 0x00200210U, -/*01ff*/ 0x00100211U, -/*0200*/ 0x00200212U, -/*0201*/ 0x00200213U, -/*0202*/ 0x00200214U, -/*0203*/ 0x00200215U, -/*0204*/ 0x00090216U, -/*0205*/ 0x10010216U, -/*0206*/ 0x00200217U, -/*0207*/ 0x00050218U, -/*0208*/ 0x08010218U, -/*0209*/ 0x10080218U, -/*020a*/ 0x18080218U, -/*020b*/ 0x001c0219U, -/*020c*/ 0x001c021aU, -/*020d*/ 0x001c021bU, -/*020e*/ 0x001c021cU, -/*020f*/ 0x001c021dU, -/*0210*/ 0x001c021eU, -/*0211*/ 0x001c021fU, -/*0212*/ 0x001c0220U, -/*0213*/ 0x001c0221U, -/*0214*/ 0x001c0222U, -/*0215*/ 0x001c0223U, -/*0216*/ 0x001c0224U, -/*0217*/ 0x001c0225U, -/*0218*/ 0x001c0226U, -/*0219*/ 0x001c0227U, -/*021a*/ 0x001c0228U, -/*021b*/ 0x00010229U, -/*021c*/ 0x08010229U, -/*021d*/ 0x10010229U, -/*021e*/ 0x18040229U, -/*021f*/ 0x0008022aU, -/*0220*/ 0x0808022aU, -/*0221*/ 0x1008022aU, -/*0222*/ 0x1804022aU, -/*0223*/ 0x0006022bU, -/*0224*/ 0xffffffffU, -/*0225*/ 0x0807022bU, -/*0226*/ 0x1006022bU, -/*0227*/ 0xffffffffU, -/*0228*/ 0x1807022bU, -/*0229*/ 0x0006022cU, -/*022a*/ 0xffffffffU, -/*022b*/ 0x0807022cU, -/*022c*/ 0x1002022cU, -/*022d*/ 0x1801022cU, -/*022e*/ 0xffffffffU, -/*022f*/ 0x000a022dU, -/*0230*/ 0x1010022dU, -/*0231*/ 0x000a022eU, -/*0232*/ 0x1010022eU, -/*0233*/ 0x000a022fU, -/*0234*/ 0x1010022fU, -/*0235*/ 0xffffffffU, -/*0236*/ 0x00100230U, -/*0237*/ 0xffffffffU, -/*0238*/ 0xffffffffU, -/*0239*/ 0x10010230U, -/*023a*/ 0x18010230U, -/*023b*/ 0x00010231U, -/*023c*/ 0x08010231U, -/*023d*/ 0x10010231U, -/*023e*/ 0x18010231U, -/*023f*/ 0x00020232U, -/*0240*/ 0x08020232U, -/*0241*/ 0x10020232U, -/*0242*/ 0x18020232U, -/*0243*/ 0x00020233U, -/*0244*/ 0x08030233U, -/*0245*/ 0x10010233U, -/*0246*/ 0x18010233U, -/*0247*/ 0x00010234U, -/*0248*/ 0x08010234U, -/*0249*/ 0xffffffffU, -/*024a*/ 0x10020234U, -/*024b*/ 0x18010234U, -/*024c*/ 0x00010235U, -/*024d*/ 0xffffffffU, -/*024e*/ 0x08020235U, -/*024f*/ 0x10010235U, -/*0250*/ 0x18010235U, -/*0251*/ 0xffffffffU, -/*0252*/ 0x00020236U, -/*0253*/ 0x08010236U, -/*0254*/ 0x10010236U, -/*0255*/ 0xffffffffU, -/*0256*/ 0x18020236U, -/*0257*/ 0x00070237U, -/*0258*/ 0x08010237U, -/*0259*/ 0x10010237U, -/*025a*/ 0x18010237U, -/*025b*/ 0x00010238U, -/*025c*/ 0x08010238U, -/*025d*/ 0x10010238U, -/*025e*/ 0xffffffffU, -/*025f*/ 0x18010238U, -/*0260*/ 0x00040239U, -/*0261*/ 0x08040239U, -/*0262*/ 0x10040239U, -/*0263*/ 0x18010239U, -/*0264*/ 0x0002023aU, -/*0265*/ 0x0806023aU, -/*0266*/ 0x1006023aU, -/*0267*/ 0xffffffffU, -/*0268*/ 0xffffffffU, -/*0269*/ 0xffffffffU, -/*026a*/ 0x1802023aU, -/*026b*/ 0x0010023bU, -/*026c*/ 0x1001023bU, -/*026d*/ 0x1801023bU, -/*026e*/ 0xffffffffU, -/*026f*/ 0x0004023cU, -/*0270*/ 0x0801023cU, -/*0271*/ 0x1004023cU, -/*0272*/ 0x1802023cU, -/*0273*/ 0x0008023dU, -/*0274*/ 0xffffffffU, -/*0275*/ 0xffffffffU, -/*0276*/ 0xffffffffU, -/*0277*/ 0x080a023dU, -/*0278*/ 0x0020023eU, -/*0279*/ 0x0020023fU, -/*027a*/ 0x00050240U, -/*027b*/ 0x08010240U, -/*027c*/ 0x10050240U, -/*027d*/ 0x18080240U, -/*027e*/ 0x00010241U, -/*027f*/ 0x08080241U, -/*0280*/ 0x10010241U, -/*0281*/ 0x18080241U, -/*0282*/ 0x00010242U, -/*0283*/ 0x08040242U, -/*0284*/ 0x10040242U, -/*0285*/ 0x18040242U, -/*0286*/ 0x00040243U, -/*0287*/ 0x08040243U, -/*0288*/ 0x10040243U, -/*0289*/ 0x18040243U, -/*028a*/ 0x00040244U, -/*028b*/ 0x08040244U, -/*028c*/ 0x10040244U, -/*028d*/ 0x18010244U, -/*028e*/ 0x00040245U, -/*028f*/ 0x08040245U, -/*0290*/ 0x10040245U, -/*0291*/ 0x18040245U, -/*0292*/ 0x00040246U, -/*0293*/ 0x08040246U, -/*0294*/ 0x10060246U, -/*0295*/ 0x18060246U, -/*0296*/ 0x00060247U, -/*0297*/ 0x08060247U, -/*0298*/ 0x10060247U, -/*0299*/ 0x18060247U, -/*029a*/ 0xffffffffU, -/*029b*/ 0x00010248U, -/*029c*/ 0x08010248U, -/*029d*/ 0x10020248U, -/*029e*/ 0xffffffffU, -/*029f*/ 0xffffffffU, -/*02a0*/ 0xffffffffU, -/*02a1*/ 0xffffffffU, -/*02a2*/ 0xffffffffU, -/*02a3*/ 0xffffffffU, -/*02a4*/ 0xffffffffU, -/*02a5*/ 0xffffffffU, -/*02a6*/ 0x18040248U, -/*02a7*/ 0x00040249U, -/*02a8*/ 0x08010249U, -/*02a9*/ 0x10010249U, -/*02aa*/ 0xffffffffU, -/*02ab*/ 0x18010249U, -/*02ac*/ 0x0001024aU, -/*02ad*/ 0xffffffffU, -/*02ae*/ 0x0801024aU, -/*02af*/ 0x1001024aU, -/*02b0*/ 0x1801024aU, -/*02b1*/ 0x0004024bU, -/*02b2*/ 0x0804024bU, -/*02b3*/ 0x100a024bU, -/*02b4*/ 0x0020024cU, -/*02b5*/ 0x0004024dU, -/*02b6*/ 0x0808024dU, -/*02b7*/ 0xffffffffU, -/*02b8*/ 0xffffffffU, -/*02b9*/ 0xffffffffU, -/*02ba*/ 0xffffffffU, -/*02bb*/ 0xffffffffU, -/*02bc*/ 0xffffffffU, -/*02bd*/ 0x1002024dU, -/*02be*/ 0x1802024dU, -/*02bf*/ 0x0020024eU, -/*02c0*/ 0x0002024fU, -/*02c1*/ 0x0810024fU, -/*02c2*/ 0x00100250U, -/*02c3*/ 0x10040250U, -/*02c4*/ 0x18040250U, -/*02c5*/ 0x00050251U, -/*02c6*/ 0x08050251U, -/*02c7*/ 0xffffffffU, -/*02c8*/ 0xffffffffU, -/*02c9*/ 0xffffffffU, -/*02ca*/ 0xffffffffU, -/*02cb*/ 0x10010251U, -/*02cc*/ 0x18010251U, -/*02cd*/ 0x00070252U, -/*02ce*/ 0x08070252U, -/*02cf*/ 0x10070252U, -/*02d0*/ 0x18070252U, -/*02d1*/ 0x00070253U, -/*02d2*/ 0x08070253U, -/*02d3*/ 0x10070253U, -/*02d4*/ 0x18070253U, -/*02d5*/ 0x00070254U, -/*02d6*/ 0x08070254U, -/*02d7*/ 0x10070254U, -/*02d8*/ 0xffffffffU, -/*02d9*/ 0xffffffffU, -/*02da*/ 0xffffffffU, -/*02db*/ 0xffffffffU, -/*02dc*/ 0xffffffffU, -/*02dd*/ 0xffffffffU, -/*02de*/ 0x18030254U, -/*02df*/ 0x00010255U, -/*02e0*/ 0x08020255U, -/*02e1*/ 0x10010255U, -/*02e2*/ 0x18040255U, -/*02e3*/ 0x00020256U, -/*02e4*/ 0x08010256U, -/*02e5*/ 0x10010256U, -/*02e6*/ 0xffffffffU, -/*02e7*/ 0x18010256U, -/*02e8*/ 0x00040257U, -/*02e9*/ 0x08080257U, -/*02ea*/ 0x100a0257U, -/*02eb*/ 0x000a0258U, -/*02ec*/ 0x100a0258U, -/*02ed*/ 0x000a0259U, -/*02ee*/ 0x100a0259U, -/*02ef*/ 0x000a025aU, -/*02f0*/ 0x0020025bU, -/*02f1*/ 0x0020025cU, -/*02f2*/ 0x0001025dU, -/*02f3*/ 0xffffffffU, -/*02f4*/ 0xffffffffU, -/*02f5*/ 0xffffffffU, -/*02f6*/ 0x0802025dU, -/*02f7*/ 0x1002025dU, -/*02f8*/ 0x0010025eU, -/*02f9*/ 0x1005025eU, -/*02fa*/ 0x1806025eU, -/*02fb*/ 0x0005025fU, -/*02fc*/ 0x0805025fU, -/*02fd*/ 0x100e025fU, -/*02fe*/ 0x00050260U, -/*02ff*/ 0x080e0260U, -/*0300*/ 0x18050260U, -/*0301*/ 0x000e0261U, -/*0302*/ 0x10050261U, -/*0303*/ 0x18010261U, -/*0304*/ 0x00050262U, -/*0305*/ 0x08050262U, -/*0306*/ 0x100a0262U, -/*0307*/ 0x000a0263U, -/*0308*/ 0x10050263U, -/*0309*/ 0x18050263U, -/*030a*/ 0x000a0264U, -/*030b*/ 0x100a0264U, -/*030c*/ 0x00050265U, -/*030d*/ 0x08050265U, -/*030e*/ 0x100a0265U, -/*030f*/ 0x000a0266U, -/*0310*/ 0xffffffffU, -/*0311*/ 0xffffffffU, -/*0312*/ 0xffffffffU, -/*0313*/ 0xffffffffU, -/*0314*/ 0xffffffffU, -/*0315*/ 0xffffffffU, -/*0316*/ 0x10070266U, -/*0317*/ 0x18070266U, -/*0318*/ 0x00040267U, -/*0319*/ 0x08040267U, -/*031a*/ 0xffffffffU, -/*031b*/ 0xffffffffU, -/*031c*/ 0xffffffffU, -/*031d*/ 0x10040267U, -/*031e*/ 0x18080267U, -/*031f*/ 0x00080268U, -/*0320*/ 0x08040268U, -/*0321*/ 0xffffffffU, -/*0322*/ 0xffffffffU, -/*0323*/ 0xffffffffU, -/*0324*/ 0x10040268U, -/*0325*/ 0xffffffffU, -/*0326*/ 0xffffffffU, -/*0327*/ 0xffffffffU, -/*0328*/ 0x18040268U, -/*0329*/ 0xffffffffU, -/*032a*/ 0xffffffffU, -/*032b*/ 0xffffffffU, -/*032c*/ 0x00040269U, -/*032d*/ 0x08050269U, -/*032e*/ 0x10070269U, -/*032f*/ 0x18080269U, -/*0330*/ 0x0010026aU, -/*0331*/ 0x1008026aU, -/*0332*/ 0x0010026bU, -/*0333*/ 0x1008026bU, -/*0334*/ 0x0010026cU, -/*0335*/ 0x1008026cU, -/*0336*/ 0x1808026cU, -/*0337*/ 0x0001026dU, -/*0338*/ 0x0801026dU, -/*0339*/ 0x1006026dU, -/*033a*/ 0x1806026dU, -/*033b*/ 0x0006026eU, -/*033c*/ 0xffffffffU, -/*033d*/ 0x0801026eU, -/*033e*/ 0x1003026eU, -/*033f*/ 0xffffffffU, -/*0340*/ 0xffffffffU, -/*0341*/ 0xffffffffU, -/*0342*/ 0x000a026fU, -/*0343*/ 0x100a026fU, -/*0344*/ 0x00040270U, -/*0345*/ 0x08010270U, -/*0346*/ 0x10040270U, -/*0347*/ 0xffffffffU, -/*0348*/ 0xffffffffU, -/*0349*/ 0xffffffffU, -/*034a*/ 0xffffffffU, -/*034b*/ 0xffffffffU, -/*034c*/ 0xffffffffU, -/*034d*/ 0x18070270U, -/*034e*/ 0x00070271U, -/*034f*/ 0x08050271U, -/*0350*/ 0x10050271U, -/*0351*/ 0xffffffffU, -/*0352*/ 0xffffffffU, -/*0353*/ 0xffffffffU, -/*0354*/ 0x18040271U, -/*0355*/ 0x00010272U, -/*0356*/ 0x08010272U, -/*0357*/ 0x10020272U, -/*0358*/ 0x18080272U, -/*0359*/ 0x00200273U, -/*035a*/ 0x00200274U, -/*035b*/ 0x00100275U, -/*035c*/ 0xffffffffU, -/*035d*/ 0xffffffffU, -/*035e*/ 0xffffffffU, -/*035f*/ 0x10020275U, -/*0360*/ 0x18010275U, -/*0361*/ 0xffffffffU, -/*0362*/ 0x00020276U, -/*0363*/ 0x08080276U, -/*0364*/ 0x10080276U, -/*0365*/ 0x18080276U, -/*0366*/ 0x00080277U, -/*0367*/ 0x08080277U, -/*0368*/ 0x10080277U, -/*0369*/ 0xffffffffU, -/*036a*/ 0x18080277U, -/*036b*/ 0x00080278U, -/*036c*/ 0x08080278U, -/*036d*/ 0x10080278U, -/*036e*/ 0x18080278U, -/*036f*/ 0x00080279U, -/*0370*/ 0xffffffffU, -/*0371*/ 0x08080279U, -/*0372*/ 0x10080279U, -/*0373*/ 0x18080279U, -/*0374*/ 0x0008027aU, -/*0375*/ 0x0808027aU, -/*0376*/ 0x1008027aU, -/*0377*/ 0xffffffffU, -/*0378*/ 0x1808027aU, -/*0379*/ 0x0008027bU, -/*037a*/ 0x0808027bU, -/*037b*/ 0x1008027bU, -/*037c*/ 0x1808027bU, -/*037d*/ 0x0008027cU, -/*037e*/ 0x0808027cU, -/*037f*/ 0xffffffffU, -/*0380*/ 0x1008027cU, -/*0381*/ 0x1808027cU, -/*0382*/ 0x0008027dU, -/*0383*/ 0x0808027dU, -/*0384*/ 0x1008027dU, -/*0385*/ 0x1808027dU, -/*0386*/ 0xffffffffU, -/*0387*/ 0x0008027eU, -/*0388*/ 0x0808027eU, -/*0389*/ 0x1008027eU, -/*038a*/ 0x1808027eU, -/*038b*/ 0x0008027fU, -/*038c*/ 0x0808027fU, -/*038d*/ 0xffffffffU, -/*038e*/ 0x1008027fU, -/*038f*/ 0x1808027fU, -/*0390*/ 0x00080280U, -/*0391*/ 0x08080280U, -/*0392*/ 0x10080280U, -/*0393*/ 0x18080280U, -/*0394*/ 0x00080281U, -/*0395*/ 0xffffffffU, -/*0396*/ 0x08080281U, -/*0397*/ 0x10080281U, -/*0398*/ 0x18080281U, -/*0399*/ 0x00080282U, -/*039a*/ 0x08080282U, -/*039b*/ 0x10080282U, -/*039c*/ 0xffffffffU, -/*039d*/ 0x18080282U, -/*039e*/ 0x00080283U, -/*039f*/ 0x08080283U, -/*03a0*/ 0x10080283U, -/*03a1*/ 0x18080283U, -/*03a2*/ 0x00080284U, -/*03a3*/ 0xffffffffU, -/*03a4*/ 0x08080284U, -/*03a5*/ 0x10080284U, -/*03a6*/ 0x18080284U, -/*03a7*/ 0x00080285U, -/*03a8*/ 0x08080285U, -/*03a9*/ 0x10080285U, -/*03aa*/ 0x18080285U, -/*03ab*/ 0xffffffffU, -/*03ac*/ 0x00080286U, -/*03ad*/ 0x08080286U, -/*03ae*/ 0x10080286U, -/*03af*/ 0x18080286U, -/*03b0*/ 0x00080287U, -/*03b1*/ 0x08080287U, -/*03b2*/ 0xffffffffU, -/*03b3*/ 0x10080287U, -/*03b4*/ 0x18080287U, -/*03b5*/ 0x00080288U, -/*03b6*/ 0x08080288U, -/*03b7*/ 0x10080288U, -/*03b8*/ 0x18080288U, -/*03b9*/ 0xffffffffU, -/*03ba*/ 0x00080289U, -/*03bb*/ 0x08020289U, -/*03bc*/ 0x10030289U, -/*03bd*/ 0x000a028aU, -/*03be*/ 0x100a028aU, -/*03bf*/ 0x000a028bU, -/*03c0*/ 0x1005028bU, -/*03c1*/ 0x1804028bU, -/*03c2*/ 0x0008028cU, -/*03c3*/ 0x0808028cU, -/*03c4*/ 0x1006028cU, -/*03c5*/ 0x1806028cU, -/*03c6*/ 0x0011028dU, -/*03c7*/ 0x1808028dU, -/*03c8*/ 0x0004028eU, -/*03c9*/ 0x0806028eU, -/*03ca*/ 0xffffffffU, -/*03cb*/ 0x1006028eU, -/*03cc*/ 0x1808028eU, -/*03cd*/ 0xffffffffU, -/*03ce*/ 0x0004028fU, -/*03cf*/ 0x0808028fU, -/*03d0*/ 0x1008028fU, -/*03d1*/ 0x1806028fU, -/*03d2*/ 0x00060290U, -/*03d3*/ 0x08110290U, -/*03d4*/ 0x00080291U, -/*03d5*/ 0x08040291U, -/*03d6*/ 0x10060291U, -/*03d7*/ 0xffffffffU, -/*03d8*/ 0x18060291U, -/*03d9*/ 0x00080292U, -/*03da*/ 0xffffffffU, -/*03db*/ 0x08040292U, -/*03dc*/ 0x10080292U, -/*03dd*/ 0x18080292U, -/*03de*/ 0x00060293U, -/*03df*/ 0x08060293U, -/*03e0*/ 0x00110294U, -/*03e1*/ 0x18080294U, -/*03e2*/ 0x00040295U, -/*03e3*/ 0x08060295U, -/*03e4*/ 0xffffffffU, -/*03e5*/ 0x10060295U, -/*03e6*/ 0x18080295U, -/*03e7*/ 0xffffffffU, -/*03e8*/ 0x00040296U, -/*03e9*/ 0x08040296U, -/*03ea*/ 0x10040296U, -/*03eb*/ 0x18040296U, -/*03ec*/ 0x00040297U, -/*03ed*/ 0x08040297U, -/*03ee*/ 0x10040297U, -/*03ef*/ 0x18040297U, -/*03f0*/ 0x00040298U, -/*03f1*/ 0x08040298U, -/*03f2*/ 0x10040298U, -/*03f3*/ 0x18040298U, -/*03f4*/ 0x00040299U, -/*03f5*/ 0x08040299U, -/*03f6*/ 0x10040299U, -/*03f7*/ 0x18040299U, -/*03f8*/ 0x0004029aU, -/*03f9*/ 0x0804029aU, -/*03fa*/ 0x1004029aU, -/*03fb*/ 0x1804029aU, -/*03fc*/ 0x0011029bU, -/*03fd*/ 0x0010029cU, -/*03fe*/ 0x0011029dU, -/*03ff*/ 0x0020029eU, -/*0400*/ 0x0020029fU, -/*0401*/ 0x002002a0U, -/*0402*/ 0x002002a1U, -/*0403*/ 0x002002a2U, -/*0404*/ 0x002002a3U, -/*0405*/ 0x002002a4U, -/*0406*/ 0x002002a5U, -/*0407*/ 0x002002a6U, -/*0408*/ 0x000202a7U, -/*0409*/ 0x080502a7U, -/*040a*/ 0x100502a7U, -/*040b*/ 0xffffffffU, -/*040c*/ 0xffffffffU, -/*040d*/ 0xffffffffU, -/*040e*/ 0xffffffffU, -/*040f*/ 0xffffffffU, -/*0410*/ 0xffffffffU, -/*0411*/ 0xffffffffU, -/*0412*/ 0xffffffffU, -/*0413*/ 0xffffffffU, -/*0414*/ 0xffffffffU, -/*0415*/ 0xffffffffU, -/*0416*/ 0xffffffffU, -/*0417*/ 0xffffffffU, -/*0418*/ 0xffffffffU, -/*0419*/ 0xffffffffU, -/*041a*/ 0xffffffffU, -/*041b*/ 0xffffffffU, -/*041c*/ 0xffffffffU, -/*041d*/ 0xffffffffU, -/*041e*/ 0xffffffffU, -/*041f*/ 0xffffffffU, -/*0420*/ 0xffffffffU, -/*0421*/ 0xffffffffU, -/*0422*/ 0xffffffffU, -/*0423*/ 0xffffffffU, -/*0424*/ 0xffffffffU, -/*0425*/ 0xffffffffU, -/*0426*/ 0xffffffffU, -/*0427*/ 0x180102a7U, -/*0428*/ 0x000402a8U, -/*0429*/ 0x081002a8U, -/*042a*/ 0x002002a9U, -/*042b*/ 0x001002aaU, -/*042c*/ 0x002002abU, -/*042d*/ 0x001002acU, -/*042e*/ 0x002002adU, -/*042f*/ 0x000702aeU, -/*0430*/ 0x080102aeU, -/*0431*/ 0x100202aeU, -/*0432*/ 0x180602aeU, -/*0433*/ 0x000102afU, -/*0434*/ 0x080102afU, -/*0435*/ 0x002002b0U, -/*0436*/ 0x000202b1U, -/*0437*/ 0x002002b2U, -/*0438*/ 0x002002b3U, -/*0439*/ 0xffffffffU, -/*043a*/ 0xffffffffU, -/*043b*/ 0xffffffffU, -/*043c*/ 0xffffffffU, -/*043d*/ 0xffffffffU, -/*043e*/ 0xffffffffU, -/*043f*/ 0xffffffffU, -/*0440*/ 0xffffffffU, -/*0441*/ 0xffffffffU, -/*0442*/ 0xffffffffU, -/*0443*/ 0xffffffffU, -/*0444*/ 0xffffffffU, -/*0445*/ 0xffffffffU, -/*0446*/ 0xffffffffU, -/*0447*/ 0xffffffffU, -/*0448*/ 0xffffffffU, -/*0449*/ 0xffffffffU, -/*044a*/ 0xffffffffU, -/*044b*/ 0xffffffffU, -/*044c*/ 0xffffffffU, -/*044d*/ 0xffffffffU, -/*044e*/ 0xffffffffU, -/*044f*/ 0xffffffffU, -/*0450*/ 0xffffffffU, -/*0451*/ 0xffffffffU, -/*0452*/ 0xffffffffU, -/*0453*/ 0xffffffffU, -/*0454*/ 0xffffffffU, -/*0455*/ 0xffffffffU, -/*0456*/ 0xffffffffU, -/*0457*/ 0xffffffffU, -/*0458*/ 0xffffffffU, -/*0459*/ 0xffffffffU, -/*045a*/ 0xffffffffU, -/*045b*/ 0xffffffffU, -/*045c*/ 0xffffffffU, -/*045d*/ 0xffffffffU, -/*045e*/ 0xffffffffU, -/*045f*/ 0x000402b4U, -/*0460*/ 0xffffffffU, -/*0461*/ 0xffffffffU, -/*0462*/ 0xffffffffU, -/*0463*/ 0xffffffffU, -/*0464*/ 0xffffffffU, -/*0465*/ 0xffffffffU, -/*0466*/ 0xffffffffU, -/*0467*/ 0xffffffffU, -/*0468*/ 0xffffffffU, -/*0469*/ 0xffffffffU, -/*046a*/ 0xffffffffU, -/*046b*/ 0xffffffffU, -/*046c*/ 0xffffffffU, -/*046d*/ 0xffffffffU, -/*046e*/ 0xffffffffU, -/*046f*/ 0xffffffffU, -/*0470*/ 0xffffffffU, -/*0471*/ 0xffffffffU, -/*0472*/ 0xffffffffU, -/*0473*/ 0xffffffffU, -/*0474*/ 0xffffffffU, -/*0475*/ 0xffffffffU, -/*0476*/ 0xffffffffU, -/*0477*/ 0xffffffffU, -/*0478*/ 0xffffffffU, -/*0479*/ 0xffffffffU, -/*047a*/ 0xffffffffU, -/*047b*/ 0xffffffffU, -/*047c*/ 0xffffffffU, -/*047d*/ 0xffffffffU, -/*047e*/ 0xffffffffU, -/*047f*/ 0xffffffffU, -/*0480*/ 0xffffffffU, -/*0481*/ 0xffffffffU, -/*0482*/ 0xffffffffU, -/*0483*/ 0xffffffffU, -/*0484*/ 0xffffffffU, -/*0485*/ 0xffffffffU, -/*0486*/ 0xffffffffU, -/*0487*/ 0xffffffffU, -/*0488*/ 0xffffffffU, -/*0489*/ 0xffffffffU, -/*048a*/ 0xffffffffU, -/*048b*/ 0xffffffffU, -/*048c*/ 0xffffffffU, -/*048d*/ 0xffffffffU, -/*048e*/ 0xffffffffU, -/*048f*/ 0xffffffffU, -/*0490*/ 0xffffffffU, -/*0491*/ 0xffffffffU, -/*0492*/ 0xffffffffU, -/*0493*/ 0xffffffffU, -/*0494*/ 0xffffffffU, - }, - { -/*0000*/ 0x00200800U, -/*0001*/ 0x00040801U, -/*0002*/ 0x080b0801U, -/*0003*/ 0xffffffffU, -/*0004*/ 0xffffffffU, -/*0005*/ 0x18010801U, -/*0006*/ 0x00050802U, -/*0007*/ 0x08050802U, -/*0008*/ 0x10050802U, -/*0009*/ 0x18050802U, -/*000a*/ 0x00050803U, -/*000b*/ 0x08050803U, -/*000c*/ 0x10050803U, -/*000d*/ 0x18050803U, -/*000e*/ 0x00050804U, -/*000f*/ 0x08040804U, -/*0010*/ 0x10030804U, -/*0011*/ 0x00180805U, -/*0012*/ 0x18030805U, -/*0013*/ 0x00180806U, -/*0014*/ 0x18020806U, -/*0015*/ 0x00010807U, -/*0016*/ 0x08020807U, -/*0017*/ 0x10010807U, -/*0018*/ 0x18010807U, -/*0019*/ 0x00020808U, -/*001a*/ 0x08040808U, -/*001b*/ 0x10040808U, -/*001c*/ 0x18040808U, -/*001d*/ 0x000a0809U, -/*001e*/ 0x10040809U, -/*001f*/ 0xffffffffU, -/*0020*/ 0xffffffffU, -/*0021*/ 0x18070809U, -/*0022*/ 0xffffffffU, -/*0023*/ 0xffffffffU, -/*0024*/ 0xffffffffU, -/*0025*/ 0xffffffffU, -/*0026*/ 0xffffffffU, -/*0027*/ 0xffffffffU, -/*0028*/ 0x000a080aU, -/*0029*/ 0x1005080aU, -/*002a*/ 0x1801080aU, -/*002b*/ 0x0001080bU, -/*002c*/ 0x0802080bU, -/*002d*/ 0x1009080bU, -/*002e*/ 0x0009080cU, -/*002f*/ 0x1002080cU, -/*0030*/ 0x0020080dU, -/*0031*/ 0xffffffffU, -/*0032*/ 0x0001080eU, -/*0033*/ 0xffffffffU, -/*0034*/ 0xffffffffU, -/*0035*/ 0xffffffffU, -/*0036*/ 0xffffffffU, -/*0037*/ 0x0020080fU, -/*0038*/ 0x00200810U, -/*0039*/ 0x00200811U, -/*003a*/ 0x00200812U, -/*003b*/ 0x00030813U, -/*003c*/ 0x08010813U, -/*003d*/ 0x10030813U, -/*003e*/ 0x18030813U, -/*003f*/ 0x00040814U, -/*0040*/ 0x08040814U, -/*0041*/ 0x10040814U, -/*0042*/ 0x18040814U, -/*0043*/ 0x00010815U, -/*0044*/ 0x08010815U, -/*0045*/ 0x10060815U, -/*0046*/ 0x18040815U, -/*0047*/ 0xffffffffU, -/*0048*/ 0x00060816U, -/*0049*/ 0x08040816U, -/*004a*/ 0x10060816U, -/*004b*/ 0x18040816U, -/*004c*/ 0x00020817U, -/*004d*/ 0x08050817U, -/*004e*/ 0x10080817U, -/*004f*/ 0x00200818U, -/*0050*/ 0x00060819U, -/*0051*/ 0x08030819U, -/*0052*/ 0x100b0819U, -/*0053*/ 0x0004081aU, -/*0054*/ 0x0804081aU, -/*0055*/ 0x1004081aU, -/*0056*/ 0xffffffffU, -/*0057*/ 0x1801081aU, -/*0058*/ 0x0009081bU, -/*0059*/ 0x0020081cU, -/*005a*/ 0x0020081dU, -/*005b*/ 0x0020081eU, -/*005c*/ 0x0020081fU, -/*005d*/ 0x00100820U, -/*005e*/ 0xffffffffU, -/*005f*/ 0x10010820U, -/*0060*/ 0x18060820U, -/*0061*/ 0x00080821U, -/*0062*/ 0x00200822U, -/*0063*/ 0xffffffffU, -/*0064*/ 0x000a0823U, -/*0065*/ 0x10060823U, -/*0066*/ 0x18070823U, -/*0067*/ 0x00080824U, -/*0068*/ 0x08080824U, -/*0069*/ 0x100a0824U, -/*006a*/ 0x00070825U, -/*006b*/ 0x08080825U, -/*006c*/ 0x10080825U, -/*006d*/ 0x18030825U, -/*006e*/ 0x000a0826U, -/*006f*/ 0x100a0826U, -/*0070*/ 0x00110827U, -/*0071*/ 0x00090828U, -/*0072*/ 0x10090828U, -/*0073*/ 0x00100829U, -/*0074*/ 0x100e0829U, -/*0075*/ 0x000e082aU, -/*0076*/ 0x100c082aU, -/*0077*/ 0x000a082bU, -/*0078*/ 0x100a082bU, -/*0079*/ 0x0002082cU, -/*007a*/ 0x0020082dU, -/*007b*/ 0x000b082eU, -/*007c*/ 0x100b082eU, -/*007d*/ 0x0020082fU, -/*007e*/ 0x00120830U, -/*007f*/ 0x00200831U, -/*0080*/ 0x00200832U, -/*0081*/ 0xffffffffU, -/*0082*/ 0xffffffffU, -/*0083*/ 0x00010833U, -/*0084*/ 0x08010833U, -/*0085*/ 0x10080833U, -/*0086*/ 0x000c0834U, -/*0087*/ 0x100c0834U, -/*0088*/ 0x000c0835U, -/*0089*/ 0x100c0835U, -/*008a*/ 0x000c0836U, -/*008b*/ 0x100c0836U, -/*008c*/ 0x000c0837U, -/*008d*/ 0x100c0837U, -/*008e*/ 0x000c0838U, -/*008f*/ 0x100c0838U, -/*0090*/ 0x000c0839U, -/*0091*/ 0x100b0839U, -/*0092*/ 0xffffffffU, -/*0093*/ 0xffffffffU, -/*0094*/ 0x000b083aU, -/*0095*/ 0x100b083aU, -/*0096*/ 0x000b083bU, -/*0097*/ 0x100b083bU, -/*0098*/ 0x000b083cU, -/*0099*/ 0x100b083cU, -/*009a*/ 0x000b083dU, -/*009b*/ 0x100b083dU, -/*009c*/ 0x000b083eU, -/*009d*/ 0x100a083eU, -/*009e*/ 0xffffffffU, -/*009f*/ 0x000a083fU, -/*00a0*/ 0x100a083fU, -/*00a1*/ 0x000a0840U, -/*00a2*/ 0x100a0840U, -/*00a3*/ 0x000a0841U, -/*00a4*/ 0x100a0841U, -/*00a5*/ 0x000a0842U, -/*00a6*/ 0x100a0842U, -/*00a7*/ 0x000a0843U, -/*00a8*/ 0x100a0843U, -/*00a9*/ 0x000a0844U, -/*00aa*/ 0x100a0844U, -/*00ab*/ 0x000a0845U, -/*00ac*/ 0x100a0845U, -/*00ad*/ 0x000a0846U, -/*00ae*/ 0x100a0846U, -/*00af*/ 0x000a0847U, -/*00b0*/ 0x100a0847U, -/*00b1*/ 0x000a0848U, -/*00b2*/ 0x100a0848U, -/*00b3*/ 0x000a0849U, -/*00b4*/ 0x100a0849U, -/*00b5*/ 0x000a084aU, -/*00b6*/ 0x100a084aU, -/*00b7*/ 0x000a084bU, -/*00b8*/ 0x100a084bU, -/*00b9*/ 0x000a084cU, -/*00ba*/ 0x100a084cU, -/*00bb*/ 0x0004084dU, -/*00bc*/ 0x0803084dU, -/*00bd*/ 0x100a084dU, -/*00be*/ 0x000a084eU, -/*00bf*/ 0x1001084eU, -/*00c0*/ 0x000a084fU, -/*00c1*/ 0x1004084fU, -/*00c2*/ 0x000b0850U, -/*00c3*/ 0x100a0850U, -/*00c4*/ 0xffffffffU, -/*00c5*/ 0x00080851U, -/*00c6*/ 0x08080851U, -/*00c7*/ 0x10080851U, -/*00c8*/ 0x18080851U, -/*00c9*/ 0x00080852U, -/*00ca*/ 0xffffffffU, -/*00cb*/ 0x08080852U, -/*00cc*/ 0x10010852U, -/*00cd*/ 0x18080852U, -/*00ce*/ 0x00080853U, -/*00cf*/ 0x08020853U, -/*00d0*/ 0x10020853U, -/*00d1*/ 0x18040853U, -/*00d2*/ 0x00040854U, -/*00d3*/ 0xffffffffU, -/*00d4*/ 0x08040854U, -/*00d5*/ 0x100a0854U, -/*00d6*/ 0x00060855U, -/*00d7*/ 0x08080855U, -/*00d8*/ 0xffffffffU, -/*00d9*/ 0x10040855U, -/*00da*/ 0x18040855U, -/*00db*/ 0x00050856U, -/*00dc*/ 0x08040856U, -/*00dd*/ 0x10050856U, -/*00de*/ 0x000a0857U, -/*00df*/ 0x100a0857U, -/*00e0*/ 0x00080858U, -/*00e1*/ 0xffffffffU, -/*00e2*/ 0x08040858U, -/*00e3*/ 0xffffffffU, -/*00e4*/ 0xffffffffU, -/*00e5*/ 0x00050a00U, -/*00e6*/ 0x08050a00U, -/*00e7*/ 0x10050a00U, -/*00e8*/ 0x18050a00U, -/*00e9*/ 0x00050a01U, -/*00ea*/ 0x08050a01U, -/*00eb*/ 0x100b0a01U, -/*00ec*/ 0x00010a02U, -/*00ed*/ 0x08030a02U, -/*00ee*/ 0x00200a03U, -/*00ef*/ 0xffffffffU, -/*00f0*/ 0x00030a04U, -/*00f1*/ 0x080a0a04U, -/*00f2*/ 0xffffffffU, -/*00f3*/ 0xffffffffU, -/*00f4*/ 0x18030a04U, -/*00f5*/ 0x00030a05U, -/*00f6*/ 0x08010a05U, -/*00f7*/ 0x10010a05U, -/*00f8*/ 0x18060a05U, -/*00f9*/ 0xffffffffU, -/*00fa*/ 0xffffffffU, -/*00fb*/ 0xffffffffU, -/*00fc*/ 0x00020a06U, -/*00fd*/ 0x08030a06U, -/*00fe*/ 0x10010a06U, -/*00ff*/ 0x000f0a07U, -/*0100*/ 0x00200a08U, -/*0101*/ 0x00200a09U, -/*0102*/ 0x000b0a0aU, -/*0103*/ 0x100b0a0aU, -/*0104*/ 0x000b0a0bU, -/*0105*/ 0xffffffffU, -/*0106*/ 0xffffffffU, -/*0107*/ 0x00180a0cU, -/*0108*/ 0x00180a0dU, -/*0109*/ 0x00180a0eU, -/*010a*/ 0x00180a0fU, -/*010b*/ 0x18040a0fU, -/*010c*/ 0x00020a10U, -/*010d*/ 0x08020a10U, -/*010e*/ 0x10040a10U, -/*010f*/ 0x18040a10U, -/*0110*/ 0x00010a11U, -/*0111*/ 0x08010a11U, -/*0112*/ 0x10010a11U, -/*0113*/ 0x18030a11U, -/*0114*/ 0x00200a12U, -/*0115*/ 0x00200a13U, -/*0116*/ 0xffffffffU, -/*0117*/ 0x00140a14U, -/*0118*/ 0x00140a15U, -/*0119*/ 0x00140a16U, -/*011a*/ 0x00140a17U, -/*011b*/ 0x00140a18U, -/*011c*/ 0x00140a19U, -/*011d*/ 0x00140a1aU, -/*011e*/ 0x00140a1bU, -/*011f*/ 0x001e0a1cU, -/*0120*/ 0x000a0a1dU, -/*0121*/ 0x10060a1dU, -/*0122*/ 0x18060a1dU, -/*0123*/ 0x00060a1eU, -/*0124*/ 0xffffffffU, -/*0125*/ 0x08060a1eU, -/*0126*/ 0x00080a1fU, -/*0127*/ 0x080b0a1fU, -/*0128*/ 0x000b0a20U, -/*0129*/ 0x100b0a20U, -/*012a*/ 0x000b0a21U, -/*012b*/ 0x100b0a21U, -/*012c*/ 0x000b0a22U, -/*012d*/ 0x10040a22U, -/*012e*/ 0x000a0a23U, -/*012f*/ 0x10060a23U, -/*0130*/ 0x18080a23U, -/*0131*/ 0xffffffffU, -/*0132*/ 0x00040a24U, -/*0133*/ 0xffffffffU, -/*0134*/ 0xffffffffU, -/*0135*/ 0x00010b80U, -/*0136*/ 0x08020b80U, -/*0137*/ 0x10050b80U, -/*0138*/ 0x18050b80U, -/*0139*/ 0x00050b81U, -/*013a*/ 0x08050b81U, -/*013b*/ 0x100b0b81U, -/*013c*/ 0x00050b82U, -/*013d*/ 0x08010b82U, -/*013e*/ 0x10010b82U, -/*013f*/ 0xffffffffU, -/*0140*/ 0x18010b82U, -/*0141*/ 0x00010b83U, -/*0142*/ 0x08040b83U, -/*0143*/ 0x100b0b83U, -/*0144*/ 0x000b0b84U, -/*0145*/ 0xffffffffU, -/*0146*/ 0x10040b84U, -/*0147*/ 0x000b0b85U, -/*0148*/ 0x10040b85U, -/*0149*/ 0x18010b85U, -/*014a*/ 0x00010b86U, -/*014b*/ 0x08010b86U, -/*014c*/ 0x00200b87U, -/*014d*/ 0x00200b88U, -/*014e*/ 0x00080b89U, -/*014f*/ 0x080a0b89U, -/*0150*/ 0x18050b89U, -/*0151*/ 0x000a0b8aU, -/*0152*/ 0x10030b8aU, -/*0153*/ 0x18030b8aU, -/*0154*/ 0x00010b8bU, -/*0155*/ 0x08020b8bU, -/*0156*/ 0x10010b8bU, -/*0157*/ 0x18010b8bU, -/*0158*/ 0x00010b8cU, -/*0159*/ 0x08030b8cU, -/*015a*/ 0xffffffffU, -/*015b*/ 0x10040b8cU, -/*015c*/ 0x18040b8cU, -/*015d*/ 0x00040b8dU, -/*015e*/ 0x08040b8dU, -/*015f*/ 0xffffffffU, -/*0160*/ 0xffffffffU, -/*0161*/ 0xffffffffU, -/*0162*/ 0xffffffffU, -/*0163*/ 0xffffffffU, -/*0164*/ 0xffffffffU, -/*0165*/ 0xffffffffU, -/*0166*/ 0xffffffffU, -/*0167*/ 0xffffffffU, -/*0168*/ 0x000d0b8eU, -/*0169*/ 0x100d0b8eU, -/*016a*/ 0x000d0b8fU, -/*016b*/ 0x00050b90U, -/*016c*/ 0x00010b91U, -/*016d*/ 0x080e0b91U, -/*016e*/ 0x000e0b92U, -/*016f*/ 0x100e0b92U, -/*0170*/ 0x000e0b93U, -/*0171*/ 0x100e0b93U, -/*0172*/ 0x00040b94U, -/*0173*/ 0x08040b94U, -/*0174*/ 0x10040b94U, -/*0175*/ 0x18040b94U, -/*0176*/ 0x00040b95U, -/*0177*/ 0x080b0b95U, -/*0178*/ 0x000b0b96U, -/*0179*/ 0x100b0b96U, -/*017a*/ 0x000b0b97U, -/*017b*/ 0xffffffffU, -/*017c*/ 0xffffffffU, -/*017d*/ 0xffffffffU, -/*017e*/ 0xffffffffU, -/*017f*/ 0x000d0b98U, -/*0180*/ 0x100d0b98U, -/*0181*/ 0x000d0b99U, -/*0182*/ 0x10100b99U, -/*0183*/ 0x10080b8dU, -/*0184*/ 0x18080b8dU, -/*0185*/ 0x00100b9aU, -/*0186*/ 0x10100b9aU, -/*0187*/ 0x00100b9bU, -/*0188*/ 0x10100b9bU, -/*0189*/ 0x00100b9cU, -/*018a*/ 0x10030b9cU, -/*018b*/ 0x18040b9cU, -/*018c*/ 0x00010b9dU, -/*018d*/ 0x08040b9dU, -/*018e*/ 0xffffffffU, -/*018f*/ 0xffffffffU, -/*0190*/ 0x10010b9dU, -/*0191*/ 0x00140b9eU, -/*0192*/ 0x000a0b9fU, -/*0193*/ 0x100c0b9fU, -/*0194*/ 0x00120ba0U, -/*0195*/ 0x00140ba1U, -/*0196*/ 0x00120ba2U, -/*0197*/ 0x00110ba3U, -/*0198*/ 0x00110ba4U, -/*0199*/ 0x00120ba5U, -/*019a*/ 0x00120ba6U, -/*019b*/ 0x00120ba7U, -/*019c*/ 0x00120ba8U, -/*019d*/ 0x00120ba9U, -/*019e*/ 0x00120baaU, -/*019f*/ 0x00120babU, -/*01a0*/ 0x00120bacU, -/*01a1*/ 0xffffffffU, -/*01a2*/ 0xffffffffU, -/*01a3*/ 0x00190badU, -/*01a4*/ 0x00190baeU, -/*01a5*/ 0x00200bafU, -/*01a6*/ 0x00170bb0U, -/*01a7*/ 0x18080bb0U, -/*01a8*/ 0x00010bb1U, -/*01a9*/ 0x08010bb1U, -/*01aa*/ 0x00200bb2U, -/*01ab*/ 0x00080bb3U, -/*01ac*/ 0xffffffffU, -/*01ad*/ 0x08030bb3U, -/*01ae*/ 0x00180bb4U, -/*01af*/ 0x00180bb5U, -/*01b0*/ 0xffffffffU, -/*01b1*/ 0xffffffffU, -/*01b2*/ 0xffffffffU, -/*01b3*/ 0xffffffffU, -/*01b4*/ 0xffffffffU, -/*01b5*/ 0xffffffffU, -/*01b6*/ 0xffffffffU, -/*01b7*/ 0xffffffffU, -/*01b8*/ 0xffffffffU, -/*01b9*/ 0xffffffffU, -/*01ba*/ 0xffffffffU, -/*01bb*/ 0xffffffffU, -/*01bc*/ 0xffffffffU, -/*01bd*/ 0xffffffffU, -/*01be*/ 0xffffffffU, -/*01bf*/ 0x00100bb6U, -/*01c0*/ 0x10010bb6U, -/*01c1*/ 0x18010bb6U, -/*01c2*/ 0x00050bb7U, -/*01c3*/ 0x00200bb8U, -/*01c4*/ 0x00090bb9U, -/*01c5*/ 0xffffffffU, -/*01c6*/ 0xffffffffU, -/*01c7*/ 0x00200bbaU, -/*01c8*/ 0x00040bbbU, -/*01c9*/ 0x08100bbbU, -/*01ca*/ 0x18060bbbU, -/*01cb*/ 0x00100bbcU, -/*01cc*/ 0xffffffffU, -/*01cd*/ 0x10080bbcU, -/*01ce*/ 0xffffffffU, -/*01cf*/ 0xffffffffU, -/*01d0*/ 0xffffffffU, -/*01d1*/ 0x18030bbcU, -/*01d2*/ 0x00020bbdU, -/*01d3*/ 0xffffffffU, -/*01d4*/ 0x00200bbeU, -/*01d5*/ 0x000b0bbfU, -/*01d6*/ 0xffffffffU, -/*01d7*/ 0xffffffffU, -/*01d8*/ 0xffffffffU, -/*01d9*/ 0x10020bbfU, -/*01da*/ 0xffffffffU, -/*01db*/ 0xffffffffU, -/*01dc*/ 0xffffffffU, -/*01dd*/ 0xffffffffU, -/*01de*/ 0x00010200U, -/*01df*/ 0x08040200U, -/*01e0*/ 0x10100200U, -/*01e1*/ 0x00010201U, -/*01e2*/ 0x08010201U, -/*01e3*/ 0xffffffffU, -/*01e4*/ 0xffffffffU, -/*01e5*/ 0x10100201U, -/*01e6*/ 0xffffffffU, -/*01e7*/ 0xffffffffU, -/*01e8*/ 0xffffffffU, -/*01e9*/ 0xffffffffU, -/*01ea*/ 0xffffffffU, -/*01eb*/ 0xffffffffU, -/*01ec*/ 0xffffffffU, -/*01ed*/ 0xffffffffU, -/*01ee*/ 0xffffffffU, -/*01ef*/ 0x00200202U, -/*01f0*/ 0x00100203U, -/*01f1*/ 0x00200204U, -/*01f2*/ 0x00100205U, -/*01f3*/ 0x00200206U, -/*01f4*/ 0x00100207U, -/*01f5*/ 0x10100207U, -/*01f6*/ 0x00200208U, -/*01f7*/ 0x00200209U, -/*01f8*/ 0x0020020aU, -/*01f9*/ 0x0020020bU, -/*01fa*/ 0x0010020cU, -/*01fb*/ 0x0020020dU, -/*01fc*/ 0x0020020eU, -/*01fd*/ 0x0020020fU, -/*01fe*/ 0x00200210U, -/*01ff*/ 0x00100211U, -/*0200*/ 0x00200212U, -/*0201*/ 0x00200213U, -/*0202*/ 0x00200214U, -/*0203*/ 0x00200215U, -/*0204*/ 0x00090216U, -/*0205*/ 0x10010216U, -/*0206*/ 0x00200217U, -/*0207*/ 0x00050218U, -/*0208*/ 0x08010218U, -/*0209*/ 0x10080218U, -/*020a*/ 0x18080218U, -/*020b*/ 0x001e0219U, -/*020c*/ 0x001e021aU, -/*020d*/ 0x001e021bU, -/*020e*/ 0x001e021cU, -/*020f*/ 0x001e021dU, -/*0210*/ 0x001e021eU, -/*0211*/ 0x001e021fU, -/*0212*/ 0x001e0220U, -/*0213*/ 0x001e0221U, -/*0214*/ 0x001e0222U, -/*0215*/ 0x001e0223U, -/*0216*/ 0x001e0224U, -/*0217*/ 0x001e0225U, -/*0218*/ 0x001e0226U, -/*0219*/ 0x001e0227U, -/*021a*/ 0x001e0228U, -/*021b*/ 0x00010229U, -/*021c*/ 0x08010229U, -/*021d*/ 0x10010229U, -/*021e*/ 0x18040229U, -/*021f*/ 0x0008022aU, -/*0220*/ 0x0808022aU, -/*0221*/ 0x1008022aU, -/*0222*/ 0x1804022aU, -/*0223*/ 0x0005022bU, -/*0224*/ 0x0806022bU, -/*0225*/ 0x1007022bU, -/*0226*/ 0x1805022bU, -/*0227*/ 0x0006022cU, -/*0228*/ 0x0807022cU, -/*0229*/ 0x1005022cU, -/*022a*/ 0x1806022cU, -/*022b*/ 0x0007022dU, -/*022c*/ 0x0802022dU, -/*022d*/ 0x1001022dU, -/*022e*/ 0xffffffffU, -/*022f*/ 0x000a022eU, -/*0230*/ 0x1010022eU, -/*0231*/ 0x000a022fU, -/*0232*/ 0x1010022fU, -/*0233*/ 0x000a0230U, -/*0234*/ 0x10100230U, -/*0235*/ 0xffffffffU, -/*0236*/ 0x00100231U, -/*0237*/ 0xffffffffU, -/*0238*/ 0xffffffffU, -/*0239*/ 0x10010231U, -/*023a*/ 0x18010231U, -/*023b*/ 0x00010232U, -/*023c*/ 0x08010232U, -/*023d*/ 0x10010232U, -/*023e*/ 0x18010232U, -/*023f*/ 0x00020233U, -/*0240*/ 0x08020233U, -/*0241*/ 0x10020233U, -/*0242*/ 0x18020233U, -/*0243*/ 0x00020234U, -/*0244*/ 0x08030234U, -/*0245*/ 0x10010234U, -/*0246*/ 0x18010234U, -/*0247*/ 0x00010235U, -/*0248*/ 0x08010235U, -/*0249*/ 0xffffffffU, -/*024a*/ 0x10020235U, -/*024b*/ 0x18010235U, -/*024c*/ 0x00010236U, -/*024d*/ 0xffffffffU, -/*024e*/ 0x08020236U, -/*024f*/ 0x10010236U, -/*0250*/ 0x18010236U, -/*0251*/ 0xffffffffU, -/*0252*/ 0x00020237U, -/*0253*/ 0x08010237U, -/*0254*/ 0x10010237U, -/*0255*/ 0xffffffffU, -/*0256*/ 0x18020237U, -/*0257*/ 0x00070238U, -/*0258*/ 0x08010238U, -/*0259*/ 0x10010238U, -/*025a*/ 0x18010238U, -/*025b*/ 0x00010239U, -/*025c*/ 0x08010239U, -/*025d*/ 0x10010239U, -/*025e*/ 0xffffffffU, -/*025f*/ 0x18010239U, -/*0260*/ 0x0004023aU, -/*0261*/ 0x0804023aU, -/*0262*/ 0x1004023aU, -/*0263*/ 0x1801023aU, -/*0264*/ 0x0002023bU, -/*0265*/ 0x0806023bU, -/*0266*/ 0x1006023bU, -/*0267*/ 0xffffffffU, -/*0268*/ 0xffffffffU, -/*0269*/ 0xffffffffU, -/*026a*/ 0x1802023bU, -/*026b*/ 0x0010023cU, -/*026c*/ 0x1001023cU, -/*026d*/ 0x1801023cU, -/*026e*/ 0xffffffffU, -/*026f*/ 0x0004023dU, -/*0270*/ 0x0801023dU, -/*0271*/ 0x1004023dU, -/*0272*/ 0x1802023dU, -/*0273*/ 0x0008023eU, -/*0274*/ 0xffffffffU, -/*0275*/ 0xffffffffU, -/*0276*/ 0xffffffffU, -/*0277*/ 0x080a023eU, -/*0278*/ 0x0020023fU, -/*0279*/ 0x00200240U, -/*027a*/ 0x00050241U, -/*027b*/ 0x08010241U, -/*027c*/ 0x10050241U, -/*027d*/ 0x18080241U, -/*027e*/ 0x00010242U, -/*027f*/ 0x08080242U, -/*0280*/ 0x10010242U, -/*0281*/ 0x18080242U, -/*0282*/ 0x00010243U, -/*0283*/ 0x08040243U, -/*0284*/ 0x10040243U, -/*0285*/ 0x18040243U, -/*0286*/ 0x00040244U, -/*0287*/ 0x08040244U, -/*0288*/ 0x10040244U, -/*0289*/ 0x18040244U, -/*028a*/ 0x00040245U, -/*028b*/ 0x08040245U, -/*028c*/ 0x10040245U, -/*028d*/ 0x18010245U, -/*028e*/ 0x00040246U, -/*028f*/ 0x08040246U, -/*0290*/ 0x10040246U, -/*0291*/ 0x18040246U, -/*0292*/ 0x00040247U, -/*0293*/ 0x08040247U, -/*0294*/ 0x10060247U, -/*0295*/ 0x18060247U, -/*0296*/ 0x00060248U, -/*0297*/ 0x08060248U, -/*0298*/ 0x10060248U, -/*0299*/ 0x18060248U, -/*029a*/ 0x00040249U, -/*029b*/ 0x08010249U, -/*029c*/ 0x10010249U, -/*029d*/ 0x18020249U, -/*029e*/ 0xffffffffU, -/*029f*/ 0xffffffffU, -/*02a0*/ 0xffffffffU, -/*02a1*/ 0xffffffffU, -/*02a2*/ 0xffffffffU, -/*02a3*/ 0xffffffffU, -/*02a4*/ 0xffffffffU, -/*02a5*/ 0xffffffffU, -/*02a6*/ 0x0004024aU, -/*02a7*/ 0x0804024aU, -/*02a8*/ 0x1001024aU, -/*02a9*/ 0x1801024aU, -/*02aa*/ 0xffffffffU, -/*02ab*/ 0x0001024bU, -/*02ac*/ 0x0801024bU, -/*02ad*/ 0xffffffffU, -/*02ae*/ 0x1001024bU, -/*02af*/ 0x1801024bU, -/*02b0*/ 0x0001024cU, -/*02b1*/ 0x0804024cU, -/*02b2*/ 0x1004024cU, -/*02b3*/ 0x000a024dU, -/*02b4*/ 0x0020024eU, -/*02b5*/ 0x0004024fU, -/*02b6*/ 0x0808024fU, -/*02b7*/ 0xffffffffU, -/*02b8*/ 0xffffffffU, -/*02b9*/ 0xffffffffU, -/*02ba*/ 0xffffffffU, -/*02bb*/ 0xffffffffU, -/*02bc*/ 0xffffffffU, -/*02bd*/ 0x1002024fU, -/*02be*/ 0x1802024fU, -/*02bf*/ 0x00200250U, -/*02c0*/ 0x00020251U, -/*02c1*/ 0x08100251U, -/*02c2*/ 0x00100252U, -/*02c3*/ 0x10040252U, -/*02c4*/ 0x18040252U, -/*02c5*/ 0x00050253U, -/*02c6*/ 0x08050253U, -/*02c7*/ 0xffffffffU, -/*02c8*/ 0xffffffffU, -/*02c9*/ 0xffffffffU, -/*02ca*/ 0xffffffffU, -/*02cb*/ 0x10010253U, -/*02cc*/ 0x18010253U, -/*02cd*/ 0x00080254U, -/*02ce*/ 0x08080254U, -/*02cf*/ 0x10080254U, -/*02d0*/ 0x18080254U, -/*02d1*/ 0x00080255U, -/*02d2*/ 0x08080255U, -/*02d3*/ 0x10080255U, -/*02d4*/ 0x18080255U, -/*02d5*/ 0x00080256U, -/*02d6*/ 0x08080256U, -/*02d7*/ 0x10080256U, -/*02d8*/ 0xffffffffU, -/*02d9*/ 0xffffffffU, -/*02da*/ 0xffffffffU, -/*02db*/ 0xffffffffU, -/*02dc*/ 0xffffffffU, -/*02dd*/ 0xffffffffU, -/*02de*/ 0x18030256U, -/*02df*/ 0x00010257U, -/*02e0*/ 0x08020257U, -/*02e1*/ 0x10010257U, -/*02e2*/ 0x18040257U, -/*02e3*/ 0x00020258U, -/*02e4*/ 0x08010258U, -/*02e5*/ 0x10010258U, -/*02e6*/ 0xffffffffU, -/*02e7*/ 0x18010258U, -/*02e8*/ 0x00040259U, -/*02e9*/ 0x08080259U, -/*02ea*/ 0x100a0259U, -/*02eb*/ 0x000a025aU, -/*02ec*/ 0x100a025aU, -/*02ed*/ 0x000a025bU, -/*02ee*/ 0x100a025bU, -/*02ef*/ 0x000a025cU, -/*02f0*/ 0x0020025dU, -/*02f1*/ 0x0020025eU, -/*02f2*/ 0x0001025fU, -/*02f3*/ 0xffffffffU, -/*02f4*/ 0xffffffffU, -/*02f5*/ 0xffffffffU, -/*02f6*/ 0x0802025fU, -/*02f7*/ 0x1002025fU, -/*02f8*/ 0x00100260U, -/*02f9*/ 0x10050260U, -/*02fa*/ 0x18060260U, -/*02fb*/ 0x00050261U, -/*02fc*/ 0x08050261U, -/*02fd*/ 0x100e0261U, -/*02fe*/ 0x00050262U, -/*02ff*/ 0x080e0262U, -/*0300*/ 0x18050262U, -/*0301*/ 0x000e0263U, -/*0302*/ 0x10050263U, -/*0303*/ 0x18010263U, -/*0304*/ 0x00050264U, -/*0305*/ 0x08050264U, -/*0306*/ 0x100a0264U, -/*0307*/ 0x000a0265U, -/*0308*/ 0x10050265U, -/*0309*/ 0x18050265U, -/*030a*/ 0x000a0266U, -/*030b*/ 0x100a0266U, -/*030c*/ 0x00050267U, -/*030d*/ 0x08050267U, -/*030e*/ 0x100a0267U, -/*030f*/ 0x000a0268U, -/*0310*/ 0xffffffffU, -/*0311*/ 0xffffffffU, -/*0312*/ 0xffffffffU, -/*0313*/ 0xffffffffU, -/*0314*/ 0xffffffffU, -/*0315*/ 0xffffffffU, -/*0316*/ 0x10070268U, -/*0317*/ 0x18070268U, -/*0318*/ 0x00040269U, -/*0319*/ 0x08040269U, -/*031a*/ 0xffffffffU, -/*031b*/ 0xffffffffU, -/*031c*/ 0xffffffffU, -/*031d*/ 0x10040269U, -/*031e*/ 0x18080269U, -/*031f*/ 0x0008026aU, -/*0320*/ 0x0804026aU, -/*0321*/ 0xffffffffU, -/*0322*/ 0xffffffffU, -/*0323*/ 0xffffffffU, -/*0324*/ 0x1004026aU, -/*0325*/ 0xffffffffU, -/*0326*/ 0xffffffffU, -/*0327*/ 0xffffffffU, -/*0328*/ 0x1804026aU, -/*0329*/ 0xffffffffU, -/*032a*/ 0xffffffffU, -/*032b*/ 0xffffffffU, -/*032c*/ 0x0004026bU, -/*032d*/ 0x0805026bU, -/*032e*/ 0x1007026bU, -/*032f*/ 0x1808026bU, -/*0330*/ 0x0010026cU, -/*0331*/ 0x1008026cU, -/*0332*/ 0x0010026dU, -/*0333*/ 0x1008026dU, -/*0334*/ 0x0010026eU, -/*0335*/ 0x1008026eU, -/*0336*/ 0x1808026eU, -/*0337*/ 0x0001026fU, -/*0338*/ 0x0801026fU, -/*0339*/ 0x1006026fU, -/*033a*/ 0x1806026fU, -/*033b*/ 0x00060270U, -/*033c*/ 0xffffffffU, -/*033d*/ 0x08010270U, -/*033e*/ 0x10030270U, -/*033f*/ 0xffffffffU, -/*0340*/ 0xffffffffU, -/*0341*/ 0xffffffffU, -/*0342*/ 0x000a0271U, -/*0343*/ 0x100a0271U, -/*0344*/ 0x00040272U, -/*0345*/ 0x08010272U, -/*0346*/ 0x10040272U, -/*0347*/ 0xffffffffU, -/*0348*/ 0xffffffffU, -/*0349*/ 0xffffffffU, -/*034a*/ 0xffffffffU, -/*034b*/ 0xffffffffU, -/*034c*/ 0xffffffffU, -/*034d*/ 0x18070272U, -/*034e*/ 0x00070273U, -/*034f*/ 0x08050273U, -/*0350*/ 0x10050273U, -/*0351*/ 0xffffffffU, -/*0352*/ 0xffffffffU, -/*0353*/ 0xffffffffU, -/*0354*/ 0x18040273U, -/*0355*/ 0x00010274U, -/*0356*/ 0x08010274U, -/*0357*/ 0x10020274U, -/*0358*/ 0x18080274U, -/*0359*/ 0x00200275U, -/*035a*/ 0x00200276U, -/*035b*/ 0x00100277U, -/*035c*/ 0xffffffffU, -/*035d*/ 0xffffffffU, -/*035e*/ 0xffffffffU, -/*035f*/ 0x10020277U, -/*0360*/ 0x18010277U, -/*0361*/ 0xffffffffU, -/*0362*/ 0x00020278U, -/*0363*/ 0x08100278U, -/*0364*/ 0x00100279U, -/*0365*/ 0x10100279U, -/*0366*/ 0x0008027aU, -/*0367*/ 0x0808027aU, -/*0368*/ 0x1008027aU, -/*0369*/ 0xffffffffU, -/*036a*/ 0x0010027bU, -/*036b*/ 0x1010027bU, -/*036c*/ 0x0010027cU, -/*036d*/ 0x1008027cU, -/*036e*/ 0x1808027cU, -/*036f*/ 0x0008027dU, -/*0370*/ 0xffffffffU, -/*0371*/ 0x0810027dU, -/*0372*/ 0x0010027eU, -/*0373*/ 0x1010027eU, -/*0374*/ 0x0008027fU, -/*0375*/ 0x0808027fU, -/*0376*/ 0x1008027fU, -/*0377*/ 0xffffffffU, -/*0378*/ 0x1808027fU, -/*0379*/ 0x00100280U, -/*037a*/ 0x10100280U, -/*037b*/ 0x00100281U, -/*037c*/ 0x10080281U, -/*037d*/ 0x18080281U, -/*037e*/ 0x00080282U, -/*037f*/ 0xffffffffU, -/*0380*/ 0x08100282U, -/*0381*/ 0x00100283U, -/*0382*/ 0x10100283U, -/*0383*/ 0x00080284U, -/*0384*/ 0x08080284U, -/*0385*/ 0x10080284U, -/*0386*/ 0xffffffffU, -/*0387*/ 0x00100285U, -/*0388*/ 0x10100285U, -/*0389*/ 0x00100286U, -/*038a*/ 0x10080286U, -/*038b*/ 0x18080286U, -/*038c*/ 0x00080287U, -/*038d*/ 0xffffffffU, -/*038e*/ 0x08080287U, -/*038f*/ 0x10100287U, -/*0390*/ 0x00100288U, -/*0391*/ 0x10100288U, -/*0392*/ 0x00080289U, -/*0393*/ 0x08080289U, -/*0394*/ 0x10080289U, -/*0395*/ 0xffffffffU, -/*0396*/ 0x0010028aU, -/*0397*/ 0x1010028aU, -/*0398*/ 0x0010028bU, -/*0399*/ 0x1008028bU, -/*039a*/ 0x1808028bU, -/*039b*/ 0x0008028cU, -/*039c*/ 0xffffffffU, -/*039d*/ 0x0810028cU, -/*039e*/ 0x0010028dU, -/*039f*/ 0x1010028dU, -/*03a0*/ 0x0008028eU, -/*03a1*/ 0x0808028eU, -/*03a2*/ 0x1008028eU, -/*03a3*/ 0xffffffffU, -/*03a4*/ 0x1808028eU, -/*03a5*/ 0x0010028fU, -/*03a6*/ 0x1010028fU, -/*03a7*/ 0x00100290U, -/*03a8*/ 0x10080290U, -/*03a9*/ 0x18080290U, -/*03aa*/ 0x00080291U, -/*03ab*/ 0xffffffffU, -/*03ac*/ 0x08100291U, -/*03ad*/ 0x00100292U, -/*03ae*/ 0x10100292U, -/*03af*/ 0x00080293U, -/*03b0*/ 0x08080293U, -/*03b1*/ 0x10080293U, -/*03b2*/ 0xffffffffU, -/*03b3*/ 0x00100294U, -/*03b4*/ 0x10100294U, -/*03b5*/ 0x00100295U, -/*03b6*/ 0x10080295U, -/*03b7*/ 0x18080295U, -/*03b8*/ 0x00080296U, -/*03b9*/ 0xffffffffU, -/*03ba*/ 0x08080296U, -/*03bb*/ 0x10020296U, -/*03bc*/ 0x18030296U, -/*03bd*/ 0x000a0297U, -/*03be*/ 0x100a0297U, -/*03bf*/ 0x000a0298U, -/*03c0*/ 0x10050298U, -/*03c1*/ 0x18040298U, -/*03c2*/ 0x00080299U, -/*03c3*/ 0x08080299U, -/*03c4*/ 0x10060299U, -/*03c5*/ 0x18060299U, -/*03c6*/ 0x0011029aU, -/*03c7*/ 0x1808029aU, -/*03c8*/ 0x0004029bU, -/*03c9*/ 0x0806029bU, -/*03ca*/ 0xffffffffU, -/*03cb*/ 0x1006029bU, -/*03cc*/ 0x1808029bU, -/*03cd*/ 0x0008029cU, -/*03ce*/ 0x0804029cU, -/*03cf*/ 0x1008029cU, -/*03d0*/ 0x1808029cU, -/*03d1*/ 0x0006029dU, -/*03d2*/ 0x0806029dU, -/*03d3*/ 0x0011029eU, -/*03d4*/ 0x1808029eU, -/*03d5*/ 0x0004029fU, -/*03d6*/ 0x0806029fU, -/*03d7*/ 0xffffffffU, -/*03d8*/ 0x1006029fU, -/*03d9*/ 0x1808029fU, -/*03da*/ 0x000802a0U, -/*03db*/ 0x080402a0U, -/*03dc*/ 0x100802a0U, -/*03dd*/ 0x180802a0U, -/*03de*/ 0x000602a1U, -/*03df*/ 0x080602a1U, -/*03e0*/ 0x001102a2U, -/*03e1*/ 0x180802a2U, -/*03e2*/ 0x000402a3U, -/*03e3*/ 0x080602a3U, -/*03e4*/ 0xffffffffU, -/*03e5*/ 0x100602a3U, -/*03e6*/ 0x180802a3U, -/*03e7*/ 0x000802a4U, -/*03e8*/ 0x080402a4U, -/*03e9*/ 0x100402a4U, -/*03ea*/ 0x180402a4U, -/*03eb*/ 0x000402a5U, -/*03ec*/ 0x080402a5U, -/*03ed*/ 0x100402a5U, -/*03ee*/ 0x180402a5U, -/*03ef*/ 0x000402a6U, -/*03f0*/ 0x080402a6U, -/*03f1*/ 0x100402a6U, -/*03f2*/ 0x180402a6U, -/*03f3*/ 0x000402a7U, -/*03f4*/ 0x080402a7U, -/*03f5*/ 0x100402a7U, -/*03f6*/ 0x180402a7U, -/*03f7*/ 0x000402a8U, -/*03f8*/ 0x080402a8U, -/*03f9*/ 0x100402a8U, -/*03fa*/ 0x180402a8U, -/*03fb*/ 0x000402a9U, -/*03fc*/ 0x081202a9U, -/*03fd*/ 0x001102aaU, -/*03fe*/ 0x001202abU, -/*03ff*/ 0x002002acU, -/*0400*/ 0x002002adU, -/*0401*/ 0x002002aeU, -/*0402*/ 0x002002afU, -/*0403*/ 0x002002b0U, -/*0404*/ 0x002002b1U, -/*0405*/ 0x002002b2U, -/*0406*/ 0x002002b3U, -/*0407*/ 0x002002b4U, -/*0408*/ 0x000302b5U, -/*0409*/ 0x080502b5U, -/*040a*/ 0x100502b5U, -/*040b*/ 0x180102b5U, -/*040c*/ 0x000502b6U, -/*040d*/ 0x080502b6U, -/*040e*/ 0x100502b6U, -/*040f*/ 0x180502b6U, -/*0410*/ 0x000502b7U, -/*0411*/ 0x080502b7U, -/*0412*/ 0x100502b7U, -/*0413*/ 0x180502b7U, -/*0414*/ 0x000502b8U, -/*0415*/ 0x080502b8U, -/*0416*/ 0x100502b8U, -/*0417*/ 0x180502b8U, -/*0418*/ 0x000502b9U, -/*0419*/ 0x080502b9U, -/*041a*/ 0x100502b9U, -/*041b*/ 0x180502b9U, -/*041c*/ 0x000502baU, -/*041d*/ 0x080502baU, -/*041e*/ 0x100502baU, -/*041f*/ 0x180502baU, -/*0420*/ 0x000502bbU, -/*0421*/ 0x080502bbU, -/*0422*/ 0x100102bbU, -/*0423*/ 0x180202bbU, -/*0424*/ 0x000202bcU, -/*0425*/ 0x080202bcU, -/*0426*/ 0x100202bcU, -/*0427*/ 0x180102bcU, -/*0428*/ 0x000402bdU, -/*0429*/ 0x081002bdU, -/*042a*/ 0x002002beU, -/*042b*/ 0x001002bfU, -/*042c*/ 0x002002c0U, -/*042d*/ 0x001002c1U, -/*042e*/ 0x002002c2U, -/*042f*/ 0x000702c3U, -/*0430*/ 0x080102c3U, -/*0431*/ 0x100202c3U, -/*0432*/ 0x180602c3U, -/*0433*/ 0x000102c4U, -/*0434*/ 0x080102c4U, -/*0435*/ 0x002002c5U, -/*0436*/ 0x000302c6U, -/*0437*/ 0x002002c7U, -/*0438*/ 0x002002c8U, -/*0439*/ 0xffffffffU, -/*043a*/ 0xffffffffU, -/*043b*/ 0xffffffffU, -/*043c*/ 0xffffffffU, -/*043d*/ 0xffffffffU, -/*043e*/ 0xffffffffU, -/*043f*/ 0xffffffffU, -/*0440*/ 0xffffffffU, -/*0441*/ 0xffffffffU, -/*0442*/ 0xffffffffU, -/*0443*/ 0xffffffffU, -/*0444*/ 0xffffffffU, -/*0445*/ 0xffffffffU, -/*0446*/ 0xffffffffU, -/*0447*/ 0xffffffffU, -/*0448*/ 0xffffffffU, -/*0449*/ 0xffffffffU, -/*044a*/ 0xffffffffU, -/*044b*/ 0xffffffffU, -/*044c*/ 0xffffffffU, -/*044d*/ 0xffffffffU, -/*044e*/ 0xffffffffU, -/*044f*/ 0xffffffffU, -/*0450*/ 0xffffffffU, -/*0451*/ 0xffffffffU, -/*0452*/ 0xffffffffU, -/*0453*/ 0xffffffffU, -/*0454*/ 0xffffffffU, -/*0455*/ 0xffffffffU, -/*0456*/ 0xffffffffU, -/*0457*/ 0xffffffffU, -/*0458*/ 0xffffffffU, -/*0459*/ 0xffffffffU, -/*045a*/ 0xffffffffU, -/*045b*/ 0xffffffffU, -/*045c*/ 0xffffffffU, -/*045d*/ 0xffffffffU, -/*045e*/ 0xffffffffU, -/*045f*/ 0x000402c9U, -/*0460*/ 0xffffffffU, -/*0461*/ 0xffffffffU, -/*0462*/ 0xffffffffU, -/*0463*/ 0xffffffffU, -/*0464*/ 0xffffffffU, -/*0465*/ 0xffffffffU, -/*0466*/ 0xffffffffU, -/*0467*/ 0xffffffffU, -/*0468*/ 0xffffffffU, -/*0469*/ 0xffffffffU, -/*046a*/ 0xffffffffU, -/*046b*/ 0xffffffffU, -/*046c*/ 0xffffffffU, -/*046d*/ 0xffffffffU, -/*046e*/ 0xffffffffU, -/*046f*/ 0xffffffffU, -/*0470*/ 0xffffffffU, -/*0471*/ 0xffffffffU, -/*0472*/ 0xffffffffU, -/*0473*/ 0xffffffffU, -/*0474*/ 0xffffffffU, -/*0475*/ 0xffffffffU, -/*0476*/ 0xffffffffU, -/*0477*/ 0xffffffffU, -/*0478*/ 0xffffffffU, -/*0479*/ 0xffffffffU, -/*047a*/ 0xffffffffU, -/*047b*/ 0xffffffffU, -/*047c*/ 0xffffffffU, -/*047d*/ 0xffffffffU, -/*047e*/ 0xffffffffU, -/*047f*/ 0xffffffffU, -/*0480*/ 0xffffffffU, -/*0481*/ 0xffffffffU, -/*0482*/ 0xffffffffU, -/*0483*/ 0xffffffffU, -/*0484*/ 0xffffffffU, -/*0485*/ 0xffffffffU, -/*0486*/ 0xffffffffU, -/*0487*/ 0xffffffffU, -/*0488*/ 0xffffffffU, -/*0489*/ 0xffffffffU, -/*048a*/ 0xffffffffU, -/*048b*/ 0xffffffffU, -/*048c*/ 0xffffffffU, -/*048d*/ 0xffffffffU, -/*048e*/ 0xffffffffU, -/*048f*/ 0xffffffffU, -/*0490*/ 0xffffffffU, -/*0491*/ 0xffffffffU, -/*0492*/ 0xffffffffU, -/*0493*/ 0xffffffffU, -/*0494*/ 0xffffffffU, - }, - { -/*0000*/ 0x00200400U, -/*0001*/ 0x00040401U, -/*0002*/ 0x080b0401U, -/*0003*/ 0x000a0402U, -/*0004*/ 0x10020402U, -/*0005*/ 0x18010402U, -/*0006*/ 0x00050403U, -/*0007*/ 0x08050403U, -/*0008*/ 0x10050403U, -/*0009*/ 0x18050403U, -/*000a*/ 0x00050404U, -/*000b*/ 0x08050404U, -/*000c*/ 0x10050404U, -/*000d*/ 0x18050404U, -/*000e*/ 0x00050405U, -/*000f*/ 0x08040405U, -/*0010*/ 0x10030405U, -/*0011*/ 0x00180406U, -/*0012*/ 0x18030406U, -/*0013*/ 0x00180407U, -/*0014*/ 0x18020407U, -/*0015*/ 0x00010408U, -/*0016*/ 0x08020408U, -/*0017*/ 0x10010408U, -/*0018*/ 0x18010408U, -/*0019*/ 0x00020409U, -/*001a*/ 0x08040409U, -/*001b*/ 0x10040409U, -/*001c*/ 0x18040409U, -/*001d*/ 0xffffffffU, -/*001e*/ 0x0004040aU, -/*001f*/ 0xffffffffU, -/*0020*/ 0xffffffffU, -/*0021*/ 0x0809040aU, -/*0022*/ 0x1801040aU, -/*0023*/ 0x0020040bU, -/*0024*/ 0x001c040cU, -/*0025*/ 0x0001040dU, -/*0026*/ 0x0807040dU, -/*0027*/ 0x1009040dU, -/*0028*/ 0x000a040eU, -/*0029*/ 0x1005040eU, -/*002a*/ 0x1801040eU, -/*002b*/ 0x1001040fU, -/*002c*/ 0x1802040fU, -/*002d*/ 0x0009040fU, -/*002e*/ 0x00090410U, -/*002f*/ 0x10020410U, -/*0030*/ 0x00200411U, -/*0031*/ 0x00010412U, -/*0032*/ 0x08020412U, -/*0033*/ 0xffffffffU, -/*0034*/ 0xffffffffU, -/*0035*/ 0xffffffffU, -/*0036*/ 0xffffffffU, -/*0037*/ 0x00200413U, -/*0038*/ 0x00200414U, -/*0039*/ 0x00200415U, -/*003a*/ 0x00200416U, -/*003b*/ 0x00030417U, -/*003c*/ 0x08010417U, -/*003d*/ 0x10040417U, -/*003e*/ 0x18030417U, -/*003f*/ 0x00040418U, -/*0040*/ 0x08040418U, -/*0041*/ 0x10040418U, -/*0042*/ 0x18040418U, -/*0043*/ 0x00010419U, -/*0044*/ 0x08010419U, -/*0045*/ 0x10060419U, -/*0046*/ 0x18040419U, -/*0047*/ 0xffffffffU, -/*0048*/ 0x0006041aU, -/*0049*/ 0x0804041aU, -/*004a*/ 0x1006041aU, -/*004b*/ 0x1804041aU, -/*004c*/ 0x0002041bU, -/*004d*/ 0x0805041bU, -/*004e*/ 0x1008041bU, -/*004f*/ 0xffffffffU, -/*0050*/ 0x1806041bU, -/*0051*/ 0x0003041cU, -/*0052*/ 0x080b041cU, -/*0053*/ 0x1804041cU, -/*0054*/ 0x0004041dU, -/*0055*/ 0x0804041dU, -/*0056*/ 0x1001041dU, -/*0057*/ 0xffffffffU, -/*0058*/ 0x0009041eU, -/*0059*/ 0x0020041fU, -/*005a*/ 0x00200420U, -/*005b*/ 0x00200421U, -/*005c*/ 0x00200422U, -/*005d*/ 0x00100423U, -/*005e*/ 0xffffffffU, -/*005f*/ 0x10010423U, -/*0060*/ 0x18060423U, -/*0061*/ 0x00080424U, -/*0062*/ 0x00200425U, -/*0063*/ 0x00100426U, -/*0064*/ 0x100a0426U, -/*0065*/ 0x00060427U, -/*0066*/ 0x08070427U, -/*0067*/ 0x10080427U, -/*0068*/ 0x18080427U, -/*0069*/ 0x000a0428U, -/*006a*/ 0x10070428U, -/*006b*/ 0x18080428U, -/*006c*/ 0x00080429U, -/*006d*/ 0x08030429U, -/*006e*/ 0x100a0429U, -/*006f*/ 0x000a042aU, -/*0070*/ 0x0011042bU, -/*0071*/ 0x0009042cU, -/*0072*/ 0x1009042cU, -/*0073*/ 0x0010042dU, -/*0074*/ 0x100e042dU, -/*0075*/ 0x000e042eU, -/*0076*/ 0x0012042fU, -/*0077*/ 0x000a0430U, -/*0078*/ 0x100a0430U, -/*0079*/ 0x00020431U, -/*007a*/ 0x00200432U, -/*007b*/ 0x000b0433U, -/*007c*/ 0x100b0433U, -/*007d*/ 0x00200434U, -/*007e*/ 0x00120435U, -/*007f*/ 0x00200436U, -/*0080*/ 0x00200437U, -/*0081*/ 0x00080438U, -/*0082*/ 0x08010438U, -/*0083*/ 0x10010438U, -/*0084*/ 0x18010438U, -/*0085*/ 0x00080439U, -/*0086*/ 0x080c0439U, -/*0087*/ 0x000c043aU, -/*0088*/ 0x100c043aU, -/*0089*/ 0x000c043bU, -/*008a*/ 0x100c043bU, -/*008b*/ 0x000c043cU, -/*008c*/ 0x100c043cU, -/*008d*/ 0x000c043dU, -/*008e*/ 0x100c043dU, -/*008f*/ 0x000c043eU, -/*0090*/ 0x100c043eU, -/*0091*/ 0x000b043fU, -/*0092*/ 0x1009043fU, -/*0093*/ 0x00010440U, -/*0094*/ 0x000b0441U, -/*0095*/ 0x100b0441U, -/*0096*/ 0x000b0442U, -/*0097*/ 0x100b0442U, -/*0098*/ 0x000b0443U, -/*0099*/ 0x100b0443U, -/*009a*/ 0x000b0444U, -/*009b*/ 0x100b0444U, -/*009c*/ 0x000b0445U, -/*009d*/ 0x100a0445U, -/*009e*/ 0x00020446U, -/*009f*/ 0x080a0446U, -/*00a0*/ 0x000a0447U, -/*00a1*/ 0x100a0447U, -/*00a2*/ 0x000a0448U, -/*00a3*/ 0x100a0448U, -/*00a4*/ 0x000a0449U, -/*00a5*/ 0x100a0449U, -/*00a6*/ 0x000a044aU, -/*00a7*/ 0x100a044aU, -/*00a8*/ 0x000a044bU, -/*00a9*/ 0x100a044bU, -/*00aa*/ 0x000a044cU, -/*00ab*/ 0x100a044cU, -/*00ac*/ 0x000a044dU, -/*00ad*/ 0x100a044dU, -/*00ae*/ 0x000a044eU, -/*00af*/ 0x100a044eU, -/*00b0*/ 0x000a044fU, -/*00b1*/ 0x100a044fU, -/*00b2*/ 0x000a0450U, -/*00b3*/ 0x100a0450U, -/*00b4*/ 0x000a0451U, -/*00b5*/ 0x100a0451U, -/*00b6*/ 0x000a0452U, -/*00b7*/ 0x100a0452U, -/*00b8*/ 0x000a0453U, -/*00b9*/ 0x100a0453U, -/*00ba*/ 0x000a0454U, -/*00bb*/ 0x10040454U, -/*00bc*/ 0x18030454U, -/*00bd*/ 0x000a0455U, -/*00be*/ 0x100a0455U, -/*00bf*/ 0x00010456U, -/*00c0*/ 0x080a0456U, -/*00c1*/ 0x18040456U, -/*00c2*/ 0x000b0457U, -/*00c3*/ 0x100a0457U, -/*00c4*/ 0x00030458U, -/*00c5*/ 0x00080459U, -/*00c6*/ 0x08080459U, -/*00c7*/ 0x10080459U, -/*00c8*/ 0x18080459U, -/*00c9*/ 0x0008045aU, -/*00ca*/ 0xffffffffU, -/*00cb*/ 0x0808045aU, -/*00cc*/ 0x1001045aU, -/*00cd*/ 0x1808045aU, -/*00ce*/ 0x0008045bU, -/*00cf*/ 0x0802045bU, -/*00d0*/ 0x1002045bU, -/*00d1*/ 0x1805045bU, -/*00d2*/ 0x0005045cU, -/*00d3*/ 0xffffffffU, -/*00d4*/ 0x0804045cU, -/*00d5*/ 0x100a045cU, -/*00d6*/ 0x0006045dU, -/*00d7*/ 0x0808045dU, -/*00d8*/ 0x1008045dU, -/*00d9*/ 0x1804045dU, -/*00da*/ 0x0004045eU, -/*00db*/ 0x0805045eU, -/*00dc*/ 0x1004045eU, -/*00dd*/ 0x1805045eU, -/*00de*/ 0x000a045fU, -/*00df*/ 0x100a045fU, -/*00e0*/ 0x00080460U, -/*00e1*/ 0xffffffffU, -/*00e2*/ 0x08040460U, -/*00e3*/ 0xffffffffU, -/*00e4*/ 0xffffffffU, -/*00e5*/ 0x00050600U, -/*00e6*/ 0x08050600U, -/*00e7*/ 0x10050600U, -/*00e8*/ 0x18050600U, -/*00e9*/ 0x00050601U, -/*00ea*/ 0x08050601U, -/*00eb*/ 0x100b0601U, -/*00ec*/ 0x00010602U, -/*00ed*/ 0x08030602U, -/*00ee*/ 0x00200603U, -/*00ef*/ 0x00100604U, -/*00f0*/ 0x10040604U, -/*00f1*/ 0x000a0605U, -/*00f2*/ 0x10090605U, -/*00f3*/ 0x00080606U, -/*00f4*/ 0x08030606U, -/*00f5*/ 0x10030606U, -/*00f6*/ 0x18010606U, -/*00f7*/ 0x00010607U, -/*00f8*/ 0x08070607U, -/*00f9*/ 0x10070607U, -/*00fa*/ 0x18050607U, -/*00fb*/ 0x00010608U, -/*00fc*/ 0x08020608U, -/*00fd*/ 0x10030608U, -/*00fe*/ 0x18010608U, -/*00ff*/ 0x000f0609U, -/*0100*/ 0x0020060aU, -/*0101*/ 0x0020060bU, -/*0102*/ 0x000b060cU, -/*0103*/ 0x100b060cU, -/*0104*/ 0x000b060dU, -/*0105*/ 0x0018060eU, -/*0106*/ 0x0018060fU, -/*0107*/ 0xffffffffU, -/*0108*/ 0xffffffffU, -/*0109*/ 0xffffffffU, -/*010a*/ 0xffffffffU, -/*010b*/ 0xffffffffU, -/*010c*/ 0x1802060fU, -/*010d*/ 0x00020610U, -/*010e*/ 0x08040610U, -/*010f*/ 0x10040610U, -/*0110*/ 0x18010610U, -/*0111*/ 0x00010611U, -/*0112*/ 0x08010611U, -/*0113*/ 0x10030611U, -/*0114*/ 0x00200612U, -/*0115*/ 0x00200613U, -/*0116*/ 0xffffffffU, -/*0117*/ 0x00140614U, -/*0118*/ 0x00140615U, -/*0119*/ 0x00140616U, -/*011a*/ 0x00140617U, -/*011b*/ 0x00140618U, -/*011c*/ 0x00140619U, -/*011d*/ 0x0014061aU, -/*011e*/ 0x0014061bU, -/*011f*/ 0x0018061cU, -/*0120*/ 0x000a061dU, -/*0121*/ 0x1006061dU, -/*0122*/ 0x1806061dU, -/*0123*/ 0x0006061eU, -/*0124*/ 0xffffffffU, -/*0125*/ 0x0806061eU, -/*0126*/ 0x0008061fU, -/*0127*/ 0x080b061fU, -/*0128*/ 0x000b0620U, -/*0129*/ 0x100b0620U, -/*012a*/ 0x000b0621U, -/*012b*/ 0x100b0621U, -/*012c*/ 0x000b0622U, -/*012d*/ 0x10040622U, -/*012e*/ 0x000a0623U, -/*012f*/ 0x10060623U, -/*0130*/ 0x18080623U, -/*0131*/ 0x00080624U, -/*0132*/ 0x08040624U, -/*0133*/ 0x00020680U, -/*0134*/ 0x00010681U, -/*0135*/ 0x08010681U, -/*0136*/ 0x10020681U, -/*0137*/ 0x18050681U, -/*0138*/ 0x00050682U, -/*0139*/ 0x08050682U, -/*013a*/ 0x10050682U, -/*013b*/ 0x000b0683U, -/*013c*/ 0x10050683U, -/*013d*/ 0x18010683U, -/*013e*/ 0x00010684U, -/*013f*/ 0xffffffffU, -/*0140*/ 0x08010684U, -/*0141*/ 0x10010684U, -/*0142*/ 0x18040684U, -/*0143*/ 0x000b0685U, -/*0144*/ 0x100b0685U, -/*0145*/ 0x000b0686U, -/*0146*/ 0x10040686U, -/*0147*/ 0x000b0687U, -/*0148*/ 0x10040687U, -/*0149*/ 0x18010687U, -/*014a*/ 0x00010688U, -/*014b*/ 0x08010688U, -/*014c*/ 0x00200689U, -/*014d*/ 0x0020068aU, -/*014e*/ 0x0008068bU, -/*014f*/ 0x080a068bU, -/*0150*/ 0x1805068bU, -/*0151*/ 0x000a068cU, -/*0152*/ 0x1003068cU, -/*0153*/ 0x1803068cU, -/*0154*/ 0x0001068dU, -/*0155*/ 0x0802068dU, -/*0156*/ 0x1001068dU, -/*0157*/ 0x1801068dU, -/*0158*/ 0x0001068eU, -/*0159*/ 0x0802068eU, -/*015a*/ 0x1001068eU, -/*015b*/ 0x0004068fU, -/*015c*/ 0x0804068fU, -/*015d*/ 0x1004068fU, -/*015e*/ 0x1804068fU, -/*015f*/ 0x00010690U, -/*0160*/ 0x08010690U, -/*0161*/ 0x10010690U, -/*0162*/ 0x00200691U, -/*0163*/ 0x00200692U, -/*0164*/ 0x00200693U, -/*0165*/ 0x00200694U, -/*0166*/ 0xffffffffU, -/*0167*/ 0x1801068eU, -/*0168*/ 0x000d0696U, -/*0169*/ 0x100d0696U, -/*016a*/ 0x000d0697U, -/*016b*/ 0x00050698U, -/*016c*/ 0x00010699U, -/*016d*/ 0x080e0699U, -/*016e*/ 0x000e069aU, -/*016f*/ 0x100e069aU, -/*0170*/ 0x000e069bU, -/*0171*/ 0x100e069bU, -/*0172*/ 0x0004069cU, -/*0173*/ 0x0804069cU, -/*0174*/ 0x1004069cU, -/*0175*/ 0x1804069cU, -/*0176*/ 0x0004069dU, -/*0177*/ 0x080b069dU, -/*0178*/ 0x000b069eU, -/*0179*/ 0x100b069eU, -/*017a*/ 0x000b069fU, -/*017b*/ 0xffffffffU, -/*017c*/ 0xffffffffU, -/*017d*/ 0xffffffffU, -/*017e*/ 0xffffffffU, -/*017f*/ 0x000d06a0U, -/*0180*/ 0x100d06a0U, -/*0181*/ 0x000d06a1U, -/*0182*/ 0x101006a1U, -/*0183*/ 0x00080695U, -/*0184*/ 0x08080695U, -/*0185*/ 0x001006a2U, -/*0186*/ 0x101006a2U, -/*0187*/ 0x001006a3U, -/*0188*/ 0x101006a3U, -/*0189*/ 0x001006a4U, -/*018a*/ 0x100306a4U, -/*018b*/ 0x180406a4U, -/*018c*/ 0x000106a5U, -/*018d*/ 0x080806a5U, -/*018e*/ 0x100106a5U, -/*018f*/ 0x180506a5U, -/*0190*/ 0x000106a6U, -/*0191*/ 0x081406a6U, -/*0192*/ 0x000a06a7U, -/*0193*/ 0x100c06a7U, -/*0194*/ 0x001206a8U, -/*0195*/ 0x001406a9U, -/*0196*/ 0x001206aaU, -/*0197*/ 0x001106abU, -/*0198*/ 0x001106acU, -/*0199*/ 0x001206adU, -/*019a*/ 0x001206aeU, -/*019b*/ 0x001206afU, -/*019c*/ 0x001206b0U, -/*019d*/ 0x001206b1U, -/*019e*/ 0x001206b2U, -/*019f*/ 0x001206b3U, -/*01a0*/ 0x001206b4U, -/*01a1*/ 0x001206b5U, -/*01a2*/ 0x001206b6U, -/*01a3*/ 0x000e06b7U, -/*01a4*/ 0x100d06b7U, -/*01a5*/ 0x002006b8U, -/*01a6*/ 0x001706b9U, -/*01a7*/ 0x000906baU, -/*01a8*/ 0x100106baU, -/*01a9*/ 0x180106baU, -/*01aa*/ 0x002006bbU, -/*01ab*/ 0x000806bcU, -/*01ac*/ 0x080306bcU, -/*01ad*/ 0x100306bcU, -/*01ae*/ 0x001806bdU, -/*01af*/ 0x001806beU, -/*01b0*/ 0x180706beU, -/*01b1*/ 0x000506bfU, -/*01b2*/ 0x080806bfU, -/*01b3*/ 0x100806bfU, -/*01b4*/ 0x180806bfU, -/*01b5*/ 0x000106c0U, -/*01b6*/ 0x080106c0U, -/*01b7*/ 0x002006c1U, -/*01b8*/ 0xffffffffU, -/*01b9*/ 0xffffffffU, -/*01ba*/ 0xffffffffU, -/*01bb*/ 0xffffffffU, -/*01bc*/ 0xffffffffU, -/*01bd*/ 0xffffffffU, -/*01be*/ 0xffffffffU, -/*01bf*/ 0x001006c2U, -/*01c0*/ 0x100106c2U, -/*01c1*/ 0x180106c2U, -/*01c2*/ 0x000206c3U, -/*01c3*/ 0x080406c3U, -/*01c4*/ 0x100906c3U, -/*01c5*/ 0x000706c4U, -/*01c6*/ 0x080406c4U, -/*01c7*/ 0x002006c5U, -/*01c8*/ 0x000106c6U, -/*01c9*/ 0x080206c6U, -/*01ca*/ 0x100606c6U, -/*01cb*/ 0x001006c7U, -/*01cc*/ 0x100106c7U, -/*01cd*/ 0x002006c8U, -/*01ce*/ 0x000806c9U, -/*01cf*/ 0x080106c9U, -/*01d0*/ 0x100506c9U, -/*01d1*/ 0xffffffffU, -/*01d2*/ 0x180206c9U, -/*01d3*/ 0x000106caU, -/*01d4*/ 0x002006cbU, -/*01d5*/ 0x000b06ccU, -/*01d6*/ 0x100106ccU, -/*01d7*/ 0x180306ccU, -/*01d8*/ 0x000806cdU, -/*01d9*/ 0x080206cdU, -/*01da*/ 0x100c06cdU, -/*01db*/ 0x000406ceU, -/*01dc*/ 0x080106ceU, -/*01dd*/ 0xffffffffU, -/*01de*/ 0x00010200U, -/*01df*/ 0x08040200U, -/*01e0*/ 0x10100200U, -/*01e1*/ 0x00010201U, -/*01e2*/ 0x08010201U, -/*01e3*/ 0x10010201U, -/*01e4*/ 0xffffffffU, -/*01e5*/ 0x00100202U, -/*01e6*/ 0x10080202U, -/*01e7*/ 0xffffffffU, -/*01e8*/ 0xffffffffU, -/*01e9*/ 0xffffffffU, -/*01ea*/ 0xffffffffU, -/*01eb*/ 0xffffffffU, -/*01ec*/ 0xffffffffU, -/*01ed*/ 0xffffffffU, -/*01ee*/ 0xffffffffU, -/*01ef*/ 0x00200203U, -/*01f0*/ 0x00100204U, -/*01f1*/ 0x00200205U, -/*01f2*/ 0x00100206U, -/*01f3*/ 0x00200207U, -/*01f4*/ 0x00100208U, -/*01f5*/ 0x00140209U, -/*01f6*/ 0x0020020aU, -/*01f7*/ 0x0020020bU, -/*01f8*/ 0x0020020cU, -/*01f9*/ 0x0020020dU, -/*01fa*/ 0x0014020eU, -/*01fb*/ 0x0020020fU, -/*01fc*/ 0x00200210U, -/*01fd*/ 0x00200211U, -/*01fe*/ 0x00200212U, -/*01ff*/ 0x00140213U, -/*0200*/ 0x00200214U, -/*0201*/ 0x00200215U, -/*0202*/ 0x00200216U, -/*0203*/ 0x00200217U, -/*0204*/ 0x00090218U, -/*0205*/ 0x10010218U, -/*0206*/ 0x00200219U, -/*0207*/ 0x0005021aU, -/*0208*/ 0x0801021aU, -/*0209*/ 0x1008021aU, -/*020a*/ 0x1808021aU, -/*020b*/ 0x001c021bU, -/*020c*/ 0x001c021cU, -/*020d*/ 0x001c021dU, -/*020e*/ 0x001c021eU, -/*020f*/ 0x001c021fU, -/*0210*/ 0x001c0220U, -/*0211*/ 0x001c0221U, -/*0212*/ 0x001c0222U, -/*0213*/ 0x001c0223U, -/*0214*/ 0x001c0224U, -/*0215*/ 0x001c0225U, -/*0216*/ 0x001c0226U, -/*0217*/ 0x001c0227U, -/*0218*/ 0x001c0228U, -/*0219*/ 0x001c0229U, -/*021a*/ 0x001c022aU, -/*021b*/ 0x0001022bU, -/*021c*/ 0x0801022bU, -/*021d*/ 0x1001022bU, -/*021e*/ 0x1804022bU, -/*021f*/ 0x0008022cU, -/*0220*/ 0x0808022cU, -/*0221*/ 0x1008022cU, -/*0222*/ 0x1804022cU, -/*0223*/ 0x0007022dU, -/*0224*/ 0xffffffffU, -/*0225*/ 0x0807022dU, -/*0226*/ 0x1007022dU, -/*0227*/ 0xffffffffU, -/*0228*/ 0x1807022dU, -/*0229*/ 0x0007022eU, -/*022a*/ 0xffffffffU, -/*022b*/ 0x0807022eU, -/*022c*/ 0x1002022eU, -/*022d*/ 0x1801022eU, -/*022e*/ 0x0001022fU, -/*022f*/ 0x080a022fU, -/*0230*/ 0x00140230U, -/*0231*/ 0x000a0231U, -/*0232*/ 0x00140232U, -/*0233*/ 0x000a0233U, -/*0234*/ 0x00140234U, -/*0235*/ 0x18010234U, -/*0236*/ 0x00100235U, -/*0237*/ 0x10050235U, -/*0238*/ 0x18010235U, -/*0239*/ 0x00010236U, -/*023a*/ 0x08010236U, -/*023b*/ 0x10010236U, -/*023c*/ 0x18010236U, -/*023d*/ 0x00010237U, -/*023e*/ 0x08010237U, -/*023f*/ 0x10020237U, -/*0240*/ 0x18020237U, -/*0241*/ 0x00020238U, -/*0242*/ 0x08020238U, -/*0243*/ 0x10020238U, -/*0244*/ 0x18030238U, -/*0245*/ 0x00010239U, -/*0246*/ 0x08010239U, -/*0247*/ 0x10010239U, -/*0248*/ 0x18010239U, -/*0249*/ 0xffffffffU, -/*024a*/ 0x0002023aU, -/*024b*/ 0x0801023aU, -/*024c*/ 0x1001023aU, -/*024d*/ 0xffffffffU, -/*024e*/ 0x1802023aU, -/*024f*/ 0x0001023bU, -/*0250*/ 0x0801023bU, -/*0251*/ 0xffffffffU, -/*0252*/ 0x1002023bU, -/*0253*/ 0x1801023bU, -/*0254*/ 0x0001023cU, -/*0255*/ 0xffffffffU, -/*0256*/ 0x0802023cU, -/*0257*/ 0x1007023cU, -/*0258*/ 0x1801023cU, -/*0259*/ 0x0001023dU, -/*025a*/ 0x0801023dU, -/*025b*/ 0x1001023dU, -/*025c*/ 0x1801023dU, -/*025d*/ 0x0001023eU, -/*025e*/ 0x0801023eU, -/*025f*/ 0x1001023eU, -/*0260*/ 0x1804023eU, -/*0261*/ 0x0004023fU, -/*0262*/ 0x0804023fU, -/*0263*/ 0x1001023fU, -/*0264*/ 0x1802023fU, -/*0265*/ 0x00060240U, -/*0266*/ 0x08060240U, -/*0267*/ 0x10020240U, -/*0268*/ 0x18020240U, -/*0269*/ 0x00020241U, -/*026a*/ 0xffffffffU, -/*026b*/ 0x08100241U, -/*026c*/ 0x18010241U, -/*026d*/ 0x00010242U, -/*026e*/ 0x08010242U, -/*026f*/ 0x10040242U, -/*0270*/ 0x18010242U, -/*0271*/ 0x00040243U, -/*0272*/ 0x08020243U, -/*0273*/ 0x10080243U, -/*0274*/ 0xffffffffU, -/*0275*/ 0xffffffffU, -/*0276*/ 0xffffffffU, -/*0277*/ 0x000a0244U, -/*0278*/ 0x00200245U, -/*0279*/ 0x00200246U, -/*027a*/ 0x00050247U, -/*027b*/ 0x08010247U, -/*027c*/ 0x10050247U, -/*027d*/ 0x18080247U, -/*027e*/ 0x00010248U, -/*027f*/ 0x08080248U, -/*0280*/ 0x10010248U, -/*0281*/ 0x18080248U, -/*0282*/ 0x00010249U, -/*0283*/ 0x08040249U, -/*0284*/ 0x10040249U, -/*0285*/ 0x18040249U, -/*0286*/ 0x0004024aU, -/*0287*/ 0x0804024aU, -/*0288*/ 0x1004024aU, -/*0289*/ 0x1804024aU, -/*028a*/ 0x0004024bU, -/*028b*/ 0x0804024bU, -/*028c*/ 0x1004024bU, -/*028d*/ 0x1801024bU, -/*028e*/ 0x0004024cU, -/*028f*/ 0x0804024cU, -/*0290*/ 0x1004024cU, -/*0291*/ 0x1804024cU, -/*0292*/ 0x0004024dU, -/*0293*/ 0x0804024dU, -/*0294*/ 0x1006024dU, -/*0295*/ 0x1806024dU, -/*0296*/ 0x0006024eU, -/*0297*/ 0x0806024eU, -/*0298*/ 0x1006024eU, -/*0299*/ 0x1806024eU, -/*029a*/ 0xffffffffU, -/*029b*/ 0x0001024fU, -/*029c*/ 0x0801024fU, -/*029d*/ 0x1002024fU, -/*029e*/ 0xffffffffU, -/*029f*/ 0xffffffffU, -/*02a0*/ 0xffffffffU, -/*02a1*/ 0xffffffffU, -/*02a2*/ 0xffffffffU, -/*02a3*/ 0xffffffffU, -/*02a4*/ 0xffffffffU, -/*02a5*/ 0xffffffffU, -/*02a6*/ 0x1804024fU, -/*02a7*/ 0x00040250U, -/*02a8*/ 0x08010250U, -/*02a9*/ 0x10010250U, -/*02aa*/ 0x18010250U, -/*02ab*/ 0x00010251U, -/*02ac*/ 0x08010251U, -/*02ad*/ 0x10010251U, -/*02ae*/ 0x18010251U, -/*02af*/ 0x00010252U, -/*02b0*/ 0x08010252U, -/*02b1*/ 0x10040252U, -/*02b2*/ 0x18040252U, -/*02b3*/ 0x000a0253U, -/*02b4*/ 0x00200254U, -/*02b5*/ 0x00040255U, -/*02b6*/ 0x08080255U, -/*02b7*/ 0x10020255U, -/*02b8*/ 0x18020255U, -/*02b9*/ 0x00020256U, -/*02ba*/ 0x08020256U, -/*02bb*/ 0x10020256U, -/*02bc*/ 0x18020256U, -/*02bd*/ 0xffffffffU, -/*02be*/ 0xffffffffU, -/*02bf*/ 0x00200257U, -/*02c0*/ 0x00020258U, -/*02c1*/ 0x08100258U, -/*02c2*/ 0x00100259U, -/*02c3*/ 0x10040259U, -/*02c4*/ 0x18040259U, -/*02c5*/ 0x0005025aU, -/*02c6*/ 0x0805025aU, -/*02c7*/ 0x0020025bU, -/*02c8*/ 0x0020025cU, -/*02c9*/ 0x0020025dU, -/*02ca*/ 0x0020025eU, -/*02cb*/ 0x0001025fU, -/*02cc*/ 0x0801025fU, -/*02cd*/ 0x1007025fU, -/*02ce*/ 0x1807025fU, -/*02cf*/ 0x00070260U, -/*02d0*/ 0x08070260U, -/*02d1*/ 0x10070260U, -/*02d2*/ 0x18070260U, -/*02d3*/ 0x00070261U, -/*02d4*/ 0x08070261U, -/*02d5*/ 0x10070261U, -/*02d6*/ 0x18070261U, -/*02d7*/ 0x00070262U, -/*02d8*/ 0x08070262U, -/*02d9*/ 0x10070262U, -/*02da*/ 0x18070262U, -/*02db*/ 0x00030263U, -/*02dc*/ 0x08030263U, -/*02dd*/ 0x10030263U, -/*02de*/ 0xffffffffU, -/*02df*/ 0x18010263U, -/*02e0*/ 0x00020264U, -/*02e1*/ 0x08010264U, -/*02e2*/ 0x10040264U, -/*02e3*/ 0x18020264U, -/*02e4*/ 0x00010265U, -/*02e5*/ 0x08010265U, -/*02e6*/ 0x10010265U, -/*02e7*/ 0x18010265U, -/*02e8*/ 0x00040266U, -/*02e9*/ 0x08080266U, -/*02ea*/ 0x100a0266U, -/*02eb*/ 0x000a0267U, -/*02ec*/ 0x100a0267U, -/*02ed*/ 0x000a0268U, -/*02ee*/ 0x100a0268U, -/*02ef*/ 0x000a0269U, -/*02f0*/ 0x0020026aU, -/*02f1*/ 0x0020026bU, -/*02f2*/ 0x0001026cU, -/*02f3*/ 0x0802026cU, -/*02f4*/ 0x1002026cU, -/*02f5*/ 0x1802026cU, -/*02f6*/ 0xffffffffU, -/*02f7*/ 0x0002026dU, -/*02f8*/ 0x0810026dU, -/*02f9*/ 0x1805026dU, -/*02fa*/ 0x0006026eU, -/*02fb*/ 0x0805026eU, -/*02fc*/ 0x1005026eU, -/*02fd*/ 0x000e026fU, -/*02fe*/ 0x1005026fU, -/*02ff*/ 0x000e0270U, -/*0300*/ 0x10050270U, -/*0301*/ 0x000e0271U, -/*0302*/ 0x10050271U, -/*0303*/ 0x18010271U, -/*0304*/ 0x00050272U, -/*0305*/ 0x08050272U, -/*0306*/ 0x100a0272U, -/*0307*/ 0x000a0273U, -/*0308*/ 0x10050273U, -/*0309*/ 0x18050273U, -/*030a*/ 0x000a0274U, -/*030b*/ 0x100a0274U, -/*030c*/ 0x00050275U, -/*030d*/ 0x08050275U, -/*030e*/ 0x100a0275U, -/*030f*/ 0x000a0276U, -/*0310*/ 0xffffffffU, -/*0311*/ 0xffffffffU, -/*0312*/ 0xffffffffU, -/*0313*/ 0xffffffffU, -/*0314*/ 0xffffffffU, -/*0315*/ 0xffffffffU, -/*0316*/ 0x10070276U, -/*0317*/ 0x18070276U, -/*0318*/ 0x00040277U, -/*0319*/ 0x08040277U, -/*031a*/ 0xffffffffU, -/*031b*/ 0xffffffffU, -/*031c*/ 0xffffffffU, -/*031d*/ 0x10040277U, -/*031e*/ 0x18080277U, -/*031f*/ 0x00080278U, -/*0320*/ 0x08040278U, -/*0321*/ 0xffffffffU, -/*0322*/ 0xffffffffU, -/*0323*/ 0xffffffffU, -/*0324*/ 0x10040278U, -/*0325*/ 0xffffffffU, -/*0326*/ 0xffffffffU, -/*0327*/ 0xffffffffU, -/*0328*/ 0x18040278U, -/*0329*/ 0xffffffffU, -/*032a*/ 0xffffffffU, -/*032b*/ 0xffffffffU, -/*032c*/ 0x00040279U, -/*032d*/ 0x08050279U, -/*032e*/ 0x10070279U, -/*032f*/ 0x18080279U, -/*0330*/ 0x0010027aU, -/*0331*/ 0x1008027aU, -/*0332*/ 0x0010027bU, -/*0333*/ 0x1008027bU, -/*0334*/ 0x0010027cU, -/*0335*/ 0x1008027cU, -/*0336*/ 0x1808027cU, -/*0337*/ 0x0001027dU, -/*0338*/ 0x0801027dU, -/*0339*/ 0x1006027dU, -/*033a*/ 0x1806027dU, -/*033b*/ 0x0006027eU, -/*033c*/ 0x0801027eU, -/*033d*/ 0x1001027eU, -/*033e*/ 0x1803027eU, -/*033f*/ 0x000a027fU, -/*0340*/ 0x100a027fU, -/*0341*/ 0x000a0280U, -/*0342*/ 0xffffffffU, -/*0343*/ 0x100a0280U, -/*0344*/ 0x00040281U, -/*0345*/ 0x08010281U, -/*0346*/ 0x10040281U, -/*0347*/ 0xffffffffU, -/*0348*/ 0xffffffffU, -/*0349*/ 0xffffffffU, -/*034a*/ 0xffffffffU, -/*034b*/ 0xffffffffU, -/*034c*/ 0xffffffffU, -/*034d*/ 0x18070281U, -/*034e*/ 0x00070282U, -/*034f*/ 0x08050282U, -/*0350*/ 0x10050282U, -/*0351*/ 0xffffffffU, -/*0352*/ 0xffffffffU, -/*0353*/ 0xffffffffU, -/*0354*/ 0x18040282U, -/*0355*/ 0x00010283U, -/*0356*/ 0x08010283U, -/*0357*/ 0x10020283U, -/*0358*/ 0x18080283U, -/*0359*/ 0x00200284U, -/*035a*/ 0x00200285U, -/*035b*/ 0x00100286U, -/*035c*/ 0x10020286U, -/*035d*/ 0x18020286U, -/*035e*/ 0x00020287U, -/*035f*/ 0xffffffffU, -/*0360*/ 0x08010287U, -/*0361*/ 0x10010287U, -/*0362*/ 0x18020287U, -/*0363*/ 0x00080288U, -/*0364*/ 0x08080288U, -/*0365*/ 0x10080288U, -/*0366*/ 0x18080288U, -/*0367*/ 0x00080289U, -/*0368*/ 0x08080289U, -/*0369*/ 0xffffffffU, -/*036a*/ 0x10080289U, -/*036b*/ 0x18080289U, -/*036c*/ 0x0008028aU, -/*036d*/ 0x0808028aU, -/*036e*/ 0x1008028aU, -/*036f*/ 0x1808028aU, -/*0370*/ 0xffffffffU, -/*0371*/ 0x0008028bU, -/*0372*/ 0x0808028bU, -/*0373*/ 0x1008028bU, -/*0374*/ 0x1808028bU, -/*0375*/ 0x0008028cU, -/*0376*/ 0x0808028cU, -/*0377*/ 0xffffffffU, -/*0378*/ 0x1008028cU, -/*0379*/ 0x1808028cU, -/*037a*/ 0x0008028dU, -/*037b*/ 0x0808028dU, -/*037c*/ 0x1008028dU, -/*037d*/ 0x1808028dU, -/*037e*/ 0x0008028eU, -/*037f*/ 0xffffffffU, -/*0380*/ 0x0808028eU, -/*0381*/ 0x1008028eU, -/*0382*/ 0x1808028eU, -/*0383*/ 0x0008028fU, -/*0384*/ 0x0808028fU, -/*0385*/ 0x1008028fU, -/*0386*/ 0xffffffffU, -/*0387*/ 0x1808028fU, -/*0388*/ 0x00080290U, -/*0389*/ 0x08080290U, -/*038a*/ 0x10080290U, -/*038b*/ 0x18080290U, -/*038c*/ 0x00080291U, -/*038d*/ 0xffffffffU, -/*038e*/ 0x08080291U, -/*038f*/ 0x10080291U, -/*0390*/ 0x18080291U, -/*0391*/ 0x00080292U, -/*0392*/ 0x08080292U, -/*0393*/ 0x10080292U, -/*0394*/ 0x18080292U, -/*0395*/ 0xffffffffU, -/*0396*/ 0x00080293U, -/*0397*/ 0x08080293U, -/*0398*/ 0x10080293U, -/*0399*/ 0x18080293U, -/*039a*/ 0x00080294U, -/*039b*/ 0x08080294U, -/*039c*/ 0xffffffffU, -/*039d*/ 0x10080294U, -/*039e*/ 0x18080294U, -/*039f*/ 0x00080295U, -/*03a0*/ 0x08080295U, -/*03a1*/ 0x10080295U, -/*03a2*/ 0x18080295U, -/*03a3*/ 0xffffffffU, -/*03a4*/ 0x00080296U, -/*03a5*/ 0x08080296U, -/*03a6*/ 0x10080296U, -/*03a7*/ 0x18080296U, -/*03a8*/ 0x00080297U, -/*03a9*/ 0x08080297U, -/*03aa*/ 0x10080297U, -/*03ab*/ 0xffffffffU, -/*03ac*/ 0x18080297U, -/*03ad*/ 0x00080298U, -/*03ae*/ 0x08080298U, -/*03af*/ 0x10080298U, -/*03b0*/ 0x18080298U, -/*03b1*/ 0x00080299U, -/*03b2*/ 0xffffffffU, -/*03b3*/ 0x08080299U, -/*03b4*/ 0x10080299U, -/*03b5*/ 0x18080299U, -/*03b6*/ 0x0008029aU, -/*03b7*/ 0x0808029aU, -/*03b8*/ 0x1008029aU, -/*03b9*/ 0xffffffffU, -/*03ba*/ 0x1808029aU, -/*03bb*/ 0x0002029bU, -/*03bc*/ 0x0803029bU, -/*03bd*/ 0x100a029bU, -/*03be*/ 0x000a029cU, -/*03bf*/ 0x100a029cU, -/*03c0*/ 0x0005029dU, -/*03c1*/ 0x0808029dU, -/*03c2*/ 0x1008029dU, -/*03c3*/ 0x1808029dU, -/*03c4*/ 0x0006029eU, -/*03c5*/ 0x0806029eU, -/*03c6*/ 0x0011029fU, -/*03c7*/ 0x1808029fU, -/*03c8*/ 0x000402a0U, -/*03c9*/ 0x080602a0U, -/*03ca*/ 0xffffffffU, -/*03cb*/ 0x100602a0U, -/*03cc*/ 0x180802a0U, -/*03cd*/ 0xffffffffU, -/*03ce*/ 0x000802a1U, -/*03cf*/ 0x080802a1U, -/*03d0*/ 0x100802a1U, -/*03d1*/ 0x180602a1U, -/*03d2*/ 0x000602a2U, -/*03d3*/ 0x081102a2U, -/*03d4*/ 0x000802a3U, -/*03d5*/ 0x080402a3U, -/*03d6*/ 0x100602a3U, -/*03d7*/ 0xffffffffU, -/*03d8*/ 0x180602a3U, -/*03d9*/ 0x000802a4U, -/*03da*/ 0xffffffffU, -/*03db*/ 0x080802a4U, -/*03dc*/ 0x100802a4U, -/*03dd*/ 0x180802a4U, -/*03de*/ 0x000602a5U, -/*03df*/ 0x080602a5U, -/*03e0*/ 0x001102a6U, -/*03e1*/ 0x180802a6U, -/*03e2*/ 0x000402a7U, -/*03e3*/ 0x080602a7U, -/*03e4*/ 0xffffffffU, -/*03e5*/ 0x100602a7U, -/*03e6*/ 0x180802a7U, -/*03e7*/ 0xffffffffU, -/*03e8*/ 0x000402a8U, -/*03e9*/ 0x080402a8U, -/*03ea*/ 0x100402a8U, -/*03eb*/ 0x180402a8U, -/*03ec*/ 0x000402a9U, -/*03ed*/ 0x080402a9U, -/*03ee*/ 0x100402a9U, -/*03ef*/ 0x180402a9U, -/*03f0*/ 0x000402aaU, -/*03f1*/ 0x080402aaU, -/*03f2*/ 0x100402aaU, -/*03f3*/ 0x180402aaU, -/*03f4*/ 0x000402abU, -/*03f5*/ 0x080402abU, -/*03f6*/ 0x100402abU, -/*03f7*/ 0x180402abU, -/*03f8*/ 0x000402acU, -/*03f9*/ 0x080402acU, -/*03fa*/ 0x100402acU, -/*03fb*/ 0x180402acU, -/*03fc*/ 0x001202adU, -/*03fd*/ 0x001102aeU, -/*03fe*/ 0x001202afU, -/*03ff*/ 0x002002b0U, -/*0400*/ 0x002002b1U, -/*0401*/ 0x002002b2U, -/*0402*/ 0x002002b3U, -/*0403*/ 0x002002b4U, -/*0404*/ 0x002002b5U, -/*0405*/ 0x002002b6U, -/*0406*/ 0x002002b7U, -/*0407*/ 0x002002b8U, -/*0408*/ 0x000202b9U, -/*0409*/ 0x080502b9U, -/*040a*/ 0x100502b9U, -/*040b*/ 0x180102b9U, -/*040c*/ 0x000402baU, -/*040d*/ 0x080402baU, -/*040e*/ 0x100402baU, -/*040f*/ 0x180402baU, -/*0410*/ 0x000402bbU, -/*0411*/ 0x080402bbU, -/*0412*/ 0x100402bbU, -/*0413*/ 0x180402bbU, -/*0414*/ 0xffffffffU, -/*0415*/ 0xffffffffU, -/*0416*/ 0xffffffffU, -/*0417*/ 0xffffffffU, -/*0418*/ 0xffffffffU, -/*0419*/ 0xffffffffU, -/*041a*/ 0x000402bcU, -/*041b*/ 0x080402bcU, -/*041c*/ 0x100402bcU, -/*041d*/ 0x180402bcU, -/*041e*/ 0x000402bdU, -/*041f*/ 0x080402bdU, -/*0420*/ 0x100402bdU, -/*0421*/ 0x180402bdU, -/*0422*/ 0x000102beU, -/*0423*/ 0x080202beU, -/*0424*/ 0x100202beU, -/*0425*/ 0x180202beU, -/*0426*/ 0x000202bfU, -/*0427*/ 0x080102bfU, -/*0428*/ 0x100402bfU, -/*0429*/ 0x001002c0U, -/*042a*/ 0x002002c1U, -/*042b*/ 0x001002c2U, -/*042c*/ 0x002002c3U, -/*042d*/ 0x001002c4U, -/*042e*/ 0x002002c5U, -/*042f*/ 0x000702c6U, -/*0430*/ 0x080102c6U, -/*0431*/ 0x100202c6U, -/*0432*/ 0x180602c6U, -/*0433*/ 0x000102c7U, -/*0434*/ 0x080102c7U, -/*0435*/ 0x002002c8U, -/*0436*/ 0x000202c9U, -/*0437*/ 0x002002caU, -/*0438*/ 0x002002cbU, -/*0439*/ 0x000c02ccU, -/*043a*/ 0x100c02ccU, -/*043b*/ 0x002002cdU, -/*043c*/ 0x000302ceU, -/*043d*/ 0x002002cfU, -/*043e*/ 0x000302d0U, -/*043f*/ 0x002002d1U, -/*0440*/ 0x000302d2U, -/*0441*/ 0x002002d3U, -/*0442*/ 0x000302d4U, -/*0443*/ 0x002002d5U, -/*0444*/ 0x000302d6U, -/*0445*/ 0x002002d7U, -/*0446*/ 0x000302d8U, -/*0447*/ 0x002002d9U, -/*0448*/ 0x000302daU, -/*0449*/ 0x002002dbU, -/*044a*/ 0x000302dcU, -/*044b*/ 0x002002ddU, -/*044c*/ 0x000302deU, -/*044d*/ 0x002002dfU, -/*044e*/ 0x000302e0U, -/*044f*/ 0x080302e0U, -/*0450*/ 0x100202e0U, -/*0451*/ 0x180202e0U, -/*0452*/ 0x002002e1U, -/*0453*/ 0x002002e2U, -/*0454*/ 0x002002e3U, -/*0455*/ 0x002002e4U, -/*0456*/ 0x000402e5U, -/*0457*/ 0x001e02e6U, -/*0458*/ 0x001e02e7U, -/*0459*/ 0x001e02e8U, -/*045a*/ 0x001e02e9U, -/*045b*/ 0x001e02eaU, -/*045c*/ 0x001e02ebU, -/*045d*/ 0x001e02ecU, -/*045e*/ 0x001e02edU, -/*045f*/ 0x000402eeU, -/*0460*/ 0xffffffffU, -/*0461*/ 0xffffffffU, -/*0462*/ 0xffffffffU, -/*0463*/ 0xffffffffU, -/*0464*/ 0x080402eeU, -/*0465*/ 0x100102eeU, -/*0466*/ 0x180802eeU, -/*0467*/ 0x000402efU, -/*0468*/ 0x080102efU, -/*0469*/ 0x100802efU, -/*046a*/ 0x180402efU, -/*046b*/ 0x000102f0U, -/*046c*/ 0x080802f0U, -/*046d*/ 0x100402f0U, -/*046e*/ 0x180102f0U, -/*046f*/ 0x000802f1U, -/*0470*/ 0x080402f1U, -/*0471*/ 0x100102f1U, -/*0472*/ 0x180802f1U, -/*0473*/ 0x000402f2U, -/*0474*/ 0x080102f2U, -/*0475*/ 0x100802f2U, -/*0476*/ 0x180402f2U, -/*0477*/ 0x000102f3U, -/*0478*/ 0x080802f3U, -/*0479*/ 0x100402f3U, -/*047a*/ 0x180102f3U, -/*047b*/ 0x000802f4U, -/*047c*/ 0x080802f4U, -/*047d*/ 0x100102f4U, -/*047e*/ 0x180502f4U, -/*047f*/ 0xffffffffU, -/*0480*/ 0xffffffffU, -/*0481*/ 0xffffffffU, -/*0482*/ 0xffffffffU, -/*0483*/ 0xffffffffU, -/*0484*/ 0xffffffffU, -/*0485*/ 0xffffffffU, -/*0486*/ 0xffffffffU, -/*0487*/ 0xffffffffU, -/*0488*/ 0xffffffffU, -/*0489*/ 0xffffffffU, -/*048a*/ 0xffffffffU, -/*048b*/ 0xffffffffU, -/*048c*/ 0xffffffffU, -/*048d*/ 0xffffffffU, -/*048e*/ 0xffffffffU, -/*048f*/ 0xffffffffU, -/*0490*/ 0xffffffffU, -/*0491*/ 0xffffffffU, -/*0492*/ 0xffffffffU, -/*0493*/ 0xffffffffU, -/*0494*/ 0xffffffffU, - }, - { -/*0000*/ 0x00200800U, -/*0001*/ 0x00040801U, -/*0002*/ 0x080b0801U, -/*0003*/ 0x000a0802U, -/*0004*/ 0x10020802U, -/*0005*/ 0x18010802U, -/*0006*/ 0x00060803U, -/*0007*/ 0x08060803U, -/*0008*/ 0x10060803U, -/*0009*/ 0x18060803U, -/*000a*/ 0x00060804U, -/*000b*/ 0x08060804U, -/*000c*/ 0x10050804U, -/*000d*/ 0x18060804U, -/*000e*/ 0x00060805U, -/*000f*/ 0x08040805U, -/*0010*/ 0x10030805U, -/*0011*/ 0x00180806U, -/*0012*/ 0x18030806U, -/*0013*/ 0x00180807U, -/*0014*/ 0x18020807U, -/*0015*/ 0x0801085eU, -/*0016*/ 0x00020808U, -/*0017*/ 0x08010808U, -/*0018*/ 0x10010808U, -/*0019*/ 0x18020808U, -/*001a*/ 0x00050809U, -/*001b*/ 0x08050809U, -/*001c*/ 0x10040809U, -/*001d*/ 0xffffffffU, -/*001e*/ 0x18040809U, -/*001f*/ 0x0002080aU, -/*0020*/ 0x0805080aU, -/*0021*/ 0x1009080aU, -/*0022*/ 0x0001080bU, -/*0023*/ 0x0020080cU, -/*0024*/ 0x001c080dU, -/*0025*/ 0x0001080eU, -/*0026*/ 0x0807080eU, -/*0027*/ 0x1009080eU, -/*0028*/ 0x000a080fU, -/*0029*/ 0x1005080fU, -/*002a*/ 0x1801080fU, -/*002b*/ 0x10010810U, -/*002c*/ 0x18020810U, -/*002d*/ 0x00090810U, -/*002e*/ 0x00090811U, -/*002f*/ 0x10020811U, -/*0030*/ 0x00200812U, -/*0031*/ 0x00010813U, -/*0032*/ 0x08020813U, -/*0033*/ 0x00200814U, -/*0034*/ 0x00200815U, -/*0035*/ 0x00200816U, -/*0036*/ 0x00200817U, -/*0037*/ 0xffffffffU, -/*0038*/ 0xffffffffU, -/*0039*/ 0xffffffffU, -/*003a*/ 0xffffffffU, -/*003b*/ 0x00030818U, -/*003c*/ 0x08010818U, -/*003d*/ 0x10040818U, -/*003e*/ 0x18030818U, -/*003f*/ 0x00040819U, -/*0040*/ 0x08040819U, -/*0041*/ 0x10040819U, -/*0042*/ 0x18040819U, -/*0043*/ 0x0001081aU, -/*0044*/ 0x0801081aU, -/*0045*/ 0x1006081aU, -/*0046*/ 0x1804081aU, -/*0047*/ 0x0008081bU, -/*0048*/ 0x0806081bU, -/*0049*/ 0x1004081bU, -/*004a*/ 0x1806081bU, -/*004b*/ 0x0004081cU, -/*004c*/ 0x0802081cU, -/*004d*/ 0x1005081cU, -/*004e*/ 0x1808081cU, -/*004f*/ 0xffffffffU, -/*0050*/ 0x0006081dU, -/*0051*/ 0x0803081dU, -/*0052*/ 0x100b081dU, -/*0053*/ 0x0004081eU, -/*0054*/ 0x0804081eU, -/*0055*/ 0x1004081eU, -/*0056*/ 0x1801081eU, -/*0057*/ 0xffffffffU, -/*0058*/ 0x0009081fU, -/*0059*/ 0x00200820U, -/*005a*/ 0x00200821U, -/*005b*/ 0x00200822U, -/*005c*/ 0x00200823U, -/*005d*/ 0x00100824U, -/*005e*/ 0xffffffffU, -/*005f*/ 0x10010824U, -/*0060*/ 0x18060824U, -/*0061*/ 0x00080825U, -/*0062*/ 0x00200826U, -/*0063*/ 0x00100827U, -/*0064*/ 0x100b0827U, -/*0065*/ 0x00070828U, -/*0066*/ 0x08070828U, -/*0067*/ 0x10090828U, -/*0068*/ 0x00090829U, -/*0069*/ 0x100b0829U, -/*006a*/ 0x0007082aU, -/*006b*/ 0x0808082aU, -/*006c*/ 0x1009082aU, -/*006d*/ 0x0003082bU, -/*006e*/ 0x080a082bU, -/*006f*/ 0x000a082cU, -/*0070*/ 0x0011082dU, -/*0071*/ 0x000a082eU, -/*0072*/ 0x100a082eU, -/*0073*/ 0x0010082fU, -/*0074*/ 0x100e082fU, -/*0075*/ 0x000e0830U, -/*0076*/ 0x00120831U, -/*0077*/ 0x000a0832U, -/*0078*/ 0x100a0832U, -/*0079*/ 0x00020833U, -/*007a*/ 0x00200834U, -/*007b*/ 0x000b0835U, -/*007c*/ 0x100b0835U, -/*007d*/ 0x00200836U, -/*007e*/ 0x00130837U, -/*007f*/ 0x00200838U, -/*0080*/ 0x00200839U, -/*0081*/ 0x0008083aU, -/*0082*/ 0x0801083aU, -/*0083*/ 0x1001083aU, -/*0084*/ 0x1801083aU, -/*0085*/ 0x0008083bU, -/*0086*/ 0x080c083bU, -/*0087*/ 0x000c083cU, -/*0088*/ 0x100c083cU, -/*0089*/ 0x000c083dU, -/*008a*/ 0x100c083dU, -/*008b*/ 0x000c083eU, -/*008c*/ 0x100c083eU, -/*008d*/ 0x000c083fU, -/*008e*/ 0x100c083fU, -/*008f*/ 0x000c0840U, -/*0090*/ 0x100c0840U, -/*0091*/ 0x000b0841U, -/*0092*/ 0x10090841U, -/*0093*/ 0x00010842U, -/*0094*/ 0x000b0843U, -/*0095*/ 0x100b0843U, -/*0096*/ 0x000b0844U, -/*0097*/ 0x100b0844U, -/*0098*/ 0x000b0845U, -/*0099*/ 0x100b0845U, -/*009a*/ 0x000b0846U, -/*009b*/ 0x100b0846U, -/*009c*/ 0x000b0847U, -/*009d*/ 0x100a0847U, -/*009e*/ 0x00020848U, -/*009f*/ 0x080a0848U, -/*00a0*/ 0x000a0849U, -/*00a1*/ 0x100a0849U, -/*00a2*/ 0x000a084aU, -/*00a3*/ 0x100a084aU, -/*00a4*/ 0x000a084bU, -/*00a5*/ 0x100a084bU, -/*00a6*/ 0x000a084cU, -/*00a7*/ 0x100a084cU, -/*00a8*/ 0x000a084dU, -/*00a9*/ 0x100a084dU, -/*00aa*/ 0x000a084eU, -/*00ab*/ 0x100a084eU, -/*00ac*/ 0x000a084fU, -/*00ad*/ 0x100a084fU, -/*00ae*/ 0x000a0850U, -/*00af*/ 0x100a0850U, -/*00b0*/ 0x000a0851U, -/*00b1*/ 0x100a0851U, -/*00b2*/ 0x000a0852U, -/*00b3*/ 0x100a0852U, -/*00b4*/ 0x000a0853U, -/*00b5*/ 0x100a0853U, -/*00b6*/ 0x000a0854U, -/*00b7*/ 0x100a0854U, -/*00b8*/ 0x000a0855U, -/*00b9*/ 0x100a0855U, -/*00ba*/ 0x000a0856U, -/*00bb*/ 0x10040856U, -/*00bc*/ 0x18030856U, -/*00bd*/ 0x000a0857U, -/*00be*/ 0x100a0857U, -/*00bf*/ 0x00010858U, -/*00c0*/ 0x080a0858U, -/*00c1*/ 0x18040858U, -/*00c2*/ 0x000b0859U, -/*00c3*/ 0x100a0859U, -/*00c4*/ 0x0003085aU, -/*00c5*/ 0x0008085bU, -/*00c6*/ 0x0808085bU, -/*00c7*/ 0x1008085bU, -/*00c8*/ 0x1808085bU, -/*00c9*/ 0x0008085cU, -/*00ca*/ 0x0808085cU, -/*00cb*/ 0x1008085cU, -/*00cc*/ 0x1801085cU, -/*00cd*/ 0x0008085dU, -/*00ce*/ 0x0808085dU, -/*00cf*/ 0x1002085dU, -/*00d0*/ 0x1802085dU, -/*00d1*/ 0x0005085eU, -/*00d2*/ 0x1005085eU, -/*00d3*/ 0x1805085eU, -/*00d4*/ 0x0004085fU, -/*00d5*/ 0x080b085fU, -/*00d6*/ 0x1806085fU, -/*00d7*/ 0x00080860U, -/*00d8*/ 0x08080860U, -/*00d9*/ 0x10040860U, -/*00da*/ 0x18040860U, -/*00db*/ 0x00060861U, -/*00dc*/ 0x08040861U, -/*00dd*/ 0x10050861U, -/*00de*/ 0x000a0862U, -/*00df*/ 0x100a0862U, -/*00e0*/ 0x00080863U, -/*00e1*/ 0x08010863U, -/*00e2*/ 0x10040863U, -/*00e3*/ 0x00020864U, -/*00e4*/ 0x08030864U, -/*00e5*/ 0x00050a00U, -/*00e6*/ 0x08050a00U, -/*00e7*/ 0x10050a00U, -/*00e8*/ 0x18050a00U, -/*00e9*/ 0x00050a01U, -/*00ea*/ 0x08050a01U, -/*00eb*/ 0x100b0a01U, -/*00ec*/ 0x00010a02U, -/*00ed*/ 0x08030a02U, -/*00ee*/ 0x00200a03U, -/*00ef*/ 0x00100a04U, -/*00f0*/ 0x10040a04U, -/*00f1*/ 0x000b0a05U, -/*00f2*/ 0x10070a05U, -/*00f3*/ 0x00090a06U, -/*00f4*/ 0x10030a06U, -/*00f5*/ 0x18030a06U, -/*00f6*/ 0x00010a07U, -/*00f7*/ 0x08010a07U, -/*00f8*/ 0x10070a07U, -/*00f9*/ 0x18070a07U, -/*00fa*/ 0x00050a08U, -/*00fb*/ 0x08010a08U, -/*00fc*/ 0x10020a08U, -/*00fd*/ 0x18030a08U, -/*00fe*/ 0x00010a09U, -/*00ff*/ 0x080f0a09U, -/*0100*/ 0x00200a0aU, -/*0101*/ 0x00200a0bU, -/*0102*/ 0x000b0a0cU, -/*0103*/ 0x100b0a0cU, -/*0104*/ 0x000b0a0dU, -/*0105*/ 0x00180a0eU, -/*0106*/ 0x00180a0fU, -/*0107*/ 0xffffffffU, -/*0108*/ 0xffffffffU, -/*0109*/ 0xffffffffU, -/*010a*/ 0xffffffffU, -/*010b*/ 0xffffffffU, -/*010c*/ 0x18020a0fU, -/*010d*/ 0x00020a10U, -/*010e*/ 0x08040a10U, -/*010f*/ 0x10040a10U, -/*0110*/ 0x18010a10U, -/*0111*/ 0x00010a11U, -/*0112*/ 0x08010a11U, -/*0113*/ 0x10030a11U, -/*0114*/ 0x00200a12U, -/*0115*/ 0x00200a13U, -/*0116*/ 0xffffffffU, -/*0117*/ 0x00140a14U, -/*0118*/ 0x00140a15U, -/*0119*/ 0x00140a16U, -/*011a*/ 0x00140a17U, -/*011b*/ 0x00140a18U, -/*011c*/ 0x00140a19U, -/*011d*/ 0x00140a1aU, -/*011e*/ 0x00140a1bU, -/*011f*/ 0x001e0a1cU, -/*0120*/ 0x000a0a1dU, -/*0121*/ 0x10060a1dU, -/*0122*/ 0x18060a1dU, -/*0123*/ 0x00060a1eU, -/*0124*/ 0x08060a1eU, -/*0125*/ 0x10060a1eU, -/*0126*/ 0x00080a1fU, -/*0127*/ 0x080b0a1fU, -/*0128*/ 0x000b0a20U, -/*0129*/ 0x100b0a20U, -/*012a*/ 0x000b0a21U, -/*012b*/ 0x100b0a21U, -/*012c*/ 0x000b0a22U, -/*012d*/ 0x10040a22U, -/*012e*/ 0x000b0a23U, -/*012f*/ 0x10060a23U, -/*0130*/ 0x18080a23U, -/*0131*/ 0x00080a24U, -/*0132*/ 0x08040a24U, -/*0133*/ 0x00020b80U, -/*0134*/ 0x00010b81U, -/*0135*/ 0x08010b81U, -/*0136*/ 0x10020b81U, -/*0137*/ 0x18050b81U, -/*0138*/ 0x00050b82U, -/*0139*/ 0x08050b82U, -/*013a*/ 0x10050b82U, -/*013b*/ 0x000b0b83U, -/*013c*/ 0x10050b83U, -/*013d*/ 0x18010b83U, -/*013e*/ 0x00010b84U, -/*013f*/ 0x08010b84U, -/*0140*/ 0x10010b84U, -/*0141*/ 0x18010b84U, -/*0142*/ 0x00040b85U, -/*0143*/ 0x080b0b85U, -/*0144*/ 0x000b0b86U, -/*0145*/ 0x100b0b86U, -/*0146*/ 0x00040b87U, -/*0147*/ 0x080b0b87U, -/*0148*/ 0x18040b87U, -/*0149*/ 0x00010b88U, -/*014a*/ 0x08010b88U, -/*014b*/ 0x10010b88U, -/*014c*/ 0x00200b89U, -/*014d*/ 0x00200b8aU, -/*014e*/ 0x00080b8bU, -/*014f*/ 0x080a0b8bU, -/*0150*/ 0x18050b8bU, -/*0151*/ 0x000b0b8cU, -/*0152*/ 0x10030b8cU, -/*0153*/ 0x18030b8cU, -/*0154*/ 0x00010b8dU, -/*0155*/ 0x08020b8dU, -/*0156*/ 0x10010b8dU, -/*0157*/ 0x18010b8dU, -/*0158*/ 0x00010b8eU, -/*0159*/ 0xffffffffU, -/*015a*/ 0x08010b8eU, -/*015b*/ 0x18040b8eU, -/*015c*/ 0x00040b8fU, -/*015d*/ 0x08040b8fU, -/*015e*/ 0x10040b8fU, -/*015f*/ 0x18010b8fU, -/*0160*/ 0x00010b90U, -/*0161*/ 0x08010b90U, -/*0162*/ 0x00200b91U, -/*0163*/ 0x00200b92U, -/*0164*/ 0x00200b93U, -/*0165*/ 0x00200b94U, -/*0166*/ 0xffffffffU, -/*0167*/ 0x10010b8eU, -/*0168*/ 0x000d0b96U, -/*0169*/ 0x100d0b96U, -/*016a*/ 0x000d0b97U, -/*016b*/ 0x00050b98U, -/*016c*/ 0x00010b99U, -/*016d*/ 0x080e0b99U, -/*016e*/ 0x000e0b9aU, -/*016f*/ 0x100e0b9aU, -/*0170*/ 0x000e0b9bU, -/*0171*/ 0x100e0b9bU, -/*0172*/ 0x00040b9cU, -/*0173*/ 0x08040b9cU, -/*0174*/ 0x10040b9cU, -/*0175*/ 0x18040b9cU, -/*0176*/ 0x00040b9dU, -/*0177*/ 0x080b0b9dU, -/*0178*/ 0x000b0b9eU, -/*0179*/ 0x100b0b9eU, -/*017a*/ 0x000b0b9fU, -/*017b*/ 0x00040ba0U, -/*017c*/ 0x08040ba0U, -/*017d*/ 0x10040ba0U, -/*017e*/ 0x18040ba0U, -/*017f*/ 0x000d0ba1U, -/*0180*/ 0x100d0ba1U, -/*0181*/ 0x000d0ba2U, -/*0182*/ 0x10100ba2U, -/*0183*/ 0x00080b95U, -/*0184*/ 0x08080b95U, -/*0185*/ 0x00100ba3U, -/*0186*/ 0x10100ba3U, -/*0187*/ 0x00100ba4U, -/*0188*/ 0x10100ba4U, -/*0189*/ 0x00100ba5U, -/*018a*/ 0x10030ba5U, -/*018b*/ 0x18040ba5U, -/*018c*/ 0x00010ba6U, -/*018d*/ 0x08080ba6U, -/*018e*/ 0x10010ba6U, -/*018f*/ 0x000a0ba7U, -/*0190*/ 0x10010ba7U, -/*0191*/ 0x00140ba8U, -/*0192*/ 0x000b0ba9U, -/*0193*/ 0x100c0ba9U, -/*0194*/ 0x00120baaU, -/*0195*/ 0x00140babU, -/*0196*/ 0x00120bacU, -/*0197*/ 0x00110badU, -/*0198*/ 0x00110baeU, -/*0199*/ 0x00120bafU, -/*019a*/ 0x00120bb0U, -/*019b*/ 0x00120bb1U, -/*019c*/ 0x00120bb2U, -/*019d*/ 0x00120bb3U, -/*019e*/ 0x00120bb4U, -/*019f*/ 0x00120bb5U, -/*01a0*/ 0x00120bb6U, -/*01a1*/ 0x00120bb7U, -/*01a2*/ 0x00120bb8U, -/*01a3*/ 0x000e0bb9U, -/*01a4*/ 0x100d0bb9U, -/*01a5*/ 0x00200bbaU, -/*01a6*/ 0x00170bbbU, -/*01a7*/ 0x000d0bbcU, -/*01a8*/ 0x10010bbcU, -/*01a9*/ 0x18010bbcU, -/*01aa*/ 0x00200bbdU, -/*01ab*/ 0x00080bbeU, -/*01ac*/ 0x08030bbeU, -/*01ad*/ 0x10030bbeU, -/*01ae*/ 0x00180bbfU, -/*01af*/ 0x00180bc0U, -/*01b0*/ 0x18070bc0U, -/*01b1*/ 0x00070bc1U, -/*01b2*/ 0x08080bc1U, -/*01b3*/ 0x10080bc1U, -/*01b4*/ 0x18080bc1U, -/*01b5*/ 0x00010bc2U, -/*01b6*/ 0x08010bc2U, -/*01b7*/ 0x00200bc3U, -/*01b8*/ 0x00070bc4U, -/*01b9*/ 0x08140bc4U, -/*01ba*/ 0x00140bc5U, -/*01bb*/ 0x00190bc6U, -/*01bc*/ 0x00170bc7U, -/*01bd*/ 0x00110bc8U, -/*01be*/ 0x00110bc9U, -/*01bf*/ 0x00100bcaU, -/*01c0*/ 0x10010bcaU, -/*01c1*/ 0x18010bcaU, -/*01c2*/ 0x00020bcbU, -/*01c3*/ 0x08040bcbU, -/*01c4*/ 0x10090bcbU, -/*01c5*/ 0x00070bccU, -/*01c6*/ 0x08040bccU, -/*01c7*/ 0x00200bcdU, -/*01c8*/ 0x00010bceU, -/*01c9*/ 0x08020bceU, -/*01ca*/ 0x10060bceU, -/*01cb*/ 0x00100bcfU, -/*01cc*/ 0x10010bcfU, -/*01cd*/ 0x00200bd0U, -/*01ce*/ 0x00080bd1U, -/*01cf*/ 0x08010bd1U, -/*01d0*/ 0x10050bd1U, -/*01d1*/ 0x18030bd1U, -/*01d2*/ 0x00020bd2U, -/*01d3*/ 0xffffffffU, -/*01d4*/ 0x00200bd3U, -/*01d5*/ 0x000b0bd4U, -/*01d6*/ 0xffffffffU, -/*01d7*/ 0x10030bd4U, -/*01d8*/ 0x18080bd4U, -/*01d9*/ 0x00020bd5U, -/*01da*/ 0x080c0bd5U, -/*01db*/ 0x18040bd5U, -/*01dc*/ 0x00010bd6U, -/*01dd*/ 0x08050bd6U, -/*01de*/ 0x00010200U, -/*01df*/ 0x08040200U, -/*01e0*/ 0x10100200U, -/*01e1*/ 0x00010201U, -/*01e2*/ 0x08010201U, -/*01e3*/ 0x10010201U, -/*01e4*/ 0x18010201U, -/*01e5*/ 0x00100202U, -/*01e6*/ 0x10080202U, -/*01e7*/ 0x18010202U, -/*01e8*/ 0x00200203U, -/*01e9*/ 0x00200204U, -/*01ea*/ 0x00200205U, -/*01eb*/ 0x00200206U, -/*01ec*/ 0x00020207U, -/*01ed*/ 0x08010207U, -/*01ee*/ 0x10010207U, -/*01ef*/ 0x00200208U, -/*01f0*/ 0x00140209U, -/*01f1*/ 0x0020020aU, -/*01f2*/ 0x0014020bU, -/*01f3*/ 0x0020020cU, -/*01f4*/ 0x0014020dU, -/*01f5*/ 0x0014020eU, -/*01f6*/ 0x0020020fU, -/*01f7*/ 0x00200210U, -/*01f8*/ 0x00200211U, -/*01f9*/ 0x00200212U, -/*01fa*/ 0x00140213U, -/*01fb*/ 0x00200214U, -/*01fc*/ 0x00200215U, -/*01fd*/ 0x00200216U, -/*01fe*/ 0x00200217U, -/*01ff*/ 0x00140218U, -/*0200*/ 0x00200219U, -/*0201*/ 0x0020021aU, -/*0202*/ 0x0020021bU, -/*0203*/ 0x0020021cU, -/*0204*/ 0x0009021dU, -/*0205*/ 0x1001021dU, -/*0206*/ 0x0020021eU, -/*0207*/ 0x0005021fU, -/*0208*/ 0x0801021fU, -/*0209*/ 0x1008021fU, -/*020a*/ 0x1808021fU, -/*020b*/ 0x001e0220U, -/*020c*/ 0x001e0221U, -/*020d*/ 0x001e0222U, -/*020e*/ 0x001e0223U, -/*020f*/ 0x001e0224U, -/*0210*/ 0x001e0225U, -/*0211*/ 0x001e0226U, -/*0212*/ 0x001e0227U, -/*0213*/ 0x001e0228U, -/*0214*/ 0x001e0229U, -/*0215*/ 0x001e022aU, -/*0216*/ 0x001e022bU, -/*0217*/ 0x001e022cU, -/*0218*/ 0x001e022dU, -/*0219*/ 0x001e022eU, -/*021a*/ 0x001e022fU, -/*021b*/ 0x00010230U, -/*021c*/ 0x08010230U, -/*021d*/ 0x10010230U, -/*021e*/ 0x18040230U, -/*021f*/ 0x00080231U, -/*0220*/ 0x08080231U, -/*0221*/ 0x10080231U, -/*0222*/ 0x18040231U, -/*0223*/ 0x00070232U, -/*0224*/ 0x08060232U, -/*0225*/ 0x10070232U, -/*0226*/ 0x18070232U, -/*0227*/ 0x00060233U, -/*0228*/ 0x08070233U, -/*0229*/ 0x10070233U, -/*022a*/ 0x18060233U, -/*022b*/ 0x00070234U, -/*022c*/ 0x08020234U, -/*022d*/ 0x10010234U, -/*022e*/ 0x18010234U, -/*022f*/ 0x000a0235U, -/*0230*/ 0x00140236U, -/*0231*/ 0x000a0237U, -/*0232*/ 0x00140238U, -/*0233*/ 0x000a0239U, -/*0234*/ 0x0014023aU, -/*0235*/ 0xffffffffU, -/*0236*/ 0xffffffffU, -/*0237*/ 0x0005023bU, -/*0238*/ 0x0001023cU, -/*0239*/ 0x1001023cU, -/*023a*/ 0x1801023cU, -/*023b*/ 0x0001023dU, -/*023c*/ 0x0801023dU, -/*023d*/ 0x1001023dU, -/*023e*/ 0x1801023dU, -/*023f*/ 0x0002023eU, -/*0240*/ 0x0802023eU, -/*0241*/ 0x1002023eU, -/*0242*/ 0x1802023eU, -/*0243*/ 0x0002023fU, -/*0244*/ 0x0803023fU, -/*0245*/ 0x1001023fU, -/*0246*/ 0x1801023fU, -/*0247*/ 0x00010240U, -/*0248*/ 0x08010240U, -/*0249*/ 0x10010240U, -/*024a*/ 0x18020240U, -/*024b*/ 0x00010241U, -/*024c*/ 0x08010241U, -/*024d*/ 0x10010241U, -/*024e*/ 0x18020241U, -/*024f*/ 0x00010242U, -/*0250*/ 0x08010242U, -/*0251*/ 0x10010242U, -/*0252*/ 0x18020242U, -/*0253*/ 0x00010243U, -/*0254*/ 0x08010243U, -/*0255*/ 0x10010243U, -/*0256*/ 0x18020243U, -/*0257*/ 0xffffffffU, -/*0258*/ 0x00010244U, -/*0259*/ 0x08010244U, -/*025a*/ 0x10010244U, -/*025b*/ 0x18010244U, -/*025c*/ 0x00010245U, -/*025d*/ 0x08010245U, -/*025e*/ 0x10010245U, -/*025f*/ 0x18010245U, -/*0260*/ 0x00040246U, -/*0261*/ 0x08040246U, -/*0262*/ 0x10040246U, -/*0263*/ 0x18010246U, -/*0264*/ 0x00020247U, -/*0265*/ 0x08060247U, -/*0266*/ 0x10060247U, -/*0267*/ 0x18020247U, -/*0268*/ 0x00020248U, -/*0269*/ 0x08020248U, -/*026a*/ 0xffffffffU, -/*026b*/ 0x10100248U, -/*026c*/ 0x00010249U, -/*026d*/ 0x08010249U, -/*026e*/ 0x10010249U, -/*026f*/ 0x18040249U, -/*0270*/ 0x0001024aU, -/*0271*/ 0x0804024aU, -/*0272*/ 0x1003024aU, -/*0273*/ 0x1808024aU, -/*0274*/ 0x000a024bU, -/*0275*/ 0x100a024bU, -/*0276*/ 0x000a024cU, -/*0277*/ 0xffffffffU, -/*0278*/ 0x0020024dU, -/*0279*/ 0x0020024eU, -/*027a*/ 0x0005024fU, -/*027b*/ 0x1801023aU, -/*027c*/ 0x0805023cU, -/*027d*/ 0x0808024fU, -/*027e*/ 0x1001024fU, -/*027f*/ 0x1808024fU, -/*0280*/ 0x00010250U, -/*0281*/ 0x08080250U, -/*0282*/ 0x10010250U, -/*0283*/ 0x18040250U, -/*0284*/ 0x00040251U, -/*0285*/ 0x08040251U, -/*0286*/ 0x10040251U, -/*0287*/ 0x18040251U, -/*0288*/ 0x00040252U, -/*0289*/ 0x08040252U, -/*028a*/ 0x10040252U, -/*028b*/ 0x18040252U, -/*028c*/ 0x00040253U, -/*028d*/ 0x08010253U, -/*028e*/ 0x10040253U, -/*028f*/ 0x18040253U, -/*0290*/ 0x00040254U, -/*0291*/ 0x08040254U, -/*0292*/ 0x10040254U, -/*0293*/ 0x18040254U, -/*0294*/ 0x00060255U, -/*0295*/ 0x08060255U, -/*0296*/ 0x10060255U, -/*0297*/ 0x18060255U, -/*0298*/ 0x00060256U, -/*0299*/ 0x08060256U, -/*029a*/ 0x10040256U, -/*029b*/ 0x18010256U, -/*029c*/ 0x00010257U, -/*029d*/ 0x08020257U, -/*029e*/ 0x00200258U, -/*029f*/ 0x00200259U, -/*02a0*/ 0x0020025aU, -/*02a1*/ 0x0020025bU, -/*02a2*/ 0x0020025cU, -/*02a3*/ 0x0020025dU, -/*02a4*/ 0x0020025eU, -/*02a5*/ 0x0020025fU, -/*02a6*/ 0x00040260U, -/*02a7*/ 0x08040260U, -/*02a8*/ 0x10010260U, -/*02a9*/ 0x18010260U, -/*02aa*/ 0x00010261U, -/*02ab*/ 0x08010261U, -/*02ac*/ 0x10010261U, -/*02ad*/ 0x18010261U, -/*02ae*/ 0x00010262U, -/*02af*/ 0x08010262U, -/*02b0*/ 0x10010262U, -/*02b1*/ 0x18040262U, -/*02b2*/ 0x00040263U, -/*02b3*/ 0x080a0263U, -/*02b4*/ 0x00200264U, -/*02b5*/ 0x00040265U, -/*02b6*/ 0x08080265U, -/*02b7*/ 0x10020265U, -/*02b8*/ 0x18020265U, -/*02b9*/ 0x00020266U, -/*02ba*/ 0x08020266U, -/*02bb*/ 0x10020266U, -/*02bc*/ 0x18020266U, -/*02bd*/ 0xffffffffU, -/*02be*/ 0xffffffffU, -/*02bf*/ 0x00200267U, -/*02c0*/ 0x00030268U, -/*02c1*/ 0x08100268U, -/*02c2*/ 0x00100269U, -/*02c3*/ 0x10040269U, -/*02c4*/ 0x18040269U, -/*02c5*/ 0x0005026aU, -/*02c6*/ 0x0805026aU, -/*02c7*/ 0xffffffffU, -/*02c8*/ 0xffffffffU, -/*02c9*/ 0xffffffffU, -/*02ca*/ 0xffffffffU, -/*02cb*/ 0x1001026aU, -/*02cc*/ 0x1801026aU, -/*02cd*/ 0x0008026bU, -/*02ce*/ 0x0808026bU, -/*02cf*/ 0x1008026bU, -/*02d0*/ 0x1808026bU, -/*02d1*/ 0x0008026cU, -/*02d2*/ 0x0808026cU, -/*02d3*/ 0x1008026cU, -/*02d4*/ 0x1808026cU, -/*02d5*/ 0x0008026dU, -/*02d6*/ 0x0808026dU, -/*02d7*/ 0x1008026dU, -/*02d8*/ 0x1808026dU, -/*02d9*/ 0x0008026eU, -/*02da*/ 0x0808026eU, -/*02db*/ 0x1003026eU, -/*02dc*/ 0x1803026eU, -/*02dd*/ 0x0003026fU, -/*02de*/ 0xffffffffU, -/*02df*/ 0x0801026fU, -/*02e0*/ 0x1002026fU, -/*02e1*/ 0x1801026fU, -/*02e2*/ 0x00040270U, -/*02e3*/ 0x08020270U, -/*02e4*/ 0x10010270U, -/*02e5*/ 0x18010270U, -/*02e6*/ 0x00010271U, -/*02e7*/ 0x08010271U, -/*02e8*/ 0x10040271U, -/*02e9*/ 0x18080271U, -/*02ea*/ 0x000a0272U, -/*02eb*/ 0x100a0272U, -/*02ec*/ 0x000a0273U, -/*02ed*/ 0x100a0273U, -/*02ee*/ 0x000a0274U, -/*02ef*/ 0x100a0274U, -/*02f0*/ 0x00200275U, -/*02f1*/ 0x00200276U, -/*02f2*/ 0x00010277U, -/*02f3*/ 0x08020277U, -/*02f4*/ 0x10020277U, -/*02f5*/ 0x18020277U, -/*02f6*/ 0xffffffffU, -/*02f7*/ 0x00020278U, -/*02f8*/ 0x08100278U, -/*02f9*/ 0x18050278U, -/*02fa*/ 0x00060279U, -/*02fb*/ 0x08050279U, -/*02fc*/ 0x10050279U, -/*02fd*/ 0x000e027aU, -/*02fe*/ 0x1005027aU, -/*02ff*/ 0x000e027bU, -/*0300*/ 0x1005027bU, -/*0301*/ 0x000e027cU, -/*0302*/ 0x1005027cU, -/*0303*/ 0x1801027cU, -/*0304*/ 0x0005027dU, -/*0305*/ 0x0805027dU, -/*0306*/ 0x100a027dU, -/*0307*/ 0x000a027eU, -/*0308*/ 0x1005027eU, -/*0309*/ 0x1805027eU, -/*030a*/ 0x000a027fU, -/*030b*/ 0x100a027fU, -/*030c*/ 0x00050280U, -/*030d*/ 0x08050280U, -/*030e*/ 0x100a0280U, -/*030f*/ 0x000a0281U, -/*0310*/ 0x10070281U, -/*0311*/ 0x18070281U, -/*0312*/ 0x00070282U, -/*0313*/ 0x08070282U, -/*0314*/ 0x10070282U, -/*0315*/ 0x18070282U, -/*0316*/ 0xffffffffU, -/*0317*/ 0xffffffffU, -/*0318*/ 0x00040283U, -/*0319*/ 0x08040283U, -/*031a*/ 0x10040283U, -/*031b*/ 0x18040283U, -/*031c*/ 0x00040284U, -/*031d*/ 0xffffffffU, -/*031e*/ 0x08080284U, -/*031f*/ 0x10080284U, -/*0320*/ 0x18040284U, -/*0321*/ 0x00050285U, -/*0322*/ 0x08080285U, -/*0323*/ 0x10050285U, -/*0324*/ 0x18040285U, -/*0325*/ 0x00050286U, -/*0326*/ 0x08080286U, -/*0327*/ 0x10050286U, -/*0328*/ 0x18040286U, -/*0329*/ 0x00050287U, -/*032a*/ 0x08080287U, -/*032b*/ 0x10050287U, -/*032c*/ 0x18040287U, -/*032d*/ 0x00050288U, -/*032e*/ 0x08070288U, -/*032f*/ 0x10080288U, -/*0330*/ 0x00100289U, -/*0331*/ 0x10080289U, -/*0332*/ 0x0010028aU, -/*0333*/ 0x1008028aU, -/*0334*/ 0x0010028bU, -/*0335*/ 0x1008028bU, -/*0336*/ 0x1808028bU, -/*0337*/ 0x0001028cU, -/*0338*/ 0x0801028cU, -/*0339*/ 0x1006028cU, -/*033a*/ 0x1806028cU, -/*033b*/ 0x0006028dU, -/*033c*/ 0x0801028dU, -/*033d*/ 0x1001028dU, -/*033e*/ 0x1803028dU, -/*033f*/ 0x000a028eU, -/*0340*/ 0x100a028eU, -/*0341*/ 0x000a028fU, -/*0342*/ 0xffffffffU, -/*0343*/ 0x100a028fU, -/*0344*/ 0x00040290U, -/*0345*/ 0x08010290U, -/*0346*/ 0x10040290U, -/*0347*/ 0x18070290U, -/*0348*/ 0x00070291U, -/*0349*/ 0x08070291U, -/*034a*/ 0x10070291U, -/*034b*/ 0x18070291U, -/*034c*/ 0x00070292U, -/*034d*/ 0xffffffffU, -/*034e*/ 0xffffffffU, -/*034f*/ 0x08050292U, -/*0350*/ 0x10050292U, -/*0351*/ 0x18040292U, -/*0352*/ 0x00040293U, -/*0353*/ 0x08040293U, -/*0354*/ 0xffffffffU, -/*0355*/ 0x10010293U, -/*0356*/ 0x18010293U, -/*0357*/ 0x00020294U, -/*0358*/ 0x08080294U, -/*0359*/ 0x00200295U, -/*035a*/ 0x00200296U, -/*035b*/ 0x00100297U, -/*035c*/ 0x10020297U, -/*035d*/ 0x18020297U, -/*035e*/ 0x00020298U, -/*035f*/ 0xffffffffU, -/*0360*/ 0x08010298U, -/*0361*/ 0x10010298U, -/*0362*/ 0x18020298U, -/*0363*/ 0x00100299U, -/*0364*/ 0x10100299U, -/*0365*/ 0x0010029aU, -/*0366*/ 0x1008029aU, -/*0367*/ 0x1808029aU, -/*0368*/ 0x0008029bU, -/*0369*/ 0x0808029bU, -/*036a*/ 0x1010029bU, -/*036b*/ 0x0010029cU, -/*036c*/ 0x1010029cU, -/*036d*/ 0x0008029dU, -/*036e*/ 0x0808029dU, -/*036f*/ 0x1008029dU, -/*0370*/ 0x1808029dU, -/*0371*/ 0x0010029eU, -/*0372*/ 0x1010029eU, -/*0373*/ 0x0010029fU, -/*0374*/ 0x1008029fU, -/*0375*/ 0x1808029fU, -/*0376*/ 0x000802a0U, -/*0377*/ 0x080802a0U, -/*0378*/ 0x100802a0U, -/*0379*/ 0x001002a1U, -/*037a*/ 0x101002a1U, -/*037b*/ 0x001002a2U, -/*037c*/ 0x100802a2U, -/*037d*/ 0x180802a2U, -/*037e*/ 0x000802a3U, -/*037f*/ 0x080802a3U, -/*0380*/ 0x101002a3U, -/*0381*/ 0x001002a4U, -/*0382*/ 0x101002a4U, -/*0383*/ 0x000802a5U, -/*0384*/ 0x080802a5U, -/*0385*/ 0x100802a5U, -/*0386*/ 0x180802a5U, -/*0387*/ 0x001002a6U, -/*0388*/ 0x101002a6U, -/*0389*/ 0x001002a7U, -/*038a*/ 0x100802a7U, -/*038b*/ 0x180802a7U, -/*038c*/ 0x000802a8U, -/*038d*/ 0x080802a8U, -/*038e*/ 0x100802a8U, -/*038f*/ 0x001002a9U, -/*0390*/ 0x101002a9U, -/*0391*/ 0x001002aaU, -/*0392*/ 0x100802aaU, -/*0393*/ 0x180802aaU, -/*0394*/ 0x000802abU, -/*0395*/ 0x080802abU, -/*0396*/ 0x101002abU, -/*0397*/ 0x001002acU, -/*0398*/ 0x101002acU, -/*0399*/ 0x000802adU, -/*039a*/ 0x080802adU, -/*039b*/ 0x100802adU, -/*039c*/ 0x180802adU, -/*039d*/ 0x001002aeU, -/*039e*/ 0x101002aeU, -/*039f*/ 0x001002afU, -/*03a0*/ 0x100802afU, -/*03a1*/ 0x180802afU, -/*03a2*/ 0x000802b0U, -/*03a3*/ 0x080802b0U, -/*03a4*/ 0x100802b0U, -/*03a5*/ 0x001002b1U, -/*03a6*/ 0x101002b1U, -/*03a7*/ 0x001002b2U, -/*03a8*/ 0x100802b2U, -/*03a9*/ 0x180802b2U, -/*03aa*/ 0x000802b3U, -/*03ab*/ 0x080802b3U, -/*03ac*/ 0x101002b3U, -/*03ad*/ 0x001002b4U, -/*03ae*/ 0x101002b4U, -/*03af*/ 0x000802b5U, -/*03b0*/ 0x080802b5U, -/*03b1*/ 0x100802b5U, -/*03b2*/ 0x180802b5U, -/*03b3*/ 0x001002b6U, -/*03b4*/ 0x101002b6U, -/*03b5*/ 0x001002b7U, -/*03b6*/ 0x100802b7U, -/*03b7*/ 0x180802b7U, -/*03b8*/ 0x000802b8U, -/*03b9*/ 0x080802b8U, -/*03ba*/ 0x100802b8U, -/*03bb*/ 0x180202b8U, -/*03bc*/ 0x000302b9U, -/*03bd*/ 0x080a02b9U, -/*03be*/ 0x000a02baU, -/*03bf*/ 0x100a02baU, -/*03c0*/ 0x000502bbU, -/*03c1*/ 0x080802bbU, -/*03c2*/ 0x100802bbU, -/*03c3*/ 0x180802bbU, -/*03c4*/ 0x000602bcU, -/*03c5*/ 0x080602bcU, -/*03c6*/ 0x001102bdU, -/*03c7*/ 0x180802bdU, -/*03c8*/ 0x000402beU, -/*03c9*/ 0x080602beU, -/*03ca*/ 0x100802beU, -/*03cb*/ 0x180802beU, -/*03cc*/ 0x000802bfU, -/*03cd*/ 0x080802bfU, -/*03ce*/ 0x100802bfU, -/*03cf*/ 0x180802bfU, -/*03d0*/ 0x000802c0U, -/*03d1*/ 0x080602c0U, -/*03d2*/ 0x100602c0U, -/*03d3*/ 0x001102c1U, -/*03d4*/ 0x180802c1U, -/*03d5*/ 0x000402c2U, -/*03d6*/ 0x080602c2U, -/*03d7*/ 0x100802c2U, -/*03d8*/ 0x180802c2U, -/*03d9*/ 0x000802c3U, -/*03da*/ 0x080802c3U, -/*03db*/ 0x100802c3U, -/*03dc*/ 0x180802c3U, -/*03dd*/ 0x000802c4U, -/*03de*/ 0x080602c4U, -/*03df*/ 0x100602c4U, -/*03e0*/ 0x001102c5U, -/*03e1*/ 0x180802c5U, -/*03e2*/ 0x000402c6U, -/*03e3*/ 0x080602c6U, -/*03e4*/ 0x100802c6U, -/*03e5*/ 0x180802c6U, -/*03e6*/ 0x000802c7U, -/*03e7*/ 0x080802c7U, -/*03e8*/ 0x100402c7U, -/*03e9*/ 0x180402c7U, -/*03ea*/ 0x000402c8U, -/*03eb*/ 0x080402c8U, -/*03ec*/ 0x100402c8U, -/*03ed*/ 0x180402c8U, -/*03ee*/ 0x000402c9U, -/*03ef*/ 0x080402c9U, -/*03f0*/ 0x100402c9U, -/*03f1*/ 0x180402c9U, -/*03f2*/ 0x000402caU, -/*03f3*/ 0x080402caU, -/*03f4*/ 0x100402caU, -/*03f5*/ 0x180402caU, -/*03f6*/ 0x000402cbU, -/*03f7*/ 0x080402cbU, -/*03f8*/ 0x100402cbU, -/*03f9*/ 0x180402cbU, -/*03fa*/ 0x000402ccU, -/*03fb*/ 0x080402ccU, -/*03fc*/ 0x001702cdU, -/*03fd*/ 0x001602ceU, -/*03fe*/ 0x001702cfU, -/*03ff*/ 0x002002d0U, -/*0400*/ 0x002002d1U, -/*0401*/ 0x002002d2U, -/*0402*/ 0x002002d3U, -/*0403*/ 0x002002d4U, -/*0404*/ 0x002002d5U, -/*0405*/ 0x002002d6U, -/*0406*/ 0x002002d7U, -/*0407*/ 0x002002d8U, -/*0408*/ 0x000202d9U, -/*0409*/ 0x080502d9U, -/*040a*/ 0x100502d9U, -/*040b*/ 0x180102d9U, -/*040c*/ 0x000502daU, -/*040d*/ 0x080502daU, -/*040e*/ 0x100502daU, -/*040f*/ 0x180502daU, -/*0410*/ 0x000502dbU, -/*0411*/ 0x080502dbU, -/*0412*/ 0x100502dbU, -/*0413*/ 0x180502dbU, -/*0414*/ 0x000502dcU, -/*0415*/ 0x080502dcU, -/*0416*/ 0x100502dcU, -/*0417*/ 0x180502dcU, -/*0418*/ 0x000502ddU, -/*0419*/ 0x080502ddU, -/*041a*/ 0x100502ddU, -/*041b*/ 0x180502ddU, -/*041c*/ 0x000502deU, -/*041d*/ 0x080502deU, -/*041e*/ 0x100502deU, -/*041f*/ 0x180502deU, -/*0420*/ 0x000502dfU, -/*0421*/ 0x080502dfU, -/*0422*/ 0x100102dfU, -/*0423*/ 0x180202dfU, -/*0424*/ 0x000202e0U, -/*0425*/ 0x080202e0U, -/*0426*/ 0x100202e0U, -/*0427*/ 0x180102e0U, -/*0428*/ 0x000802e1U, -/*0429*/ 0x081502e1U, -/*042a*/ 0x002002e2U, -/*042b*/ 0x001502e3U, -/*042c*/ 0x002002e4U, -/*042d*/ 0x001502e5U, -/*042e*/ 0x002002e6U, -/*042f*/ 0x000702e7U, -/*0430*/ 0x080102e7U, -/*0431*/ 0x100202e7U, -/*0432*/ 0x180602e7U, -/*0433*/ 0x000102e8U, -/*0434*/ 0x080102e8U, -/*0435*/ 0x002002e9U, -/*0436*/ 0x000202eaU, -/*0437*/ 0x002002ebU, -/*0438*/ 0x002002ecU, -/*0439*/ 0x000c02edU, -/*043a*/ 0x100c02edU, -/*043b*/ 0x002002eeU, -/*043c*/ 0x000302efU, -/*043d*/ 0x002002f0U, -/*043e*/ 0x000302f1U, -/*043f*/ 0x002002f2U, -/*0440*/ 0x000302f3U, -/*0441*/ 0x002002f4U, -/*0442*/ 0x000302f5U, -/*0443*/ 0x002002f6U, -/*0444*/ 0x000302f7U, -/*0445*/ 0x002002f8U, -/*0446*/ 0x000302f9U, -/*0447*/ 0x002002faU, -/*0448*/ 0x000302fbU, -/*0449*/ 0x002002fcU, -/*044a*/ 0x000302fdU, -/*044b*/ 0x002002feU, -/*044c*/ 0x000302ffU, -/*044d*/ 0x00200300U, -/*044e*/ 0x00030301U, -/*044f*/ 0x08030301U, -/*0450*/ 0x10020301U, -/*0451*/ 0x18020301U, -/*0452*/ 0x00200302U, -/*0453*/ 0x00200303U, -/*0454*/ 0x00200304U, -/*0455*/ 0x00200305U, -/*0456*/ 0x00040306U, -/*0457*/ 0x001e0307U, -/*0458*/ 0x001e0308U, -/*0459*/ 0x001e0309U, -/*045a*/ 0x001e030aU, -/*045b*/ 0x001e030bU, -/*045c*/ 0x001e030cU, -/*045d*/ 0x001e030dU, -/*045e*/ 0x001e030eU, -/*045f*/ 0x0004030fU, -/*0460*/ 0x0801030fU, -/*0461*/ 0x1010030fU, -/*0462*/ 0x00100310U, -/*0463*/ 0x10100310U, -/*0464*/ 0x00040311U, -/*0465*/ 0x08010311U, -/*0466*/ 0x10080311U, -/*0467*/ 0x18040311U, -/*0468*/ 0x00010312U, -/*0469*/ 0x08080312U, -/*046a*/ 0x10040312U, -/*046b*/ 0x18010312U, -/*046c*/ 0x00080313U, -/*046d*/ 0x08040313U, -/*046e*/ 0x10010313U, -/*046f*/ 0x18080313U, -/*0470*/ 0x00040314U, -/*0471*/ 0x08010314U, -/*0472*/ 0x10080314U, -/*0473*/ 0x18040314U, -/*0474*/ 0x00010315U, -/*0475*/ 0x08080315U, -/*0476*/ 0x10040315U, -/*0477*/ 0x18010315U, -/*0478*/ 0x00080316U, -/*0479*/ 0x08040316U, -/*047a*/ 0x10010316U, -/*047b*/ 0x18080316U, -/*047c*/ 0x00080317U, -/*047d*/ 0x00010318U, -/*047e*/ 0x08050318U, -/*047f*/ 0x10010318U, -/*0480*/ 0x18020318U, -/*0481*/ 0x00010319U, -/*0482*/ 0x08010319U, -/*0483*/ 0x10010319U, -/*0484*/ 0x18010319U, -/*0485*/ 0x0001031aU, -/*0486*/ 0x0801031aU, -/*0487*/ 0x1001031aU, -/*0488*/ 0x1801031aU, -/*0489*/ 0x0001031bU, -/*048a*/ 0x0801031bU, -/*048b*/ 0x1001031bU, -/*048c*/ 0x1801031bU, -/*048d*/ 0x0001031cU, -/*048e*/ 0x0801031cU, -/*048f*/ 0x1001031cU, -/*0490*/ 0x1801031cU, -/*0491*/ 0x0008031dU, -/*0492*/ 0x0808031dU, -/*0493*/ 0x1008031dU, -/*0494*/ 0x1808031dU, - } -}; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h deleted file mode 100644 index 357f8bad0..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h +++ /dev/null @@ -1,441 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define DDR_PHY_SLICE_REGSET_OFS_H3 0x0400 -#define DDR_PHY_ADR_V_REGSET_OFS_H3 0x0600 -#define DDR_PHY_ADR_I_REGSET_OFS_H3 0x0680 -#define DDR_PHY_ADR_G_REGSET_OFS_H3 0x0700 -#define DDR_PI_REGSET_OFS_H3 0x0200 - -#define DDR_PHY_SLICE_REGSET_SIZE_H3 0x80 -#define DDR_PHY_ADR_V_REGSET_SIZE_H3 0x80 -#define DDR_PHY_ADR_I_REGSET_SIZE_H3 0x80 -#define DDR_PHY_ADR_G_REGSET_SIZE_H3 0x80 -#define DDR_PI_REGSET_SIZE_H3 0x100 - -#define DDR_PHY_SLICE_REGSET_NUM_H3 88 -#define DDR_PHY_ADR_V_REGSET_NUM_H3 37 -#define DDR_PHY_ADR_I_REGSET_NUM_H3 37 -#define DDR_PHY_ADR_G_REGSET_NUM_H3 59 -#define DDR_PI_REGSET_NUM_H3 181 - -static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = { - /*0400*/ 0x000004f0, - /*0401*/ 0x00000000, - /*0402*/ 0x00000000, - /*0403*/ 0x00000100, - /*0404*/ 0x01003c0c, - /*0405*/ 0x02003c0c, - /*0406*/ 0x00010300, - /*0407*/ 0x04000100, - /*0408*/ 0x00000300, - /*0409*/ 0x000700c0, - /*040a*/ 0x00b00201, - /*040b*/ 0x00000020, - /*040c*/ 0x00000000, - /*040d*/ 0x00000000, - /*040e*/ 0x00000000, - /*040f*/ 0x00000000, - /*0410*/ 0x00000000, - /*0411*/ 0x00000000, - /*0412*/ 0x00000000, - /*0413*/ 0x09000000, - /*0414*/ 0x04080000, - /*0415*/ 0x04080400, - /*0416*/ 0x00000000, - /*0417*/ 0x32103210, - /*0418*/ 0x00800708, - /*0419*/ 0x000f000c, - /*041a*/ 0x00000100, - /*041b*/ 0x55aa55aa, - /*041c*/ 0x33cc33cc, - /*041d*/ 0x0ff00ff0, - /*041e*/ 0x0f0ff0f0, - /*041f*/ 0x00008e38, - /*0420*/ 0x76543210, - /*0421*/ 0x00000001, - /*0422*/ 0x00000000, - /*0423*/ 0x00000000, - /*0424*/ 0x00000000, - /*0425*/ 0x00000000, - /*0426*/ 0x00000000, - /*0427*/ 0x00000000, - /*0428*/ 0x00000000, - /*0429*/ 0x00000000, - /*042a*/ 0x00000000, - /*042b*/ 0x00000000, - /*042c*/ 0x00000000, - /*042d*/ 0x00000000, - /*042e*/ 0x00000000, - /*042f*/ 0x00000000, - /*0430*/ 0x00000000, - /*0431*/ 0x00000000, - /*0432*/ 0x00000000, - /*0433*/ 0x00200000, - /*0434*/ 0x08200820, - /*0435*/ 0x08200820, - /*0436*/ 0x08200820, - /*0437*/ 0x08200820, - /*0438*/ 0x08200820, - /*0439*/ 0x00000820, - /*043a*/ 0x03000300, - /*043b*/ 0x03000300, - /*043c*/ 0x03000300, - /*043d*/ 0x03000300, - /*043e*/ 0x00000300, - /*043f*/ 0x00000000, - /*0440*/ 0x00000000, - /*0441*/ 0x00000000, - /*0442*/ 0x00000000, - /*0443*/ 0x00a000a0, - /*0444*/ 0x00a000a0, - /*0445*/ 0x00a000a0, - /*0446*/ 0x00a000a0, - /*0447*/ 0x00a000a0, - /*0448*/ 0x00a000a0, - /*0449*/ 0x00a000a0, - /*044a*/ 0x00a000a0, - /*044b*/ 0x00a000a0, - /*044c*/ 0x01040109, - /*044d*/ 0x00000200, - /*044e*/ 0x01000000, - /*044f*/ 0x00000200, - /*0450*/ 0x4041a151, - /*0451*/ 0xc00141a0, - /*0452*/ 0x0e0100c0, - /*0453*/ 0x0010000c, - /*0454*/ 0x0c064208, - /*0455*/ 0x000f0c18, - /*0456*/ 0x00e00140, - /*0457*/ 0x00000c20 -}; - -static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = { - /*0600*/ 0x00000000, - /*0601*/ 0x00000000, - /*0602*/ 0x00000000, - /*0603*/ 0x00000000, - /*0604*/ 0x00000000, - /*0605*/ 0x00000000, - /*0606*/ 0x00000002, - /*0607*/ 0x00000000, - /*0608*/ 0x00000000, - /*0609*/ 0x00000000, - /*060a*/ 0x00400320, - /*060b*/ 0x00000040, - /*060c*/ 0x00dcba98, - /*060d*/ 0x00000000, - /*060e*/ 0x00dcba98, - /*060f*/ 0x01000000, - /*0610*/ 0x00020003, - /*0611*/ 0x00000000, - /*0612*/ 0x00000000, - /*0613*/ 0x00000000, - /*0614*/ 0x00002a01, - /*0615*/ 0x00000015, - /*0616*/ 0x00000015, - /*0617*/ 0x0000002a, - /*0618*/ 0x00000033, - /*0619*/ 0x0000000c, - /*061a*/ 0x0000000c, - /*061b*/ 0x00000033, - /*061c*/ 0x00418820, - /*061d*/ 0x003f0000, - /*061e*/ 0x0000003f, - /*061f*/ 0x0002006e, - /*0620*/ 0x02000200, - /*0621*/ 0x02000200, - /*0622*/ 0x00000200, - /*0623*/ 0x42080010, - /*0624*/ 0x00000003 -}; - -static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = { - /*0680*/ 0x04040404, - /*0681*/ 0x00000404, - /*0682*/ 0x00000000, - /*0683*/ 0x00000000, - /*0684*/ 0x00000000, - /*0685*/ 0x00000000, - /*0686*/ 0x00000002, - /*0687*/ 0x00000000, - /*0688*/ 0x00000000, - /*0689*/ 0x00000000, - /*068a*/ 0x00400320, - /*068b*/ 0x00000040, - /*068c*/ 0x00000000, - /*068d*/ 0x00000000, - /*068e*/ 0x00000000, - /*068f*/ 0x01000000, - /*0690*/ 0x00020003, - /*0691*/ 0x00000000, - /*0692*/ 0x00000000, - /*0693*/ 0x00000000, - /*0694*/ 0x00002a01, - /*0695*/ 0x00000015, - /*0696*/ 0x00000015, - /*0697*/ 0x0000002a, - /*0698*/ 0x00000033, - /*0699*/ 0x0000000c, - /*069a*/ 0x0000000c, - /*069b*/ 0x00000033, - /*069c*/ 0x00000000, - /*069d*/ 0x00000000, - /*069e*/ 0x00000000, - /*069f*/ 0x0002006e, - /*06a0*/ 0x02000200, - /*06a1*/ 0x02000200, - /*06a2*/ 0x00000200, - /*06a3*/ 0x42080010, - /*06a4*/ 0x00000003 -}; - -static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = { - /*0700*/ 0x00000001, - /*0701*/ 0x00000000, - /*0702*/ 0x00000005, - /*0703*/ 0x04000f00, - /*0704*/ 0x00020080, - /*0705*/ 0x00020055, - /*0706*/ 0x00000000, - /*0707*/ 0x00000000, - /*0708*/ 0x00000000, - /*0709*/ 0x00000050, - /*070a*/ 0x00000000, - /*070b*/ 0x01010100, - /*070c*/ 0x00000200, - /*070d*/ 0x00001102, - /*070e*/ 0x00000000, - /*070f*/ 0x000f1f00, - /*0710*/ 0x0f1f0f1f, - /*0711*/ 0x0f1f0f1f, - /*0712*/ 0x00020003, - /*0713*/ 0x02000200, - /*0714*/ 0x00000200, - /*0715*/ 0x00001102, - /*0716*/ 0x00000064, - /*0717*/ 0x00000000, - /*0718*/ 0x00000000, - /*0719*/ 0x00000502, - /*071a*/ 0x027f6e00, - /*071b*/ 0x007f007f, - /*071c*/ 0x00007f3c, - /*071d*/ 0x00047f6e, - /*071e*/ 0x0003154f, - /*071f*/ 0x0001154f, - /*0720*/ 0x0001154f, - /*0721*/ 0x0001154f, - /*0722*/ 0x0001154f, - /*0723*/ 0x00003fee, - /*0724*/ 0x0001154f, - /*0725*/ 0x00003fee, - /*0726*/ 0x0001154f, - /*0727*/ 0x00007f3c, - /*0728*/ 0x0001154f, - /*0729*/ 0x00000000, - /*072a*/ 0x00000000, - /*072b*/ 0x00000000, - /*072c*/ 0x65000000, - /*072d*/ 0x00000000, - /*072e*/ 0x00000000, - /*072f*/ 0x00000201, - /*0730*/ 0x00000000, - /*0731*/ 0x00000000, - /*0732*/ 0x00000000, - /*0733*/ 0x00000000, - /*0734*/ 0x00000000, - /*0735*/ 0x00000000, - /*0736*/ 0x00000000, - /*0737*/ 0x00000000, - /*0738*/ 0x00000000, - /*0739*/ 0x00000000, - /*073a*/ 0x00000000 -}; - -static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = { - /*0200*/ 0x00000b00, - /*0201*/ 0x00000100, - /*0202*/ 0x00000000, - /*0203*/ 0x0000ffff, - /*0204*/ 0x00000000, - /*0205*/ 0x0000ffff, - /*0206*/ 0x00000000, - /*0207*/ 0x304cffff, - /*0208*/ 0x00000200, - /*0209*/ 0x00000200, - /*020a*/ 0x00000200, - /*020b*/ 0x00000200, - /*020c*/ 0x0000304c, - /*020d*/ 0x00000200, - /*020e*/ 0x00000200, - /*020f*/ 0x00000200, - /*0210*/ 0x00000200, - /*0211*/ 0x0000304c, - /*0212*/ 0x00000200, - /*0213*/ 0x00000200, - /*0214*/ 0x00000200, - /*0215*/ 0x00000200, - /*0216*/ 0x00010000, - /*0217*/ 0x00000003, - /*0218*/ 0x01000001, - /*0219*/ 0x00000000, - /*021a*/ 0x00000000, - /*021b*/ 0x00000000, - /*021c*/ 0x00000000, - /*021d*/ 0x00000000, - /*021e*/ 0x00000000, - /*021f*/ 0x00000000, - /*0220*/ 0x00000000, - /*0221*/ 0x00000000, - /*0222*/ 0x00000000, - /*0223*/ 0x00000000, - /*0224*/ 0x00000000, - /*0225*/ 0x00000000, - /*0226*/ 0x00000000, - /*0227*/ 0x00000000, - /*0228*/ 0x00000000, - /*0229*/ 0x0f000101, - /*022a*/ 0x08492d25, - /*022b*/ 0x500e0c04, - /*022c*/ 0x0002500e, - /*022d*/ 0x00460003, - /*022e*/ 0x182600cf, - /*022f*/ 0x182600cf, - /*0230*/ 0x00000005, - /*0231*/ 0x00000000, - /*0232*/ 0x00000000, - /*0233*/ 0x00000000, - /*0234*/ 0x00000000, - /*0235*/ 0x00000000, - /*0236*/ 0x00000000, - /*0237*/ 0x00000000, - /*0238*/ 0x01000000, - /*0239*/ 0x00040404, - /*023a*/ 0x01280a00, - /*023b*/ 0x00000000, - /*023c*/ 0x000f0000, - /*023d*/ 0x00001803, - /*023e*/ 0x00000000, - /*023f*/ 0x00000000, - /*0240*/ 0x00060002, - /*0241*/ 0x00010001, - /*0242*/ 0x01000101, - /*0243*/ 0x04020201, - /*0244*/ 0x00080804, - /*0245*/ 0x00000000, - /*0246*/ 0x08030000, - /*0247*/ 0x15150408, - /*0248*/ 0x00000000, - /*0249*/ 0x00000000, - /*024a*/ 0x00000000, - /*024b*/ 0x001e0f0f, - /*024c*/ 0x00000000, - /*024d*/ 0x01000300, - /*024e*/ 0x00000000, - /*024f*/ 0x00000000, - /*0250*/ 0x01000000, - /*0251*/ 0x00010101, - /*0252*/ 0x000e0e0e, - /*0253*/ 0x000c0c0c, - /*0254*/ 0x02060601, - /*0255*/ 0x00000000, - /*0256*/ 0x00000003, - /*0257*/ 0x00181703, - /*0258*/ 0x00280006, - /*0259*/ 0x00280016, - /*025a*/ 0x00000016, - /*025b*/ 0x00000000, - /*025c*/ 0x00000000, - /*025d*/ 0x00000000, - /*025e*/ 0x140a0000, - /*025f*/ 0x0005010a, - /*0260*/ 0x03018d03, - /*0261*/ 0x000a018d, - /*0262*/ 0x00060100, - /*0263*/ 0x01000006, - /*0264*/ 0x018e018e, - /*0265*/ 0x018e0100, - /*0266*/ 0x1111018e, - /*0267*/ 0x10010204, - /*0268*/ 0x09090650, - /*0269*/ 0x20110202, - /*026a*/ 0x00201000, - /*026b*/ 0x00201000, - /*026c*/ 0x04041000, - /*026d*/ 0x18020100, - /*026e*/ 0x00010118, - /*026f*/ 0x004b004a, - /*0270*/ 0x050f0000, - /*0271*/ 0x0c01021e, - /*0272*/ 0x34000000, - /*0273*/ 0x00000000, - /*0274*/ 0x00000000, - /*0275*/ 0x00000000, - /*0276*/ 0x312ed400, - /*0277*/ 0xd4111132, - /*0278*/ 0x1132312e, - /*0279*/ 0x312ed411, - /*027a*/ 0x00111132, - /*027b*/ 0x32312ed4, - /*027c*/ 0x2ed41111, - /*027d*/ 0x11113231, - /*027e*/ 0x32312ed4, - /*027f*/ 0xd4001111, - /*0280*/ 0x1132312e, - /*0281*/ 0x312ed411, - /*0282*/ 0xd4111132, - /*0283*/ 0x1132312e, - /*0284*/ 0x2ed40011, - /*0285*/ 0x11113231, - /*0286*/ 0x32312ed4, - /*0287*/ 0x2ed41111, - /*0288*/ 0x11113231, - /*0289*/ 0x00020000, - /*028a*/ 0x018d018d, - /*028b*/ 0x0c08018d, - /*028c*/ 0x1f121d22, - /*028d*/ 0x4301b344, - /*028e*/ 0x10172006, - /*028f*/ 0x121d220c, - /*0290*/ 0x01b3441f, - /*0291*/ 0x17200643, - /*0292*/ 0x1d220c10, - /*0293*/ 0x00001f12, - /*0294*/ 0x4301b344, - /*0295*/ 0x10172006, - /*0296*/ 0x00020002, - /*0297*/ 0x00020002, - /*0298*/ 0x00020002, - /*0299*/ 0x00020002, - /*029a*/ 0x00020002, - /*029b*/ 0x00000000, - /*029c*/ 0x00000000, - /*029d*/ 0x00000000, - /*029e*/ 0x00000000, - /*029f*/ 0x00000000, - /*02a0*/ 0x00000000, - /*02a1*/ 0x00000000, - /*02a2*/ 0x00000000, - /*02a3*/ 0x00000000, - /*02a4*/ 0x00000000, - /*02a5*/ 0x00000000, - /*02a6*/ 0x00000000, - /*02a7*/ 0x01000400, - /*02a8*/ 0x00304c00, - /*02a9*/ 0x0001e2f8, - /*02aa*/ 0x0000304c, - /*02ab*/ 0x0001e2f8, - /*02ac*/ 0x0000304c, - /*02ad*/ 0x0001e2f8, - /*02ae*/ 0x08000000, - /*02af*/ 0x00000100, - /*02b0*/ 0x00000000, - /*02b1*/ 0x00000000, - /*02b2*/ 0x00000000, - /*02b3*/ 0x00000000, - /*02b4*/ 0x00000002 -}; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h deleted file mode 100644 index e5258af6c..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h +++ /dev/null @@ -1,538 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define DDR_PHY_SLICE_REGSET_OFS_H3VER2 0x0400 -#define DDR_PHY_ADR_V_REGSET_OFS_H3VER2 0x0600 -#define DDR_PHY_ADR_I_REGSET_OFS_H3VER2 0x0640 -#define DDR_PHY_ADR_G_REGSET_OFS_H3VER2 0x0680 -#define DDR_PI_REGSET_OFS_H3VER2 0x0200 - -#define DDR_PHY_SLICE_REGSET_SIZE_H3VER2 0x80 -#define DDR_PHY_ADR_V_REGSET_SIZE_H3VER2 0x40 -#define DDR_PHY_ADR_I_REGSET_SIZE_H3VER2 0x40 -#define DDR_PHY_ADR_G_REGSET_SIZE_H3VER2 0x80 -#define DDR_PI_REGSET_SIZE_H3VER2 0x100 - -#define DDR_PHY_SLICE_REGSET_NUM_H3VER2 97 -#define DDR_PHY_ADR_V_REGSET_NUM_H3VER2 37 -#define DDR_PHY_ADR_I_REGSET_NUM_H3VER2 37 -#define DDR_PHY_ADR_G_REGSET_NUM_H3VER2 79 -#define DDR_PI_REGSET_NUM_H3VER2 245 - -static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2 - [DDR_PHY_SLICE_REGSET_NUM_H3VER2] = { - /*0400*/ 0x76543210, - /*0401*/ 0x0004f008, - /*0402*/ 0x00020133, - /*0403*/ 0x00000000, - /*0404*/ 0x00000000, - /*0405*/ 0x00010000, - /*0406*/ 0x016e6e0e, - /*0407*/ 0x026e6e0e, - /*0408*/ 0x00010300, - /*0409*/ 0x04000100, - /*040a*/ 0x01000000, - /*040b*/ 0x00000000, - /*040c*/ 0x00000000, - /*040d*/ 0x00000100, - /*040e*/ 0x001700c0, - /*040f*/ 0x020100b0, - /*0410*/ 0x00030020, - /*0411*/ 0x00000000, - /*0412*/ 0x00000000, - /*0413*/ 0x00000000, - /*0414*/ 0x00000000, - /*0415*/ 0x00000000, - /*0416*/ 0x00000000, - /*0417*/ 0x00000000, - /*0418*/ 0x09000000, - /*0419*/ 0x04080000, - /*041a*/ 0x04080400, - /*041b*/ 0x08000000, - /*041c*/ 0x0c008007, - /*041d*/ 0x00000f00, - /*041e*/ 0x00000100, - /*041f*/ 0x55aa55aa, - /*0420*/ 0x33cc33cc, - /*0421*/ 0x0ff00ff0, - /*0422*/ 0x0f0ff0f0, - /*0423*/ 0x00018e38, - /*0424*/ 0x00000000, - /*0425*/ 0x00000000, - /*0426*/ 0x00000000, - /*0427*/ 0x00000000, - /*0428*/ 0x00000000, - /*0429*/ 0x00000000, - /*042a*/ 0x00000000, - /*042b*/ 0x00000000, - /*042c*/ 0x00000000, - /*042d*/ 0x00000000, - /*042e*/ 0x00000000, - /*042f*/ 0x00000000, - /*0430*/ 0x00000000, - /*0431*/ 0x00000000, - /*0432*/ 0x00000000, - /*0433*/ 0x00000000, - /*0434*/ 0x00000000, - /*0435*/ 0x00000000, - /*0436*/ 0x00000000, - /*0437*/ 0x00000000, - /*0438*/ 0x00000104, - /*0439*/ 0x00082020, - /*043a*/ 0x08200820, - /*043b*/ 0x08200820, - /*043c*/ 0x08200820, - /*043d*/ 0x08200820, - /*043e*/ 0x08200820, - /*043f*/ 0x00000000, - /*0440*/ 0x00000000, - /*0441*/ 0x03000300, - /*0442*/ 0x03000300, - /*0443*/ 0x03000300, - /*0444*/ 0x03000300, - /*0445*/ 0x00000300, - /*0446*/ 0x00000000, - /*0447*/ 0x00000000, - /*0448*/ 0x00000000, - /*0449*/ 0x00000000, - /*044a*/ 0x00000000, - /*044b*/ 0x00a000a0, - /*044c*/ 0x00a000a0, - /*044d*/ 0x00a000a0, - /*044e*/ 0x00a000a0, - /*044f*/ 0x00a000a0, - /*0450*/ 0x00a000a0, - /*0451*/ 0x00a000a0, - /*0452*/ 0x00a000a0, - /*0453*/ 0x00a000a0, - /*0454*/ 0x01040109, - /*0455*/ 0x00000200, - /*0456*/ 0x01000000, - /*0457*/ 0x00000200, - /*0458*/ 0x00000004, - /*0459*/ 0x4041a151, - /*045a*/ 0xc00141a0, - /*045b*/ 0x0e0000c0, - /*045c*/ 0x0010000c, - /*045d*/ 0x063e4208, - /*045e*/ 0x0f0c180c, - /*045f*/ 0x00e00140, - /*0460*/ 0x00000c20 -}; - -static const uint32_t - DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = { - /*0600*/ 0x00000000, - /*0601*/ 0x00000000, - /*0602*/ 0x00000000, - /*0603*/ 0x00000000, - /*0604*/ 0x00000000, - /*0605*/ 0x00000000, - /*0606*/ 0x00000000, - /*0607*/ 0x00010000, - /*0608*/ 0x00000200, - /*0609*/ 0x00000000, - /*060a*/ 0x00000000, - /*060b*/ 0x00000000, - /*060c*/ 0x00400320, - /*060d*/ 0x00000040, - /*060e*/ 0x00dcba98, - /*060f*/ 0x03000000, - /*0610*/ 0x00000200, - /*0611*/ 0x00000000, - /*0612*/ 0x00000000, - /*0613*/ 0x00000000, - /*0614*/ 0x0000002a, - /*0615*/ 0x00000015, - /*0616*/ 0x00000015, - /*0617*/ 0x0000002a, - /*0618*/ 0x00000033, - /*0619*/ 0x0000000c, - /*061a*/ 0x0000000c, - /*061b*/ 0x00000033, - /*061c*/ 0x00418820, - /*061d*/ 0x003f0000, - /*061e*/ 0x0000003f, - /*061f*/ 0x0002c06e, - /*0620*/ 0x02c002c0, - /*0621*/ 0x02c002c0, - /*0622*/ 0x000002c0, - /*0623*/ 0x42080010, - /*0624*/ 0x0000033e -}; - -static const uint32_t - DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = { - /*0640*/ 0x00000000, - /*0641*/ 0x00000000, - /*0642*/ 0x00000000, - /*0643*/ 0x00000000, - /*0644*/ 0x00000000, - /*0645*/ 0x00000000, - /*0646*/ 0x00000000, - /*0647*/ 0x00000000, - /*0648*/ 0x00000000, - /*0649*/ 0x00000000, - /*064a*/ 0x00000000, - /*064b*/ 0x00000000, - /*064c*/ 0x00000000, - /*064d*/ 0x00000000, - /*064e*/ 0x00000000, - /*064f*/ 0x00000000, - /*0650*/ 0x00000000, - /*0651*/ 0x00000000, - /*0652*/ 0x00000000, - /*0653*/ 0x00000000, - /*0654*/ 0x00000000, - /*0655*/ 0x00000000, - /*0656*/ 0x00000000, - /*0657*/ 0x00000000, - /*0658*/ 0x00000000, - /*0659*/ 0x00000000, - /*065a*/ 0x00000000, - /*065b*/ 0x00000000, - /*065c*/ 0x00000000, - /*065d*/ 0x00000000, - /*065e*/ 0x00000000, - /*065f*/ 0x00000000, - /*0660*/ 0x00000000, - /*0661*/ 0x00000000, - /*0662*/ 0x00000000, - /*0663*/ 0x00000000, - /*0664*/ 0x00000000 -}; - -static const uint32_t - DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = { - /*0680*/ 0x00000000, - /*0681*/ 0x00000100, - /*0682*/ 0x00000000, - /*0683*/ 0x00050000, - /*0684*/ 0x0f000000, - /*0685*/ 0x00800400, - /*0686*/ 0x00020032, - /*0687*/ 0x00020055, - /*0688*/ 0x00000000, - /*0689*/ 0x00000000, - /*068a*/ 0x00000000, - /*068b*/ 0x00000050, - /*068c*/ 0x00000000, - /*068d*/ 0x01010100, - /*068e*/ 0x01000200, - /*068f*/ 0x00000000, - /*0690*/ 0x00010100, - /*0691*/ 0x00000000, - /*0692*/ 0x00000000, - /*0693*/ 0x00000000, - /*0694*/ 0x00000000, - /*0695*/ 0x00005064, - /*0696*/ 0x01421142, - /*0697*/ 0x00000142, - /*0698*/ 0x00000000, - /*0699*/ 0x000f1100, - /*069a*/ 0x0f110f11, - /*069b*/ 0x09000f11, - /*069c*/ 0x00000003, - /*069d*/ 0x0002c000, - /*069e*/ 0x02c002c0, - /*069f*/ 0x000002c0, - /*06a0*/ 0x03421342, - /*06a1*/ 0x00000342, - /*06a2*/ 0x00000000, - /*06a3*/ 0x00000000, - /*06a4*/ 0x05020000, - /*06a5*/ 0x14000000, - /*06a6*/ 0x027f6e00, - /*06a7*/ 0x047f027f, - /*06a8*/ 0x00027f6e, - /*06a9*/ 0x00047f6e, - /*06aa*/ 0x0003554f, - /*06ab*/ 0x0001554f, - /*06ac*/ 0x0001554f, - /*06ad*/ 0x0001554f, - /*06ae*/ 0x0001554f, - /*06af*/ 0x00003fee, - /*06b0*/ 0x0001554f, - /*06b1*/ 0x00003fee, - /*06b2*/ 0x0001554f, - /*06b3*/ 0x00027f6e, - /*06b4*/ 0x0001554f, - /*06b5*/ 0x00004011, - /*06b6*/ 0x00004410, - /*06b7*/ 0x00000000, - /*06b8*/ 0x00000000, - /*06b9*/ 0x00000000, - /*06ba*/ 0x00000065, - /*06bb*/ 0x00000000, - /*06bc*/ 0x00020201, - /*06bd*/ 0x00000000, - /*06be*/ 0x03000000, - /*06bf*/ 0x00000008, - /*06c0*/ 0x00000000, - /*06c1*/ 0x00000000, - /*06c2*/ 0x00000000, - /*06c3*/ 0x00000000, - /*06c4*/ 0x00000001, - /*06c5*/ 0x00000000, - /*06c6*/ 0x00000000, - /*06c7*/ 0x00000000, - /*06c8*/ 0x000000e4, - /*06c9*/ 0x00010198, - /*06ca*/ 0x00000000, - /*06cb*/ 0x00000000, - /*06cc*/ 0x07010000, - /*06cd*/ 0x00000104, - /*06ce*/ 0x00000000 -}; - -static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = { - /*0200*/ 0x00000b00, - /*0201*/ 0x00000100, - /*0202*/ 0x00640000, - /*0203*/ 0x00000000, - /*0204*/ 0x0000ffff, - /*0205*/ 0x00000000, - /*0206*/ 0x0000ffff, - /*0207*/ 0x00000000, - /*0208*/ 0x0000ffff, - /*0209*/ 0x0000304c, - /*020a*/ 0x00000200, - /*020b*/ 0x00000200, - /*020c*/ 0x00000200, - /*020d*/ 0x00000200, - /*020e*/ 0x0000304c, - /*020f*/ 0x00000200, - /*0210*/ 0x00000200, - /*0211*/ 0x00000200, - /*0212*/ 0x00000200, - /*0213*/ 0x0000304c, - /*0214*/ 0x00000200, - /*0215*/ 0x00000200, - /*0216*/ 0x00000200, - /*0217*/ 0x00000200, - /*0218*/ 0x00010000, - /*0219*/ 0x00000003, - /*021a*/ 0x01000001, - /*021b*/ 0x00000000, - /*021c*/ 0x00000000, - /*021d*/ 0x00000000, - /*021e*/ 0x00000000, - /*021f*/ 0x00000000, - /*0220*/ 0x00000000, - /*0221*/ 0x00000000, - /*0222*/ 0x00000000, - /*0223*/ 0x00000000, - /*0224*/ 0x00000000, - /*0225*/ 0x00000000, - /*0226*/ 0x00000000, - /*0227*/ 0x00000000, - /*0228*/ 0x00000000, - /*0229*/ 0x00000000, - /*022a*/ 0x00000000, - /*022b*/ 0x0f000101, - /*022c*/ 0x08492d25, - /*022d*/ 0x500e0c04, - /*022e*/ 0x0002500e, - /*022f*/ 0x00000301, - /*0230*/ 0x00000046, - /*0231*/ 0x000000cf, - /*0232*/ 0x00001826, - /*0233*/ 0x000000cf, - /*0234*/ 0x00001826, - /*0235*/ 0x00000005, - /*0236*/ 0x00000000, - /*0237*/ 0x00000000, - /*0238*/ 0x00000000, - /*0239*/ 0x00000000, - /*023a*/ 0x00000000, - /*023b*/ 0x00000000, - /*023c*/ 0x00000000, - /*023d*/ 0x00000000, - /*023e*/ 0x04010000, - /*023f*/ 0x00000404, - /*0240*/ 0x0101280a, - /*0241*/ 0x00000000, - /*0242*/ 0x00000000, - /*0243*/ 0x0003000f, - /*0244*/ 0x00000018, - /*0245*/ 0x00000000, - /*0246*/ 0x00000000, - /*0247*/ 0x00060002, - /*0248*/ 0x00010001, - /*0249*/ 0x01000101, - /*024a*/ 0x04020201, - /*024b*/ 0x00080804, - /*024c*/ 0x00000000, - /*024d*/ 0x08030000, - /*024e*/ 0x15150408, - /*024f*/ 0x00000000, - /*0250*/ 0x00000000, - /*0251*/ 0x00000000, - /*0252*/ 0x0f0f0000, - /*0253*/ 0x0000001e, - /*0254*/ 0x00000000, - /*0255*/ 0x01000300, - /*0256*/ 0x00000100, - /*0257*/ 0x00000000, - /*0258*/ 0x00000000, - /*0259*/ 0x01000000, - /*025a*/ 0x00000101, - /*025b*/ 0x55555a5a, - /*025c*/ 0x55555a5a, - /*025d*/ 0x55555a5a, - /*025e*/ 0x55555a5a, - /*025f*/ 0x0e0e0001, - /*0260*/ 0x0c0c000e, - /*0261*/ 0x0601000c, - /*0262*/ 0x17170106, - /*0263*/ 0x00020202, - /*0264*/ 0x03000000, - /*0265*/ 0x00000000, - /*0266*/ 0x00181703, - /*0267*/ 0x00280006, - /*0268*/ 0x00280016, - /*0269*/ 0x00000016, - /*026a*/ 0x00000000, - /*026b*/ 0x00000000, - /*026c*/ 0x00000000, - /*026d*/ 0x0a000000, - /*026e*/ 0x00010a14, - /*026f*/ 0x00030005, - /*0270*/ 0x0003018d, - /*0271*/ 0x000a018d, - /*0272*/ 0x00060100, - /*0273*/ 0x01000006, - /*0274*/ 0x018e018e, - /*0275*/ 0x018e0100, - /*0276*/ 0x1111018e, - /*0277*/ 0x10010204, - /*0278*/ 0x09090650, - /*0279*/ 0xff110202, - /*027a*/ 0x00ff1000, - /*027b*/ 0x00ff1000, - /*027c*/ 0x04041000, - /*027d*/ 0x18020100, - /*027e*/ 0x01010018, - /*027f*/ 0x004a004a, - /*0280*/ 0x004b004a, - /*0281*/ 0x050f0000, - /*0282*/ 0x0c01021e, - /*0283*/ 0x34000000, - /*0284*/ 0x00000000, - /*0285*/ 0x00000000, - /*0286*/ 0x00000000, - /*0287*/ 0x00000000, - /*0288*/ 0x36312ed4, - /*0289*/ 0x2ed41111, - /*028a*/ 0x11113631, - /*028b*/ 0x36312ed4, - /*028c*/ 0xd4001111, - /*028d*/ 0x1136312e, - /*028e*/ 0x312ed411, - /*028f*/ 0xd4111136, - /*0290*/ 0x1136312e, - /*0291*/ 0x2ed40011, - /*0292*/ 0x11113631, - /*0293*/ 0x36312ed4, - /*0294*/ 0x2ed41111, - /*0295*/ 0x11113631, - /*0296*/ 0x312ed400, - /*0297*/ 0xd4111136, - /*0298*/ 0x1136312e, - /*0299*/ 0x312ed411, - /*029a*/ 0x00111136, - /*029b*/ 0x018d0200, - /*029c*/ 0x018d018d, - /*029d*/ 0x1d220c08, - /*029e*/ 0x00001f12, - /*029f*/ 0x4301b344, - /*02a0*/ 0x10172006, - /*02a1*/ 0x121d220c, - /*02a2*/ 0x01b3441f, - /*02a3*/ 0x17200643, - /*02a4*/ 0x1d220c10, - /*02a5*/ 0x00001f12, - /*02a6*/ 0x4301b344, - /*02a7*/ 0x10172006, - /*02a8*/ 0x00020002, - /*02a9*/ 0x00020002, - /*02aa*/ 0x00020002, - /*02ab*/ 0x00020002, - /*02ac*/ 0x00020002, - /*02ad*/ 0x00000000, - /*02ae*/ 0x00000000, - /*02af*/ 0x00000000, - /*02b0*/ 0x00000000, - /*02b1*/ 0x00000000, - /*02b2*/ 0x00000000, - /*02b3*/ 0x00000000, - /*02b4*/ 0x00000000, - /*02b5*/ 0x00000000, - /*02b6*/ 0x00000000, - /*02b7*/ 0x00000000, - /*02b8*/ 0x00000000, - /*02b9*/ 0x00000400, - /*02ba*/ 0x05040302, - /*02bb*/ 0x01000f0e, - /*02bc*/ 0x07060504, - /*02bd*/ 0x03020100, - /*02be*/ 0x02010000, - /*02bf*/ 0x00000103, - /*02c0*/ 0x0000304c, - /*02c1*/ 0x0001e2f8, - /*02c2*/ 0x0000304c, - /*02c3*/ 0x0001e2f8, - /*02c4*/ 0x0000304c, - /*02c5*/ 0x0001e2f8, - /*02c6*/ 0x08000000, - /*02c7*/ 0x00000100, - /*02c8*/ 0x00000000, - /*02c9*/ 0x00000000, - /*02ca*/ 0x00000000, - /*02cb*/ 0x00000000, - /*02cc*/ 0x00010000, - /*02cd*/ 0x00000000, - /*02ce*/ 0x00000000, - /*02cf*/ 0x00000000, - /*02d0*/ 0x00000000, - /*02d1*/ 0x00000000, - /*02d2*/ 0x00000000, - /*02d3*/ 0x00000000, - /*02d4*/ 0x00000000, - /*02d5*/ 0x00000000, - /*02d6*/ 0x00000000, - /*02d7*/ 0x00000000, - /*02d8*/ 0x00000000, - /*02d9*/ 0x00000000, - /*02da*/ 0x00000000, - /*02db*/ 0x00000000, - /*02dc*/ 0x00000000, - /*02dd*/ 0x00000000, - /*02de*/ 0x00000000, - /*02df*/ 0x00000000, - /*02e0*/ 0x00000000, - /*02e1*/ 0x00000000, - /*02e2*/ 0x00000000, - /*02e3*/ 0x00000000, - /*02e4*/ 0x00000000, - /*02e5*/ 0x00000000, - /*02e6*/ 0x00000000, - /*02e7*/ 0x00000000, - /*02e8*/ 0x00000000, - /*02e9*/ 0x00000000, - /*02ea*/ 0x00000000, - /*02eb*/ 0x00000000, - /*02ec*/ 0x00000000, - /*02ed*/ 0x00000000, - /*02ee*/ 0x00000002, - /*02ef*/ 0x00000000, - /*02f0*/ 0x00000000, - /*02f1*/ 0x00000000, - /*02f2*/ 0x00000000, - /*02f3*/ 0x00000000, - /*02f4*/ 0x00000000 -}; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h deleted file mode 100644 index b491f0e91..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h +++ /dev/null @@ -1,468 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define DDR_PHY_SLICE_REGSET_OFS_M3 0x0800 -#define DDR_PHY_ADR_V_REGSET_OFS_M3 0x0a00 -#define DDR_PHY_ADR_I_REGSET_OFS_M3 0x0a80 -#define DDR_PHY_ADR_G_REGSET_OFS_M3 0x0b80 -#define DDR_PI_REGSET_OFS_M3 0x0200 - -#define DDR_PHY_SLICE_REGSET_SIZE_M3 0x80 -#define DDR_PHY_ADR_V_REGSET_SIZE_M3 0x80 -#define DDR_PHY_ADR_I_REGSET_SIZE_M3 0x80 -#define DDR_PHY_ADR_G_REGSET_SIZE_M3 0x80 -#define DDR_PI_REGSET_SIZE_M3 0x100 - -#define DDR_PHY_SLICE_REGSET_NUM_M3 89 -#define DDR_PHY_ADR_V_REGSET_NUM_M3 37 -#define DDR_PHY_ADR_I_REGSET_NUM_M3 37 -#define DDR_PHY_ADR_G_REGSET_NUM_M3 64 -#define DDR_PI_REGSET_NUM_M3 202 - -static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = { - /*0800*/ 0x76543210, - /*0801*/ 0x0004f008, - /*0802*/ 0x00000000, - /*0803*/ 0x00000000, - /*0804*/ 0x00010000, - /*0805*/ 0x036e6e0e, - /*0806*/ 0x026e6e0e, - /*0807*/ 0x00010300, - /*0808*/ 0x04000100, - /*0809*/ 0x00000300, - /*080a*/ 0x001700c0, - /*080b*/ 0x00b00201, - /*080c*/ 0x00030020, - /*080d*/ 0x00000000, - /*080e*/ 0x00000000, - /*080f*/ 0x00000000, - /*0810*/ 0x00000000, - /*0811*/ 0x00000000, - /*0812*/ 0x00000000, - /*0813*/ 0x00000000, - /*0814*/ 0x09000000, - /*0815*/ 0x04080000, - /*0816*/ 0x04080400, - /*0817*/ 0x00000000, - /*0818*/ 0x32103210, - /*0819*/ 0x00800708, - /*081a*/ 0x000f000c, - /*081b*/ 0x00000100, - /*081c*/ 0x55aa55aa, - /*081d*/ 0x33cc33cc, - /*081e*/ 0x0ff00ff0, - /*081f*/ 0x0f0ff0f0, - /*0820*/ 0x00018e38, - /*0821*/ 0x00000000, - /*0822*/ 0x00000000, - /*0823*/ 0x00000000, - /*0824*/ 0x00000000, - /*0825*/ 0x00000000, - /*0826*/ 0x00000000, - /*0827*/ 0x00000000, - /*0828*/ 0x00000000, - /*0829*/ 0x00000000, - /*082a*/ 0x00000000, - /*082b*/ 0x00000000, - /*082c*/ 0x00000000, - /*082d*/ 0x00000000, - /*082e*/ 0x00000000, - /*082f*/ 0x00000000, - /*0830*/ 0x00000000, - /*0831*/ 0x00000000, - /*0832*/ 0x00000000, - /*0833*/ 0x00200000, - /*0834*/ 0x08200820, - /*0835*/ 0x08200820, - /*0836*/ 0x08200820, - /*0837*/ 0x08200820, - /*0838*/ 0x08200820, - /*0839*/ 0x00000820, - /*083a*/ 0x03000300, - /*083b*/ 0x03000300, - /*083c*/ 0x03000300, - /*083d*/ 0x03000300, - /*083e*/ 0x00000300, - /*083f*/ 0x00000000, - /*0840*/ 0x00000000, - /*0841*/ 0x00000000, - /*0842*/ 0x00000000, - /*0843*/ 0x00a00000, - /*0844*/ 0x00a000a0, - /*0845*/ 0x00a000a0, - /*0846*/ 0x00a000a0, - /*0847*/ 0x00a000a0, - /*0848*/ 0x00a000a0, - /*0849*/ 0x00a000a0, - /*084a*/ 0x00a000a0, - /*084b*/ 0x00a000a0, - /*084c*/ 0x010900a0, - /*084d*/ 0x02000104, - /*084e*/ 0x00000000, - /*084f*/ 0x00010000, - /*0850*/ 0x00000200, - /*0851*/ 0x4041a151, - /*0852*/ 0xc00141a0, - /*0853*/ 0x0e0100c0, - /*0854*/ 0x0010000c, - /*0855*/ 0x0c064208, - /*0856*/ 0x000f0c18, - /*0857*/ 0x00e00140, - /*0858*/ 0x00000c20 -}; - -static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = { - /*0a00*/ 0x00000000, - /*0a01*/ 0x00000000, - /*0a02*/ 0x00000000, - /*0a03*/ 0x00000000, - /*0a04*/ 0x00000000, - /*0a05*/ 0x00000000, - /*0a06*/ 0x00000002, - /*0a07*/ 0x00000000, - /*0a08*/ 0x00000000, - /*0a09*/ 0x00000000, - /*0a0a*/ 0x00400320, - /*0a0b*/ 0x00000040, - /*0a0c*/ 0x00dcba98, - /*0a0d*/ 0x00000000, - /*0a0e*/ 0x00dcba98, - /*0a0f*/ 0x01000000, - /*0a10*/ 0x00020003, - /*0a11*/ 0x00000000, - /*0a12*/ 0x00000000, - /*0a13*/ 0x00000000, - /*0a14*/ 0x0000002a, - /*0a15*/ 0x00000015, - /*0a16*/ 0x00000015, - /*0a17*/ 0x0000002a, - /*0a18*/ 0x00000033, - /*0a19*/ 0x0000000c, - /*0a1a*/ 0x0000000c, - /*0a1b*/ 0x00000033, - /*0a1c*/ 0x0a418820, - /*0a1d*/ 0x003f0000, - /*0a1e*/ 0x0000003f, - /*0a1f*/ 0x0002c06e, - /*0a20*/ 0x02c002c0, - /*0a21*/ 0x02c002c0, - /*0a22*/ 0x000002c0, - /*0a23*/ 0x42080010, - /*0a24*/ 0x00000003 -}; - -static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = { - /*0a80*/ 0x04040404, - /*0a81*/ 0x00000404, - /*0a82*/ 0x00000000, - /*0a83*/ 0x00000000, - /*0a84*/ 0x00000000, - /*0a85*/ 0x00000000, - /*0a86*/ 0x00000002, - /*0a87*/ 0x00000000, - /*0a88*/ 0x00000000, - /*0a89*/ 0x00000000, - /*0a8a*/ 0x00400320, - /*0a8b*/ 0x00000040, - /*0a8c*/ 0x00000000, - /*0a8d*/ 0x00000000, - /*0a8e*/ 0x00000000, - /*0a8f*/ 0x01000000, - /*0a90*/ 0x00020003, - /*0a91*/ 0x00000000, - /*0a92*/ 0x00000000, - /*0a93*/ 0x00000000, - /*0a94*/ 0x0000002a, - /*0a95*/ 0x00000015, - /*0a96*/ 0x00000015, - /*0a97*/ 0x0000002a, - /*0a98*/ 0x00000033, - /*0a99*/ 0x0000000c, - /*0a9a*/ 0x0000000c, - /*0a9b*/ 0x00000033, - /*0a9c*/ 0x00000000, - /*0a9d*/ 0x00000000, - /*0a9e*/ 0x00000000, - /*0a9f*/ 0x0002c06e, - /*0aa0*/ 0x02c002c0, - /*0aa1*/ 0x02c002c0, - /*0aa2*/ 0x000002c0, - /*0aa3*/ 0x42080010, - /*0aa4*/ 0x00000003 -}; - -static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = { - /*0b80*/ 0x00000001, - /*0b81*/ 0x00000000, - /*0b82*/ 0x00000005, - /*0b83*/ 0x04000f00, - /*0b84*/ 0x00020080, - /*0b85*/ 0x00020055, - /*0b86*/ 0x00000000, - /*0b87*/ 0x00000000, - /*0b88*/ 0x00000000, - /*0b89*/ 0x00000050, - /*0b8a*/ 0x00000000, - /*0b8b*/ 0x01010100, - /*0b8c*/ 0x00000600, - /*0b8d*/ 0x50640000, - /*0b8e*/ 0x01421142, - /*0b8f*/ 0x00000142, - /*0b90*/ 0x00000000, - /*0b91*/ 0x000f1600, - /*0b92*/ 0x0f160f16, - /*0b93*/ 0x0f160f16, - /*0b94*/ 0x00000003, - /*0b95*/ 0x0002c000, - /*0b96*/ 0x02c002c0, - /*0b97*/ 0x000002c0, - /*0b98*/ 0x03421342, - /*0b99*/ 0x00000342, - /*0b9a*/ 0x00000000, - /*0b9b*/ 0x00000000, - /*0b9c*/ 0x05020000, - /*0b9d*/ 0x00000000, - /*0b9e*/ 0x00027f6e, - /*0b9f*/ 0x047f027f, - /*0ba0*/ 0x00027f6e, - /*0ba1*/ 0x00047f6e, - /*0ba2*/ 0x0003554f, - /*0ba3*/ 0x0001554f, - /*0ba4*/ 0x0001554f, - /*0ba5*/ 0x0001554f, - /*0ba6*/ 0x0001554f, - /*0ba7*/ 0x00003fee, - /*0ba8*/ 0x0001554f, - /*0ba9*/ 0x00003fee, - /*0baa*/ 0x0001554f, - /*0bab*/ 0x00027f6e, - /*0bac*/ 0x0001554f, - /*0bad*/ 0x00000000, - /*0bae*/ 0x00000000, - /*0baf*/ 0x00000000, - /*0bb0*/ 0x65000000, - /*0bb1*/ 0x00000000, - /*0bb2*/ 0x00000000, - /*0bb3*/ 0x00000201, - /*0bb4*/ 0x00000000, - /*0bb5*/ 0x00000000, - /*0bb6*/ 0x00000000, - /*0bb7*/ 0x00000000, - /*0bb8*/ 0x00000000, - /*0bb9*/ 0x00000000, - /*0bba*/ 0x00000000, - /*0bbb*/ 0x00000000, - /*0bbc*/ 0x06e40000, - /*0bbd*/ 0x00000000, - /*0bbe*/ 0x00000000, - /*0bbf*/ 0x00010000 -}; - -static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = { - /*0200*/ 0x00000b00, - /*0201*/ 0x00000100, - /*0202*/ 0x00000000, - /*0203*/ 0x0000ffff, - /*0204*/ 0x00000000, - /*0205*/ 0x0000ffff, - /*0206*/ 0x00000000, - /*0207*/ 0x304cffff, - /*0208*/ 0x00000200, - /*0209*/ 0x00000200, - /*020a*/ 0x00000200, - /*020b*/ 0x00000200, - /*020c*/ 0x0000304c, - /*020d*/ 0x00000200, - /*020e*/ 0x00000200, - /*020f*/ 0x00000200, - /*0210*/ 0x00000200, - /*0211*/ 0x0000304c, - /*0212*/ 0x00000200, - /*0213*/ 0x00000200, - /*0214*/ 0x00000200, - /*0215*/ 0x00000200, - /*0216*/ 0x00010000, - /*0217*/ 0x00000003, - /*0218*/ 0x01000001, - /*0219*/ 0x00000000, - /*021a*/ 0x00000000, - /*021b*/ 0x00000000, - /*021c*/ 0x00000000, - /*021d*/ 0x00000000, - /*021e*/ 0x00000000, - /*021f*/ 0x00000000, - /*0220*/ 0x00000000, - /*0221*/ 0x00000000, - /*0222*/ 0x00000000, - /*0223*/ 0x00000000, - /*0224*/ 0x00000000, - /*0225*/ 0x00000000, - /*0226*/ 0x00000000, - /*0227*/ 0x00000000, - /*0228*/ 0x00000000, - /*0229*/ 0x0f000101, - /*022a*/ 0x08492d25, - /*022b*/ 0x0e0c0004, - /*022c*/ 0x000e5000, - /*022d*/ 0x00000250, - /*022e*/ 0x00460003, - /*022f*/ 0x182600cf, - /*0230*/ 0x182600cf, - /*0231*/ 0x00000005, - /*0232*/ 0x00000000, - /*0233*/ 0x00000000, - /*0234*/ 0x00000000, - /*0235*/ 0x00000000, - /*0236*/ 0x00000000, - /*0237*/ 0x00000000, - /*0238*/ 0x00000000, - /*0239*/ 0x01000000, - /*023a*/ 0x00040404, - /*023b*/ 0x01280a00, - /*023c*/ 0x00000000, - /*023d*/ 0x000f0000, - /*023e*/ 0x00001803, - /*023f*/ 0x00000000, - /*0240*/ 0x00000000, - /*0241*/ 0x00060002, - /*0242*/ 0x00010001, - /*0243*/ 0x01000101, - /*0244*/ 0x04020201, - /*0245*/ 0x00080804, - /*0246*/ 0x00000000, - /*0247*/ 0x08030000, - /*0248*/ 0x15150408, - /*0249*/ 0x00000000, - /*024a*/ 0x00000000, - /*024b*/ 0x00000000, - /*024c*/ 0x000f0f00, - /*024d*/ 0x0000001e, - /*024e*/ 0x00000000, - /*024f*/ 0x01000300, - /*0250*/ 0x00000000, - /*0251*/ 0x00000000, - /*0252*/ 0x01000000, - /*0253*/ 0x00010101, - /*0254*/ 0x000e0e0e, - /*0255*/ 0x000c0c0c, - /*0256*/ 0x02060601, - /*0257*/ 0x00000000, - /*0258*/ 0x00000003, - /*0259*/ 0x00181703, - /*025a*/ 0x00280006, - /*025b*/ 0x00280016, - /*025c*/ 0x00000016, - /*025d*/ 0x00000000, - /*025e*/ 0x00000000, - /*025f*/ 0x00000000, - /*0260*/ 0x140a0000, - /*0261*/ 0x0005010a, - /*0262*/ 0x03018d03, - /*0263*/ 0x000a018d, - /*0264*/ 0x00060100, - /*0265*/ 0x01000006, - /*0266*/ 0x018e018e, - /*0267*/ 0x018e0100, - /*0268*/ 0x1111018e, - /*0269*/ 0x10010204, - /*026a*/ 0x09090650, - /*026b*/ 0x20110202, - /*026c*/ 0x00201000, - /*026d*/ 0x00201000, - /*026e*/ 0x04041000, - /*026f*/ 0x18020100, - /*0270*/ 0x00010118, - /*0271*/ 0x004b004a, - /*0272*/ 0x050f0000, - /*0273*/ 0x0c01021e, - /*0274*/ 0x34000000, - /*0275*/ 0x00000000, - /*0276*/ 0x00000000, - /*0277*/ 0x00000000, - /*0278*/ 0x0000d400, - /*0279*/ 0x0031002e, - /*027a*/ 0x00111136, - /*027b*/ 0x002e00d4, - /*027c*/ 0x11360031, - /*027d*/ 0x0000d411, - /*027e*/ 0x0031002e, - /*027f*/ 0x00111136, - /*0280*/ 0x002e00d4, - /*0281*/ 0x11360031, - /*0282*/ 0x0000d411, - /*0283*/ 0x0031002e, - /*0284*/ 0x00111136, - /*0285*/ 0x002e00d4, - /*0286*/ 0x11360031, - /*0287*/ 0x00d40011, - /*0288*/ 0x0031002e, - /*0289*/ 0x00111136, - /*028a*/ 0x002e00d4, - /*028b*/ 0x11360031, - /*028c*/ 0x0000d411, - /*028d*/ 0x0031002e, - /*028e*/ 0x00111136, - /*028f*/ 0x002e00d4, - /*0290*/ 0x11360031, - /*0291*/ 0x0000d411, - /*0292*/ 0x0031002e, - /*0293*/ 0x00111136, - /*0294*/ 0x002e00d4, - /*0295*/ 0x11360031, - /*0296*/ 0x02000011, - /*0297*/ 0x018d018d, - /*0298*/ 0x0c08018d, - /*0299*/ 0x1f121d22, - /*029a*/ 0x4301b344, - /*029b*/ 0x10172006, - /*029c*/ 0x1d220c10, - /*029d*/ 0x00001f12, - /*029e*/ 0x4301b344, - /*029f*/ 0x10172006, - /*02a0*/ 0x1d220c10, - /*02a1*/ 0x00001f12, - /*02a2*/ 0x4301b344, - /*02a3*/ 0x10172006, - /*02a4*/ 0x02000210, - /*02a5*/ 0x02000200, - /*02a6*/ 0x02000200, - /*02a7*/ 0x02000200, - /*02a8*/ 0x02000200, - /*02a9*/ 0x00000000, - /*02aa*/ 0x00000000, - /*02ab*/ 0x00000000, - /*02ac*/ 0x00000000, - /*02ad*/ 0x00000000, - /*02ae*/ 0x00000000, - /*02af*/ 0x00000000, - /*02b0*/ 0x00000000, - /*02b1*/ 0x00000000, - /*02b2*/ 0x00000000, - /*02b3*/ 0x00000000, - /*02b4*/ 0x00000000, - /*02b5*/ 0x00000400, - /*02b6*/ 0x15141312, - /*02b7*/ 0x11100f0e, - /*02b8*/ 0x080b0c0d, - /*02b9*/ 0x05040a09, - /*02ba*/ 0x01000706, - /*02bb*/ 0x00000302, - /*02bc*/ 0x01030201, - /*02bd*/ 0x00304c00, - /*02be*/ 0x0001e2f8, - /*02bf*/ 0x0000304c, - /*02c0*/ 0x0001e2f8, - /*02c1*/ 0x0000304c, - /*02c2*/ 0x0001e2f8, - /*02c3*/ 0x08000000, - /*02c4*/ 0x00000100, - /*02c5*/ 0x00000000, - /*02c6*/ 0x00000000, - /*02c7*/ 0x00000000, - /*02c8*/ 0x00000000, - /*02c9*/ 0x00000002 -}; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h deleted file mode 100644 index 8d80842fd..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h +++ /dev/null @@ -1,587 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define DDR_PHY_SLICE_REGSET_OFS_M3N 0x0800 -#define DDR_PHY_ADR_V_REGSET_OFS_M3N 0x0a00 -#define DDR_PHY_ADR_I_REGSET_OFS_M3N 0x0a80 -#define DDR_PHY_ADR_G_REGSET_OFS_M3N 0x0b80 -#define DDR_PI_REGSET_OFS_M3N 0x0200 - -#define DDR_PHY_SLICE_REGSET_SIZE_M3N 0x80 -#define DDR_PHY_ADR_V_REGSET_SIZE_M3N 0x80 -#define DDR_PHY_ADR_I_REGSET_SIZE_M3N 0x80 -#define DDR_PHY_ADR_G_REGSET_SIZE_M3N 0x80 -#define DDR_PI_REGSET_SIZE_M3N 0x100 - -#define DDR_PHY_SLICE_REGSET_NUM_M3N 101 -#define DDR_PHY_ADR_V_REGSET_NUM_M3N 37 -#define DDR_PHY_ADR_I_REGSET_NUM_M3N 37 -#define DDR_PHY_ADR_G_REGSET_NUM_M3N 87 -#define DDR_PI_REGSET_NUM_M3N 286 - -static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = { - /*0800*/ 0x76543210, - /*0801*/ 0x0004f008, - /*0802*/ 0x00020200, - /*0803*/ 0x00000000, - /*0804*/ 0x00000000, - /*0805*/ 0x00010000, - /*0806*/ 0x036e6e0e, - /*0807*/ 0x026e6e0e, - /*0808*/ 0x00000103, - /*0809*/ 0x00040001, - /*080a*/ 0x00000103, - /*080b*/ 0x00000001, - /*080c*/ 0x00000000, - /*080d*/ 0x00000000, - /*080e*/ 0x00000100, - /*080f*/ 0x001800c0, - /*0810*/ 0x020100b0, - /*0811*/ 0x00030020, - /*0812*/ 0x00000000, - /*0813*/ 0x00000000, - /*0814*/ 0x0000aaaa, - /*0815*/ 0x00005555, - /*0816*/ 0x0000b5b5, - /*0817*/ 0x00004a4a, - /*0818*/ 0x00000000, - /*0819*/ 0x09000000, - /*081a*/ 0x04080000, - /*081b*/ 0x08040000, - /*081c*/ 0x00000004, - /*081d*/ 0x00800710, - /*081e*/ 0x000f000c, - /*081f*/ 0x00000100, - /*0820*/ 0x55aa55aa, - /*0821*/ 0x33cc33cc, - /*0822*/ 0x0ff00ff0, - /*0823*/ 0x0f0ff0f0, - /*0824*/ 0x00018e38, - /*0825*/ 0x00000000, - /*0826*/ 0x00000000, - /*0827*/ 0x00000000, - /*0828*/ 0x00000000, - /*0829*/ 0x00000000, - /*082a*/ 0x00000000, - /*082b*/ 0x00000000, - /*082c*/ 0x00000000, - /*082d*/ 0x00000000, - /*082e*/ 0x00000000, - /*082f*/ 0x00000000, - /*0830*/ 0x00000000, - /*0831*/ 0x00000000, - /*0832*/ 0x00000000, - /*0833*/ 0x00000000, - /*0834*/ 0x00000000, - /*0835*/ 0x00000000, - /*0836*/ 0x00000000, - /*0837*/ 0x00000000, - /*0838*/ 0x00000000, - /*0839*/ 0x00000000, - /*083a*/ 0x00000104, - /*083b*/ 0x00082020, - /*083c*/ 0x08200820, - /*083d*/ 0x08200820, - /*083e*/ 0x08200820, - /*083f*/ 0x08200820, - /*0840*/ 0x08200820, - /*0841*/ 0x00000000, - /*0842*/ 0x00000000, - /*0843*/ 0x03000300, - /*0844*/ 0x03000300, - /*0845*/ 0x03000300, - /*0846*/ 0x03000300, - /*0847*/ 0x00000300, - /*0848*/ 0x00000000, - /*0849*/ 0x00000000, - /*084a*/ 0x00000000, - /*084b*/ 0x00000000, - /*084c*/ 0x00000000, - /*084d*/ 0x00a000a0, - /*084e*/ 0x00a000a0, - /*084f*/ 0x00a000a0, - /*0850*/ 0x00a000a0, - /*0851*/ 0x00a000a0, - /*0852*/ 0x00a000a0, - /*0853*/ 0x00a000a0, - /*0854*/ 0x00a000a0, - /*0855*/ 0x00a000a0, - /*0856*/ 0x01040119, - /*0857*/ 0x00000200, - /*0858*/ 0x01000000, - /*0859*/ 0x00000200, - /*085a*/ 0x00000004, - /*085b*/ 0x4041a151, - /*085c*/ 0x0141c0a0, - /*085d*/ 0x0000c0c0, - /*085e*/ 0x0e0c000e, - /*085f*/ 0x10001000, - /*0860*/ 0x0c073e42, - /*0861*/ 0x000f0c28, - /*0862*/ 0x00e00140, - /*0863*/ 0x000c0020, - /*0864*/ 0x00000203 -}; - -static const uint32_t DDR_PHY_ADR_V_REGSET_M3N[DDR_PHY_ADR_V_REGSET_NUM_M3N] = { - /*0a00*/ 0x00000000, - /*0a01*/ 0x00000000, - /*0a02*/ 0x00000000, - /*0a03*/ 0x00000000, - /*0a04*/ 0x00000000, - /*0a05*/ 0x00000000, - /*0a06*/ 0x00000000, - /*0a07*/ 0x01000000, - /*0a08*/ 0x00020000, - /*0a09*/ 0x00000000, - /*0a0a*/ 0x00000000, - /*0a0b*/ 0x00000000, - /*0a0c*/ 0x00400000, - /*0a0d*/ 0x00000080, - /*0a0e*/ 0x00dcba98, - /*0a0f*/ 0x03000000, - /*0a10*/ 0x00000200, - /*0a11*/ 0x00000000, - /*0a12*/ 0x00000000, - /*0a13*/ 0x00000000, - /*0a14*/ 0x0000002a, - /*0a15*/ 0x00000015, - /*0a16*/ 0x00000015, - /*0a17*/ 0x0000002a, - /*0a18*/ 0x00000033, - /*0a19*/ 0x0000000c, - /*0a1a*/ 0x0000000c, - /*0a1b*/ 0x00000033, - /*0a1c*/ 0x0a418820, - /*0a1d*/ 0x003f0000, - /*0a1e*/ 0x0000013f, - /*0a1f*/ 0x0002c06e, - /*0a20*/ 0x02c002c0, - /*0a21*/ 0x02c002c0, - /*0a22*/ 0x000002c0, - /*0a23*/ 0x42080010, - /*0a24*/ 0x0000033e -}; - -static const uint32_t DDR_PHY_ADR_I_REGSET_M3N[DDR_PHY_ADR_I_REGSET_NUM_M3N] = { - /*0a80*/ 0x00000000, - /*0a81*/ 0x00000000, - /*0a82*/ 0x00000000, - /*0a83*/ 0x00000000, - /*0a84*/ 0x00000000, - /*0a85*/ 0x00000000, - /*0a86*/ 0x00000000, - /*0a87*/ 0x01000000, - /*0a88*/ 0x00020000, - /*0a89*/ 0x00000000, - /*0a8a*/ 0x00000000, - /*0a8b*/ 0x00000000, - /*0a8c*/ 0x00400000, - /*0a8d*/ 0x00000080, - /*0a8e*/ 0x00000000, - /*0a8f*/ 0x03000000, - /*0a90*/ 0x00000200, - /*0a91*/ 0x00000000, - /*0a92*/ 0x00000000, - /*0a93*/ 0x00000000, - /*0a94*/ 0x0000002a, - /*0a95*/ 0x00000015, - /*0a96*/ 0x00000015, - /*0a97*/ 0x0000002a, - /*0a98*/ 0x00000033, - /*0a99*/ 0x0000000c, - /*0a9a*/ 0x0000000c, - /*0a9b*/ 0x00000033, - /*0a9c*/ 0x00000000, - /*0a9d*/ 0x00000000, - /*0a9e*/ 0x00000000, - /*0a9f*/ 0x0002c06e, - /*0aa0*/ 0x02c002c0, - /*0aa1*/ 0x02c002c0, - /*0aa2*/ 0x000002c0, - /*0aa3*/ 0x42080010, - /*0aa4*/ 0x0000033e -}; - -static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = { - /*0b80*/ 0x00000000, - /*0b81*/ 0x00000100, - /*0b82*/ 0x00000000, - /*0b83*/ 0x00050000, - /*0b84*/ 0x00000000, - /*0b85*/ 0x0004000f, - /*0b86*/ 0x00280080, - /*0b87*/ 0x02005502, - /*0b88*/ 0x00000000, - /*0b89*/ 0x00000000, - /*0b8a*/ 0x00000000, - /*0b8b*/ 0x00000050, - /*0b8c*/ 0x00000000, - /*0b8d*/ 0x01010100, - /*0b8e*/ 0x00010000, - /*0b8f*/ 0x00000000, - /*0b90*/ 0x00000101, - /*0b91*/ 0x00000000, - /*0b92*/ 0x00000000, - /*0b93*/ 0x00000000, - /*0b94*/ 0x00000000, - /*0b95*/ 0x00005064, - /*0b96*/ 0x01421142, - /*0b97*/ 0x00000142, - /*0b98*/ 0x00000000, - /*0b99*/ 0x000f1600, - /*0b9a*/ 0x0f160f16, - /*0b9b*/ 0x0f160f16, - /*0b9c*/ 0x00000003, - /*0b9d*/ 0x0002c000, - /*0b9e*/ 0x02c002c0, - /*0b9f*/ 0x000002c0, - /*0ba0*/ 0x08040201, - /*0ba1*/ 0x03421342, - /*0ba2*/ 0x00000342, - /*0ba3*/ 0x00000000, - /*0ba4*/ 0x00000000, - /*0ba5*/ 0x05030000, - /*0ba6*/ 0x00010700, - /*0ba7*/ 0x00000014, - /*0ba8*/ 0x00027f6e, - /*0ba9*/ 0x047f027f, - /*0baa*/ 0x00027f6e, - /*0bab*/ 0x00047f6e, - /*0bac*/ 0x0003554f, - /*0bad*/ 0x0001554f, - /*0bae*/ 0x0001554f, - /*0baf*/ 0x0001554f, - /*0bb0*/ 0x0001554f, - /*0bb1*/ 0x00003fee, - /*0bb2*/ 0x0001554f, - /*0bb3*/ 0x00003fee, - /*0bb4*/ 0x0001554f, - /*0bb5*/ 0x00027f6e, - /*0bb6*/ 0x0001554f, - /*0bb7*/ 0x00004011, - /*0bb8*/ 0x00004410, - /*0bb9*/ 0x00000000, - /*0bba*/ 0x00000000, - /*0bbb*/ 0x00000000, - /*0bbc*/ 0x00000265, - /*0bbd*/ 0x00000000, - /*0bbe*/ 0x00040401, - /*0bbf*/ 0x00000000, - /*0bc0*/ 0x03000000, - /*0bc1*/ 0x00000020, - /*0bc2*/ 0x00000000, - /*0bc3*/ 0x00000000, - /*0bc4*/ 0x04102006, - /*0bc5*/ 0x00041020, - /*0bc6*/ 0x01c98c98, - /*0bc7*/ 0x00400000, - /*0bc8*/ 0x00000000, - /*0bc9*/ 0x0001ffff, - /*0bca*/ 0x00000000, - /*0bcb*/ 0x00000000, - /*0bcc*/ 0x00000001, - /*0bcd*/ 0x00000000, - /*0bce*/ 0x00000000, - /*0bcf*/ 0x00000000, - /*0bd0*/ 0x76543210, - /*0bd1*/ 0x06010198, - /*0bd2*/ 0x00000000, - /*0bd3*/ 0x00000000, - /*0bd4*/ 0x04070000, - /*0bd5*/ 0x00000001, - /*0bd6*/ 0x00000f00 -}; - -static const uint32_t DDR_PI_REGSET_M3N[DDR_PI_REGSET_NUM_M3N] = { - /*0200*/ 0x00000b00, - /*0201*/ 0x00000101, - /*0202*/ 0x01640000, - /*0203*/ 0x00000014, - /*0204*/ 0x00000014, - /*0205*/ 0x00000014, - /*0206*/ 0x00000014, - /*0207*/ 0x00000000, - /*0208*/ 0x00000000, - /*0209*/ 0x0000ffff, - /*020a*/ 0x00000000, - /*020b*/ 0x0000ffff, - /*020c*/ 0x00000000, - /*020d*/ 0x0000ffff, - /*020e*/ 0x0000304c, - /*020f*/ 0x00000200, - /*0210*/ 0x00000200, - /*0211*/ 0x00000200, - /*0212*/ 0x00000200, - /*0213*/ 0x0000304c, - /*0214*/ 0x00000200, - /*0215*/ 0x00000200, - /*0216*/ 0x00000200, - /*0217*/ 0x00000200, - /*0218*/ 0x0000304c, - /*0219*/ 0x00000200, - /*021a*/ 0x00000200, - /*021b*/ 0x00000200, - /*021c*/ 0x00000200, - /*021d*/ 0x00010000, - /*021e*/ 0x00000003, - /*021f*/ 0x01000001, - /*0220*/ 0x00000000, - /*0221*/ 0x00000000, - /*0222*/ 0x00000000, - /*0223*/ 0x00000000, - /*0224*/ 0x00000000, - /*0225*/ 0x00000000, - /*0226*/ 0x00000000, - /*0227*/ 0x00000000, - /*0228*/ 0x00000000, - /*0229*/ 0x00000000, - /*022a*/ 0x00000000, - /*022b*/ 0x00000000, - /*022c*/ 0x00000000, - /*022d*/ 0x00000000, - /*022e*/ 0x00000000, - /*022f*/ 0x00000000, - /*0230*/ 0x0f000101, - /*0231*/ 0x084d3129, - /*0232*/ 0x0e0c0004, - /*0233*/ 0x000e5000, - /*0234*/ 0x01000250, - /*0235*/ 0x00000003, - /*0236*/ 0x00000046, - /*0237*/ 0x000000cf, - /*0238*/ 0x00001826, - /*0239*/ 0x000000cf, - /*023a*/ 0x00001826, - /*023b*/ 0x00000000, - /*023c*/ 0x00000000, - /*023d*/ 0x00000000, - /*023e*/ 0x00000000, - /*023f*/ 0x00000000, - /*0240*/ 0x00000000, - /*0241*/ 0x00000000, - /*0242*/ 0x00000000, - /*0243*/ 0x00000000, - /*0244*/ 0x00000000, - /*0245*/ 0x01000000, - /*0246*/ 0x00040404, - /*0247*/ 0x01280a00, - /*0248*/ 0x00000001, - /*0249*/ 0x00000000, - /*024a*/ 0x03000f00, - /*024b*/ 0x00200020, - /*024c*/ 0x00000020, - /*024d*/ 0x00000000, - /*024e*/ 0x00000000, - /*024f*/ 0x00010002, - /*0250*/ 0x01010001, - /*0251*/ 0x02010100, - /*0252*/ 0x08040402, - /*0253*/ 0x00000008, - /*0254*/ 0x00000000, - /*0255*/ 0x04080803, - /*0256*/ 0x00001515, - /*0257*/ 0x00000000, - /*0258*/ 0x000000aa, - /*0259*/ 0x00000055, - /*025a*/ 0x000000b5, - /*025b*/ 0x0000004a, - /*025c*/ 0x00000056, - /*025d*/ 0x000000a9, - /*025e*/ 0x000000a9, - /*025f*/ 0x000000b5, - /*0260*/ 0x00000000, - /*0261*/ 0x00000000, - /*0262*/ 0x0f000000, - /*0263*/ 0x00001e0f, - /*0264*/ 0x000007d0, - /*0265*/ 0x01000300, - /*0266*/ 0x00000100, - /*0267*/ 0x00000000, - /*0268*/ 0x00000000, - /*0269*/ 0x01000000, - /*026a*/ 0x00010101, - /*026b*/ 0x000e0e0e, - /*026c*/ 0x000c0c0c, - /*026d*/ 0x01060601, - /*026e*/ 0x04041717, - /*026f*/ 0x00000004, - /*0270*/ 0x00000300, - /*0271*/ 0x17030000, - /*0272*/ 0x00060018, - /*0273*/ 0x00160028, - /*0274*/ 0x00160028, - /*0275*/ 0x00000000, - /*0276*/ 0x00000000, - /*0277*/ 0x00000000, - /*0278*/ 0x0a000000, - /*0279*/ 0x00010a14, - /*027a*/ 0x00030005, - /*027b*/ 0x0003018d, - /*027c*/ 0x000a018d, - /*027d*/ 0x00060100, - /*027e*/ 0x01000006, - /*027f*/ 0x018e018e, - /*0280*/ 0x018e0100, - /*0281*/ 0x1e1a018e, - /*0282*/ 0x1e1a1e1a, - /*0283*/ 0x01010204, - /*0284*/ 0x06501001, - /*0285*/ 0x090d0a07, - /*0286*/ 0x090d0a07, - /*0287*/ 0x0811180f, - /*0288*/ 0x00ff1102, - /*0289*/ 0x00ff1000, - /*028a*/ 0x00ff1000, - /*028b*/ 0x04041000, - /*028c*/ 0x18020100, - /*028d*/ 0x01010018, - /*028e*/ 0x005f005f, - /*028f*/ 0x005f005f, - /*0290*/ 0x050f0000, - /*0291*/ 0x051e051e, - /*0292*/ 0x0c01021e, - /*0293*/ 0x00000c0c, - /*0294*/ 0x00003400, - /*0295*/ 0x00000000, - /*0296*/ 0x00000000, - /*0297*/ 0x00000000, - /*0298*/ 0x00000000, - /*0299*/ 0x002e00d4, - /*029a*/ 0x11360031, - /*029b*/ 0x00d41611, - /*029c*/ 0x0031002e, - /*029d*/ 0x16111136, - /*029e*/ 0x002e00d4, - /*029f*/ 0x11360031, - /*02a0*/ 0x00001611, - /*02a1*/ 0x002e00d4, - /*02a2*/ 0x11360031, - /*02a3*/ 0x00d41611, - /*02a4*/ 0x0031002e, - /*02a5*/ 0x16111136, - /*02a6*/ 0x002e00d4, - /*02a7*/ 0x11360031, - /*02a8*/ 0x00001611, - /*02a9*/ 0x002e00d4, - /*02aa*/ 0x11360031, - /*02ab*/ 0x00d41611, - /*02ac*/ 0x0031002e, - /*02ad*/ 0x16111136, - /*02ae*/ 0x002e00d4, - /*02af*/ 0x11360031, - /*02b0*/ 0x00001611, - /*02b1*/ 0x002e00d4, - /*02b2*/ 0x11360031, - /*02b3*/ 0x00d41611, - /*02b4*/ 0x0031002e, - /*02b5*/ 0x16111136, - /*02b6*/ 0x002e00d4, - /*02b7*/ 0x11360031, - /*02b8*/ 0x00001611, - /*02b9*/ 0x00018d00, - /*02ba*/ 0x018d018d, - /*02bb*/ 0x1d220c08, - /*02bc*/ 0x00001f12, - /*02bd*/ 0x4301b344, - /*02be*/ 0x17032006, - /*02bf*/ 0x220c1010, - /*02c0*/ 0x001f121d, - /*02c1*/ 0x4301b344, - /*02c2*/ 0x17062006, - /*02c3*/ 0x220c1010, - /*02c4*/ 0x001f121d, - /*02c5*/ 0x4301b344, - /*02c6*/ 0x17182006, - /*02c7*/ 0x00021010, - /*02c8*/ 0x00020002, - /*02c9*/ 0x00020002, - /*02ca*/ 0x00020002, - /*02cb*/ 0x00020002, - /*02cc*/ 0x00000002, - /*02cd*/ 0x00000000, - /*02ce*/ 0x00000000, - /*02cf*/ 0x00000000, - /*02d0*/ 0x00000000, - /*02d1*/ 0x00000000, - /*02d2*/ 0x00000000, - /*02d3*/ 0x00000000, - /*02d4*/ 0x00000000, - /*02d5*/ 0x00000000, - /*02d6*/ 0x00000000, - /*02d7*/ 0x00000000, - /*02d8*/ 0x00000000, - /*02d9*/ 0x00000400, - /*02da*/ 0x15141312, - /*02db*/ 0x11100f0e, - /*02dc*/ 0x080b0c0d, - /*02dd*/ 0x05040a09, - /*02de*/ 0x01000706, - /*02df*/ 0x00000302, - /*02e0*/ 0x01030201, - /*02e1*/ 0x00304c08, - /*02e2*/ 0x0001e2f8, - /*02e3*/ 0x0000304c, - /*02e4*/ 0x0001e2f8, - /*02e5*/ 0x0000304c, - /*02e6*/ 0x0001e2f8, - /*02e7*/ 0x08000000, - /*02e8*/ 0x00000100, - /*02e9*/ 0x00000000, - /*02ea*/ 0x00000000, - /*02eb*/ 0x00000000, - /*02ec*/ 0x00000000, - /*02ed*/ 0x00010000, - /*02ee*/ 0x00000000, - /*02ef*/ 0x00000000, - /*02f0*/ 0x00000000, - /*02f1*/ 0x00000000, - /*02f2*/ 0x00000000, - /*02f3*/ 0x00000000, - /*02f4*/ 0x00000000, - /*02f5*/ 0x00000000, - /*02f6*/ 0x00000000, - /*02f7*/ 0x00000000, - /*02f8*/ 0x00000000, - /*02f9*/ 0x00000000, - /*02fa*/ 0x00000000, - /*02fb*/ 0x00000000, - /*02fc*/ 0x00000000, - /*02fd*/ 0x00000000, - /*02fe*/ 0x00000000, - /*02ff*/ 0x00000000, - /*0300*/ 0x00000000, - /*0301*/ 0x00000000, - /*0302*/ 0x00000000, - /*0303*/ 0x00000000, - /*0304*/ 0x00000000, - /*0305*/ 0x00000000, - /*0306*/ 0x00000000, - /*0307*/ 0x00000000, - /*0308*/ 0x00000000, - /*0309*/ 0x00000000, - /*030a*/ 0x00000000, - /*030b*/ 0x00000000, - /*030c*/ 0x00000000, - /*030d*/ 0x00000000, - /*030e*/ 0x00000000, - /*030f*/ 0x00050002, - /*0310*/ 0x015c0057, - /*0311*/ 0x01000100, - /*0312*/ 0x01020001, - /*0313*/ 0x00010300, - /*0314*/ 0x05000104, - /*0315*/ 0x01060001, - /*0316*/ 0x00010700, - /*0317*/ 0x00000000, - /*0318*/ 0x00000000, - /*0319*/ 0x00000001, - /*031a*/ 0x00000000, - /*031b*/ 0x00000000, - /*031c*/ 0x00000000, - /*031d*/ 0x20080101 -}; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_regs.h b/drivers/staging/renesas/rcar/ddr/ddr_regs.h deleted file mode 100644 index ba26c69c8..000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_regs.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef BOOT_INIT_DRAM_REGDEF_H_ -#define BOOT_INIT_DRAM_REGDEF_H_ - -/* DBSC registers */ -#define DBSC_DBSYSCONF0 0xE6790000U -#define DBSC_DBSYSCONF1 0xE6790004U -#define DBSC_DBPHYCONF0 0xE6790010U -#define DBSC_DBKIND 0xE6790020U -#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) -#define DBSC_DBMEMCONF_0_0 0xE6790030U -#define DBSC_DBMEMCONF_0_1 0xE6790034U -#define DBSC_DBMEMCONF_0_2 0xE6790038U -#define DBSC_DBMEMCONF_0_3 0xE679003CU -#define DBSC_DBMEMCONF_1_2 0xE6790048U -#define DBSC_DBMEMCONF_1_3 0xE679004CU -#define DBSC_DBMEMCONF_1_0 0xE6790040U -#define DBSC_DBMEMCONF_1_1 0xE6790044U -#define DBSC_DBMEMCONF_2_0 0xE6790050U -#define DBSC_DBMEMCONF_2_1 0xE6790054U -#define DBSC_DBMEMCONF_2_2 0xE6790058U -#define DBSC_DBMEMCONF_2_3 0xE679005CU -#define DBSC_DBMEMCONF_3_0 0xE6790060U -#define DBSC_DBMEMCONF_3_1 0xE6790064U -#define DBSC_DBMEMCONF_3_2 0xE6790068U -#define DBSC_DBMEMCONF_3_3 0xE679006CU -#define DBSC_DBSYSCNT0 0xE6790100U -#define DBSC_DBSVCR1 0xE6790104U -#define DBSC_DBSTATE0 0xE6790108U -#define DBSC_DBSTATE1 0xE679010CU -#define DBSC_DBINTEN 0xE6790180U -#define DBSC_DBINTSTAT0 0xE6790184U -#define DBSC_DBACEN 0xE6790200U -#define DBSC_DBRFEN 0xE6790204U -#define DBSC_DBCMD 0xE6790208U -#define DBSC_DBWAIT 0xE6790210U -#define DBSC_DBSYSCTRL0 0xE6790280U -#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x)) -#define DBSC_DBTR0 0xE6790300U -#define DBSC_DBTR1 0xE6790304U -#define DBSC_DBTR2 0xE6790308U -#define DBSC_DBTR3 0xE679030CU -#define DBSC_DBTR4 0xE6790310U -#define DBSC_DBTR5 0xE6790314U -#define DBSC_DBTR6 0xE6790318U -#define DBSC_DBTR7 0xE679031CU -#define DBSC_DBTR8 0xE6790320U -#define DBSC_DBTR9 0xE6790324U -#define DBSC_DBTR10 0xE6790328U -#define DBSC_DBTR11 0xE679032CU -#define DBSC_DBTR12 0xE6790330U -#define DBSC_DBTR13 0xE6790334U -#define DBSC_DBTR14 0xE6790338U -#define DBSC_DBTR15 0xE679033CU -#define DBSC_DBTR16 0xE6790340U -#define DBSC_DBTR17 0xE6790344U -#define DBSC_DBTR18 0xE6790348U -#define DBSC_DBTR19 0xE679034CU -#define DBSC_DBTR20 0xE6790350U -#define DBSC_DBTR21 0xE6790354U -#define DBSC_DBTR22 0xE6790358U -#define DBSC_DBTR23 0xE679035CU -#define DBSC_DBTR24 0xE6790360U -#define DBSC_DBTR25 0xE6790364U -#define DBSC_DBTR26 0xE6790368U -#define DBSC_DBBL 0xE6790400U -#define DBSC_DBRFCNF1 0xE6790414U -#define DBSC_DBRFCNF2 0xE6790418U -#define DBSC_DBTSPCNF 0xE6790420U -#define DBSC_DBCALCNF 0xE6790424U -#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x)) -#define DBSC_DBRNK2 0xE6790438U -#define DBSC_DBRNK3 0xE679043CU -#define DBSC_DBRNK4 0xE6790440U -#define DBSC_DBRNK5 0xE6790444U -#define DBSC_DBPDNCNF 0xE6790450U -#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x)) -#define DBSC_DBODT0 0xE6790460U -#define DBSC_DBODT1 0xE6790464U -#define DBSC_DBODT2 0xE6790468U -#define DBSC_DBODT3 0xE679046CU -#define DBSC_DBODT4 0xE6790470U -#define DBSC_DBODT5 0xE6790474U -#define DBSC_DBODT6 0xE6790478U -#define DBSC_DBODT7 0xE679047CU -#define DBSC_DBADJ0 0xE6790500U -#define DBSC_DBDBICNT 0xE6790518U -#define DBSC_DBDFIPMSTRCNF 0xE6790520U -#define DBSC_DBDFICUPDCNF 0xE679052CU -#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch)) -#define DBSC_DBDFISTAT_0 0xE6790600U -#define DBSC_DBDFISTAT_1 0xE6790640U -#define DBSC_DBDFISTAT_2 0xE6790680U -#define DBSC_DBDFISTAT_3 0xE67906C0U -#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch)) -#define DBSC_DBDFICNT_0 0xE6790604U -#define DBSC_DBDFICNT_1 0xE6790644U -#define DBSC_DBDFICNT_2 0xE6790684U -#define DBSC_DBDFICNT_3 0xE67906C4U -#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch)) -#define DBSC_DBPDCNT0_0 0xE6790610U -#define DBSC_DBPDCNT0_1 0xE6790650U -#define DBSC_DBPDCNT0_2 0xE6790690U -#define DBSC_DBPDCNT0_3 0xE67906D0U -#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch)) -#define DBSC_DBPDCNT1_0 0xE6790614U -#define DBSC_DBPDCNT1_1 0xE6790654U -#define DBSC_DBPDCNT1_2 0xE6790694U -#define DBSC_DBPDCNT1_3 0xE67906D4U -#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch)) -#define DBSC_DBPDCNT2_0 0xE6790618U -#define DBSC_DBPDCNT2_1 0xE6790658U -#define DBSC_DBPDCNT2_2 0xE6790698U -#define DBSC_DBPDCNT2_3 0xE67906D8U -#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch)) -#define DBSC_DBPDCNT3_0 0xE679061CU -#define DBSC_DBPDCNT3_1 0xE679065CU -#define DBSC_DBPDCNT3_2 0xE679069CU -#define DBSC_DBPDCNT3_3 0xE67906DCU -#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch)) -#define DBSC_DBPDLK_0 0xE6790620U -#define DBSC_DBPDLK_1 0xE6790660U -#define DBSC_DBPDLK_2 0xE67906a0U -#define DBSC_DBPDLK_3 0xE67906e0U -#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch)) -#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch)) -#define DBSC_DBPDRGA_0 0xE6790624U -#define DBSC_DBPDRGD_0 0xE6790628U -#define DBSC_DBPDRGA_1 0xE6790664U -#define DBSC_DBPDRGD_1 0xE6790668U -#define DBSC_DBPDRGA_2 0xE67906A4U -#define DBSC_DBPDRGD_2 0xE67906A8U -#define DBSC_DBPDRGA_3 0xE67906E4U -#define DBSC_DBPDRGD_3 0xE67906E8U -#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch)) -#define DBSC_DBPDSTAT_0 0xE6790630U -#define DBSC_DBPDSTAT_1 0xE6790670U -#define DBSC_DBPDSTAT_2 0xE67906B0U -#define DBSC_DBPDSTAT_3 0xE67906F0U -#define DBSC_DBBUS0CNF0 0xE6790800U -#define DBSC_DBBUS0CNF1 0xE6790804U -#define DBSC_DBCAM0CNF1 0xE6790904U -#define DBSC_DBCAM0CNF2 0xE6790908U -#define DBSC_DBCAM0CNF3 0xE679090CU -#define DBSC_DBBSWAP 0xE67909F0U -#define DBSC_DBBCAMDIS 0xE67909FCU -#define DBSC_DBSCHCNT0 0xE6791000U -#define DBSC_DBSCHCNT1 0xE6791004U -#define DBSC_DBSCHSZ0 0xE6791010U -#define DBSC_DBSCHRW0 0xE6791020U -#define DBSC_DBSCHRW1 0xE6791024U -#define DBSC_DBSCHQOS_0(x) (0xE6791030U + 0x10U * (x)) -#define DBSC_DBSCHQOS_1(x) (0xE6791034U + 0x10U * (x)) -#define DBSC_DBSCHQOS_2(x) (0xE6791038U + 0x10U * (x)) -#define DBSC_DBSCHQOS_3(x) (0xE679103CU + 0x10U * (x)) -#define DBSC_DBSCHQOS00 0xE6791030U -#define DBSC_DBSCHQOS01 0xE6791034U -#define DBSC_DBSCHQOS02 0xE6791038U -#define DBSC_DBSCHQOS03 0xE679103CU -#define DBSC_DBSCHQOS10 0xE6791040U -#define DBSC_DBSCHQOS11 0xE6791044U -#define DBSC_DBSCHQOS12 0xE6791048U -#define DBSC_DBSCHQOS13 0xE679104CU -#define DBSC_DBSCHQOS20 0xE6791050U -#define DBSC_DBSCHQOS21 0xE6791054U -#define DBSC_DBSCHQOS22 0xE6791058U -#define DBSC_DBSCHQOS23 0xE679105CU -#define DBSC_DBSCHQOS30 0xE6791060U -#define DBSC_DBSCHQOS31 0xE6791064U -#define DBSC_DBSCHQOS32 0xE6791068U -#define DBSC_DBSCHQOS33 0xE679106CU -#define DBSC_DBSCHQOS40 0xE6791070U -#define DBSC_DBSCHQOS41 0xE6791074U -#define DBSC_DBSCHQOS42 0xE6791078U -#define DBSC_DBSCHQOS43 0xE679107CU -#define DBSC_DBSCHQOS50 0xE6791080U -#define DBSC_DBSCHQOS51 0xE6791084U -#define DBSC_DBSCHQOS52 0xE6791088U -#define DBSC_DBSCHQOS53 0xE679108CU -#define DBSC_DBSCHQOS60 0xE6791090U -#define DBSC_DBSCHQOS61 0xE6791094U -#define DBSC_DBSCHQOS62 0xE6791098U -#define DBSC_DBSCHQOS63 0xE679109CU -#define DBSC_DBSCHQOS70 0xE67910A0U -#define DBSC_DBSCHQOS71 0xE67910A4U -#define DBSC_DBSCHQOS72 0xE67910A8U -#define DBSC_DBSCHQOS73 0xE67910ACU -#define DBSC_DBSCHQOS80 0xE67910B0U -#define DBSC_DBSCHQOS81 0xE67910B4U -#define DBSC_DBSCHQOS82 0xE67910B8U -#define DBSC_DBSCHQOS83 0xE67910BCU -#define DBSC_DBSCHQOS90 0xE67910C0U -#define DBSC_DBSCHQOS91 0xE67910C4U -#define DBSC_DBSCHQOS92 0xE67910C8U -#define DBSC_DBSCHQOS93 0xE67910CCU -#define DBSC_DBSCHQOS100 0xE67910D0U -#define DBSC_DBSCHQOS101 0xE67910D4U -#define DBSC_DBSCHQOS102 0xE67910D8U -#define DBSC_DBSCHQOS103 0xE67910DCU -#define DBSC_DBSCHQOS110 0xE67910E0U -#define DBSC_DBSCHQOS111 0xE67910E4U -#define DBSC_DBSCHQOS112 0xE67910E8U -#define DBSC_DBSCHQOS113 0xE67910ECU -#define DBSC_DBSCHQOS120 0xE67910F0U -#define DBSC_DBSCHQOS121 0xE67910F4U -#define DBSC_DBSCHQOS122 0xE67910F8U -#define DBSC_DBSCHQOS123 0xE67910FCU -#define DBSC_DBSCHQOS130 0xE6791100U -#define DBSC_DBSCHQOS131 0xE6791104U -#define DBSC_DBSCHQOS132 0xE6791108U -#define DBSC_DBSCHQOS133 0xE679110CU -#define DBSC_DBSCHQOS140 0xE6791110U -#define DBSC_DBSCHQOS141 0xE6791114U -#define DBSC_DBSCHQOS142 0xE6791118U -#define DBSC_DBSCHQOS143 0xE679111CU -#define DBSC_DBSCHQOS150 0xE6791120U -#define DBSC_DBSCHQOS151 0xE6791124U -#define DBSC_DBSCHQOS152 0xE6791128U -#define DBSC_DBSCHQOS153 0xE679112CU -#define DBSC_DBSCTR0 0xE6791700U -#define DBSC_DBSCTR1 0xE6791708U -#define DBSC_DBSCHRW2 0xE679170CU -#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x)) -#define DBSC_SCFCTST0 0xE6791700U -#define DBSC_SCFCTST1 0xE6791708U -#define DBSC_SCFCTST2 0xE679170CU -#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab)) -#define DBSC_DBMRRDR_0 0xE6791800U -#define DBSC_DBMRRDR_1 0xE6791804U -#define DBSC_DBMRRDR_2 0xE6791808U -#define DBSC_DBMRRDR_3 0xE679180CU -#define DBSC_DBMRRDR_4 0xE6791810U -#define DBSC_DBMRRDR_5 0xE6791814U -#define DBSC_DBMRRDR_6 0xE6791818U -#define DBSC_DBMRRDR_7 0xE679181CU -#define DBSC_DBMEMSWAPCONF0 0xE6792000U - -/* CPG registers */ -#define CPG_BASE 0xE6150000U -#define CPG_FRQCRB (CPG_BASE + 0x0004U) -#define CPG_PLLECR (CPG_BASE + 0x00D0U) -#define CPG_MSTPSR5 (CPG_BASE + 0x003CU) -#define CPG_SRCR4 (CPG_BASE + 0x00BCU) -#define CPG_PLL3CR (CPG_BASE + 0x00DCU) -#define CPG_ZB3CKCR (CPG_BASE + 0x0380U) -#define CPG_FRQCRD (CPG_BASE + 0x00E4U) -#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) -#define CPG_CPGWPR (CPG_BASE + 0x0900U) -#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U) - -#endif /* BOOT_INIT_DRAM_REGDEF_H_*/ diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c deleted file mode 100644 index ab8eabbc6..000000000 --- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include "dram_sub_func.h" -#include "rcar_def.h" - -#if RCAR_SYSTEM_SUSPEND -/* Local defines */ -#define DRAM_BACKUP_GPIO_USE 0 -#include "iic_dvfs.h" -#if PMIC_ROHM_BD9571 -#define PMIC_SLAVE_ADDR 0x30U -#define PMIC_BKUP_MODE_CNT 0x20U -#define PMIC_QLLM_CNT 0x27U -#define BIT_BKUP_CTRL_OUT BIT(4) -#define BIT_QLLM_DDR0_EN BIT(0) -#define BIT_QLLM_DDR1_EN BIT(1) -#endif - -#define GPIO_BKUP_REQB_SHIFT_SALVATOR 9U /* GP1_9 (BKUP_REQB) */ -#define GPIO_BKUP_TRG_SHIFT_SALVATOR 8U /* GP1_8 (BKUP_TRG) */ -#define GPIO_BKUP_REQB_SHIFT_EBISU 14U /* GP6_14(BKUP_REQB) */ -#define GPIO_BKUP_TRG_SHIFT_EBISU 13U /* GP6_13(BKUP_TRG) */ -#define GPIO_BKUP_REQB_SHIFT_CONDOR 1U /* GP3_1 (BKUP_REQB) */ -#define GPIO_BKUP_TRG_SHIFT_CONDOR 0U /* GP3_0 (BKUP_TRG) */ - -#define DRAM_BKUP_TRG_LOOP_CNT 1000U -#endif - -void rcar_dram_get_boot_status(uint32_t *status) -{ -#if RCAR_SYSTEM_SUSPEND - uint32_t reg_data; - uint32_t product; - uint32_t shift; - uint32_t gpio; - - product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; - if (product == PRR_PRODUCT_V3H) { - shift = GPIO_BKUP_TRG_SHIFT_CONDOR; - gpio = GPIO_INDT3; - } else if (product == PRR_PRODUCT_E3) { - shift = GPIO_BKUP_TRG_SHIFT_EBISU; - gpio = GPIO_INDT6; - } else { - shift = GPIO_BKUP_TRG_SHIFT_SALVATOR; - gpio = GPIO_INDT1; - } - - reg_data = mmio_read_32(gpio); - if (reg_data & BIT(shift)) - *status = DRAM_BOOT_STATUS_WARM; - else - *status = DRAM_BOOT_STATUS_COLD; -#else /* RCAR_SYSTEM_SUSPEND */ - *status = DRAM_BOOT_STATUS_COLD; -#endif /* RCAR_SYSTEM_SUSPEND */ -} - -int32_t rcar_dram_update_boot_status(uint32_t status) -{ - int32_t ret = 0; -#if RCAR_SYSTEM_SUSPEND - uint32_t reg_data; -#if PMIC_ROHM_BD9571 -#if DRAM_BACKUP_GPIO_USE == 0 - uint8_t bkup_mode_cnt = 0U; -#else - uint32_t reqb, outd; -#endif - uint8_t qllm_cnt = 0U; - int32_t i2c_dvfs_ret = -1; -#endif - uint32_t loop_count; - uint32_t product; - uint32_t trg; - uint32_t gpio; - - product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; - if (product == PRR_PRODUCT_V3H) { -#if DRAM_BACKUP_GPIO_USE == 1 - reqb = GPIO_BKUP_REQB_SHIFT_CONDOR; - outd = GPIO_OUTDT3; -#endif - trg = GPIO_BKUP_TRG_SHIFT_CONDOR; - gpio = GPIO_INDT3; - } else if (product == PRR_PRODUCT_E3) { -#if DRAM_BACKUP_GPIO_USE == 1 - reqb = GPIO_BKUP_REQB_SHIFT_EBISU; - outd = GPIO_OUTDT6; -#endif - trg = GPIO_BKUP_TRG_SHIFT_EBISU; - gpio = GPIO_INDT6; - } else { -#if DRAM_BACKUP_GPIO_USE == 1 - reqb = GPIO_BKUP_REQB_SHIFT_SALVATOR; - outd = GPIO_OUTDT1; -#endif - trg = GPIO_BKUP_TRG_SHIFT_SALVATOR; - gpio = GPIO_INDT1; - } - - if (status == DRAM_BOOT_STATUS_WARM) { -#if DRAM_BACKUP_GPIO_USE == 1 - mmio_setbits_32(outd, BIT(reqb)); -#else -#if PMIC_ROHM_BD9571 - /* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */ - i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR, - PMIC_BKUP_MODE_CNT, - &bkup_mode_cnt); - if (i2c_dvfs_ret) { - ERROR("BKUP mode cnt READ ERROR.\n"); - ret = DRAM_UPDATE_STATUS_ERR; - } else { - bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT; - i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR, - PMIC_BKUP_MODE_CNT, - bkup_mode_cnt); - if (i2c_dvfs_ret) { - ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", - bkup_mode_cnt); - ret = DRAM_UPDATE_STATUS_ERR; - } - } -#endif /* PMIC_ROHM_BD9571 */ -#endif /* DRAM_BACKUP_GPIO_USE == 1 */ - /* Wait BKUP_TRG=Low */ - loop_count = DRAM_BKUP_TRG_LOOP_CNT; - while (loop_count > 0) { - reg_data = mmio_read_32(gpio); - if (!(reg_data & BIT(trg))) - break; - loop_count--; - } - - if (!loop_count) { - ERROR("\nWarm booting...\n" - " The potential of BKUP_TRG did not switch to Low.\n" - " If you expect the operation of cold boot,\n" - " check the board configuration (ex, Dip-SW) and/or the H/W failure.\n"); - ret = DRAM_UPDATE_STATUS_ERR; - } - } -#if PMIC_ROHM_BD9571 - if (!ret) { - qllm_cnt = BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN; - i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR, - PMIC_QLLM_CNT, - qllm_cnt); - if (i2c_dvfs_ret) { - ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm_cnt); - ret = DRAM_UPDATE_STATUS_ERR; - } - } -#endif -#endif - return ret; -} diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h b/drivers/staging/renesas/rcar/ddr/dram_sub_func.h deleted file mode 100644 index 69c4d8605..000000000 --- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef DRAM_SUB_FUNC_H -#define DRAM_SUB_FUNC_H - -#define DRAM_UPDATE_STATUS_ERR -1 -#define DRAM_BOOT_STATUS_COLD 0 -#define DRAM_BOOT_STATUS_WARM 1 - -int32_t rcar_dram_update_boot_status(uint32_t status); -void rcar_dram_get_boot_status(uint32_t *status); - -#endif /* DRAM_SUB_FUNC_H */ diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk index dc58e191d..4c41dd341 100644 --- a/plat/renesas/rcar/platform.mk +++ b/plat/renesas/rcar/platform.mk @@ -348,12 +348,12 @@ ERRATA_A53_855873 := 1 ERRATA_A57_859972 := 1 ERRATA_A57_813419 := 1 -include drivers/staging/renesas/rcar/ddr/ddr.mk +include drivers/renesas/rcar/ddr/ddr.mk include drivers/renesas/rcar/qos/qos.mk include drivers/renesas/rcar/pfc/pfc.mk include lib/libfdt/libfdt.mk -PLAT_INCLUDES := -Idrivers/staging/renesas/rcar/ddr \ +PLAT_INCLUDES := -Idrivers/renesas/rcar/ddr \ -Idrivers/renesas/rcar/qos \ -Idrivers/renesas/rcar/iic_dvfs \ -Idrivers/renesas/rcar/board \ -- cgit v1.2.3 From cc6bc641757cb3d53ebff58fd984ea4c6ad840cf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 1 Dec 2019 22:56:43 +0100 Subject: rcar_gen3: plat: Pass DT to OpTee OS Pass DT to OpTee OS, so that OpTee OS can extract NSEC RAM layout from the DT. Signed-off-by: Marek Vasut Change-Id: I7d5ebae8d7ab9c70f079e30563d66bbd6a8ac7a4 --- plat/renesas/rcar/bl2_plat_mem_params_desc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/plat/renesas/rcar/bl2_plat_mem_params_desc.c b/plat/renesas/rcar/bl2_plat_mem_params_desc.c index 3b124c789..bf2706d53 100644 --- a/plat/renesas/rcar/bl2_plat_mem_params_desc.c +++ b/plat/renesas/rcar/bl2_plat_mem_params_desc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -53,6 +53,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { entry_point_info_t, SECURE | EXECUTABLE), .ep_info.pc = BL32_BASE, .ep_info.spsr = 0, + .ep_info.args.arg3 = (uintptr_t)fdt_blob, SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), -- cgit v1.2.3 From 786890caaeb3e3d01a3a5986a4e4af104c510e62 Mon Sep 17 00:00:00 2001 From: Avinash Mehta Date: Wed, 18 Dec 2019 10:13:40 +0000 Subject: A5DS: Correct system freq, Cache Writeback Granule Correct the system, timer and uart frequencies to successfully run the stack on FPGA Correct Cortex-A5MPcore to 8 word granularity for Cache writeback Change-Id: I2c59c26b7dca440791ad39f2297c68ae513da7b6 Signed-off-by: Avinash Mehta --- fdts/a5ds.dts | 19 +++++++++++++------ plat/arm/board/a5ds/include/platform_def.h | 12 ++++++------ 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts index fc8783dd8..31d635ac8 100644 --- a/fdts/a5ds.dts +++ b/fdts/a5ds.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,10 +64,17 @@ arm,tag-latency = <1 1 1>; }; - refclk100mhz: refclk100mhz { + refclk7500khz: refclk7500khz { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <100000000>; + clock-frequency = <7500000>; + clock-output-names = "apb_pclk"; + }; + + refclk24mhz: refclk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; clock-output-names = "apb_pclk"; }; @@ -82,7 +89,7 @@ rtc@1a220000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x1a220000 0x1000>; - clocks = <&refclk100mhz>; + clocks = <&refclk24mhz>; interrupts = <0 6 0xf04>; clock-names = "apb_pclk"; }; @@ -102,7 +109,7 @@ reg = <0x1a200000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 8 0xf04>; - clocks = <&refclk100mhz>; + clocks = <&refclk7500khz>; clock-names = "apb_pclk"; }; @@ -111,7 +118,7 @@ reg = <0x1a210000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 9 0xf04>; - clocks = <&refclk100mhz>; + clocks = <&refclk7500khz>; clock-names = "apb_pclk"; }; diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h index e9e4b9aef..649cb8b1e 100644 --- a/plat/arm/board/a5ds/include/platform_def.h +++ b/plat/arm/board/a5ds/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -47,7 +47,7 @@ #define A5_PERIPHERALS_BASE 0x1c000000 #define A5_PERIPHERALS_SIZE 0x10000 -#define ARM_CACHE_WRITEBACK_SHIFT 6 +#define ARM_CACHE_WRITEBACK_SHIFT 5 #define ARM_IRQ_SEC_PHY_TIMER 29 @@ -162,7 +162,7 @@ ARM_BL_REGIONS) /* Memory mapped Generic timer interfaces */ -#define A5DS_TIMER_BASE_FREQUENCY UL(24000000) +#define A5DS_TIMER_BASE_FREQUENCY UL(7500000) #define ARM_CONSOLE_BAUDRATE 115200 @@ -310,15 +310,15 @@ * PL011 related constants */ #define PLAT_ARM_BOOT_UART_BASE 0x1A200000 -#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 24000000 +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ UL(7500000) #define PLAT_ARM_RUN_UART_BASE 0x1A210000 -#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ UL(7500000) #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ -#define A5DS_TIMER_BASE_FREQUENCY UL(24000000) +#define A5DS_TIMER_BASE_FREQUENCY UL(7500000) /* System timer related constants */ #define PLAT_ARM_NSTIMER_FRAME_ID 1 -- cgit v1.2.3 From e343bf13841ec7573648bfee60a604d6c29a36ac Mon Sep 17 00:00:00 2001 From: Avinash Mehta Date: Wed, 18 Dec 2019 10:18:46 +0000 Subject: A5DS: Change boot address to point to DDR address Point boot address to DDR location for booting A5DS FPGA FIP, Kernel and rootfs are sideloaded to DDR Also move BL2 to higher address in DDR Change-Id: Ia2a57a0bda776a1a0a96bcd3cfb5c6cd2cf4dc04 Signed-off-by: Avinash Mehta --- plat/arm/board/a5ds/a5ds_common.c | 6 ++-- plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts | 4 +-- plat/arm/board/a5ds/include/platform_def.h | 44 ++++++++++++-------------- 3 files changed, 26 insertions(+), 28 deletions(-) diff --git a/plat/arm/board/a5ds/a5ds_common.c b/plat/arm/board/a5ds/a5ds_common.c index e462fa16e..a4a0cff92 100644 --- a/plat/arm/board/a5ds/a5ds_common.c +++ b/plat/arm/board/a5ds/a5ds_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,18 +23,18 @@ #ifdef IMAGE_BL1 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, - MAP_FLASH1_RW, MAP_PERIPHBASE, MAP_A5_PERIPHERALS, + MAP_BOOT_RW, {0} }; #endif #ifdef IMAGE_BL2 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, - MAP_FLASH1_RW, MAP_PERIPHBASE, MAP_A5_PERIPHERALS, + MAP_BOOT_RW, ARM_MAP_NS_DRAM1, {0} }; diff --git a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts index 9ab2d9656..7b3aa1144 100644 --- a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts +++ b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,7 @@ /* Platform Config */ plat_arm_bl2 { compatible = "arm,tb_fw"; - hw_config_addr = <0x0 0x82000000>; + hw_config_addr = <0x0 0x83000000>; hw_config_max_size = <0x01000000>; /* Disable authentication for development */ disable_auth = <0x0>; diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h index 649cb8b1e..322645fc2 100644 --- a/plat/arm/board/a5ds/include/platform_def.h +++ b/plat/arm/board/a5ds/include/platform_def.h @@ -21,14 +21,6 @@ #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ ARM_DRAM1_SIZE - 1) -#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE -/* - * The last 2MB is meant to be NOLOAD and will not be zero - * initialized. - */ -#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ - 0x00200000) - #define SRAM_BASE 0x2000000 #define SRAM_SIZE 0x200000 @@ -101,16 +93,22 @@ #define A5DS_PRIMARY_CPU 0x0 -#define FLASH1_BASE UL(0x8000000) -#define FLASH1_SIZE UL(0x2800000) +#define BOOT_BASE ARM_DRAM1_BASE +#define BOOT_SIZE UL(0x2800000) -#define MAP_FLASH1_RW MAP_REGION_FLAT(FLASH1_BASE,\ - FLASH1_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) +#define ARM_NS_DRAM1_BASE (ARM_DRAM1_BASE + BOOT_SIZE) +/* + * The last 2MB is meant to be NOLOAD and will not be zero + * initialized. + */ +#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ + BOOT_SIZE - \ + 0x00200000) -#define MAP_FLASH1_RO MAP_REGION_FLAT(FLASH1_BASE,\ - FLASH1_SIZE, \ - MT_RO_DATA | MT_SECURE) +#define MAP_BOOT_RW MAP_REGION_FLAT( \ + BOOT_BASE, \ + BOOT_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ A5DS_SHARED_RAM_BASE, \ @@ -122,9 +120,9 @@ ARM_NS_DRAM1_SIZE, \ MT_MEMORY | MT_RW | MT_NS) -#define ARM_MAP_SRAM MAP_REGION_FLAT( \ - SRAM_BASE, \ - SRAM_SIZE, \ +#define ARM_MAP_SRAM MAP_REGION_FLAT( \ + SRAM_BASE, \ + SRAM_SIZE, \ MT_MEMORY | MT_RW | MT_NS) /* @@ -300,11 +298,11 @@ #define MAX_IO_HANDLES 4 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ -#define PLAT_ARM_FIP_BASE FLASH1_BASE -#define PLAT_ARM_FIP_MAX_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE) +#define PLAT_ARM_FIP_BASE BOOT_BASE +#define PLAT_ARM_FIP_MAX_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE) -#define PLAT_ARM_NVM_BASE FLASH1_BASE -#define PLAT_ARM_NVM_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE) +#define PLAT_ARM_NVM_BASE BOOT_BASE +#define PLAT_ARM_NVM_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE) /* * PL011 related constants -- cgit v1.2.3 From a6ffd375c78672bb22020347700dec15caff52bd Mon Sep 17 00:00:00 2001 From: Ambroise Vincent Date: Wed, 17 Jul 2019 11:17:28 +0100 Subject: FVP: Stop reclaiming init code with Clang builds The reclaim init code functionality relies on forward reference in the linker script. The LLVM linker does not process it correctly. Change-Id: I993aeb9587bfa07af25b60ed823a6a2c5e970c94 Signed-off-by: Ambroise Vincent Signed-off-by: Zelalem Aweke --- plat/arm/board/fvp/platform.mk | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index ea72e7984..97a326c09 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -245,10 +245,12 @@ ENABLE_AMU := 1 DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 # Enable reclaiming of BL31 initialisation code for secondary cores -# stacks for FVP. +# stacks for FVP. However, don't enable reclaiming for clang. ifneq (${RESET_TO_BL31},1) +ifeq ($(findstring clang,$(notdir $(CC))),) RECLAIM_INIT_CODE := 1 endif +endif ifeq (${ENABLE_AMU},1) BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ -- cgit v1.2.3 From 345a85aef4d74930ef138e7e9072c56e8a60dcc2 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Sat, 23 Mar 2019 15:26:31 +0530 Subject: arm64: zynqmp: Add id for new RFSoC device ZU39DR This patch adds new RFSoC device ZU39DR to zynqmp devices list Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Jolly Shah Change-Id: I35735da9e7d7facbde44323c49eac1b714e4909d --- plat/xilinx/zynqmp/aarch64/zynqmp_common.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c index ab5d95d1e..ded37bc99 100644 --- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c +++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -189,6 +189,10 @@ static const struct { .id = 0x65, .name = "25DR", }, + { + .id = 0x66, + .name = "39DR", + }, }; #define ZYNQMP_PL_STATUS_BIT 9 -- cgit v1.2.3 From c613a6602e1b51ee778bcdd8cc82ee781e899c8e Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Tue, 30 Jul 2019 11:12:55 +0530 Subject: arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR Add support for zu48dr and zu49dr to the list of zynqmp devices. The zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b and 0x7e. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Jolly Shah Change-Id: I2978f16bb663853951ef8059bf0327f909447f34 --- plat/xilinx/zynqmp/aarch64/zynqmp_common.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c index ded37bc99..902d70c9d 100644 --- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c +++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -193,6 +193,14 @@ static const struct { .id = 0x66, .name = "39DR", }, + { + .id = 0x7b, + .name = "48DR", + }, + { + .id = 0x7e, + .name = "49DR", + }, }; #define ZYNQMP_PL_STATUS_BIT 9 -- cgit v1.2.3 From 65501a7ca4683f02fa0a43594d2304bcb767ded9 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 17 Apr 2019 15:21:28 +0200 Subject: plat: xilinx: zynqmp: Correct syscnt freq for QEMU Correct the syscnt frequency for ZynqMP QEMU to 65Mhz. Signed-off-by: Edgar E. Iglesias Signed-off-by: Jolly Shah Change-Id: Ie0137feb9b7e24ed4e5d6cbf81c58ac77bb69214 --- plat/xilinx/zynqmp/aarch64/zynqmp_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c index 902d70c9d..d6313a68f 100644 --- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c +++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -350,7 +350,7 @@ unsigned int plat_get_syscnt_freq2(void) unsigned int ver = zynqmp_get_silicon_ver(); if (ver == ZYNQMP_CSU_VERSION_QEMU) - return 50000000; + return 65000000; else return mmio_read_32(IOU_SCNTRS_BASEFREQ); } -- cgit v1.2.3 From fa8ae3c8d705a0cfcecba946eeb94efb2a200d29 Mon Sep 17 00:00:00 2001 From: Mounika Grace Akula Date: Wed, 9 Jan 2019 17:38:12 +0530 Subject: zynqmp: pm: Rename FPD WDT clock ID This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT. Signed-off-by: Mounika Grace Akula Signed-off-by: Jolly Shah Change-Id: I4d00a59b1dc54920115a2da55e8a06347fe2231c --- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 6 +++--- plat/xilinx/zynqmp/pm_service/pm_api_clock.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index 85cffcb13..375c0b6c7 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -2035,8 +2035,8 @@ static struct pm_clock clocks[] = { .nodes = &acpu_half_nodes, .num_nodes = ARRAY_SIZE(acpu_half_nodes), }, - [CLK_WDT] = { - .name = "wdt", + [CLK_FPD_WDT] = { + .name = "fpd_wdt", .control_reg = FPD_SLCR_WDT_CLK_SEL, .status_reg = 0, .parents = &((int32_t []) { diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h index 9717ca86a..c758efdfc 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -132,7 +132,7 @@ enum clock_id { CLK_PL1_REF, CLK_PL2_REF, CLK_PL3_REF, - CLK_WDT, + CLK_FPD_WDT, CLK_IOPLL_INT, CLK_IOPLL_PRE_SRC, CLK_IOPLL_HALF, -- cgit v1.2.3 From 06ad98030550d4bdc94d8ffdf7164288877ca1fb Mon Sep 17 00:00:00 2001 From: Mirela Simonovic Date: Mon, 17 Sep 2018 14:25:16 +0200 Subject: zynqmp: pm: Fix clock models and IDs of GEM-related clocks GEM-related clock models were incorrect and are fixed as follows (documented below for GEM0, but the same holds for any GEM ID): - CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this clock is newly introduced in this patch. - CLK_GEM0_REF models the clock mux that selects the reference clock for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL. Note that the routing of external clock to the mux is not modelled and is assumed to be configured by the FSBL if required, and not changeable at runtime. The ID of this clock is introduced in this patch. - CLK_GEM0_TX models clock with only a gate that is controlled via bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID value of CLK_GEM0_REF. This is done in order to fix the clock models and incorrect binding without requiring to change device-tree (binding of clock IDs to GEM interface). - CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced from external RGMII PHY (via MIO or EMIO). We do not model the whole clock path to the Rx gate, since this is configured by the FSBL and never changed at runtime (and there is no mechanism to change the path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX were swapped in device tree, so by fixing the IDs this way there is no need for device tree fix. Rates of the external RX/TX clocks can be specified in device tree if needed. Right now, that's not necessary because Tx clock is sourced from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas the Rx clock is sourced from external reference and the driver never attempts to get/get clock rate (only to enable it). If this changes in future, ATF clock model doesn't need to be changed. Instead, the clock rates for gem0_tx_ext and gem0_rx_ext have to be specified in device tree. Signed-off-by: Mirela Simonovic Acked-by: Will Wong Signed-off-by: Jolly Shah Change-Id: I6497d4309e92205c527bd81b3aa932f4474f5b79 --- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 291 +++++++++++++++++---------- plat/xilinx/zynqmp/pm_service/pm_api_clock.h | 28 ++- 2 files changed, 203 insertions(+), 116 deletions(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index 375c0b6c7..347f5892f 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -562,13 +562,13 @@ static struct pm_clock_node gpu_pp1_nodes[] = { }, }; -static struct pm_clock_node gem_nodes[] = { +static struct pm_clock_node gem_ref_ungated_nodes[] = { GENERIC_MUX, { .type = TYPE_DIV1, .offset = 8, .width = 6, - .clkflags = CLK_IS_BASIC, + .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC, .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, .mult = NA_MULT, .div = NA_DIV, @@ -577,77 +577,73 @@ static struct pm_clock_node gem_nodes[] = { .type = TYPE_DIV2, .offset = 16, .width = 6, - .clkflags = CLK_IS_BASIC, + .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC, .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, .mult = NA_MULT, .div = NA_DIV, }, - { - .type = TYPE_GATE, - .offset = 25, - .width = PERIPH_GATE_WIDTH, - .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC, - .typeflags = NA_TYPE_FLAGS, - .mult = NA_MULT, - .div = NA_DIV, - }, }; -static struct pm_clock_node gem0_tx_nodes[] = { +static struct pm_clock_node gem0_ref_nodes[] = { { .type = TYPE_MUX, .offset = 1, .width = 1, - .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC, - .typeflags = NA_TYPE_FLAGS, - .mult = NA_MULT, - .div = NA_DIV, - }, - { - .type = TYPE_GATE, - .offset = 26, - .width = PERIPH_GATE_WIDTH, - .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC, + .clkflags = CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT | + CLK_IS_BASIC, .typeflags = NA_TYPE_FLAGS, .mult = NA_MULT, .div = NA_DIV, }, }; -static struct pm_clock_node gem1_tx_nodes[] = { +static struct pm_clock_node gem1_ref_nodes[] = { { .type = TYPE_MUX, .offset = 6, .width = 1, - .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC, + .clkflags = CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT | + CLK_IS_BASIC, .typeflags = NA_TYPE_FLAGS, .mult = NA_MULT, .div = NA_DIV, }, +}; + +static struct pm_clock_node gem2_ref_nodes[] = { { - .type = TYPE_GATE, - .offset = 26, - .width = PERIPH_GATE_WIDTH, - .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC, + .type = TYPE_MUX, + .offset = 11, + .width = 1, + .clkflags = CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT | + CLK_IS_BASIC, .typeflags = NA_TYPE_FLAGS, .mult = NA_MULT, .div = NA_DIV, }, }; -static struct pm_clock_node gem2_tx_nodes[] = { +static struct pm_clock_node gem3_ref_nodes[] = { { .type = TYPE_MUX, - .offset = 11, + .offset = 16, .width = 1, - .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC, + .clkflags = CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT | + CLK_IS_BASIC, .typeflags = NA_TYPE_FLAGS, .mult = NA_MULT, .div = NA_DIV, }, +}; + +static struct pm_clock_node gem_tx_nodes[] = { { .type = TYPE_GATE, - .offset = 26, + .offset = 25, .width = PERIPH_GATE_WIDTH, .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC, .typeflags = NA_TYPE_FLAGS, @@ -656,21 +652,12 @@ static struct pm_clock_node gem2_tx_nodes[] = { }, }; -static struct pm_clock_node gem3_tx_nodes[] = { - { - .type = TYPE_MUX, - .offset = 16, - .width = 1, - .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC, - .typeflags = NA_TYPE_FLAGS, - .mult = NA_MULT, - .div = NA_DIV, - }, +static struct pm_clock_node gem_rx_nodes[] = { { .type = TYPE_GATE, .offset = 26, .width = PERIPH_GATE_WIDTH, - .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC, + .clkflags = CLK_IS_BASIC, .typeflags = NA_TYPE_FLAGS, .mult = NA_MULT, .div = NA_DIV, @@ -1442,8 +1429,8 @@ static struct pm_clock clocks[] = { .nodes = &generic_mux_div_unused_gate_nodes, .num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes), }, - [CLK_GEM0_REF] = { - .name = "gem0_ref", + [CLK_GEM0_REF_UNGATED] = { + .name = "gem0_ref_ung", .control_reg = CRL_APB_GEM0_REF_CTRL, .status_reg = 0, .parents = &((int32_t []) { @@ -1453,11 +1440,11 @@ static struct pm_clock clocks[] = { CLK_DPLL_TO_LPD, CLK_NA_PARENT }), - .nodes = &gem_nodes, - .num_nodes = ARRAY_SIZE(gem_nodes), + .nodes = &gem_ref_ungated_nodes, + .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes), }, - [CLK_GEM1_REF] = { - .name = "gem1_ref", + [CLK_GEM1_REF_UNGATED] = { + .name = "gem1_ref_ung", .control_reg = CRL_APB_GEM1_REF_CTRL, .status_reg = 0, .parents = &((int32_t []) { @@ -1467,11 +1454,11 @@ static struct pm_clock clocks[] = { CLK_DPLL_TO_LPD, CLK_NA_PARENT }), - .nodes = &gem_nodes, - .num_nodes = ARRAY_SIZE(gem_nodes), + .nodes = &gem_ref_ungated_nodes, + .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes), }, - [CLK_GEM2_REF] = { - .name = "gem2_ref", + [CLK_GEM2_REF_UNGATED] = { + .name = "gem2_ref_ung", .control_reg = CRL_APB_GEM2_REF_CTRL, .status_reg = 0, .parents = &((int32_t []) { @@ -1481,11 +1468,11 @@ static struct pm_clock clocks[] = { CLK_DPLL_TO_LPD, CLK_NA_PARENT }), - .nodes = &gem_nodes, - .num_nodes = ARRAY_SIZE(gem_nodes), + .nodes = &gem_ref_ungated_nodes, + .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes), }, - [CLK_GEM3_REF] = { - .name = "gem3_ref", + [CLK_GEM3_REF_UNGATED] = { + .name = "gem3_ref_ung", .control_reg = CRL_APB_GEM3_REF_CTRL, .status_reg = 0, .parents = &((int32_t []) { @@ -1495,8 +1482,60 @@ static struct pm_clock clocks[] = { CLK_DPLL_TO_LPD, CLK_NA_PARENT }), - .nodes = &gem_nodes, - .num_nodes = ARRAY_SIZE(gem_nodes), + .nodes = &gem_ref_ungated_nodes, + .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes), + }, + [CLK_GEM0_REF] = { + .name = "gem0_ref", + .control_reg = IOU_SLCR_GEM_CLK_CTRL, + .status_reg = 0, + .parents = &((int32_t []) { + CLK_GEM0_REF_UNGATED | + (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), + EXT_CLK_GEM0_TX_EMIO | CLK_EXTERNAL_PARENT, + CLK_NA_PARENT + }), + .nodes = &gem0_ref_nodes, + .num_nodes = ARRAY_SIZE(gem0_ref_nodes), + }, + [CLK_GEM1_REF] = { + .name = "gem1_ref", + .control_reg = IOU_SLCR_GEM_CLK_CTRL, + .status_reg = 0, + .parents = &((int32_t []) { + CLK_GEM1_REF_UNGATED | + (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), + EXT_CLK_GEM1_TX_EMIO | CLK_EXTERNAL_PARENT, + CLK_NA_PARENT + }), + .nodes = &gem1_ref_nodes, + .num_nodes = ARRAY_SIZE(gem1_ref_nodes), + }, + [CLK_GEM2_REF] = { + .name = "gem2_ref", + .control_reg = IOU_SLCR_GEM_CLK_CTRL, + .status_reg = 0, + .parents = &((int32_t []) { + CLK_GEM2_REF_UNGATED | + (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), + EXT_CLK_GEM2_TX_EMIO | CLK_EXTERNAL_PARENT, + CLK_NA_PARENT + }), + .nodes = &gem2_ref_nodes, + .num_nodes = ARRAY_SIZE(gem2_ref_nodes), + }, + [CLK_GEM3_REF] = { + .name = "gem3_ref", + .control_reg = IOU_SLCR_GEM_CLK_CTRL, + .status_reg = 0, + .parents = &((int32_t []) { + CLK_GEM3_REF_UNGATED | + (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), + EXT_CLK_GEM3_TX_EMIO | CLK_EXTERNAL_PARENT, + CLK_NA_PARENT + }), + .nodes = &gem3_ref_nodes, + .num_nodes = ARRAY_SIZE(gem3_ref_nodes), }, [CLK_USB0_BUS_REF] = { .name = "usb0_bus_ref", @@ -1960,69 +1999,93 @@ static struct pm_clock clocks[] = { .nodes = &generic_domain_crossing_nodes, .num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes), }, - /* - * This clock control requires different registers for mux and gate. - * Use control and status registers for the same. - */ [CLK_GEM0_TX] = { .name = "gem0_tx", - .control_reg = IOU_SLCR_GEM_CLK_CTRL, - .status_reg = CRL_APB_GEM0_REF_CTRL, + .control_reg = CRL_APB_GEM0_REF_CTRL, + .status_reg = 0, .parents = &((int32_t []) { - CLK_GEM0_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), - EXT_CLK_GEM0_EMIO | CLK_EXTERNAL_PARENT, + CLK_GEM0_REF, CLK_NA_PARENT }), - .nodes = &gem0_tx_nodes, - .num_nodes = ARRAY_SIZE(gem0_tx_nodes), + .nodes = &gem_tx_nodes, + .num_nodes = ARRAY_SIZE(gem_tx_nodes), }, - /* - * This clock control requires different registers for mux and gate. - * Use control and status registers for the same. - */ [CLK_GEM1_TX] = { .name = "gem1_tx", - .control_reg = IOU_SLCR_GEM_CLK_CTRL, - .status_reg = CRL_APB_GEM1_REF_CTRL, + .control_reg = CRL_APB_GEM1_REF_CTRL, + .status_reg = 0, .parents = &((int32_t []) { - CLK_GEM1_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), - EXT_CLK_GEM1_EMIO | CLK_EXTERNAL_PARENT, + CLK_GEM1_REF, CLK_NA_PARENT }), - .nodes = &gem1_tx_nodes, - .num_nodes = ARRAY_SIZE(gem1_tx_nodes), + .nodes = &gem_tx_nodes, + .num_nodes = ARRAY_SIZE(gem_tx_nodes), }, - /* - * This clock control requires different registers for mux and gate. - * Use control and status registers for the same. - */ [CLK_GEM2_TX] = { .name = "gem2_tx", - .control_reg = IOU_SLCR_GEM_CLK_CTRL, - .status_reg = CRL_APB_GEM2_REF_CTRL, + .control_reg = CRL_APB_GEM2_REF_CTRL, + .status_reg = 0, .parents = &((int32_t []) { - CLK_GEM2_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), - EXT_CLK_GEM2_EMIO | CLK_EXTERNAL_PARENT, + CLK_GEM2_REF, CLK_NA_PARENT }), - .nodes = &gem2_tx_nodes, - .num_nodes = ARRAY_SIZE(gem2_tx_nodes), + .nodes = &gem_tx_nodes, + .num_nodes = ARRAY_SIZE(gem_tx_nodes), }, - /* - * This clock control requires different registers for mux and gate. - * Use control and status registers for the same. - */ [CLK_GEM3_TX] = { .name = "gem3_tx", - .control_reg = IOU_SLCR_GEM_CLK_CTRL, - .status_reg = CRL_APB_GEM3_REF_CTRL, + .control_reg = CRL_APB_GEM3_REF_CTRL, + .status_reg = 0, + .parents = &((int32_t []) { + CLK_GEM3_REF, + CLK_NA_PARENT + }), + .nodes = &gem_tx_nodes, + .num_nodes = ARRAY_SIZE(gem_tx_nodes), + }, + [CLK_GEM0_RX] = { + .name = "gem0_rx", + .control_reg = CRL_APB_GEM0_REF_CTRL, + .status_reg = 0, .parents = &((int32_t []) { - CLK_GEM3_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), - EXT_CLK_GEM3_EMIO | CLK_EXTERNAL_PARENT, + EXT_CLK_GEM0_RX_EMIO | CLK_EXTERNAL_PARENT, CLK_NA_PARENT }), - .nodes = &gem3_tx_nodes, - .num_nodes = ARRAY_SIZE(gem3_tx_nodes), + .nodes = &gem_rx_nodes, + .num_nodes = ARRAY_SIZE(gem_rx_nodes), + }, + [CLK_GEM1_RX] = { + .name = "gem1_rx", + .control_reg = CRL_APB_GEM1_REF_CTRL, + .status_reg = 0, + .parents = &((int32_t []) { + EXT_CLK_GEM1_RX_EMIO | CLK_EXTERNAL_PARENT, + CLK_NA_PARENT + }), + .nodes = &gem_rx_nodes, + .num_nodes = ARRAY_SIZE(gem_rx_nodes), + }, + [CLK_GEM2_RX] = { + .name = "gem2_rx", + .control_reg = CRL_APB_GEM2_REF_CTRL, + .status_reg = 0, + .parents = &((int32_t []) { + EXT_CLK_GEM2_RX_EMIO | CLK_EXTERNAL_PARENT, + CLK_NA_PARENT + }), + .nodes = &gem_rx_nodes, + .num_nodes = ARRAY_SIZE(gem_rx_nodes), + }, + [CLK_GEM3_RX] = { + .name = "gem3_rx", + .control_reg = CRL_APB_GEM3_REF_CTRL, + .status_reg = 0, + .parents = &((int32_t []) { + EXT_CLK_GEM3_RX_EMIO | CLK_EXTERNAL_PARENT, + CLK_NA_PARENT + }), + .nodes = &gem_rx_nodes, + .num_nodes = ARRAY_SIZE(gem_rx_nodes), }, [CLK_ACPU_HALF] = { .name = "acpu_half", @@ -2159,17 +2222,29 @@ static struct pm_ext_clock ext_clocks[] = { [EXT_CLK_INDEX(EXT_CLK_SWDT1)] = { .name = "swdt1_ext_clk", }, - [EXT_CLK_INDEX(EXT_CLK_GEM0_EMIO)] = { - .name = "gem0_emio_clk", + [EXT_CLK_INDEX(EXT_CLK_GEM0_TX_EMIO)] = { + .name = "gem0_tx_ext", + }, + [EXT_CLK_INDEX(EXT_CLK_GEM1_TX_EMIO)] = { + .name = "gem1_tx_ext", + }, + [EXT_CLK_INDEX(EXT_CLK_GEM2_TX_EMIO)] = { + .name = "gem2_tx_ext", + }, + [EXT_CLK_INDEX(EXT_CLK_GEM3_TX_EMIO)] = { + .name = "gem3_tx_ext", + }, + [EXT_CLK_INDEX(EXT_CLK_GEM0_RX_EMIO)] = { + .name = "gem0_rx_ext", }, - [EXT_CLK_INDEX(EXT_CLK_GEM1_EMIO)] = { - .name = "gem1_emio_clk", + [EXT_CLK_INDEX(EXT_CLK_GEM1_RX_EMIO)] = { + .name = "gem1_rx_ext", }, - [EXT_CLK_INDEX(EXT_CLK_GEM2_EMIO)] = { - .name = "gem2_emio_clk", + [EXT_CLK_INDEX(EXT_CLK_GEM2_RX_EMIO)] = { + .name = "gem2_rx_ext", }, - [EXT_CLK_INDEX(EXT_CLK_GEM3_EMIO)] = { - .name = "gem3_emio_clk", + [EXT_CLK_INDEX(EXT_CLK_GEM3_RX_EMIO)] = { + .name = "gem3_rx_ext", }, [EXT_CLK_INDEX(EXT_CLK_MIO50_OR_MIO51)] = { .name = "mio_clk_50_51", diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h index c758efdfc..4c5f22dff 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h @@ -102,14 +102,14 @@ enum clock_id { CLK_IOU_SWITCH, CLK_GEM_TSU_REF, CLK_GEM_TSU, - CLK_GEM0_REF, - CLK_GEM1_REF, - CLK_GEM2_REF, - CLK_GEM3_REF, CLK_GEM0_TX, CLK_GEM1_TX, CLK_GEM2_TX, CLK_GEM3_TX, + CLK_GEM0_RX, + CLK_GEM1_RX, + CLK_GEM2_RX, + CLK_GEM3_RX, CLK_QSPI_REF, CLK_SDIO0_REF, CLK_SDIO1_REF, @@ -161,6 +161,14 @@ enum clock_id { CLK_CAN0_MIO, CLK_CAN1_MIO, CLK_ACPU_FULL, + CLK_GEM0_REF, + CLK_GEM1_REF, + CLK_GEM2_REF, + CLK_GEM3_REF, + CLK_GEM0_REF_UNGATED, + CLK_GEM1_REF_UNGATED, + CLK_GEM2_REF_UNGATED, + CLK_GEM3_REF_UNGATED, END_OF_OUTPUT_CLKS, }; @@ -175,10 +183,14 @@ enum { EXT_CLK_GT_CRX_REF, EXT_CLK_SWDT0, EXT_CLK_SWDT1, - EXT_CLK_GEM0_EMIO, - EXT_CLK_GEM1_EMIO, - EXT_CLK_GEM2_EMIO, - EXT_CLK_GEM3_EMIO, + EXT_CLK_GEM0_TX_EMIO, + EXT_CLK_GEM1_TX_EMIO, + EXT_CLK_GEM2_TX_EMIO, + EXT_CLK_GEM3_TX_EMIO, + EXT_CLK_GEM0_RX_EMIO, + EXT_CLK_GEM1_RX_EMIO, + EXT_CLK_GEM2_RX_EMIO, + EXT_CLK_GEM3_RX_EMIO, EXT_CLK_MIO50_OR_MIO51, EXT_CLK_MIO0, EXT_CLK_MIO1, -- cgit v1.2.3 From b3ce966ab3d88f84b0f0c709d47cc8755f2d9170 Mon Sep 17 00:00:00 2001 From: Mounika Grace Akula Date: Wed, 9 Jan 2019 17:38:13 +0530 Subject: zynqmp: pm: Add LPD WDT clock to the pm_clock structure This patch adds LPD WDT clock node to the pm_clock clocks structure list so that LPD WDT can be used from Linux. Also this patch removes the CLK_LPD_LSBUS from invalid clock list to allow the registration of this clock to CCF framework as it is the parent of LPD WDT. Signed-off-by: Mounika Grace Akula Signed-off-by: Jolly Shah Change-Id: Iea065aa8150eaba4bb4b42bc6be1fd4b7fe7b403 --- plat/xilinx/zynqmp/include/zynqmp_def.h | 3 ++- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 13 ++++++++++++- plat/xilinx/zynqmp/pm_service/pm_api_clock.h | 1 + 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h index 8648b9ab2..5d335d945 100644 --- a/plat/xilinx/zynqmp/include/zynqmp_def.h +++ b/plat/xilinx/zynqmp/include/zynqmp_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -330,6 +330,7 @@ #define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) #define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) #define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) +#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) /* Global general storage register base address */ #define GGS_BASEADDR (0xFFD80030U) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index 347f5892f..e3050724d 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -2198,6 +2198,18 @@ static struct pm_clock clocks[] = { .nodes = &can1_nodes, .num_nodes = ARRAY_SIZE(can1_nodes), }, + [CLK_LPD_WDT] = { + .name = "lpd_wdt", + .control_reg = IOU_SLCR_WDT_CLK_SEL, + .status_reg = 0, + .parents = &((int32_t []) { + CLK_LPD_LSBUS, + EXT_CLK_SWDT1 | CLK_EXTERNAL_PARENT, + CLK_NA_PARENT + }), + .nodes = &wdt_nodes, + .num_nodes = ARRAY_SIZE(wdt_nodes), + }, }; static struct pm_ext_clock ext_clocks[] = { @@ -2343,7 +2355,6 @@ static uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB, CLK_TOPSW_LSBUS, CLK_GTGREF0_REF, CLK_LPD_SWITCH, - CLK_LPD_LSBUS, CLK_CPU_R5, CLK_CPU_R5_CORE, CLK_CSU_SPB, diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h index 4c5f22dff..5bed5a617 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h @@ -169,6 +169,7 @@ enum clock_id { CLK_GEM1_REF_UNGATED, CLK_GEM2_REF_UNGATED, CLK_GEM3_REF_UNGATED, + CLK_LPD_WDT, END_OF_OUTPUT_CLKS, }; -- cgit v1.2.3 From 20fdf0b05c950c46688ff6d6ee8dd1e1c99d88d6 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Fri, 5 Oct 2018 11:18:42 -0700 Subject: zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid clock list would not be registered to CCF framework and so cannot be used as parent of other clocks. WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock). If CLK_TOPSW_LSBUS is not registered, CCF would not recognize that clock and hence rate of WDT clock would be calculated to be 0 by CCF(as parent rate is considered 0). So it is necessary to allow registration of CLK_TOPSW_LSBUS clock. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: Iceaba0f137784fc5fd666e66ffc4c143381c6ccc --- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index e3050724d..9ea8cd43e 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -2352,7 +2352,6 @@ static uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB, CLK_DBG_TSTMP, CLK_DDR_REF, CLK_TOPSW_MAIN, - CLK_TOPSW_LSBUS, CLK_GTGREF0_REF, CLK_LPD_SWITCH, CLK_CPU_R5, -- cgit v1.2.3 From e1fcb1bf8949a20ca6af9c5aa3ce744554a0a36b Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 3 Jan 2020 14:21:03 -0800 Subject: Tegra194: mce: fix error code signedness The MCE driver's helper functions were using postive values as error codes. This patch updates the functions to return negative values as error codes instead. Some functions are updated to use the right error code. Signed-off-by: Varun Wadekar Change-Id: I3e2ecc30a6272a357e1a22ec850543fde2a694f6 --- plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 29 +++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index 1dd1f51b9..536ed57c0 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -165,7 +165,7 @@ int32_t nvg_online_core(uint32_t core) /* sanity check the core ID value */ if (core > (uint32_t)PLATFORM_CORE_COUNT) { ERROR("%s: unknown core id (%d)\n", __func__, core); - ret = EINVAL; + ret = -EINVAL; } else { /* get a core online */ nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE, @@ -183,15 +183,15 @@ int32_t nvg_online_core(uint32_t core) */ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) { - int32_t ret; + int32_t ret = 0; /* sanity check GSC ID */ if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) { ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx); - ret = EINVAL; + ret = -EINVAL; } else { nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, - (uint64_t)gsc_idx); + (uint64_t)gsc_idx); } return ret; @@ -209,11 +209,12 @@ int32_t nvg_roc_clean_cache(void) ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { if (nvg_cache_clean() == 0U) { ERROR("%s: failed\n", __func__); - ret = EINVAL; + ret = -ENODEV; } } else { - ret = EINVAL; + ret = -ENOTSUP; } + return ret; } @@ -229,11 +230,12 @@ int32_t nvg_roc_flush_cache(void) ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { if (nvg_cache_clean_inval() == 0U) { ERROR("%s: failed\n", __func__); - ret = EINVAL; + ret = -ENODEV; } } else { - ret = EINVAL; + ret = -ENOTSUP; } + return ret; } @@ -249,11 +251,12 @@ int32_t nvg_roc_clean_cache_trbits(void) ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { if (nvg_cache_inval_all() == 0U) { ERROR("%s: failed\n", __func__); - ret = EINVAL; + ret = -ENODEV; } } else { - ret = EINVAL; + ret = -ENOTSUP; } + return ret; } @@ -271,8 +274,8 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) (state != (uint32_t)TEGRA_NVG_CORE_C6) && (state != (uint32_t)TEGRA_NVG_CORE_C7)) { - ERROR("%s: unknown cstate (%d)\n", __func__, state); - ret = EINVAL; + ERROR("%s: unknown cstate (%u)\n", __func__, state); + ret = -EINVAL; } else { /* time (TSC ticks) until the core is expected to get a wake event */ nvg_set_wake_time(wake_time); -- cgit v1.2.3 From 650a435c8359b14ac1ca63788c90d0683db397fd Mon Sep 17 00:00:00 2001 From: Mark Dykes Date: Wed, 8 Jan 2020 20:37:18 +0000 Subject: Revert "GCC: Upgrade to version 9.2-2019.12 of toolchain" This reverts commit de9bf1d8a2de952bfc17cdf7082b41f9c185e54d. Change-Id: Iebb6297ce290a10ee850bf6a9c71e7eb530b085f --- docs/getting_started/initial-build.rst | 8 ++++---- docs/getting_started/prerequisites.rst | 2 +- docs/plat/allwinner.rst | 4 ++-- docs/plat/arm/fvp/index.rst | 2 +- docs/plat/arm/juno/index.rst | 2 +- docs/plat/hikey.rst | 2 +- docs/plat/imx8.rst | 2 +- docs/plat/imx8m.rst | 2 +- docs/plat/intel-agilex.rst | 2 +- docs/plat/intel-stratix10.rst | 2 +- docs/plat/ls1043a.rst | 4 ++-- docs/plat/marvell/build.rst | 2 +- docs/plat/meson-g12a.rst | 2 +- docs/plat/meson-gxbb.rst | 2 +- docs/plat/meson-gxl.rst | 2 +- docs/plat/mt8183.rst | 2 +- docs/plat/poplar.rst | 2 +- docs/plat/qemu-sbsa.rst | 2 +- docs/plat/rockchip.rst | 2 +- docs/plat/rpi3.rst | 8 ++++---- docs/plat/rpi4.rst | 2 +- docs/plat/ti-k3.rst | 2 +- 22 files changed, 30 insertions(+), 30 deletions(-) diff --git a/docs/getting_started/initial-build.rst b/docs/getting_started/initial-build.rst index 893aba245..41cd4d1c9 100644 --- a/docs/getting_started/initial-build.rst +++ b/docs/getting_started/initial-build.rst @@ -8,13 +8,13 @@ Performing an Initial Build .. code:: shell - export CROSS_COMPILE=/bin/aarch64-none-elf- + export CROSS_COMPILE=/bin/aarch64-linux-gnu- For AArch32: .. code:: shell - export CROSS_COMPILE=/bin/arm-none-eabi- + export CROSS_COMPILE=/bin/arm-eabi- It is possible to build TF-A using Clang or Arm Compiler 6. To do so ``CC`` needs to point to the clang or armclang binary, which will @@ -32,7 +32,7 @@ Performing an Initial Build .. code:: shell - export CROSS_COMPILE=/bin/aarch64-none-elf- + export CROSS_COMPILE=/bin/aarch64-linux-gnu- make CC=/bin/armclang PLAT= all Clang will be selected when the base name of the path assigned to ``CC`` @@ -43,7 +43,7 @@ Performing an Initial Build .. code:: shell - export CROSS_COMPILE=/bin/aarch64-none-elf- + export CROSS_COMPILE=/bin/aarch64-linux-gnu- make CC=/bin/clang PLAT= all - Change to the root directory of the TF-A source tree and build. diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst index 3e0c8fff2..27ad0ed5f 100644 --- a/docs/getting_started/prerequisites.rst +++ b/docs/getting_started/prerequisites.rst @@ -26,7 +26,7 @@ Toolchain |TF-A| can be built with any of the following *cross-compiler* toolchains that target the Armv7-A or Armv8-A architectures: -- GCC >= 9.2-2019.12 (from the `Arm Developer website`_) +- GCC >= 8.3-2019.03 (from the `Arm Developer website`_) - Clang >= 4.0 - Arm Compiler >= 6.0 diff --git a/docs/plat/allwinner.rst b/docs/plat/allwinner.rst index 5c905d86b..a1e06590a 100644 --- a/docs/plat/allwinner.rst +++ b/docs/plat/allwinner.rst @@ -26,13 +26,13 @@ To build for machines with an A64 or H5 SoC: .. code:: shell - make CROSS_COMPILE=aarch64-none-elf- PLAT=sun50i_a64 DEBUG=1 bl31 + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31 To build for machines with an H6 SoC: .. code:: shell - make CROSS_COMPILE=aarch64-none-elf- PLAT=sun50i_h6 DEBUG=1 bl31 + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31 .. _U-Boot documentation: http://git.denx.de/?p=u-boot.git;f=board/sunxi/README.sunxi64;hb=HEAD diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index 37010e1a5..b6396b97c 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -223,7 +223,7 @@ address ``0x82000000``, the firmware can be built like this: .. code:: shell - CROSS_COMPILE=aarch64-none-elf- \ + CROSS_COMPILE=aarch64-linux-gnu- \ make PLAT=fvp DEBUG=1 \ RESET_TO_BL31=1 \ ARM_LINUX_KERNEL_AS_BL33=1 \ diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst index cf328fac9..6429ede7a 100644 --- a/docs/plat/arm/juno/index.rst +++ b/docs/plat/arm/juno/index.rst @@ -136,7 +136,7 @@ a single FIP binary. It assumes that a Linaro release has been installed. .. code:: shell - export CROSS_COMPILE=/bin/aarch64-none-elf- + export CROSS_COMPILE=/bin/aarch64-linux-gnu- - The following parameters should be used to build BL1 and BL2 in AArch64 and point to the BL32 file. diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst index d7a01a881..372d38867 100644 --- a/docs/plat/hikey.rst +++ b/docs/plat/hikey.rst @@ -78,7 +78,7 @@ Build Procedure EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey/${BUILD_OPTION}_${AARCH64_TOOLCHAIN} # Build fastboot for Trusted Firmware-A. It's used for recovery mode. cd ${BUILD_PATH}/atf-fastboot - CROSS_COMPILE=aarch64-none-elf- make PLAT=hikey DEBUG=1 + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=hikey DEBUG=1 # Convert DEBUG/RELEASE to debug/release FASTBOOT_BUILD_OPTION=$(echo ${BUILD_OPTION} | tr '[A-Z]' '[a-z]') cd ${EDK2_DIR} diff --git a/docs/plat/imx8.rst b/docs/plat/imx8.rst index cec1a39d8..49ba37412 100644 --- a/docs/plat/imx8.rst +++ b/docs/plat/imx8.rst @@ -40,7 +40,7 @@ Build Procedure .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make PLAT= bl31 + CROSS_COMPILE=aarch64-linux-gnu- make PLAT= bl31 Target_SoC should be "imx8qm" for i.MX8QM SoC. Target_SoC should be "imx8qx" for i.MX8QX SoC. diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst index 0116b34a9..8acd13cf7 100644 --- a/docs/plat/imx8m.rst +++ b/docs/plat/imx8m.rst @@ -28,7 +28,7 @@ Build Procedure .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make PLAT= bl31 + CROSS_COMPILE=aarch64-linux-gnu- make PLAT= bl31 Target_SoC should be "imx8mq" for i.MX8MQ SoC. Target_SoC should be "imx8mm" for i.MX8MM SoC. diff --git a/docs/plat/intel-agilex.rst b/docs/plat/intel-agilex.rst index f60bf14ad..ff27b6b5f 100644 --- a/docs/plat/intel-agilex.rst +++ b/docs/plat/intel-agilex.rst @@ -41,7 +41,7 @@ Build Procedure .. code:: bash - make CROSS_COMPILE=aarch64-none-elf- bl2 fip PLAT=agilex + make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=agilex BL33=PEI.ROM Install Procedure diff --git a/docs/plat/intel-stratix10.rst b/docs/plat/intel-stratix10.rst index 5f33d12de..7f8d18e03 100644 --- a/docs/plat/intel-stratix10.rst +++ b/docs/plat/intel-stratix10.rst @@ -41,7 +41,7 @@ Build Procedure .. code:: bash - make CROSS_COMPILE=aarch64-none-elf- bl2 fip PLAT=stratix10 + make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=stratix10 BL33=PEI.ROM Install Procedure diff --git a/docs/plat/ls1043a.rst b/docs/plat/ls1043a.rst index 5a8f7558f..72a51f3cc 100644 --- a/docs/plat/ls1043a.rst +++ b/docs/plat/ls1043a.rst @@ -59,13 +59,13 @@ Build Procedure .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make PLAT=ls1043 bl1 + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 bl1 Build fip: .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make PLAT=ls1043 fip \ + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 fip \ BL33=u-boot.bin NEED_BL32=yes BL32=tee.bin SPD=opteed Deploy TF-A Images diff --git a/docs/plat/marvell/build.rst b/docs/plat/marvell/build.rst index d0e37c683..c10bcff79 100644 --- a/docs/plat/marvell/build.rst +++ b/docs/plat/marvell/build.rst @@ -9,7 +9,7 @@ Build Instructions .. code:: shell - > export CROSS_COMPILE=/path/to/toolchain/aarch64-none-elf- + > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu- (2) Set path for FIP images: diff --git a/docs/plat/meson-g12a.rst b/docs/plat/meson-g12a.rst index 8b06cc287..7cd1bf746 100644 --- a/docs/plat/meson-g12a.rst +++ b/docs/plat/meson-g12a.rst @@ -17,7 +17,7 @@ In order to build it: .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=g12a + CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=g12a This port has been tested on a SEI510 board. After building it, follow the instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the diff --git a/docs/plat/meson-gxbb.rst b/docs/plat/meson-gxbb.rst index f891ecd81..2cd8342cb 100644 --- a/docs/plat/meson-gxbb.rst +++ b/docs/plat/meson-gxbb.rst @@ -17,7 +17,7 @@ In order to build it: .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=gxbb bl31 + CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxbb bl31 This port has been tested in a ODROID-C2. After building it, follow the instructions in the `U-Boot repository`_, replacing the mentioned **bl31.bin** diff --git a/docs/plat/meson-gxl.rst b/docs/plat/meson-gxl.rst index 170d7c774..c6d850446 100644 --- a/docs/plat/meson-gxl.rst +++ b/docs/plat/meson-gxl.rst @@ -17,7 +17,7 @@ In order to build it: .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=gxl + CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxl This port has been tested on a Lepotato. After building it, follow the instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the diff --git a/docs/plat/mt8183.rst b/docs/plat/mt8183.rst index 7a0830f08..c639be1ee 100644 --- a/docs/plat/mt8183.rst +++ b/docs/plat/mt8183.rst @@ -17,4 +17,4 @@ How to Build .. code:: shell - make CROSS_COMPILE=aarch64-none-elf- PLAT=mt8183 DEBUG=1 + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8183 DEBUG=1 diff --git a/docs/plat/poplar.rst b/docs/plat/poplar.rst index 040b59396..215f55142 100644 --- a/docs/plat/poplar.rst +++ b/docs/plat/poplar.rst @@ -68,7 +68,7 @@ Build Procedure .. code:: bash - make CROSS_COMPILE=aarch64-none-elf- all fip SPD=none PLAT=poplar + make CROSS_COMPILE=aarch64-linux-gnu- all fip SPD=none PLAT=poplar BL33=u-boot.bin - Build l-loader (generated the final fastboot.bin) diff --git a/docs/plat/qemu-sbsa.rst b/docs/plat/qemu-sbsa.rst index 5e8535c72..51fe41404 100644 --- a/docs/plat/qemu-sbsa.rst +++ b/docs/plat/qemu-sbsa.rst @@ -27,7 +27,7 @@ To build TF-A: git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa cd tfa - export CROSS_COMPILE=aarch64-none-elf- + export CROSS_COMPILE=aarch64-linux-gnu- make PLAT=qemu_sbsa all fip Images will be placed at build/qemu_sbsa/release (bl1.bin and fip.bin). diff --git a/docs/plat/rockchip.rst b/docs/plat/rockchip.rst index 2c3c38fb5..b7c43fbe1 100644 --- a/docs/plat/rockchip.rst +++ b/docs/plat/rockchip.rst @@ -35,7 +35,7 @@ these images need to get build from the TF-A repository. For AARCH64 architectures the build command looks like - make CROSS_COMPILE=aarch64-none-elf- PLAT=rk3399 bl32 + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl32 while AARCH32 needs a slightly different command diff --git a/docs/plat/rpi3.rst b/docs/plat/rpi3.rst index 5c7b6d5dd..38c3dfa82 100644 --- a/docs/plat/rpi3.rst +++ b/docs/plat/rpi3.rst @@ -315,7 +315,7 @@ Then compile TF-A. For a 32-bit kernel, use the following command line: .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \ + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \ RPI3_BL33_IN_AARCH32=1 \ BL33=../rpi3-arm-tf-bootstrap/aarch32/el2-bootstrap.bin @@ -323,7 +323,7 @@ For a 64-bit kernel, use this other command line: .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \ + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \ BL33=../rpi3-arm-tf-bootstrap/aarch64/el2-bootstrap.bin However, enabling PSCI support in a 64-bit kernel is really easy. In the @@ -340,7 +340,7 @@ For a 64-bit kernel: .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \ + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \ PRELOADED_BL33_BASE=0x02000000 \ RPI3_PRELOADED_DTB_BASE=0x01000000 \ RPI3_DIRECT_LINUX_BOOT=1 @@ -349,7 +349,7 @@ For a 32-bit kernel: .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \ + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \ PRELOADED_BL33_BASE=0x02000000 \ RPI3_PRELOADED_DTB_BASE=0x01000000 \ RPI3_DIRECT_LINUX_BOOT=1 \ diff --git a/docs/plat/rpi4.rst b/docs/plat/rpi4.rst index e87aef71a..0f529c103 100644 --- a/docs/plat/rpi4.rst +++ b/docs/plat/rpi4.rst @@ -22,7 +22,7 @@ one universal binary (bl31.bin), which can be built with: .. code:: shell - CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi4 DEBUG=1 + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi4 DEBUG=1 Copy the generated build/rpi4/debug/bl31.bin to the SD card, either renaming it to ``armstub8.bin`` or adding an entry starting with ``armstub=``, diff --git a/docs/plat/ti-k3.rst b/docs/plat/ti-k3.rst index 2626e6741..4843227df 100644 --- a/docs/plat/ti-k3.rst +++ b/docs/plat/ti-k3.rst @@ -27,7 +27,7 @@ TF-A: .. code:: shell - make CROSS_COMPILE=aarch64-none-elf- PLAT=k3 SPD=opteed all + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=k3 SPD=opteed all OP-TEE: -- cgit v1.2.3 From 3c0d784cfbeaed2f1b8be6be6eedd3a5fd66fd2f Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Mon, 9 Dec 2019 16:08:00 -0600 Subject: docs: Creating a Change Log Template File Creating a Change Log Template for ALL to update with relevant new features, changes, fixes and known issues for each upcoming release of Trusted Firmware-A. The contents of this file should be added to the collective change log at the time of release code freeze. Signed-off-by: Lauren Wehrmeister Change-Id: Idfbdcef0d40b10312dc88b6e1cbe31856fda887e --- docs/change-log-upcoming.rst | 145 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 docs/change-log-upcoming.rst diff --git a/docs/change-log-upcoming.rst b/docs/change-log-upcoming.rst new file mode 100644 index 000000000..3d7d5094d --- /dev/null +++ b/docs/change-log-upcoming.rst @@ -0,0 +1,145 @@ +Change Log for Upcoming Release +=============================== + +This document contains a summary of the new features, changes, fixes and known +issues to be included in the upcoming release of Trusted Firmware-A. The contents +of this file will be moved to the collective change-log.rst file at the time of +release code freeze. + + +Upcoming Release Version 2.3 +---------------------------- + +**Trusted Firmware-A Contributors, +Please log all relevant new features, changes, fixes, and known issues for the +upcoming release. For the CPU support, drivers, and tools sections please preface +the log description with the relevant key word, example: ": ". Use the RST format convention already used in the Change Log.** + +New Features +^^^^^^^^^^^^ + +- Arm Architecture + - Example: "Add support for Branch Target Identification (BTI)" + +- Build System + - Example: "Add support for default stack-protector flag" + +- CPU Support + - Example: "cortex-a55: Workaround for erratum 1221012" + +- Drivers + - Example: "console: Allow the console to register multiple times" + +- Libraries + - Example: "Introduce BTI support in Library at ROM (romlib)" + +- New Platforms Support + - Example: "qemu/qemu_sbsa: New platform support added for QEMU SBSA platform" + +- Platforms + - Example: "arm/common: Introduce wrapper functions to setup secure watchdog" + +- PSCI + - Example: "Adding new optional PSCI hook ``pwr_domain_on_finish_late``" + +- Security + - Example: "UBSAN support and handlers" + +- Tools + - Example: "fiptool: Add support to build fiptool on Windows." + + +Changed +^^^^^^^ + +- Arm Architecture + - Example: "Refactor ARMv8.3 Pointer Authentication support code" + +- BL-Specific + - Example: "BL2: Invalidate dcache build option for BL2 entry at EL3" + +- Boot Flow + - Example: "Add helper to parse BL31 parameters (both versions)" + +- Drivers + - Example: "gicv3: Prevent pending G1S interrupt from becoming G0 interrupt" + +- Platforms + - Example: "arm/common: Shorten the Firmware Update (FWU) process" + +- PSCI + - Example: "PSCI: Lookup list of parent nodes to lock only once" + +- Secure Partition Manager (SPM) + - Example: "Move shim layer to TTBR1_EL1" + +- Security + - Example: "Refactor SPSR initialisation code" + +- Tools + - Example: "cert_create: Remove RSA PKCS#1 v1.5 support" + + +Resolved Issues +^^^^^^^^^^^^^^^ + +- Arm Architecture + - Example: "Fix restoration of PAuth context" + +- BL-Specific + - Example: "Fix BL31 crash reporting on AArch64 only platforms" + +- Build System + - Example: "Remove several warnings reported with W=2 and W=1" + +- Code Quality + - Example: "Unify type of "cpu_idx" across PSCI module" + +- CPU Support + - Example: "cortex-a12: Fix MIDR mask" + +- Drivers + - Example: "scmi: Fix wrong payload length" + +- Library Code + - Example: "libc: Fix memchr implementation" + +- Platforms + - Example: "rpi: rpi3: Fix compilation error when stack protector is enabled" + +- Security + - Example: "AArch32: Disable Secure Cycle Counter" + +Deprecations +^^^^^^^^^^^^ + +- Common Code + - Example: "Remove MULTI_CONSOLE_API flag and references to it" + +- Drivers + - Example: "console: Remove deprecated finish_console_register" + +- Secure Partition Manager (SPM): + - Example: "Prototype SPCI-based SPM (services/std_svc/spm) will be replaced + with alternative methods of secure partitioning support." + +Known Issues +^^^^^^^^^^^^ + +- Build System + - dtb: DTB creation not supported when building on a Windows host. + + This step in the build process is skipped when running on a Windows host. A + known issue from the 1.6 release. + +- Platforms + - arm/juno: System suspend from Linux does not function as documented in the + user guide + + Following the instructions provided in the user guide document does not + result in the platform entering system suspend state as expected. A message + relating to the hdlcd driver failing to suspend will be emitted on the + Linux terminal. + + - mediatek/mt6795: This platform does not build in this release -- cgit v1.2.3 From 7a05f06a84f75ee36b6fb2f1c72591eeb5c9de69 Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Thu, 2 Jan 2020 16:32:41 -0600 Subject: Remove redundant declarations. In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by: Madhukar Pappireddy --- drivers/auth/auth_mod.c | 3 --- drivers/renesas/rcar/io/io_rcar.c | 3 --- plat/imx/imx8m/include/imx8m_psci.h | 4 ---- plat/intel/soc/agilex/include/agilex_system_manager.h | 1 - plat/intel/soc/stratix10/include/s10_system_manager.h | 2 -- plat/mediatek/mt8173/drivers/spm/spm.h | 1 - plat/nvidia/tegra/include/tegra_private.h | 1 - plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h | 1 - plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 1 - plat/rockchip/rk3328/drivers/soc/soc.h | 2 -- 10 files changed, 19 deletions(-) diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c index a6538c4e5..3fb2d1a48 100644 --- a/drivers/auth/auth_mod.c +++ b/drivers/auth/auth_mod.c @@ -30,9 +30,6 @@ #pragma weak plat_set_nv_ctr2 -/* Pointer to CoT */ -extern const auth_img_desc_t *const *const cot_desc_ptr; -extern unsigned int auth_img_flags[MAX_NUMBER_IDS]; static int cmp_auth_param_type_desc(const auth_param_type_desc_t *a, const auth_param_type_desc_t *b) diff --git a/drivers/renesas/rcar/io/io_rcar.c b/drivers/renesas/rcar/io/io_rcar.c index 650931bb4..b82c51078 100644 --- a/drivers/renesas/rcar/io/io_rcar.c +++ b/drivers/renesas/rcar/io/io_rcar.c @@ -28,9 +28,6 @@ extern int32_t plat_get_drv_source(uint32_t id, uintptr_t *dev, uintptr_t *image_spec); -extern int auth_mod_verify_img(unsigned int img_id, void *ptr, - unsigned int len); - static int32_t rcar_dev_open(const uintptr_t dev_spec __attribute__ ((unused)), io_dev_info_t **dev_info); static int32_t rcar_dev_close(io_dev_info_t *dev_info); diff --git a/plat/imx/imx8m/include/imx8m_psci.h b/plat/imx/imx8m/include/imx8m_psci.h index 496640383..c33d25e82 100644 --- a/plat/imx/imx8m/include/imx8m_psci.h +++ b/plat/imx/imx8m/include/imx8m_psci.h @@ -15,13 +15,9 @@ int imx_pwr_domain_on(u_register_t mpidr); void imx_pwr_domain_on_finish(const psci_power_state_t *target_state); void imx_pwr_domain_off(const psci_power_state_t *target_state); int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint); -int imx_validate_power_state(unsigned int power_state, psci_power_state_t *rq_state); void imx_cpu_standby(plat_local_state_t cpu_state); void imx_domain_suspend(const psci_power_state_t *target_state); void imx_domain_suspend_finish(const psci_power_state_t *target_state); -void imx_get_sys_suspend_power_state(psci_power_state_t *req_state); -void __dead2 imx_system_reset(void); -void __dead2 imx_system_off(void); void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state); #endif /* IMX8M_PSCI_H */ diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h index 381c2d355..be2953664 100644 --- a/plat/intel/soc/agilex/include/agilex_system_manager.h +++ b/plat/intel/soc/agilex/include/agilex_system_manager.h @@ -73,7 +73,6 @@ #define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 #define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) -void enable_nonsecure_access(void); void enable_ns_bridge_access(void); #endif diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h index a67d689fa..4abfedb56 100644 --- a/plat/intel/soc/stratix10/include/s10_system_manager.h +++ b/plat/intel/soc/stratix10/include/s10_system_manager.h @@ -69,5 +69,3 @@ #define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) -void enable_nonsecure_access(void); - diff --git a/plat/mediatek/mt8173/drivers/spm/spm.h b/plat/mediatek/mt8173/drivers/spm/spm.h index 403303a0d..0c05410a6 100644 --- a/plat/mediatek/mt8173/drivers/spm/spm.h +++ b/plat/mediatek/mt8173/drivers/spm/spm.h @@ -320,7 +320,6 @@ void spm_register_init(void); void spm_go_to_hotplug(void); void spm_init_event_vector(const struct pcm_desc *pcmdesc); void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc); -void spm_set_sysclk_settle(void); int is_mcdi_ready(void); int is_hotplug_ready(void); int is_suspend_ready(void); diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index cd2f77308..761acdea5 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -137,7 +137,6 @@ int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); void tegra_delay_timer_init(void); void tegra_secure_entrypoint(void); -void tegra186_cpu_reset_handler(void); /* Declarations for tegra_sip_calls.c */ uintptr_t tegra_sip_handler(uint32_t smc_fid, diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 3994b2d75..7dcfd84be 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -66,7 +66,6 @@ uint64_t nvg_get_result(void); uint64_t nvg_cache_clean(void); uint64_t nvg_cache_clean_inval(void); uint64_t nvg_cache_inval_all(void); -int32_t nvg_roc_clean_cache_trbits(void); void nvg_enable_strict_checking_mode(void); /* MCE helper functions */ diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 1188a3b81..fa5ba6263 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -26,7 +26,6 @@ #include #include -extern void tegra194_cpu_reset_handler(void); extern uint32_t __tegra194_cpu_reset_handler_data, __tegra194_cpu_reset_handler_end; diff --git a/plat/rockchip/rk3328/drivers/soc/soc.h b/plat/rockchip/rk3328/drivers/soc/soc.h index a1f35b282..e8cbc09f6 100644 --- a/plat/rockchip/rk3328/drivers/soc/soc.h +++ b/plat/rockchip/rk3328/drivers/soc/soc.h @@ -16,8 +16,6 @@ #define TIMER_INTSTATUS 0x18 #define TIMER_EN 0x1 -extern const unsigned char rockchip_power_domain_tree_desc[]; - /**************************** read/write **************************************/ #ifndef BITS_WMSK #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) -- cgit v1.2.3 From daa9b6ea641c841478b861b0fb459bc066233358 Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Mon, 6 Jan 2020 14:42:30 -0600 Subject: Simplify PMF helper macro definitions across header files In further patches, we aim to enable -Wredundant-decls by default. This rearragement of helper macros is necessary to make Coverity tool happy as well as making sure there are no redundant function declarations for PMF related declarations. Also, PMF related macros were added to provide appropriate function declarations for helper APIs which capture PSCI statistics. Change-Id: I36273032dde8fa079ef71235ed3a4629c5bfd981 Signed-off-by: Madhukar Pappireddy --- include/lib/pmf/pmf.h | 102 ------------------------------------- include/lib/pmf/pmf_helpers.h | 112 +++++++++++++++++++++++++++++++++++++---- plat/common/plat_psci_common.c | 2 + 3 files changed, 104 insertions(+), 112 deletions(-) diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h index df7c9ff31..3fc8e3863 100644 --- a/include/lib/pmf/pmf.h +++ b/include/lib/pmf/pmf.h @@ -54,108 +54,6 @@ #define PMF_PSCI_STAT_SVC_ID 0 #define PMF_RT_INSTR_SVC_ID 1 -#if ENABLE_PMF -/* - * Convenience macros for capturing time-stamp. - */ -#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) \ - void pmf_capture_timestamp_with_cache_maint_ ## _name( \ - unsigned int tid, \ - unsigned long long ts); \ - void pmf_capture_timestamp_ ## _name( \ - unsigned int tid, \ - unsigned long long ts); - -#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) \ - do { \ - unsigned long long ts = read_cntpct_el0(); \ - if (((_flags) & PMF_CACHE_MAINT) != 0U) \ - pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), ts);\ - else \ - pmf_capture_timestamp_ ## _name((_tid), ts); \ - } while (0) - -#define PMF_CAPTURE_AND_GET_TIMESTAMP(_name, _tid, _flags, _tsval) \ - do { \ - (_tsval) = read_cntpct_el0(); \ - CASSERT(sizeof(_tsval) == sizeof(unsigned long long), invalid_tsval_size);\ - if (((_flags) & PMF_CACHE_MAINT) != 0U) \ - pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_tsval));\ - else \ - pmf_capture_timestamp_ ## _name((_tid), (_tsval));\ - } while (0) - -#define PMF_WRITE_TIMESTAMP(_name, _tid, _flags, _wrval) \ - do { \ - CASSERT(sizeof(_wrval) == sizeof(unsigned long long), invalid_wrval_size);\ - if (((_flags) & PMF_CACHE_MAINT) != 0U) \ - pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_wrval));\ - else \ - pmf_capture_timestamp_ ## _name((_tid), (_wrval));\ - } while (0) - -/* - * Convenience macros for retrieving time-stamp. - */ -#define PMF_DECLARE_GET_TIMESTAMP(_name) \ - unsigned long long pmf_get_timestamp_by_index_ ## _name(\ - unsigned int tid, \ - unsigned int cpuid, \ - unsigned int flags); \ - unsigned long long pmf_get_timestamp_by_mpidr_ ## _name(\ - unsigned int tid, \ - u_register_t mpidr, \ - unsigned int flags); - -#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)\ - _tsval = pmf_get_timestamp_by_mpidr_ ## _name(_tid, _mpidr, _flags) - -#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)\ - _tsval = pmf_get_timestamp_by_index_ ## _name(_tid, _cpuid, _flags) - -/* Convenience macros to register a PMF service.*/ -/* - * This macro is used to register a PMF Service. It allocates PMF memory - * and defines default service-specific PMF functions. - */ -#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \ - PMF_ALLOCATE_TIMESTAMP_MEMORY(_name, _totalid) \ - PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags) \ - PMF_DEFINE_GET_TIMESTAMP(_name) - -/* - * This macro is used to register a PMF service, including an - * SMC interface to that service. - */ -#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)\ - PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \ - PMF_DEFINE_SERVICE_DESC(_name, PMF_ARM_TIF_IMPL_ID, \ - _svcid, _totalid, NULL, \ - pmf_get_timestamp_by_mpidr_ ## _name) - -/* - * This macro is used to register a PMF service that has an SMC interface - * but provides its own service-specific PMF functions. - */ -#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \ - _init, _getts) \ - PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid, \ - _init, _getts) - -#else - -#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) -#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags) -#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \ - _init, _getts) -#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) -#define PMF_DECLARE_GET_TIMESTAMP(_name) -#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) -#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval) -#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval) - -#endif /* ENABLE_PMF */ - /******************************************************************************* * Function & variable prototypes ******************************************************************************/ diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h index e6798a7ce..db38e556a 100644 --- a/include/lib/pmf/pmf_helpers.h +++ b/include/lib/pmf/pmf_helpers.h @@ -43,6 +43,108 @@ typedef struct pmf_svc_desc { pmf_svc_get_ts_t get_ts; } pmf_svc_desc_t; +#if ENABLE_PMF +/* + * Convenience macros for capturing time-stamp. + */ +#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) \ + void pmf_capture_timestamp_with_cache_maint_ ## _name( \ + unsigned int tid, \ + unsigned long long ts); \ + void pmf_capture_timestamp_ ## _name( \ + unsigned int tid, \ + unsigned long long ts); + +#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) \ + do { \ + unsigned long long ts = read_cntpct_el0(); \ + if (((_flags) & PMF_CACHE_MAINT) != 0U) \ + pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), ts);\ + else \ + pmf_capture_timestamp_ ## _name((_tid), ts); \ + } while (0) + +#define PMF_CAPTURE_AND_GET_TIMESTAMP(_name, _tid, _flags, _tsval) \ + do { \ + (_tsval) = read_cntpct_el0(); \ + CASSERT(sizeof(_tsval) == sizeof(unsigned long long), invalid_tsval_size);\ + if (((_flags) & PMF_CACHE_MAINT) != 0U) \ + pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_tsval));\ + else \ + pmf_capture_timestamp_ ## _name((_tid), (_tsval));\ + } while (0) + +#define PMF_WRITE_TIMESTAMP(_name, _tid, _flags, _wrval) \ + do { \ + CASSERT(sizeof(_wrval) == sizeof(unsigned long long), invalid_wrval_size);\ + if (((_flags) & PMF_CACHE_MAINT) != 0U) \ + pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_wrval));\ + else \ + pmf_capture_timestamp_ ## _name((_tid), (_wrval));\ + } while (0) + +/* + * Convenience macros for retrieving time-stamp. + */ +#define PMF_DECLARE_GET_TIMESTAMP(_name) \ + unsigned long long pmf_get_timestamp_by_index_ ## _name(\ + unsigned int tid, \ + unsigned int cpuid, \ + unsigned int flags); \ + unsigned long long pmf_get_timestamp_by_mpidr_ ## _name(\ + unsigned int tid, \ + u_register_t mpidr, \ + unsigned int flags); + +#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)\ + _tsval = pmf_get_timestamp_by_mpidr_ ## _name(_tid, _mpidr, _flags) + +#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)\ + _tsval = pmf_get_timestamp_by_index_ ## _name(_tid, _cpuid, _flags) + +/* Convenience macros to register a PMF service.*/ +/* + * This macro is used to register a PMF Service. It allocates PMF memory + * and defines default service-specific PMF functions. + */ +#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \ + PMF_ALLOCATE_TIMESTAMP_MEMORY(_name, _totalid) \ + PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags) \ + PMF_DEFINE_GET_TIMESTAMP(_name) + +/* + * This macro is used to register a PMF service, including an + * SMC interface to that service. + */ +#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)\ + PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \ + PMF_DEFINE_SERVICE_DESC(_name, PMF_ARM_TIF_IMPL_ID, \ + _svcid, _totalid, NULL, \ + pmf_get_timestamp_by_mpidr_ ## _name) + +/* + * This macro is used to register a PMF service that has an SMC interface + * but provides its own service-specific PMF functions. + */ +#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \ + _init, _getts) \ + PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid, \ + _init, _getts) + +#else + +#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) +#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags) +#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \ + _init, _getts) +#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) +#define PMF_DECLARE_GET_TIMESTAMP(_name) +#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) +#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval) +#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval) + +#endif /* ENABLE_PMF */ + /* * Convenience macro to allocate memory for a PMF service. * @@ -67,9 +169,6 @@ typedef struct pmf_svc_desc { * The extern declaration is there to satisfy MISRA C-2012 rule 8.4. */ #define PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags) \ - void pmf_capture_timestamp_ ## _name( \ - unsigned int tid, \ - unsigned long long ts); \ void pmf_capture_timestamp_ ## _name( \ unsigned int tid, \ unsigned long long ts) \ @@ -82,9 +181,6 @@ typedef struct pmf_svc_desc { if (((_flags) & PMF_DUMP_ENABLE) != 0) \ __pmf_dump_timestamp(tid, ts); \ } \ - void pmf_capture_timestamp_with_cache_maint_ ## _name( \ - unsigned int tid, \ - unsigned long long ts); \ void pmf_capture_timestamp_with_cache_maint_ ## _name( \ unsigned int tid, \ unsigned long long ts) \ @@ -104,8 +200,6 @@ typedef struct pmf_svc_desc { * The extern declaration is there to satisfy MISRA C-2012 rule 8.4. */ #define PMF_DEFINE_GET_TIMESTAMP(_name) \ - unsigned long long pmf_get_timestamp_by_index_ ## _name( \ - unsigned int tid, unsigned int cpuid, unsigned int flags);\ unsigned long long pmf_get_timestamp_by_index_ ## _name( \ unsigned int tid, unsigned int cpuid, unsigned int flags)\ { \ @@ -113,8 +207,6 @@ typedef struct pmf_svc_desc { uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ return __pmf_get_timestamp(base_addr, tid, cpuid, flags);\ } \ - unsigned long long pmf_get_timestamp_by_mpidr_ ## _name( \ - unsigned int tid, u_register_t mpidr, unsigned int flags);\ unsigned long long pmf_get_timestamp_by_mpidr_ ## _name( \ unsigned int tid, u_register_t mpidr, unsigned int flags)\ { \ diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c index 16bec7972..a756d5e40 100644 --- a/plat/common/plat_psci_common.c +++ b/plat/common/plat_psci_common.c @@ -31,6 +31,8 @@ #define PSCI_STAT_ID_EXIT_LOW_PWR 1 #define PSCI_STAT_TOTAL_IDS 2 +PMF_DECLARE_CAPTURE_TIMESTAMP(psci_svc) +PMF_DECLARE_GET_TIMESTAMP(psci_svc) PMF_REGISTER_SERVICE(psci_svc, PMF_PSCI_STAT_SVC_ID, PSCI_STAT_TOTAL_IDS, PMF_STORE_ENABLE) -- cgit v1.2.3 From f1f720199491353293e8e2ae691cb3188dfb2aba Mon Sep 17 00:00:00 2001 From: Olivier Deprez Date: Thu, 9 Jan 2020 10:45:52 +0100 Subject: plat: nvidia: remove spurious UTF-8 characters at top of platform files Signed-off-by: Olivier Deprez Change-Id: Iee7fb43990047b27972e99572ec4b3dc4e5c0423 --- plat/nvidia/tegra/include/drivers/security_engine.h | 4 ++-- plat/nvidia/tegra/soc/t194/drivers/se/se.c | 3 ++- plat/nvidia/tegra/soc/t194/drivers/se/se_private.h | 3 ++- plat/nvidia/tegra/soc/t210/drivers/se/se_private.h | 4 ++-- plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c | 4 ++-- 5 files changed, 10 insertions(+), 8 deletions(-) diff --git a/plat/nvidia/tegra/include/drivers/security_engine.h b/plat/nvidia/tegra/include/drivers/security_engine.h index 4ab2f9a23..8a249249b 100644 --- a/plat/nvidia/tegra/include/drivers/security_engine.h +++ b/plat/nvidia/tegra/include/drivers/security_engine.h @@ -1,5 +1,5 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. +/* + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c index 3df670c92..a9f461071 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/se/se.c +++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c @@ -1,4 +1,5 @@ -/* +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h index 7d531bb9d..f5c00456a 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h @@ -1,4 +1,5 @@ -/* +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/plat/nvidia/tegra/soc/t210/drivers/se/se_private.h b/plat/nvidia/tegra/soc/t210/drivers/se/se_private.h index be1f9cc39..352107d2c 100644 --- a/plat/nvidia/tegra/soc/t210/drivers/se/se_private.h +++ b/plat/nvidia/tegra/soc/t210/drivers/se/se_private.h @@ -1,5 +1,5 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. +/* + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c index 8d7dbf9e5..d5e049126 100644 --- a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c +++ b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c @@ -1,5 +1,5 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. +/* + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause -- cgit v1.2.3 From e073e0700e867512e2d83dafead106072fe8a806 Mon Sep 17 00:00:00 2001 From: Olivier Deprez Date: Mon, 23 Dec 2019 12:04:45 +0100 Subject: smccc: add get smc function id num macro Signed-off-by: Olivier Deprez Change-Id: I2953f0a6f35bc678402bc185640d1f328b065af5 --- include/lib/smccc.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/lib/smccc.h b/include/lib/smccc.h index dd3c578dc..5e13e6f0a 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,6 +41,8 @@ #define FUNCID_NUM_MASK U(0xffff) #define FUNCID_NUM_WIDTH U(16) +#define GET_SMC_NUM(id) (((id) >> FUNCID_NUM_SHIFT) & \ + FUNCID_NUM_MASK) #define GET_SMC_TYPE(id) (((id) >> FUNCID_TYPE_SHIFT) & \ FUNCID_TYPE_MASK) #define GET_SMC_CC(id) (((id) >> FUNCID_CC_SHIFT) & \ -- cgit v1.2.3 From 94f1c9593d3956c77d0cf17239185e50ba258bfa Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Fri, 10 Jan 2020 14:24:17 +0000 Subject: FVP: Remove re-definition of topology related build options This patch removes re-definition of the following FVP build options from plat\arm\board\fvp\fvp_def.h: 'FVP_CLUSTER_COUNT' 'FVP_MAX_CPUS_PER_CLUSTER' 'FVP_MAX_PE_PER_CPU' which are set in platform.mk. This fixes a potential problem when a build option set in platform.mk file can be re-defined in fvp_def.h header file used by other build component with a different makefile which does not set this option. Ref. GENFW-3505. Change-Id: I4288629920516acf2c239c7b733f92a0c5a812ff Signed-off-by: Alexei Fedorov --- plat/arm/board/fvp/fvp_def.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h index 1b9f84b00..347ba2e1e 100644 --- a/plat/arm/board/fvp/fvp_def.h +++ b/plat/arm/board/fvp/fvp_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,15 +10,15 @@ #include #ifndef FVP_CLUSTER_COUNT -#define FVP_CLUSTER_COUNT 2 +#error "FVP_CLUSTER_COUNT is not set in makefile" #endif #ifndef FVP_MAX_CPUS_PER_CLUSTER -#define FVP_MAX_CPUS_PER_CLUSTER 4 +#error "FVP_MAX_CPUS_PER_CLUSTER is not set in makefile" #endif #ifndef FVP_MAX_PE_PER_CPU -# define FVP_MAX_PE_PER_CPU 1 +#error "FVP_MAX_PE_PER_CPU is not set in makefile" #endif #define FVP_PRIMARY_CPU 0x0 -- cgit v1.2.3 From 5b33ad174a03a5ccdcd6321c64d69167361dc21a Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:23:18 -0600 Subject: Unify type of "cpu_idx" across PSCI module. NOTE for platform integrators: API `plat_psci_stat_get_residency()` third argument `last_cpu_idx` is changed from "signed int" to the "unsigned int" type. Issue / Trouble points 1. cpu_idx is used as mix of `unsigned int` and `signed int` in code with typecasting at some places leading to coverity issues. 2. Underlying platform API's return cpu_idx as `unsigned int` and comparison is performed with platform specific defines `PLAFORM_xxx` which is not consistent Misra Rule 10.4: The value of a complex expression of integer type may only be cast to a type that is narrower and of the same signedness as the underlying type of the expression. Based on above points, cpu_idx is kept as `unsigned int` to match the API's and low-level functions and platform defines are updated where ever required Signed-off-by: Deepika Bhavnani Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c --- docs/getting_started/porting-guide.rst | 2 +- drivers/arm/css/scp/css_pm_scmi.c | 5 +++-- include/export/lib/utils_def_exp.h | 4 +++- include/lib/psci/psci.h | 2 +- include/plat/arm/common/arm_def.h | 2 +- include/plat/common/platform.h | 2 +- lib/psci/psci_main.c | 13 +++++++----- lib/psci/psci_off.c | 4 ++-- lib/psci/psci_on.c | 24 ++++++++++++----------- lib/psci/psci_private.h | 6 +++--- lib/psci/psci_setup.c | 16 +++++++-------- lib/psci/psci_stat.c | 12 ++++++------ lib/psci/psci_suspend.c | 8 ++++---- plat/arm/board/a5ds/include/platform_def.h | 10 +++++----- plat/arm/board/corstone700/include/platform_def.h | 6 +++--- plat/arm/board/fvp/include/platform_def.h | 11 ++++++----- plat/arm/board/fvp_ve/fvp_ve_def.h | 10 +++++----- plat/arm/board/fvp_ve/include/platform_def.h | 6 +++--- plat/arm/board/juno/juno_def.h | 8 ++++---- plat/arm/board/rde1edge/include/platform_def.h | 6 +++--- plat/arm/board/rdn1edge/include/platform_def.h | 6 +++--- plat/arm/board/sgi575/include/platform_def.h | 8 ++++---- plat/arm/board/sgm775/include/platform_def.h | 6 +++--- plat/arm/css/sgm/include/sgm_base_platform_def.h | 6 +++--- plat/common/plat_psci_common.c | 6 +++--- 25 files changed, 99 insertions(+), 90 deletions(-) diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index 17fd54662..bb1471752 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -1999,7 +1999,7 @@ Function : plat_psci_stat_get_residency() [optional] :: - Argument : unsigned int, const psci_power_state_t *, int + Argument : unsigned int, const psci_power_state_t *, unsigned int Return : u_register_t This is an optional interface that is is invoked after resuming from a low power diff --git a/drivers/arm/css/scp/css_pm_scmi.c b/drivers/arm/css/scp/css_pm_scmi.c index 8dbefa16b..b945cda78 100644 --- a/drivers/arm/css/scp/css_pm_scmi.c +++ b/drivers/arm/css/scp/css_pm_scmi.c @@ -186,7 +186,7 @@ void css_scp_off(const struct psci_power_state *target_state) void css_scp_on(u_register_t mpidr) { unsigned int lvl = 0; - int ret, core_pos; + int core_pos, ret; uint32_t scmi_pwr_state = 0; for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) @@ -196,7 +196,8 @@ void css_scp_on(u_register_t mpidr) SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); core_pos = plat_core_pos_by_mpidr(mpidr); - assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT); + assert((core_pos >= 0) && + (((unsigned int)core_pos) < PLATFORM_CORE_COUNT)); ret = scmi_pwr_state_set(scmi_handle, plat_css_core_pos_to_scmi_dmn_id_map[core_pos], diff --git a/include/export/lib/utils_def_exp.h b/include/export/lib/utils_def_exp.h index 86c409ce1..d4a4a85dd 100644 --- a/include/export/lib/utils_def_exp.h +++ b/include/export/lib/utils_def_exp.h @@ -25,11 +25,13 @@ # define L(_x) (_x) # define LL(_x) (_x) #else -# define U(_x) (_x##U) +# define U_(_x) (_x##U) +# define U(_x) U_(_x) # define UL(_x) (_x##UL) # define ULL(_x) (_x##ULL) # define L(_x) (_x##L) # define LL(_x) (_x##LL) + #endif #endif /* ARM_TRUSTED_FIRMWARE_EXPORT_LIB_UTILS_DEF_EXP_H */ diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h index 7f7b7e3ff..b56e98b5f 100644 --- a/include/lib/psci/psci.h +++ b/include/lib/psci/psci.h @@ -20,7 +20,7 @@ #ifdef PLAT_NUM_PWR_DOMAINS #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS #else -#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT) +#define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT) #endif #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 72e2e8e96..b419c853e 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -21,7 +21,7 @@ /* Special value used to verify platform parameters from BL2 to BL31 */ #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) -#define ARM_SYSTEM_COUNT 1 +#define ARM_SYSTEM_COUNT U(1) #define ARM_CACHE_WRITEBACK_SHIFT 6 diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index 9efb2fd52..332cfca8d 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -237,7 +237,7 @@ void plat_psci_stat_accounting_start(const psci_power_state_t *state_info); void plat_psci_stat_accounting_stop(const psci_power_state_t *state_info); u_register_t plat_psci_stat_get_residency(unsigned int lvl, const psci_power_state_t *state_info, - int last_cpu_idx); + unsigned int last_cpu_idx); plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, const plat_local_state_t *states, unsigned int ncpu); diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c index 5c0e952a9..52a8b8a18 100644 --- a/lib/psci/psci_main.c +++ b/lib/psci/psci_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -219,16 +219,19 @@ int psci_cpu_off(void) int psci_affinity_info(u_register_t target_affinity, unsigned int lowest_affinity_level) { - int target_idx; + int ret; + unsigned int target_idx; /* We dont support level higher than PSCI_CPU_PWR_LVL */ if (lowest_affinity_level > PSCI_CPU_PWR_LVL) return PSCI_E_INVALID_PARAMS; /* Calculate the cpu index of the target */ - target_idx = plat_core_pos_by_mpidr(target_affinity); - if (target_idx == -1) + ret = plat_core_pos_by_mpidr(target_affinity); + if (ret == -1) { return PSCI_E_INVALID_PARAMS; + } + target_idx = (unsigned int)ret; /* * Generic management: @@ -245,7 +248,7 @@ int psci_affinity_info(u_register_t target_affinity, * target CPUs shutdown was not seen by the current CPU's cluster. And * so the cache may contain stale data for the target CPU. */ - flush_cpu_data_by_index((unsigned int)target_idx, + flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); return psci_get_aff_info_state_by_idx(target_idx); diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c index e8cd8feb0..54470457a 100644 --- a/lib/psci/psci_off.c +++ b/lib/psci/psci_off.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -43,7 +43,7 @@ static void psci_set_power_off_state(psci_power_state_t *state_info) int psci_do_cpu_off(unsigned int end_pwrlvl) { int rc = PSCI_E_SUCCESS; - int idx = (int) plat_my_core_pos(); + unsigned int idx = plat_my_core_pos(); psci_power_state_t state_info; unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c index 470b4f33e..dd48e105d 100644 --- a/lib/psci/psci_on.c +++ b/lib/psci/psci_on.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,12 +20,12 @@ /* * Helper functions for the CPU level spinlocks */ -static inline void psci_spin_lock_cpu(int idx) +static inline void psci_spin_lock_cpu(unsigned int idx) { spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock); } -static inline void psci_spin_unlock_cpu(int idx) +static inline void psci_spin_unlock_cpu(unsigned int idx) { spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock); } @@ -61,12 +61,14 @@ int psci_cpu_on_start(u_register_t target_cpu, { int rc; aff_info_state_t target_aff_state; - int target_idx = plat_core_pos_by_mpidr(target_cpu); + int ret = plat_core_pos_by_mpidr(target_cpu); + unsigned int target_idx = (unsigned int)ret; /* Calling function must supply valid input arguments */ - assert(target_idx >= 0); + assert(ret >= 0); assert(ep != NULL); + /* * This function must only be called on platforms where the * CPU_ON platform hooks have been implemented. @@ -93,7 +95,7 @@ int psci_cpu_on_start(u_register_t target_cpu, * target CPUs shutdown was not seen by the current CPU's cluster. And * so the cache may contain stale data for the target CPU. */ - flush_cpu_data_by_index((unsigned int)target_idx, + flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); if (rc != PSCI_E_SUCCESS) @@ -113,7 +115,7 @@ int psci_cpu_on_start(u_register_t target_cpu, * turned OFF. */ psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); - flush_cpu_data_by_index((unsigned int)target_idx, + flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); /* @@ -126,7 +128,7 @@ int psci_cpu_on_start(u_register_t target_cpu, if (target_aff_state != AFF_STATE_ON_PENDING) { assert(target_aff_state == AFF_STATE_OFF); psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); - flush_cpu_data_by_index((unsigned int)target_idx, + flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); assert(psci_get_aff_info_state_by_idx(target_idx) == @@ -146,11 +148,11 @@ int psci_cpu_on_start(u_register_t target_cpu, if (rc == PSCI_E_SUCCESS) /* Store the re-entry information for the non-secure world. */ - cm_init_context_by_index((unsigned int)target_idx, ep); + cm_init_context_by_index(target_idx, ep); else { /* Restore the state on error. */ psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); - flush_cpu_data_by_index((unsigned int)target_idx, + flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); } @@ -164,7 +166,7 @@ exit: * are called by the common finisher routine in psci_common.c. The `state_info` * is the psci_power_state from which this CPU has woken up from. ******************************************************************************/ -void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info) +void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info) { /* * Plat. management: Perform the platform specific actions diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h index 0f25e6563..e2dcfa8b1 100644 --- a/lib/psci/psci_private.h +++ b/lib/psci/psci_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -301,7 +301,7 @@ void prepare_cpu_pwr_dwn(unsigned int power_level); int psci_cpu_on_start(u_register_t target_cpu, const entry_point_info_t *ep); -void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info); +void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info); /* Private exported functions from psci_off.c */ int psci_do_cpu_off(unsigned int end_pwrlvl); @@ -312,7 +312,7 @@ void psci_cpu_suspend_start(const entry_point_info_t *ep, psci_power_state_t *state_info, unsigned int is_power_down_state); -void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info); +void psci_cpu_suspend_finish(unsigned int cpu_idx, const psci_power_state_t *state_info); /* Private exported functions from psci_helpers.S */ void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c index becb54709..d1ec99808 100644 --- a/lib/psci/psci_setup.c +++ b/lib/psci/psci_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -91,9 +91,9 @@ static void __init psci_update_pwrlvl_limits(void) for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { psci_get_parent_pwr_domain_nodes(cpu_idx, - (unsigned int)PLAT_MAX_PWR_LVL, + PLAT_MAX_PWR_LVL, temp_index); - for (j = (int) PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { + for (j = (int)PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { if (temp_index[j] != nodes_idx[j]) { nodes_idx[j] = temp_index[j]; psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx @@ -115,8 +115,8 @@ static unsigned int __init populate_power_domain_tree(const unsigned char { unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl; unsigned int node_index = 0U, num_children; - int parent_node_index = 0; - int level = (int) PLAT_MAX_PWR_LVL; + unsigned int parent_node_index = 0U; + int level = (int)PLAT_MAX_PWR_LVL; /* * For each level the inputs are: @@ -145,8 +145,8 @@ static unsigned int __init populate_power_domain_tree(const unsigned char for (j = node_index; j < (node_index + num_children); j++) psci_init_pwr_domain_node((unsigned char)j, - parent_node_index - 1, - (unsigned char)level); + parent_node_index - 1U, + (unsigned char)level); node_index = j; num_nodes_at_next_lvl += num_children; @@ -162,7 +162,7 @@ static unsigned int __init populate_power_domain_tree(const unsigned char } /* Validate the sanity of array exported by the platform */ - assert(j <= (unsigned int)PLATFORM_CORE_COUNT); + assert(j <= PLATFORM_CORE_COUNT); return j; } diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c index 772a1840a..ecef95ab6 100644 --- a/lib/psci/psci_stat.c +++ b/lib/psci/psci_stat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,7 +28,7 @@ typedef struct psci_stat { * that goes to power down in non cpu power domains. */ static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = { - [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS - 1] = -1}; + [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS - 1U] = -1}; /* * Following are used to store PSCI STAT values for @@ -77,7 +77,7 @@ void psci_stats_update_pwr_down(unsigned int end_pwrlvl, const psci_power_state_t *state_info) { unsigned int lvl, parent_idx; - int cpu_idx = (int) plat_my_core_pos(); + unsigned int cpu_idx = plat_my_core_pos(); assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); assert(state_info != NULL); @@ -94,7 +94,7 @@ void psci_stats_update_pwr_down(unsigned int end_pwrlvl, * The power domain is entering a low power state, so this is * the last CPU for this power domain */ - last_cpu_in_non_cpu_pd[parent_idx] = cpu_idx; + last_cpu_in_non_cpu_pd[parent_idx] = (int)cpu_idx; parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; } @@ -110,7 +110,7 @@ void psci_stats_update_pwr_up(unsigned int end_pwrlvl, const psci_power_state_t *state_info) { unsigned int lvl, parent_idx; - int cpu_idx = (int) plat_my_core_pos(); + unsigned int cpu_idx = plat_my_core_pos(); int stat_idx; plat_local_state_t local_state; u_register_t residency; @@ -150,7 +150,7 @@ void psci_stats_update_pwr_up(unsigned int end_pwrlvl, /* Call into platform interface to calculate residency. */ residency = plat_psci_stat_get_residency(lvl, state_info, - last_cpu_in_non_cpu_pd[parent_idx]); + (unsigned int)last_cpu_in_non_cpu_pd[parent_idx]); /* Initialize back to reset value */ last_cpu_in_non_cpu_pd[parent_idx] = -1; diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c index 98dd2d62c..da9f328a5 100644 --- a/lib/psci/psci_suspend.c +++ b/lib/psci/psci_suspend.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,7 +25,7 @@ * This function does generic and platform specific operations after a wake-up * from standby/retention states at multiple power levels. ******************************************************************************/ -static void psci_suspend_to_standby_finisher(int cpu_idx, +static void psci_suspend_to_standby_finisher(unsigned int cpu_idx, unsigned int end_pwrlvl) { unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; @@ -157,7 +157,7 @@ void psci_cpu_suspend_start(const entry_point_info_t *ep, unsigned int is_power_down_state) { int skip_wfi = 0; - int idx = (int) plat_my_core_pos(); + unsigned int idx = plat_my_core_pos(); unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; /* @@ -276,7 +276,7 @@ exit: * are called by the common finisher routine in psci_common.c. The `state_info` * is the psci_power_state from which this CPU has woken up from. ******************************************************************************/ -void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info) +void psci_cpu_suspend_finish(unsigned int cpu_idx, const psci_power_state_t *state_info) { unsigned int counter_freq; unsigned int max_off_lvl; diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h index d200af686..d30bfc877 100644 --- a/plat/arm/board/a5ds/include/platform_def.h +++ b/plat/arm/board/a5ds/include/platform_def.h @@ -89,15 +89,15 @@ #define A5DS_IRQ_SEC_SYS_TIMER 57 /* Default cluster count for A5DS */ -#define A5DS_CLUSTER_COUNT 1 +#define A5DS_CLUSTER_COUNT U(1) /* Default number of CPUs per cluster on A5DS */ -#define A5DS_MAX_CPUS_PER_CLUSTER 4 +#define A5DS_MAX_CPUS_PER_CLUSTER U(4) /* Default number of threads per CPU on A5DS */ -#define A5DS_MAX_PE_PER_CPU 1 +#define A5DS_MAX_PE_PER_CPU U(1) -#define A5DS_CORE_COUNT 4 +#define A5DS_CORE_COUNT U(4) #define A5DS_PRIMARY_CPU 0x0 @@ -231,7 +231,7 @@ /* Required platform porting definitions */ #define PLATFORM_CORE_COUNT A5DS_CORE_COUNT #define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \ - PLATFORM_CORE_COUNT) + 1 + PLATFORM_CORE_COUNT) + U(1) #define PLAT_MAX_PWR_LVL 2 diff --git a/plat/arm/board/corstone700/include/platform_def.h b/plat/arm/board/corstone700/include/platform_def.h index de99b06ad..8dff3ec3f 100644 --- a/plat/arm/board/corstone700/include/platform_def.h +++ b/plat/arm/board/corstone700/include/platform_def.h @@ -14,9 +14,9 @@ #include /* Core/Cluster/Thread counts for Corstone700 */ -#define CORSTONE700_CLUSTER_COUNT 1 -#define CORSTONE700_MAX_CPUS_PER_CLUSTER 4 -#define CORSTONE700_MAX_PE_PER_CPU 1 +#define CORSTONE700_CLUSTER_COUNT U(1) +#define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4) +#define CORSTONE700_MAX_PE_PER_CPU U(1) #define CORSTONE700_CORE_COUNT (CORSTONE700_CLUSTER_COUNT * \ CORSTONE700_MAX_CPUS_PER_CLUSTER * \ CORSTONE700_MAX_PE_PER_CPU) diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index f1afe36c4..c2b7b98d4 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -17,11 +17,12 @@ #include "../fvp_def.h" /* Required platform porting definitions */ -#define PLATFORM_CORE_COUNT \ - (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) +#define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ + U(FVP_MAX_CPUS_PER_CLUSTER) * \ + U(FVP_MAX_PE_PER_CPU)) -#define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ - PLATFORM_CORE_COUNT) + 1 +#define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ + PLATFORM_CORE_COUNT + U(1)) #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 @@ -32,7 +33,7 @@ /* * Required ARM standard platform porting definitions */ -#define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT +#define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ diff --git a/plat/arm/board/fvp_ve/fvp_ve_def.h b/plat/arm/board/fvp_ve/fvp_ve_def.h index 565753ae7..98de5f66e 100644 --- a/plat/arm/board/fvp_ve/fvp_ve_def.h +++ b/plat/arm/board/fvp_ve/fvp_ve_def.h @@ -10,17 +10,17 @@ #include /* Default cluster count for FVP VE */ -#define FVP_VE_CLUSTER_COUNT 1 +#define FVP_VE_CLUSTER_COUNT U(1) /* Default number of CPUs per cluster on FVP VE */ -#define FVP_VE_MAX_CPUS_PER_CLUSTER 1 +#define FVP_VE_MAX_CPUS_PER_CLUSTER U(1) /* Default number of threads per CPU on FVP VE */ -#define FVP_VE_MAX_PE_PER_CPU 1 +#define FVP_VE_MAX_PE_PER_CPU U(1) -#define FVP_VE_CORE_COUNT 1 +#define FVP_VE_CORE_COUNT U(1) -#define FVP_VE_PRIMARY_CPU 0x0 +#define FVP_VE_PRIMARY_CPU 0x0 /******************************************************************************* * FVP memory map related constants diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h index 4e575e1ab..1b07a9b42 100644 --- a/plat/arm/board/fvp_ve/include/platform_def.h +++ b/plat/arm/board/fvp_ve/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -211,9 +211,9 @@ #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) /* Required platform porting definitions */ -#define PLATFORM_CORE_COUNT 1 +#define PLATFORM_CORE_COUNT FVP_VE_CLUSTER_COUNT #define PLAT_NUM_PWR_DOMAINS ((FVP_VE_CLUSTER_COUNT + \ - PLATFORM_CORE_COUNT) + 1) + PLATFORM_CORE_COUNT) + U(1)) #define PLAT_MAX_PWR_LVL 2 diff --git a/plat/arm/board/juno/juno_def.h b/plat/arm/board/juno/juno_def.h index 7a8bedf5a..3b34a9f6a 100644 --- a/plat/arm/board/juno/juno_def.h +++ b/plat/arm/board/juno/juno_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,9 +32,9 @@ /******************************************************************************* * Juno topology related constants ******************************************************************************/ -#define JUNO_CLUSTER_COUNT 2 -#define JUNO_CLUSTER0_CORE_COUNT 2 -#define JUNO_CLUSTER1_CORE_COUNT 4 +#define JUNO_CLUSTER_COUNT U(2) +#define JUNO_CLUSTER0_CORE_COUNT U(2) +#define JUNO_CLUSTER1_CORE_COUNT U(4) /******************************************************************************* * TZC-400 related constants diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h index 50b04f049..2be3f8852 100644 --- a/plat/arm/board/rde1edge/include/platform_def.h +++ b/plat/arm/board/rde1edge/include/platform_def.h @@ -11,9 +11,9 @@ #include -#define PLAT_ARM_CLUSTER_COUNT 2 -#define CSS_SGI_MAX_CPUS_PER_CLUSTER 8 -#define CSS_SGI_MAX_PE_PER_CPU 2 +#define PLAT_ARM_CLUSTER_COUNT U(2) +#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(8) +#define CSS_SGI_MAX_PE_PER_CPU U(2) #define PLAT_CSS_MHU_BASE UL(0x45400000) #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h index 580ab8e6f..c635faa44 100644 --- a/plat/arm/board/rdn1edge/include/platform_def.h +++ b/plat/arm/board/rdn1edge/include/platform_def.h @@ -11,9 +11,9 @@ #include -#define PLAT_ARM_CLUSTER_COUNT 2 -#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4 -#define CSS_SGI_MAX_PE_PER_CPU 1 +#define PLAT_ARM_CLUSTER_COUNT U(2) +#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4) +#define CSS_SGI_MAX_PE_PER_CPU U(1) #define PLAT_CSS_MHU_BASE UL(0x45400000) #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h index f00146f99..fd59e5277 100644 --- a/plat/arm/board/sgi575/include/platform_def.h +++ b/plat/arm/board/sgi575/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,9 +11,9 @@ #include -#define PLAT_ARM_CLUSTER_COUNT 2 -#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4 -#define CSS_SGI_MAX_PE_PER_CPU 1 +#define PLAT_ARM_CLUSTER_COUNT U(2) +#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4) +#define CSS_SGI_MAX_PE_PER_CPU U(1) #define PLAT_CSS_MHU_BASE UL(0x45000000) #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE diff --git a/plat/arm/board/sgm775/include/platform_def.h b/plat/arm/board/sgm775/include/platform_def.h index 27d1b3304..d165ff9ed 100644 --- a/plat/arm/board/sgm775/include/platform_def.h +++ b/plat/arm/board/sgm775/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +9,8 @@ #include -#define PLAT_MAX_CPUS_PER_CLUSTER 8 -#define PLAT_MAX_PE_PER_CPU 1 +#define PLAT_MAX_CPUS_PER_CLUSTER U(8) +#define PLAT_MAX_PE_PER_CPU U(1) /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h index f349c196d..24bbed513 100644 --- a/plat/arm/css/sgm/include/sgm_base_platform_def.h +++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,8 +17,8 @@ #include /* CPU topology */ -#define PLAT_ARM_CLUSTER_COUNT 1 -#define PLAT_ARM_CLUSTER_CORE_COUNT 8 +#define PLAT_ARM_CLUSTER_COUNT U(1) +#define PLAT_ARM_CLUSTER_CORE_COUNT U(8) #define PLATFORM_CORE_COUNT PLAT_ARM_CLUSTER_CORE_COUNT #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c index 16bec7972..27ec81e15 100644 --- a/plat/common/plat_psci_common.c +++ b/plat/common/plat_psci_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -92,7 +92,7 @@ void plat_psci_stat_accounting_stop( */ u_register_t plat_psci_stat_get_residency(unsigned int lvl, const psci_power_state_t *state_info, - int last_cpu_idx) + unsigned int last_cpu_idx) { plat_local_state_t state; unsigned long long pwrup_ts = 0, pwrdn_ts = 0; @@ -103,7 +103,7 @@ u_register_t plat_psci_stat_get_residency(unsigned int lvl, assert(last_cpu_idx <= PLATFORM_CORE_COUNT); if (lvl == PSCI_CPU_PWR_LVL) - assert((unsigned int)last_cpu_idx == plat_my_core_pos()); + assert(last_cpu_idx == plat_my_core_pos()); /* * If power down is requested, then timestamp capture will -- cgit v1.2.3 From 70cb0bff7d42bd9e09dddef3c2fc6e3b385c6e5a Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 16 Apr 2019 11:35:19 +0200 Subject: io: change seek offset to signed long long IO seek offset can be set to values above UINT32_MAX, this change changes the seek offset argument from 'ssize_t' to 'signed long long'. Fixing platform seek functions to match the new interface update. Change-Id: I25de83b3b7abe5f52a7b0fee36f71e60cac9cfcb Signed-off-by: Yann Gautier Signed-off-by: Etienne Carriere Signed-off-by: Lionel Debieve --- drivers/intel/soc/stratix10/io/s10_memmap_qspi.c | 18 +++---- drivers/io/io_block.c | 60 ++++++++++++------------ drivers/io/io_fip.c | 6 ++- drivers/io/io_memmap.c | 30 +++++++----- drivers/io/io_semihosting.c | 6 +-- drivers/io/io_storage.c | 2 +- drivers/renesas/rcar/io/io_emmcdrv.c | 20 ++++---- drivers/renesas/rcar/io/io_memdrv.c | 19 ++++---- drivers/st/io/io_mmc.c | 10 ++-- include/drivers/io/io_driver.h | 2 +- include/drivers/io/io_storage.h | 2 +- 11 files changed, 94 insertions(+), 81 deletions(-) diff --git a/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c b/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c index a0fc034d8..dcd199148 100644 --- a/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c +++ b/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c @@ -26,9 +26,9 @@ typedef struct { * valid. */ int in_use; - uintptr_t base; - size_t file_pos; - size_t size; + uintptr_t base; + unsigned long long file_pos; + unsigned long long size; } file_state_t; static file_state_t current_file = {0}; @@ -44,7 +44,7 @@ static int memmap_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity); static int memmap_block_seek(io_entity_t *entity, int mode, - ssize_t offset); + signed long long offset); static int memmap_block_len(io_entity_t *entity, size_t *length); static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read); @@ -131,7 +131,8 @@ static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, /* Seek to a particular file offset on the memmap device */ -static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset) +static int memmap_block_seek(io_entity_t *entity, int mode, + signed long long offset) { int result = -ENOENT; file_state_t *fp; @@ -143,7 +144,8 @@ static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset) fp = (file_state_t *) entity->info; /* Assert that new file position is valid */ - assert((offset >= 0) && (offset < fp->size)); + assert((offset >= 0) && + ((unsigned long long)offset < fp->size)); /* Reset file position */ fp->file_pos = offset; @@ -171,7 +173,7 @@ static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read) { file_state_t *fp; - size_t pos_after; + unsigned long long pos_after; assert(entity != NULL); assert(length_read != NULL); @@ -198,7 +200,7 @@ static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer, size_t length, size_t *length_written) { file_state_t *fp; - size_t pos_after; + unsigned long long pos_after; assert(entity != NULL); assert(length_written != NULL); diff --git a/drivers/io/io_block.c b/drivers/io/io_block.c index f190a4307..5d45c2f17 100644 --- a/drivers/io/io_block.c +++ b/drivers/io/io_block.c @@ -19,17 +19,17 @@ typedef struct { io_block_dev_spec_t *dev_spec; uintptr_t base; - size_t file_pos; - size_t size; + unsigned long long file_pos; + unsigned long long size; } block_dev_state_t; -#define is_power_of_2(x) ((x != 0) && ((x & (x - 1)) == 0)) +#define is_power_of_2(x) (((x) != 0U) && (((x) & ((x) - 1U)) == 0U)) io_type_t device_type_block(void); static int block_open(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity); -static int block_seek(io_entity_t *entity, int mode, ssize_t offset); +static int block_seek(io_entity_t *entity, int mode, signed long long offset); static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read); static int block_write(io_entity_t *entity, const uintptr_t buffer, @@ -148,21 +148,21 @@ static int block_open(io_dev_info_t *dev_info, const uintptr_t spec, } /* parameter offset is relative address at here */ -static int block_seek(io_entity_t *entity, int mode, ssize_t offset) +static int block_seek(io_entity_t *entity, int mode, signed long long offset) { block_dev_state_t *cur; assert(entity->info != (uintptr_t)NULL); cur = (block_dev_state_t *)entity->info; - assert((offset >= 0) && (offset < cur->size)); + assert((offset >= 0) && ((unsigned long long)offset < cur->size)); switch (mode) { case IO_SEEK_SET: - cur->file_pos = offset; + cur->file_pos = (unsigned long long)offset; break; case IO_SEEK_CUR: - cur->file_pos += offset; + cur->file_pos += (unsigned long long)offset; break; default: return -EINVAL; @@ -270,7 +270,7 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length, buf = &(cur->dev_spec->buffer); block_size = cur->dev_spec->block_size; assert((length <= cur->size) && - (length > 0) && + (length > 0U) && (ops->read != 0)); /* @@ -279,7 +279,7 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length, * on the low level driver. */ count = 0; - for (left = length; left > 0; left -= nbytes) { + for (left = length; left > 0U; left -= nbytes) { /* * We must only request operations aligned to the block * size. Therefore if file_pos is not block-aligned, @@ -288,7 +288,7 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length, * similarly, the number of bytes requested must be a * block size multiple */ - skip = cur->file_pos & (block_size - 1); + skip = cur->file_pos & (block_size - 1U); /* * Calculate the block number containing file_pos @@ -296,7 +296,7 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length, */ lba = (cur->file_pos + cur->base) / block_size; - if (skip + left > buf->length) { + if ((skip + left) > buf->length) { /* * The underlying read buffer is too small to * read all the required data - limit to just @@ -311,7 +311,8 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length, * block size. */ request = skip + left; - request = (request + (block_size - 1)) & ~(block_size - 1); + request = (request + (block_size - 1U)) & + ~(block_size - 1U); } request = ops->read(lba, buf->offset, request); @@ -330,7 +331,7 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length, * the read data when copying to the user buffer. */ nbytes = request - skip; - padding = (nbytes > left) ? nbytes - left : 0; + padding = (nbytes > left) ? nbytes - left : 0U; nbytes -= padding; memcpy((void *)(buffer + count), @@ -381,7 +382,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer, buf = &(cur->dev_spec->buffer); block_size = cur->dev_spec->block_size; assert((length <= cur->size) && - (length > 0) && + (length > 0U) && (ops->read != 0) && (ops->write != 0)); @@ -391,7 +392,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer, * on the low level driver. */ count = 0; - for (left = length; left > 0; left -= nbytes) { + for (left = length; left > 0U; left -= nbytes) { /* * We must only request operations aligned to the block * size. Therefore if file_pos is not block-aligned, @@ -400,7 +401,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer, * similarly, the number of bytes requested must be a * block size multiple */ - skip = cur->file_pos & (block_size - 1); + skip = cur->file_pos & (block_size - 1U); /* * Calculate the block number containing file_pos @@ -408,7 +409,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer, */ lba = (cur->file_pos + cur->base) / block_size; - if (skip + left > buf->length) { + if ((skip + left) > buf->length) { /* * The underlying read buffer is too small to * read all the required data - limit to just @@ -423,7 +424,8 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer, * block size. */ request = skip + left; - request = (request + (block_size - 1)) & ~(block_size - 1); + request = (request + (block_size - 1U)) & + ~(block_size - 1U); } /* @@ -432,7 +434,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer, * of the current request. */ nbytes = request - skip; - padding = (nbytes > left) ? nbytes - left : 0; + padding = (nbytes > left) ? nbytes - left : 0U; nbytes -= padding; /* @@ -440,14 +442,14 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer, * some content and it means that we have to read before * writing */ - if (skip > 0 || padding > 0) { + if ((skip > 0U) || (padding > 0U)) { request = ops->read(lba, buf->offset, request); /* * The read may return size less than * requested. Round down to the nearest block * boundary */ - request &= ~(block_size-1); + request &= ~(block_size - 1U); if (request <= skip) { /* * We couldn't read enough bytes to jump over @@ -458,7 +460,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer, return -EIO; } nbytes = request - skip; - padding = (nbytes > left) ? nbytes - left : 0; + padding = (nbytes > left) ? nbytes - left : 0U; nbytes -= padding; } @@ -477,7 +479,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer, * buffer */ nbytes = request - skip; - padding = (nbytes > left) ? nbytes - left : 0; + padding = (nbytes > left) ? nbytes - left : 0U; nbytes -= padding; cur->file_pos += nbytes; @@ -505,7 +507,7 @@ static int block_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info) assert(dev_info != NULL); result = allocate_dev_info(&info); - if (result) + if (result != 0) return -ENOENT; cur = (block_dev_state_t *)info->info; @@ -513,10 +515,10 @@ static int block_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info) cur->dev_spec = (io_block_dev_spec_t *)dev_spec; buffer = &(cur->dev_spec->buffer); block_size = cur->dev_spec->block_size; - assert((block_size > 0) && - (is_power_of_2(block_size) != 0) && - ((buffer->offset % block_size) == 0) && - ((buffer->length % block_size) == 0)); + assert((block_size > 0U) && + (is_power_of_2(block_size) != 0U) && + ((buffer->offset % block_size) == 0U) && + ((buffer->length % block_size) == 0U)); *dev_info = info; /* cast away const */ (void)block_size; diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c index 544b37dbe..5d49fffaa 100644 --- a/drivers/io/io_fip.c +++ b/drivers/io/io_fip.c @@ -304,7 +304,8 @@ static int fip_file_open(io_dev_info_t *dev_info, const uintptr_t spec, } /* Seek past the FIP header into the Table of Contents */ - result = io_seek(backend_handle, IO_SEEK_SET, sizeof(fip_toc_header_t)); + result = io_seek(backend_handle, IO_SEEK_SET, + (signed long long)sizeof(fip_toc_header_t)); if (result != 0) { WARN("fip_file_open: failed to seek\n"); result = -ENOENT; @@ -389,7 +390,8 @@ static int fip_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, /* Seek to the position in the FIP where the payload lives */ file_offset = fp->entry.offset_address + fp->file_pos; - result = io_seek(backend_handle, IO_SEEK_SET, file_offset); + result = io_seek(backend_handle, IO_SEEK_SET, + (signed long long)file_offset); if (result != 0) { WARN("fip_file_read: failed to seek\n"); result = -ENOENT; diff --git a/drivers/io/io_memmap.c b/drivers/io/io_memmap.c index 96590b6c0..eed50cc08 100644 --- a/drivers/io/io_memmap.c +++ b/drivers/io/io_memmap.c @@ -23,10 +23,10 @@ typedef struct { /* Use the 'in_use' flag as any value for base and file_pos could be * valid. */ - int in_use; - uintptr_t base; - size_t file_pos; - size_t size; + int in_use; + uintptr_t base; + unsigned long long file_pos; + unsigned long long size; } file_state_t; static file_state_t current_file = {0}; @@ -42,7 +42,7 @@ static int memmap_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity); static int memmap_block_seek(io_entity_t *entity, int mode, - ssize_t offset); + signed long long offset); static int memmap_block_len(io_entity_t *entity, size_t *length); static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read); @@ -129,7 +129,8 @@ static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, /* Seek to a particular file offset on the memmap device */ -static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset) +static int memmap_block_seek(io_entity_t *entity, int mode, + signed long long offset) { int result = -ENOENT; file_state_t *fp; @@ -141,10 +142,11 @@ static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset) fp = (file_state_t *) entity->info; /* Assert that new file position is valid */ - assert((offset >= 0) && (offset < fp->size)); + assert((offset >= 0) && + ((unsigned long long)offset < fp->size)); /* Reset file position */ - fp->file_pos = offset; + fp->file_pos = (unsigned long long)offset; result = 0; } @@ -158,7 +160,7 @@ static int memmap_block_len(io_entity_t *entity, size_t *length) assert(entity != NULL); assert(length != NULL); - *length = ((file_state_t *)entity->info)->size; + *length = (size_t)((file_state_t *)entity->info)->size; return 0; } @@ -169,7 +171,7 @@ static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read) { file_state_t *fp; - size_t pos_after; + unsigned long long pos_after; assert(entity != NULL); assert(length_read != NULL); @@ -180,7 +182,8 @@ static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, pos_after = fp->file_pos + length; assert((pos_after >= fp->file_pos) && (pos_after <= fp->size)); - memcpy((void *)buffer, (void *)(fp->base + fp->file_pos), length); + memcpy((void *)buffer, + (void *)((uintptr_t)(fp->base + fp->file_pos)), length); *length_read = length; @@ -196,7 +199,7 @@ static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer, size_t length, size_t *length_written) { file_state_t *fp; - size_t pos_after; + unsigned long long pos_after; assert(entity != NULL); assert(length_written != NULL); @@ -207,7 +210,8 @@ static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer, pos_after = fp->file_pos + length; assert((pos_after >= fp->file_pos) && (pos_after <= fp->size)); - memcpy((void *)(fp->base + fp->file_pos), (void *)buffer, length); + memcpy((void *)((uintptr_t)(fp->base + fp->file_pos)), + (void *)buffer, length); *length_written = length; diff --git a/drivers/io/io_semihosting.c b/drivers/io/io_semihosting.c index 23d09c118..4ceddc6cc 100644 --- a/drivers/io/io_semihosting.c +++ b/drivers/io/io_semihosting.c @@ -25,7 +25,7 @@ static io_type_t device_type_sh(void) static int sh_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); static int sh_file_open(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity); -static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset); +static int sh_file_seek(io_entity_t *entity, int mode, signed long long offset); static int sh_file_len(io_entity_t *entity, size_t *length); static int sh_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read); @@ -90,7 +90,7 @@ static int sh_file_open(io_dev_info_t *dev_info __unused, /* Seek to a particular file offset on the semi-hosting device */ -static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset) +static int sh_file_seek(io_entity_t *entity, int mode, signed long long offset) { long file_handle, sh_result; @@ -98,7 +98,7 @@ static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset) file_handle = (long)entity->info; - sh_result = semihosting_file_seek(file_handle, offset); + sh_result = semihosting_file_seek(file_handle, (ssize_t)offset); return (sh_result == 0) ? 0 : -ENOENT; } diff --git a/drivers/io/io_storage.c b/drivers/io/io_storage.c index e444f87f7..b8c1d6479 100644 --- a/drivers/io/io_storage.c +++ b/drivers/io/io_storage.c @@ -237,7 +237,7 @@ int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle) /* Seek to a specific position in an IO entity */ -int io_seek(uintptr_t handle, io_seek_mode_t mode, ssize_t offset) +int io_seek(uintptr_t handle, io_seek_mode_t mode, signed long long offset) { int result = -ENODEV; assert(is_valid_entity(handle) && is_valid_seek_mode(mode)); diff --git a/drivers/renesas/rcar/io/io_emmcdrv.c b/drivers/renesas/rcar/io/io_emmcdrv.c index 4b464fb3e..84240d260 100644 --- a/drivers/renesas/rcar/io/io_emmcdrv.c +++ b/drivers/renesas/rcar/io/io_emmcdrv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,7 +25,7 @@ static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info); typedef struct { uint32_t in_use; uintptr_t base; - ssize_t file_pos; + signed long long file_pos; EMMC_PARTITION_ID partition; } file_state_t; @@ -39,7 +39,7 @@ static io_type_t device_type_emmcdrv(void) } static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode, - ssize_t offset) + signed long long offset) { if (mode != IO_SEEK_SET) return IO_FAIL; @@ -59,12 +59,12 @@ static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer, sector_add = current_file.file_pos >> EMMC_SECTOR_SIZE_SHIFT; sector_num = (length + EMMC_SECTOR_SIZE - 1U) >> EMMC_SECTOR_SIZE_SHIFT; - NOTICE("BL2: Load dst=0x%lx src=(p:%d)0x%lx(%d) len=0x%lx(%d)\n", + NOTICE("BL2: Load dst=0x%lx src=(p:%d)0x%llx(%d) len=0x%lx(%d)\n", buffer, current_file.partition, current_file.file_pos, sector_add, length, sector_num); - if (buffer + length - 1 <= UINT32_MAX) + if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX) emmc_dma = LOADIMAGE_FLAGS_DMA_ENABLE; if (emmc_read_sector((uint32_t *) buffer, sector_add, sector_num, @@ -72,7 +72,7 @@ static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer, result = IO_FAIL; *length_read = length; - fp->file_pos += length; + fp->file_pos += (signed long long)length; return result; } @@ -82,7 +82,7 @@ static int32_t emmcdrv_block_open(io_dev_info_t *dev_info, { const io_drv_spec_t *block_spec = (io_drv_spec_t *) spec; - if (current_file.in_use) { + if (current_file.in_use != 0U) { WARN("mmc_block: Only one open spec at a time\n"); return IO_RESOURCES_EXHAUSTED; } @@ -103,9 +103,9 @@ static int32_t emmcdrv_block_open(io_dev_info_t *dev_info, return IO_FAIL; } - if (PARTITION_ID_USER == block_spec->partition || - PARTITION_ID_BOOT_1 == block_spec->partition || - PARTITION_ID_BOOT_2 == block_spec->partition) + if ((PARTITION_ID_USER == block_spec->partition) || + (PARTITION_ID_BOOT_1 == block_spec->partition) || + (PARTITION_ID_BOOT_2 == block_spec->partition)) current_file.partition = block_spec->partition; else current_file.partition = emmcdrv_bootpartition; diff --git a/drivers/renesas/rcar/io/io_memdrv.c b/drivers/renesas/rcar/io/io_memdrv.c index 3f6b4c71b..7e8c1d3a6 100644 --- a/drivers/renesas/rcar/io/io_memdrv.c +++ b/drivers/renesas/rcar/io/io_memdrv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,7 +28,7 @@ static int32_t memdrv_dev_close(io_dev_info_t *dev_info); typedef struct { uint32_t in_use; uintptr_t base; - ssize_t file_pos; + signed long long file_pos; } file_state_t; static file_state_t current_file = { 0 }; @@ -47,7 +47,7 @@ static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, * spec at a time. When we have dynamic memory we can malloc and set * entity->info. */ - if (current_file.in_use) + if (current_file.in_use != 0U) return IO_RESOURCES_EXHAUSTED; /* File cursor offset for seek and incremental reads etc. */ @@ -61,7 +61,7 @@ static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, } static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode, - ssize_t offset) + signed long long offset) { if (mode != IO_SEEK_SET) return IO_FAIL; @@ -78,16 +78,17 @@ static int32_t memdrv_block_read(io_entity_t *entity, uintptr_t buffer, fp = (file_state_t *) entity->info; - NOTICE("BL2: dst=0x%lx src=0x%lx len=%ld(0x%lx)\n", - buffer, fp->base + fp->file_pos, length, length); + NOTICE("BL2: dst=0x%lx src=0x%llx len=%ld(0x%lx)\n", + buffer, (unsigned long long)fp->base + + (unsigned long long)fp->file_pos, length, length); - if (FLASH_MEMORY_SIZE < fp->file_pos + length) { + if (FLASH_MEMORY_SIZE < (fp->file_pos + (signed long long)length)) { ERROR("BL2: check load image (source address)\n"); return IO_FAIL; } - rcar_dma_exec(buffer, fp->base + fp->file_pos, length); - fp->file_pos += length; + rcar_dma_exec(buffer, fp->base + (uintptr_t)fp->file_pos, length); + fp->file_pos += (signed long long)length; *cnt = length; return IO_SUCCESS; diff --git a/drivers/st/io/io_mmc.c b/drivers/st/io/io_mmc.c index a239b5f3a..44b7d1907 100644 --- a/drivers/st/io/io_mmc.c +++ b/drivers/st/io/io_mmc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,14 +20,15 @@ static int mmc_dev_open(const uintptr_t init_params, io_dev_info_t **dev_info); static int mmc_block_open(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity); static int mmc_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params); -static int mmc_block_seek(io_entity_t *entity, int mode, ssize_t offset); +static int mmc_block_seek(io_entity_t *entity, int mode, + signed long long offset); static int mmc_block_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read); static int mmc_block_close(io_entity_t *entity); static int mmc_dev_close(io_dev_info_t *dev_info); static io_type_t device_type_mmc(void); -static ssize_t seek_offset; +static signed long long seek_offset; static const io_dev_connector_t mmc_dev_connector = { .dev_open = mmc_dev_open @@ -85,7 +86,8 @@ static int mmc_block_open(io_dev_info_t *dev_info, const uintptr_t spec, } /* Seek to a particular file offset on the mmc device */ -static int mmc_block_seek(io_entity_t *entity, int mode, ssize_t offset) +static int mmc_block_seek(io_entity_t *entity, int mode, + signed long long offset) { seek_offset = offset; return 0; diff --git a/include/drivers/io/io_driver.h b/include/drivers/io/io_driver.h index 2b704f491..d8bb435aa 100644 --- a/include/drivers/io/io_driver.h +++ b/include/drivers/io/io_driver.h @@ -39,7 +39,7 @@ typedef struct io_dev_funcs { io_type_t (*type)(void); int (*open)(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity); - int (*seek)(io_entity_t *entity, int mode, ssize_t offset); + int (*seek)(io_entity_t *entity, int mode, signed long long offset); int (*size)(io_entity_t *entity, size_t *length); int (*read)(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read); diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h index 084c67c47..d40a828e1 100644 --- a/include/drivers/io/io_storage.h +++ b/include/drivers/io/io_storage.h @@ -86,7 +86,7 @@ int io_dev_close(uintptr_t dev_handle); /* Synchronous operations */ int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle); -int io_seek(uintptr_t handle, io_seek_mode_t mode, ssize_t offset); +int io_seek(uintptr_t handle, io_seek_mode_t mode, signed long long offset); int io_size(uintptr_t handle, size_t *length); -- cgit v1.2.3 From f35e5ab39cc9e107779a5bc673e6159cd119aee0 Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Fri, 10 Jan 2020 16:11:18 -0600 Subject: docs: GCC toolchain upgrade to version 9.2-2019.12 This toolchain provides multiple cross compilers and are publicly available on developer.arm.com We build TF-A in CI using: AArch32 bare-metal target (arm-none-eabi) AArch64 ELF bare-metal target (aarch64-none-elf) Change-Id: I910200174d5bad985504d1af4a1ae5819b524003 Signed-off-by: Madhukar Pappireddy --- docs/getting_started/initial-build.rst | 8 ++++---- docs/getting_started/prerequisites.rst | 2 +- docs/plat/arm/fvp/index.rst | 2 +- docs/plat/arm/juno/index.rst | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/getting_started/initial-build.rst b/docs/getting_started/initial-build.rst index 41cd4d1c9..893aba245 100644 --- a/docs/getting_started/initial-build.rst +++ b/docs/getting_started/initial-build.rst @@ -8,13 +8,13 @@ Performing an Initial Build .. code:: shell - export CROSS_COMPILE=/bin/aarch64-linux-gnu- + export CROSS_COMPILE=/bin/aarch64-none-elf- For AArch32: .. code:: shell - export CROSS_COMPILE=/bin/arm-eabi- + export CROSS_COMPILE=/bin/arm-none-eabi- It is possible to build TF-A using Clang or Arm Compiler 6. To do so ``CC`` needs to point to the clang or armclang binary, which will @@ -32,7 +32,7 @@ Performing an Initial Build .. code:: shell - export CROSS_COMPILE=/bin/aarch64-linux-gnu- + export CROSS_COMPILE=/bin/aarch64-none-elf- make CC=/bin/armclang PLAT= all Clang will be selected when the base name of the path assigned to ``CC`` @@ -43,7 +43,7 @@ Performing an Initial Build .. code:: shell - export CROSS_COMPILE=/bin/aarch64-linux-gnu- + export CROSS_COMPILE=/bin/aarch64-none-elf- make CC=/bin/clang PLAT= all - Change to the root directory of the TF-A source tree and build. diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst index 27ad0ed5f..3e0c8fff2 100644 --- a/docs/getting_started/prerequisites.rst +++ b/docs/getting_started/prerequisites.rst @@ -26,7 +26,7 @@ Toolchain |TF-A| can be built with any of the following *cross-compiler* toolchains that target the Armv7-A or Armv8-A architectures: -- GCC >= 8.3-2019.03 (from the `Arm Developer website`_) +- GCC >= 9.2-2019.12 (from the `Arm Developer website`_) - Clang >= 4.0 - Arm Compiler >= 6.0 diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index b6396b97c..37010e1a5 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -223,7 +223,7 @@ address ``0x82000000``, the firmware can be built like this: .. code:: shell - CROSS_COMPILE=aarch64-linux-gnu- \ + CROSS_COMPILE=aarch64-none-elf- \ make PLAT=fvp DEBUG=1 \ RESET_TO_BL31=1 \ ARM_LINUX_KERNEL_AS_BL33=1 \ diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst index 6429ede7a..cf328fac9 100644 --- a/docs/plat/arm/juno/index.rst +++ b/docs/plat/arm/juno/index.rst @@ -136,7 +136,7 @@ a single FIP binary. It assumes that a Linaro release has been installed. .. code:: shell - export CROSS_COMPILE=/bin/aarch64-linux-gnu- + export CROSS_COMPILE=/bin/aarch64-none-elf- - The following parameters should be used to build BL1 and BL2 in AArch64 and point to the BL32 file. -- cgit v1.2.3 From 67db32319582e6e3d31d3540731c7203578f4df3 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 9 Jan 2020 08:52:10 -0800 Subject: Tegra: include: fix violations of MISRA Rule 21.1 This patch fixes the violations of Rule 21.1 from all the Tegra common header files. Rule 21.1 "#define and #undef shall not be used on a reserved identifier or reserved macro name" Signed-off-by: Varun Wadekar Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185 --- plat/nvidia/tegra/include/drivers/bpmp_ipc.h | 7 ++++--- plat/nvidia/tegra/include/drivers/gpcdma.h | 7 ++++--- plat/nvidia/tegra/include/drivers/tegra_gic.h | 7 ++++--- plat/nvidia/tegra/include/lib/profiler.h | 7 ++++--- plat/nvidia/tegra/include/t194/tegra194_private.h | 8 ++++---- plat/nvidia/tegra/include/t194/tegra_def.h | 8 ++++---- plat/nvidia/tegra/include/t194/tegra_mc_def.h | 8 ++++---- 7 files changed, 28 insertions(+), 24 deletions(-) diff --git a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h index 0d1e40596..a0d02c949 100644 --- a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h +++ b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h @@ -1,11 +1,12 @@ /* * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __BPMP_IPC_H__ -#define __BPMP_IPC_H__ +#ifndef BPMP_IPC_H +#define BPMP_IPC_H #include #include @@ -44,4 +45,4 @@ int tegra_bpmp_ipc_enable_clock(uint32_t clk_id); */ int tegra_bpmp_ipc_disable_clock(uint32_t clk_id); -#endif /* __BPMP_IPC_H__ */ +#endif /* BPMP_IPC_H */ diff --git a/plat/nvidia/tegra/include/drivers/gpcdma.h b/plat/nvidia/tegra/include/drivers/gpcdma.h index fb5486a8e..a59df37e3 100644 --- a/plat/nvidia/tegra/include/drivers/gpcdma.h +++ b/plat/nvidia/tegra/include/drivers/gpcdma.h @@ -1,11 +1,12 @@ /* * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __GPCDMA_H__ -#define __GPCDMA_H__ +#ifndef GPCDMA_H +#define GPCDMA_H #include @@ -13,4 +14,4 @@ void tegra_gpcdma_memcpy(uint64_t dst_addr, uint64_t src_addr, uint32_t num_bytes); void tegra_gpcdma_zeromem(uint64_t dst_addr, uint32_t num_bytes); -#endif /* __GPCDMA_H__ */ +#endif /* GPCDMA_H */ diff --git a/plat/nvidia/tegra/include/drivers/tegra_gic.h b/plat/nvidia/tegra/include/drivers/tegra_gic.h index 6106b40a7..6661dff76 100644 --- a/plat/nvidia/tegra/include/drivers/tegra_gic.h +++ b/plat/nvidia/tegra/include/drivers/tegra_gic.h @@ -1,11 +1,12 @@ /* * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __TEGRA_GIC_H__ -#define __TEGRA_GIC_H__ +#ifndef TEGRA_GIC_H +#define TEGRA_GIC_H #include @@ -26,4 +27,4 @@ void tegra_gic_pcpu_init(void); void tegra_gic_setup(const interrupt_prop_t *interrupt_props, unsigned int interrupt_props_num); -#endif /* __TEGRA_GIC_H__ */ +#endif /* TEGRA_GIC_H */ diff --git a/plat/nvidia/tegra/include/lib/profiler.h b/plat/nvidia/tegra/include/lib/profiler.h index 60f8d804a..684c872f0 100644 --- a/plat/nvidia/tegra/include/lib/profiler.h +++ b/plat/nvidia/tegra/include/lib/profiler.h @@ -1,11 +1,12 @@ /* * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PROFILER_H__ -#define __PROFILER_H__ +#ifndef PROFILER_H +#define PROFILER_H /******************************************************************************* * Number of bytes of memory used by the profiler on Tegra @@ -16,4 +17,4 @@ void boot_profiler_init(uint64_t shmem_base, uint32_t tmr_base); void boot_profiler_add_record(const char *str); void boot_profiler_deinit(void); -#endif /* __PROFILER_H__ */ +#endif /* PROFILER_H */ diff --git a/plat/nvidia/tegra/include/t194/tegra194_private.h b/plat/nvidia/tegra/include/t194/tegra194_private.h index e519cdccc..8f1deb2a3 100644 --- a/plat/nvidia/tegra/include/t194/tegra194_private.h +++ b/plat/nvidia/tegra/include/t194/tegra194_private.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __TEGRA194_PRIVATE_H__ -#define __TEGRA194_PRIVATE_H__ +#ifndef TEGRA194_PRIVATE_H +#define TEGRA194_PRIVATE_H void tegra194_cpu_reset_handler(void); uint64_t tegra194_get_cpu_reset_handler_base(void); @@ -13,4 +13,4 @@ uint64_t tegra194_get_cpu_reset_handler_size(void); uint64_t tegra194_get_smmu_ctx_offset(void); void tegra194_set_system_suspend_entry(void); -#endif /* __TEGRA194_PRIVATE_H__ */ +#endif /* TEGRA194_PRIVATE_H */ diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 67f5abbd2..e20b2c634 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __TEGRA_DEF_H__ -#define __TEGRA_DEF_H__ +#ifndef TEGRA_DEF_H +#define TEGRA_DEF_H #include @@ -237,4 +237,4 @@ #define TEGRA_SID_XUSB_VF2 U(0x5f) #define TEGRA_SID_XUSB_VF3 U(0x60) -#endif /* __TEGRA_DEF_H__ */ +#endif /* TEGRA_DEF_H */ diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h index e0444c160..1433a2ea6 100644 --- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2019, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __TEGRA_MC_DEF_H__ -#define __TEGRA_MC_DEF_H__ +#ifndef TEGRA_MC_DEF_H +#define TEGRA_MC_DEF_H /******************************************************************************* * Memory Controller Order_id registers @@ -647,4 +647,4 @@ #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) -#endif /* __TEGRA_MC_DEF_H__ */ +#endif /* TEGRA_MC_DEF_H */ -- cgit v1.2.3 From 22c72f2a29a22d41785b613f1778737c334330e8 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 9 Jan 2020 08:58:34 -0800 Subject: Tegra194: drivers: fix violations of MISRA Rule 21.1 This patch fixes the violations of Rule 21.1 from all the header files. Rule 21.1 "#define and #undef shall not be used on a reserved identifier or reserved macro name" Signed-off-by: Varun Wadekar Change-Id: I12e17a5d7158defd33b03416daab3049749905fc --- plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h | 8 ++++---- plat/nvidia/tegra/soc/t194/drivers/include/se.h | 8 ++++---- plat/nvidia/tegra/soc/t194/drivers/se/se_private.h | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 7dcfd84be..226ab5bc5 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __MCE_PRIVATE_H__ -#define __MCE_PRIVATE_H__ +#ifndef MCE_PRIVATE_H +#define MCE_PRIVATE_H #include @@ -71,4 +71,4 @@ void nvg_enable_strict_checking_mode(void); /* MCE helper functions */ void mce_enable_strict_checking(void); -#endif /* __MCE_PRIVATE_H__ */ +#endif /* MCE_PRIVATE_H */ diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/se.h b/plat/nvidia/tegra/soc/t194/drivers/include/se.h index 6e656f677..e7cf88d05 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/se.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/se.h @@ -1,13 +1,13 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __SE_H__ -#define __SE_H__ +#ifndef SE_H +#define SE_H int32_t tegra_se_suspend(void); void tegra_se_resume(void); -#endif /* __SE_H__ */ +#endif /* SE_H */ diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h index f5c00456a..a2c5d1c38 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __SE_PRIVATE_H__ -#define __SE_PRIVATE_H__ +#ifndef SE_PRIVATE_H +#define SE_PRIVATE_H #include @@ -82,4 +82,4 @@ static inline void tegra_se_write_32(uint32_t offset, uint32_t val) mmio_write_32(TEGRA_SE0_BASE + offset, val); } -#endif /* __SE_PRIVATE_H__ */ +#endif /* SE_PRIVATE_H */ -- cgit v1.2.3 From f6c4b19ac84054f191d69662404f4af321f08b2e Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Mon, 13 Jan 2020 16:26:22 +0800 Subject: intel: Remove un-needed checks for qspi driver r/w This patch removes un-needed r/w parameter checks for qspi driver. The driver can actually access any offset and size. Signed-off-by: Hadi Asyrafi Change-Id: If60b2c016aa91e2c24ddc57c6ad410c8dc5dcf53 --- plat/intel/soc/common/drivers/qspi/cadence_qspi.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c index d7cd71bec..cecf56088 100644 --- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c +++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c @@ -688,10 +688,7 @@ int cad_qspi_read(void *buffer, uint32_t offset, uint32_t size) if ((offset >= qspi_device_size) || (offset + size - 1 >= qspi_device_size) || - (size == 0) || - ((long) ((int *)buffer) & 0x3) || - (offset & 0x3) || - (size & 0x3)) { + (size == 0)) { ERROR("Invalid read parameter\n"); return -1; } @@ -766,11 +763,9 @@ int cad_qspi_write(void *buffer, uint32_t offset, uint32_t size) if ((offset >= qspi_device_size) || (offset + size - 1 >= qspi_device_size) || - (size == 0) || - ((long)buffer & 0x3) || - (offset & 0x3) || - (size & 0x3)) + (size == 0)) { return -2; + } if (CAD_QSPI_INDWR_RDSTAT(mmio_read_32(CAD_QSPI_OFFSET + CAD_QSPI_INDWR))) { -- cgit v1.2.3 From 2d51b55ee5d2a30b4e9140d8f9b6ccc541301db5 Mon Sep 17 00:00:00 2001 From: Balint Dobszay Date: Fri, 10 Jan 2020 17:16:27 +0100 Subject: Replace dts includes with C preprocessor syntax Using the /include/ syntax, the include was evaluated by dtc, only after running the preprocessor, therefore the .dtsi files were not preprocessed. This patch adds the #include syntax instead. Evaluating this and preprocessing the files now happens in a single step, done by the C preprocessor. Change-Id: I6d0104b6274316fc736e84973502a4d6c2c9d6e0 Signed-off-by: Balint Dobszay --- Makefile | 4 ++-- fdts/fvp-base-gicv2-psci-aarch32.dts | 4 ++-- fdts/fvp-base-gicv2-psci.dts | 4 ++-- fdts/fvp-base-gicv3-psci-1t.dts | 4 ++-- fdts/fvp-base-gicv3-psci-aarch32-1t.dts | 4 ++-- fdts/fvp-base-gicv3-psci-aarch32-common.dtsi | 4 ++-- fdts/fvp-base-gicv3-psci-aarch32.dts | 4 ++-- fdts/fvp-base-gicv3-psci-common.dtsi | 4 ++-- fdts/fvp-base-gicv3-psci-dynamiq-2t.dts | 4 ++-- fdts/fvp-base-gicv3-psci-dynamiq.dts | 4 ++-- fdts/fvp-base-gicv3-psci.dts | 4 ++-- fdts/fvp-foundation-gicv2-psci.dts | 4 ++-- fdts/fvp-foundation-gicv3-psci.dts | 4 ++-- fdts/fvp-ve-Cortex-A5x1.dts | 4 ++-- fdts/fvp-ve-Cortex-A7x1.dts | 4 ++-- make_helpers/build_macros.mk | 4 ++-- 16 files changed, 32 insertions(+), 32 deletions(-) diff --git a/Makefile b/Makefile index 42fdb7326..a25845ee9 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -344,7 +344,7 @@ TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) endif DTC_FLAGS += -I dts -O dtb -DTC_CPPFLAGS += -nostdinc -Iinclude -undef -x assembler-with-cpp +DTC_CPPFLAGS += -P -nostdinc -Iinclude -Ifdts -undef -x assembler-with-cpp ################################################################################ # Common sources and include directories diff --git a/fdts/fvp-base-gicv2-psci-aarch32.dts b/fdts/fvp-base-gicv2-psci-aarch32.dts index 87ac68d67..e71a39519 100644 --- a/fdts/fvp-base-gicv2-psci-aarch32.dts +++ b/fdts/fvp-base-gicv2-psci-aarch32.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -279,7 +279,7 @@ <0 0 41 &gic 0 41 4>, <0 0 42 &gic 0 42 4>; - /include/ "rtsm_ve-motherboard-aarch32.dtsi" + #include "rtsm_ve-motherboard-aarch32.dtsi" }; panels { diff --git a/fdts/fvp-base-gicv2-psci.dts b/fdts/fvp-base-gicv2-psci.dts index 941040d8e..c9c9d9594 100644 --- a/fdts/fvp-base-gicv2-psci.dts +++ b/fdts/fvp-base-gicv2-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -233,7 +233,7 @@ <4 0 0 0x0c000000 0x04000000>, <5 0 0 0x10000000 0x04000000>; - /include/ "rtsm_ve-motherboard.dtsi" + #include "rtsm_ve-motherboard.dtsi" }; panels { diff --git a/fdts/fvp-base-gicv3-psci-1t.dts b/fdts/fvp-base-gicv3-psci-1t.dts index 36fbd4444..3c82f7b13 100644 --- a/fdts/fvp-base-gicv3-psci-1t.dts +++ b/fdts/fvp-base-gicv3-psci-1t.dts @@ -1,12 +1,12 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /dts-v1/; -/include/ "fvp-base-gicv3-psci-common.dtsi" +#include "fvp-base-gicv3-psci-common.dtsi" &CPU0 { reg = <0x0 0x0>; diff --git a/fdts/fvp-base-gicv3-psci-aarch32-1t.dts b/fdts/fvp-base-gicv3-psci-aarch32-1t.dts index f7c936210..d1d33485c 100644 --- a/fdts/fvp-base-gicv3-psci-aarch32-1t.dts +++ b/fdts/fvp-base-gicv3-psci-aarch32-1t.dts @@ -1,12 +1,12 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /dts-v1/; -/include/ "fvp-base-gicv3-psci-aarch32-common.dtsi" +#include "fvp-base-gicv3-psci-aarch32-common.dtsi" &CPU0 { reg = <0x0>; diff --git a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi index 6179c66e7..f9809db8b 100644 --- a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi +++ b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -286,7 +286,7 @@ <0 0 41 &gic 0 0 0 41 4>, <0 0 42 &gic 0 0 0 42 4>; - /include/ "rtsm_ve-motherboard-aarch32.dtsi" + #include "rtsm_ve-motherboard-aarch32.dtsi" }; panels { diff --git a/fdts/fvp-base-gicv3-psci-aarch32.dts b/fdts/fvp-base-gicv3-psci-aarch32.dts index 2833cdfac..513014b32 100644 --- a/fdts/fvp-base-gicv3-psci-aarch32.dts +++ b/fdts/fvp-base-gicv3-psci-aarch32.dts @@ -1,9 +1,9 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /dts-v1/; -/include/ "fvp-base-gicv3-psci-aarch32-common.dtsi" +#include "fvp-base-gicv3-psci-aarch32-common.dtsi" diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-gicv3-psci-common.dtsi index 631c4e345..94ed67d55 100644 --- a/fdts/fvp-base-gicv3-psci-common.dtsi +++ b/fdts/fvp-base-gicv3-psci-common.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -240,7 +240,7 @@ <4 0 0 0x0c000000 0x04000000>, <5 0 0 0x10000000 0x04000000>; - /include/ "rtsm_ve-motherboard.dtsi" + #include "rtsm_ve-motherboard.dtsi" }; panels { diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts index f35eaf482..48269a065 100644 --- a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts +++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts @@ -1,12 +1,12 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /dts-v1/; -/include/ "fvp-base-gicv3-psci-common.dtsi" +#include "fvp-base-gicv3-psci-common.dtsi" &CPU0 { reg = <0x0 0x0>; diff --git a/fdts/fvp-base-gicv3-psci-dynamiq.dts b/fdts/fvp-base-gicv3-psci-dynamiq.dts index 614c5d5c0..51c7acacf 100644 --- a/fdts/fvp-base-gicv3-psci-dynamiq.dts +++ b/fdts/fvp-base-gicv3-psci-dynamiq.dts @@ -1,12 +1,12 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /dts-v1/; -/include/ "fvp-base-gicv3-psci-common.dtsi" +#include "fvp-base-gicv3-psci-common.dtsi" &CPU0 { reg = <0x0 0x0>; diff --git a/fdts/fvp-base-gicv3-psci.dts b/fdts/fvp-base-gicv3-psci.dts index 3ea429ce9..65fa4b0d9 100644 --- a/fdts/fvp-base-gicv3-psci.dts +++ b/fdts/fvp-base-gicv3-psci.dts @@ -1,9 +1,9 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /dts-v1/; -/include/ "fvp-base-gicv3-psci-common.dtsi" +#include "fvp-base-gicv3-psci-common.dtsi" diff --git a/fdts/fvp-foundation-gicv2-psci.dts b/fdts/fvp-foundation-gicv2-psci.dts index 03b61dd73..b6da90549 100644 --- a/fdts/fvp-foundation-gicv2-psci.dts +++ b/fdts/fvp-foundation-gicv2-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -182,6 +182,6 @@ <4 0 0 0x0c000000 0x04000000>, <5 0 0 0x10000000 0x04000000>; - /include/ "fvp-foundation-motherboard.dtsi" + #include "fvp-foundation-motherboard.dtsi" }; }; diff --git a/fdts/fvp-foundation-gicv3-psci.dts b/fdts/fvp-foundation-gicv3-psci.dts index 1488ed7f7..81071e255 100644 --- a/fdts/fvp-foundation-gicv3-psci.dts +++ b/fdts/fvp-foundation-gicv3-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -191,6 +191,6 @@ <4 0 0 0x0c000000 0x04000000>, <5 0 0 0x10000000 0x04000000>; - /include/ "fvp-foundation-motherboard.dtsi" + #include "fvp-foundation-motherboard.dtsi" }; }; diff --git a/fdts/fvp-ve-Cortex-A5x1.dts b/fdts/fvp-ve-Cortex-A5x1.dts index 0f766016d..9d2d1d552 100644 --- a/fdts/fvp-ve-Cortex-A5x1.dts +++ b/fdts/fvp-ve-Cortex-A5x1.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -139,6 +139,6 @@ <0 0 5 &gic 0 5 4>, <0 0 42 &gic 0 42 4>; - /include/ "rtsm_ve-motherboard-aarch32.dtsi" + #include "rtsm_ve-motherboard-aarch32.dtsi" }; }; diff --git a/fdts/fvp-ve-Cortex-A7x1.dts b/fdts/fvp-ve-Cortex-A7x1.dts index fca3d90ab..28de91d3c 100644 --- a/fdts/fvp-ve-Cortex-A7x1.dts +++ b/fdts/fvp-ve-Cortex-A7x1.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -71,6 +71,6 @@ <0 0 5 &gic 0 5 4>, <0 0 42 &gic 0 42 4>; - /include/ "rtsm_ve-motherboard-aarch32.dtsi" + #include "rtsm_ve-motherboard-aarch32.dtsi" }; }; diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index 47f3ebd86..6b72cfd0d 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -513,7 +513,7 @@ $(DOBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | fdt_dirs $(eval DTBS := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2)))) $$(Q)$$(PP) $$(DTC_CPPFLAGS) -MT $(DTBS) -MMD -MF $(DTSDEP) -o $(DPRE) $$< $${ECHO} " DTC $$<" - $$(Q)$$(DTC) $$(DTC_FLAGS) -i fdts -d $(DTBDEP) -o $$@ $(DPRE) + $$(Q)$$(DTC) $$(DTC_FLAGS) -d $(DTBDEP) -o $$@ $(DPRE) -include $(DTBDEP) -include $(DTSDEP) -- cgit v1.2.3 From ba1eaabfffa29585aeacb85d0fbc9e834af72976 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Tue, 7 Jan 2020 15:12:08 +0100 Subject: cert_create: Remove some unused header files inclusions The chain of trust definitions are only needed in the part of the code dealing with the TBBR CoT (tbbr/* files). Change-Id: I6f9a86bba4a2d16313b6842a3ec85b7c951074bc Signed-off-by: Sandrine Bailleux --- tools/cert_create/src/cert.c | 8 +------- tools/cert_create/src/key.c | 8 +------- tools/cert_create/src/main.c | 11 +---------- 3 files changed, 3 insertions(+), 24 deletions(-) diff --git a/tools/cert_create/src/cert.c b/tools/cert_create/src/cert.c index c68a265b4..153f5557d 100644 --- a/tools/cert_create/src/cert.c +++ b/tools/cert_create/src/cert.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,12 +15,6 @@ #include #include -#if USE_TBBR_DEFS -#include -#else -#include -#endif - #include "cert.h" #include "cmd_opt.h" #include "debug.h" diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c index 0f80cce9b..fcc9d5316 100644 --- a/tools/cert_create/src/key.c +++ b/tools/cert_create/src/key.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,12 +13,6 @@ #include #include -#if USE_TBBR_DEFS -#include -#else -#include -#endif - #include "cert.h" #include "cmd_opt.h" #include "debug.h" diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c index 0cbd2196b..863db7b6e 100644 --- a/tools/cert_create/src/main.c +++ b/tools/cert_create/src/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,21 +19,12 @@ #include #include -#if USE_TBBR_DEFS -#include -#else -#include -#endif - #include "cert.h" #include "cmd_opt.h" #include "debug.h" #include "ext.h" #include "key.h" #include "sha.h" -#include "tbbr/tbb_cert.h" -#include "tbbr/tbb_ext.h" -#include "tbbr/tbb_key.h" /* * Helper macros to simplify the code. This macro assigns the return value of -- cgit v1.2.3 From 433090515dd4a97ed234ed20e6902da68b917346 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Mon, 9 Dec 2019 12:48:42 +0100 Subject: rpi4: Fix documentation of armstub config entry It's in fact mandatory. Seen with RPi firmware 1.20190925. Signed-off-by: Jan Kiszka Change-Id: I80739b74f25817294adc52cfd26a3ec59c06f892 --- docs/plat/rpi4.rst | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/docs/plat/rpi4.rst b/docs/plat/rpi4.rst index 0f529c103..beb0227c2 100644 --- a/docs/plat/rpi4.rst +++ b/docs/plat/rpi4.rst @@ -24,11 +24,10 @@ one universal binary (bl31.bin), which can be built with: CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi4 DEBUG=1 -Copy the generated build/rpi4/debug/bl31.bin to the SD card, either -renaming it to ``armstub8.bin`` or adding an entry starting with ``armstub=``, -then followed by the respective file name to ``config.txt``. -You should have AArch64 code in the file loaded as the "kernel", as BL31 -will drop into AArch64/EL2 to the respective load address. +Copy the generated build/rpi4/debug/bl31.bin to the SD card, adding an entry +starting with ``armstub=``, then followed by the respective file name to +``config.txt``. You should have AArch64 code in the file loaded as the +"kernel", as BL31 will drop into AArch64/EL2 to the respective load address. arm64 Linux kernels are known to work this way. Other options that should be set in ``config.txt`` to properly boot 64-bit -- cgit v1.2.3 From b0eae6f942ba8b36a27440290ba7bb13f9886038 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Mon, 4 Mar 2019 11:09:39 +0530 Subject: plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function Add GET_CALLBACK_DATA function again as now Linux driver supports both mailbox as well as ISR method. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: Ieb99d61976e1cb718fcd1021d9cf4958e7556c81 --- plat/xilinx/zynqmp/pm_service/pm_api_sys.c | 18 +++++++++++++++++- plat/xilinx/zynqmp/pm_service/pm_api_sys.h | 3 ++- plat/xilinx/zynqmp/pm_service/pm_svc_main.c | 13 ++++++++++++- 3 files changed, 31 insertions(+), 3 deletions(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c index e0b9816e4..cd6f44f83 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -629,6 +629,22 @@ enum pm_ret_status pm_aes_engine(uint32_t address_high, return pm_ipi_send_sync(primary_proc, payload, value, 1); } +/** + * pm_get_callbackdata() - Read from IPI response buffer + * @data - array of PAYLOAD_ARG_CNT elements + * + * Read value from ipi buffer response buffer. + */ +void pm_get_callbackdata(uint32_t *data, size_t count) +{ + /* Return if interrupt is not from PMU */ + if (!pm_ipi_irq_status(primary_proc)) + return; + + pm_ipi_buff_read_callb(data, count); + pm_ipi_irq_clear(primary_proc); +} + /** * pm_pinctrl_request() - Request Pin from firmware * @pin Pin number to request diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h index 282ca3dc6..56c004339 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -116,6 +116,7 @@ enum pm_ret_status pm_secure_rsaaes(uint32_t address_high, uint32_t size, uint32_t flags); unsigned int pm_get_shutdown_scope(void); +void pm_get_callbackdata(uint32_t *data, size_t count); enum pm_ret_status pm_pinctrl_request(unsigned int pin); enum pm_ret_status pm_pinctrl_release(unsigned int pin); enum pm_ret_status pm_pinctrl_get_function(unsigned int pin, diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c index faa282745..5a320f1ba 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c +++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,6 +25,7 @@ #include "pm_client.h" #include "pm_ipi.h" +#define PM_GET_CALLBACK_DATA 0xa01 #define PM_SET_SUSPEND_MODE 0xa02 #define PM_GET_TRUSTZONE_VERSION 0xa03 @@ -412,6 +413,16 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, pm_arg[3]); SMC_RET1(handle, (uint64_t)ret); + case PM_GET_CALLBACK_DATA: + { + uint32_t result[4] = {0}; + + pm_get_callbackdata(result, (sizeof(result)/sizeof(uint32_t))); + SMC_RET2(handle, + (uint64_t)result[0] | ((uint64_t)result[1] << 32), + (uint64_t)result[2] | ((uint64_t)result[3] << 32)); + } + case PM_PINCTRL_REQUEST: ret = pm_pinctrl_request(pm_arg[0]); SMC_RET1(handle, (uint64_t)ret); -- cgit v1.2.3 From 75b90fe86501bcb028c99f9b9d0ea57e14f461eb Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Fri, 15 Mar 2019 14:19:25 +0530 Subject: zynqmp: pm: clock: Add support for custom type flags Add support to add extra custom type flags and provide to caller in topology query. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: Id9cc065dbadfed2291dd4f62674d7838da4cdf40 --- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index 9ea8cd43e..d57def823 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -30,6 +30,10 @@ #define CLK_TYPE_SHIFT U(2) #define CLK_CLKFLAGS_SHIFT U(8) #define CLK_TYPEFLAGS_SHIFT U(24) +#define CLK_TYPEFLAGS2_SHIFT U(4) +#define CLK_TYPEFLAGS_BITS_MASK U(0xFF) +#define CLK_TYPEFLAGS2_BITS_MASK U(0x0F00) +#define CLK_TYPEFLAGS_BITS U(8) #define CLK_EXTERNAL_PARENT (PARENT_CLK_EXTERNAL << CLK_PARENTS_ID_LEN) @@ -2461,6 +2465,7 @@ enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id, struct pm_clock_node *clock_nodes; uint8_t num_nodes; unsigned int i; + uint16_t typeflags; if (!pm_clock_valid(clock_id)) return PM_RET_ERROR_ARGS; @@ -2480,11 +2485,14 @@ enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id, for (i = 0; i < 3U; i++) { if ((index + i) == num_nodes) break; - topology[i] = clock_nodes[index + i].type; + topology[i] = clock_nodes[index + i].type; topology[i] |= clock_nodes[index + i].clkflags << CLK_CLKFLAGS_SHIFT; - topology[i] |= clock_nodes[index + i].typeflags << + typeflags = clock_nodes[index + i].typeflags; + topology[i] |= (typeflags & CLK_TYPEFLAGS_BITS_MASK) << CLK_TYPEFLAGS_SHIFT; + topology[i] |= (typeflags & CLK_TYPEFLAGS2_BITS_MASK) >> + (CLK_TYPEFLAGS_BITS - CLK_TYPEFLAGS2_SHIFT); } return PM_RET_SUCCESS; -- cgit v1.2.3 From 74cf2158ca6195cb8f9fa4a784e60b95935291a1 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Fri, 15 Mar 2019 14:19:26 +0530 Subject: zynqmp: pm: clock: Move custom flags to typeflags Linux expects custom flags in type flags. So move custom flags to type flags instead of providing them to clock core flags. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78 --- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 15 ++++++++------- plat/xilinx/zynqmp/pm_service/pm_api_clock.h | 2 +- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index d57def823..0ba8e34bc 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -368,9 +368,8 @@ static struct pm_clock_node dp_audio_video_ref_nodes[] = { .offset = PERIPH_MUX_SHIFT, .width = PERIPH_MUX_WIDTH, .clkflags = CLK_SET_RATE_NO_REPARENT | - CLK_SET_RATE_PARENT | - CLK_FRAC | CLK_IS_BASIC, - .typeflags = NA_TYPE_FLAGS, + CLK_SET_RATE_PARENT | CLK_IS_BASIC, + .typeflags = CLK_FRAC, .mult = NA_MULT, .div = NA_DIV, }, @@ -379,8 +378,9 @@ static struct pm_clock_node dp_audio_video_ref_nodes[] = { .offset = PERIPH_DIV1_SHIFT, .width = PERIPH_DIV1_WIDTH, .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | - CLK_FRAC | CLK_IS_BASIC, - .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + CLK_IS_BASIC, + .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | + CLK_FRAC, .mult = NA_MULT, .div = NA_DIV, }, @@ -389,8 +389,9 @@ static struct pm_clock_node dp_audio_video_ref_nodes[] = { .offset = PERIPH_DIV2_SHIFT, .width = PERIPH_DIV2_WIDTH, .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | - CLK_FRAC | CLK_IS_BASIC, - .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + CLK_IS_BASIC, + .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | + CLK_FRAC, .mult = NA_MULT, .div = NA_DIV, }, diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h index 5bed5a617..48f5a5ec4 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h @@ -43,7 +43,6 @@ #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ /* parents need enable during gate/ungate, set rate and re-parent */ #define CLK_OPS_PARENT_ENABLE BIT(12) -#define CLK_FRAC BIT(13) #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) @@ -52,6 +51,7 @@ #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +#define CLK_FRAC BIT(8) #define END_OF_CLK "END_OF_CLK" -- cgit v1.2.3 From 138cde662f99f8659be554810d8b8e2d9b1ba7ac Mon Sep 17 00:00:00 2001 From: Ravi Patel Date: Fri, 15 Mar 2019 18:02:48 +0530 Subject: zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node Existing implementation does not allow to change the value of the DIV1 because DIV2 does not have SET_RATE_PARENT flag. This causes DIV1 value to be fixed and only value of DIV2 will be adjusted according to required clock rate. Signed-off-by: Ravi Patel Signed-off-by: Jolly Shah Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b --- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index 0ba8e34bc..6e53bd89d 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -582,7 +582,8 @@ static struct pm_clock_node gem_ref_ungated_nodes[] = { .type = TYPE_DIV2, .offset = 16, .width = 6, - .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC, + .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC | + CLK_SET_RATE_PARENT, .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, .mult = NA_MULT, .div = NA_DIV, -- cgit v1.2.3 From 5e07b7001ba9675458ade856846440d508a1e4b3 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Wed, 20 Mar 2019 01:13:21 +0530 Subject: zynqmp: pm_service: Add support to query max divisor Add new QID to get maximum supported divisor by clock. Signed-off-by: Rajan Vaja Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: I35fc92457e522f3f0614d983c21e55c2b0b8e80a --- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 36 ++++++++++++++++++++++++++++ plat/xilinx/zynqmp/pm_service/pm_api_clock.h | 3 +++ plat/xilinx/zynqmp/pm_service/pm_api_sys.c | 22 +++++++++++++++++ plat/xilinx/zynqmp/pm_service/pm_api_sys.h | 1 + 4 files changed, 62 insertions(+) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index 6e53bd89d..852f92763 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -2620,6 +2620,42 @@ enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id, return PM_RET_SUCCESS; } +/** + * pm_api_clock_get_max_divisor - PM call to get max divisor + * @clock_id Clock ID + * @div_type Divisor Type (TYPE_DIV1 or TYPE_DIV2) + * @max_div Maximum supported divisor + * + * This function is used by master to get maximum supported value. + * + * Return: Returns status, either success or error+reason. + */ +enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id, + uint8_t div_type, + uint32_t *max_div) +{ + uint32_t i; + struct pm_clock_node *nodes; + + if (clock_id >= CLK_MAX_OUTPUT_CLK) + return PM_RET_ERROR_ARGS; + + nodes = *clocks[clock_id].nodes; + for (i = 0; i < clocks[clock_id].num_nodes; i++) { + if (nodes[i].type == div_type) { + if (CLK_DIVIDER_POWER_OF_TWO & + nodes[i].typeflags) { + *max_div = (1 << (BIT(nodes[i].width) - 1)); + } else { + *max_div = BIT(nodes[i].width) - 1; + } + return PM_RET_SUCCESS; + } + } + + return PM_RET_ERROR_ARGS; +} + /** * struct pm_pll - PLL related data required to map IOCTL-based PLL control * implemented by linux to system-level EEMI APIs diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h index 48f5a5ec4..301ed24b6 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h @@ -307,6 +307,9 @@ enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id, uint32_t *parents); enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id, uint32_t *attr); +enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id, + uint8_t div_type, + uint32_t *max_div); enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id, enum pm_node_id *node_id); diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c index cd6f44f83..b1720d9f6 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c @@ -756,6 +756,23 @@ enum pm_ret_status pm_ioctl(enum pm_node_id nid, return pm_api_ioctl(nid, ioctl_id, arg1, arg2, value); } +/** + * pm_clock_get_max_divisor - PM call to get max divisor + * @clock_id Clock ID + * @div_type Divisor ID (TYPE_DIV1 or TYPE_DIV2) + * @max_div Maximum supported divisor + * + * This function is used by master to get maximum supported value. + * + * Return: Returns status, either success or error+reason. + */ +static enum pm_ret_status pm_clock_get_max_divisor(unsigned int clock_id, + uint8_t div_type, + uint32_t *max_div) +{ + return pm_api_clock_get_max_divisor(clock_id, div_type, max_div); +} + /** * pm_clock_get_num_clocks - PM call to request number of clocks * @nclockss: Number of clocks @@ -1338,6 +1355,11 @@ enum pm_ret_status pm_query_data(enum pm_query_id qid, ret = pm_clock_get_num_clocks(&data[1]); data[0] = (unsigned int)ret; break; + + case PM_QID_CLOCK_GET_MAX_DIVISOR: + ret = pm_clock_get_max_divisor(arg1, arg2, &data[1]); + data[0] = (unsigned int)ret; + break; default: ret = PM_RET_ERROR_ARGS; WARN("Unimplemented query service call: 0x%x\n", qid); diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h index 56c004339..ff66d3f02 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h @@ -25,6 +25,7 @@ enum pm_query_id { PM_QID_PINCTRL_GET_FUNCTION_GROUPS, PM_QID_PINCTRL_GET_PIN_GROUPS, PM_QID_CLOCK_GET_NUM_CLOCKS, + PM_QID_CLOCK_GET_MAX_DIVISOR, }; /********************************************************** -- cgit v1.2.3 From 6be71b09c92102ea7aca54cdcda4ef565aa22916 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 6 Jan 2020 03:26:43 +0100 Subject: rcar_gen3: Add missing #{address,size}-cells into generated DT Add missing #address-cells and #size-cells into generated DT, otherwise the DT is invalid. While the parsers thus far handled this correctly via various fallbacks, this is not applicable in the long run, so fix this. Signed-off-by: Marek Vasut Change-Id: Ic808a3b27b93e5258ec1a19acc3d593e53625c15 --- plat/renesas/rcar/bl2_plat_setup.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index b4762f330..193d80e70 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -415,6 +415,9 @@ static void bl2_populate_compatible_string(void *dt) uint32_t reg; int ret; + fdt_setprop_u32(dt, 0, "#address-cells", 2); + fdt_setprop_u32(dt, 0, "#size-cells", 2); + /* Populate compatible string */ rcar_get_board_type(&board_type, &board_rev); switch (board_type) { -- cgit v1.2.3 From 8c11ebfcdac0802119293f8c00912a54048ddd02 Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Mon, 13 Jan 2020 20:37:35 +0100 Subject: a8k: Implement platform specific power off Implements a way to add platform specific power off code to a Marvell Armada 8K platform. Marvell Armada 8K boards can now add a board/system_power.c file that contains a system_power_off() function. This function can now send a command to a power management MCU or other board periferals before shutting the board down. Signed-off-by: Luka Kovacic Cc: Luka Perkov Change-Id: Iaba20bc2f603195679c54ad12c0c18962dd8e3db --- I am working on a device that will be ported later, which has a custom power management MCU that handles LEDs, board power and fans and requires this separation. --- include/plat/marvell/a8k/common/armada_common.h | 1 + plat/marvell/a8k/common/a8k_common.mk | 11 +++++++++++ plat/marvell/a8k/common/plat_pm.c | 12 ++++++++++++ 3 files changed, 24 insertions(+) diff --git a/include/plat/marvell/a8k/common/armada_common.h b/include/plat/marvell/a8k/common/armada_common.h index dd2a24abc..709d009c2 100644 --- a/include/plat/marvell/a8k/common/armada_common.h +++ b/include/plat/marvell/a8k/common/armada_common.h @@ -124,5 +124,6 @@ int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base); int marvell_get_ccu_memory_map(int ap_idx, struct addr_map_win **win, uint32_t *size); +int system_power_off(void); #endif /* ARMADA_COMMON_H */ diff --git a/plat/marvell/a8k/common/a8k_common.mk b/plat/marvell/a8k/common/a8k_common.mk index ccb662bb2..bf79ebeec 100644 --- a/plat/marvell/a8k/common/a8k_common.mk +++ b/plat/marvell/a8k/common/a8k_common.mk @@ -37,6 +37,13 @@ DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage ROM_BIN_EXT ?= $(BUILD_PLAT)/ble.bin DOIMAGE_FLAGS += -b $(ROM_BIN_EXT) $(NAND_DOIMAGE_FLAGS) $(DOIMAGE_SEC_FLAGS) +# Check whether to build system_power.c for the platform +ifneq ("$(wildcard $(PLAT_FAMILY_BASE)/$(PLAT)/board/system_power.c)","") +SYSTEM_POWER_SUPPORT = 1 +else +SYSTEM_POWER_SUPPORT = 0 +endif + # This define specifies DDR type for BLE $(eval $(call add_define,CONFIG_DDR4)) @@ -82,6 +89,10 @@ MARVELL_DRV := $(MARVELL_DRV_BASE)/io_win.c \ BL31_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/marvell_plat_config.c +ifeq ($(SYSTEM_POWER_SUPPORT),1) +BL31_PORTING_SOURCES += $(PLAT_FAMILY_BASE)/$(PLAT)/board/system_power.c +endif + BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \ $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ $(PLAT_COMMON_BASE)/aarch64/plat_arch_config.c \ diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c index d07601a5f..96e95c271 100644 --- a/plat/marvell/a8k/common/plat_pm.c +++ b/plat/marvell/a8k/common/plat_pm.c @@ -792,8 +792,20 @@ __dead2 a8k_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) * A8K handlers to shutdown/reboot the system ***************************************************************************** */ + +/* Set a weak stub for platforms that don't configure system power off */ +#pragma weak system_power_off +int system_power_off(void) +{ + return 0; +} + static void __dead2 a8k_system_off(void) { + /* Call the platform specific system power off function */ + system_power_off(); + + /* board doesn't have a system off implementation */ ERROR("%s: needs to be implemented\n", __func__); panic(); } -- cgit v1.2.3 From 6c281cc3a402b6bf9b403301f0d1d645c1f6a655 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 27 Oct 2019 17:21:24 -0500 Subject: allwinner: Reenable USE_COHERENT_MEM Now that there is plenty of space (32 KiB) available for NOBITS sections, we can afford using an entire page for coherent memory. In fact, because it simplifies the code, this is a beneficial change for loaded image (.text) size, where we are still close to the size limit. Signed-off-by: Samuel Holland Change-Id: I0b899dabcb162015c63b0e4aed0869569c889ed9 --- plat/allwinner/common/allwinner-common.mk | 3 --- plat/allwinner/common/include/platform_def.h | 2 +- plat/allwinner/common/sunxi_common.c | 4 ++++ 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk index e717e20b0..98bcf3e22 100644 --- a/plat/allwinner/common/allwinner-common.mk +++ b/plat/allwinner/common/allwinner-common.mk @@ -61,8 +61,5 @@ SEPARATE_NOBITS_REGION := 1 # BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL RESET_TO_BL31 := 1 -# We are short on memory, so save 3.5KB by not having an extra coherent page. -USE_COHERENT_MEM := 0 - # This platform is single-cluster and does not require coherency setup. WARMBOOT_ENABLE_DCACHE_EARLY := 1 diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h index 4de8b0bc4..0a0007667 100644 --- a/plat/allwinner/common/include/platform_def.h +++ b/plat/allwinner/common/include/platform_def.h @@ -32,7 +32,7 @@ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) -#define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) +#define MAX_MMAP_REGIONS (4 + PLATFORM_MMAP_REGIONS) #define MAX_XLAT_TABLES 1 #define PLAT_MAX_PWR_LVL_STATES U(2) diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c index 1e21a4262..cff826819 100644 --- a/plat/allwinner/common/sunxi_common.c +++ b/plat/allwinner/common/sunxi_common.c @@ -57,6 +57,10 @@ void sunxi_configure_mmu_el3(int flags) mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_SECURE); + mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, + MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER); + mmap_add(sunxi_mmap); init_xlat_tables(); -- cgit v1.2.3 From e5ebe87b6daad2a7d0fd3fd8bc6ee026f20f095a Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 17 Dec 2019 15:25:04 +0800 Subject: intel: Change all global sip function to static All function in socfpga_sip_svc.c should only be called locally except sip_smc_handler(). Signed-off-by: Hadi Asyrafi Change-Id: Ib84ef9a2e521967baa4cfd32e6bc569dd3a5d2f5 --- plat/intel/soc/common/socfpga_sip_svc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index f58b58faf..ce88fb489 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -42,7 +42,7 @@ DEFINE_SVC_UUID2(intl_svc_uid, 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); -uint64_t socfpga_sip_handler(uint32_t smc_fid, +static uint64_t socfpga_sip_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, @@ -93,7 +93,7 @@ static int intel_fpga_sdm_write_all(void) return 0; } -uint32_t intel_mailbox_fpga_config_isdone(void) +static uint32_t intel_mailbox_fpga_config_isdone(void) { uint32_t ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); @@ -129,7 +129,7 @@ static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) return -1; } -int intel_fpga_config_completed_write(uint32_t *completed_addr, +static int intel_fpga_config_completed_write(uint32_t *completed_addr, uint32_t *count) { uint32_t status = INTEL_SIP_SMC_STATUS_OK; @@ -186,7 +186,7 @@ int intel_fpga_config_completed_write(uint32_t *completed_addr, return status; } -int intel_fpga_config_start(uint32_t config_type) +static int intel_fpga_config_start(uint32_t config_type) { uint32_t response[3]; int status = 0; @@ -239,7 +239,7 @@ static bool is_address_in_ddr_range(uint64_t addr) return false; } -uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) +static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) { int i; -- cgit v1.2.3 From 389091a8d659bc622cc1382657ae5dabd1c10e8f Mon Sep 17 00:00:00 2001 From: "Tien Hock, Loh" Date: Mon, 14 Oct 2019 14:48:24 +0800 Subject: plat: intel: Fix UEFI decompression issue UEFI decompression will fail if the payload size is too large and the load address is too low. This patch moves the payload to a higher address to fix the issue Signed-off-by: Tien Hock, Loh Change-Id: I36087fbd2237b62891c59dbe2d34336bddfaa396 --- plat/intel/soc/common/include/platform_def.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index 06f3a1b0d..8d04479df 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -29,7 +29,7 @@ #define L2_RESET_DONE_STATUS 0x1228E5E7 /* Define next boot image name and offset */ -#define PLAT_NS_IMAGE_OFFSET 0x50000 +#define PLAT_NS_IMAGE_OFFSET 0x10000000 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 /******************************************************************************* -- cgit v1.2.3 From fe550edef034ec6b9c4564a0b9c27136a7df5968 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Thu, 4 Apr 2019 14:23:32 +0530 Subject: plat: xilinx: zynqmp: Add checksum support for IPI data This patch adds support for CRC checksum for IPI data when the macro ZYNQMP_IPI_CRC_CHECK is defined. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Jolly Shah Change-Id: Ic981f162666b3c1fffeb1b9fef3ee7714ecd889d --- plat/xilinx/common/include/pm_ipi.h | 5 ++- plat/xilinx/common/pm_service/pm_ipi.c | 64 ++++++++++++++++++++++++++++- plat/xilinx/zynqmp/include/plat_pm_common.h | 13 +++++- plat/xilinx/zynqmp/platform.mk | 10 ++++- 4 files changed, 86 insertions(+), 6 deletions(-) diff --git a/plat/xilinx/common/include/pm_ipi.h b/plat/xilinx/common/include/pm_ipi.h index 16db5c548..7bcf59626 100644 --- a/plat/xilinx/common/include/pm_ipi.h +++ b/plat/xilinx/common/include/pm_ipi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,5 +26,8 @@ void pm_ipi_buff_read_callb(unsigned int *value, size_t count); void pm_ipi_irq_enable(const struct pm_proc *proc); void pm_ipi_irq_clear(const struct pm_proc *proc); uint32_t pm_ipi_irq_status(const struct pm_proc *proc); +#if ZYNQMP_IPI_CRC_CHECK +uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t buffersize); +#endif #endif /* PM_IPI_H */ diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c index 034cd5bc8..c83d25b0d 100644 --- a/plat/xilinx/common/pm_service/pm_ipi.c +++ b/plat/xilinx/common/pm_service/pm_ipi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -57,6 +57,9 @@ static enum pm_ret_status pm_ipi_send_common(const struct pm_proc *proc, uintptr_t buffer_base = proc->ipi->buffer_base + IPI_BUFFER_TARGET_REMOTE_OFFSET + IPI_BUFFER_REQ_OFFSET; +#if ZYNQMP_IPI_CRC_CHECK + payload[PAYLOAD_CRC_POS] = calculate_crc(payload, IPI_W0_TO_W6_SIZE); +#endif /* Write payload into IPI buffer */ for (size_t i = 0; i < PAYLOAD_ARG_CNT; i++) { @@ -132,6 +135,10 @@ static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc, unsigned int *value, size_t count) { size_t i; +#if ZYNQMP_IPI_CRC_CHECK + size_t j; + unsigned int response_payload[PAYLOAD_ARG_CNT]; +#endif uintptr_t buffer_base = proc->ipi->buffer_base + IPI_BUFFER_TARGET_REMOTE_OFFSET + IPI_BUFFER_RESP_OFFSET; @@ -147,6 +154,16 @@ static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc, *value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE)); value++; } +#if ZYNQMP_IPI_CRC_CHECK + for (j = 0; j < PAYLOAD_ARG_CNT; j++) + response_payload[j] = mmio_read_32(buffer_base + + (j * PAYLOAD_ARG_SIZE)); + + if (response_payload[PAYLOAD_CRC_POS] != + calculate_crc(response_payload, IPI_W0_TO_W6_SIZE)) + NOTICE("ERROR in CRC response payload value:0x%x\n", + response_payload[PAYLOAD_CRC_POS]); +#endif return mmio_read_32(buffer_base); } @@ -162,6 +179,10 @@ static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc, void pm_ipi_buff_read_callb(unsigned int *value, size_t count) { size_t i; +#if ZYNQMP_IPI_CRC_CHECK + size_t j; + unsigned int response_payload[PAYLOAD_ARG_CNT]; +#endif uintptr_t buffer_base = IPI_BUFFER_REMOTE_BASE + IPI_BUFFER_TARGET_LOCAL_OFFSET + IPI_BUFFER_REQ_OFFSET; @@ -173,6 +194,16 @@ void pm_ipi_buff_read_callb(unsigned int *value, size_t count) *value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE)); value++; } +#if ZYNQMP_IPI_CRC_CHECK + for (j = 0; j < PAYLOAD_ARG_CNT; j++) + response_payload[j] = mmio_read_32(buffer_base + + (j * PAYLOAD_ARG_SIZE)); + + if (response_payload[PAYLOAD_CRC_POS] != + calculate_crc(response_payload, IPI_W0_TO_W6_SIZE)) + NOTICE("ERROR in CRC response payload value:0x%x\n", + response_payload[PAYLOAD_CRC_POS]); +#endif } /** @@ -228,3 +259,34 @@ uint32_t pm_ipi_irq_status(const struct pm_proc *proc) else return 0; } + +#if ZYNQMP_IPI_CRC_CHECK +uint32_t calculate_crc(uint32_t *payload, uint32_t bufsize) +{ + uint32_t crcinit = CRC_INIT_VALUE; + uint32_t order = CRC_ORDER; + uint32_t polynom = CRC_POLYNOM; + uint32_t i, j, c, bit, datain, crcmask, crchighbit; + uint32_t crc = crcinit; + + crcmask = ((uint32_t)((1U << (order - 1U)) - 1U) << 1U) | 1U; + crchighbit = (uint32_t)(1U << (order - 1U)); + + for (i = 0U; i < bufsize; i++) { + datain = mmio_read_8((unsigned long)payload + i); + c = datain; + j = 0x80U; + while (j != 0U) { + bit = crc & crchighbit; + crc <<= 1U; + if (0U != (c & j)) + bit ^= crchighbit; + if (bit != 0U) + crc ^= polynom; + j >>= 1U; + } + crc &= crcmask; + } + return crc; +} +#endif diff --git a/plat/xilinx/zynqmp/include/plat_pm_common.h b/plat/xilinx/zynqmp/include/plat_pm_common.h index 1b371cc36..56a747a4f 100644 --- a/plat/xilinx/zynqmp/include/plat_pm_common.h +++ b/plat/xilinx/zynqmp/include/plat_pm_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +16,16 @@ #include #include "pm_defs.h" -#define PAYLOAD_ARG_CNT 6U +#if ZYNQMP_IPI_CRC_CHECK +#define PAYLOAD_ARG_CNT 8U +#define IPI_W0_TO_W6_SIZE 28U +#define PAYLOAD_CRC_POS 7U +#define CRC_INIT_VALUE 0x4F4EU +#define CRC_ORDER 16U +#define CRC_POLYNOM 0x8005U +#else +#define PAYLOAD_ARG_CNT 6U +#endif #define PAYLOAD_ARG_SIZE 4U /* size in bytes */ #define ZYNQMP_TZ_VERSION_MAJOR 1 diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index c34a51674..1039e2751 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -9,6 +9,7 @@ PSCI_EXTENDED_STATE_ID := 1 A53_DISABLE_NON_TEMPORAL_HINT := 0 SEPARATE_CODE_AND_RODATA := 1 ZYNQMP_WDT_RESTART := 0 +ZYNQMP_IPI_CRC_CHECK := 0 override RESET_TO_BL31 := 1 # Do not enable SVE @@ -45,7 +46,12 @@ ifdef ZYNQMP_WDT_RESTART $(eval $(call add_define,ZYNQMP_WDT_RESTART)) endif -PLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64/ \ +ifdef ZYNQMP_IPI_CRC_CHECK + $(eval $(call add_define,ZYNQMP_IPI_CRC_CHECK)) +endif + +PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ + -Iinclude/plat/arm/common/aarch64/ \ -Iplat/xilinx/common/include/ \ -Iplat/xilinx/zynqmp/include/ \ -Iplat/xilinx/zynqmp/pm_service/ \ -- cgit v1.2.3 From 256d133a8a489b8731e5f499457468a4b8a13ab4 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 24 Sep 2018 22:51:49 -0700 Subject: plat: xilinx: zynqmp: Use GIC framework for warm restart - Flag GICV2_G0_FOR_EL3 needs to be set for group interrupts to be targeted to EL3. - Raise SGI interrupts for individual CPU cores as GIC API uses CPU num as parameter, not CPU mask. - Flag WARMBOOT_ENABLE_DCACHE_EARLY needs to be set to enable CPU interface mask work properly for all CPU cores which is required when generating SGI. - Call plat_ic_end_of_interrupt() from ttc_fiq_handler() to clear GIC interrupt to avoid same interrupt again. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: I71d4935b8d4688a3729c62753ca8a1a77cd92ae7 --- plat/xilinx/zynqmp/plat_psci.c | 5 ++--- plat/xilinx/zynqmp/platform.mk | 2 ++ plat/xilinx/zynqmp/pm_service/pm_svc_main.c | 10 ++++++++-- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c index a32e08988..f579f795f 100644 --- a/plat/xilinx/zynqmp/plat_psci.c +++ b/plat/xilinx/zynqmp/plat_psci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -100,9 +100,8 @@ static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); - + plat_arm_gic_pcpu_init(); gicv2_cpuif_enable(); - gicv2_pcpu_distif_init(); } static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index 1039e2751..33d648860 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -11,6 +11,8 @@ SEPARATE_CODE_AND_RODATA := 1 ZYNQMP_WDT_RESTART := 0 ZYNQMP_IPI_CRC_CHECK := 0 override RESET_TO_BL31 := 1 +override GICV2_G0_FOR_EL3 := 1 +override WARMBOOT_ENABLE_DCACHE_EARLY := 1 # Do not enable SVE ENABLE_SVE_FOR_NS := 0 diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c index 5a320f1ba..98dbe7d6e 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c +++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c @@ -77,8 +77,12 @@ static void trigger_wdt_restart(void) INFO("Active Cores: %d\n", active_cores); - /* trigger SGI to active cores */ - gicv2_raise_sgi(ARM_IRQ_SEC_SGI_7, target_cpu_list); + for (i = PLATFORM_CORE_COUNT - 1; i >= 0; i--) { + if (target_cpu_list & (1 << i)) { + /* trigger SGI to active cores */ + plat_ic_raise_el3_sgi(ARM_IRQ_SEC_SGI_7, i); + } + } } /** @@ -106,6 +110,8 @@ static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle, { INFO("BL31: Got TTC FIQ\n"); + plat_ic_end_of_interrupt(id); + /* Clear TTC interrupt by reading interrupt register */ mmio_read_32(TTC3_INTR_REGISTER_1); -- cgit v1.2.3 From d4821739ef36f8fda5504fa5c57e0c41f0e09c24 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Fri, 14 Dec 2018 00:55:29 -0800 Subject: plat: xilinx: versal: Move versal_private.h to include directory Move versal_private.h to platform specific include directory. Also, rename it to plat_private.h instead of having platform name. So, it can be used to common source files which needs platform specific data. Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: I65eefbea7722ffa2760b992491c00eebef5bcef4 --- plat/xilinx/versal/aarch64/versal_common.c | 5 ++--- plat/xilinx/versal/bl31_versal_setup.c | 6 ++---- plat/xilinx/versal/include/plat_private.h | 24 ++++++++++++++++++++++++ plat/xilinx/versal/plat_psci.c | 5 ++--- plat/xilinx/versal/plat_versal.c | 5 ++--- plat/xilinx/versal/versal_gicv3.c | 5 ++--- plat/xilinx/versal/versal_private.h | 24 ------------------------ 7 files changed, 34 insertions(+), 40 deletions(-) create mode 100644 plat/xilinx/versal/include/plat_private.h delete mode 100644 plat/xilinx/versal/versal_private.h diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c index 587b797d7..598079cba 100644 --- a/plat/xilinx/versal/aarch64/versal_common.c +++ b/plat/xilinx/versal/aarch64/versal_common.c @@ -1,17 +1,16 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include #include #include #include - #include "../versal_def.h" -#include "../versal_private.h" /* * Table of regions to map using the MMU. diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c index d7e07e036..0deff9006 100644 --- a/plat/xilinx/versal/bl31_versal_setup.c +++ b/plat/xilinx/versal/bl31_versal_setup.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include #include - +#include #include #include #include @@ -15,8 +15,6 @@ #include #include -#include "versal_private.h" - static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; static console_pl011_t versal_runtime_console; diff --git a/plat/xilinx/versal/include/plat_private.h b/plat/xilinx/versal/include/plat_private.h new file mode 100644 index 000000000..cb35be87e --- /dev/null +++ b/plat/xilinx/versal/include/plat_private.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PRIVATE_H +#define PLAT_PRIVATE_H + +#include + +void versal_config_setup(void); + +const mmap_region_t *plat_versal_get_mmap(void); + +void plat_versal_gic_driver_init(void); +void plat_versal_gic_init(void); +void plat_versal_gic_cpuif_enable(void); +void plat_versal_gic_cpuif_disable(void); +void plat_versal_gic_pcpu_init(void); + +unsigned int versal_calc_core_pos(u_register_t mpidr); + +#endif /* PLAT_PRIVATE_H */ diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c index 4a443697f..de581bd0b 100644 --- a/plat/xilinx/versal/plat_psci.c +++ b/plat/xilinx/versal/plat_psci.c @@ -1,16 +1,15 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include #include #include -#include "versal_private.h" - static uintptr_t versal_sec_entry; static int versal_nopmc_pwr_domain_on(u_register_t mpidr) diff --git a/plat/xilinx/versal/plat_versal.c b/plat/xilinx/versal/plat_versal.c index 642867da2..a080a76a9 100644 --- a/plat/xilinx/versal/plat_versal.c +++ b/plat/xilinx/versal/plat_versal.c @@ -1,13 +1,12 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include #include -#include "versal_private.h" - int plat_core_pos_by_mpidr(u_register_t mpidr) { if (mpidr & MPIDR_CLUSTER_MASK) diff --git a/plat/xilinx/versal/versal_gicv3.c b/plat/xilinx/versal/versal_gicv3.c index dcf23b425..08e7cf95a 100644 --- a/plat/xilinx/versal/versal_gicv3.c +++ b/plat/xilinx/versal/versal_gicv3.c @@ -1,9 +1,10 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include @@ -11,8 +12,6 @@ #include #include -#include "versal_private.h" - /****************************************************************************** * The following functions are defined as weak to allow a platform to override * the way the GICv3 driver is initialised and used. diff --git a/plat/xilinx/versal/versal_private.h b/plat/xilinx/versal/versal_private.h deleted file mode 100644 index 5d98d080c..000000000 --- a/plat/xilinx/versal/versal_private.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef VERSAL_PRIVATE_H -#define VERSAL_PRIVATE_H - -#include - -void versal_config_setup(void); - -const mmap_region_t *plat_versal_get_mmap(void); - -void plat_versal_gic_driver_init(void); -void plat_versal_gic_init(void); -void plat_versal_gic_cpuif_enable(void); -void plat_versal_gic_cpuif_disable(void); -void plat_versal_gic_pcpu_init(void); - -unsigned int versal_calc_core_pos(u_register_t mpidr); - -#endif /* VERSAL_PRIVATE_H */ -- cgit v1.2.3 From ab36d0970945986accaecc0cfe74f27edc16d031 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Fri, 14 Dec 2018 00:55:30 -0800 Subject: plat: xilinx: versal: Move versal_def.h to include directory Move versal_def.h to platform specific include directory. Also, update source file to include header file from updated path of versal_def.h Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: I313592a17552843b9cc7048f31bcaaefa40ffd91 --- plat/xilinx/versal/aarch64/versal_common.c | 2 +- plat/xilinx/versal/include/platform_def.h | 5 +- plat/xilinx/versal/include/versal_def.h | 109 +++++++++++++++++++++++++++++ plat/xilinx/versal/versal_def.h | 109 ----------------------------- 4 files changed, 112 insertions(+), 113 deletions(-) create mode 100644 plat/xilinx/versal/include/versal_def.h delete mode 100644 plat/xilinx/versal/versal_def.h diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c index 598079cba..0d7eefb43 100644 --- a/plat/xilinx/versal/aarch64/versal_common.c +++ b/plat/xilinx/versal/aarch64/versal_common.c @@ -4,13 +4,13 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include #include #include #include #include -#include "../versal_def.h" /* * Table of regions to map using the MMU. diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h index 0c4b9544f..e61929cc1 100644 --- a/plat/xilinx/versal/include/platform_def.h +++ b/plat/xilinx/versal/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,8 +8,7 @@ #define PLATFORM_DEF_H #include - -#include "../versal_def.h" +#include "versal_def.h" /******************************************************************************* * Generic platform constants diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h new file mode 100644 index 000000000..d4e388597 --- /dev/null +++ b/plat/xilinx/versal/include/versal_def.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VERSAL_DEF_H +#define VERSAL_DEF_H + +#include + +/* List all consoles */ +#define VERSAL_CONSOLE_ID_pl011 1 +#define VERSAL_CONSOLE_ID_pl011_0 1 +#define VERSAL_CONSOLE_ID_pl011_1 2 +#define VERSAL_CONSOLE_ID_dcc 3 + +#define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) + +/* List all supported platforms */ +#define VERSAL_PLATFORM_ID_versal_virt 1 + +#define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) + +/* Firmware Image Package */ +#define VERSAL_PRIMARY_CPU 0 + +/******************************************************************************* + * memory map related constants + ******************************************************************************/ +#define DEVICE0_BASE 0xFF000000 +#define DEVICE0_SIZE 0x00E00000 +#define DEVICE1_BASE 0xF9000000 +#define DEVICE1_SIZE 0x00800000 + +/* CRL */ +#define VERSAL_CRL 0xFF5E0000 +#define VERSAL_CRL_IOU_SWITCH_CTRL (VERSAL_CRL + 0x114) +#define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C) +#define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348) + +#define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25) +#define VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT (1 << 25) +#define VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 + +/* IOU SCNTRS */ +#define VERSAL_IOU_SCNTRS 0xFF140000 +#define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0) +#define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20) + +#define VERSAL_IOU_SCNTRS_CONTROL_EN 1 + +/******************************************************************************* + * IRQ constants + ******************************************************************************/ +#define VERSAL_IRQ_SEC_PHY_TIMER 29 + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define VERSAL_UART0_BASE 0xFF000000 +#define VERSAL_UART1_BASE 0xFF010000 + +#if VERSAL_CONSOLE_IS(pl011) +# define VERSAL_UART_BASE VERSAL_UART0_BASE +#elif VERSAL_CONSOLE_IS(pl011_1) +# define VERSAL_UART_BASE VERSAL_UART1_BASE +#else +# error "invalid VERSAL_CONSOLE" +#endif + +#define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE +#define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK +#define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE + +/******************************************************************************* + * Platform related constants + ******************************************************************************/ +#if VERSAL_PLATFORM_IS(versal_virt) +# define PLATFORM_NAME "Versal Virt" +# define VERSAL_UART_CLOCK 25000000 +# define VERSAL_UART_BAUDRATE 115200 +# define VERSAL_CPU_CLOCK 62500000 +#endif + +/* Access control register defines */ +#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) +#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) + +/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ +#define CRF_BASE 0xFD1A0000 +#define CRF_SIZE 0x00600000 + +/* CRF registers and bitfields */ +#define CRF_RST_APU (CRF_BASE + 0X00000300) + +#define CRF_RST_APU_ACPU_RESET (1 << 0) +#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) + +/* APU registers and bitfields */ +#define FPD_APU_BASE 0xFD5C0000 +#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20) +#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40) +#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44) +#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90) + +#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8 + +#endif /* VERSAL_DEF_H */ diff --git a/plat/xilinx/versal/versal_def.h b/plat/xilinx/versal/versal_def.h deleted file mode 100644 index 41c65b94d..000000000 --- a/plat/xilinx/versal/versal_def.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef VERSAL_DEF_H -#define VERSAL_DEF_H - -#include - -/* List all consoles */ -#define VERSAL_CONSOLE_ID_pl011 1 -#define VERSAL_CONSOLE_ID_pl011_0 1 -#define VERSAL_CONSOLE_ID_pl011_1 2 -#define VERSAL_CONSOLE_ID_dcc 3 - -#define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) - -/* List all supported platforms */ -#define VERSAL_PLATFORM_ID_versal_virt 1 - -#define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) - -/* Firmware Image Package */ -#define VERSAL_PRIMARY_CPU 0 - -/******************************************************************************* - * memory map related constants - ******************************************************************************/ -#define DEVICE0_BASE 0xFF000000 -#define DEVICE0_SIZE 0x00E00000 -#define DEVICE1_BASE 0xF9000000 -#define DEVICE1_SIZE 0x00800000 - -/* CRL */ -#define VERSAL_CRL 0xFF5E0000 -#define VERSAL_CRL_IOU_SWITCH_CTRL (VERSAL_CRL + 0x114) -#define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C) -#define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348) - -#define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25) -#define VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT (1 << 25) -#define VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 - -/* IOU SCNTRS */ -#define VERSAL_IOU_SCNTRS 0xFF140000 -#define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0) -#define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20) - -#define VERSAL_IOU_SCNTRS_CONTROL_EN 1 - -/******************************************************************************* - * IRQ constants - ******************************************************************************/ -#define VERSAL_IRQ_SEC_PHY_TIMER 29 - -/******************************************************************************* - * UART related constants - ******************************************************************************/ -#define VERSAL_UART0_BASE 0xFF000000 -#define VERSAL_UART1_BASE 0xFF010000 - -#if VERSAL_CONSOLE_IS(pl011) -# define VERSAL_UART_BASE VERSAL_UART0_BASE -#elif VERSAL_CONSOLE_IS(pl011_1) -# define VERSAL_UART_BASE VERSAL_UART1_BASE -#else -# error "invalid VERSAL_CONSOLE" -#endif - -#define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE -#define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK -#define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE - -/******************************************************************************* - * Platform related constants - ******************************************************************************/ -#if VERSAL_PLATFORM_IS(versal_virt) -# define PLATFORM_NAME "Versal Virt" -# define VERSAL_UART_CLOCK 25000000 -# define VERSAL_UART_BAUDRATE 115200 -# define VERSAL_CPU_CLOCK 62500000 -#endif - -/* Access control register defines */ -#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) -#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) - -/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ -#define CRF_BASE 0xFD1A0000 -#define CRF_SIZE 0x00600000 - -/* CRF registers and bitfields */ -#define CRF_RST_APU (CRF_BASE + 0X00000300) - -#define CRF_RST_APU_ACPU_RESET (1 << 0) -#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) - -/* APU registers and bitfields */ -#define FPD_APU_BASE 0xFD5C0000 -#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20) -#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40) -#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44) -#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90) - -#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8 - -#endif /* VERSAL_DEF_H */ -- cgit v1.2.3 From c73a90e571e763e3afc1d9cbef09e7d134b25af8 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Fri, 14 Dec 2018 00:55:37 -0800 Subject: xilinx: Add support to send PM API to PMC using IPI for versal Port ZynqMP PM services for versal to send PM APIs to PMC using IPI. Signed-off-by: Tejas Patel Signed-off-by: Wendy Liang Signed-off-by: Jolly Shah Change-Id: I27a52faf27f1a2919213498276a6885a177cb6da --- plat/xilinx/versal/aarch64/versal_common.c | 4 + plat/xilinx/versal/include/plat_ipi.h | 55 ++++++++ plat/xilinx/versal/include/plat_pm_common.h | 22 ++++ plat/xilinx/versal/include/versal_def.h | 15 +++ plat/xilinx/versal/platform.mk | 11 +- plat/xilinx/versal/pm_service/pm_client.c | 38 ++++++ plat/xilinx/versal/pm_service/pm_client.h | 21 +++ plat/xilinx/versal/pm_service/pm_defs.h | 55 ++++++++ plat/xilinx/versal/pm_service/pm_node.h | 192 ++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_svc_main.c | 42 ++++++ plat/xilinx/versal/pm_service/pm_svc_main.h | 14 ++ plat/xilinx/versal/sip_svc_setup.c | 6 +- plat/xilinx/versal/versal_ipi.c | 82 ++++++++++++ 13 files changed, 554 insertions(+), 3 deletions(-) create mode 100644 plat/xilinx/versal/include/plat_ipi.h create mode 100644 plat/xilinx/versal/include/plat_pm_common.h create mode 100644 plat/xilinx/versal/pm_service/pm_client.c create mode 100644 plat/xilinx/versal/pm_service/pm_client.h create mode 100644 plat/xilinx/versal/pm_service/pm_defs.h create mode 100644 plat/xilinx/versal/pm_service/pm_node.h create mode 100644 plat/xilinx/versal/pm_service/pm_svc_main.c create mode 100644 plat/xilinx/versal/pm_service/pm_svc_main.h create mode 100644 plat/xilinx/versal/versal_ipi.c diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c index 0d7eefb43..2c6ff0537 100644 --- a/plat/xilinx/versal/aarch64/versal_common.c +++ b/plat/xilinx/versal/aarch64/versal_common.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include #include @@ -38,6 +39,9 @@ void versal_config_setup(void) { uint32_t val; + /* Configure IPI data for versal */ + versal_ipi_config_table_init(); + versal_print_platform_name(); mmio_write_32(VERSAL_CRL_IOU_SWITCH_CTRL, diff --git a/plat/xilinx/versal/include/plat_ipi.h b/plat/xilinx/versal/include/plat_ipi.h new file mode 100644 index 000000000..6b08f322d --- /dev/null +++ b/plat/xilinx/versal/include/plat_ipi.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019, Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Versal IPI management enums and defines */ + +#ifndef PLAT_IPI_H +#define PLAT_IPI_H + +#include +#include + +/********************************************************************* + * IPI agent IDs macros + ********************************************************************/ +#define IPI_ID_PMC 1U +#define IPI_ID_APU 2U +#define IPI_ID_RPU0 3U +#define IPI_ID_RPU1 4U +#define IPI_ID_3 5U +#define IPI_ID_4 6U +#define IPI_ID_5 7U + +/********************************************************************* + * IPI message buffers + ********************************************************************/ +#define IPI_BUFFER_BASEADDR 0xFF3F0000U + +#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U) +#define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U) + +#define IPI_BUFFER_TARGET_APU_OFFSET 0x0U +#define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U + +#define IPI_BUFFER_LOCAL_BASE IPI_BUFFER_APU_BASE +#define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMC_BASE + +#define IPI_BUFFER_TARGET_LOCAL_OFFSET IPI_BUFFER_TARGET_APU_OFFSET +#define IPI_BUFFER_TARGET_REMOTE_OFFSET IPI_BUFFER_TARGET_PMC_OFFSET + +#define IPI_BUFFER_MAX_WORDS 8 + +#define IPI_BUFFER_REQ_OFFSET 0x0U +#define IPI_BUFFER_RESP_OFFSET 0x20U + +/********************************************************************* + * Platform specific IPI API declarations + ********************************************************************/ + +/* Configure IPI table for versal */ +void versal_ipi_config_table_init(void); + +#endif /* PLAT_IPI_H */ diff --git a/plat/xilinx/versal/include/plat_pm_common.h b/plat/xilinx/versal/include/plat_pm_common.h new file mode 100644 index 000000000..6b202c746 --- /dev/null +++ b/plat/xilinx/versal/include/plat_pm_common.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019, Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Contains platform specific definitions of commonly used macros data types + * for PU Power Management. This file should be common for all PU's. + */ + +#ifndef PLAT_PM_COMMON_H +#define PLAT_PM_COMMON_H + +#include +#include +#include "pm_defs.h" + +#define PAYLOAD_ARG_CNT 6U +#define PAYLOAD_ARG_SIZE 4U /* size in bytes */ + +#endif /* PLAT_PM_COMMON_H */ diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h index d4e388597..21883a1a9 100644 --- a/plat/xilinx/versal/include/versal_def.h +++ b/plat/xilinx/versal/include/versal_def.h @@ -106,4 +106,19 @@ #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8 +/* IPI registers and bitfields */ +#define IPI0_REG_BASE 0xFF330000 +#define IPI0_TRIG_BIT (1 << 2) +#define PMC_IPI_TRIG_BIT (1 << 1) +#define IPI1_REG_BASE 0xFF340000 +#define IPI1_TRIG_BIT (1 << 3) +#define IPI2_REG_BASE 0xFF350000 +#define IPI2_TRIG_BIT (1 << 4) +#define IPI3_REG_BASE 0xFF360000 +#define IPI3_TRIG_BIT (1 << 5) +#define IPI4_REG_BASE 0xFF370000 +#define IPI4_TRIG_BIT (1 << 5) +#define IPI5_REG_BASE 0xFF380000 +#define IPI5_TRIG_BIT (1 << 6) + #endif /* VERSAL_DEF_H */ diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk index 1c56364c8..190be328b 100644 --- a/plat/xilinx/versal/platform.mk +++ b/plat/xilinx/versal/platform.mk @@ -37,7 +37,9 @@ $(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFOR VERSAL_CONSOLE ?= pl011 $(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE})) -PLAT_INCLUDES := -Iplat/xilinx/versal/include/ +PLAT_INCLUDES := -Iplat/xilinx/common/include/ \ + -Iplat/xilinx/versal/include/ \ + -Iplat/xilinx/versal/pm_service/ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ lib/xlat_tables/aarch64/xlat_tables.c \ @@ -55,9 +57,14 @@ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a72.S \ plat/common/plat_psci_common.c \ + plat/xilinx/common/ipi.c \ + plat/xilinx/common/pm_service/pm_ipi.c \ plat/xilinx/versal/bl31_versal_setup.c \ plat/xilinx/versal/plat_psci.c \ plat/xilinx/versal/plat_versal.c \ plat/xilinx/versal/plat_topology.c \ plat/xilinx/versal/sip_svc_setup.c \ - plat/xilinx/versal/versal_gicv3.c + plat/xilinx/versal/versal_gicv3.c \ + plat/xilinx/versal/versal_ipi.c \ + plat/xilinx/versal/pm_service/pm_svc_main.c \ + plat/xilinx/versal/pm_service/pm_client.c diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c new file mode 100644 index 000000000..6183b7822 --- /dev/null +++ b/plat/xilinx/versal/pm_service/pm_client.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2019, Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * APU specific definition of processors in the subsystem as well as functions + * for getting information about and changing state of the APU. + */ + +#include +#include +#include +#include +#include "pm_client.h" + +DEFINE_BAKERY_LOCK(pm_client_secure_lock); + +static const struct pm_ipi apu_ipi = { + .local_ipi_id = IPI_ID_APU, + .remote_ipi_id = IPI_ID_PMC, + .buffer_base = IPI_BUFFER_APU_BASE, +}; + +/* Order in pm_procs_all array must match cpu ids */ +static const struct pm_proc pm_procs_all[] = { + { + .node_id = XPM_DEVID_ACPU_0, + .ipi = &apu_ipi, + }, + { + .node_id = XPM_DEVID_ACPU_1, + .ipi = &apu_ipi, + } +}; + +const struct pm_proc *primary_proc = &pm_procs_all[0]; diff --git a/plat/xilinx/versal/pm_service/pm_client.h b/plat/xilinx/versal/pm_service/pm_client.h new file mode 100644 index 000000000..6840bb1dd --- /dev/null +++ b/plat/xilinx/versal/pm_service/pm_client.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2019, Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Contains APU specific macros and macros to be defined depending on + * the execution environment. + */ + +#ifndef PM_CLIENT_H +#define PM_CLIENT_H + +#include "pm_common.h" +#include "pm_defs.h" + +/* Global variables to be set in pm_client.c */ +extern const struct pm_proc *primary_proc; + +#endif /* PM_CLIENT_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h new file mode 100644 index 000000000..c435b7ada --- /dev/null +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019, Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Versal power management enums and defines */ + +#ifndef PM_DEFS_H +#define PM_DEFS_H + +#include "pm_node.h" + +/********************************************************************* + * Macro definitions + ********************************************************************/ + +/* Processor core device IDs */ +#define APU_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \ + XPM_NODETYPE_DEV_CORE_APU, (IDX)) + +#define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0) +#define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1) + +/********************************************************************* + * Enum definitions + ********************************************************************/ + +/** + * @PM_RET_SUCCESS: success + * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated) + * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated) + * @PM_RET_ERROR_INTERNAL: internal error + * @PM_RET_ERROR_CONFLICT: conflict + * @PM_RET_ERROR_ACCESS: access rights violation + * @PM_RET_ERROR_INVALID_NODE: invalid node + * @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node + * @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted + * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU + * @PM_RET_ERROR_NODE_USED: node is already in use + */ +enum pm_ret_status { + PM_RET_SUCCESS, + PM_RET_ERROR_ARGS = 1, + PM_RET_ERROR_NOTSUPPORTED = 4, + PM_RET_ERROR_INTERNAL = 2000, + PM_RET_ERROR_CONFLICT = 2001, + PM_RET_ERROR_ACCESS = 2002, + PM_RET_ERROR_INVALID_NODE = 2003, + PM_RET_ERROR_DOUBLE_REQ = 2004, + PM_RET_ERROR_ABORT_SUSPEND = 2005, + PM_RET_ERROR_TIMEOUT = 2006, + PM_RET_ERROR_NODE_USED = 2007 +}; +#endif /* PM_DEFS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_node.h b/plat/xilinx/versal/pm_service/pm_node.h new file mode 100644 index 000000000..1b82ec70d --- /dev/null +++ b/plat/xilinx/versal/pm_service/pm_node.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2019, Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Versal PM nodes enums and defines */ + +#ifndef PM_NODE_H +#define PM_NODE_H + +/********************************************************************* + * Macro definitions + ********************************************************************/ + +#define NODE_CLASS_SHIFT 26U +#define NODE_SUBCLASS_SHIFT 20U +#define NODE_TYPE_SHIFT 14U +#define NODE_INDEX_SHIFT 0U +#define NODE_CLASS_MASK_BITS 0x3F +#define NODE_SUBCLASS_MASK_BITS 0x3F +#define NODE_TYPE_MASK_BITS 0x3F +#define NODE_INDEX_MASK_BITS 0x3FFF +#define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT) +#define NODE_SUBCLASS_MASK (NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT) +#define NODE_TYPE_MASK (NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT) +#define NODE_INDEX_MASK (NODE_INDEX_MASK_BITS << NODE_INDEX_SHIFT) + +#define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \ + ((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \ + (((SUBCLASS) & NODE_SUBCLASS_MASK_BITS) << NODE_SUBCLASS_SHIFT) | \ + (((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \ + (((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT)) + +#define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT) +#define NODESUBCLASS(ID) (((ID) & NODE_SUBCLASS_MASK) >> \ + NODE_SUBCLASS_SHIFT) +#define NODETYPE(ID) (((ID) & NODE_TYPE_MASK) >> NODE_TYPE_SHIFT) +#define NODEINDEX(ID) (((ID) & NODE_INDEX_MASK) >> NODE_INDEX_SHIFT) + +/********************************************************************* + * Enum definitions + ********************************************************************/ + +/* Node class types */ +enum pm_node_class { + XPM_NODECLASS_MIN, + + XPM_NODECLASS_POWER, + XPM_NODECLASS_CLOCK, + XPM_NODECLASS_RESET, + XPM_NODECLASS_MEMIC, + XPM_NODECLASS_STMIC, + XPM_NODECLASS_DEVICE, + + XPM_NODECLASS_MAX +}; + +enum pm_device_node_subclass { + /* Device types */ + XPM_NODESUBCL_DEV_CORE = 1, + XPM_NODESUBCL_DEV_PERIPH, + XPM_NODESUBCL_DEV_MEM, + XPM_NODESUBCL_DEV_SOC, + XPM_NODESUBCL_DEV_MEM_CTRLR, + XPM_NODESUBCL_DEV_PHY, +}; + +enum pm_device_node_type { + /* Device types */ + XPM_NODETYPE_DEV_CORE_PMC = 1, + XPM_NODETYPE_DEV_CORE_PSM, + XPM_NODETYPE_DEV_CORE_APU, + XPM_NODETYPE_DEV_CORE_RPU, + XPM_NODETYPE_DEV_OCM, + XPM_NODETYPE_DEV_TCM, + XPM_NODETYPE_DEV_L2CACHE, + XPM_NODETYPE_DEV_DDR, + XPM_NODETYPE_DEV_PERIPH, + XPM_NODETYPE_DEV_SOC, + XPM_NODETYPE_DEV_GT, +}; + +/* Device node Indexes */ +enum pm_device_node_idx { + /* Device nodes */ + XPM_NODEIDX_DEV_MIN, + + /* Processor devices */ + XPM_NODEIDX_DEV_PMC_PROC, + XPM_NODEIDX_DEV_PSM_PROC, + XPM_NODEIDX_DEV_ACPU_0, + XPM_NODEIDX_DEV_ACPU_1, + XPM_NODEIDX_DEV_RPU0_0, + XPM_NODEIDX_DEV_RPU0_1, + + /* Memory devices */ + XPM_NODEIDX_DEV_OCM_0, + XPM_NODEIDX_DEV_OCM_1, + XPM_NODEIDX_DEV_OCM_2, + XPM_NODEIDX_DEV_OCM_3, + XPM_NODEIDX_DEV_TCM_0_A, + XPM_NODEIDX_DEV_TCM_0_B, + XPM_NODEIDX_DEV_TCM_1_A, + XPM_NODEIDX_DEV_TCM_1_B, + XPM_NODEIDX_DEV_L2_BANK_0, + XPM_NODEIDX_DEV_DDR_0, + XPM_NODEIDX_DEV_DDR_1, + XPM_NODEIDX_DEV_DDR_2, + XPM_NODEIDX_DEV_DDR_3, + XPM_NODEIDX_DEV_DDR_4, + XPM_NODEIDX_DEV_DDR_5, + XPM_NODEIDX_DEV_DDR_6, + XPM_NODEIDX_DEV_DDR_7, + + /* LPD Peripheral devices */ + XPM_NODEIDX_DEV_USB_0, + XPM_NODEIDX_DEV_GEM_0, + XPM_NODEIDX_DEV_GEM_1, + XPM_NODEIDX_DEV_SPI_0, + XPM_NODEIDX_DEV_SPI_1, + XPM_NODEIDX_DEV_I2C_0, + XPM_NODEIDX_DEV_I2C_1, + XPM_NODEIDX_DEV_CAN_FD_0, + XPM_NODEIDX_DEV_CAN_FD_1, + XPM_NODEIDX_DEV_UART_0, + XPM_NODEIDX_DEV_UART_1, + XPM_NODEIDX_DEV_GPIO, + XPM_NODEIDX_DEV_TTC_0, + XPM_NODEIDX_DEV_TTC_1, + XPM_NODEIDX_DEV_TTC_2, + XPM_NODEIDX_DEV_TTC_3, + XPM_NODEIDX_DEV_SWDT_LPD, + + /* FPD Peripheral devices */ + XPM_NODEIDX_DEV_SWDT_FPD, + + /* PMC Peripheral devices */ + XPM_NODEIDX_DEV_OSPI, + XPM_NODEIDX_DEV_QSPI, + XPM_NODEIDX_DEV_GPIO_PMC, + XPM_NODEIDX_DEV_I2C_PMC, + XPM_NODEIDX_DEV_SDIO_0, + XPM_NODEIDX_DEV_SDIO_1, + + XPM_NODEIDX_DEV_PL_0, + XPM_NODEIDX_DEV_PL_1, + XPM_NODEIDX_DEV_PL_2, + XPM_NODEIDX_DEV_PL_3, + XPM_NODEIDX_DEV_RTC, + XPM_NODEIDX_DEV_ADMA_0, + XPM_NODEIDX_DEV_ADMA_1, + XPM_NODEIDX_DEV_ADMA_2, + XPM_NODEIDX_DEV_ADMA_3, + XPM_NODEIDX_DEV_ADMA_4, + XPM_NODEIDX_DEV_ADMA_5, + XPM_NODEIDX_DEV_ADMA_6, + XPM_NODEIDX_DEV_ADMA_7, + XPM_NODEIDX_DEV_IPI_0, + XPM_NODEIDX_DEV_IPI_1, + XPM_NODEIDX_DEV_IPI_2, + XPM_NODEIDX_DEV_IPI_3, + XPM_NODEIDX_DEV_IPI_4, + XPM_NODEIDX_DEV_IPI_5, + XPM_NODEIDX_DEV_IPI_6, + + /* Entire SoC */ + XPM_NODEIDX_DEV_SOC, + + /* DDR memory controllers */ + XPM_NODEIDX_DEV_DDRMC_0, + XPM_NODEIDX_DEV_DDRMC_1, + XPM_NODEIDX_DEV_DDRMC_2, + XPM_NODEIDX_DEV_DDRMC_3, + + /* GT devices */ + XPM_NODEIDX_DEV_GT_0, + XPM_NODEIDX_DEV_GT_1, + XPM_NODEIDX_DEV_GT_2, + XPM_NODEIDX_DEV_GT_3, + XPM_NODEIDX_DEV_GT_4, + XPM_NODEIDX_DEV_GT_5, + XPM_NODEIDX_DEV_GT_6, + XPM_NODEIDX_DEV_GT_7, + XPM_NODEIDX_DEV_GT_8, + XPM_NODEIDX_DEV_GT_9, + XPM_NODEIDX_DEV_GT_10, + + XPM_NODEIDX_DEV_MAX +}; + +#endif /* PM_NODE_H */ diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c new file mode 100644 index 000000000..a1c457fa1 --- /dev/null +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2019, Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Top-level SMC handler for Versal power management calls and + * IPI setup functions for communication with PMC. + */ + +#include +#include +#include "pm_client.h" +#include "pm_ipi.h" + +/** + * pm_setup() - PM service setup + * + * @return On success, the initialization function must return 0. + * Any other return value will cause the framework to ignore + * the service + * + * Initialization functions for Versal power management for + * communicaton with PMC. + * + * Called from sip_svc_setup initialization function with the + * rt_svc_init signature. + */ +int pm_setup(void) +{ + int status, ret = 0; + + status = pm_ipi_init(primary_proc); + + if (status < 0) { + INFO("BL31: PM Service Init Failed, Error Code %d!\n", status); + ret = status; + } + + return ret; +} diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.h b/plat/xilinx/versal/pm_service/pm_svc_main.h new file mode 100644 index 000000000..ec279b642 --- /dev/null +++ b/plat/xilinx/versal/pm_service/pm_svc_main.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2019, Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PM_SVC_MAIN_H +#define PM_SVC_MAIN_H + +#include + +int pm_setup(void); + +#endif /* PM_SVC_MAIN_H */ diff --git a/plat/xilinx/versal/sip_svc_setup.c b/plat/xilinx/versal/sip_svc_setup.c index 8f2180b21..6437bbf2c 100644 --- a/plat/xilinx/versal/sip_svc_setup.c +++ b/plat/xilinx/versal/sip_svc_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include #include #include +#include "pm_svc_main.h" /* SMC function IDs for SiP Service queries */ #define VERSAL_SIP_SVC_CALL_COUNT 0x8200ff00 @@ -36,6 +37,9 @@ DEFINE_SVC_UUID2(versal_sip_uuid, */ static int32_t sip_svc_setup(void) { + /* PM implementation as SiP Service */ + pm_setup(); + return 0; } diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c new file mode 100644 index 000000000..27541ff4b --- /dev/null +++ b/plat/xilinx/versal/versal_ipi.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2019, Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Versal IPI agent registers access management + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* versal ipi configuration table */ +const static struct ipi_config versal_ipi_table[] = { + /* A72 IPI */ + [IPI_ID_APU] = { + .ipi_bit_mask = IPI0_TRIG_BIT, + .ipi_reg_base = IPI0_REG_BASE, + .secure_only = 0, + }, + + /* PMC IPI */ + [IPI_ID_PMC] = { + .ipi_bit_mask = PMC_IPI_TRIG_BIT, + .ipi_reg_base = IPI0_REG_BASE, + .secure_only = 0, + }, + + /* RPU0 IPI */ + [IPI_ID_RPU0] = { + .ipi_bit_mask = IPI1_TRIG_BIT, + .ipi_reg_base = IPI1_REG_BASE, + .secure_only = 0, + }, + + /* RPU1 IPI */ + [IPI_ID_RPU1] = { + .ipi_bit_mask = IPI2_TRIG_BIT, + .ipi_reg_base = IPI2_REG_BASE, + .secure_only = 0, + }, + + /* IPI3 IPI */ + [IPI_ID_3] = { + .ipi_bit_mask = IPI3_TRIG_BIT, + .ipi_reg_base = IPI3_REG_BASE, + .secure_only = 0, + }, + + /* IPI4 IPI */ + [IPI_ID_4] = { + .ipi_bit_mask = IPI4_TRIG_BIT, + .ipi_reg_base = IPI4_REG_BASE, + .secure_only = 0, + }, + + /* IPI5 IPI */ + [IPI_ID_5] = { + .ipi_bit_mask = IPI5_TRIG_BIT, + .ipi_reg_base = IPI5_REG_BASE, + .secure_only = 0, + }, +}; + +/* versal_ipi_config_table_init() - Initialize versal IPI configuration data + * + * @ipi_config_table - IPI configuration table + * @ipi_total - Total number of IPI available + * + */ +void versal_ipi_config_table_init(void) +{ + ipi_config_table_init(versal_ipi_table, ARRAY_SIZE(versal_ipi_table)); +} -- cgit v1.2.3 From 95794c732367ff2bc595f9226d70bb8d6eaaa1d8 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Tue, 8 Jan 2019 01:46:35 -0800 Subject: xilinx: versal: Add get_api_version support Add support for EEMI API get_api_verion. Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: Ic1ef90a194ae6164994a7fc5d8ff0b7b192636fe --- plat/xilinx/versal/platform.mk | 1 + plat/xilinx/versal/pm_service/pm_api_sys.c | 45 ++++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 18 ++++++++++++ plat/xilinx/versal/pm_service/pm_defs.h | 3 ++ 4 files changed, 67 insertions(+) create mode 100644 plat/xilinx/versal/pm_service/pm_api_sys.c create mode 100644 plat/xilinx/versal/pm_service/pm_api_sys.h diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk index 190be328b..eb1f0bb61 100644 --- a/plat/xilinx/versal/platform.mk +++ b/plat/xilinx/versal/platform.mk @@ -67,4 +67,5 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ plat/xilinx/versal/versal_gicv3.c \ plat/xilinx/versal/versal_ipi.c \ plat/xilinx/versal/pm_service/pm_svc_main.c \ + plat/xilinx/versal/pm_service/pm_api_sys.c \ plat/xilinx/versal/pm_service/pm_client.c diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c new file mode 100644 index 000000000..618624e88 --- /dev/null +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2019, Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Versal system level PM-API functions and communication with PMC via + * IPI interrupts + */ + +#include +#include +#include "pm_api_sys.h" +#include "pm_client.h" + +/********************************************************************* + * Target module IDs macros + ********************************************************************/ +#define LIBPM_MODULE_ID 0x2 +#define LOADER_MODULE_ID 0x7 + +/** + * Assigning of argument values into array elements. + */ +#define PM_PACK_PAYLOAD1(pl, mid, arg0) { \ + pl[0] = (uint32_t)((uint32_t)((arg0) & 0xFF) | (mid << 8)); \ +} + +/* PM API functions */ + +/** + * pm_get_api_version() - Get version number of PMC PM firmware + * @version Returns 32-bit version number of PMC Power Management Firmware + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_get_api_version(unsigned int *version) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD1(payload, LIBPM_MODULE_ID, PM_GET_API_VERSION); + return pm_ipi_send_sync(primary_proc, payload, version, 1); +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h new file mode 100644 index 000000000..59f39524d --- /dev/null +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2019, Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PM_API_SYS_H +#define PM_API_SYS_H + +#include + +/********************************************************** + * PM API function declarations + **********************************************************/ + +enum pm_ret_status pm_get_api_version(unsigned int *version); + +#endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index c435b7ada..ff3d26603 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -22,6 +22,9 @@ #define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0) #define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1) +/* PM API ids */ +#define PM_GET_API_VERSION 1U + /********************************************************************* * Enum definitions ********************************************************************/ -- cgit v1.2.3 From fbb32695a27536818004e60772bd4240ae3cec1b Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Sun, 8 Dec 2019 23:29:44 -0800 Subject: xilinx: versal: Add support for suspend related APIs Add support for below suspend related APIs. - self_suspend - abort_suspend - request_suspend Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: If568e0cd33b64754fe66f66fc0cdd0ec62c1b32e --- plat/xilinx/versal/include/versal_def.h | 2 + plat/xilinx/versal/pm_service/pm_api_sys.c | 115 +++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 10 +++ plat/xilinx/versal/pm_service/pm_client.c | 57 ++++++++++++++ plat/xilinx/versal/pm_service/pm_client.h | 4 + plat/xilinx/versal/pm_service/pm_defs.h | 10 +++ 6 files changed, 198 insertions(+) diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h index 21883a1a9..a77fa30d0 100644 --- a/plat/xilinx/versal/include/versal_def.h +++ b/plat/xilinx/versal/include/versal_def.h @@ -105,6 +105,8 @@ #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90) #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8 +#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 +#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 /* IPI registers and bitfields */ #define IPI0_REG_BASE 0xFF330000 diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 618624e88..16c2541b9 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -11,6 +11,7 @@ #include #include +#include #include "pm_api_sys.h" #include "pm_client.h" @@ -27,6 +28,31 @@ pl[0] = (uint32_t)((uint32_t)((arg0) & 0xFF) | (mid << 8)); \ } +#define PM_PACK_PAYLOAD2(pl, mid, arg0, arg1) { \ + pl[1] = (uint32_t)(arg1); \ + PM_PACK_PAYLOAD1(pl, mid, arg0); \ +} + +#define PM_PACK_PAYLOAD3(pl, mid, arg0, arg1, arg2) { \ + pl[2] = (uint32_t)(arg2); \ + PM_PACK_PAYLOAD2(pl, mid, arg0, arg1); \ +} + +#define PM_PACK_PAYLOAD4(pl, mid, arg0, arg1, arg2, arg3) { \ + pl[3] = (uint32_t)(arg3); \ + PM_PACK_PAYLOAD3(pl, mid, arg0, arg1, arg2); \ +} + +#define PM_PACK_PAYLOAD5(pl, mid, arg0, arg1, arg2, arg3, arg4) { \ + pl[4] = (uint32_t)(arg4); \ + PM_PACK_PAYLOAD4(pl, mid, arg0, arg1, arg2, arg3); \ +} + +#define PM_PACK_PAYLOAD6(pl, mid, arg0, arg1, arg2, arg3, arg4, arg5) { \ + pl[5] = (uint32_t)(arg5); \ + PM_PACK_PAYLOAD5(pl, mid, arg0, arg1, arg2, arg3, arg4); \ +} + /* PM API functions */ /** @@ -43,3 +69,92 @@ enum pm_ret_status pm_get_api_version(unsigned int *version) PM_PACK_PAYLOAD1(payload, LIBPM_MODULE_ID, PM_GET_API_VERSION); return pm_ipi_send_sync(primary_proc, payload, version, 1); } + +/** + * pm_self_suspend() - PM call for processor to suspend itself + * @nid Node id of the processor or subsystem + * @latency Requested maximum wakeup latency (not supported) + * @state Requested state + * @address Resume address + * + * This is a blocking call, it will return only once PMU has responded. + * On a wakeup, resume address will be automatically set by PMU. + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_self_suspend(uint32_t nid, + unsigned int latency, + unsigned int state, + uintptr_t address) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + unsigned int cpuid = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpuid); + + if (!proc) { + WARN("Failed to get proc %d\n", cpuid); + return PM_RET_ERROR_INTERNAL; + } + + /* + * Do client specific suspend operations + * (e.g. set powerdown request bit) + */ + pm_client_suspend(proc, state); + + /* Send request to the PLM */ + PM_PACK_PAYLOAD6(payload, LIBPM_MODULE_ID, PM_SELF_SUSPEND, + proc->node_id, latency, state, address, + (address >> 32)); + return pm_ipi_send_sync(proc, payload, NULL, 0); +} + +/** + * pm_abort_suspend() - PM call to announce that a prior suspend request + * is to be aborted. + * @reason Reason for the abort + * + * Calling PU expects the PMU to abort the initiated suspend procedure. + * This is a non-blocking call without any acknowledge. + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* + * Do client specific abort suspend operations + * (e.g. enable interrupts and clear powerdown request bit) + */ + pm_client_abort_suspend(); + + /* Send request to the PLM */ + PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_ABORT_SUSPEND, reason, + primary_proc->node_id); + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_req_suspend() - PM call to request for another PU or subsystem to + * be suspended gracefully. + * @target Node id of the targeted PU or subsystem + * @ack Flag to specify whether acknowledge is requested + * @latency Requested wakeup latency (not supported) + * @state Requested state (not supported) + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_req_suspend(uint32_t target, uint8_t ack, + unsigned int latency, unsigned int state) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, PM_REQ_SUSPEND, target, + latency, state); + if (ack == IPI_BLOCKING) + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); + else + return pm_ipi_send(primary_proc, payload); +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 59f39524d..f67682329 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -8,11 +8,21 @@ #define PM_API_SYS_H #include +#include "pm_defs.h" /********************************************************** * PM API function declarations **********************************************************/ enum pm_ret_status pm_get_api_version(unsigned int *version); +enum pm_ret_status pm_self_suspend(uint32_t nid, + unsigned int latency, + unsigned int state, + uintptr_t address); +enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason); +enum pm_ret_status pm_req_suspend(uint32_t target, + uint8_t ack, + unsigned int latency, + unsigned int state); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c index 6183b7822..636b719fd 100644 --- a/plat/xilinx/versal/pm_service/pm_client.c +++ b/plat/xilinx/versal/pm_service/pm_client.c @@ -13,6 +13,9 @@ #include #include #include +#include +#include +#include #include "pm_client.h" DEFINE_BAKERY_LOCK(pm_client_secure_lock); @@ -28,11 +31,65 @@ static const struct pm_proc pm_procs_all[] = { { .node_id = XPM_DEVID_ACPU_0, .ipi = &apu_ipi, + .pwrdn_mask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK, }, { .node_id = XPM_DEVID_ACPU_1, .ipi = &apu_ipi, + .pwrdn_mask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK, } }; const struct pm_proc *primary_proc = &pm_procs_all[0]; + +/** + * pm_client_suspend() - Client-specific suspend actions + * + * This function should contain any PU-specific actions + * required prior to sending suspend request to PMU + * Actions taken depend on the state system is suspending to. + */ +void pm_client_suspend(const struct pm_proc *proc, unsigned int state) +{ + bakery_lock_get(&pm_client_secure_lock); + + /* Set powerdown request */ + mmio_write_32(FPD_APU_PWRCTL, mmio_read_32(FPD_APU_PWRCTL) | + proc->pwrdn_mask); + + bakery_lock_release(&pm_client_secure_lock); +} + +/** + * pm_client_abort_suspend() - Client-specific abort-suspend actions + * + * This function should contain any PU-specific actions + * required for aborting a prior suspend request + */ +void pm_client_abort_suspend(void) +{ + /* Enable interrupts at processor level (for current cpu) */ + gicv3_cpuif_enable(plat_my_core_pos()); + + bakery_lock_get(&pm_client_secure_lock); + + /* Clear powerdown request */ + mmio_write_32(FPD_APU_PWRCTL, mmio_read_32(FPD_APU_PWRCTL) & + ~primary_proc->pwrdn_mask); + + bakery_lock_release(&pm_client_secure_lock); +} + +/** + * pm_get_proc() - returns pointer to the proc structure + * @cpuid: id of the cpu whose proc struct pointer should be returned + * + * Return: pointer to a proc structure if proc is found, otherwise NULL + */ +const struct pm_proc *pm_get_proc(unsigned int cpuid) +{ + if (cpuid < ARRAY_SIZE(pm_procs_all)) + return &pm_procs_all[cpuid]; + + return NULL; +} diff --git a/plat/xilinx/versal/pm_service/pm_client.h b/plat/xilinx/versal/pm_service/pm_client.h index 6840bb1dd..228094e67 100644 --- a/plat/xilinx/versal/pm_service/pm_client.h +++ b/plat/xilinx/versal/pm_service/pm_client.h @@ -15,6 +15,10 @@ #include "pm_common.h" #include "pm_defs.h" +/* Functions to be implemented by each PU */ +void pm_client_suspend(const struct pm_proc *proc, unsigned int state); +void pm_client_abort_suspend(void); + /* Global variables to be set in pm_client.c */ extern const struct pm_proc *primary_proc; diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index ff3d26603..d482cb75a 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -24,11 +24,21 @@ /* PM API ids */ #define PM_GET_API_VERSION 1U +#define PM_REQ_SUSPEND 6U +#define PM_SELF_SUSPEND 7U +#define PM_ABORT_SUSPEND 9U /********************************************************************* * Enum definitions ********************************************************************/ +enum pm_abort_reason { + ABORT_REASON_WKUP_EVENT = 100, + ABORT_REASON_PU_BUSY, + ABORT_REASON_NO_PWRDN, + ABORT_REASON_UNKNOWN, +}; + /** * @PM_RET_SUCCESS: success * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated) -- cgit v1.2.3 From cf1e56a4e74752f3ee7e2953ebd2ebb4ed8f9e20 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Tue, 8 Jan 2019 01:46:37 -0800 Subject: xilinx: versal: Implement device related PM APIs Implement below device related PM APIs: - Request device - Release device - Set requirement - Get device status Signed-off-by: Tejas Patel Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Jolly Shah Change-Id: I9d84b9ee1be3ee6c5f27a4d6dc324113fc1acb68 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 77 ++++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 6 +++ plat/xilinx/versal/pm_service/pm_defs.h | 20 ++++++++ 3 files changed, 103 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 16c2541b9..64c1e3503 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -158,3 +158,80 @@ enum pm_ret_status pm_req_suspend(uint32_t target, uint8_t ack, else return pm_ipi_send(primary_proc, payload); } + +/** + * pm_request_device() - Request a device + * @device_id Device ID + * @capabilities Requested capabilities for the device + * @qos Required Quality of Service + * @ack Flag to specify whether acknowledge requested + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_request_device(uint32_t device_id, uint32_t capabilities, + uint32_t qos, uint32_t ack) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_REQUEST_DEVICE, + device_id, capabilities, qos, ack); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_release_device() - Release a device + * @device_id Device ID + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_release_device(uint32_t device_id) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_RELEASE_DEVICE, + device_id); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_set_requirement() - Set requirement for the device + * @device_id Device ID + * @capabilities Requested capabilities for the device + * @latency Requested maximum latency + * @qos Required Quality of Service + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_set_requirement(uint32_t device_id, uint32_t capabilities, + uint32_t latency, uint32_t qos) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_SET_REQUIREMENT, + device_id, capabilities, latency, qos); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_get_device_status() - Get device's status + * @device_id Device ID + * @response Buffer to store device status response + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_get_device_status(uint32_t device_id, uint32_t *response) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_GET_DEVICE_STATUS, + device_id); + + return pm_ipi_send_sync(primary_proc, payload, response, 3); +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index f67682329..6e50e94b9 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -24,5 +24,11 @@ enum pm_ret_status pm_req_suspend(uint32_t target, uint8_t ack, unsigned int latency, unsigned int state); +enum pm_ret_status pm_request_device(uint32_t device_id, uint32_t capabilities, + uint32_t qos, uint32_t ack); +enum pm_ret_status pm_release_device(uint32_t device_id); +enum pm_ret_status pm_set_requirement(uint32_t device_id, uint32_t capabilities, + uint32_t latency, uint32_t qos); +enum pm_ret_status pm_get_device_status(uint32_t device_id, uint32_t *response); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index d482cb75a..feaeee120 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -24,9 +24,13 @@ /* PM API ids */ #define PM_GET_API_VERSION 1U +#define PM_GET_DEVICE_STATUS 3U #define PM_REQ_SUSPEND 6U #define PM_SELF_SUSPEND 7U #define PM_ABORT_SUSPEND 9U +#define PM_REQUEST_DEVICE 13U +#define PM_RELEASE_DEVICE 14U +#define PM_SET_REQUIREMENT 15U /********************************************************************* * Enum definitions @@ -39,6 +43,22 @@ enum pm_abort_reason { ABORT_REASON_UNKNOWN, }; +/** + * Subsystem IDs + */ +typedef enum { + XPM_SUBSYSID_PMC, + XPM_SUBSYSID_PSM, + XPM_SUBSYSID_APU, + XPM_SUBSYSID_RPU0_LOCK, + XPM_SUBSYSID_RPU0_0, + XPM_SUBSYSID_RPU0_1, + XPM_SUBSYSID_DDR0, + XPM_SUBSYSID_ME, + XPM_SUBSYSID_PL, + XPM_SUBSYSID_MAX, +} XPm_SubsystemId; + /** * @PM_RET_SUCCESS: success * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated) -- cgit v1.2.3 From 9c3c5e0737c91f5523f93797a2b38b9477f241b7 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Tue, 8 Jan 2019 01:46:38 -0800 Subject: xilinx: versal: Implement reset related PM APIs Implement below reset related APIs: - Reset assert - Get reset status Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: Id42c9d3950a0d69125cb0eab79b75e5d22674f14 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 35 ++++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 2 ++ plat/xilinx/versal/pm_service/pm_defs.h | 2 ++ 3 files changed, 39 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 64c1e3503..51f1c2d4d 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -235,3 +235,38 @@ enum pm_ret_status pm_get_device_status(uint32_t device_id, uint32_t *response) return pm_ipi_send_sync(primary_proc, payload, response, 3); } + +/** + * pm_reset_assert() - Assert/De-assert reset + * @reset Reset ID + * @assert Assert (1) or de-assert (0) + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_reset_assert(uint32_t reset, bool assert) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_RESET_ASSERT, reset, + assert); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_reset_get_status() - Get current status of a reset line + * @reset Reset ID + * @status Returns current status of selected reset ID + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_reset_get_status(uint32_t reset, uint32_t *status) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_RESET_ASSERT, reset); + + return pm_ipi_send_sync(primary_proc, payload, status, 1); +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 6e50e94b9..28e5504a7 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -30,5 +30,7 @@ enum pm_ret_status pm_release_device(uint32_t device_id); enum pm_ret_status pm_set_requirement(uint32_t device_id, uint32_t capabilities, uint32_t latency, uint32_t qos); enum pm_ret_status pm_get_device_status(uint32_t device_id, uint32_t *response); +enum pm_ret_status pm_reset_assert(uint32_t reset, bool assert); +enum pm_ret_status pm_reset_get_status(uint32_t reset, uint32_t *status); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index feaeee120..1b8871f7f 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -31,6 +31,8 @@ #define PM_REQUEST_DEVICE 13U #define PM_RELEASE_DEVICE 14U #define PM_SET_REQUIREMENT 15U +#define PM_RESET_ASSERT 17U +#define PM_RESET_GET_STATUS 18U /********************************************************************* * Enum definitions -- cgit v1.2.3 From 0ed83c621c7eb8460806fff48c573f3d293b37ad Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Tue, 8 Jan 2019 01:46:39 -0800 Subject: xilinx: versal: Implement pin control related PM APIs Implement below pin control related APIs: - Request pin - Release pin - Set pin function - Get pin function - Set pin parameter value - Get pin parameter value Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: Ib805cc8c936b63206d44bf1f7bebd0f03f7b3c01 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 108 +++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 8 +++ plat/xilinx/versal/pm_service/pm_defs.h | 6 ++ 3 files changed, 122 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 51f1c2d4d..149f2c8a9 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -270,3 +270,111 @@ enum pm_ret_status pm_reset_get_status(uint32_t reset, uint32_t *status) return pm_ipi_send_sync(primary_proc, payload, status, 1); } + +/** + * pm_pinctrl_request() - Request a pin + * @pin Pin ID + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_pinctrl_request(uint32_t pin) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_PINCTRL_REQUEST, pin); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_pinctrl_release() - Release a pin + * @pin Pin ID + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_pinctrl_release(uint32_t pin) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_PINCTRL_RELEASE, pin); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_pinctrl_set_function() - Set pin function + * @pin Pin ID + * @function Function ID + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_pinctrl_set_function(uint32_t pin, uint32_t function) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_PINCTRL_SET_FUNCTION, pin, + function) + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_pinctrl_get_function() - Get function set on the pin + * @pin Pin ID + * @function Function set on the pin + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_pinctrl_get_function(uint32_t pin, uint32_t *function) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_PINCTRL_SET_FUNCTION, + pin); + + return pm_ipi_send_sync(primary_proc, payload, function, 1); +} + +/** + * pm_pinctrl_set_pin_param() - Set configuration parameter for the pin + * @pin Pin ID + * @param Parameter ID + * @value Parameter value + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_pinctrl_set_pin_param(uint32_t pin, uint32_t param, + uint32_t value) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, PM_PINCTRL_CONFIG_PARAM_SET, + pin, param, value); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_pinctrl_get_pin_param() - Get configuration parameter value for the pin + * @pin Pin ID + * @param Parameter ID + * @value Buffer to store parameter value + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_pinctrl_get_pin_param(uint32_t pin, uint32_t param, + uint32_t *value) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_PINCTRL_CONFIG_PARAM_GET, + pin, param); + + return pm_ipi_send_sync(primary_proc, payload, value, 1); +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 28e5504a7..c3f26515a 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -32,5 +32,13 @@ enum pm_ret_status pm_set_requirement(uint32_t device_id, uint32_t capabilities, enum pm_ret_status pm_get_device_status(uint32_t device_id, uint32_t *response); enum pm_ret_status pm_reset_assert(uint32_t reset, bool assert); enum pm_ret_status pm_reset_get_status(uint32_t reset, uint32_t *status); +enum pm_ret_status pm_pinctrl_request(uint32_t pin); +enum pm_ret_status pm_pinctrl_release(uint32_t pin); +enum pm_ret_status pm_pinctrl_set_function(uint32_t pin, uint32_t function); +enum pm_ret_status pm_pinctrl_get_function(uint32_t pin, uint32_t *function); +enum pm_ret_status pm_pinctrl_set_pin_param(uint32_t pin, uint32_t param, + uint32_t value); +enum pm_ret_status pm_pinctrl_get_pin_param(uint32_t pin, uint32_t param, + uint32_t *value); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index 1b8871f7f..8a42663ed 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -33,6 +33,12 @@ #define PM_SET_REQUIREMENT 15U #define PM_RESET_ASSERT 17U #define PM_RESET_GET_STATUS 18U +#define PM_PINCTRL_REQUEST 28U +#define PM_PINCTRL_RELEASE 29U +#define PM_PINCTRL_GET_FUNCTION 30U +#define PM_PINCTRL_SET_FUNCTION 31U +#define PM_PINCTRL_CONFIG_PARAM_GET 32U +#define PM_PINCTRL_CONFIG_PARAM_SET 33U /********************************************************************* * Enum definitions -- cgit v1.2.3 From 2394b94bfd05292f81fd5ec3d66a2d5ca51ab3a0 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Tue, 8 Jan 2019 01:46:40 -0800 Subject: xilinx: versal: Implement clock related PM APIs Implement below clock related APIs: - Clock enable - Clock disable - Clock get status - Clock set divider - Clock get divider - Clock set parent - Clock get parent Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: Ibb3606e88ac6796d9d759226908b2c2997c5fea0 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 119 +++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 7 ++ plat/xilinx/versal/pm_service/pm_defs.h | 9 +++ 3 files changed, 135 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 149f2c8a9..8ac9a1d0d 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -378,3 +378,122 @@ enum pm_ret_status pm_pinctrl_get_pin_param(uint32_t pin, uint32_t param, return pm_ipi_send_sync(primary_proc, payload, value, 1); } + +/** + * pm_clock_enable() - Enable the clock + * @clk_id Clock ID + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_clock_enable(uint32_t clk_id) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_ENABLE, clk_id); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_clock_disable() - Disable the clock + * @clk_id Clock ID + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_clock_disable(uint32_t clk_id) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_DISABLE, clk_id); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_clock_get_state() - Get clock status + * @clk_id Clock ID + * @state: Buffer to store clock status (1: Enabled, 0:Disabled) + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_clock_get_state(uint32_t clk_id, uint32_t *state) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_GETSTATE, clk_id); + + return pm_ipi_send_sync(primary_proc, payload, state, 1); +} + +/** + * pm_clock_set_divider() - Set divider for the clock + * @clk_id Clock ID + * @divider Divider value + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_clock_set_divider(uint32_t clk_id, uint32_t divider) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_CLOCK_SETDIVIDER, clk_id, + divider); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_clock_get_divider() - Get divider value for the clock + * @clk_id Clock ID + * @divider: Buffer to store clock divider value + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_clock_get_divider(uint32_t clk_id, uint32_t *divider) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_GETDIVIDER, clk_id); + + return pm_ipi_send_sync(primary_proc, payload, divider, 1); +} + +/** + * pm_clock_set_parent() - Set parent for the clock + * @clk_id Clock ID + * @parent Parent ID + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_clock_set_parent(uint32_t clk_id, uint32_t parent) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_CLOCK_SETPARENT, clk_id, + parent); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_clock_get_parent() - Get parent value for the clock + * @clk_id Clock ID + * @parent: Buffer to store clock parent value + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_GETPARENT, clk_id); + + return pm_ipi_send_sync(primary_proc, payload, parent, 1); +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index c3f26515a..a91895cca 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -40,5 +40,12 @@ enum pm_ret_status pm_pinctrl_set_pin_param(uint32_t pin, uint32_t param, uint32_t value); enum pm_ret_status pm_pinctrl_get_pin_param(uint32_t pin, uint32_t param, uint32_t *value); +enum pm_ret_status pm_clock_enable(uint32_t clk_id); +enum pm_ret_status pm_clock_disable(uint32_t clk_id); +enum pm_ret_status pm_clock_get_state(uint32_t clk_id, uint32_t *state); +enum pm_ret_status pm_clock_set_divider(uint32_t clk_id, uint32_t divider); +enum pm_ret_status pm_clock_get_divider(uint32_t clk_id, uint32_t *divider); +enum pm_ret_status pm_clock_set_parent(uint32_t clk_id, uint32_t parent); +enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index 8a42663ed..e9aa51286 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -39,6 +39,15 @@ #define PM_PINCTRL_SET_FUNCTION 31U #define PM_PINCTRL_CONFIG_PARAM_GET 32U #define PM_PINCTRL_CONFIG_PARAM_SET 33U +#define PM_CLOCK_ENABLE 36U +#define PM_CLOCK_DISABLE 37U +#define PM_CLOCK_GETSTATE 38U +#define PM_CLOCK_SETDIVIDER 39U +#define PM_CLOCK_GETDIVIDER 40U +#define PM_CLOCK_SETRATE 41U +#define PM_CLOCK_GETRATE 42U +#define PM_CLOCK_SETPARENT 43U +#define PM_CLOCK_GETPARENT 44U /********************************************************************* * Enum definitions -- cgit v1.2.3 From baccc60e8b79fef7e34f067facebcb166119f69b Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Tue, 8 Jan 2019 01:46:41 -0800 Subject: xilinx: versal: Implement PLL related PM APIs Implement below PLL related APIs: - Set PLL parameter - Get PLL parameter - Set PLL mode - Get PLL mode Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: I37749d05cdb73641d32da120d319cf36df97c73f --- plat/xilinx/versal/pm_service/pm_api_sys.c | 75 ++++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 6 +++ plat/xilinx/versal/pm_service/pm_defs.h | 4 ++ 3 files changed, 85 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 8ac9a1d0d..1b32e4bd9 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -497,3 +497,78 @@ enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent) return pm_ipi_send_sync(primary_proc, payload, parent, 1); } + +/** + * pm_pll_set_param() - Set PLL parameter + * @clk_id PLL clock ID + * @param PLL parameter ID + * @value Value to set for PLL parameter + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param, + uint32_t value) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, PM_PLL_SET_PARAMETER, clk_id, + param, value); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_pll_get_param() - Get PLL parameter value + * @clk_id PLL clock ID + * @param PLL parameter ID + * @value: Buffer to store PLL parameter value + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param, + uint32_t *value) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_PLL_GET_PARAMETER, clk_id, + param); + + return pm_ipi_send_sync(primary_proc, payload, value, 1); +} + +/** + * pm_pll_set_mode() - Set PLL mode + * @clk_id PLL clock ID + * @mode PLL mode + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_PLL_SET_MODE, clk_id, + mode); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + +/** + * pm_pll_get_mode() - Get PLL mode + * @clk_id PLL clock ID + * @mode: Buffer to store PLL mode + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_PLL_GET_MODE, clk_id); + + return pm_ipi_send_sync(primary_proc, payload, mode, 1); +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index a91895cca..025255bda 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -47,5 +47,11 @@ enum pm_ret_status pm_clock_set_divider(uint32_t clk_id, uint32_t divider); enum pm_ret_status pm_clock_get_divider(uint32_t clk_id, uint32_t *divider); enum pm_ret_status pm_clock_set_parent(uint32_t clk_id, uint32_t parent); enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent); +enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param, + uint32_t value); +enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param, + uint32_t *value); +enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode); +enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index e9aa51286..ce2605a14 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -48,6 +48,10 @@ #define PM_CLOCK_GETRATE 42U #define PM_CLOCK_SETPARENT 43U #define PM_CLOCK_GETPARENT 44U +#define PM_PLL_SET_PARAMETER 48U +#define PM_PLL_GET_PARAMETER 49U +#define PM_PLL_SET_MODE 50U +#define PM_PLL_GET_MODE 51U /********************************************************************* * Enum definitions -- cgit v1.2.3 From ab43d15b9137cf8def6d97ee878d60cad48ae770 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Wed, 9 Jan 2019 04:10:29 -0800 Subject: xilinx: versal: Add SMC handler for EEMI API Add SMC handler for EEMI API calls coming from EL1/EL2. Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: If0ef2a1f2cfc2747be6b91828371bcbec56b1e15 --- plat/xilinx/versal/pm_service/pm_svc_main.c | 203 ++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_svc_main.h | 3 + plat/xilinx/versal/sip_svc_setup.c | 6 + 3 files changed, 212 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index a1c457fa1..5dd315799 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -11,9 +11,15 @@ #include #include +#include +#include +#include "pm_api_sys.h" #include "pm_client.h" #include "pm_ipi.h" +/* pm_up = true - UP, pm_up = false - DOWN */ +static bool pm_up; + /** * pm_setup() - PM service setup * @@ -36,7 +42,204 @@ int pm_setup(void) if (status < 0) { INFO("BL31: PM Service Init Failed, Error Code %d!\n", status); ret = status; + } else { + pm_up = true; } return ret; } + +/** + * pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2. + * @smc_fid - Function Identifier + * @x1 - x4 - Arguments + * @cookie - Unused + * @handler - Pointer to caller's context structure + * + * @return - Unused + * + * Determines that smc_fid is valid and supported PM SMC Function ID from the + * list of pm_api_ids, otherwise completes the request with + * the unknown SMC Function ID + * + * The SMC calls for PM service are forwarded from SIP Service SMC handler + * function with rt_svc_handle signature + */ +uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, void *handle, uint64_t flags) +{ + enum pm_ret_status ret; + + uint32_t pm_arg[4]; + + /* Handle case where PM wasn't initialized properly */ + if (!pm_up) + SMC_RET1(handle, SMC_UNK); + + pm_arg[0] = (uint32_t)x1; + pm_arg[1] = (uint32_t)(x1 >> 32); + pm_arg[2] = (uint32_t)x2; + pm_arg[3] = (uint32_t)(x2 >> 32); + + switch (smc_fid & FUNCID_NUM_MASK) { + /* PM API Functions */ + case PM_SELF_SUSPEND: + ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2], + pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_REQ_SUSPEND: + ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2], + pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_ABORT_SUSPEND: + ret = pm_abort_suspend(pm_arg[0]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_REQUEST_DEVICE: + ret = pm_request_device(pm_arg[0], pm_arg[1], pm_arg[2], + pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_RELEASE_DEVICE: + ret = pm_release_device(pm_arg[0]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_SET_REQUIREMENT: + ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2], + pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_GET_API_VERSION: + { + uint32_t api_version; + + ret = pm_get_api_version(&api_version); + SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | + ((uint64_t)api_version << 32)); + } + + case PM_GET_DEVICE_STATUS: + { + uint32_t buff[3]; + + ret = pm_get_device_status(pm_arg[0], buff); + SMC_RET2(handle, (uint64_t)ret | ((uint64_t)buff[0] << 32), + (uint64_t)buff[1] | ((uint64_t)buff[2] << 32)); + } + + case PM_RESET_ASSERT: + ret = pm_reset_assert(pm_arg[0], pm_arg[1]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_RESET_GET_STATUS: + { + uint32_t reset_status; + + ret = pm_reset_get_status(pm_arg[0], &reset_status); + SMC_RET1(handle, (uint64_t)ret | + ((uint64_t)reset_status << 32)); + } + + case PM_PINCTRL_REQUEST: + ret = pm_pinctrl_request(pm_arg[0]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_PINCTRL_RELEASE: + ret = pm_pinctrl_release(pm_arg[0]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_PINCTRL_GET_FUNCTION: + { + uint32_t value = 0; + + ret = pm_pinctrl_get_function(pm_arg[0], &value); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + } + + case PM_PINCTRL_SET_FUNCTION: + ret = pm_pinctrl_set_function(pm_arg[0], pm_arg[1]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_PINCTRL_CONFIG_PARAM_GET: + { + uint32_t value; + + ret = pm_pinctrl_get_pin_param(pm_arg[0], pm_arg[1], &value); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + } + + case PM_PINCTRL_CONFIG_PARAM_SET: + ret = pm_pinctrl_set_pin_param(pm_arg[0], pm_arg[1], pm_arg[2]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_CLOCK_ENABLE: + ret = pm_clock_enable(pm_arg[0]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_CLOCK_DISABLE: + ret = pm_clock_disable(pm_arg[0]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_CLOCK_GETSTATE: + { + uint32_t value; + + ret = pm_clock_get_state(pm_arg[0], &value); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + } + + case PM_CLOCK_SETDIVIDER: + ret = pm_clock_set_divider(pm_arg[0], pm_arg[1]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_CLOCK_GETDIVIDER: + { + uint32_t value; + + ret = pm_clock_get_divider(pm_arg[0], &value); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + } + + case PM_CLOCK_SETPARENT: + ret = pm_clock_set_parent(pm_arg[0], pm_arg[1]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_CLOCK_GETPARENT: + { + uint32_t value; + + ret = pm_clock_get_parent(pm_arg[0], &value); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + } + + case PM_PLL_SET_PARAMETER: + ret = pm_pll_set_param(pm_arg[0], pm_arg[1], pm_arg[2]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_PLL_GET_PARAMETER: + { + uint32_t value; + + ret = pm_pll_get_param(pm_arg[0], pm_arg[1], &value); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32)); + } + + case PM_PLL_SET_MODE: + ret = pm_pll_set_mode(pm_arg[0], pm_arg[1]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_PLL_GET_MODE: + { + uint32_t mode; + + ret = pm_pll_get_mode(pm_arg[0], &mode); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32)); + } + + default: + WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.h b/plat/xilinx/versal/pm_service/pm_svc_main.h index ec279b642..71329ca93 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.h +++ b/plat/xilinx/versal/pm_service/pm_svc_main.h @@ -10,5 +10,8 @@ #include int pm_setup(void); +uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, void *handle, + uint64_t flags); #endif /* PM_SVC_MAIN_H */ diff --git a/plat/xilinx/versal/sip_svc_setup.c b/plat/xilinx/versal/sip_svc_setup.c index 6437bbf2c..404c496a7 100644 --- a/plat/xilinx/versal/sip_svc_setup.c +++ b/plat/xilinx/versal/sip_svc_setup.c @@ -58,6 +58,12 @@ uintptr_t sip_svc_smc_handler(uint32_t smc_fid, void *handle, u_register_t flags) { + /* Let PM SMC handler deal with PM-related requests */ + if (is_pm_fid(smc_fid)) { + return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, + flags); + } + /* Let PM SMC handler deal with PM-related requests */ switch (smc_fid) { case VERSAL_SIP_SVC_CALL_COUNT: -- cgit v1.2.3 From ffecfe79fb4a1ae6c5d637bccfa4ddb3dd2b59d5 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Thu, 10 Jan 2019 03:03:47 -0800 Subject: xilinx: versal: Implement power down/restart related EEMI API Add power down/restart related below API - Force power down - System shutdown Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: Icd4a922923b1fd50eca1f5361f1e604aedcdb529 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 40 +++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 2 ++ plat/xilinx/versal/pm_service/pm_defs.h | 2 ++ plat/xilinx/versal/pm_service/pm_svc_main.c | 8 ++++++ 4 files changed, 52 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 1b32e4bd9..be28a41ae 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -572,3 +572,43 @@ enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode) return pm_ipi_send_sync(primary_proc, payload, mode, 1); } + +/** + * pm_force_powerdown() - PM call to request for another PU or subsystem to + * be powered down forcefully + * @target Device ID of the PU node to be forced powered down. + * @ack Flag to specify whether acknowledge is requested + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_FORCE_POWERDOWN, target, + ack); + + if (ack == IPI_BLOCKING) + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); + else + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_system_shutdown() - PM call to request a system shutdown or restart + * @type Shutdown or restart? 0=shutdown, 1=restart + * @subtype Scope: 0=APU-subsystem, 1=PS, 2=system + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_SYSTEM_SHUTDOWN, type, + subtype); + + return pm_ipi_send_non_blocking(primary_proc, payload); +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 025255bda..375199549 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -53,5 +53,7 @@ enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param, uint32_t *value); enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode); enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode); +enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack); +enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index ce2605a14..248c7151f 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -27,7 +27,9 @@ #define PM_GET_DEVICE_STATUS 3U #define PM_REQ_SUSPEND 6U #define PM_SELF_SUSPEND 7U +#define PM_FORCE_POWERDOWN 8U #define PM_ABORT_SUSPEND 9U +#define PM_SYSTEM_SHUTDOWN 12U #define PM_REQUEST_DEVICE 13U #define PM_RELEASE_DEVICE 14U #define PM_SET_REQUIREMENT 15U diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index 5dd315799..aa008ac9b 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -88,6 +88,10 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, pm_arg[3]); SMC_RET1(handle, (uint64_t)ret); + case PM_FORCE_POWERDOWN: + ret = pm_force_powerdown(pm_arg[0], pm_arg[1]); + SMC_RET1(handle, (uint64_t)ret); + case PM_REQ_SUSPEND: ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); @@ -97,6 +101,10 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, ret = pm_abort_suspend(pm_arg[0]); SMC_RET1(handle, (uint64_t)ret); + case PM_SYSTEM_SHUTDOWN: + ret = pm_system_shutdown(pm_arg[0], pm_arg[1]); + SMC_RET1(handle, (uint64_t)ret); + case PM_REQUEST_DEVICE: ret = pm_request_device(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); -- cgit v1.2.3 From d62fa4bcb1e2e82a34053b66a9ec367c2f6c85de Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Thu, 10 Jan 2019 03:03:48 -0800 Subject: plat: xilinx: versal: Implement PM IOCTL API Add PM IOCTL EEMI. Below PLL related IOCTLs are not available in versal PLM. * IOCTL_SET_PLL_FRAC_MODE * IOCTL_GET_PLL_FRAC_MODE * IOCTL_SET_PLL_FRAC_DATA * IOCTL_SET_PLL_FRAC_DATA PLM has new EEMI APIs for PLL related operations. Call them instead of passing IOCTL API to PLM. For other IOCTL, ATF just pass through IOCTL request to PLM (Platform Loader and Manager). Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: I96f8da46a4d3965c9291b7b2da96056408137839 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 34 +++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 2 ++ plat/xilinx/versal/pm_service/pm_defs.h | 11 ++++++++++ plat/xilinx/versal/pm_service/pm_svc_main.c | 9 ++++++++ 4 files changed, 56 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index be28a41ae..dd69f0679 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -612,3 +612,37 @@ enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype) return pm_ipi_send_non_blocking(primary_proc, payload); } + +/** + * pm_api_ioctl() - PM IOCTL API for device control and configs + * @device_id Device ID + * @ioctl_id ID of the requested IOCTL + * @arg1 Argument 1 to requested IOCTL call + * @arg2 Argument 2 to requested IOCTL call + * @value Returned output value + * + * This function calls IOCTL to firmware for device control and configuration. + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_api_ioctl(uint32_t device_id, uint32_t ioctl_id, + uint32_t arg1, uint32_t arg2, uint32_t *value) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + switch (ioctl_id) { + case IOCTL_SET_PLL_FRAC_MODE: + return pm_pll_set_mode(arg1, arg2); + case IOCTL_GET_PLL_FRAC_MODE: + return pm_pll_get_mode(arg1, value); + case IOCTL_SET_PLL_FRAC_DATA: + return pm_pll_set_param(arg1, PM_PLL_PARAM_DATA, arg2); + case IOCTL_GET_PLL_FRAC_DATA: + return pm_pll_get_param(arg1, PM_PLL_PARAM_DATA, value); + default: + /* Send request to the PMC */ + PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_IOCTL, device_id, + ioctl_id, arg1, arg2); + return pm_ipi_send_sync(primary_proc, payload, value, 1); + } +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 375199549..04074b18e 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -55,5 +55,7 @@ enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode); enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode); enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack); enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype); +enum pm_ret_status pm_api_ioctl(uint32_t device_id, uint32_t ioctl_id, + uint32_t arg1, uint32_t arg2, uint32_t *value); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index 248c7151f..fa3506607 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -41,6 +41,7 @@ #define PM_PINCTRL_SET_FUNCTION 31U #define PM_PINCTRL_CONFIG_PARAM_GET 32U #define PM_PINCTRL_CONFIG_PARAM_SET 33U +#define PM_IOCTL 34U #define PM_CLOCK_ENABLE 36U #define PM_CLOCK_DISABLE 37U #define PM_CLOCK_GETSTATE 38U @@ -55,6 +56,16 @@ #define PM_PLL_SET_MODE 50U #define PM_PLL_GET_MODE 51U +/* IOCTL IDs for clock driver */ +#define IOCTL_SET_PLL_FRAC_MODE 8 +#define IOCTL_GET_PLL_FRAC_MODE 9 +#define IOCTL_SET_PLL_FRAC_DATA 10 +#define IOCTL_GET_PLL_FRAC_DATA 11 + +/* Parameter ID for PLL IOCTLs */ +/* Fractional data portion for PLL */ +#define PM_PLL_PARAM_DATA 2 + /********************************************************************* * Enum definitions ********************************************************************/ diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index aa008ac9b..3aac79a86 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -182,6 +182,15 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, ret = pm_pinctrl_set_pin_param(pm_arg[0], pm_arg[1], pm_arg[2]); SMC_RET1(handle, (uint64_t)ret); + case PM_IOCTL: + { + uint32_t value; + + ret = pm_api_ioctl(pm_arg[0], pm_arg[1], pm_arg[2], + pm_arg[3], &value); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + } + case PM_CLOCK_ENABLE: ret = pm_clock_enable(pm_arg[0]); SMC_RET1(handle, (uint64_t)ret); -- cgit v1.2.3 From 26f1534ebdd5c91eb3581eae06dac78ba9043b95 Mon Sep 17 00:00:00 2001 From: Wendy Liang Date: Mon, 21 Jan 2019 13:45:48 +0530 Subject: xilinx: move ipi mailbox svc to xilinx common As IPI mailbox service is common to both ZynqMP and Versal, move it to xilinx/common. Signed-off-by: Wendy Liang Signed-off-by: Jolly Shah Change-Id: I1a7008ccf7930829621147922d2c6d8d46df5502 --- .../common/ipi_mailbox_service/ipi_mailbox_svc.c | 133 +++++++++++++++++++++ .../common/ipi_mailbox_service/ipi_mailbox_svc.h | 39 ++++++ .../zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c | 133 --------------------- .../zynqmp/ipi_mailbox_service/ipi_mailbox_svc.h | 39 ------ plat/xilinx/zynqmp/platform.mk | 10 +- 5 files changed, 179 insertions(+), 175 deletions(-) create mode 100644 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c create mode 100644 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.h delete mode 100644 plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c delete mode 100644 plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.h diff --git a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c new file mode 100644 index 000000000..f53115885 --- /dev/null +++ b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Top-level SMC handler for ZynqMP IPI Mailbox doorbell functions. + */ + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "ipi_mailbox_svc.h" +#include "../../../services/spd/trusty/smcall.h" + +/********************************************************************* + * Macros definitions + ********************************************************************/ + +/* IPI SMC calls macros: */ +#define IPI_SMC_OPEN_IRQ_MASK 0x00000001U /* IRQ enable bit in IPI + * open SMC call + */ +#define IPI_SMC_NOTIFY_BLOCK_MASK 0x00000001U /* Flag to indicate if + * IPI notification needs + * to be blocking. + */ +#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x00000001U /* Flag to indicate if + * notification interrupt + * to be disabled. + */ +#define IPI_SMC_ACK_EIRQ_MASK 0x00000001U /* Flag to indicate if + * notification interrupt + * to be enable. + */ + +#define UNSIGNED32_MASK 0xFFFFFFFFU /* 32bit mask */ + +/** + * ipi_smc_handler() - SMC handler for IPI SMC calls + * + * @smc_fid - Function identifier + * @x1 - x4 - Arguments + * @cookie - Unused + * @handler - Pointer to caller's context structure + * + * @return - Unused + * + * Determines that smc_fid is valid and supported PM SMC Function ID from the + * list of pm_api_ids, otherwise completes the request with + * the unknown SMC Function ID + * + * The SMC calls for PM service are forwarded from SIP Service SMC handler + * function with rt_svc_handle signature + */ +uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, + uint64_t x3, uint64_t x4, void *cookie, + void *handle, uint64_t flags) +{ + int ret; + uint32_t ipi_local_id; + uint32_t ipi_remote_id; + unsigned int is_secure; + + ipi_local_id = x1 & UNSIGNED32_MASK; + ipi_remote_id = x2 & UNSIGNED32_MASK; + + if (SMC_ENTITY(smc_fid) >= SMC_ENTITY_TRUSTED_APP) + is_secure = 1; + else + is_secure = 0; + + /* Validate IPI mailbox access */ + ret = ipi_mb_validate(ipi_local_id, ipi_remote_id, is_secure); + if (ret) + SMC_RET1(handle, ret); + + switch (SMC_FUNCTION(smc_fid)) { + case IPI_MAILBOX_OPEN: + ipi_mb_open(ipi_local_id, ipi_remote_id); + SMC_RET1(handle, 0); + case IPI_MAILBOX_RELEASE: + ipi_mb_release(ipi_local_id, ipi_remote_id); + SMC_RET1(handle, 0); + case IPI_MAILBOX_STATUS_ENQUIRY: + { + int disable_irq; + + disable_irq = (x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) ? 1 : 0; + ret = ipi_mb_enquire_status(ipi_local_id, ipi_remote_id); + if ((ret & IPI_MB_STATUS_RECV_PENDING) && disable_irq) + ipi_mb_disable_irq(ipi_local_id, ipi_remote_id); + SMC_RET1(handle, ret); + } + case IPI_MAILBOX_NOTIFY: + { + uint32_t is_blocking; + + is_blocking = (x3 & IPI_SMC_NOTIFY_BLOCK_MASK) ? 1 : 0; + ipi_mb_notify(ipi_local_id, ipi_remote_id, is_blocking); + SMC_RET1(handle, 0); + } + case IPI_MAILBOX_ACK: + { + int enable_irq; + + enable_irq = (x3 & IPI_SMC_ACK_EIRQ_MASK) ? 1 : 0; + ipi_mb_ack(ipi_local_id, ipi_remote_id); + if (enable_irq) + ipi_mb_enable_irq(ipi_local_id, ipi_remote_id); + SMC_RET1(handle, 0); + } + case IPI_MAILBOX_ENABLE_IRQ: + ipi_mb_enable_irq(ipi_local_id, ipi_remote_id); + SMC_RET1(handle, 0); + case IPI_MAILBOX_DISABLE_IRQ: + ipi_mb_disable_irq(ipi_local_id, ipi_remote_id); + SMC_RET1(handle, 0); + default: + WARN("Unimplemented IPI service call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} diff --git a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.h b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.h new file mode 100644 index 000000000..10682d835 --- /dev/null +++ b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* ZynqMP IPI mailbox doorbell service enums and defines */ + +#ifndef IPI_MAILBOX_SVC_H +#define IPI_MAILBOX_SVC_H + +#include + +/********************************************************************* + * Enum definitions + ********************************************************************/ + +/* IPI SMC function numbers enum definition */ +enum ipi_api_id { + /* IPI mailbox operations functions: */ + IPI_MAILBOX_OPEN = 0x1000, + IPI_MAILBOX_RELEASE, + IPI_MAILBOX_STATUS_ENQUIRY, + IPI_MAILBOX_NOTIFY, + IPI_MAILBOX_ACK, + IPI_MAILBOX_ENABLE_IRQ, + IPI_MAILBOX_DISABLE_IRQ +}; + +/********************************************************************* + * IPI mailbox service APIs declarations + ********************************************************************/ + +/* IPI SMC handler */ +uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, + uint64_t x3, uint64_t x4, void *cookie, void *handle, + uint64_t flags); + +#endif /* IPI_MAILBOX_SVC_H */ diff --git a/plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c b/plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c deleted file mode 100644 index c499d78e9..000000000 --- a/plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * Top-level SMC handler for ZynqMP IPI Mailbox doorbell functions. - */ - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "ipi_mailbox_svc.h" -#include "../../../services/spd/trusty/smcall.h" - -/********************************************************************* - * Macros definitions - ********************************************************************/ - -/* IPI SMC calls macros: */ -#define IPI_SMC_OPEN_IRQ_MASK 0x00000001U /* IRQ enable bit in IPI - * open SMC call - */ -#define IPI_SMC_NOTIFY_BLOCK_MASK 0x00000001U /* Flag to indicate if - * IPI notification needs - * to be blocking. - */ -#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x00000001U /* Flag to indicate if - * notification interrupt - * to be disabled. - */ -#define IPI_SMC_ACK_EIRQ_MASK 0x00000001U /* Flag to indicate if - * notification interrupt - * to be enable. - */ - -#define UNSIGNED32_MASK 0xFFFFFFFFU /* 32bit mask */ - -/** - * ipi_smc_handler() - SMC handler for IPI SMC calls - * - * @smc_fid - Function identifier - * @x1 - x4 - Arguments - * @cookie - Unused - * @handler - Pointer to caller's context structure - * - * @return - Unused - * - * Determines that smc_fid is valid and supported PM SMC Function ID from the - * list of pm_api_ids, otherwise completes the request with - * the unknown SMC Function ID - * - * The SMC calls for PM service are forwarded from SIP Service SMC handler - * function with rt_svc_handle signature - */ -uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, - uint64_t x3, uint64_t x4, void *cookie, - void *handle, uint64_t flags) -{ - int ret; - uint32_t ipi_local_id; - uint32_t ipi_remote_id; - unsigned int is_secure; - - ipi_local_id = x1 & UNSIGNED32_MASK; - ipi_remote_id = x2 & UNSIGNED32_MASK; - - if (SMC_ENTITY(smc_fid) >= SMC_ENTITY_TRUSTED_APP) - is_secure = 1; - else - is_secure = 0; - - /* Validate IPI mailbox access */ - ret = ipi_mb_validate(ipi_local_id, ipi_remote_id, is_secure); - if (ret) - SMC_RET1(handle, ret); - - switch (SMC_FUNCTION(smc_fid)) { - case IPI_MAILBOX_OPEN: - ipi_mb_open(ipi_local_id, ipi_remote_id); - SMC_RET1(handle, 0); - case IPI_MAILBOX_RELEASE: - ipi_mb_release(ipi_local_id, ipi_remote_id); - SMC_RET1(handle, 0); - case IPI_MAILBOX_STATUS_ENQUIRY: - { - int disable_irq; - - disable_irq = (x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) ? 1 : 0; - ret = ipi_mb_enquire_status(ipi_local_id, ipi_remote_id); - if ((ret & IPI_MB_STATUS_RECV_PENDING) && disable_irq) - ipi_mb_disable_irq(ipi_local_id, ipi_remote_id); - SMC_RET1(handle, ret); - } - case IPI_MAILBOX_NOTIFY: - { - uint32_t is_blocking; - - is_blocking = (x3 & IPI_SMC_NOTIFY_BLOCK_MASK) ? 1 : 0; - ipi_mb_notify(ipi_local_id, ipi_remote_id, is_blocking); - SMC_RET1(handle, 0); - } - case IPI_MAILBOX_ACK: - { - int enable_irq; - - enable_irq = (x3 & IPI_SMC_ACK_EIRQ_MASK) ? 1 : 0; - ipi_mb_ack(ipi_local_id, ipi_remote_id); - if (enable_irq) - ipi_mb_enable_irq(ipi_local_id, ipi_remote_id); - SMC_RET1(handle, 0); - } - case IPI_MAILBOX_ENABLE_IRQ: - ipi_mb_enable_irq(ipi_local_id, ipi_remote_id); - SMC_RET1(handle, 0); - case IPI_MAILBOX_DISABLE_IRQ: - ipi_mb_disable_irq(ipi_local_id, ipi_remote_id); - SMC_RET1(handle, 0); - default: - WARN("Unimplemented IPI service call: 0x%x\n", smc_fid); - SMC_RET1(handle, SMC_UNK); - } -} diff --git a/plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.h b/plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.h deleted file mode 100644 index 197c78819..000000000 --- a/plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* ZynqMP IPI mailbox doorbell service enums and defines */ - -#ifndef IPI_MAILBOX_SVC_H -#define IPI_MAILBOX_SVC_H - -#include - -/********************************************************************* - * Enum definitions - ********************************************************************/ - -/* IPI SMC function numbers enum definition */ -enum ipi_api_id { - /* IPI mailbox operations functions: */ - IPI_MAILBOX_OPEN = 0x1000, - IPI_MAILBOX_RELEASE, - IPI_MAILBOX_STATUS_ENQUIRY, - IPI_MAILBOX_NOTIFY, - IPI_MAILBOX_ACK, - IPI_MAILBOX_ENABLE_IRQ, - IPI_MAILBOX_DISABLE_IRQ -}; - -/********************************************************************* - * IPI mailbox service APIs declarations - ********************************************************************/ - -/* IPI SMC handler */ -uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, - uint64_t x3, uint64_t x4, void *cookie, void *handle, - uint64_t flags); - -#endif /* IPI_MAILBOX_SVC_H */ diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index 33d648860..de4bf3a0b 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -55,9 +55,9 @@ endif PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ -Iinclude/plat/arm/common/aarch64/ \ -Iplat/xilinx/common/include/ \ + -Iplat/xilinx/common/ipi_mailbox_service/ \ -Iplat/xilinx/zynqmp/include/ \ -Iplat/xilinx/zynqmp/pm_service/ \ - -Iplat/xilinx/zynqmp/ipi_mailbox_service/ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ lib/xlat_tables/aarch64/xlat_tables.c \ @@ -80,6 +80,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ + plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ plat/xilinx/common/pm_service/pm_ipi.c \ plat/xilinx/zynqmp/bl31_zynqmp_setup.c \ plat/xilinx/zynqmp/plat_psci.c \ @@ -92,5 +93,8 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c \ plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c \ plat/xilinx/zynqmp/pm_service/pm_api_clock.c \ - plat/xilinx/zynqmp/pm_service/pm_client.c \ - plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c + plat/xilinx/zynqmp/pm_service/pm_client.c + +ifneq (${RESET_TO_BL31},1) + $(error "Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1.") +endif -- cgit v1.2.3 From 6e2f0d105d137257dbdae4d0ed73d813c6b03119 Mon Sep 17 00:00:00 2001 From: Wendy Liang Date: Mon, 21 Jan 2019 13:45:49 +0530 Subject: xilinx: versal: enable ipi mailbox service Enable IPI mailbox service on versal platform. Signed-off-by: Wendy Liang Signed-off-by: Jolly Shah Change-Id: Idfba3bcd7e7b868133da0bc1d03c96db2d0bb1b7 --- plat/xilinx/versal/platform.mk | 2 ++ plat/xilinx/versal/sip_svc_setup.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk index eb1f0bb61..638f4fb21 100644 --- a/plat/xilinx/versal/platform.mk +++ b/plat/xilinx/versal/platform.mk @@ -38,6 +38,7 @@ VERSAL_CONSOLE ?= pl011 $(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE})) PLAT_INCLUDES := -Iplat/xilinx/common/include/ \ + -Iplat/xilinx/common/ipi_mailbox_service/ \ -Iplat/xilinx/versal/include/ \ -Iplat/xilinx/versal/pm_service/ @@ -58,6 +59,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a72.S \ plat/common/plat_psci_common.c \ plat/xilinx/common/ipi.c \ + plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ plat/xilinx/common/pm_service/pm_ipi.c \ plat/xilinx/versal/bl31_versal_setup.c \ plat/xilinx/versal/plat_psci.c \ diff --git a/plat/xilinx/versal/sip_svc_setup.c b/plat/xilinx/versal/sip_svc_setup.c index 404c496a7..bc7d8b7af 100644 --- a/plat/xilinx/versal/sip_svc_setup.c +++ b/plat/xilinx/versal/sip_svc_setup.c @@ -9,6 +9,8 @@ #include #include #include + +#include "ipi_mailbox_svc.h" #include "pm_svc_main.h" /* SMC function IDs for SiP Service queries */ @@ -23,7 +25,9 @@ /* These macros are used to identify PM calls from the SMC function ID */ #define PM_FID_MASK 0xf000u #define PM_FID_VALUE 0u +#define IPI_FID_VALUE 0x1000u #define is_pm_fid(_fid) (((_fid) & PM_FID_MASK) == PM_FID_VALUE) +#define is_ipi_fid(_fid) (((_fid) & PM_FID_MASK) == IPI_FID_VALUE) /* SiP Service UUID */ DEFINE_SVC_UUID2(versal_sip_uuid, @@ -64,6 +68,12 @@ uintptr_t sip_svc_smc_handler(uint32_t smc_fid, flags); } + /* Let IPI SMC handler deal with IPI-related requests */ + if (is_ipi_fid(smc_fid)) { + return ipi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, + flags); + } + /* Let PM SMC handler deal with PM-related requests */ switch (smc_fid) { case VERSAL_SIP_SVC_CALL_COUNT: -- cgit v1.2.3 From 4b0f32a411377bdbbc3d7913bde818afddde02ee Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Mon, 21 Jan 2019 17:56:48 +0530 Subject: xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API PM_GET_TRUSTZONE_VERSION API is required to use zynqmp-firmware driver for versal. Add support of PM_GET_TRUSTZONE_VERSION API for versal. Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: Ie1c859890096024cc8be67386e3fd0f5f8a4385f --- plat/xilinx/versal/include/plat_pm_common.h | 4 ++++ plat/xilinx/versal/pm_service/pm_svc_main.c | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/plat/xilinx/versal/include/plat_pm_common.h b/plat/xilinx/versal/include/plat_pm_common.h index 6b202c746..2d0080168 100644 --- a/plat/xilinx/versal/include/plat_pm_common.h +++ b/plat/xilinx/versal/include/plat_pm_common.h @@ -19,4 +19,8 @@ #define PAYLOAD_ARG_CNT 6U #define PAYLOAD_ARG_SIZE 4U /* size in bytes */ +#define VERSAL_TZ_VERSION_MAJOR 1 +#define VERSAL_TZ_VERSION_MINOR 0 +#define VERSAL_TZ_VERSION ((VERSAL_TZ_VERSION_MAJOR << 16) | \ + VERSAL_TZ_VERSION_MINOR) #endif /* PLAT_PM_COMMON_H */ diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index 3aac79a86..cb2ac5534 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -17,6 +17,8 @@ #include "pm_client.h" #include "pm_ipi.h" +#define PM_GET_TRUSTZONE_VERSION 0xa03 + /* pm_up = true - UP, pm_up = false - DOWN */ static bool pm_up; @@ -255,6 +257,10 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32)); } + case PM_GET_TRUSTZONE_VERSION: + SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | + ((uint64_t)VERSAL_TZ_VERSION << 32)); + default: WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid); SMC_RET1(handle, SMC_UNK); -- cgit v1.2.3 From ad19911c72db1da8f05d4f846b15fb5386290493 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Mon, 21 Jan 2019 17:56:49 +0530 Subject: xilinx: versal: Add PM_INIT_FINALIZE API for versal PM_INIT_FINALIZE is not required for versal. To use Linux Zynqmp PM driver for versal, handle PM_INIT_FINALIZE API in ATF for versal by always returning SUCCESS. Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: I6fe5445d78e713d70282ac8931ff8b17c96b2a14 --- plat/xilinx/versal/pm_service/pm_defs.h | 1 + plat/xilinx/versal/pm_service/pm_svc_main.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index fa3506607..e8a3f3dbd 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -35,6 +35,7 @@ #define PM_SET_REQUIREMENT 15U #define PM_RESET_ASSERT 17U #define PM_RESET_GET_STATUS 18U +#define PM_INIT_FINALIZE 21U #define PM_PINCTRL_REQUEST 28U #define PM_PINCTRL_RELEASE 29U #define PM_PINCTRL_GET_FUNCTION 30U diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index cb2ac5534..9e7a5885e 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -152,6 +152,9 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, ((uint64_t)reset_status << 32)); } + case PM_INIT_FINALIZE: + SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS); + case PM_PINCTRL_REQUEST: ret = pm_pinctrl_request(pm_arg[0]); SMC_RET1(handle, (uint64_t)ret); -- cgit v1.2.3 From c56be55df319eac18c5d33ea6fe49ead80b18b0a Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Wed, 23 Jan 2019 14:18:51 +0530 Subject: xilinx: versal: Add request wakeup API Implement request wakeup API for versal. Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: I40a2a4ea85bf05623ac8a17ef4a6fa329babd27e --- plat/xilinx/versal/pm_service/pm_api_sys.c | 28 ++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 2 ++ plat/xilinx/versal/pm_service/pm_defs.h | 1 + plat/xilinx/versal/pm_service/pm_svc_main.c | 4 ++++ 4 files changed, 35 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index dd69f0679..3e7e8d15e 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -159,6 +159,34 @@ enum pm_ret_status pm_req_suspend(uint32_t target, uint8_t ack, return pm_ipi_send(primary_proc, payload); } +/** + * pm_req_wakeup() - PM call for processor to wake up selected processor + * or subsystem + * @target Device ID of the processor or subsystem to wake up + * @set_address Resume address presence indicator + * 1 - resume address specified, 0 - otherwise + * @address Resume address + * @ack Flag to specify whether acknowledge requested + * + * This API function is either used to power up another APU core for SMP + * (by PSCI) or to power up an entirely different PU or subsystem, such + * as RPU0, RPU, or PL_CORE_xx. Resume address for the target PU will be + * automatically set by PMC. + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_req_wakeup(uint32_t target, uint32_t set_address, + uintptr_t address, uint8_t ack) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC to perform the wake of the PU */ + PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_REQ_WAKEUP, target, + set_address, address, ack); + + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} + /** * pm_request_device() - Request a device * @device_id Device ID diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 04074b18e..91d3368f9 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -24,6 +24,8 @@ enum pm_ret_status pm_req_suspend(uint32_t target, uint8_t ack, unsigned int latency, unsigned int state); +enum pm_ret_status pm_req_wakeup(uint32_t target, uint32_t set_address, + uintptr_t address, uint8_t ack); enum pm_ret_status pm_request_device(uint32_t device_id, uint32_t capabilities, uint32_t qos, uint32_t ack); enum pm_ret_status pm_release_device(uint32_t device_id); diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index e8a3f3dbd..cfb1ca6cf 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -29,6 +29,7 @@ #define PM_SELF_SUSPEND 7U #define PM_FORCE_POWERDOWN 8U #define PM_ABORT_SUSPEND 9U +#define PM_REQ_WAKEUP 10U #define PM_SYSTEM_SHUTDOWN 12U #define PM_REQUEST_DEVICE 13U #define PM_RELEASE_DEVICE 14U diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index 9e7a5885e..bd3ebf3bd 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -107,6 +107,10 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, ret = pm_system_shutdown(pm_arg[0], pm_arg[1]); SMC_RET1(handle, (uint64_t)ret); + case PM_REQ_WAKEUP: + ret = pm_req_wakeup(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + case PM_REQUEST_DEVICE: ret = pm_request_device(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); -- cgit v1.2.3 From 1f71e4fbfe6aaf349e764bc51ecdb3463536a82a Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Fri, 1 Feb 2019 17:25:19 +0530 Subject: xilinx: versal: Add query data API Add PM_QUERY_DATA API to pass query data EEMI call from Linux to PLM . Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: I18735b72ab9cb62fb6cbc7582e77de6cb57f99b0 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 20 ++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 3 ++- plat/xilinx/versal/pm_service/pm_defs.h | 1 + plat/xilinx/versal/pm_service/pm_svc_main.c | 10 ++++++++++ 4 files changed, 33 insertions(+), 1 deletion(-) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 3e7e8d15e..125134db8 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -641,6 +641,26 @@ enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype) return pm_ipi_send_non_blocking(primary_proc, payload); } +/** +* pm_query_data() - PM API for querying firmware data +* @qid The type of data to query +* @arg1 Argument 1 to requested query data call +* @arg2 Argument 2 to requested query data call +* @arg3 Argument 3 to requested query data call +* @data Returned output data +* +* This function returns requested data. +*/ +enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2, + uint32_t arg3, uint32_t *data) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_QUERY_DATA, qid, arg1, + arg2, arg3); + return pm_ipi_send_sync(primary_proc, payload, data, 4); +} /** * pm_api_ioctl() - PM IOCTL API for device control and configs * @device_id Device ID diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 91d3368f9..ff3588236 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -59,5 +59,6 @@ enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack); enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype); enum pm_ret_status pm_api_ioctl(uint32_t device_id, uint32_t ioctl_id, uint32_t arg1, uint32_t arg2, uint32_t *value); - +enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2, + uint32_t arg3, uint32_t *data); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index cfb1ca6cf..bd7430433 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -44,6 +44,7 @@ #define PM_PINCTRL_CONFIG_PARAM_GET 32U #define PM_PINCTRL_CONFIG_PARAM_SET 33U #define PM_IOCTL 34U +#define PM_QUERY_DATA 35U #define PM_CLOCK_ENABLE 36U #define PM_CLOCK_DISABLE 37U #define PM_CLOCK_GETSTATE 38U diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index bd3ebf3bd..7f8e42fba 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -200,6 +200,16 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); } + case PM_QUERY_DATA: + { + uint32_t data[4] = { 0 }; + + ret = pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2], + pm_arg[3], data); + SMC_RET2(handle, (uint64_t)ret | ((uint64_t)data[0] << 32), + (uint64_t)data[1] | ((uint64_t)data[2] << 32)); + } + case PM_CLOCK_ENABLE: ret = pm_clock_enable(pm_arg[0]); SMC_RET1(handle, (uint64_t)ret); -- cgit v1.2.3 From 25b1a91033ae3e4220c933333764c01c7a687c2d Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Wed, 27 Feb 2019 18:44:54 +0530 Subject: xilinx: versal: Add client wakeup API Implement client wakeup API for versal. Signed-off-by: Tejas Patel Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: I31b1b362fe645a82f89ce2d698ee71eb00cf15dc --- plat/xilinx/versal/pm_service/pm_client.c | 40 +++++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_client.h | 1 + 2 files changed, 41 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c index 636b719fd..b234e1bfa 100644 --- a/plat/xilinx/versal/pm_service/pm_client.c +++ b/plat/xilinx/versal/pm_service/pm_client.c @@ -18,6 +18,8 @@ #include #include "pm_client.h" +#define UNDEFINED_CPUID (~0) + DEFINE_BAKERY_LOCK(pm_client_secure_lock); static const struct pm_ipi apu_ipi = { @@ -80,6 +82,44 @@ void pm_client_abort_suspend(void) bakery_lock_release(&pm_client_secure_lock); } +/** + * pm_get_cpuid() - get the local cpu ID for a global node ID + * @nid: node id of the processor + * + * Return: the cpu ID (starting from 0) for the subsystem + */ +static unsigned int pm_get_cpuid(uint32_t nid) +{ + for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) { + if (pm_procs_all[i].node_id == nid) + return i; + } + return UNDEFINED_CPUID; +} + +/** + * pm_client_wakeup() - Client-specific wakeup actions + * + * This function should contain any PU-specific actions + * required for waking up another APU core + */ +void pm_client_wakeup(const struct pm_proc *proc) +{ + unsigned int cpuid = pm_get_cpuid(proc->node_id); + + if (cpuid == UNDEFINED_CPUID) + return; + + bakery_lock_get(&pm_client_secure_lock); + + /* clear powerdown bit for affected cpu */ + uint32_t val = mmio_read_32(FPD_APU_PWRCTL); + val &= ~(proc->pwrdn_mask); + mmio_write_32(FPD_APU_PWRCTL, val); + + bakery_lock_release(&pm_client_secure_lock); +} + /** * pm_get_proc() - returns pointer to the proc structure * @cpuid: id of the cpu whose proc struct pointer should be returned diff --git a/plat/xilinx/versal/pm_service/pm_client.h b/plat/xilinx/versal/pm_service/pm_client.h index 228094e67..91f135c06 100644 --- a/plat/xilinx/versal/pm_service/pm_client.h +++ b/plat/xilinx/versal/pm_service/pm_client.h @@ -17,6 +17,7 @@ /* Functions to be implemented by each PU */ void pm_client_suspend(const struct pm_proc *proc, unsigned int state); +void pm_client_wakeup(const struct pm_proc *proc); void pm_client_abort_suspend(void); /* Global variables to be set in pm_client.c */ -- cgit v1.2.3 From 42cd77e386d4d0b847bcbbbe26fff315ed754087 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Wed, 23 Jan 2019 14:18:53 +0530 Subject: xilinx: versal: Add set wakeup source API Implement set wakeup source API to pass SMC call for set wakeup source to PLM (Platform Loader and Manager). Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: I654ce07235c0fc7dfcb81bf98820153255f61537 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 18 ++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 2 ++ plat/xilinx/versal/pm_service/pm_defs.h | 1 + plat/xilinx/versal/pm_service/pm_svc_main.c | 4 ++++ 4 files changed, 25 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 125134db8..5f3e30fff 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -694,3 +694,21 @@ enum pm_ret_status pm_api_ioctl(uint32_t device_id, uint32_t ioctl_id, return pm_ipi_send_sync(primary_proc, payload, value, 1); } } + +/** + * pm_set_wakeup_source() - PM call to specify the wakeup source while suspended + * @target Device id of the targeted PU or subsystem + * @wkup_node Device id of the wakeup peripheral + * @enable Enable or disable the specified peripheral as wake source + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t wkup_device, + uint8_t enable) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, PM_SET_WAKEUP_SOURCE, target, + wkup_device, enable); + return pm_ipi_send(primary_proc, payload); +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index ff3588236..16722e72b 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -26,6 +26,8 @@ enum pm_ret_status pm_req_suspend(uint32_t target, unsigned int state); enum pm_ret_status pm_req_wakeup(uint32_t target, uint32_t set_address, uintptr_t address, uint8_t ack); +enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t device_id, + uint8_t enable); enum pm_ret_status pm_request_device(uint32_t device_id, uint32_t capabilities, uint32_t qos, uint32_t ack); enum pm_ret_status pm_release_device(uint32_t device_id); diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index bd7430433..7d69699ba 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -30,6 +30,7 @@ #define PM_FORCE_POWERDOWN 8U #define PM_ABORT_SUSPEND 9U #define PM_REQ_WAKEUP 10U +#define PM_SET_WAKEUP_SOURCE 11U #define PM_SYSTEM_SHUTDOWN 12U #define PM_REQUEST_DEVICE 13U #define PM_RELEASE_DEVICE 14U diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index 7f8e42fba..94d1438cf 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -111,6 +111,10 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, ret = pm_req_wakeup(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); SMC_RET1(handle, (uint64_t)ret); + case PM_SET_WAKEUP_SOURCE: + ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2]); + SMC_RET1(handle, (uint64_t)ret); + case PM_REQUEST_DEVICE: ret = pm_request_device(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); -- cgit v1.2.3 From 394a65aa96d6ce8cd55c0a824dc112d60ef97835 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Wed, 27 Feb 2019 18:44:57 +0530 Subject: xilinx: versal: Remove no_pmc ops to ON power domain Add PMC ops for power domain ON and remove no_pmc ops. Signed-off-by: Tejas Patel Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: Id4308dfe124b60a751765beb3397d1b0071f14fc --- plat/xilinx/versal/plat_psci.c | 51 +++++++++++++----------------------------- 1 file changed, 15 insertions(+), 36 deletions(-) diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c index de581bd0b..5e3b6f7fc 100644 --- a/plat/xilinx/versal/plat_psci.c +++ b/plat/xilinx/versal/plat_psci.c @@ -5,56 +5,35 @@ */ #include +#include #include #include #include #include +#include "pm_api_sys.h" +#include "pm_client.h" + static uintptr_t versal_sec_entry; -static int versal_nopmc_pwr_domain_on(u_register_t mpidr) +static int versal_pwr_domain_on(u_register_t mpidr) { - uint32_t r; unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); + const struct pm_proc *proc; VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); if (cpu_id == -1) return PSCI_E_INTERN_FAIL; - /* - * program RVBAR - */ - mmio_write_32(FPD_APU_RVBAR_L_0 + (cpu_id << 3), versal_sec_entry); - mmio_write_32(FPD_APU_RVBAR_H_0 + (cpu_id << 3), versal_sec_entry >> 32); - - /* - * clear VINITHI - */ - r = mmio_read_32(FPD_APU_CONFIG_0); - r &= ~(1 << FPD_APU_CONFIG_0_VINITHI_SHIFT << cpu_id); - mmio_write_32(FPD_APU_CONFIG_0, r); - - /* - * FIXME: Add power up sequence, By default it works - * now without the need of it as it was powered up by - * default. - */ - - /* - * clear power down request - */ - r = mmio_read_32(FPD_APU_PWRCTL); - r &= ~(1 << cpu_id); - mmio_write_32(FPD_APU_PWRCTL, r); - - /* - * release core reset - */ - r = mmio_read_32(CRF_RST_APU); - r &= ~((CRF_RST_APU_ACPU_PWRON_RESET | - CRF_RST_APU_ACPU_RESET) << cpu_id); - mmio_write_32(CRF_RST_APU, r); + proc = pm_get_proc(cpu_id); + + /* Send request to PMC to wake up selected ACPU core */ + pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFF) | 0x1, + versal_sec_entry >> 32, 0); + + /* Clear power down request */ + pm_client_wakeup(proc); return PSCI_E_SUCCESS; } @@ -69,7 +48,7 @@ void versal_pwr_domain_on_finish(const psci_power_state_t *target_state) } static const struct plat_psci_ops versal_nopmc_psci_ops = { - .pwr_domain_on = versal_nopmc_pwr_domain_on, + .pwr_domain_on = versal_pwr_domain_on, .pwr_domain_on_finish = versal_pwr_domain_on_finish, }; -- cgit v1.2.3 From 5a8ffeabf97eb7fb1e1276cb967584af0ff7adbb Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Wed, 27 Feb 2019 18:44:55 +0530 Subject: xilinx: versal: Add PSCI APIs for suspend/resume Add following APIs in plat_psci to support suspend resume: - versal_pwr_domain_off - versal_pwr_domain_suspend - versal_pwr_domain_suspend_finish - versal_validate_power_state - versal_get_sys_suspend_power_state Signed-off-by: Tejas Patel Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: Ife908a45f32e2037c9c19e13211a8e4b373b8342 --- plat/xilinx/versal/aarch64/versal_common.c | 2 + plat/xilinx/versal/bl31_versal_setup.c | 4 + plat/xilinx/versal/include/plat_private.h | 2 + plat/xilinx/versal/include/platform_def.h | 2 +- plat/xilinx/versal/include/versal_def.h | 10 ++ plat/xilinx/versal/plat_psci.c | 142 +++++++++++++++++++++++++++++ plat/xilinx/versal/platform.mk | 9 +- plat/xilinx/versal/pm_service/pm_defs.h | 7 ++ 8 files changed, 175 insertions(+), 3 deletions(-) diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c index 2c6ff0537..29528da8a 100644 --- a/plat/xilinx/versal/aarch64/versal_common.c +++ b/plat/xilinx/versal/aarch64/versal_common.c @@ -22,6 +22,8 @@ const mmap_region_t plat_versal_mmap[] = { MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(FPD_MAINCCI_BASE, FPD_MAINCCI_SIZE, MT_DEVICE | MT_RW | + MT_SECURE), { 0 } }; diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c index 0deff9006..6b56307af 100644 --- a/plat/xilinx/versal/bl31_versal_setup.c +++ b/plat/xilinx/versal/bl31_versal_setup.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -102,6 +103,9 @@ void bl31_plat_runtime_setup(void) */ void bl31_plat_arch_setup(void) { + plat_arm_interconnect_init(); + plat_arm_interconnect_enter_coherency(); + const mmap_region_t bl_regions[] = { MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE), diff --git a/plat/xilinx/versal/include/plat_private.h b/plat/xilinx/versal/include/plat_private.h index cb35be87e..e302096eb 100644 --- a/plat/xilinx/versal/include/plat_private.h +++ b/plat/xilinx/versal/include/plat_private.h @@ -18,6 +18,8 @@ void plat_versal_gic_init(void); void plat_versal_gic_cpuif_enable(void); void plat_versal_gic_cpuif_disable(void); void plat_versal_gic_pcpu_init(void); +void plat_versal_gic_save(void); +void plat_versal_gic_resume(void); unsigned int versal_calc_core_pos(u_register_t mpidr); diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h index e61929cc1..c6be09e75 100644 --- a/plat/xilinx/versal/include/platform_def.h +++ b/plat/xilinx/versal/include/platform_def.h @@ -75,7 +75,7 @@ ******************************************************************************/ #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) -#define MAX_MMAP_REGIONS 7 +#define MAX_MMAP_REGIONS 8 #define MAX_XLAT_TABLES 5 #define CACHE_WRITEBACK_SHIFT 6 diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h index a77fa30d0..c2f78882d 100644 --- a/plat/xilinx/versal/include/versal_def.h +++ b/plat/xilinx/versal/include/versal_def.h @@ -55,6 +55,13 @@ ******************************************************************************/ #define VERSAL_IRQ_SEC_PHY_TIMER 29 +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define PLAT_ARM_CCI_BASE 0xFD000000 +#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 +#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 + /******************************************************************************* * UART related constants ******************************************************************************/ @@ -97,6 +104,9 @@ #define CRF_RST_APU_ACPU_RESET (1 << 0) #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) +#define FPD_MAINCCI_BASE 0xFD000000 +#define FPD_MAINCCI_SIZE 0x00100000 + /* APU registers and bitfields */ #define FPD_APU_BASE 0xFD5C0000 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20) diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c index 5e3b6f7fc..942ef01cc 100644 --- a/plat/xilinx/versal/plat_psci.c +++ b/plat/xilinx/versal/plat_psci.c @@ -4,6 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include +#include #include #include #include @@ -38,6 +40,71 @@ static int versal_pwr_domain_on(u_register_t mpidr) return PSCI_E_SUCCESS; } +/** + * versal_pwr_domain_suspend() - This function sends request to PMC to suspend + * core. + * + * @target_state Targated state + */ +static void versal_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + unsigned int state; + unsigned int cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + plat_versal_gic_cpuif_disable(); + + plat_versal_gic_save(); + + state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? + PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; + + /* Send request to PMC to suspend this core */ + pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry); + + /* APU is to be turned off */ + if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { + /* disable coherency */ + plat_arm_interconnect_exit_coherency(); + } +} + +/** + * versal_pwr_domain_suspend_finish() - This function performs actions to finish + * suspend procedure. + * + * @target_state Targated state + */ +static void versal_pwr_domain_suspend_finish( + const psci_power_state_t *target_state) +{ + unsigned int cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* Clear the APU power control register for this cpu */ + pm_client_wakeup(proc); + + /* enable coherency */ + plat_arm_interconnect_enter_coherency(); + + /* APU was turned off, so restore GIC context */ + if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { + plat_versal_gic_resume(); + plat_versal_gic_cpuif_enable(); + } else { + plat_versal_gic_cpuif_enable(); + plat_versal_gic_pcpu_init(); + } +} + void versal_pwr_domain_on_finish(const psci_power_state_t *target_state) { /* Enable the gic cpu interface */ @@ -47,9 +114,84 @@ void versal_pwr_domain_on_finish(const psci_power_state_t *target_state) plat_versal_gic_cpuif_enable(); } +/** + * versal_pwr_domain_off() - This function performs actions to turn off core + * + * @target_state Targated state + */ +static void versal_pwr_domain_off(const psci_power_state_t *target_state) +{ + unsigned int cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* Prevent interrupts from spuriously waking up this cpu */ + plat_versal_gic_cpuif_disable(); + + /* + * Send request to PMC to power down the appropriate APU CPU + * core. + * According to PSCI specification, CPU_off function does not + * have resume address and CPU core can only be woken up + * invoking CPU_on function, during which resume address will + * be set. + */ + pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0); +} + +/** + * versal_validate_power_state() - This function ensures that the power state + * parameter in request is valid. + * + * @power_state Power state of core + * @req_state Requested state + * + * @return Returns status, either success or reason + */ +static int versal_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); + + int pstate = psci_get_pstate_type(power_state); + + assert(req_state); + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) + req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; + else + req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; + + /* We expect the 'state id' to be zero */ + if (psci_get_pstate_id(power_state)) + return PSCI_E_INVALID_PARAMS; + + return PSCI_E_SUCCESS; +} + +/** + * versal_get_sys_suspend_power_state() - Get power state for system suspend + * + * @req_state Requested state + */ +static void versal_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; + req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; +} + static const struct plat_psci_ops versal_nopmc_psci_ops = { .pwr_domain_on = versal_pwr_domain_on, + .pwr_domain_off = versal_pwr_domain_off, .pwr_domain_on_finish = versal_pwr_domain_on_finish, + .pwr_domain_suspend = versal_pwr_domain_suspend, + .pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish, + .validate_power_state = versal_validate_power_state, + .get_sys_suspend_power_state = versal_get_sys_suspend_power_state, }; /******************************************************************************* diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk index 638f4fb21..52d2c977b 100644 --- a/plat/xilinx/versal/platform.mk +++ b/plat/xilinx/versal/platform.mk @@ -37,7 +37,8 @@ $(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFOR VERSAL_CONSOLE ?= pl011 $(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE})) -PLAT_INCLUDES := -Iplat/xilinx/common/include/ \ +PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ + -Iplat/xilinx/common/include/ \ -Iplat/xilinx/common/ipi_mailbox_service/ \ -Iplat/xilinx/versal/include/ \ -Iplat/xilinx/versal/pm_service/ @@ -47,15 +48,19 @@ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v3/arm_gicv3_common.c \ + drivers/arm/gic/v3/gic500.c \ drivers/arm/gic/v3/gicv3_main.c \ drivers/arm/gic/v3/gicv3_helpers.c \ drivers/arm/pl011/aarch64/pl011_console.S \ plat/common/aarch64/crash_console_helpers.S \ + plat/arm/common/arm_cci.c \ plat/common/plat_gicv3.c \ plat/xilinx/versal/aarch64/versal_helpers.S \ plat/xilinx/versal/aarch64/versal_common.c -BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ +BL31_SOURCES += drivers/arm/cci/cci.c \ + lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a72.S \ plat/common/plat_psci_common.c \ plat/xilinx/common/ipi.c \ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index 7d69699ba..f090db538 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -15,6 +15,13 @@ * Macro definitions ********************************************************************/ +/* State arguments of the self suspend */ +#define PM_STATE_CPU_IDLE 0x0U +#define PM_STATE_SUSPEND_TO_RAM 0xFU + +#define MAX_LATENCY (~0U) +#define MAX_QOS 100U + /* Processor core device IDs */ #define APU_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \ XPM_NODETYPE_DEV_CORE_APU, (IDX)) -- cgit v1.2.3 From 0abf4bba500e59dfe4b68468bb855e3897869e55 Mon Sep 17 00:00:00 2001 From: Saeed Nowshadi Date: Sun, 8 Dec 2019 23:35:35 -0800 Subject: xilinx: versal: Add PSCI APIs for system shutdown & reset Add following APIs in plat_psci to support system shutdown & reset: - versal_system_off - versal_system_reset Signed-off-by: Saeed Nowshadi Signed-off-by: Jolly Shah Change-Id: Ia2c1a19ded18984b393e1fdee760bf48b45e9902 --- plat/xilinx/versal/plat_psci.c | 31 ++++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.c | 21 +++++++++++++++++++- plat/xilinx/versal/pm_service/pm_api_sys.h | 2 ++ plat/xilinx/versal/pm_service/pm_defs.h | 9 +++++++++ 4 files changed, 62 insertions(+), 1 deletion(-) diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c index 942ef01cc..39550858a 100644 --- a/plat/xilinx/versal/plat_psci.c +++ b/plat/xilinx/versal/plat_psci.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "pm_api_sys.h" #include "pm_client.h" @@ -114,6 +115,34 @@ void versal_pwr_domain_on_finish(const psci_power_state_t *target_state) plat_versal_gic_cpuif_enable(); } +/** + * versal_system_off() - This function sends the system off request + * to firmware. This function does not return. + */ +static void __dead2 versal_system_off(void) +{ + /* Send the power down request to the PMC */ + pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN, + pm_get_shutdown_scope()); + + while (1) + wfi(); +} + +/** + * versal_system_reset() - This function sends the reset request + * to firmware for the system to reset. This function does not return. + */ +static void __dead2 versal_system_reset(void) +{ + /* Send the system reset request to the PMC */ + pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET, + pm_get_shutdown_scope()); + + while (1) + wfi(); +} + /** * versal_pwr_domain_off() - This function performs actions to turn off core * @@ -190,6 +219,8 @@ static const struct plat_psci_ops versal_nopmc_psci_ops = { .pwr_domain_on_finish = versal_pwr_domain_on_finish, .pwr_domain_suspend = versal_pwr_domain_suspend, .pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish, + .system_off = versal_system_off, + .system_reset = versal_system_reset, .validate_power_state = versal_validate_power_state, .get_sys_suspend_power_state = versal_get_sys_suspend_power_state, }; diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 5f3e30fff..99897ba9d 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -21,6 +21,19 @@ #define LIBPM_MODULE_ID 0x2 #define LOADER_MODULE_ID 0x7 +/* default shutdown/reboot scope is system(2) */ +static unsigned int pm_shutdown_scope = XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM; + +/** + * pm_get_shutdown_scope() - Get the currently set shutdown scope + * + * @return Shutdown scope value + */ +unsigned int pm_get_shutdown_scope(void) +{ + return pm_shutdown_scope; +} + /** * Assigning of argument values into array elements. */ @@ -625,7 +638,7 @@ enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack) /** * pm_system_shutdown() - PM call to request a system shutdown or restart - * @type Shutdown or restart? 0=shutdown, 1=restart + * @type Shutdown or restart? 0=shutdown, 1=restart, 2=setscope * @subtype Scope: 0=APU-subsystem, 1=PS, 2=system * * @return Returns status, either success or error+reason @@ -634,6 +647,12 @@ enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype) { uint32_t payload[PAYLOAD_ARG_CNT]; + if (type == XPM_SHUTDOWN_TYPE_SETSCOPE_ONLY) { + /* Setting scope for subsequent PSCI reboot or shutdown */ + pm_shutdown_scope = subtype; + return PM_RET_SUCCESS; + } + /* Send request to the PMC */ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_SYSTEM_SHUTDOWN, type, subtype); diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 16722e72b..b1ad3f276 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -63,4 +63,6 @@ enum pm_ret_status pm_api_ioctl(uint32_t device_id, uint32_t ioctl_id, uint32_t arg1, uint32_t arg2, uint32_t *value); enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t *data); +unsigned int pm_get_shutdown_scope(void); + #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index f090db538..626fa3916 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -77,6 +77,15 @@ /* Fractional data portion for PLL */ #define PM_PLL_PARAM_DATA 2 +/* System shutdown macros */ +#define XPM_SHUTDOWN_TYPE_SHUTDOWN 0U +#define XPM_SHUTDOWN_TYPE_RESET 1U +#define XPM_SHUTDOWN_TYPE_SETSCOPE_ONLY 2U + +#define XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM 0U +#define XPM_SHUTDOWN_SUBTYPE_RST_PS_ONLY 1U +#define XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM 2U + /********************************************************************* * Enum definitions ********************************************************************/ -- cgit v1.2.3 From 89224531b43f4a2396a0b5a9ab34349bd7c58b06 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Mon, 4 Mar 2019 11:09:40 +0530 Subject: plat: xilinx: versal: Add GET_CALLBACK_DATA function Add GET_CALLBACK_DATA function to get IPI callback data in Linux during init suspend callback. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: Ieb60e561b5f656611f0702c43ba6a4296a012651 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 16 ++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 1 + plat/xilinx/versal/pm_service/pm_svc_main.c | 11 +++++++++++ 3 files changed, 28 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 99897ba9d..216bc9801 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -312,6 +312,22 @@ enum pm_ret_status pm_reset_get_status(uint32_t reset, uint32_t *status) return pm_ipi_send_sync(primary_proc, payload, status, 1); } +/** + * pm_get_callbackdata() - Read from IPI response buffer + * @data - array of PAYLOAD_ARG_CNT elements + * + * Read value from ipi buffer response buffer. + */ +void pm_get_callbackdata(uint32_t *data, size_t count) +{ + /* Return if interrupt is not from PMU */ + if (!pm_ipi_irq_status(primary_proc)) + return; + + pm_ipi_buff_read_callb(data, count); + pm_ipi_irq_clear(primary_proc); +} + /** * pm_pinctrl_request() - Request a pin * @pin Pin ID diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index b1ad3f276..282c175a8 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -36,6 +36,7 @@ enum pm_ret_status pm_set_requirement(uint32_t device_id, uint32_t capabilities, enum pm_ret_status pm_get_device_status(uint32_t device_id, uint32_t *response); enum pm_ret_status pm_reset_assert(uint32_t reset, bool assert); enum pm_ret_status pm_reset_get_status(uint32_t reset, uint32_t *status); +void pm_get_callbackdata(uint32_t *data, size_t count); enum pm_ret_status pm_pinctrl_request(uint32_t pin); enum pm_ret_status pm_pinctrl_release(uint32_t pin); enum pm_ret_status pm_pinctrl_set_function(uint32_t pin, uint32_t function); diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index 94d1438cf..8140b6644 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -17,6 +17,7 @@ #include "pm_client.h" #include "pm_ipi.h" +#define PM_GET_CALLBACK_DATA 0xa01 #define PM_GET_TRUSTZONE_VERSION 0xa03 /* pm_up = true - UP, pm_up = false - DOWN */ @@ -163,6 +164,16 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, case PM_INIT_FINALIZE: SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS); + case PM_GET_CALLBACK_DATA: + { + uint32_t result[4] = {0}; + + pm_get_callbackdata(result, sizeof(result)); + SMC_RET2(handle, + (uint64_t)result[0] | ((uint64_t)result[1] << 32), + (uint64_t)result[2] | ((uint64_t)result[3] << 32)); + } + case PM_PINCTRL_REQUEST: ret = pm_pinctrl_request(pm_arg[0]); SMC_RET1(handle, (uint64_t)ret); -- cgit v1.2.3 From 6e82cd8c9b37ad6226523e88829ecba776b15bc8 Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Wed, 27 Feb 2019 18:44:56 +0530 Subject: xilinx: versal: Implement set wakeup source for client Add support to set wakeup source for APU while suspending. Signed-off-by: Tejas Patel Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: I4809fd83a710def8144fdad74990c45e62b8fdf3 --- plat/xilinx/versal/pm_service/pm_client.c | 114 ++++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_defs.h | 4 ++ 2 files changed, 118 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c index b234e1bfa..5b47838e9 100644 --- a/plat/xilinx/versal/pm_service/pm_client.c +++ b/plat/xilinx/versal/pm_service/pm_client.c @@ -9,16 +9,22 @@ * for getting information about and changing state of the APU. */ +#include #include #include #include #include #include +#include #include +#include #include +#include "pm_api_sys.h" #include "pm_client.h" #define UNDEFINED_CPUID (~0) +#define IRQ_MAX 142 +#define NUM_GICD_ISENABLER ((IRQ_MAX >> 5) + 1) DEFINE_BAKERY_LOCK(pm_client_secure_lock); @@ -44,6 +50,111 @@ static const struct pm_proc pm_procs_all[] = { const struct pm_proc *primary_proc = &pm_procs_all[0]; +/* Interrupt to PM node index map */ +static enum pm_device_node_idx irq_node_map[IRQ_MAX + 1] = { + [13] = XPM_NODEIDX_DEV_GPIO, + [14] = XPM_NODEIDX_DEV_I2C_0, + [15] = XPM_NODEIDX_DEV_I2C_1, + [16] = XPM_NODEIDX_DEV_SPI_0, + [17] = XPM_NODEIDX_DEV_SPI_1, + [18] = XPM_NODEIDX_DEV_UART_0, + [19] = XPM_NODEIDX_DEV_UART_1, + [20] = XPM_NODEIDX_DEV_CAN_FD_0, + [21] = XPM_NODEIDX_DEV_CAN_FD_1, + [22] = XPM_NODEIDX_DEV_USB_0, + [23] = XPM_NODEIDX_DEV_USB_0, + [24] = XPM_NODEIDX_DEV_USB_0, + [25] = XPM_NODEIDX_DEV_USB_0, + [26] = XPM_NODEIDX_DEV_USB_0, + [37] = XPM_NODEIDX_DEV_TTC_0, + [38] = XPM_NODEIDX_DEV_TTC_0, + [39] = XPM_NODEIDX_DEV_TTC_0, + [40] = XPM_NODEIDX_DEV_TTC_1, + [41] = XPM_NODEIDX_DEV_TTC_1, + [42] = XPM_NODEIDX_DEV_TTC_1, + [43] = XPM_NODEIDX_DEV_TTC_2, + [44] = XPM_NODEIDX_DEV_TTC_2, + [45] = XPM_NODEIDX_DEV_TTC_2, + [46] = XPM_NODEIDX_DEV_TTC_3, + [47] = XPM_NODEIDX_DEV_TTC_3, + [48] = XPM_NODEIDX_DEV_TTC_3, + [56] = XPM_NODEIDX_DEV_GEM_0, + [57] = XPM_NODEIDX_DEV_GEM_0, + [58] = XPM_NODEIDX_DEV_GEM_1, + [59] = XPM_NODEIDX_DEV_GEM_1, + [60] = XPM_NODEIDX_DEV_ADMA_0, + [61] = XPM_NODEIDX_DEV_ADMA_1, + [62] = XPM_NODEIDX_DEV_ADMA_2, + [63] = XPM_NODEIDX_DEV_ADMA_3, + [64] = XPM_NODEIDX_DEV_ADMA_4, + [65] = XPM_NODEIDX_DEV_ADMA_5, + [66] = XPM_NODEIDX_DEV_ADMA_6, + [67] = XPM_NODEIDX_DEV_ADMA_7, + [74] = XPM_NODEIDX_DEV_USB_0, + [126] = XPM_NODEIDX_DEV_SDIO_0, + [127] = XPM_NODEIDX_DEV_SDIO_0, + [128] = XPM_NODEIDX_DEV_SDIO_1, + [129] = XPM_NODEIDX_DEV_SDIO_1, + [142] = XPM_NODEIDX_DEV_RTC, +}; + +/** + * irq_to_pm_node_idx - Get PM node index corresponding to the interrupt number + * @irq: Interrupt number + * + * Return: PM node index corresponding to the specified interrupt + */ +static enum pm_device_node_idx irq_to_pm_node_idx(unsigned int irq) +{ + assert(irq <= IRQ_MAX); + return irq_node_map[irq]; +} + +/** + * pm_client_set_wakeup_sources - Set all devices with enabled interrupts as + * wake sources in the LibPM. + */ +static void pm_client_set_wakeup_sources(void) +{ + uint32_t reg_num; + uint32_t device_id; + uint8_t pm_wakeup_nodes_set[XPM_NODEIDX_DEV_MAX]; + uintptr_t isenabler1 = PLAT_VERSAL_GICD_BASE + GICD_ISENABLER + 4; + + zeromem(&pm_wakeup_nodes_set, sizeof(pm_wakeup_nodes_set)); + + for (reg_num = 0; reg_num < NUM_GICD_ISENABLER; reg_num++) { + uint32_t base_irq = reg_num << ISENABLER_SHIFT; + uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2)); + + if (!reg) + continue; + + while (reg) { + enum pm_device_node_idx node_idx; + uint32_t idx, ret, irq, lowest_set = reg & (-reg); + + idx = __builtin_ctz(lowest_set); + irq = base_irq + idx; + + if (irq > IRQ_MAX) + break; + + node_idx = irq_to_pm_node_idx(irq); + reg &= ~lowest_set; + + if ((node_idx != XPM_NODEIDX_DEV_MIN) && + (!pm_wakeup_nodes_set[node_idx])) { + /* Get device ID from node index */ + device_id = PERIPH_DEVID(node_idx); + ret = pm_set_wakeup_source(XPM_DEVID_ACPU_0, + device_id, 1); + pm_wakeup_nodes_set[node_idx] = !ret; + } + } + } +} + /** * pm_client_suspend() - Client-specific suspend actions * @@ -55,6 +166,9 @@ void pm_client_suspend(const struct pm_proc *proc, unsigned int state) { bakery_lock_get(&pm_client_secure_lock); + if (state == PM_STATE_SUSPEND_TO_RAM) + pm_client_set_wakeup_sources(); + /* Set powerdown request */ mmio_write_32(FPD_APU_PWRCTL, mmio_read_32(FPD_APU_PWRCTL) | proc->pwrdn_mask); diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index 626fa3916..281494a76 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -29,6 +29,10 @@ #define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0) #define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1) +#define PERIPH_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, \ + XPM_NODESUBCL_DEV_PERIPH, \ + XPM_NODETYPE_DEV_PERIPH, (IDX)) + /* PM API ids */ #define PM_GET_API_VERSION 1U #define PM_GET_DEVICE_STATUS 3U -- cgit v1.2.3 From 39db98efc96afc853b55e98d1b0587c58066e5c0 Mon Sep 17 00:00:00 2001 From: Ravi Patel Date: Wed, 6 Mar 2019 12:34:46 +0530 Subject: xilinx: versal: Add feature check API Add API to check availability of given API in ATF as well as platform management controller and returns the supported version number. Signed-off-by: Ravi Patel Signed-off-by: Jolly Shah Change-Id: I608b38f60b36c4d105b7a205ecb8b02de0c00f3c --- plat/xilinx/versal/pm_service/pm_api_sys.c | 70 +++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 2 +- plat/xilinx/versal/pm_service/pm_defs.h | 9 ++++ plat/xilinx/versal/pm_service/pm_svc_main.c | 11 +++-- 4 files changed, 88 insertions(+), 4 deletions(-) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 216bc9801..54fd6e118 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -747,3 +747,73 @@ enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t wkup_device, wkup_device, enable); return pm_ipi_send(primary_proc, payload); } + +/** + * pm_feature_check() - Returns the supported API version if supported + * @api_id API ID to check + * @value Returned supported API version + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version) +{ + uint32_t payload[PAYLOAD_ARG_CNT], fw_api_version; + uint32_t status; + + switch (api_id) { + case PM_GET_CALLBACK_DATA: + case PM_GET_TRUSTZONE_VERSION: + case PM_INIT_FINALIZE: + *version = (PM_API_BASE_VERSION << 16); + return PM_RET_SUCCESS; + case PM_GET_API_VERSION: + case PM_GET_DEVICE_STATUS: + case PM_REQ_SUSPEND: + case PM_SELF_SUSPEND: + case PM_FORCE_POWERDOWN: + case PM_ABORT_SUSPEND: + case PM_REQ_WAKEUP: + case PM_SET_WAKEUP_SOURCE: + case PM_SYSTEM_SHUTDOWN: + case PM_REQUEST_DEVICE: + case PM_RELEASE_DEVICE: + case PM_SET_REQUIREMENT: + case PM_RESET_ASSERT: + case PM_RESET_GET_STATUS: + case PM_PINCTRL_REQUEST: + case PM_PINCTRL_RELEASE: + case PM_PINCTRL_GET_FUNCTION: + case PM_PINCTRL_SET_FUNCTION: + case PM_PINCTRL_CONFIG_PARAM_GET: + case PM_PINCTRL_CONFIG_PARAM_SET: + case PM_IOCTL: + case PM_QUERY_DATA: + case PM_CLOCK_ENABLE: + case PM_CLOCK_DISABLE: + case PM_CLOCK_GETSTATE: + case PM_CLOCK_SETDIVIDER: + case PM_CLOCK_GETDIVIDER: + case PM_CLOCK_SETPARENT: + case PM_CLOCK_GETPARENT: + case PM_PLL_SET_PARAMETER: + case PM_PLL_GET_PARAMETER: + case PM_PLL_SET_MODE: + case PM_PLL_GET_MODE: + case PM_FEATURE_CHECK: + *version = (PM_API_BASE_VERSION << 16); + break; + default: + *version = 0U; + return PM_RET_ERROR_NOFEATURE; + } + + PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_FEATURE_CHECK, api_id); + + status = pm_ipi_send_sync(primary_proc, payload, &fw_api_version, 1); + if (status != PM_RET_SUCCESS) + return status; + + *version |= fw_api_version; + + return PM_RET_SUCCESS; +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 282c175a8..4e884e087 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -65,5 +65,5 @@ enum pm_ret_status pm_api_ioctl(uint32_t device_id, uint32_t ioctl_id, enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t *data); unsigned int pm_get_shutdown_scope(void); - +enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index 281494a76..a7b0a0297 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -33,6 +33,12 @@ XPM_NODESUBCL_DEV_PERIPH, \ XPM_NODETYPE_DEV_PERIPH, (IDX)) +#define PM_GET_CALLBACK_DATA 0xa01 +#define PM_GET_TRUSTZONE_VERSION 0xa03 + +/* PM API Versions */ +#define PM_API_BASE_VERSION 1U + /* PM API ids */ #define PM_GET_API_VERSION 1U #define PM_GET_DEVICE_STATUS 3U @@ -70,6 +76,7 @@ #define PM_PLL_GET_PARAMETER 49U #define PM_PLL_SET_MODE 50U #define PM_PLL_GET_MODE 51U +#define PM_FEATURE_CHECK 63U /* IOCTL IDs for clock driver */ #define IOCTL_SET_PLL_FRAC_MODE 8 @@ -121,6 +128,7 @@ typedef enum { * @PM_RET_SUCCESS: success * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated) * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated) + * @PM_RET_ERROR_NOFEATURE: feature is not available * @PM_RET_ERROR_INTERNAL: internal error * @PM_RET_ERROR_CONFLICT: conflict * @PM_RET_ERROR_ACCESS: access rights violation @@ -134,6 +142,7 @@ enum pm_ret_status { PM_RET_SUCCESS, PM_RET_ERROR_ARGS = 1, PM_RET_ERROR_NOTSUPPORTED = 4, + PM_RET_ERROR_NOFEATURE = 19, PM_RET_ERROR_INTERNAL = 2000, PM_RET_ERROR_CONFLICT = 2001, PM_RET_ERROR_ACCESS = 2002, diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index 8140b6644..b5a678332 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -17,9 +17,6 @@ #include "pm_client.h" #include "pm_ipi.h" -#define PM_GET_CALLBACK_DATA 0xa01 -#define PM_GET_TRUSTZONE_VERSION 0xa03 - /* pm_up = true - UP, pm_up = false - DOWN */ static bool pm_up; @@ -293,6 +290,14 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | ((uint64_t)VERSAL_TZ_VERSION << 32)); + case PM_FEATURE_CHECK: + { + uint32_t version; + + ret = pm_feature_check(pm_arg[0], &version); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)version << 32)); + } + default: WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid); SMC_RET1(handle, SMC_UNK); -- cgit v1.2.3 From e4c54c0d2d54599db4b0f9e0e6f644864b05dd3e Mon Sep 17 00:00:00 2001 From: Jolly Shah Date: Fri, 22 Mar 2019 05:33:39 +0530 Subject: plat: xilinx: versal: Add load Pdi API support This patch adds support for load pdi api to enable loading pdi from linux. Signed-off-by: Jolly Shah Change-Id: I48549e276e1f7b9be45a0bebf559f73bd09d5f69 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 25 +++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 2 ++ plat/xilinx/versal/pm_service/pm_defs.h | 3 +++ plat/xilinx/versal/pm_service/pm_svc_main.c | 6 ++++++ 4 files changed, 36 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 54fd6e118..e48fbf576 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -802,6 +802,9 @@ enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version) case PM_FEATURE_CHECK: *version = (PM_API_BASE_VERSION << 16); break; + case PM_LOAD_PDI: + *version = (PM_API_BASE_VERSION << 16); + return PM_RET_SUCCESS; default: *version = 0U; return PM_RET_ERROR_NOFEATURE; @@ -817,3 +820,25 @@ enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version) return PM_RET_SUCCESS; } + +/** + * pm_load_pdi() - Load the PDI + * + * This function provides support to load PDI from linux + * + * src: Source device of pdi(DDR, OCM, SD etc) + * address_low: lower 32-bit Linear memory space address + * address_high: higher 32-bit Linear memory space address + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_load_pdi(uint32_t src, + uint32_t address_low, uint32_t address_high) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, PM_LOAD_PDI, src, + address_high, address_low); + return pm_ipi_send_sync(primary_proc, payload, NULL, 0); +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 4e884e087..5effbb683 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -66,4 +66,6 @@ enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t *data); unsigned int pm_get_shutdown_scope(void); enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version); +enum pm_ret_status pm_load_pdi(uint32_t src, uint32_t address_low, + uint32_t address_high); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index a7b0a0297..892804d7f 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -78,6 +78,9 @@ #define PM_PLL_GET_MODE 51U #define PM_FEATURE_CHECK 63U +/* Loader API ids */ +#define PM_LOAD_PDI 0x701U + /* IOCTL IDs for clock driver */ #define IOCTL_SET_PLL_FRAC_MODE 8 #define IOCTL_GET_PLL_FRAC_MODE 9 diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index b5a678332..bbe8097a8 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -298,6 +298,12 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, SMC_RET1(handle, (uint64_t)ret | ((uint64_t)version << 32)); } + case PM_LOAD_PDI: + { + ret = pm_load_pdi(pm_arg[0], pm_arg[1], pm_arg[2]); + SMC_RET1(handle, (uint64_t)ret); + } + default: WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid); SMC_RET1(handle, SMC_UNK); -- cgit v1.2.3 From ea6e1c39423301b49b304fc474c649e519644fa4 Mon Sep 17 00:00:00 2001 From: Ravi Patel Date: Mon, 12 Aug 2019 03:17:54 -0700 Subject: plat: versal: Add Get_ChipID API Add support for Get_ChipID API in Versal which calls corresponding LibPM API. Signed-off-by: Ravi Patel Acked-by: Jolly Shah Signed-off-by: Jolly Shah Change-Id: I25c4b301721d7989d982ac376c59195c55564022 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 17 +++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 1 + plat/xilinx/versal/pm_service/pm_defs.h | 1 + plat/xilinx/versal/pm_service/pm_svc_main.c | 9 +++++++++ 4 files changed, 28 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index e48fbf576..a4c0b285e 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -748,6 +748,23 @@ enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t wkup_device, return pm_ipi_send(primary_proc, payload); } +/** + * pm_get_chipid() - Read silicon ID registers + * @value Buffer for return values. Must be large enough + * to hold 8 bytes. + * + * @return Returns silicon ID registers + */ +enum pm_ret_status pm_get_chipid(uint32_t *value) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD1(payload, LIBPM_MODULE_ID, PM_GET_CHIPID); + + return pm_ipi_send_sync(primary_proc, payload, value, 2); +} + /** * pm_feature_check() - Returns the supported API version if supported * @api_id API ID to check diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 5effbb683..995c49efa 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -65,6 +65,7 @@ enum pm_ret_status pm_api_ioctl(uint32_t device_id, uint32_t ioctl_id, enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t *data); unsigned int pm_get_shutdown_scope(void); +enum pm_ret_status pm_get_chipid(uint32_t *value); enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version); enum pm_ret_status pm_load_pdi(uint32_t src, uint32_t address_low, uint32_t address_high); diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index 892804d7f..7d4066bdc 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -55,6 +55,7 @@ #define PM_RESET_ASSERT 17U #define PM_RESET_GET_STATUS 18U #define PM_INIT_FINALIZE 21U +#define PM_GET_CHIPID 24U #define PM_PINCTRL_REQUEST 28U #define PM_PINCTRL_RELEASE 29U #define PM_PINCTRL_GET_FUNCTION 30U diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index bbe8097a8..d2460131f 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -290,6 +290,15 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | ((uint64_t)VERSAL_TZ_VERSION << 32)); + case PM_GET_CHIPID: + { + uint32_t result[2]; + + ret = pm_get_chipid(result); + SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32), + result[1]); + } + case PM_FEATURE_CHECK: { uint32_t version; -- cgit v1.2.3 From f50828d52ec6fc7c20459d5ce581ffa927347030 Mon Sep 17 00:00:00 2001 From: Saeed Nowshadi Date: Mon, 3 Jun 2019 10:22:35 -0700 Subject: xilinx: versal: Add support for PM_GET_OPERATING_CHARACTERISTIC EEMI call This patch adds EEMI support for PM_GET_OPERATING_CHARACTERISTIC api id. This interface obtains operating characteristic of a device from PMC firmware. The 'power', 'temperature', and 'latency' characteristic are the options that are supported. Signed-off-by: Saeed Nowshadi Signed-off-by: Jolly Shah Change-Id: If30959ba6a3a778a17df2a4281c2c09832cf7e92 --- plat/xilinx/versal/pm_service/pm_api_sys.c | 24 ++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_api_sys.h | 3 +++ plat/xilinx/versal/pm_service/pm_defs.h | 7 +++++++ plat/xilinx/versal/pm_service/pm_svc_main.c | 8 ++++++++ 4 files changed, 42 insertions(+) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index a4c0b285e..dbe94e624 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -785,6 +785,7 @@ enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version) return PM_RET_SUCCESS; case PM_GET_API_VERSION: case PM_GET_DEVICE_STATUS: + case PM_GET_OP_CHARACTERISTIC: case PM_REQ_SUSPEND: case PM_SELF_SUSPEND: case PM_FORCE_POWERDOWN: @@ -859,3 +860,26 @@ enum pm_ret_status pm_load_pdi(uint32_t src, address_high, address_low); return pm_ipi_send_sync(primary_proc, payload, NULL, 0); } + +/** + * pm_get_op_characteristic() - PM call to request operating characteristics + * of a device + * @device_id Device id + * @type Type of the operating characteristic + * (power, temperature and latency) + * @result Returns the operating characteristic for the requested device, + * specified by the type + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_get_op_characteristic(uint32_t device_id, + enum pm_opchar_type type, + uint32_t *result) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMC */ + PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_GET_OP_CHARACTERISTIC, + device_id, type); + return pm_ipi_send_sync(primary_proc, payload, result, 1); +} diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 995c49efa..4de592a2f 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -69,4 +69,7 @@ enum pm_ret_status pm_get_chipid(uint32_t *value); enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version); enum pm_ret_status pm_load_pdi(uint32_t src, uint32_t address_low, uint32_t address_high); +enum pm_ret_status pm_get_op_characteristic(uint32_t device_id, + enum pm_opchar_type type, + uint32_t *result); #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index 7d4066bdc..966b00bb5 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -42,6 +42,7 @@ /* PM API ids */ #define PM_GET_API_VERSION 1U #define PM_GET_DEVICE_STATUS 3U +#define PM_GET_OP_CHARACTERISTIC 4U #define PM_REQ_SUSPEND 6U #define PM_SELF_SUSPEND 7U #define PM_FORCE_POWERDOWN 8U @@ -112,6 +113,12 @@ enum pm_abort_reason { ABORT_REASON_UNKNOWN, }; +enum pm_opchar_type { + PM_OPCHAR_TYPE_POWER = 1, + PM_OPCHAR_TYPE_TEMP, + PM_OPCHAR_TYPE_LATENCY, +}; + /** * Subsystem IDs */ diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index d2460131f..a3a9f4316 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -313,6 +313,14 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, SMC_RET1(handle, (uint64_t)ret); } + case PM_GET_OP_CHARACTERISTIC: + { + uint32_t result; + + ret = pm_get_op_characteristic(pm_arg[0], pm_arg[1], &result); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)result << 32)); + } + default: WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid); SMC_RET1(handle, SMC_UNK); -- cgit v1.2.3 From c959c479ebda1879af5b24ce55da5bd093dca6b8 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Sat, 27 Apr 2019 11:23:20 +0530 Subject: arm64: versal: Adjust cpu clock for versal virtual This patch modifies cpu clock for Xilinx Versal virtual platform in order to keep same as used by QEMU. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Jolly Shah Change-Id: I169d082462d7ce94a82c62966ab9eb122c5a3fee --- plat/xilinx/versal/include/versal_def.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h index c2f78882d..c08928a44 100644 --- a/plat/xilinx/versal/include/versal_def.h +++ b/plat/xilinx/versal/include/versal_def.h @@ -87,7 +87,7 @@ # define PLATFORM_NAME "Versal Virt" # define VERSAL_UART_CLOCK 25000000 # define VERSAL_UART_BAUDRATE 115200 -# define VERSAL_CPU_CLOCK 62500000 +# define VERSAL_CPU_CLOCK 2720000 #endif /* Access control register defines */ -- cgit v1.2.3 From f8a650c15324efc3f8df421637cd221035701152 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 25 Jun 2019 17:48:27 +0530 Subject: plat: xilinx: versal: Dont set IOU switch clock The IOU switch clock will be set by PLM during boot so there is no need to set here and hence this patch removes it. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Jolly Shah Change-Id: I1512708411eb07a07c1a8fbd66575efee975431a --- plat/xilinx/versal/aarch64/versal_common.c | 4 ---- plat/xilinx/versal/include/versal_def.h | 3 --- 2 files changed, 7 deletions(-) diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c index 29528da8a..825421e29 100644 --- a/plat/xilinx/versal/aarch64/versal_common.c +++ b/plat/xilinx/versal/aarch64/versal_common.c @@ -46,10 +46,6 @@ void versal_config_setup(void) versal_print_platform_name(); - mmio_write_32(VERSAL_CRL_IOU_SWITCH_CTRL, - VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT | - (0x20 << VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT)); - /* Global timer init - Program time stamp reference clk */ val = mmio_read_32(VERSAL_CRL_TIMESTAMP_REF_CTRL); val |= VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h index c08928a44..a1479a10c 100644 --- a/plat/xilinx/versal/include/versal_def.h +++ b/plat/xilinx/versal/include/versal_def.h @@ -35,13 +35,10 @@ /* CRL */ #define VERSAL_CRL 0xFF5E0000 -#define VERSAL_CRL_IOU_SWITCH_CTRL (VERSAL_CRL + 0x114) #define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C) #define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348) #define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25) -#define VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT (1 << 25) -#define VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 /* IOU SCNTRS */ #define VERSAL_IOU_SCNTRS 0xFF140000 -- cgit v1.2.3 From 29af4789759714db41d10e3c80d0b00e14916d54 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Mon, 25 Nov 2019 01:47:48 -0700 Subject: versal: Increase OCM memory size for DEBUG builds ATF can't fit in current OCM size when the DEBUG is enabled, so increase the OCM size to use 128Kb. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Jolly Shah Change-Id: I2ebfd1f2e9db9c0b28770aea7f8fbf1a8a15787a --- plat/xilinx/versal/include/platform_def.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h index c6be09e75..bcc7a9364 100644 --- a/plat/xilinx/versal/include/platform_def.h +++ b/plat/xilinx/versal/include/platform_def.h @@ -31,7 +31,7 @@ * little space for growth. */ #ifndef VERSAL_ATF_MEM_BASE -# define BL31_BASE 0xfffea000 +# define BL31_BASE 0xfffe0000 # define BL31_LIMIT 0xffffffff #else # define BL31_BASE (VERSAL_ATF_MEM_BASE) -- cgit v1.2.3 From d69bbd0e80d07d4c9008a0666e192491ddf52e43 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 3 May 2019 16:35:25 +0530 Subject: xilinx: versal: Wire silicon default setup Add new option for serial and default clock setup. Signed-off-by: Michal Simek Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Jolly Shah Change-Id: I0ca7ad51637cdaa6bb891f22c53595d20da7236a --- plat/xilinx/versal/include/versal_def.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h index a1479a10c..94bd321b8 100644 --- a/plat/xilinx/versal/include/versal_def.h +++ b/plat/xilinx/versal/include/versal_def.h @@ -19,6 +19,7 @@ /* List all supported platforms */ #define VERSAL_PLATFORM_ID_versal_virt 1 +#define VERSAL_PLATFORM_ID_silicon 4 #define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) @@ -85,6 +86,11 @@ # define VERSAL_UART_CLOCK 25000000 # define VERSAL_UART_BAUDRATE 115200 # define VERSAL_CPU_CLOCK 2720000 +#elif VERSAL_PLATFORM_IS(silicon) +# define PLATFORM_NAME "Versal Silicon" +# define VERSAL_UART_CLOCK 100000000 +# define VERSAL_UART_BAUDRATE 115200 +# define VERSAL_CPU_CLOCK 100000000 #endif /* Access control register defines */ -- cgit v1.2.3 From 7b9f0cfd8c7944635ff84520ba7fa32c470b0cd8 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 10 Jul 2019 16:15:19 +0530 Subject: plat: xilinx: versal: Make silicon default build target This patch makes default build target as silicon instead of QEMU. The default can be overwritten by specifying it through build flag VERSAL_PLATFORM. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Jolly Shah Change-Id: Ia4cb1df1f206db3e514e8ce969acca875e973ace --- docs/plat/xilinx-versal.rst | 2 +- plat/xilinx/versal/platform.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/plat/xilinx-versal.rst b/docs/plat/xilinx-versal.rst index 231286e7e..95c89a8b2 100644 --- a/docs/plat/xilinx-versal.rst +++ b/docs/plat/xilinx-versal.rst @@ -14,7 +14,7 @@ To build: make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 ``` -To build ATF for different platform (for now its just versal virtual "versal_virt") +To build ATF for different platform (supported are "silicon"(default) and "versal_virt") ```bash make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal VERSAL_PLATFORM=versal_virt bl31 ``` diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk index 52d2c977b..7a8bfa31a 100644 --- a/plat/xilinx/versal/platform.mk +++ b/plat/xilinx/versal/platform.mk @@ -31,7 +31,7 @@ ifdef VERSAL_BL32_MEM_BASE $(eval $(call add_define,VERSAL_BL32_MEM_SIZE)) endif -VERSAL_PLATFORM ?= versal_virt +VERSAL_PLATFORM ?= silicon $(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFORM})) VERSAL_CONSOLE ?= pl011 -- cgit v1.2.3 From 92c30ac35b298bb4049778ed1c0b95713e44e44c Mon Sep 17 00:00:00 2001 From: Tejas Patel Date: Fri, 10 Jan 2020 03:08:40 -0800 Subject: plat: xilinx: Move pm_client.h to common directory Move pm_client.h to common directory to avoid duplication of function declaration. Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Change-Id: Iea542e681f42db089cccd9b24d286ac8f0a2ce35 --- plat/xilinx/common/include/pm_client.h | 32 +++++++++++++++++++++++++++++++ plat/xilinx/versal/pm_service/pm_client.h | 26 ------------------------- plat/xilinx/zynqmp/pm_service/pm_client.h | 29 ---------------------------- 3 files changed, 32 insertions(+), 55 deletions(-) create mode 100644 plat/xilinx/common/include/pm_client.h delete mode 100644 plat/xilinx/versal/pm_service/pm_client.h delete mode 100644 plat/xilinx/zynqmp/pm_service/pm_client.h diff --git a/plat/xilinx/common/include/pm_client.h b/plat/xilinx/common/include/pm_client.h new file mode 100644 index 000000000..e91bb8f6c --- /dev/null +++ b/plat/xilinx/common/include/pm_client.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Contains APU specific macros and macros to be defined depending on + * the execution environment. + */ + +#ifndef PM_CLIENT_H +#define PM_CLIENT_H + +#include "pm_common.h" +#include "pm_defs.h" + +/* Functions to be implemented by each PU */ +void pm_client_suspend(const struct pm_proc *proc, unsigned int state); +void pm_client_abort_suspend(void); +void pm_client_wakeup(const struct pm_proc *proc); + +/* Global variables to be set in pm_client.c */ +extern const struct pm_proc *primary_proc; + +#ifndef VERSAL_PLATFORM +enum pm_ret_status set_ocm_retention(void); +enum pm_ret_status pm_set_suspend_mode(uint32_t mode); +const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid); +#endif + +#endif /* PM_CLIENT_H */ diff --git a/plat/xilinx/versal/pm_service/pm_client.h b/plat/xilinx/versal/pm_service/pm_client.h deleted file mode 100644 index 91f135c06..000000000 --- a/plat/xilinx/versal/pm_service/pm_client.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2019, Xilinx, Inc. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * Contains APU specific macros and macros to be defined depending on - * the execution environment. - */ - -#ifndef PM_CLIENT_H -#define PM_CLIENT_H - -#include "pm_common.h" -#include "pm_defs.h" - -/* Functions to be implemented by each PU */ -void pm_client_suspend(const struct pm_proc *proc, unsigned int state); -void pm_client_wakeup(const struct pm_proc *proc); -void pm_client_abort_suspend(void); - -/* Global variables to be set in pm_client.c */ -extern const struct pm_proc *primary_proc; - -#endif /* PM_CLIENT_H */ diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.h b/plat/xilinx/zynqmp/pm_service/pm_client.h deleted file mode 100644 index adbb76f9b..000000000 --- a/plat/xilinx/zynqmp/pm_service/pm_client.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * Contains APU specific macros and macros to be defined depending on - * the execution environment. - */ - -#ifndef PM_CLIENT_H -#define PM_CLIENT_H - -#include "pm_common.h" -#include "pm_defs.h" - -/* Functions to be implemented by each PU */ -void pm_client_suspend(const struct pm_proc *proc, unsigned int state); -void pm_client_abort_suspend(void); -void pm_client_wakeup(const struct pm_proc *proc); -enum pm_ret_status set_ocm_retention(void); -enum pm_ret_status pm_set_suspend_mode(uint32_t mode); -const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid); - -/* Global variables to be set in pm_client.c */ -extern const struct pm_proc *primary_proc; - -#endif /* PM_CLIENT_H */ -- cgit v1.2.3 From 222519a0ea5cf3dbbb64de6e69de83d43c06a795 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Mon, 21 Oct 2019 16:27:29 +0800 Subject: intel: Modify non secure access function Combine both peripheral and bridge non-secure access code into a single callable function Signed-off-by: Hadi Asyrafi Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70 --- plat/intel/soc/agilex/bl2_plat_setup.c | 1 - plat/intel/soc/agilex/include/agilex_system_manager.h | 3 +++ plat/intel/soc/agilex/soc/agilex_system_manager.c | 6 ++++++ plat/intel/soc/stratix10/include/s10_system_manager.h | 12 +++++++++++- plat/intel/soc/stratix10/soc/s10_system_manager.c | 11 +++++++++++ 5 files changed, 31 insertions(+), 2 deletions(-) diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index 86b7ab88f..0366f50db 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -74,7 +74,6 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, socfpga_delay_timer_init(); init_ncore_ccu(); init_hard_memory_controller(); - enable_ns_bridge_access(); } diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h index be2953664..65ab9f96c 100644 --- a/plat/intel/soc/agilex/include/agilex_system_manager.h +++ b/plat/intel/soc/agilex/include/agilex_system_manager.h @@ -66,6 +66,7 @@ #define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 #define AGX_SYSMGR_CORE(x) (0xffd12000 + (x)) + #define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 #define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 #define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 @@ -73,6 +74,8 @@ #define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 #define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) +void enable_nonsecure_access(void); +void enable_ns_peripheral_access(void); void enable_ns_bridge_access(void); #endif diff --git a/plat/intel/soc/agilex/soc/agilex_system_manager.c b/plat/intel/soc/agilex/soc/agilex_system_manager.c index 88e895d66..2232365d3 100644 --- a/plat/intel/soc/agilex/soc/agilex_system_manager.c +++ b/plat/intel/soc/agilex/soc/agilex_system_manager.c @@ -10,6 +10,12 @@ #include "agilex_system_manager.h" void enable_nonsecure_access(void) +{ + enable_ns_peripheral_access(); + enable_ns_bridge_access(); +} + +void enable_ns_peripheral_access(void) { mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL); mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL); diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h index 4abfedb56..8c5118198 100644 --- a/plat/intel/soc/stratix10/include/s10_system_manager.h +++ b/plat/intel/soc/stratix10/include/s10_system_manager.h @@ -4,6 +4,10 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#define S10_FIREWALL_SOC2FPGA 0xffd21200 +#define S10_FIREWALL_LWSOC2FPGA 0xffd21300 + +/* L3 Interconnect Register Map */ #define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000 #define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004 #define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c @@ -59,13 +63,19 @@ #define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 #define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 +/* System Manager Register Map */ #define S10_SYSMGR_CORE(x) (0xffd12000 + (x)) + #define SYSMGR_MMC 0x28 #define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0) + #define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 #define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 #define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 - +#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 #define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) +void enable_nonsecure_access(void); +void enable_ns_peripheral_access(void); +void enable_ns_bridge_access(void); diff --git a/plat/intel/soc/stratix10/soc/s10_system_manager.c b/plat/intel/soc/stratix10/soc/s10_system_manager.c index a2ed5a3ed..6963e7da2 100644 --- a/plat/intel/soc/stratix10/soc/s10_system_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_system_manager.c @@ -9,6 +9,12 @@ #include "s10_system_manager.h" void enable_nonsecure_access(void) +{ + enable_ns_peripheral_access(); + enable_ns_bridge_access(); +} + +void enable_ns_peripheral_access(void) { mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL); mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL); @@ -91,3 +97,8 @@ void enable_nonsecure_access(void) } +void enable_ns_bridge_access(void) +{ + mmio_write_32(S10_FIREWALL_SOC2FPGA, DISABLE_BRIDGE_FIREWALL); + mmio_write_32(S10_FIREWALL_LWSOC2FPGA, DISABLE_BRIDGE_FIREWALL); +} -- cgit v1.2.3 From 3dcb94dd847cf7a0c7d26772b2973e958ee079cc Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Mon, 21 Oct 2019 16:35:08 +0800 Subject: intel: Enable bridge access in Intel platform Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: Hadi Asyrafi Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f --- plat/intel/soc/agilex/bl2_plat_setup.c | 4 +- .../soc/agilex/include/agilex_memory_controller.h | 3 - .../soc/agilex/include/agilex_reset_manager.h | 2 + .../soc/agilex/include/agilex_system_manager.h | 11 ++++ plat/intel/soc/agilex/soc/agilex_reset_manager.c | 66 ++++++++++++++++++++++ plat/intel/soc/stratix10/bl2_plat_setup.c | 2 + .../soc/stratix10/include/s10_memory_controller.h | 2 - .../soc/stratix10/include/s10_reset_manager.h | 14 ++++- .../soc/stratix10/include/s10_system_manager.h | 11 ++++ .../soc/stratix10/soc/s10_memory_controller.c | 3 +- plat/intel/soc/stratix10/soc/s10_reset_manager.c | 66 ++++++++++++++++++++++ 11 files changed, 175 insertions(+), 9 deletions(-) diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index 0366f50db..d1602798d 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -74,6 +74,8 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, socfpga_delay_timer_init(); init_ncore_ccu(); init_hard_memory_controller(); + mailbox_init(); + socfpga_bridges_enable(); } @@ -106,8 +108,6 @@ void bl2_el3_plat_arch_setup(void) info.mmc_dev_type = MMC_IS_SD; info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; - mailbox_init(); - switch (boot_source) { case BOOT_SOURCE_SDMMC: dw_mmc_init(¶ms, &info); diff --git a/plat/intel/soc/agilex/include/agilex_memory_controller.h b/plat/intel/soc/agilex/include/agilex_memory_controller.h index 419bd2eff..3746d92fc 100644 --- a/plat/intel/soc/agilex/include/agilex_memory_controller.h +++ b/plat/intel/soc/agilex/include/agilex_memory_controller.h @@ -24,9 +24,6 @@ #define AGX_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \ (((value) & 0x00000060) >> 5) -#define AGX_RSTMGR_BRGMODRST 0xffd1102c -#define AGX_RSTMGR_BRGMODRST_DDRSCH 0x00000040 - #define AGX_MPFE_HMC_ADP_ECCCTRL1 0xf8011100 #define AGX_MPFE_HMC_ADP_ECCCTRL2 0xf8011104 #define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218 diff --git a/plat/intel/soc/agilex/include/agilex_reset_manager.h b/plat/intel/soc/agilex/include/agilex_reset_manager.h index a1b6297c1..9c9c8848a 100644 --- a/plat/intel/soc/agilex/include/agilex_reset_manager.h +++ b/plat/intel/soc/agilex/include/agilex_reset_manager.h @@ -74,6 +74,8 @@ void deassert_peripheral_reset(void); void config_hps_hs_before_warm_reset(void); +int socfpga_bridges_enable(void); +int socfpga_bridges_disable(void); #endif diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h index 65ab9f96c..ab47c458b 100644 --- a/plat/intel/soc/agilex/include/agilex_system_manager.h +++ b/plat/intel/soc/agilex/include/agilex_system_manager.h @@ -67,6 +67,17 @@ #define AGX_SYSMGR_CORE(x) (0xffd12000 + (x)) +#define SYSMGR_NOC_TIMEOUT 0xc0 +#define SYSMGR_NOC_IDLEREQ_SET 0xc4 +#define SYSMGR_NOC_IDLEREQ_CLR 0xc8 +#define SYSMGR_NOC_IDLEREQ_VAL 0xcc +#define SYSMGR_NOC_IDLEACK 0xd0 +#define SYSMGR_NOC_IDLESTATUS 0xd4 + +#define IDLE_DATA_LWSOC2FPGA BIT(0) +#define IDLE_DATA_SOC2FPGA BIT(4) +#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) + #define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 #define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 #define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 diff --git a/plat/intel/soc/agilex/soc/agilex_reset_manager.c b/plat/intel/soc/agilex/soc/agilex_reset_manager.c index 65d2029df..1224a90de 100644 --- a/plat/intel/soc/agilex/soc/agilex_reset_manager.c +++ b/plat/intel/soc/agilex/soc/agilex_reset_manager.c @@ -4,9 +4,13 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include +#include #include #include "agilex_reset_manager.h" +#include "agilex_system_manager.h" +#include "socfpga_mailbox.h" void deassert_peripheral_reset(void) { @@ -80,3 +84,65 @@ void config_hps_hs_before_warm_reset(void) mmio_setbits_32(AGX_RSTMGR_HDSKEN, or_mask); } +static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match) +{ + int time_out = 1000; + + while (time_out--) { + if ((mmio_read_32(addr) & mask) == match) { + return 0; + } + } + return -ETIMEDOUT; +} + +int socfpga_bridges_enable(void) +{ + uint32_t status, poll_addr; + + status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); + + if (!status) { + /* Clear idle request */ + mmio_setbits_32(AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_CLR), ~0); + + /* De-assert all bridges */ + mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, ~0); + + /* Wait until idle ack becomes 0 */ + poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); + + return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0); + } + return status; +} + +int socfpga_bridges_disable(void) +{ + uint32_t poll_addr; + + /* Set idle request */ + mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_SET), ~0); + + /* Enable NOC timeout */ + mmio_setbits_32(SYSMGR_NOC_TIMEOUT, 1); + + /* Wait until each idle ack bit toggle to 1 */ + poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); + if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) + return -ETIMEDOUT; + + /* Wait until each idle status bit toggle to 1 */ + poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLESTATUS); + if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) + return -ETIMEDOUT; + + /* Assert all bridges */ + mmio_setbits_32(AGX_RSTMGR_BRGMODRST, + ~(AGX_RSTMGR_BRGMODRST_MPFE | AGX_RSTMGR_BRGMODRST_FPGA2SOC)); + + /* Disable NOC timeout */ + mmio_clrbits_32(AGX_SYSMGR_CORE(SYSMGR_NOC_TIMEOUT), 1); + + return 0; +} diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 85a60d651..e53d7ec04 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -72,6 +72,8 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, socfpga_delay_timer_init(); init_hard_memory_controller(); + mailbox_init(); + socfpga_bridges_enable(); } diff --git a/plat/intel/soc/stratix10/include/s10_memory_controller.h b/plat/intel/soc/stratix10/include/s10_memory_controller.h index ad7cb9db1..155b2795e 100644 --- a/plat/intel/soc/stratix10/include/s10_memory_controller.h +++ b/plat/intel/soc/stratix10/include/s10_memory_controller.h @@ -22,8 +22,6 @@ #define S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \ (((value) & 0x00000060) >> 5) -#define S10_RSTMGR_BRGMODRST 0xffd1102c -#define S10_RSTMGR_BRGMODRST_DDRSCH 0x00000040 #define S10_MPFE_HMC_ADP_ECCCTRL1 0xf8011100 #define S10_MPFE_HMC_ADP_ECCCTRL2 0xf8011104 diff --git a/plat/intel/soc/stratix10/include/s10_reset_manager.h b/plat/intel/soc/stratix10/include/s10_reset_manager.h index 731a8ddb6..40e7bac67 100644 --- a/plat/intel/soc/stratix10/include/s10_reset_manager.h +++ b/plat/intel/soc/stratix10/include/s10_reset_manager.h @@ -9,7 +9,9 @@ #define S10_RSTMGR_PER0MODRST 0xffd11024 #define S10_RSTMGR_PER1MODRST 0xffd11028 -#define S10_RSTMGR_HDSKEN 0xffd11010 +#define S10_RSTMGR_HDSKEN 0xffd11010 +#define S10_RSTMGR_BRGMODRST 0xffd1102c + #define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001 #define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002 @@ -80,8 +82,18 @@ #define S10_RSTMGR_PER0MODRST_DMAIF6 0x40000000 #define S10_RSTMGR_PER0MODRST_DMAIF7 0x80000000 +#define BRGMODRST_DDRSCH_MASK 0x40 +#define BRGMODRST_F2SSDRAM2_MASK 0x20 +#define BRGMODRST_F2SSDRAM1_MASK 0x10 +#define BRGMODRST_F2SSDRAM_MASK 0x08 +#define BRGMODRST_FPGA2SOC_MASK 0x04 +#define BRGMODRST_LWHPS2FPGA_MASK 0x02 +#define BRGMODRST_SOC2FPGA_MASK 0x01 + void deassert_peripheral_reset(void); void config_hps_hs_before_warm_reset(void); +int socfpga_bridges_enable(void); +int socfpga_bridges_disable(void); #endif diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h index 8c5118198..c34fcf7df 100644 --- a/plat/intel/soc/stratix10/include/s10_system_manager.h +++ b/plat/intel/soc/stratix10/include/s10_system_manager.h @@ -69,6 +69,17 @@ #define SYSMGR_MMC 0x28 #define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0) +#define SYSMGR_NOC_TIMEOUT 0xc0 +#define SYSMGR_NOC_IDLEREQ_SET 0xc4 +#define SYSMGR_NOC_IDLEREQ_CLR 0xc8 +#define SYSMGR_NOC_IDLEREQ_VAL 0xcc +#define SYSMGR_NOC_IDLEACK 0xd0 +#define SYSMGR_NOC_IDLESTATUS 0xd4 + +#define IDLE_DATA_LWSOC2FPGA BIT(0) +#define IDLE_DATA_SOC2FPGA BIT(4) +#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) + #define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 #define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 #define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 diff --git a/plat/intel/soc/stratix10/soc/s10_memory_controller.c b/plat/intel/soc/stratix10/soc/s10_memory_controller.c index cb4525149..a0dafe1dc 100644 --- a/plat/intel/soc/stratix10/soc/s10_memory_controller.c +++ b/plat/intel/soc/stratix10/soc/s10_memory_controller.c @@ -15,6 +15,7 @@ #include #include "s10_memory_controller.h" +#include "s10_reset_manager.h" #define ALT_CCU_NOC_DI_SET_MSK 0x10 @@ -184,7 +185,7 @@ int init_hard_memory_controller(void) return status; } - mmio_clrbits_32(S10_RSTMGR_BRGMODRST, S10_RSTMGR_BRGMODRST_DDRSCH); + mmio_clrbits_32(S10_RSTMGR_BRGMODRST, BRGMODRST_DDRSCH_MASK); status = mem_calibration(); if (status) { diff --git a/plat/intel/soc/stratix10/soc/s10_reset_manager.c b/plat/intel/soc/stratix10/soc/s10_reset_manager.c index 8b7420bf1..5030e4f20 100644 --- a/plat/intel/soc/stratix10/soc/s10_reset_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_reset_manager.c @@ -11,10 +11,14 @@ #include #include #include +#include #include #include #include + #include "s10_reset_manager.h" +#include "s10_system_manager.h" +#include "socfpga_mailbox.h" void deassert_peripheral_reset(void) { @@ -86,3 +90,65 @@ void config_hps_hs_before_warm_reset(void) mmio_setbits_32(S10_RSTMGR_HDSKEN, or_mask); } +static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match) +{ + int time_out = 1000; + + while (time_out--) { + if ((mmio_read_32(addr) & mask) == match) { + return 0; + } + } + return -ETIMEDOUT; +} + +int socfpga_bridges_enable(void) +{ + uint32_t status, poll_addr; + + status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); + + if (!status) { + /* Clear idle request */ + mmio_setbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_CLR), ~0); + + /* De-assert all bridges */ + mmio_clrbits_32(S10_RSTMGR_BRGMODRST, ~0); + + /* Wait until idle ack becomes 0 */ + poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); + + return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0); + } + return status; +} + +int socfpga_bridges_disable(void) +{ + uint32_t poll_addr; + + /* Set idle request */ + mmio_write_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_SET), ~0); + + /* Enable NOC timeout */ + mmio_setbits_32(SYSMGR_NOC_TIMEOUT, 1); + + /* Wait until each idle ack bit toggle to 1 */ + poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); + if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) + return -ETIMEDOUT; + + /* Wait until each idle status bit toggle to 1 */ + poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLESTATUS); + if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) + return -ETIMEDOUT; + + /* Assert all bridges */ + mmio_setbits_32(S10_RSTMGR_BRGMODRST, + ~(BRGMODRST_DDRSCH_MASK | BRGMODRST_FPGA2SOC_MASK)); + + /* Disable NOC timeout */ + mmio_clrbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_TIMEOUT), 1); + + return 0; +} -- cgit v1.2.3 From 391eeeef7f90c8b53ca0f63637b3d5d4e53af35b Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Mon, 23 Dec 2019 13:25:33 +0800 Subject: intel: Refactor reset manager driver Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: Hadi Asyrafi Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a --- plat/intel/soc/agilex/bl2_plat_setup.c | 2 +- .../soc/agilex/include/agilex_reset_manager.h | 81 ----------- plat/intel/soc/agilex/include/socfpga_plat_def.h | 4 +- plat/intel/soc/agilex/platform.mk | 2 +- plat/intel/soc/agilex/soc/agilex_reset_manager.c | 148 ------------------- .../soc/common/include/socfpga_reset_manager.h | 102 +++++++++++++- plat/intel/soc/common/soc/socfpga_reset_manager.c | 156 +++++++++++++++++++++ plat/intel/soc/common/socfpga_psci.c | 12 +- plat/intel/soc/stratix10/bl2_plat_setup.c | 2 +- plat/intel/soc/stratix10/bl31_plat_setup.c | 3 +- .../soc/stratix10/include/s10_reset_manager.h | 99 ------------- .../intel/soc/stratix10/include/socfpga_plat_def.h | 4 +- plat/intel/soc/stratix10/platform.mk | 2 +- .../soc/stratix10/soc/s10_memory_controller.c | 4 +- plat/intel/soc/stratix10/soc/s10_reset_manager.c | 154 -------------------- 15 files changed, 268 insertions(+), 507 deletions(-) delete mode 100644 plat/intel/soc/agilex/include/agilex_reset_manager.h delete mode 100644 plat/intel/soc/agilex/soc/agilex_reset_manager.c create mode 100644 plat/intel/soc/common/soc/socfpga_reset_manager.c delete mode 100644 plat/intel/soc/stratix10/include/s10_reset_manager.h delete mode 100644 plat/intel/soc/stratix10/soc/s10_reset_manager.c diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index d1602798d..a27680cbb 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -18,13 +18,13 @@ #include "agilex_clock_manager.h" #include "agilex_memory_controller.h" #include "agilex_pinmux.h" -#include "agilex_reset_manager.h" #include "agilex_system_manager.h" #include "ccu/ncore_ccu.h" #include "qspi/cadence_qspi.h" #include "socfpga_handoff.h" #include "socfpga_mailbox.h" #include "socfpga_private.h" +#include "socfpga_reset_manager.h" #include "wdt/watchdog.h" diff --git a/plat/intel/soc/agilex/include/agilex_reset_manager.h b/plat/intel/soc/agilex/include/agilex_reset_manager.h deleted file mode 100644 index 9c9c8848a..000000000 --- a/plat/intel/soc/agilex/include/agilex_reset_manager.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef AGX_RESETMANAGER_H -#define AGX_RESETMANAGER_H - -#define AGX_RSTMGR_HDSKEN 0xffd11010 -#define AGX_RSTMGR_PER0MODRST 0xffd11024 -#define AGX_RSTMGR_PER1MODRST 0xffd11028 -#define AGX_RSTMGR_BRGMODRST 0xffd1102c - -#define AGX_RSTMGR_PER0MODRST_EMAC0 0x00000001 -#define AGX_RSTMGR_PER0MODRST_EMAC1 0x00000002 -#define AGX_RSTMGR_PER0MODRST_EMAC2 0x00000004 -#define AGX_RSTMGR_PER0MODRST_USB0 0x00000008 -#define AGX_RSTMGR_PER0MODRST_USB1 0x00000010 -#define AGX_RSTMGR_PER0MODRST_NAND 0x00000020 -#define AGX_RSTMGR_PER0MODRST_SDMMC 0x00000080 -#define AGX_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 -#define AGX_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 -#define AGX_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 -#define AGX_RSTMGR_PER0MODRST_USB0OCP 0x00000800 -#define AGX_RSTMGR_PER0MODRST_USB1OCP 0x00001000 -#define AGX_RSTMGR_PER0MODRST_NANDOCP 0x00002000 -#define AGX_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000 -#define AGX_RSTMGR_PER0MODRST_DMA 0x00010000 -#define AGX_RSTMGR_PER0MODRST_SPIM0 0x00020000 -#define AGX_RSTMGR_PER0MODRST_SPIM1 0x00040000 -#define AGX_RSTMGR_PER0MODRST_SPIS0 0x00080000 -#define AGX_RSTMGR_PER0MODRST_SPIS1 0x00100000 -#define AGX_RSTMGR_PER0MODRST_DMAOCP 0x00200000 -#define AGX_RSTMGR_PER0MODRST_EMACPTP 0x00400000 -#define AGX_RSTMGR_PER0MODRST_DMAIF0 0x01000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF1 0x02000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF2 0x04000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF3 0x08000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF4 0x10000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF5 0x20000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF6 0x40000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF7 0x80000000 - -#define AGX_RSTMGR_PER1MODRST_WATCHDOG0 0x1 -#define AGX_RSTMGR_PER1MODRST_WATCHDOG1 0x2 -#define AGX_RSTMGR_PER1MODRST_WATCHDOG2 0x4 -#define AGX_RSTMGR_PER1MODRST_WATCHDOG3 0x8 -#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010 -#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020 -#define AGX_RSTMGR_PER1MODRST_SPTIMER0 0x00000040 -#define AGX_RSTMGR_PER1MODRST_SPTIMER1 0x00000080 -#define AGX_RSTMGR_PER1MODRST_I2C0 0x00000100 -#define AGX_RSTMGR_PER1MODRST_I2C1 0x00000200 -#define AGX_RSTMGR_PER1MODRST_I2C2 0x00000400 -#define AGX_RSTMGR_PER1MODRST_I2C3 0x00000800 -#define AGX_RSTMGR_PER1MODRST_I2C4 0x00001000 -#define AGX_RSTMGR_PER1MODRST_UART0 0x00010000 -#define AGX_RSTMGR_PER1MODRST_UART1 0x00020000 -#define AGX_RSTMGR_PER1MODRST_GPIO0 0x01000000 -#define AGX_RSTMGR_PER1MODRST_GPIO1 0x02000000 - -#define AGX_RSTMGR_HDSKEN_FPGAHSEN 0x00000004 -#define AGX_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 -#define AGX_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100 -#define AGX_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 -#define AGX_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 -#define AGX_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001 - -#define AGX_RSTMGR_BRGMODRST_SOC2FPGA 0x1 -#define AGX_RSTMGR_BRGMODRST_LWHPS2FPGA 0x2 -#define AGX_RSTMGR_BRGMODRST_FPGA2SOC 0x4 -#define AGX_RSTMGR_BRGMODRST_MPFE 0x40 - -void deassert_peripheral_reset(void); -void config_hps_hs_before_warm_reset(void); -int socfpga_bridges_enable(void); -int socfpga_bridges_disable(void); - -#endif - diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h index a346cb5f8..386750347 100644 --- a/plat/intel/soc/agilex/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h @@ -15,9 +15,7 @@ /* Register Mapping */ #define SOCFPGA_MMC_REG_BASE 0xff808000 - -#define SOCFPGA_RSTMGR_OFST 0xffd11000 -#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020 +#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 #endif /* PLAT_SOCFPGA_DEF_H */ diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index ef02a8dfb..c4904be02 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -38,7 +38,6 @@ BL2_SOURCES += \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ plat/intel/soc/agilex/soc/agilex_memory_controller.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ - plat/intel/soc/agilex/soc/agilex_reset_manager.c \ plat/intel/soc/agilex/soc/agilex_system_manager.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/common/socfpga_delay_timer.c \ @@ -46,6 +45,7 @@ BL2_SOURCES += \ plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c \ plat/intel/soc/common/drivers/ccu/ncore_ccu.c diff --git a/plat/intel/soc/agilex/soc/agilex_reset_manager.c b/plat/intel/soc/agilex/soc/agilex_reset_manager.c deleted file mode 100644 index 1224a90de..000000000 --- a/plat/intel/soc/agilex/soc/agilex_reset_manager.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include "agilex_reset_manager.h" -#include "agilex_system_manager.h" -#include "socfpga_mailbox.h" - -void deassert_peripheral_reset(void) -{ - mmio_clrbits_32(AGX_RSTMGR_PER1MODRST, - AGX_RSTMGR_PER1MODRST_WATCHDOG0 | - AGX_RSTMGR_PER1MODRST_WATCHDOG1 | - AGX_RSTMGR_PER1MODRST_WATCHDOG2 | - AGX_RSTMGR_PER1MODRST_WATCHDOG3 | - AGX_RSTMGR_PER1MODRST_L4SYSTIMER0 | - AGX_RSTMGR_PER1MODRST_L4SYSTIMER1 | - AGX_RSTMGR_PER1MODRST_SPTIMER0 | - AGX_RSTMGR_PER1MODRST_SPTIMER1 | - AGX_RSTMGR_PER1MODRST_I2C0 | - AGX_RSTMGR_PER1MODRST_I2C1 | - AGX_RSTMGR_PER1MODRST_I2C2 | - AGX_RSTMGR_PER1MODRST_I2C3 | - AGX_RSTMGR_PER1MODRST_I2C4 | - AGX_RSTMGR_PER1MODRST_UART0 | - AGX_RSTMGR_PER1MODRST_UART1 | - AGX_RSTMGR_PER1MODRST_GPIO0 | - AGX_RSTMGR_PER1MODRST_GPIO1); - - mmio_clrbits_32(AGX_RSTMGR_PER0MODRST, - AGX_RSTMGR_PER0MODRST_EMAC0OCP | - AGX_RSTMGR_PER0MODRST_EMAC1OCP | - AGX_RSTMGR_PER0MODRST_EMAC2OCP | - AGX_RSTMGR_PER0MODRST_USB0OCP | - AGX_RSTMGR_PER0MODRST_USB1OCP | - AGX_RSTMGR_PER0MODRST_NANDOCP | - AGX_RSTMGR_PER0MODRST_SDMMCOCP | - AGX_RSTMGR_PER0MODRST_DMAOCP); - - mmio_clrbits_32(AGX_RSTMGR_PER0MODRST, - AGX_RSTMGR_PER0MODRST_EMAC0 | - AGX_RSTMGR_PER0MODRST_EMAC1 | - AGX_RSTMGR_PER0MODRST_EMAC2 | - AGX_RSTMGR_PER0MODRST_USB0 | - AGX_RSTMGR_PER0MODRST_USB1 | - AGX_RSTMGR_PER0MODRST_NAND | - AGX_RSTMGR_PER0MODRST_SDMMC | - AGX_RSTMGR_PER0MODRST_DMA | - AGX_RSTMGR_PER0MODRST_SPIM0 | - AGX_RSTMGR_PER0MODRST_SPIM1 | - AGX_RSTMGR_PER0MODRST_SPIS0 | - AGX_RSTMGR_PER0MODRST_SPIS1 | - AGX_RSTMGR_PER0MODRST_EMACPTP | - AGX_RSTMGR_PER0MODRST_DMAIF0 | - AGX_RSTMGR_PER0MODRST_DMAIF1 | - AGX_RSTMGR_PER0MODRST_DMAIF2 | - AGX_RSTMGR_PER0MODRST_DMAIF3 | - AGX_RSTMGR_PER0MODRST_DMAIF4 | - AGX_RSTMGR_PER0MODRST_DMAIF5 | - AGX_RSTMGR_PER0MODRST_DMAIF6 | - AGX_RSTMGR_PER0MODRST_DMAIF7); - - mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, - AGX_RSTMGR_BRGMODRST_MPFE); -} - -void config_hps_hs_before_warm_reset(void) -{ - uint32_t or_mask = 0; - - or_mask |= AGX_RSTMGR_HDSKEN_SDRSELFREFEN; - or_mask |= AGX_RSTMGR_HDSKEN_FPGAHSEN; - or_mask |= AGX_RSTMGR_HDSKEN_ETRSTALLEN; - or_mask |= AGX_RSTMGR_HDSKEN_L2FLUSHEN; - or_mask |= AGX_RSTMGR_HDSKEN_L3NOC_DBG; - or_mask |= AGX_RSTMGR_HDSKEN_DEBUG_L3NOC; - - mmio_setbits_32(AGX_RSTMGR_HDSKEN, or_mask); -} - -static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match) -{ - int time_out = 1000; - - while (time_out--) { - if ((mmio_read_32(addr) & mask) == match) { - return 0; - } - } - return -ETIMEDOUT; -} - -int socfpga_bridges_enable(void) -{ - uint32_t status, poll_addr; - - status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); - - if (!status) { - /* Clear idle request */ - mmio_setbits_32(AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_CLR), ~0); - - /* De-assert all bridges */ - mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, ~0); - - /* Wait until idle ack becomes 0 */ - poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); - - return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0); - } - return status; -} - -int socfpga_bridges_disable(void) -{ - uint32_t poll_addr; - - /* Set idle request */ - mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_SET), ~0); - - /* Enable NOC timeout */ - mmio_setbits_32(SYSMGR_NOC_TIMEOUT, 1); - - /* Wait until each idle ack bit toggle to 1 */ - poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); - if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) - return -ETIMEDOUT; - - /* Wait until each idle status bit toggle to 1 */ - poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLESTATUS); - if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) - return -ETIMEDOUT; - - /* Assert all bridges */ - mmio_setbits_32(AGX_RSTMGR_BRGMODRST, - ~(AGX_RSTMGR_BRGMODRST_MPFE | AGX_RSTMGR_BRGMODRST_FPGA2SOC)); - - /* Disable NOC timeout */ - mmio_clrbits_32(AGX_SYSMGR_CORE(SYSMGR_NOC_TIMEOUT), 1); - - return 0; -} diff --git a/plat/intel/soc/common/include/socfpga_reset_manager.h b/plat/intel/soc/common/include/socfpga_reset_manager.h index 3fbf242f4..637f8dfe5 100644 --- a/plat/intel/soc/common/include/socfpga_reset_manager.h +++ b/plat/intel/soc/common/include/socfpga_reset_manager.h @@ -7,12 +7,102 @@ #ifndef SOCFPGA_RESETMANAGER_H #define SOCFPGA_RESETMANAGER_H -#define SOCFPGA_RSTMGR_STAT 0xffd11000 -#define SOCFPGA_RSTMGR_HDSKEN 0xffd11010 -#define SOCFPGA_RSTMGR_COLDMODRST 0xffd11034 -#define SOCFPGA_RSTMGR_HDSKTIMEOUT 0xffd11064 +#include "socfpga_plat_def.h" -#define SOCFPGA_RSTMGR_HDSKEN_SET 0x0000010D -#define SOCFPGA_RSTMGR_SDMWARMRST 0x00000002 + +/* Register Mapping */ + +#define SOCFPGA_RSTMGR_STAT 0x000 +#define SOCFPGA_RSTMGR_HDSKEN 0x010 +#define SOCFPGA_RSTMGR_MPUMODRST 0x020 +#define SOCFPGA_RSTMGR_PER0MODRST 0x024 +#define SOCFPGA_RSTMGR_PER1MODRST 0x028 +#define SOCFPGA_RSTMGR_BRGMODRST 0x02c +#define SOCFPGA_RSTMGR_COLDMODRST 0x034 +#define SOCFPGA_RSTMGR_HDSKTIMEOUT 0x064 + +/* Field Mapping */ + +#define RSTMGR_PER0MODRST_EMAC0 0x00000001 +#define RSTMGR_PER0MODRST_EMAC1 0x00000002 +#define RSTMGR_PER0MODRST_EMAC2 0x00000004 +#define RSTMGR_PER0MODRST_USB0 0x00000008 +#define RSTMGR_PER0MODRST_USB1 0x00000010 +#define RSTMGR_PER0MODRST_NAND 0x00000020 +#define RSTMGR_PER0MODRST_SDMMC 0x00000080 +#define RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 +#define RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 +#define RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 +#define RSTMGR_PER0MODRST_USB0OCP 0x00000800 +#define RSTMGR_PER0MODRST_USB1OCP 0x00001000 +#define RSTMGR_PER0MODRST_NANDOCP 0x00002000 +#define RSTMGR_PER0MODRST_SDMMCOCP 0x00008000 +#define RSTMGR_PER0MODRST_DMA 0x00010000 +#define RSTMGR_PER0MODRST_SPIM0 0x00020000 +#define RSTMGR_PER0MODRST_SPIM1 0x00040000 +#define RSTMGR_PER0MODRST_SPIS0 0x00080000 +#define RSTMGR_PER0MODRST_SPIS1 0x00100000 +#define RSTMGR_PER0MODRST_DMAOCP 0x00200000 +#define RSTMGR_PER0MODRST_EMACPTP 0x00400000 +#define RSTMGR_PER0MODRST_DMAIF0 0x01000000 +#define RSTMGR_PER0MODRST_DMAIF1 0x02000000 +#define RSTMGR_PER0MODRST_DMAIF2 0x04000000 +#define RSTMGR_PER0MODRST_DMAIF3 0x08000000 +#define RSTMGR_PER0MODRST_DMAIF4 0x10000000 +#define RSTMGR_PER0MODRST_DMAIF5 0x20000000 +#define RSTMGR_PER0MODRST_DMAIF6 0x40000000 +#define RSTMGR_PER0MODRST_DMAIF7 0x80000000 + +#define RSTMGR_PER1MODRST_WATCHDOG0 0x00000001 +#define RSTMGR_PER1MODRST_WATCHDOG1 0x00000002 +#define RSTMGR_PER1MODRST_WATCHDOG2 0x00000004 +#define RSTMGR_PER1MODRST_WATCHDOG3 0x00000008 +#define RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010 +#define RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020 +#define RSTMGR_PER1MODRST_SPTIMER0 0x00000040 +#define RSTMGR_PER1MODRST_SPTIMER1 0x00000080 +#define RSTMGR_PER1MODRST_I2C0 0x00000100 +#define RSTMGR_PER1MODRST_I2C1 0x00000200 +#define RSTMGR_PER1MODRST_I2C2 0x00000400 +#define RSTMGR_PER1MODRST_I2C3 0x00000800 +#define RSTMGR_PER1MODRST_I2C4 0x00001000 +#define RSTMGR_PER1MODRST_UART0 0x00010000 +#define RSTMGR_PER1MODRST_UART1 0x00020000 +#define RSTMGR_PER1MODRST_GPIO0 0x01000000 +#define RSTMGR_PER1MODRST_GPIO1 0x02000000 + +#define RSTMGR_HDSKEN_FPGAHSEN 0x00000004 +#define RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 +#define RSTMGR_HDSKEN_L2FLUSHEN 0x00000100 +#define RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 +#define RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 +#define RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001 + +#define RSTMGR_BRGMODRST_SOC2FPGA 0x1 +#define RSTMGR_BRGMODRST_LWHPS2FPGA 0x2 +#define RSTMGR_BRGMODRST_FPGA2SOC 0x4 +#define RSTMGR_BRGMODRST_F2SSDRAM1 0x10 +#define RSTMGR_BRGMODRST_F2SSDRAM2 0x20 +#define RSTMGR_BRGMODRST_MPFE 0x40 +#define RSTMGR_BRGMODRST_DDRSCH 0x40 + +/* Definitions */ + +#define RSTMGR_L2_MODRST 0x0100 +#define RSTMGR_HDSKEN_SET 0x010D + +/* Macros */ + +#define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE \ + + (SOCFPGA_RSTMGR_##_reg)) +#define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field) + +/* Function Declarations */ + +void deassert_peripheral_reset(void); +void config_hps_hs_before_warm_reset(void); + +int socfpga_bridges_enable(void); +int socfpga_bridges_disable(void); #endif /* SOCFPGA_RESETMANAGER_H */ diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c new file mode 100644 index 000000000..58ab282ad --- /dev/null +++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include "s10_system_manager.h" +#include "socfpga_mailbox.h" +#include "socfpga_reset_manager.h" + + +void deassert_peripheral_reset(void) +{ + mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST), + RSTMGR_FIELD(PER1, WATCHDOG0) | + RSTMGR_FIELD(PER1, WATCHDOG1) | + RSTMGR_FIELD(PER1, WATCHDOG2) | + RSTMGR_FIELD(PER1, WATCHDOG3) | + RSTMGR_FIELD(PER1, L4SYSTIMER0) | + RSTMGR_FIELD(PER1, L4SYSTIMER1) | + RSTMGR_FIELD(PER1, SPTIMER0) | + RSTMGR_FIELD(PER1, SPTIMER1) | + RSTMGR_FIELD(PER1, I2C0) | + RSTMGR_FIELD(PER1, I2C1) | + RSTMGR_FIELD(PER1, I2C2) | + RSTMGR_FIELD(PER1, I2C3) | + RSTMGR_FIELD(PER1, I2C4) | + RSTMGR_FIELD(PER1, UART0) | + RSTMGR_FIELD(PER1, UART1) | + RSTMGR_FIELD(PER1, GPIO0) | + RSTMGR_FIELD(PER1, GPIO1)); + + mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), + RSTMGR_FIELD(PER0, EMAC0OCP) | + RSTMGR_FIELD(PER0, EMAC1OCP) | + RSTMGR_FIELD(PER0, EMAC2OCP) | + RSTMGR_FIELD(PER0, USB0OCP) | + RSTMGR_FIELD(PER0, USB1OCP) | + RSTMGR_FIELD(PER0, NANDOCP) | + RSTMGR_FIELD(PER0, SDMMCOCP) | + RSTMGR_FIELD(PER0, DMAOCP)); + + mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), + RSTMGR_FIELD(PER0, EMAC0) | + RSTMGR_FIELD(PER0, EMAC1) | + RSTMGR_FIELD(PER0, EMAC2) | + RSTMGR_FIELD(PER0, USB0) | + RSTMGR_FIELD(PER0, USB1) | + RSTMGR_FIELD(PER0, NAND) | + RSTMGR_FIELD(PER0, SDMMC) | + RSTMGR_FIELD(PER0, DMA) | + RSTMGR_FIELD(PER0, SPIM0) | + RSTMGR_FIELD(PER0, SPIM1) | + RSTMGR_FIELD(PER0, SPIS0) | + RSTMGR_FIELD(PER0, SPIS1) | + RSTMGR_FIELD(PER0, EMACPTP) | + RSTMGR_FIELD(PER0, DMAIF0) | + RSTMGR_FIELD(PER0, DMAIF1) | + RSTMGR_FIELD(PER0, DMAIF2) | + RSTMGR_FIELD(PER0, DMAIF3) | + RSTMGR_FIELD(PER0, DMAIF4) | + RSTMGR_FIELD(PER0, DMAIF5) | + RSTMGR_FIELD(PER0, DMAIF6) | + RSTMGR_FIELD(PER0, DMAIF7)); + +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX + mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), + RSTMGR_FIELD(BRG, MPFE)); +#endif +} + +void config_hps_hs_before_warm_reset(void) +{ + uint32_t or_mask = 0; + + or_mask |= RSTMGR_HDSKEN_SDRSELFREFEN; + or_mask |= RSTMGR_HDSKEN_FPGAHSEN; + or_mask |= RSTMGR_HDSKEN_ETRSTALLEN; + or_mask |= RSTMGR_HDSKEN_L2FLUSHEN; + or_mask |= RSTMGR_HDSKEN_L3NOC_DBG; + or_mask |= RSTMGR_HDSKEN_DEBUG_L3NOC; + + mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask); +} + +static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match) +{ + int time_out = 1000; + + while (time_out--) { + if ((mmio_read_32(addr) & mask) == match) { + return 0; + } + } + return -ETIMEDOUT; +} + +int socfpga_bridges_enable(void) +{ + uint32_t status, poll_addr; + + status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); + + if (!status) { + /* Clear idle request */ + mmio_setbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_CLR), ~0); + + /* De-assert all bridges */ + mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0); + + /* Wait until idle ack becomes 0 */ + poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); + + return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0); + } + return status; +} + +int socfpga_bridges_disable(void) +{ + uint32_t poll_addr; + + /* Set idle request */ + mmio_write_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_SET), ~0); + + /* Enable NOC timeout */ + mmio_setbits_32(SYSMGR_NOC_TIMEOUT, 1); + + /* Wait until each idle ack bit toggle to 1 */ + poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); + if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) + return -ETIMEDOUT; + + /* Wait until each idle status bit toggle to 1 */ + poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLESTATUS); + if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) + return -ETIMEDOUT; + + /* Assert all bridges */ +#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 + mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), + ~(RSTMGR_FIELD(BRG, DDRSCH) | RSTMGR_FIELD(BRG, FPGA2SOC))); +#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX + mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), + ~(RSTMGR_FIELD(BRG, MPFE) | RSTMGR_FIELD(BRG, FPGA2SOC))); +#endif + + /* Disable NOC timeout */ + mmio_clrbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_TIMEOUT), 1); + + return 0; +} diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c index 1ba48eae1..d8a6c1980 100644 --- a/plat/intel/soc/common/socfpga_psci.c +++ b/plat/intel/soc/common/socfpga_psci.c @@ -47,7 +47,7 @@ int socfpga_pwr_domain_on(u_register_t mpidr) mmio_write_64(PLAT_CPUID_RELEASE, cpu_id); /* release core reset */ - mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); + mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id); return PSCI_E_SUCCESS; } @@ -78,7 +78,7 @@ void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state) __func__, i, target_state->pwr_domain_state[i]); /* assert core reset */ - mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); + mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id); } @@ -117,7 +117,7 @@ void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state) __func__, i, target_state->pwr_domain_state[i]); /* release core reset */ - mmio_clrbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); + mmio_clrbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id); } /******************************************************************************* @@ -148,13 +148,13 @@ static int socfpga_system_reset2(int is_vendor, int reset_type, mmio_write_32(L2_RESET_DONE_REG, L2_RESET_DONE_STATUS); /* Increase timeout */ - mmio_write_32(SOCFPGA_RSTMGR_HDSKTIMEOUT, 0xffffff); + mmio_write_32(SOCFPGA_RSTMGR(HDSKTIMEOUT), 0xffffff); /* Enable handshakes */ - mmio_setbits_32(SOCFPGA_RSTMGR_HDSKEN, SOCFPGA_RSTMGR_HDSKEN_SET); + mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_SET); /* Reset L2 module */ - mmio_setbits_32(SOCFPGA_RSTMGR_COLDMODRST, 0x100); + mmio_setbits_32(SOCFPGA_RSTMGR(COLDMODRST), 0x100); while (1) wfi(); diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index e53d7ec04..229683836 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -19,10 +19,10 @@ #include "socfpga_handoff.h" #include "socfpga_mailbox.h" #include "socfpga_private.h" +#include "socfpga_reset_manager.h" #include "s10_clock_manager.h" #include "s10_memory_controller.h" #include "s10_pinmux.h" -#include "s10_reset_manager.h" #include "s10_system_manager.h" #include "wdt/watchdog.h" diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 29bd1763f..48dad01b8 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -17,12 +17,13 @@ #include #include "socfpga_private.h" -#include "s10_reset_manager.h" +#include "socfpga_reset_manager.h" #include "s10_memory_controller.h" #include "s10_pinmux.h" #include "s10_clock_manager.h" #include "s10_system_manager.h" + static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; diff --git a/plat/intel/soc/stratix10/include/s10_reset_manager.h b/plat/intel/soc/stratix10/include/s10_reset_manager.h deleted file mode 100644 index 40e7bac67..000000000 --- a/plat/intel/soc/stratix10/include/s10_reset_manager.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __S10_RESETMANAGER_H__ -#define __S10_RESETMANAGER_H__ - -#define S10_RSTMGR_PER0MODRST 0xffd11024 -#define S10_RSTMGR_PER1MODRST 0xffd11028 -#define S10_RSTMGR_HDSKEN 0xffd11010 -#define S10_RSTMGR_BRGMODRST 0xffd1102c - - -#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001 -#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002 -#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004 -#define S10_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 -#define S10_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 -#define S10_RSTMGR_PER0MODRST_DMAOCP 0x00200000 -#define S10_RSTMGR_PER0MODRST_DMA 0x00010000 -#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001 -#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002 -#define S10_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 -#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004 -#define S10_RSTMGR_PER0MODRST_EMACPTP 0x00400000 -#define S10_RSTMGR_PER0MODRST_NANDOCP 0x00002000 -#define S10_RSTMGR_PER0MODRST_NAND 0x00000020 -#define S10_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000 -#define S10_RSTMGR_PER0MODRST_SDMMC 0x00000080 -#define S10_RSTMGR_PER0MODRST_SPIM0 0x00020000 -#define S10_RSTMGR_PER0MODRST_SPIM1 0x00040000 -#define S10_RSTMGR_PER0MODRST_SPIS0 0x00080000 -#define S10_RSTMGR_PER0MODRST_SPIS1 0x00100000 -#define S10_RSTMGR_PER0MODRST_USB0OCP 0x00000800 -#define S10_RSTMGR_PER0MODRST_USB0 0x00000008 -#define S10_RSTMGR_PER0MODRST_USB1OCP 0x00001000 -#define S10_RSTMGR_PER0MODRST_USB1 0x00000010 - -#define S10_RSTMGR_PER1MODRST_WATCHDOG0 0x1 -#define S10_RSTMGR_PER1MODRST_WATCHDOG1 0x2 -#define S10_RSTMGR_PER1MODRST_WATCHDOG2 0x4 -#define S10_RSTMGR_PER1MODRST_WATCHDOG3 0x8 -#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000 -#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000 -#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000 -#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000 -#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100 -#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100 -#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200 -#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200 -#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400 -#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400 -#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800 -#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800 -#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000 -#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000 -#define S10_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010 -#define S10_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020 -#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040 -#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040 -#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080 -#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080 -#define S10_RSTMGR_PER1MODRST_UART0 0x00010000 -#define S10_RSTMGR_PER1MODRST_UART0 0x00010000 -#define S10_RSTMGR_PER1MODRST_UART1 0x00020000 -#define S10_RSTMGR_PER1MODRST_UART1 0x00020000 -#define S10_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 -#define S10_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 -#define S10_RSTMGR_HDSKEN_FPGAHSEN 0x00000004 -#define S10_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100 -#define S10_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 - -#define S10_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001 -#define S10_RSTMGR_PER0MODRST_DMAIF0 0x01000000 -#define S10_RSTMGR_PER0MODRST_DMAIF1 0x02000000 -#define S10_RSTMGR_PER0MODRST_DMAIF2 0x04000000 -#define S10_RSTMGR_PER0MODRST_DMAIF3 0x08000000 -#define S10_RSTMGR_PER0MODRST_DMAIF4 0x10000000 -#define S10_RSTMGR_PER0MODRST_DMAIF5 0x20000000 -#define S10_RSTMGR_PER0MODRST_DMAIF6 0x40000000 -#define S10_RSTMGR_PER0MODRST_DMAIF7 0x80000000 - -#define BRGMODRST_DDRSCH_MASK 0x40 -#define BRGMODRST_F2SSDRAM2_MASK 0x20 -#define BRGMODRST_F2SSDRAM1_MASK 0x10 -#define BRGMODRST_F2SSDRAM_MASK 0x08 -#define BRGMODRST_FPGA2SOC_MASK 0x04 -#define BRGMODRST_LWHPS2FPGA_MASK 0x02 -#define BRGMODRST_SOC2FPGA_MASK 0x01 - -void deassert_peripheral_reset(void); -void config_hps_hs_before_warm_reset(void); -int socfpga_bridges_enable(void); -int socfpga_bridges_disable(void); - -#endif - diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h index ab723f79d..066585e79 100644 --- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -14,9 +14,7 @@ /* Register Mapping */ #define SOCFPGA_MMC_REG_BASE 0xff808000 - -#define SOCFPGA_RSTMGR_OFST 0xffd11000 -#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020 +#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 #endif /* PLATSOCFPGA_DEF_H */ diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index e7251c428..2b80a9473 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -38,7 +38,6 @@ BL2_SOURCES += \ plat/intel/soc/stratix10/soc/s10_clock_manager.c \ plat/intel/soc/stratix10/soc/s10_memory_controller.c \ plat/intel/soc/stratix10/soc/s10_pinmux.c \ - plat/intel/soc/stratix10/soc/s10_reset_manager.c \ plat/intel/soc/stratix10/soc/s10_system_manager.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/common/socfpga_delay_timer.c \ @@ -46,6 +45,7 @@ BL2_SOURCES += \ plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c diff --git a/plat/intel/soc/stratix10/soc/s10_memory_controller.c b/plat/intel/soc/stratix10/soc/s10_memory_controller.c index a0dafe1dc..ac756abac 100644 --- a/plat/intel/soc/stratix10/soc/s10_memory_controller.c +++ b/plat/intel/soc/stratix10/soc/s10_memory_controller.c @@ -15,7 +15,7 @@ #include #include "s10_memory_controller.h" -#include "s10_reset_manager.h" +#include "socfpga_reset_manager.h" #define ALT_CCU_NOC_DI_SET_MSK 0x10 @@ -185,7 +185,7 @@ int init_hard_memory_controller(void) return status; } - mmio_clrbits_32(S10_RSTMGR_BRGMODRST, BRGMODRST_DDRSCH_MASK); + mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_FIELD(BRG, DDRSCH)); status = mem_calibration(); if (status) { diff --git a/plat/intel/soc/stratix10/soc/s10_reset_manager.c b/plat/intel/soc/stratix10/soc/s10_reset_manager.c deleted file mode 100644 index 5030e4f20..000000000 --- a/plat/intel/soc/stratix10/soc/s10_reset_manager.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "s10_reset_manager.h" -#include "s10_system_manager.h" -#include "socfpga_mailbox.h" - -void deassert_peripheral_reset(void) -{ - mmio_clrbits_32(S10_RSTMGR_PER1MODRST, - S10_RSTMGR_PER1MODRST_WATCHDOG0 | - S10_RSTMGR_PER1MODRST_WATCHDOG1 | - S10_RSTMGR_PER1MODRST_WATCHDOG2 | - S10_RSTMGR_PER1MODRST_WATCHDOG3 | - S10_RSTMGR_PER1MODRST_L4SYSTIMER0 | - S10_RSTMGR_PER1MODRST_L4SYSTIMER1 | - S10_RSTMGR_PER1MODRST_SPTIMER0 | - S10_RSTMGR_PER1MODRST_SPTIMER1 | - S10_RSTMGR_PER1MODRST_I2C0 | - S10_RSTMGR_PER1MODRST_I2C1 | - S10_RSTMGR_PER1MODRST_I2C2 | - S10_RSTMGR_PER1MODRST_I2C3 | - S10_RSTMGR_PER1MODRST_I2C4 | - S10_RSTMGR_PER1MODRST_UART0 | - S10_RSTMGR_PER1MODRST_UART1 | - S10_RSTMGR_PER1MODRST_GPIO0 | - S10_RSTMGR_PER1MODRST_GPIO1); - - mmio_clrbits_32(S10_RSTMGR_PER0MODRST, - S10_RSTMGR_PER0MODRST_EMAC0OCP | - S10_RSTMGR_PER0MODRST_EMAC1OCP | - S10_RSTMGR_PER0MODRST_EMAC2OCP | - S10_RSTMGR_PER0MODRST_USB0OCP | - S10_RSTMGR_PER0MODRST_USB1OCP | - S10_RSTMGR_PER0MODRST_NANDOCP | - S10_RSTMGR_PER0MODRST_SDMMCOCP | - S10_RSTMGR_PER0MODRST_DMAOCP); - - mmio_clrbits_32(S10_RSTMGR_PER0MODRST, - S10_RSTMGR_PER0MODRST_EMAC0 | - S10_RSTMGR_PER0MODRST_EMAC1 | - S10_RSTMGR_PER0MODRST_EMAC2 | - S10_RSTMGR_PER0MODRST_USB0 | - S10_RSTMGR_PER0MODRST_USB1 | - S10_RSTMGR_PER0MODRST_NAND | - S10_RSTMGR_PER0MODRST_SDMMC | - S10_RSTMGR_PER0MODRST_DMA | - S10_RSTMGR_PER0MODRST_SPIM0 | - S10_RSTMGR_PER0MODRST_SPIM1 | - S10_RSTMGR_PER0MODRST_SPIS0 | - S10_RSTMGR_PER0MODRST_SPIS1 | - S10_RSTMGR_PER0MODRST_EMACPTP | - S10_RSTMGR_PER0MODRST_DMAIF0 | - S10_RSTMGR_PER0MODRST_DMAIF1 | - S10_RSTMGR_PER0MODRST_DMAIF2 | - S10_RSTMGR_PER0MODRST_DMAIF3 | - S10_RSTMGR_PER0MODRST_DMAIF4 | - S10_RSTMGR_PER0MODRST_DMAIF5 | - S10_RSTMGR_PER0MODRST_DMAIF6 | - S10_RSTMGR_PER0MODRST_DMAIF7); - -} - -void config_hps_hs_before_warm_reset(void) -{ - uint32_t or_mask = 0; - - or_mask |= S10_RSTMGR_HDSKEN_SDRSELFREFEN; - or_mask |= S10_RSTMGR_HDSKEN_FPGAHSEN; - or_mask |= S10_RSTMGR_HDSKEN_ETRSTALLEN; - or_mask |= S10_RSTMGR_HDSKEN_L2FLUSHEN; - or_mask |= S10_RSTMGR_HDSKEN_L3NOC_DBG; - or_mask |= S10_RSTMGR_HDSKEN_DEBUG_L3NOC; - - mmio_setbits_32(S10_RSTMGR_HDSKEN, or_mask); -} - -static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match) -{ - int time_out = 1000; - - while (time_out--) { - if ((mmio_read_32(addr) & mask) == match) { - return 0; - } - } - return -ETIMEDOUT; -} - -int socfpga_bridges_enable(void) -{ - uint32_t status, poll_addr; - - status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); - - if (!status) { - /* Clear idle request */ - mmio_setbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_CLR), ~0); - - /* De-assert all bridges */ - mmio_clrbits_32(S10_RSTMGR_BRGMODRST, ~0); - - /* Wait until idle ack becomes 0 */ - poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); - - return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0); - } - return status; -} - -int socfpga_bridges_disable(void) -{ - uint32_t poll_addr; - - /* Set idle request */ - mmio_write_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_SET), ~0); - - /* Enable NOC timeout */ - mmio_setbits_32(SYSMGR_NOC_TIMEOUT, 1); - - /* Wait until each idle ack bit toggle to 1 */ - poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); - if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) - return -ETIMEDOUT; - - /* Wait until each idle status bit toggle to 1 */ - poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLESTATUS); - if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) - return -ETIMEDOUT; - - /* Assert all bridges */ - mmio_setbits_32(S10_RSTMGR_BRGMODRST, - ~(BRGMODRST_DDRSCH_MASK | BRGMODRST_FPGA2SOC_MASK)); - - /* Disable NOC timeout */ - mmio_clrbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_TIMEOUT), 1); - - return 0; -} -- cgit v1.2.3 From 20335ca8d5e4e2e47c93f4e65641a807acf872f0 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Mon, 23 Dec 2019 17:58:04 +0800 Subject: intel: System Manager refactoring Refactored system manager driver to be shared across both intel platform Signed-off-by: Hadi Asyrafi Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d --- plat/intel/soc/agilex/bl2_plat_setup.c | 2 +- .../soc/agilex/include/agilex_system_manager.h | 92 ----------------- plat/intel/soc/agilex/include/socfpga_plat_def.h | 7 ++ plat/intel/soc/agilex/platform.mk | 2 +- plat/intel/soc/agilex/soc/agilex_clock_manager.c | 10 +- plat/intel/soc/agilex/soc/agilex_system_manager.c | 99 ------------------ .../soc/common/include/socfpga_system_manager.h | 113 +++++++++++++++++++++ plat/intel/soc/common/soc/socfpga_reset_manager.c | 16 +-- plat/intel/soc/common/soc/socfpga_system_manager.c | 107 +++++++++++++++++++ plat/intel/soc/stratix10/bl2_plat_setup.c | 2 +- plat/intel/soc/stratix10/bl31_plat_setup.c | 2 +- .../soc/stratix10/include/s10_system_manager.h | 92 ----------------- .../intel/soc/stratix10/include/socfpga_plat_def.h | 8 ++ plat/intel/soc/stratix10/platform.mk | 2 +- plat/intel/soc/stratix10/soc/s10_clock_manager.c | 10 +- plat/intel/soc/stratix10/soc/s10_system_manager.c | 104 ------------------- 16 files changed, 258 insertions(+), 410 deletions(-) delete mode 100644 plat/intel/soc/agilex/include/agilex_system_manager.h delete mode 100644 plat/intel/soc/agilex/soc/agilex_system_manager.c create mode 100644 plat/intel/soc/common/include/socfpga_system_manager.h create mode 100644 plat/intel/soc/common/soc/socfpga_system_manager.c delete mode 100644 plat/intel/soc/stratix10/include/s10_system_manager.h delete mode 100644 plat/intel/soc/stratix10/soc/s10_system_manager.c diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index a27680cbb..022ead6d7 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -18,13 +18,13 @@ #include "agilex_clock_manager.h" #include "agilex_memory_controller.h" #include "agilex_pinmux.h" -#include "agilex_system_manager.h" #include "ccu/ncore_ccu.h" #include "qspi/cadence_qspi.h" #include "socfpga_handoff.h" #include "socfpga_mailbox.h" #include "socfpga_private.h" #include "socfpga_reset_manager.h" +#include "socfpga_system_manager.h" #include "wdt/watchdog.h" diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h deleted file mode 100644 index ab47c458b..000000000 --- a/plat/intel/soc/agilex/include/agilex_system_manager.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef AGX_SYSTEMMANAGER_H -#define AGX_SYSTEMMANAGER_H - -#define AGX_FIREWALL_SOC2FPGA 0xffd21200 -#define AGX_FIREWALL_LWSOC2FPGA 0xffd21300 - -#define AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000 -#define AGX_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004 -#define AGX_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c -#define AGX_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010 -#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c -#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020 -#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024 -#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028 -#define AGX_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c -#define AGX_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030 -#define AGX_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034 -#define AGX_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040 -#define AGX_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044 -#define AGX_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048 -#define AGX_NOC_FW_L4_PER_SCR_I2C0 0xffd21050 -#define AGX_NOC_FW_L4_PER_SCR_I2C1 0xffd21054 -#define AGX_NOC_FW_L4_PER_SCR_I2C2 0xffd21058 -#define AGX_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c -#define AGX_NOC_FW_L4_PER_SCR_I2C4 0xffd21060 -#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064 -#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068 -#define AGX_NOC_FW_L4_PER_SCR_UART0 0xffd2106c -#define AGX_NOC_FW_L4_PER_SCR_UART1 0xffd21070 - -#define AGX_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108 -#define AGX_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c -#define AGX_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110 -#define AGX_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114 -#define AGX_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118 -#define AGX_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c -#define AGX_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120 -#define AGX_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c -#define AGX_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130 -#define AGX_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134 -#define AGX_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138 -#define AGX_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140 -#define AGX_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144 -#define AGX_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148 -#define AGX_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c -#define AGX_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154 -#define AGX_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158 -#define AGX_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c -#define AGX_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160 -#define AGX_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164 -#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168 -#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c -#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170 -#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174 -#define AGX_NOC_FW_L4_SYS_SCR_DAP 0xffd21178 -#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190 -#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194 - -#define AGX_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 -#define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 - -#define AGX_SYSMGR_CORE(x) (0xffd12000 + (x)) - -#define SYSMGR_NOC_TIMEOUT 0xc0 -#define SYSMGR_NOC_IDLEREQ_SET 0xc4 -#define SYSMGR_NOC_IDLEREQ_CLR 0xc8 -#define SYSMGR_NOC_IDLEREQ_VAL 0xcc -#define SYSMGR_NOC_IDLEACK 0xd0 -#define SYSMGR_NOC_IDLESTATUS 0xd4 - -#define IDLE_DATA_LWSOC2FPGA BIT(0) -#define IDLE_DATA_SOC2FPGA BIT(4) -#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) - -#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 -#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 -#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 - -#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 -#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) - -void enable_nonsecure_access(void); -void enable_ns_peripheral_access(void); -void enable_ns_bridge_access(void); - -#endif diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h index 386750347..b4e09210f 100644 --- a/plat/intel/soc/agilex/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h @@ -15,7 +15,14 @@ /* Register Mapping */ #define SOCFPGA_MMC_REG_BASE 0xff808000 + #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 +#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 + +#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 +#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 +#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 +#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 #endif /* PLAT_SOCFPGA_DEF_H */ diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index c4904be02..d04d630b4 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -38,7 +38,6 @@ BL2_SOURCES += \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ plat/intel/soc/agilex/soc/agilex_memory_controller.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ - plat/intel/soc/agilex/soc/agilex_system_manager.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/socfpga_image_load.c \ @@ -46,6 +45,7 @@ BL2_SOURCES += \ plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c \ + plat/intel/soc/common/soc/socfpga_system_manager.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c \ plat/intel/soc/common/drivers/ccu/ncore_ccu.c diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c index 96b669cfd..c6c48baea 100644 --- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c +++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c @@ -11,8 +11,8 @@ #include #include "agilex_clock_manager.h" -#include "agilex_system_manager.h" #include "socfpga_handoff.h" +#include "socfpga_system_manager.h" uint32_t wait_pll_lock(void) @@ -261,9 +261,9 @@ void config_clkmgr_handoff(handoff *hoff_ptr) CLKMGR_PERPLL_EN_RESET); /* Pass clock source frequency into scratch register */ - mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1), + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1), hoff_ptr->hps_osc_clk_h); - mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2), + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2), hoff_ptr->fpga_clk_hz); } @@ -275,14 +275,14 @@ uint32_t get_ref_clk(uint32_t pllglob) switch (CLKMGR_PSRC(pllglob)) { case CLKMGR_PLLGLOB_PSRC_EOSC1: - scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1); + scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1); ref_clk = mmio_read_32(scr_reg); break; case CLKMGR_PLLGLOB_PSRC_INTOSC: ref_clk = CLKMGR_INTOSC_HZ; break; case CLKMGR_PLLGLOB_PSRC_F2S: - scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2); + scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2); ref_clk = mmio_read_32(scr_reg); break; default: diff --git a/plat/intel/soc/agilex/soc/agilex_system_manager.c b/plat/intel/soc/agilex/soc/agilex_system_manager.c deleted file mode 100644 index 2232365d3..000000000 --- a/plat/intel/soc/agilex/soc/agilex_system_manager.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include "agilex_system_manager.h" - -void enable_nonsecure_access(void) -{ - enable_ns_peripheral_access(); - enable_ns_bridge_access(); -} - -void enable_ns_peripheral_access(void) -{ - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC, - DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL); - - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL); - - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL); -} - -void enable_ns_bridge_access(void) -{ - mmio_write_32(AGX_FIREWALL_SOC2FPGA, DISABLE_BRIDGE_FIREWALL); - mmio_write_32(AGX_FIREWALL_LWSOC2FPGA, DISABLE_BRIDGE_FIREWALL); -} diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h new file mode 100644 index 000000000..f1637aed3 --- /dev/null +++ b/plat/intel/soc/common/include/socfpga_system_manager.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOCFPGA_SYSTEMMANAGER_H +#define SOCFPGA_SYSTEMMANAGER_H + +#include "socfpga_plat_def.h" + +/* System Manager Register Map */ + +#define SOCFPGA_SYSMGR_SDMMC 0x28 + +#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc +#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0 +#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4 + +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 + +/* Field Masking */ + +#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) + +#define IDLE_DATA_LWSOC2FPGA BIT(0) +#define IDLE_DATA_SOC2FPGA BIT(4) +#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) + +#define SCR_AXI_AP_MASK BIT(24) +#define SCR_FPGA2SOC_MASK BIT(16) +#define SCR_MPU_MASK BIT(0) +#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \ + | SCR_MPU_MASK) +#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 + +/* Macros */ + +#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ + + (SOCFPGA_SYSMGR_##_reg)) + +#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ + + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg)) + +#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ + + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg)) + +/* L3 Interconnect Register Map */ +#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000 +#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004 +#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c +#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028 +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030 +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040 +#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044 +#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068 +#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c +#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070 + +#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094 + +#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 +#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 + +void enable_nonsecure_access(void); +void enable_ns_peripheral_access(void); +void enable_ns_bridge_access(void); + +#endif /* SOCFPGA_SYSTEMMANAGER_H */ diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c index 58ab282ad..7f6316955 100644 --- a/plat/intel/soc/common/soc/socfpga_reset_manager.c +++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c @@ -8,9 +8,9 @@ #include #include -#include "s10_system_manager.h" #include "socfpga_mailbox.h" #include "socfpga_reset_manager.h" +#include "socfpga_system_manager.h" void deassert_peripheral_reset(void) @@ -107,13 +107,13 @@ int socfpga_bridges_enable(void) if (!status) { /* Clear idle request */ - mmio_setbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_CLR), ~0); + mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0); /* De-assert all bridges */ mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0); /* Wait until idle ack becomes 0 */ - poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); + poll_addr = SOCFPGA_SYSMGR(NOC_IDLEACK); return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0); } @@ -125,18 +125,18 @@ int socfpga_bridges_disable(void) uint32_t poll_addr; /* Set idle request */ - mmio_write_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_SET), ~0); + mmio_write_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET), ~0); /* Enable NOC timeout */ - mmio_setbits_32(SYSMGR_NOC_TIMEOUT, 1); + mmio_setbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); /* Wait until each idle ack bit toggle to 1 */ - poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK); + poll_addr = SOCFPGA_SYSMGR(NOC_IDLEACK); if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) return -ETIMEDOUT; /* Wait until each idle status bit toggle to 1 */ - poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLESTATUS); + poll_addr = SOCFPGA_SYSMGR(NOC_IDLESTATUS); if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) return -ETIMEDOUT; @@ -150,7 +150,7 @@ int socfpga_bridges_disable(void) #endif /* Disable NOC timeout */ - mmio_clrbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_TIMEOUT), 1); + mmio_clrbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); return 0; } diff --git a/plat/intel/soc/common/soc/socfpga_system_manager.c b/plat/intel/soc/common/soc/socfpga_system_manager.c new file mode 100644 index 000000000..a64053ca6 --- /dev/null +++ b/plat/intel/soc/common/soc/socfpga_system_manager.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include "socfpga_system_manager.h" + +void enable_nonsecure_access(void) +{ + enable_ns_peripheral_access(); + enable_ns_bridge_access(); +} + +void enable_ns_peripheral_access(void) +{ + mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_REGISTER), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_DATA), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_READ_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_WRITE_ECC), + DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(USB0_REGISTER), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(USB1_REGISTER), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(USB0_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(USB1_ECC), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_MASTER0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_MASTER1), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_SLAVE0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_SLAVE1), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC1), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC2), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC0RX_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC0TX_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC1RX_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC1TX_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC2RX_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC2TX_ECC), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(SDMMC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(SDMMC_ECC), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(GPIO0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(GPIO1), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(I2C0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(I2C1), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(I2C2), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(I2C3), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(I2C4), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(SP_TIMER1), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(UART0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(UART1), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(DMA_ECC), DISABLE_L4_FIREWALL); + + + mmio_write_32(SOCFPGA_L4_SYS_SCR(OCRAM_ECC), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(CLK_MGR), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(IO_MGR), DISABLE_L4_FIREWALL); + + + mmio_write_32(SOCFPGA_L4_SYS_SCR(RST_MGR), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(SYS_MGR), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(OSC0_TIMER), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(OSC1_TIMER), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG1), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG2), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG3), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(DAP), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_PROBES), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_QOS), DISABLE_L4_FIREWALL); + +#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 + mmio_clrbits_32(SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0, 0x03); + mmio_clrbits_32(SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0, 0x03); + + mmio_write_32(SOCFPGA_SYSMGR(SDMMC), SYSMGR_SDMMC_DRVSEL(3)); +#endif + +} + +void enable_ns_bridge_access(void) +{ + mmio_write_32(SOCFPGA_SOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL); + mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL); +} diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 229683836..5eb796936 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -20,10 +20,10 @@ #include "socfpga_mailbox.h" #include "socfpga_private.h" #include "socfpga_reset_manager.h" +#include "socfpga_system_manager.h" #include "s10_clock_manager.h" #include "s10_memory_controller.h" #include "s10_pinmux.h" -#include "s10_system_manager.h" #include "wdt/watchdog.h" diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 48dad01b8..29f57c467 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -18,10 +18,10 @@ #include "socfpga_private.h" #include "socfpga_reset_manager.h" +#include "socfpga_system_manager.h" #include "s10_memory_controller.h" #include "s10_pinmux.h" #include "s10_clock_manager.h" -#include "s10_system_manager.h" static entry_point_info_t bl32_image_ep_info; diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h deleted file mode 100644 index c34fcf7df..000000000 --- a/plat/intel/soc/stratix10/include/s10_system_manager.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define S10_FIREWALL_SOC2FPGA 0xffd21200 -#define S10_FIREWALL_LWSOC2FPGA 0xffd21300 - -/* L3 Interconnect Register Map */ -#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000 -#define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004 -#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c -#define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010 -#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c -#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020 -#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024 -#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028 -#define S10_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c -#define S10_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030 -#define S10_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034 -#define S10_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040 -#define S10_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044 -#define S10_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048 -#define S10_NOC_FW_L4_PER_SCR_I2C0 0xffd21050 -#define S10_NOC_FW_L4_PER_SCR_I2C1 0xffd21054 -#define S10_NOC_FW_L4_PER_SCR_I2C2 0xffd21058 -#define S10_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c -#define S10_NOC_FW_L4_PER_SCR_I2C4 0xffd21060 -#define S10_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064 -#define S10_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068 -#define S10_NOC_FW_L4_PER_SCR_UART0 0xffd2106c -#define S10_NOC_FW_L4_PER_SCR_UART1 0xffd21070 - -#define S10_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108 -#define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c -#define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110 -#define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114 -#define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118 -#define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c -#define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120 -#define S10_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c -#define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130 -#define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134 -#define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138 -#define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140 -#define S10_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144 -#define S10_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148 -#define S10_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c -#define S10_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154 -#define S10_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158 -#define S10_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c -#define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160 -#define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164 -#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168 -#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c -#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170 -#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174 -#define S10_NOC_FW_L4_SYS_SCR_DAP 0xffd21178 -#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190 -#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194 - -#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 -#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 - -/* System Manager Register Map */ -#define S10_SYSMGR_CORE(x) (0xffd12000 + (x)) - -#define SYSMGR_MMC 0x28 -#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0) - -#define SYSMGR_NOC_TIMEOUT 0xc0 -#define SYSMGR_NOC_IDLEREQ_SET 0xc4 -#define SYSMGR_NOC_IDLEREQ_CLR 0xc8 -#define SYSMGR_NOC_IDLEREQ_VAL 0xcc -#define SYSMGR_NOC_IDLEACK 0xd0 -#define SYSMGR_NOC_IDLESTATUS 0xd4 - -#define IDLE_DATA_LWSOC2FPGA BIT(0) -#define IDLE_DATA_SOC2FPGA BIT(4) -#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) - -#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 -#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 -#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 - -#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 -#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) - -void enable_nonsecure_access(void); -void enable_ns_peripheral_access(void); -void enable_ns_bridge_access(void); diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h index 066585e79..9dc51514c 100644 --- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -14,7 +14,15 @@ /* Register Mapping */ #define SOCFPGA_MMC_REG_BASE 0xff808000 + #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 +#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 + +#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 +#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 +#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 +#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 + #endif /* PLATSOCFPGA_DEF_H */ diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 2b80a9473..a89c3d443 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -38,7 +38,6 @@ BL2_SOURCES += \ plat/intel/soc/stratix10/soc/s10_clock_manager.c \ plat/intel/soc/stratix10/soc/s10_memory_controller.c \ plat/intel/soc/stratix10/soc/s10_pinmux.c \ - plat/intel/soc/stratix10/soc/s10_system_manager.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/socfpga_image_load.c \ @@ -46,6 +45,7 @@ BL2_SOURCES += \ plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c \ + plat/intel/soc/common/soc/socfpga_system_manager.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c index e4ff7acf2..1e092dec4 100644 --- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c @@ -12,8 +12,8 @@ #include #include "s10_clock_manager.h" -#include "s10_system_manager.h" #include "socfpga_handoff.h" +#include "socfpga_system_manager.h" void wait_pll_lock(void) @@ -190,9 +190,9 @@ void config_clkmgr_handoff(handoff *hoff_ptr) ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK); /* Pass clock source frequency into scratch register */ - mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1), + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1), hoff_ptr->hps_osc_clk_h); - mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2), + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2), hoff_ptr->fpga_clk_hz); } @@ -205,14 +205,14 @@ uint32_t get_ref_clk(uint32_t pllglob) switch (ALT_CLKMGR_PSRC(pllglob)) { case ALT_CLKMGR_PLLGLOB_PSRC_EOSC1: - scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1); + scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1); ref_clk = mmio_read_32(scr_reg); break; case ALT_CLKMGR_PLLGLOB_PSRC_INTOSC: ref_clk = ALT_CLKMGR_INTOSC_HZ; break; case ALT_CLKMGR_PLLGLOB_PSRC_F2S: - scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2); + scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2); ref_clk = mmio_read_32(scr_reg); break; default: diff --git a/plat/intel/soc/stratix10/soc/s10_system_manager.c b/plat/intel/soc/stratix10/soc/s10_system_manager.c deleted file mode 100644 index 6963e7da2..000000000 --- a/plat/intel/soc/stratix10/soc/s10_system_manager.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include "s10_system_manager.h" - -void enable_nonsecure_access(void) -{ - enable_ns_peripheral_access(); - enable_ns_bridge_access(); -} - -void enable_ns_peripheral_access(void) -{ - mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC, - DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL); - - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL); - - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL); - - mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03); - mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03); - - mmio_write_32(S10_SYSMGR_CORE(SYSMGR_MMC), SYSMGR_MMC_DRVSEL(3)); - -} - -void enable_ns_bridge_access(void) -{ - mmio_write_32(S10_FIREWALL_SOC2FPGA, DISABLE_BRIDGE_FIREWALL); - mmio_write_32(S10_FIREWALL_LWSOC2FPGA, DISABLE_BRIDGE_FIREWALL); -} -- cgit v1.2.3 From dfdd38c2e14f4a41721f83483e82ee28b6f57c6f Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 17 Dec 2019 23:33:39 +0800 Subject: intel: FPGA config_isdone() status query SiP CONFIG_ISDONE now will query status for either CONFIG_STATUS or RECONFIG_STATUS based on passed parameter Signed-off-by: Hadi Asyrafi Change-Id: Idb8a84af4e98654759843de09a289d31246c9a91 --- plat/intel/soc/common/socfpga_sip_svc.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index ce88fb489..f9ba2351d 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -93,9 +93,14 @@ static int intel_fpga_sdm_write_all(void) return 0; } -static uint32_t intel_mailbox_fpga_config_isdone(void) +static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) { - uint32_t ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); + uint32_t ret; + + if (query_type == 1) + ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); + else + ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); if (ret) { if (ret == MBOX_CFGSTAT_STATE_CONFIG) @@ -368,7 +373,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, SMC_UUID_RET(handle, intl_svc_uid); case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: - status = intel_mailbox_fpga_config_isdone(); + status = intel_mailbox_fpga_config_isdone(x1); SMC_RET4(handle, status, 0, 0, 0); case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: -- cgit v1.2.3 From 9c8f3af50a227cb095a629c0877ff82111c801a9 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 24 Dec 2019 10:42:52 +0800 Subject: intel: Add bridge control for FPGA reconfig This is to make sure that bridge access in disabled before doing full FPGA reconfiguration and turn re-enable it once the configuration succeed. Signed-off-by: Hadi Asyrafi Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d --- plat/intel/soc/agilex/platform.mk | 1 + plat/intel/soc/common/socfpga_sip_svc.c | 16 ++++++++++++++++ plat/intel/soc/stratix10/platform.mk | 1 + 3 files changed, 18 insertions(+) diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index d04d630b4..f47c3f113 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -60,6 +60,7 @@ BL31_SOURCES += \ plat/intel/soc/common/socfpga_sip_svc.c \ plat/intel/soc/common/socfpga_topology.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index f9ba2351d..41dae9e76 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -11,6 +11,7 @@ #include #include "socfpga_mailbox.h" +#include "socfpga_reset_manager.h" #include "socfpga_sip_svc.h" /* Number of SiP Calls implemented */ @@ -27,6 +28,7 @@ static int rcv_id; static int max_blocks; static uint32_t bytes_per_block; static uint32_t blocks_submitted; +static int is_partial_reconfig; struct fpga_config_info { uint32_t addr; @@ -109,6 +111,12 @@ static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) return INTEL_SIP_SMC_STATUS_ERROR; } + if (query_type != 1) { + /* full reconfiguration */ + if (!is_partial_reconfig) + socfpga_bridges_enable(); /* Enable bridge */ + } + return INTEL_SIP_SMC_STATUS_OK; } @@ -196,6 +204,8 @@ static int intel_fpga_config_start(uint32_t config_type) uint32_t response[3]; int status = 0; + is_partial_reconfig = config_type; + mailbox_clear_response(); mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0); @@ -225,6 +235,12 @@ static int intel_fpga_config_start(uint32_t config_type) send_id = 0; rcv_id = 0; + /* full reconfiguration */ + if (!is_partial_reconfig) { + /* Disable bridge */ + socfpga_bridges_disable(); + } + return 0; } diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index a89c3d443..efbab24b3 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -59,6 +59,7 @@ BL31_SOURCES += \ plat/intel/soc/common/socfpga_sip_svc.c \ plat/intel/soc/common/socfpga_topology.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 -- cgit v1.2.3 From f2decc7690dc4d71708a20f6085ae11c9d068c5a Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Tue, 24 Dec 2019 14:43:22 +0800 Subject: intel: Add function to check fpga readiness Create a function to check for fpga readiness, and move the checking out of bridge enable function. Signed-off-by: Hadi Asyrafi Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0 --- plat/intel/soc/agilex/bl2_plat_setup.c | 4 ++- plat/intel/soc/common/include/socfpga_mailbox.h | 1 + plat/intel/soc/common/soc/socfpga_mailbox.c | 10 +++++++ plat/intel/soc/common/soc/socfpga_reset_manager.c | 32 ++++++++--------------- plat/intel/soc/stratix10/bl2_plat_setup.c | 4 ++- 5 files changed, 28 insertions(+), 23 deletions(-) diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index 022ead6d7..9587d4859 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -75,7 +75,9 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, init_ncore_ccu(); init_hard_memory_controller(); mailbox_init(); - socfpga_bridges_enable(); + + if (!intel_mailbox_is_fpga_not_ready()) + socfpga_bridges_enable(); } diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index c5f2fbe77..c4b9e5967 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -120,5 +120,6 @@ void mailbox_reset_cold(void); void mailbox_clear_response(void); uint32_t intel_mailbox_get_config_status(uint32_t cmd); +int intel_mailbox_is_fpga_not_ready(void); #endif /* SOCFPGA_MBOX_H */ diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index eb35c4a08..8d7c1d663 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -316,3 +316,13 @@ uint32_t intel_mailbox_get_config_status(uint32_t cmd) return MBOX_CFGSTAT_STATE_CONFIG; } + +int intel_mailbox_is_fpga_not_ready(void) +{ + int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); + + if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG) + ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); + + return ret; +} diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c index 7f6316955..32604c914 100644 --- a/plat/intel/soc/common/soc/socfpga_reset_manager.c +++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c @@ -101,29 +101,19 @@ static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match) int socfpga_bridges_enable(void) { - uint32_t status, poll_addr; + /* Clear idle request */ + mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0); - status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); + /* De-assert all bridges */ + mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0); - if (!status) { - /* Clear idle request */ - mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0); - - /* De-assert all bridges */ - mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0); - - /* Wait until idle ack becomes 0 */ - poll_addr = SOCFPGA_SYSMGR(NOC_IDLEACK); - - return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0); - } - return status; + /* Wait until idle ack becomes 0 */ + return poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), + IDLE_DATA_MASK, 0); } int socfpga_bridges_disable(void) { - uint32_t poll_addr; - /* Set idle request */ mmio_write_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET), ~0); @@ -131,13 +121,13 @@ int socfpga_bridges_disable(void) mmio_setbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); /* Wait until each idle ack bit toggle to 1 */ - poll_addr = SOCFPGA_SYSMGR(NOC_IDLEACK); - if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) + if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), + IDLE_DATA_MASK, IDLE_DATA_MASK)) return -ETIMEDOUT; /* Wait until each idle status bit toggle to 1 */ - poll_addr = SOCFPGA_SYSMGR(NOC_IDLESTATUS); - if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK)) + if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS), + IDLE_DATA_MASK, IDLE_DATA_MASK)) return -ETIMEDOUT; /* Assert all bridges */ diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 5eb796936..7d183db0d 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -73,7 +73,9 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, socfpga_delay_timer_init(); init_hard_memory_controller(); mailbox_init(); - socfpga_bridges_enable(); + + if (!intel_mailbox_is_fpga_not_ready()) + socfpga_bridges_enable(); } -- cgit v1.2.3 From 26c1a1e7694da88039a1cccc9010a3d19bae61e3 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 20 Nov 2017 17:14:47 -0800 Subject: Tegra194: restore XUSB stream IDs on System Resume The stream IDs for XUSB programmed during cold boot are lost on System Suspend. This patch restores the XUSB stream IDs on System Resume. NOTE: THE WARMBOOT CODE NEEDS TO MAKE SURE THAT THE XUSB MODULE IS OUT OF RESET AND THE CLOCKS ARE ENABLED, BEFORE POWERING ON THE CPU, DURING SYSTEM RESUME. Change-Id: Ibd5f1e5ebacffa6b29b625f4c41ecf204afa8191 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 48 ++++++++++++++++++++++++- plat/nvidia/tegra/soc/t194/plat_setup.c | 19 ++++------ 2 files changed, 54 insertions(+), 13 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index fa5ba6263..9a9113ec2 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -369,6 +369,52 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) /* Resume SE, RNG1 and PKA1 */ tegra_se_resume(); + /* + * Program XUSB STREAMIDs + * ====================== + * T19x XUSB has support for XUSB virtualization. It will + * have one physical function (PF) and four Virtual functions + * (VF) + * + * There were below two SIDs for XUSB until T186. + * 1) #define TEGRA_SID_XUSB_HOST 0x1bU + * 2) #define TEGRA_SID_XUSB_DEV 0x1cU + * + * We have below four new SIDs added for VF(s) + * 3) #define TEGRA_SID_XUSB_VF0 0x5dU + * 4) #define TEGRA_SID_XUSB_VF1 0x5eU + * 5) #define TEGRA_SID_XUSB_VF2 0x5fU + * 6) #define TEGRA_SID_XUSB_VF3 0x60U + * + * When virtualization is enabled then we have to disable SID + * override and program above SIDs in below newly added SID + * registers in XUSB PADCTL MMIO space. These registers are + * TZ protected and so need to be done in ATF. + * + * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) + * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) + * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) + * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) + * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) + * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) + * + * This change disables SID override and programs XUSB SIDs + * in above registers to support both virtualization and + * non-virtualization platforms + */ + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); + /* * Reset power state info for the last core doing SC7 * entry and exit, we set deepest power state as CC7 diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 8c5710557..7dde9dde5 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -197,12 +197,13 @@ void plat_enable_console(int32_t id) ******************************************************************************/ void plat_early_platform_setup(void) { - /* sanity check MCE firmware compatibility */ mce_verify_firmware_version(); - /* Program XUSB STREAMIDs - * Xavier XUSB has support for XUSB virtualization. It will have one + /* + * Program XUSB STREAMIDs + * ====================== + * T19x XUSB has support for XUSB virtualization. It will have one * physical function (PF) and four Virtual function (VF) * * There were below two SIDs for XUSB until T186. @@ -227,14 +228,8 @@ void plat_early_platform_setup(void) * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) * * This change disables SID override and programs XUSB SIDs in - * above registers to support both virtualization and non-virtualization - * - * Known Limitations: - * If xusb interface disables SMMU in XUSB DT in non-virtualization - * setup then there will be SMMU fault. We need to use WAR at - * https:\\git-master.nvidia.com/r/1529227/ to the issue. - * - * More details can be found in the bug 1971161 + * above registers to support both virtualization and + * non-virtualization platforms */ mmio_write_32(TEGRA_XUSB_PADCTL_BASE + XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); -- cgit v1.2.3 From 181a9fabce578cb122e4da37536d5fb452eb753a Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 29 Nov 2017 15:34:58 -0800 Subject: Tegra194: remove unused platform configs This patch cleans the makefile to remove unused platform config options. Change-Id: I96d9795c0f0ba593de96017dc9a401d7c2ab471a Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/platform_t194.mk | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 5ec1af296..35b46a800 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -8,18 +8,6 @@ ENABLE_CONSOLE_SPE := 0 $(eval $(call add_define,ENABLE_CONSOLE_SPE)) -ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 0 -$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) - -RELOCATE_TO_BL31_BASE := 1 -$(eval $(call add_define,RELOCATE_TO_BL31_BASE)) - -ENABLE_CHIP_VERIFICATION_HARNESS := 0 -$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) - -ENABLE_SMMU_DEVICE := 1 -$(eval $(call add_define,ENABLE_SMMU_DEVICE)) - RESET_TO_BL31 := 1 PROGRAMMABLE_RESET_ADDRESS := 1 -- cgit v1.2.3 From a3c2c0e96b6e8068fedb0b1479a921ca1d79c5ca Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Wed, 13 Dec 2017 06:39:15 +0800 Subject: Tegra194: config to enable/disable strict checking mode This patch adds a new configuration option to the platform makefiles that disables/enables strict checking mode. The config is enabled by default. Change-Id: I727dd0facee88d9517bf6956eaf9163eba25c8bb Signed-off-by: Steven Kao --- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 4 +++- plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 2 ++ plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 2 ++ plat/nvidia/tegra/soc/t194/plat_setup.c | 2 ++ plat/nvidia/tegra/soc/t194/platform_t194.mk | 3 +++ 5 files changed, 12 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index ba8436be4..c38099f05 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -186,6 +186,7 @@ void mce_verify_firmware_version(void) } } +#if ENABLE_STRICT_CHECKING_MODE /******************************************************************************* * Handler to enable the strict checking mode ******************************************************************************/ @@ -235,3 +236,4 @@ void mce_enable_strict_checking(void) nvg_enable_strict_checking_mode(); } } +#endif diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index 536ed57c0..d6b56871b 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -288,6 +288,7 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) return ret; } +#if ENABLE_STRICT_CHECKING_MODE /* * Enable strict checking mode * @@ -300,3 +301,4 @@ void nvg_enable_strict_checking_mode(void) nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params); } +#endif diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 9a9113ec2..e2001b18e 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -357,11 +357,13 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) */ if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { +#if ENABLE_STRICT_CHECKING_MODE /* * Enable strict checking after programming the GSC for * enabling TZSRAM and TZDRAM */ mce_enable_strict_checking(); +#endif /* Init SMMU */ tegra_smmu_init(); diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 7dde9dde5..3b582444c 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -293,9 +293,11 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void) void plat_late_platform_setup(void) { +#if ENABLE_STRICT_CHECKING_MODE /* * Enable strict checking after programming the GSC for * enabling TZSRAM and TZDRAM */ mce_enable_strict_checking(); +#endif } diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 35b46a800..f114b7e5b 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -8,6 +8,9 @@ ENABLE_CONSOLE_SPE := 0 $(eval $(call add_define,ENABLE_CONSOLE_SPE)) +ENABLE_STRICT_CHECKING_MODE := 1 +$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE)) + RESET_TO_BL31 := 1 PROGRAMMABLE_RESET_ADDRESS := 1 -- cgit v1.2.3 From de4a643876fa31e440cb4e4f15c47692907945f2 Mon Sep 17 00:00:00 2001 From: Vignesh Radhakrishnan Date: Wed, 20 Dec 2017 15:04:26 -0800 Subject: Tegra194: request CG7 before checking if SC7 is allowed Currently firmware seems to be checking if we can get into system suspend after checking if CC6 & C7 is allowed. For system suspend to be triggered, the firmware needs to request for CG7 as well. This patch fixes this anomaly. Change-Id: I39c4c50092a4288f4f3fa4b0b1d5026be50f058f Signed-off-by: Vignesh Radhakrishnan Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 1 + 1 file changed, 1 insertion(+) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index e2001b18e..352def13d 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -103,6 +103,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) uint32_t val; mce_cstate_info_t sc7_cstate_info = { .cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6, + .ccplex = (uint32_t)TEGRA_NVG_CG_CG7, .system = (uint32_t)TEGRA_NVG_SYSTEM_SC7, .system_state_force = 1U, .update_wake_mask = 1U, -- cgit v1.2.3 From 0789758a4db5f438219a01ae82178c2f451f4ea0 Mon Sep 17 00:00:00 2001 From: Vignesh Radhakrishnan Date: Mon, 11 Dec 2017 13:17:58 -0800 Subject: Tegra194: mce: support for shutdown and reboot This patch adds support for shutdown/reboot handlers to the MCE driver. ATF communicates with mce using nvg interface for shutdown & reboot. Both shutdown and reboot use the same nvg index. However, the 1st bit of the nvg data argument differentiates whether its a shutdown or reboot. Change-Id: Id2d1b0c4fec55abf69b7f8adb65ca70bfa920e73 Signed-off-by: Vignesh Radhakrishnan --- .../tegra/soc/t194/drivers/include/mce_private.h | 5 +++++ .../tegra/soc/t194/drivers/include/t194_nvg.h | 7 ++++++- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 16 ++++++++++++++++ plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 22 ++++++++++++++++++++++ 4 files changed, 49 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 226ab5bc5..9741d084f 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -7,6 +7,7 @@ #ifndef MCE_PRIVATE_H #define MCE_PRIVATE_H +#include #include /******************************************************************************* @@ -67,8 +68,12 @@ uint64_t nvg_cache_clean(void); uint64_t nvg_cache_clean_inval(void); uint64_t nvg_cache_inval_all(void); void nvg_enable_strict_checking_mode(void); +void nvg_system_shutdown(void); +void nvg_system_reboot(void); /* MCE helper functions */ void mce_enable_strict_checking(void); +void mce_system_shutdown(void); +void mce_system_reboot(void); #endif /* MCE_PRIVATE_H */ diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h index cc0da80bf..06cbb4a2e 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -128,6 +128,11 @@ typedef enum { TEGRA_NVG_SYSTEM_SC8 = 8 } tegra_nvg_system_sleep_state_t; +typedef enum { + TEGRA_NVG_SHUTDOWN = 0U, + TEGRA_NVG_REBOOT = 1U, +} tegra_nvg_shutdown_reboot_state_t; + // --------------------------------------------------------------------------- // NVG Data subformats // --------------------------------------------------------------------------- diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index c38099f05..00c671bcc 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -237,3 +237,19 @@ void mce_enable_strict_checking(void) } } #endif + +/******************************************************************************* + * Handler to power down the entire system + ******************************************************************************/ +void mce_system_shutdown(void) +{ + nvg_system_shutdown(); +} + +/******************************************************************************* + * Handler to reboot the entire system + ******************************************************************************/ +void mce_system_reboot(void) +{ + nvg_system_reboot(); +} diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index d6b56871b..a095fdd07 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -302,3 +302,25 @@ void nvg_enable_strict_checking_mode(void) nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params); } #endif + +/* + * Request a reboot + * + * NVGDATA[0]: reboot command + */ +void nvg_system_reboot(void) +{ + /* issue command for reboot */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_SHUTDOWN, TEGRA_NVG_REBOOT); +} + +/* + * Request a shutdown + * + * NVGDATA[0]: shutdown command + */ +void nvg_system_shutdown(void) +{ + /* issue command for shutdown */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_SHUTDOWN, TEGRA_NVG_SHUTDOWN); +} -- cgit v1.2.3 From 9091e789427ac1934d567196257b974ff8148176 Mon Sep 17 00:00:00 2001 From: Vignesh Radhakrishnan Date: Wed, 14 Jun 2017 09:59:27 -0700 Subject: Tegra194: implement system shutdown/reset handlers This patch implements the PSCI system shutdown and reset handlers, that in turn issue the MCE commands. Change-Id: Ia9c831674d7be615a6e336abca42f397e4455572 Signed-off-by: Vignesh Radhakrishnan --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 352def13d..462087ebd 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -452,8 +452,7 @@ int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) __dead2 void tegra_soc_prepare_system_off(void) { /* System power off */ - - /* SC8 */ + mce_system_shutdown(); wfi(); @@ -465,5 +464,8 @@ __dead2 void tegra_soc_prepare_system_off(void) int32_t tegra_soc_prepare_system_reset(void) { + /* System reboot */ + mce_system_reboot(); + return PSCI_E_SUCCESS; } -- cgit v1.2.3 From f3ec5c0cc9f950e13e18eb46c5029688e0f761b5 Mon Sep 17 00:00:00 2001 From: steven kao Date: Sat, 23 Dec 2017 17:58:58 -0800 Subject: Tegra194: update scratch registers used to read boot parameters This patch changes SCRATCH_BOOT_PARAMS_ADDR macro to use SECURE_SCRATCH_RSV81 instead of SECURE_SCRATCH_RSV44. The previous level bootloader changed this setting, so update here to keep both components in sync. Change-Id: I4e0c1b54fc69482d5513a8608d0bf616677e1bdd Signed-off-by: steven kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index e20b2c634..a98aa2da8 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -172,16 +172,16 @@ * Tegra scratch registers constants ******************************************************************************/ #define TEGRA_SCRATCH_BASE U(0x0C390000) -#define SECURE_SCRATCH_RSV44_LO U(0x1C4) -#define SECURE_SCRATCH_RSV44_HI U(0x1C8) +#define SECURE_SCRATCH_RSV81_LO U(0x2EC) +#define SECURE_SCRATCH_RSV81_HI U(0x2F0) #define SECURE_SCRATCH_RSV97 U(0x36C) #define SECURE_SCRATCH_RSV99_LO U(0x37C) #define SECURE_SCRATCH_RSV99_HI U(0x380) #define SECURE_SCRATCH_RSV109_LO U(0x3CC) #define SECURE_SCRATCH_RSV109_HI U(0x3D0) -#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV44_LO -#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV44_HI +#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV81_LO +#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV81_HI #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97 #define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO #define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI -- cgit v1.2.3 From c766adce6592352a6c22a048364e6ed688784514 Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Mon, 18 Dec 2017 23:00:05 -0800 Subject: Tegra194: memctrl: enable mc coalescer This patch enable the Memory Controller's "Coalescer" feature to improve performance of memory transactions. Change-Id: I50ba0354116284f85d9e170c293ce77e9f3fb4d8 Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/include/t194/tegra_mc_def.h | 3 +++ plat/nvidia/tegra/soc/t194/plat_memctrl.c | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h index 1433a2ea6..86ab85935 100644 --- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -530,6 +530,9 @@ #define MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB (1U << 25) #define MC_CLIENT_HOTRESET_STATUS2 0x1898U +#define MC_COALESCE_CTRL 0x2930U +#define MC_COALESCE_CTRL_COALESCER_ENABLE (1U << 31) + /******************************************************************************* * Tegra TSA Controller constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 54dbe7cdb..a59cd11ae 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -617,6 +617,9 @@ static void tegra194_memctrl_reconfig_mss_clients(void) wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL; tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2); + + reg_val = MC_COALESCE_CTRL_COALESCER_ENABLE; + tegra_mc_write_32(MC_COALESCE_CTRL, reg_val); } /******************************************************************************* -- cgit v1.2.3 From 95f68bc4980ea2404fd5b3849b83bb15c08b0a50 Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Sun, 17 Dec 2017 16:21:47 -0800 Subject: Tegra194: memctrl: fix bug in client order id reg value generation Client order id reset values are incorrectly and'ed with mc_client_order_id macro, which resulted in getting reg value as always zero. Updated mc_client_order_id macro to avoid and'ing outside the macro, to take the reg value and update specific bit field as necessary. Change-Id: I880be6e4291d7cd58cf70d7c247a4044e57edd9e Signed-off-by: Krishna Reddy --- plat/nvidia/tegra/include/t194/tegra_mc_def.h | 4 ++-- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 11 ++++------- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h index 86ab85935..55d4fd5c9 100644 --- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -27,8 +27,8 @@ #define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12) #define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (2U << 12) -#define mc_client_order_id(id, client) \ - (~MC_CLIENT_ORDER_ID_##id##_##client##_MASK | \ +#define mc_client_order_id(val, id, client) \ + ((val & ~MC_CLIENT_ORDER_ID_##id##_##client##_MASK) | \ MC_CLIENT_ORDER_ID_##id##_##client##_ORDER_ID) /******************************************************************************* diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index a59cd11ae..374797c07 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -577,17 +577,14 @@ static void tegra194_memctrl_reconfig_mss_clients(void) tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val); /* Set Order Id only for the clients having non zero order id */ - reg_val = MC_CLIENT_ORDER_ID_9_RESET_VAL & - mc_client_order_id(9, XUSB_HOSTW); + reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_9_RESET_VAL, 9, XUSB_HOSTW); tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val); - reg_val = MC_CLIENT_ORDER_ID_27_RESET_VAL & - mc_client_order_id(27, PCIE0W); + reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_27_RESET_VAL, 27, PCIE0W); tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val); - reg_val = MC_CLIENT_ORDER_ID_28_RESET_VAL & - mc_client_order_id(28, PCIE4W) & - mc_client_order_id(28, PCIE5W); + reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_28_RESET_VAL, 28, PCIE4W); + reg_val = mc_client_order_id(reg_val, 28, PCIE5W); tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val); /* Set VC Id only for the clients having different reset values */ -- cgit v1.2.3 From 221b8e578170a6af9c4e214ae8115022706c72b1 Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Fri, 22 Dec 2017 20:17:09 -0800 Subject: Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent Force memory transactions from viw and viflar/w as non-coherent from no-override. This is necessary as iso clients shouldn't use coherent path and stage-2 smmu mappings won't mark transactions as non-coherent. For native case, no-override works. But, not for virtualization case. Change-Id: I1a8fc17787c8d0f8579bdaeeb719084993e27276 Signed-off-by: Krishna Reddy --- plat/nvidia/tegra/include/t194/tegra_mc_def.h | 4 ++-- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 25 +++++++++++-------------- 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h index 55d4fd5c9..09dcce3c0 100644 --- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -53,8 +53,8 @@ #define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28) #define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28) -#define mc_hub_vc_id(id, client) \ - (~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK | \ +#define mc_hub_vc_id(val, id, client) \ + ((val & ~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK) | \ MC_HUB_PC_VC_ID_##id##_##client##_VC_ID) /******************************************************************************* diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 374797c07..57186503b 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -478,8 +478,9 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); @@ -587,23 +588,19 @@ static void tegra194_memctrl_reconfig_mss_clients(void) reg_val = mc_client_order_id(reg_val, 28, PCIE5W); tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val); - /* Set VC Id only for the clients having different reset values */ - reg_val = MC_HUB_PC_VC_ID_0_RESET_VAL & - /* - * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB, - * TSECSWR and TSECSWRB clients - */ - mc_hub_vc_id(0, APB); + /* + * Set VC Id only for the clients having different reset values like + * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB, TSECSWR and + * TSECSWRB clients + */ + reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_0_RESET_VAL, 0, APB); tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val); - reg_val = MC_HUB_PC_VC_ID_2_RESET_VAL & /* SDMMCRAB and SDMMCWAB clients */ - mc_hub_vc_id(2, SD); + reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_2_RESET_VAL, 2, SD); tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val); - reg_val = MC_HUB_PC_VC_ID_4_RESET_VAL & - /* AXIR and AXIW clients */ - mc_hub_vc_id(4, NIC); + reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_4_RESET_VAL, 4, NIC); tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val); wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; -- cgit v1.2.3 From e74c62e7b8c3a08a844882d2539ae4769d1bd424 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 27 Dec 2017 18:01:59 -0800 Subject: Tegra194: platform handler for entering CPU standby state This patch implements a handler to enter the standby state on Tegra194 platforms. On receiving a CPU_STANDBY state request, the platform handler issues TEGRA_NVG_CORE_C6 request to the MCE firmware to take the CPU into the standby state. Change-Id: I703a96ec12205853ddb3c3871b23e338e1f60687 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 39 ++++++++++++++++++++----- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 462087ebd..b7e370336 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -77,6 +77,12 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state, /* Sanity check the requested state id */ switch (state_id) { case PSTATE_ID_CORE_IDLE: + + /* Core idle request */ + req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; + req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN; + break; + case PSTATE_ID_CORE_POWERDN: /* Core powerdown request */ @@ -94,6 +100,25 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state, return ret; } +int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state) +{ + uint32_t cpu = plat_my_core_pos(); + mce_cstate_info_t cstate_info = { 0 }; + + /* Program default wake mask */ + cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; + cstate_info.update_wake_mask = 1; + mce_update_cstate_info(&cstate_info); + + /* Enter CPU idle */ + (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, + (uint64_t)TEGRA_NVG_CORE_C6, + t19x_percpu_data[cpu].wake_time, + 0U); + + return PSCI_E_SUCCESS; +} + int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) { const plat_local_state_t *pwr_domain_state; @@ -118,15 +143,13 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & TEGRA194_STATE_ID_MASK; - if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || - (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { + if ((stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { - /* Enter CPU idle/powerdown */ - val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? - (uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7; - ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val, - t19x_percpu_data[cpu].wake_time, 0); - assert(ret == 0); + /* Enter CPU powerdown */ + (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, + (uint64_t)TEGRA_NVG_CORE_C7, + t19x_percpu_data[cpu].wake_time, + 0U); } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { -- cgit v1.2.3 From 992d2fe020cc02a757bb1bab376ed5e1741f0419 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Fri, 17 Jan 2020 10:26:21 -0600 Subject: docs: Add upcoming Change Log to Table of Contents Signed-off-by: Lauren Wehrmeister Change-Id: I2a7f38eaae3a78fc3caa37833af755c15e8236ce --- docs/index.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/index.rst b/docs/index.rst index baadd42cf..5088bfd87 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -15,6 +15,7 @@ Trusted Firmware-A Documentation perf/index security_advisories/index change-log + change-log-upcoming glossary license -- cgit v1.2.3 From 641f16e75648d5cad3b21ce7c744bb7a2bc5a729 Mon Sep 17 00:00:00 2001 From: Ambroise Vincent Date: Wed, 17 Jul 2019 11:08:38 +0100 Subject: Set lld as the default linker for Clang builds The LLVM linker replaces the GNU linker as default for the link on Clang builds. It is possible to override the default linker by setting the LD build flag. The patch also updates the TF-A doc. Change-Id: Ic08552b9994d4fa8f0d4863e67a2726c1dce2e35 Signed-off-by: Ambroise Vincent Signed-off-by: Zelalem Aweke --- Makefile | 16 ++++++++++++++-- docs/getting_started/initial-build.rst | 9 +++++---- 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 42fdb7326..640b1206e 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -209,7 +209,10 @@ PP = $(CC) -E $(TF_CFLAGS_$(ARCH)) else ifneq ($(findstring clang,$(notdir $(CC))),) TF_CFLAGS_aarch32 = $(target32-directive) $(march32-directive) TF_CFLAGS_aarch64 = -target aarch64-elf $(march64-directive) -LD = $(LINKER) +LD = ld.lld +ifeq (, $(shell which $(LD))) +$(error "No $(LD) in PATH, make sure it is installed or set LD to a different linker") +endif AS = $(CC) -c -x assembler-with-cpp $(TF_CFLAGS_$(ARCH)) CPP = $(CC) -E PP = $(CC) -E @@ -317,10 +320,13 @@ endif GCC_V_OUTPUT := $(shell $(CC) -v 2>&1) +# LD = armlink ifneq ($(findstring armlink,$(notdir $(LD))),) TF_LDFLAGS += --diag_error=warning --lto_level=O1 TF_LDFLAGS += --remove --info=unused,unusedsymbols TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) + +# LD = gcc (used when GCC LTO is enabled) else ifneq ($(findstring gcc,$(notdir $(LD))),) # Pass ld options with Wl or Xlinker switches TF_LDFLAGS += -Wl,--fatal-warnings -O1 @@ -337,11 +343,17 @@ ifneq (${ERRATA_A53_843419},1) endif TF_LDFLAGS += -nostdlib TF_LDFLAGS += $(subst --,-Xlinker --,$(TF_LDFLAGS_$(ARCH))) + +# LD = gcc-ld (ld) or llvm-ld (ld.lld) or other else TF_LDFLAGS += --fatal-warnings -O1 TF_LDFLAGS += --gc-sections +# ld.lld doesn't recognize the errata flags, +# therefore don't add those in that case +ifeq ($(findstring ld.lld,$(notdir $(LD))),) TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) endif +endif DTC_FLAGS += -I dts -O dtb DTC_CPPFLAGS += -nostdinc -Iinclude -undef -x assembler-with-cpp diff --git a/docs/getting_started/initial-build.rst b/docs/getting_started/initial-build.rst index 893aba245..d4a8f0114 100644 --- a/docs/getting_started/initial-build.rst +++ b/docs/getting_started/initial-build.rst @@ -18,9 +18,10 @@ Performing an Initial Build It is possible to build TF-A using Clang or Arm Compiler 6. To do so ``CC`` needs to point to the clang or armclang binary, which will - also select the clang or armclang assembler. Be aware that the - GNU linker is used by default. In case of being needed the linker - can be overridden using the ``LD`` variable. Clang linker version 6 is + also select the clang or armclang assembler. Be aware that for Arm Compiler, + the GNU linker is used by default. However for Clang LLVM linker (LLD) + is used by default. In case of being needed the linker can be overridden + using the ``LD`` variable. LLVM linker (LLD) version 9 is known to work with TF-A. In both cases ``CROSS_COMPILE`` should be set as described above. @@ -114,4 +115,4 @@ Performing an Initial Build -------------- -*Copyright (c) 2019, Arm Limited. All rights reserved.* +*Copyright (c) 2020, Arm Limited. All rights reserved.* -- cgit v1.2.3 From b114abb609d42a5e237a35f6e27852c9aa9ab963 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Mon, 9 Sep 2019 20:13:34 +0200 Subject: Add raw NAND framework The raw NAND framework supports SLC NAND devices. It introduces a new high level interface (io_mtd) that defines operations a driver can register to the NAND framework. This interface will fill in the io_mtd device specification: - device_size - erase_size that could be used by the io_storage interface. NAND core source file integrates the standard read loop that performs NAND device read operations using a skip bad block strategy. A platform buffer must be defined in case of unaligned data. This buffer must fit to the maximum device page size defined by PLATFORM_MTD_MAX_PAGE_SIZE. The raw_nand.c source file embeds the specific NAND operations to read data. The read command is a raw page read without any ECC correction. This can be overridden by a low level driver. No generic support for write or erase command or software ECC correction. NAND ONFI detection is available and can be enabled using NAND_ONFI_DETECT=1. For non-ONFI NAND management, platform can define required information. Change-Id: Id80e9864456cf47f02b74938cf25d99261da8e82 Signed-off-by: Lionel Debieve Signed-off-by: Christophe Kerello --- drivers/io/io_mtd.c | 248 ++++++++++++++++++++++ drivers/mtd/nand/core.c | 118 +++++++++++ drivers/mtd/nand/raw_nand.c | 446 ++++++++++++++++++++++++++++++++++++++++ include/drivers/io/io_mtd.h | 59 ++++++ include/drivers/io/io_storage.h | 3 +- include/drivers/nand.h | 55 +++++ include/drivers/raw_nand.h | 187 +++++++++++++++++ 7 files changed, 1115 insertions(+), 1 deletion(-) create mode 100644 drivers/io/io_mtd.c create mode 100644 drivers/mtd/nand/core.c create mode 100644 drivers/mtd/nand/raw_nand.c create mode 100644 include/drivers/io/io_mtd.h create mode 100644 include/drivers/nand.h create mode 100644 include/drivers/raw_nand.h diff --git a/drivers/io/io_mtd.c b/drivers/io/io_mtd.c new file mode 100644 index 000000000..7575fa250 --- /dev/null +++ b/drivers/io/io_mtd.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +typedef struct { + io_mtd_dev_spec_t *dev_spec; + uintptr_t base; + unsigned long long offset; /* Offset in bytes */ + unsigned long long size; /* Size of device in bytes */ +} mtd_dev_state_t; + +io_type_t device_type_mtd(void); + +static int mtd_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int mtd_seek(io_entity_t *entity, int mode, signed long long offset); +static int mtd_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read); +static int mtd_close(io_entity_t *entity); +static int mtd_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); +static int mtd_dev_close(io_dev_info_t *dev_info); + +static const io_dev_connector_t mtd_dev_connector = { + .dev_open = mtd_dev_open +}; + +static const io_dev_funcs_t mtd_dev_funcs = { + .type = device_type_mtd, + .open = mtd_open, + .seek = mtd_seek, + .read = mtd_read, + .close = mtd_close, + .dev_close = mtd_dev_close, +}; + +static mtd_dev_state_t state_pool[MAX_IO_MTD_DEVICES]; +static io_dev_info_t dev_info_pool[MAX_IO_MTD_DEVICES]; + +io_type_t device_type_mtd(void) +{ + return IO_TYPE_MTD; +} + +/* Locate a MTD state in the pool, specified by address */ +static int find_first_mtd_state(const io_mtd_dev_spec_t *dev_spec, + unsigned int *index_out) +{ + unsigned int index; + int result = -ENOENT; + + for (index = 0U; index < MAX_IO_MTD_DEVICES; index++) { + /* dev_spec is used as identifier since it's unique */ + if (state_pool[index].dev_spec == dev_spec) { + result = 0; + *index_out = index; + break; + } + } + + return result; +} + +/* Allocate a device info from the pool */ +static int allocate_dev_info(io_dev_info_t **dev_info) +{ + unsigned int index = 0U; + int result; + + result = find_first_mtd_state(NULL, &index); + if (result != 0) { + return -ENOMEM; + } + + dev_info_pool[index].funcs = &mtd_dev_funcs; + dev_info_pool[index].info = (uintptr_t)&state_pool[index]; + *dev_info = &dev_info_pool[index]; + + return 0; +} + +/* Release a device info from the pool */ +static int free_dev_info(io_dev_info_t *dev_info) +{ + int result; + unsigned int index = 0U; + mtd_dev_state_t *state; + + state = (mtd_dev_state_t *)dev_info->info; + result = find_first_mtd_state(state->dev_spec, &index); + if (result != 0) { + return result; + } + + zeromem(state, sizeof(mtd_dev_state_t)); + zeromem(dev_info, sizeof(io_dev_info_t)); + + return 0; +} + +static int mtd_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + mtd_dev_state_t *cur; + + assert((dev_info->info != 0UL) && (entity->info == 0UL)); + + cur = (mtd_dev_state_t *)dev_info->info; + entity->info = (uintptr_t)cur; + cur->offset = 0U; + + return 0; +} + +/* Seek to a specific position using offset */ +static int mtd_seek(io_entity_t *entity, int mode, signed long long offset) +{ + mtd_dev_state_t *cur; + + assert((entity->info != (uintptr_t)NULL) && (offset >= 0)); + + cur = (mtd_dev_state_t *)entity->info; + + switch (mode) { + case IO_SEEK_SET: + if ((offset >= 0) && + ((unsigned long long)offset >= cur->size)) { + return -EINVAL; + } + + cur->offset = offset; + break; + case IO_SEEK_CUR: + if (((cur->offset + (unsigned long long)offset) >= + cur->size) || + ((cur->offset + (unsigned long long)offset) < + cur->offset)) { + return -EINVAL; + } + + cur->offset += (unsigned long long)offset; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int mtd_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *out_length) +{ + mtd_dev_state_t *cur; + io_mtd_ops_t *ops; + int ret; + + assert(entity->info != (uintptr_t)NULL); + assert((length > 0U) && (buffer != (uintptr_t)NULL)); + + cur = (mtd_dev_state_t *)entity->info; + ops = &cur->dev_spec->ops; + assert(ops->read != NULL); + + VERBOSE("Read at %llx into %lx, length %zi\n", + cur->offset, buffer, length); + if ((cur->offset + length) > cur->dev_spec->device_size) { + return -EINVAL; + } + + ret = ops->read(cur->offset, buffer, length, out_length); + if (ret < 0) { + return ret; + } + + assert(*out_length == length); + cur->offset += *out_length; + + return 0; +} + +static int mtd_close(io_entity_t *entity) +{ + entity->info = (uintptr_t)NULL; + + return 0; +} + +static int mtd_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info) +{ + mtd_dev_state_t *cur; + io_dev_info_t *info; + io_mtd_ops_t *ops; + int result; + + result = allocate_dev_info(&info); + if (result != 0) { + return -ENOENT; + } + + cur = (mtd_dev_state_t *)info->info; + cur->dev_spec = (io_mtd_dev_spec_t *)dev_spec; + *dev_info = info; + ops = &(cur->dev_spec->ops); + if (ops->init != NULL) { + result = ops->init(&cur->dev_spec->device_size, + &cur->dev_spec->erase_size); + } + + if (result == 0) { + cur->size = cur->dev_spec->device_size; + } else { + cur->size = 0ULL; + } + + return result; +} + +static int mtd_dev_close(io_dev_info_t *dev_info) +{ + return free_dev_info(dev_info); +} + +/* Exported functions */ + +/* Register the MTD driver in the IO abstraction */ +int register_io_dev_mtd(const io_dev_connector_t **dev_con) +{ + int result; + + result = io_register_device(&dev_info_pool[0]); + if (result == 0) { + *dev_con = &mtd_dev_connector; + } + + return result; +} diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c new file mode 100644 index 000000000..44b001e35 --- /dev/null +++ b/drivers/mtd/nand/core.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +/* + * Define a single nand_device used by specific NAND frameworks. + */ +static struct nand_device nand_dev; +static uint8_t scratch_buff[PLATFORM_MTD_MAX_PAGE_SIZE]; + +int nand_read(unsigned int offset, uintptr_t buffer, size_t length, + size_t *length_read) +{ + unsigned int block = offset / nand_dev.block_size; + unsigned int end_block = (offset + length - 1U) / nand_dev.block_size; + unsigned int page_start = + (offset % nand_dev.block_size) / nand_dev.page_size; + unsigned int nb_pages = nand_dev.block_size / nand_dev.page_size; + unsigned int start_offset = offset % nand_dev.page_size; + unsigned int page; + unsigned int bytes_read; + int is_bad; + int ret; + + VERBOSE("Block %u - %u, page_start %u, nb %u, length %zu, offset %u\n", + block, end_block, page_start, nb_pages, length, offset); + + *length_read = 0UL; + + if (((start_offset != 0U) || (length % nand_dev.page_size) != 0U) && + (sizeof(scratch_buff) < nand_dev.page_size)) { + return -EINVAL; + } + + while (block <= end_block) { + is_bad = nand_dev.mtd_block_is_bad(block); + if (is_bad < 0) { + return is_bad; + } + + if (is_bad == 1) { + /* Skip the block */ + uint32_t max_block = + nand_dev.size / nand_dev.block_size; + + block++; + end_block++; + if ((block < max_block) && (end_block < max_block)) { + continue; + } + + return -EIO; + } + + for (page = page_start; page < nb_pages; page++) { + if ((start_offset != 0U) || + (length < nand_dev.page_size)) { + ret = nand_dev.mtd_read_page( + &nand_dev, + (block * nb_pages) + page, + (uintptr_t)scratch_buff); + if (ret != 0) { + return ret; + } + + bytes_read = MIN((size_t)(nand_dev.page_size - + start_offset), + length); + + memcpy((uint8_t *)buffer, + scratch_buff + start_offset, + bytes_read); + + start_offset = 0U; + } else { + ret = nand_dev.mtd_read_page(&nand_dev, + (block * nb_pages) + page, + buffer); + if (ret != 0) { + return ret; + } + + bytes_read = nand_dev.page_size; + } + + length -= bytes_read; + buffer += bytes_read; + *length_read += bytes_read; + + if (length == 0U) { + break; + } + } + + page_start = 0U; + block++; + } + + return 0; +} + +struct nand_device *get_nand_device(void) +{ + return &nand_dev; +} diff --git a/drivers/mtd/nand/raw_nand.c b/drivers/mtd/nand/raw_nand.c new file mode 100644 index 000000000..48131fcb2 --- /dev/null +++ b/drivers/mtd/nand/raw_nand.c @@ -0,0 +1,446 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define ONFI_SIGNATURE_ADDR 0x20U + +/* CRC calculation */ +#define CRC_POLYNOM 0x8005U +#define CRC_INIT_VALUE 0x4F4EU + +/* Status register */ +#define NAND_STATUS_READY BIT(6) + +#define SZ_128M 0x08000000U +#define SZ_512 0x200U + +static struct rawnand_device rawnand_dev; + +#pragma weak plat_get_raw_nand_data +int plat_get_raw_nand_data(struct rawnand_device *device) +{ + return 0; +} + +static int nand_send_cmd(uint8_t cmd, unsigned int tim) +{ + struct nand_req req; + + zeromem(&req, sizeof(struct nand_req)); + req.nand = rawnand_dev.nand_dev; + req.type = NAND_REQ_CMD | cmd; + req.inst_delay = tim; + + return rawnand_dev.ops->exec(&req); +} + +static int nand_send_addr(uint8_t addr, unsigned int tim) +{ + struct nand_req req; + + zeromem(&req, sizeof(struct nand_req)); + req.nand = rawnand_dev.nand_dev; + req.type = NAND_REQ_ADDR; + req.addr = &addr; + req.inst_delay = tim; + + return rawnand_dev.ops->exec(&req); +} + +static int nand_send_wait(unsigned int delay, unsigned int tim) +{ + struct nand_req req; + + zeromem(&req, sizeof(struct nand_req)); + req.nand = rawnand_dev.nand_dev; + req.type = NAND_REQ_WAIT; + req.inst_delay = tim; + req.delay_ms = delay; + + return rawnand_dev.ops->exec(&req); +} + + +static int nand_read_data(uint8_t *data, unsigned int length, bool use_8bit) +{ + struct nand_req req; + + zeromem(&req, sizeof(struct nand_req)); + req.nand = rawnand_dev.nand_dev; + req.type = NAND_REQ_DATAIN | (use_8bit ? NAND_REQ_BUS_WIDTH_8 : 0U); + req.addr = data; + req.length = length; + + return rawnand_dev.ops->exec(&req); +} + +int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer, + unsigned int len) +{ + int ret; + uint8_t addr[2]; + unsigned int i; + + ret = nand_send_cmd(NAND_CMD_CHANGE_1ST, 0U); + if (ret != 0) { + return ret; + } + + if (rawnand_dev.nand_dev->buswidth == NAND_BUS_WIDTH_16) { + offset /= 2U; + } + + addr[0] = offset; + addr[1] = offset >> 8; + + for (i = 0; i < 2U; i++) { + ret = nand_send_addr(addr[i], 0U); + if (ret != 0) { + return ret; + } + } + + ret = nand_send_cmd(NAND_CMD_CHANGE_2ND, NAND_TCCS_MIN); + if (ret != 0) { + return ret; + } + + return nand_read_data((uint8_t *)buffer, len, false); +} + +int nand_read_page_cmd(unsigned int page, unsigned int offset, + uintptr_t buffer, unsigned int len) +{ + uint8_t addr[5]; + uint8_t i = 0U; + uint8_t j; + int ret; + + VERBOSE(">%s page %u offset %u buffer 0x%lx\n", __func__, page, offset, + buffer); + + if (rawnand_dev.nand_dev->buswidth == NAND_BUS_WIDTH_16) { + offset /= 2U; + } + + addr[i++] = offset; + addr[i++] = offset >> 8; + + addr[i++] = page; + addr[i++] = page >> 8; + if (rawnand_dev.nand_dev->size > SZ_128M) { + addr[i++] = page >> 16; + } + + ret = nand_send_cmd(NAND_CMD_READ_1ST, 0U); + if (ret != 0) { + return ret; + } + + for (j = 0U; j < i; j++) { + ret = nand_send_addr(addr[j], 0U); + if (ret != 0) { + return ret; + } + } + + ret = nand_send_cmd(NAND_CMD_READ_2ND, NAND_TWB_MAX); + if (ret != 0) { + return ret; + } + + ret = nand_send_wait(PSEC_TO_MSEC(NAND_TR_MAX), NAND_TRR_MIN); + if (ret != 0) { + return ret; + } + + if (buffer != 0U) { + ret = nand_read_data((uint8_t *)buffer, len, false); + } + + return ret; +} + +static int nand_status(uint8_t *status) +{ + int ret; + + ret = nand_send_cmd(NAND_CMD_STATUS, NAND_TWHR_MIN); + if (ret != 0) { + return ret; + } + + if (status != NULL) { + ret = nand_read_data(status, 1U, true); + } + + return ret; +} + +int nand_wait_ready(unsigned long delay) +{ + uint8_t status; + int ret; + uint64_t timeout; + + /* Wait before reading status */ + udelay(1); + + ret = nand_status(NULL); + if (ret != 0) { + return ret; + } + + timeout = timeout_init_us(delay); + while (!timeout_elapsed(timeout)) { + ret = nand_read_data(&status, 1U, true); + if (ret != 0) { + return ret; + } + + if ((status & NAND_STATUS_READY) != 0U) { + return nand_send_cmd(NAND_CMD_READ_1ST, 0U); + } + + udelay(10); + } + + return -ETIMEDOUT; +} + +#if NAND_ONFI_DETECT +static uint16_t nand_check_crc(uint16_t crc, uint8_t *data_in, + unsigned int data_len) +{ + uint32_t i; + uint32_t j; + uint32_t bit; + + for (i = 0U; i < data_len; i++) { + uint8_t cur_param = *data_in++; + + for (j = BIT(7); j != 0U; j >>= 1) { + bit = crc & BIT(15); + crc <<= 1; + + if ((cur_param & j) != 0U) { + bit ^= BIT(15); + } + + if (bit != 0U) { + crc ^= CRC_POLYNOM; + } + } + + crc &= GENMASK(15, 0); + } + + return crc; +} + +static int nand_read_id(uint8_t addr, uint8_t *id, unsigned int size) +{ + int ret; + + ret = nand_send_cmd(NAND_CMD_READID, 0U); + if (ret != 0) { + return ret; + } + + ret = nand_send_addr(addr, NAND_TWHR_MIN); + if (ret != 0) { + return ret; + } + + return nand_read_data(id, size, true); +} + +static int nand_reset(void) +{ + int ret; + + ret = nand_send_cmd(NAND_CMD_RESET, NAND_TWB_MAX); + if (ret != 0) { + return ret; + } + + return nand_send_wait(PSEC_TO_MSEC(NAND_TRST_MAX), 0U); +} + +static int nand_read_param_page(void) +{ + struct nand_param_page page; + uint8_t addr = 0U; + int ret; + + ret = nand_send_cmd(NAND_CMD_READ_PARAM_PAGE, 0U); + if (ret != 0) { + return ret; + } + + ret = nand_send_addr(addr, NAND_TWB_MAX); + if (ret != 0) { + return ret; + } + + ret = nand_send_wait(PSEC_TO_MSEC(NAND_TR_MAX), NAND_TRR_MIN); + if (ret != 0) { + return ret; + } + + ret = nand_read_data((uint8_t *)&page, sizeof(page), true); + if (ret != 0) { + return ret; + } + + if (strncmp((char *)&page.page_sig, "ONFI", 4) != 0) { + WARN("Error ONFI detection\n"); + return -EINVAL; + } + + if (nand_check_crc(CRC_INIT_VALUE, (uint8_t *)&page, 254U) != + page.crc16) { + WARN("Error reading param\n"); + return -EINVAL; + } + + if ((page.features & ONFI_FEAT_BUS_WIDTH_16) != 0U) { + rawnand_dev.nand_dev->buswidth = NAND_BUS_WIDTH_16; + } else { + rawnand_dev.nand_dev->buswidth = NAND_BUS_WIDTH_8; + } + + rawnand_dev.nand_dev->block_size = page.num_pages_per_blk * + page.bytes_per_page; + rawnand_dev.nand_dev->page_size = page.bytes_per_page; + rawnand_dev.nand_dev->size = page.num_pages_per_blk * + page.bytes_per_page * + page.num_blk_in_lun * page.num_lun; + + if (page.nb_ecc_bits != GENMASK_32(7, 0)) { + rawnand_dev.nand_dev->ecc.max_bit_corr = page.nb_ecc_bits; + rawnand_dev.nand_dev->ecc.size = SZ_512; + } + + VERBOSE("Page size %u, block_size %u, Size %llu, ecc %u, buswidth %u\n", + rawnand_dev.nand_dev->page_size, + rawnand_dev.nand_dev->block_size, rawnand_dev.nand_dev->size, + rawnand_dev.nand_dev->ecc.max_bit_corr, + rawnand_dev.nand_dev->buswidth); + + return 0; +} + +static int detect_onfi(void) +{ + int ret; + char id[4]; + + ret = nand_reset(); + if (ret != 0) { + return ret; + } + + ret = nand_read_id(ONFI_SIGNATURE_ADDR, (uint8_t *)id, sizeof(id)); + if (ret != 0) { + return ret; + } + + if (strncmp(id, "ONFI", sizeof(id)) != 0) { + WARN("NAND Non ONFI detected\n"); + return -ENODEV; + } + + return nand_read_param_page(); +} +#endif + +static int nand_mtd_block_is_bad(unsigned int block) +{ + unsigned int nbpages_per_block = rawnand_dev.nand_dev->block_size / + rawnand_dev.nand_dev->page_size; + uint8_t bbm_marker[2]; + uint8_t page; + int ret; + + for (page = 0U; page < 2U; page++) { + ret = nand_read_page_cmd(block * nbpages_per_block, + rawnand_dev.nand_dev->page_size, + (uintptr_t)bbm_marker, + sizeof(bbm_marker)); + if (ret != 0) { + return ret; + } + + if ((bbm_marker[0] != GENMASK_32(7, 0)) || + (bbm_marker[1] != GENMASK_32(7, 0))) { + WARN("Block %u is bad\n", block); + return 1; + } + } + + return 0; +} + +static int nand_mtd_read_page_raw(struct nand_device *nand, unsigned int page, + uintptr_t buffer) +{ + return nand_read_page_cmd(page, 0U, buffer, + rawnand_dev.nand_dev->page_size); +} + +void nand_raw_ctrl_init(const struct nand_ctrl_ops *ops) +{ + rawnand_dev.ops = ops; +} + +int nand_raw_init(unsigned long long *size, unsigned int *erase_size) +{ + rawnand_dev.nand_dev = get_nand_device(); + if (rawnand_dev.nand_dev == NULL) { + return -EINVAL; + } + + rawnand_dev.nand_dev->mtd_block_is_bad = nand_mtd_block_is_bad; + rawnand_dev.nand_dev->mtd_read_page = nand_mtd_read_page_raw; + rawnand_dev.nand_dev->ecc.mode = NAND_ECC_NONE; + + if ((rawnand_dev.ops->setup == NULL) || + (rawnand_dev.ops->exec == NULL)) { + return -ENODEV; + } + +#if NAND_ONFI_DETECT + if (detect_onfi() != 0) { + WARN("Detect ONFI failed\n"); + } +#endif + + if (plat_get_raw_nand_data(&rawnand_dev) != 0) { + return -EINVAL; + } + + assert((rawnand_dev.nand_dev->page_size != 0U) && + (rawnand_dev.nand_dev->block_size != 0U) && + (rawnand_dev.nand_dev->size != 0U)); + + *size = rawnand_dev.nand_dev->size; + *erase_size = rawnand_dev.nand_dev->block_size; + + rawnand_dev.ops->setup(rawnand_dev.nand_dev); + + return 0; +} diff --git a/include/drivers/io/io_mtd.h b/include/drivers/io/io_mtd.h new file mode 100644 index 000000000..1395ff601 --- /dev/null +++ b/include/drivers/io/io_mtd.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IO_MTD_H +#define IO_MTD_H + +#include +#include + +#include + +/* MTD devices ops */ +typedef struct io_mtd_ops { + /* + * Initialize MTD framework and retrieve device information. + * + * @size: [out] MTD device size in bytes. + * @erase_size: [out] MTD erase size in bytes. + * Return 0 on success, a negative error code otherwise. + */ + int (*init)(unsigned long long *size, unsigned int *erase_size); + + /* + * Execute a read memory operation. + * + * @offset: Offset in bytes to start read operation. + * @buffer: [out] Buffer to store read data. + * @length: Required length to be read in bytes. + * @out_length: [out] Length read in bytes. + * Return 0 on success, a negative error code otherwise. + */ + int (*read)(unsigned int offset, uintptr_t buffer, size_t length, + size_t *out_length); + + /* + * Execute a write memory operation. + * + * @offset: Offset in bytes to start write operation. + * @buffer: Buffer to be written in device. + * @length: Required length to be written in bytes. + * Return 0 on success, a negative error code otherwise. + */ + int (*write)(unsigned int offset, uintptr_t buffer, size_t length); +} io_mtd_ops_t; + +typedef struct io_mtd_dev_spec { + unsigned long long device_size; + unsigned int erase_size; + io_mtd_ops_t ops; +} io_mtd_dev_spec_t; + +struct io_dev_connector; + +int register_io_dev_mtd(const struct io_dev_connector **dev_con); + +#endif /* IO_MTD_H */ diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h index d40a828e1..0e6ffd619 100644 --- a/include/drivers/io/io_storage.h +++ b/include/drivers/io/io_storage.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,7 @@ typedef enum { IO_TYPE_DUMMY, IO_TYPE_FIRMWARE_IMAGE_PACKAGE, IO_TYPE_BLOCK, + IO_TYPE_MTD, IO_TYPE_MMC, IO_TYPE_STM32IMAGE, IO_TYPE_MAX diff --git a/include/drivers/nand.h b/include/drivers/nand.h new file mode 100644 index 000000000..1dbb008f9 --- /dev/null +++ b/include/drivers/nand.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_NAND_H +#define DRIVERS_NAND_H + +#include +#include + +#include + +#define PSEC_TO_MSEC(x) div_round_up((x), 1000000000ULL) + +struct ecc { + unsigned int mode; /* ECC mode NAND_ECC_MODE_{NONE|HW|ONDIE} */ + unsigned int size; /* Data byte per ECC step */ + unsigned int bytes; /* ECC bytes per step */ + unsigned int max_bit_corr; /* Max correctible bits per ECC steps */ +}; + +struct nand_device { + unsigned int block_size; + unsigned int page_size; + unsigned long long size; + unsigned int nb_planes; + unsigned int buswidth; + struct ecc ecc; + int (*mtd_block_is_bad)(unsigned int block); + int (*mtd_read_page)(struct nand_device *nand, unsigned int page, + uintptr_t buffer); +}; + +/* + * Read bytes from NAND device + * + * @offset: Byte offset to read from in device + * @buffer: [out] Bytes read from device + * @length: Number of bytes to read + * @length_read: [out] Number of bytes read from device + * Return: 0 on success, a negative errno on failure + */ +int nand_read(unsigned int offset, uintptr_t buffer, size_t length, + size_t *length_read); + +/* + * Get NAND device instance + * + * Return: NAND device instance reference + */ +struct nand_device *get_nand_device(void); + +#endif /* DRIVERS_NAND_H */ diff --git a/include/drivers/raw_nand.h b/include/drivers/raw_nand.h new file mode 100644 index 000000000..18e4b73da --- /dev/null +++ b/include/drivers/raw_nand.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_RAW_NAND_H +#define DRIVERS_RAW_NAND_H + +#include + +#include + +/* NAND ONFI default value mode 0 in picosecond */ +#define NAND_TADL_MIN 400000UL +#define NAND_TALH_MIN 20000UL +#define NAND_TALS_MIN 50000UL +#define NAND_TAR_MIN 25000UL +#define NAND_TCCS_MIN 500000UL +#define NAND_TCEA_MIN 100000UL +#define NAND_TCEH_MIN 20000UL +#define NAND_TCH_MIN 20000UL +#define NAND_TCHZ_MAX 100000UL +#define NAND_TCLH_MIN 20000UL +#define NAND_TCLR_MIN 20000UL +#define NAND_TCLS_MIN 50000UL +#define NAND_TCOH_MIN 0UL +#define NAND_TCS_MIN 70000UL +#define NAND_TDH_MIN 20000UL +#define NAND_TDS_MIN 40000UL +#define NAND_TFEAT_MAX 1000000UL +#define NAND_TIR_MIN 10000UL +#define NAND_TITC_MIN 1000000UL +#define NAND_TR_MAX 200000000UL +#define NAND_TRC_MIN 100000UL +#define NAND_TREA_MAX 40000UL +#define NAND_TREH_MIN 30000UL +#define NAND_TRHOH_MIN 0UL +#define NAND_TRHW_MIN 200000UL +#define NAND_TRHZ_MAX 200000UL +#define NAND_TRLOH_MIN 0UL +#define NAND_TRP_MIN 50000UL +#define NAND_TRR_MIN 40000UL +#define NAND_TRST_MAX 250000000000ULL +#define NAND_TWB_MAX 200000UL +#define NAND_TWC_MIN 100000UL +#define NAND_TWH_MIN 30000UL +#define NAND_TWHR_MIN 120000UL +#define NAND_TWP_MIN 50000UL +#define NAND_TWW_MIN 100000UL + +/* NAND request types */ +#define NAND_REQ_CMD 0x0000U +#define NAND_REQ_ADDR 0x1000U +#define NAND_REQ_DATAIN 0x2000U +#define NAND_REQ_DATAOUT 0x3000U +#define NAND_REQ_WAIT 0x4000U +#define NAND_REQ_MASK GENMASK(14, 12) +#define NAND_REQ_BUS_WIDTH_8 BIT(15) + +#define PARAM_PAGE_SIZE 256 + +/* NAND ONFI commands */ +#define NAND_CMD_READ_1ST 0x00U +#define NAND_CMD_CHANGE_1ST 0x05U +#define NAND_CMD_READID_SIG_ADDR 0x20U +#define NAND_CMD_READ_2ND 0x30U +#define NAND_CMD_STATUS 0x70U +#define NAND_CMD_READID 0x90U +#define NAND_CMD_CHANGE_2ND 0xE0U +#define NAND_CMD_READ_PARAM_PAGE 0xECU +#define NAND_CMD_RESET 0xFFU + +#define ONFI_REV_21 BIT(3) +#define ONFI_FEAT_BUS_WIDTH_16 BIT(0) +#define ONFI_FEAT_EXTENDED_PARAM BIT(7) + +/* NAND ECC type */ +#define NAND_ECC_NONE U(0) +#define NAND_ECC_HW U(1) +#define NAND_ECC_ONDIE U(2) + +/* NAND bus width */ +#define NAND_BUS_WIDTH_8 U(0) +#define NAND_BUS_WIDTH_16 U(1) + +struct nand_req { + struct nand_device *nand; + uint16_t type; + uint8_t *addr; + unsigned int length; + unsigned int delay_ms; + unsigned int inst_delay; +}; + +struct nand_param_page { + /* Rev information and feature block */ + uint32_t page_sig; + uint16_t rev; + uint16_t features; + uint16_t opt_cmd; + uint8_t jtg; + uint8_t train_cmd; + uint16_t ext_param_length; + uint8_t nb_param_pages; + uint8_t reserved1[17]; + /* Manufacturer information */ + uint8_t manufacturer[12]; + uint8_t model[20]; + uint8_t manufacturer_id; + uint16_t data_code; + uint8_t reserved2[13]; + /* Memory organization */ + uint32_t bytes_per_page; + uint16_t spare_per_page; + uint32_t bytes_per_partial; + uint16_t spare_per_partial; + uint32_t num_pages_per_blk; + uint32_t num_blk_in_lun; + uint8_t num_lun; + uint8_t num_addr_cycles; + uint8_t bit_per_cell; + uint16_t max_bb_per_lun; + uint16_t blk_endur; + uint8_t valid_blk_begin; + uint16_t blk_enbur_valid; + uint8_t nb_prog_page; + uint8_t partial_prog_attr; + uint8_t nb_ecc_bits; + uint8_t plane_addr; + uint8_t mplanes_ops; + uint8_t ez_nand; + uint8_t reserved3[12]; + /* Electrical parameters */ + uint8_t io_pin_cap_max; + uint16_t sdr_timing_mode; + uint16_t sdr_prog_cache_timing; + uint16_t tprog; + uint16_t tbers; + uint16_t tr; + uint16_t tccs; + uint8_t nvddr_timing_mode; + uint8_t nvddr2_timing_mode; + uint8_t nvddr_features; + uint16_t clk_input_cap_typ; + uint16_t io_pin_cap_typ; + uint16_t input_pin_cap_typ; + uint8_t input_pin_cap_max; + uint8_t drv_strength_support; + uint16_t tr_max; + uint16_t tadl; + uint16_t tr_typ; + uint8_t reserved4[6]; + /* Vendor block */ + uint16_t vendor_revision; + uint8_t vendor[88]; + uint16_t crc16; +} __packed; + +struct nand_ctrl_ops { + int (*exec)(struct nand_req *req); + void (*setup)(struct nand_device *nand); +}; + +struct rawnand_device { + struct nand_device *nand_dev; + const struct nand_ctrl_ops *ops; +}; + +int nand_raw_init(unsigned long long *size, unsigned int *erase_size); +int nand_wait_ready(unsigned long delay); +int nand_read_page_cmd(unsigned int page, unsigned int offset, + uintptr_t buffer, unsigned int len); +int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer, + unsigned int len); +void nand_raw_ctrl_init(const struct nand_ctrl_ops *ops); + +/* + * Platform can implement this to override default raw NAND instance + * configuration. + * + * @device: target raw NAND instance. + * Return 0 on success, negative value otherwise. + */ +int plat_get_raw_nand_data(struct rawnand_device *device); + +#endif /* DRIVERS_RAW_NAND_H */ -- cgit v1.2.3 From 05e6a5638b256a66c81d5427e020dbe184659304 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Tue, 24 Sep 2019 17:38:12 +0200 Subject: Add SPI-MEM framework This framework supports SPI operations using a common spi_mem_op structure: - command - addr - dummy - data The framework manages SPI bus configuration: - speed - bus width (Up to quad mode) - chip select Change-Id: Idc2736c59bfc5ac6e55429eba5d385275ea3fbde Signed-off-by: Lionel Debieve Signed-off-by: Christophe Kerello --- drivers/mtd/spi-mem/spi_mem.c | 288 ++++++++++++++++++++++++++++++++++++++++++ include/drivers/spi_mem.h | 130 +++++++++++++++++++ 2 files changed, 418 insertions(+) create mode 100644 drivers/mtd/spi-mem/spi_mem.c create mode 100644 include/drivers/spi_mem.h diff --git a/drivers/mtd/spi-mem/spi_mem.c b/drivers/mtd/spi-mem/spi_mem.c new file mode 100644 index 000000000..63ea7699b --- /dev/null +++ b/drivers/mtd/spi-mem/spi_mem.c @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include + +#define SPI_MEM_DEFAULT_SPEED_HZ 100000U + +/* + * struct spi_slave - Representation of a SPI slave. + * + * @max_hz: Maximum speed for this slave in Hertz. + * @cs: ID of the chip select connected to the slave. + * @mode: SPI mode to use for this slave (see SPI mode flags). + * @ops: Ops defined by the bus. + */ +struct spi_slave { + unsigned int max_hz; + unsigned int cs; + unsigned int mode; + const struct spi_bus_ops *ops; +}; + +static struct spi_slave spi_slave; + +static bool spi_mem_check_buswidth_req(uint8_t buswidth, bool tx) +{ + switch (buswidth) { + case 1U: + return true; + + case 2U: + if ((tx && (spi_slave.mode & (SPI_TX_DUAL | SPI_TX_QUAD)) != + 0U) || + (!tx && (spi_slave.mode & (SPI_RX_DUAL | SPI_RX_QUAD)) != + 0U)) { + return true; + } + break; + + case 4U: + if ((tx && (spi_slave.mode & SPI_TX_QUAD) != 0U) || + (!tx && (spi_slave.mode & SPI_RX_QUAD) != 0U)) { + return true; + } + break; + + default: + break; + } + + return false; +} + +static bool spi_mem_supports_op(const struct spi_mem_op *op) +{ + if (!spi_mem_check_buswidth_req(op->cmd.buswidth, true)) { + return false; + } + + if ((op->addr.nbytes != 0U) && + !spi_mem_check_buswidth_req(op->addr.buswidth, true)) { + return false; + } + + if ((op->dummy.nbytes != 0U) && + !spi_mem_check_buswidth_req(op->dummy.buswidth, true)) { + return false; + } + + if ((op->data.nbytes != 0U) && + !spi_mem_check_buswidth_req(op->data.buswidth, + op->data.dir == SPI_MEM_DATA_OUT)) { + return false; + } + + return true; +} + +static int spi_mem_set_speed_mode(void) +{ + const struct spi_bus_ops *ops = spi_slave.ops; + int ret; + + ret = ops->set_speed(spi_slave.max_hz); + if (ret != 0) { + VERBOSE("Cannot set speed (err=%d)\n", ret); + return ret; + } + + ret = ops->set_mode(spi_slave.mode); + if (ret != 0) { + VERBOSE("Cannot set mode (err=%d)\n", ret); + return ret; + } + + return 0; +} + +static int spi_mem_check_bus_ops(const struct spi_bus_ops *ops) +{ + bool error = false; + + if (ops->claim_bus == NULL) { + VERBOSE("Ops claim bus is not defined\n"); + error = true; + } + + if (ops->release_bus == NULL) { + VERBOSE("Ops release bus is not defined\n"); + error = true; + } + + if (ops->exec_op == NULL) { + VERBOSE("Ops exec op is not defined\n"); + error = true; + } + + if (ops->set_speed == NULL) { + VERBOSE("Ops set speed is not defined\n"); + error = true; + } + + if (ops->set_mode == NULL) { + VERBOSE("Ops set mode is not defined\n"); + error = true; + } + + return error ? -EINVAL : 0; +} + +/* + * spi_mem_exec_op() - Execute a memory operation. + * @op: The memory operation to execute. + * + * This function first checks that @op is supported and then tries to execute + * it. + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int spi_mem_exec_op(const struct spi_mem_op *op) +{ + const struct spi_bus_ops *ops = spi_slave.ops; + int ret; + + VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addqr:%llx len:%x\n", + __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, + op->dummy.buswidth, op->data.buswidth, + op->addr.val, op->data.nbytes); + + if (!spi_mem_supports_op(op)) { + WARN("Error in spi_mem_support\n"); + return -ENOTSUP; + } + + ret = ops->claim_bus(spi_slave.cs); + if (ret != 0) { + WARN("Error claim_bus\n"); + return ret; + } + + ret = ops->exec_op(op); + + ops->release_bus(); + + return ret; +} + +/* + * spi_mem_init_slave() - SPI slave device initialization. + * @fdt: Pointer to the device tree blob. + * @bus_node: Offset of the bus node. + * @ops: The SPI bus ops defined. + * + * This function first checks that @ops are supported and then tries to find + * a SPI slave device. + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int spi_mem_init_slave(void *fdt, int bus_node, const struct spi_bus_ops *ops) +{ + int ret; + int mode = 0; + int nchips = 0; + int bus_subnode = 0; + const fdt32_t *cuint = NULL; + + ret = spi_mem_check_bus_ops(ops); + if (ret != 0) { + return ret; + } + + fdt_for_each_subnode(bus_subnode, fdt, bus_node) { + nchips++; + } + + if (nchips != 1) { + ERROR("Only one SPI device is currently supported\n"); + return -EINVAL; + } + + fdt_for_each_subnode(bus_subnode, fdt, bus_node) { + /* Get chip select */ + cuint = fdt_getprop(fdt, bus_subnode, "reg", NULL); + if (cuint == NULL) { + ERROR("Chip select not well defined\n"); + return -EINVAL; + } + spi_slave.cs = fdt32_to_cpu(*cuint); + + /* Get max slave frequency */ + spi_slave.max_hz = SPI_MEM_DEFAULT_SPEED_HZ; + cuint = fdt_getprop(fdt, bus_subnode, + "spi-max-frequency", NULL); + if (cuint != NULL) { + spi_slave.max_hz = fdt32_to_cpu(*cuint); + } + + /* Get mode */ + if ((fdt_getprop(fdt, bus_subnode, "spi-cpol", NULL)) != NULL) { + mode |= SPI_CPOL; + } + if ((fdt_getprop(fdt, bus_subnode, "spi-cpha", NULL)) != NULL) { + mode |= SPI_CPHA; + } + if ((fdt_getprop(fdt, bus_subnode, "spi-cs-high", NULL)) != + NULL) { + mode |= SPI_CS_HIGH; + } + if ((fdt_getprop(fdt, bus_subnode, "spi-3wire", NULL)) != + NULL) { + mode |= SPI_3WIRE; + } + if ((fdt_getprop(fdt, bus_subnode, "spi-half-duplex", NULL)) != + NULL) { + mode |= SPI_PREAMBLE; + } + + /* Get dual/quad mode */ + cuint = fdt_getprop(fdt, bus_subnode, "spi-tx-bus-width", NULL); + if (cuint != NULL) { + switch (fdt32_to_cpu(*cuint)) { + case 1U: + break; + case 2U: + mode |= SPI_TX_DUAL; + break; + case 4U: + mode |= SPI_TX_QUAD; + break; + default: + WARN("spi-tx-bus-width %d not supported\n", + fdt32_to_cpu(*cuint)); + return -EINVAL; + } + } + + cuint = fdt_getprop(fdt, bus_subnode, "spi-rx-bus-width", NULL); + if (cuint != NULL) { + switch (fdt32_to_cpu(*cuint)) { + case 1U: + break; + case 2U: + mode |= SPI_RX_DUAL; + break; + case 4U: + mode |= SPI_RX_QUAD; + break; + default: + WARN("spi-rx-bus-width %d not supported\n", + fdt32_to_cpu(*cuint)); + return -EINVAL; + } + } + + spi_slave.mode = mode; + spi_slave.ops = ops; + } + + return spi_mem_set_speed_mode(); +} diff --git a/include/drivers/spi_mem.h b/include/drivers/spi_mem.h new file mode 100644 index 000000000..d1953acf4 --- /dev/null +++ b/include/drivers/spi_mem.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_SPI_MEM_H +#define DRIVERS_SPI_MEM_H + +#include +#include +#include + +#define SPI_MEM_BUSWIDTH_1_LINE 1U +#define SPI_MEM_BUSWIDTH_2_LINE 2U +#define SPI_MEM_BUSWIDTH_4_LINE 4U + +/* + * enum spi_mem_data_dir - Describes the direction of a SPI memory data + * transfer from the controller perspective. + * @SPI_MEM_DATA_IN: data coming from the SPI memory. + * @SPI_MEM_DATA_OUT: data sent to the SPI memory. + */ +enum spi_mem_data_dir { + SPI_MEM_DATA_IN, + SPI_MEM_DATA_OUT, +}; + +/* + * struct spi_mem_op - Describes a SPI memory operation. + * + * @cmd.buswidth: Number of IO lines used to transmit the command. + * @cmd.opcode: Operation opcode. + * @addr.nbytes: Number of address bytes to send. Can be zero if the operation + * does not need to send an address. + * @addr.buswidth: Number of IO lines used to transmit the address. + * @addr.val: Address value. This value is always sent MSB first on the bus. + * Note that only @addr.nbytes are taken into account in this + * address value, so users should make sure the value fits in the + * assigned number of bytes. + * @dummy.nbytes: Number of dummy bytes to send after an opcode or address. Can + * be zero if the operation does not require dummy bytes. + * @dummy.buswidth: Number of IO lines used to transmit the dummy bytes. + * @data.buswidth: Number of IO lines used to send/receive the data. + * @data.dir: Direction of the transfer. + * @data.nbytes: Number of data bytes to transfer. + * @data.buf: Input or output data buffer depending on data::dir. + */ +struct spi_mem_op { + struct { + uint8_t buswidth; + uint8_t opcode; + } cmd; + + struct { + uint8_t nbytes; + uint8_t buswidth; + uint64_t val; + } addr; + + struct { + uint8_t nbytes; + uint8_t buswidth; + } dummy; + + struct { + uint8_t buswidth; + enum spi_mem_data_dir dir; + unsigned int nbytes; + void *buf; + } data; +}; + +/* SPI mode flags */ +#define SPI_CPHA BIT(0) /* clock phase */ +#define SPI_CPOL BIT(1) /* clock polarity */ +#define SPI_CS_HIGH BIT(2) /* CS active high */ +#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */ +#define SPI_3WIRE BIT(4) /* SI/SO signals shared */ +#define SPI_PREAMBLE BIT(5) /* Skip preamble bytes */ +#define SPI_TX_DUAL BIT(6) /* transmit with 2 wires */ +#define SPI_TX_QUAD BIT(7) /* transmit with 4 wires */ +#define SPI_RX_DUAL BIT(8) /* receive with 2 wires */ +#define SPI_RX_QUAD BIT(9) /* receive with 4 wires */ + +struct spi_bus_ops { + /* + * Claim the bus and prepare it for communication. + * + * @cs: The chip select. + * Returns: 0 if the bus was claimed successfully, or a negative value + * if it wasn't. + */ + int (*claim_bus)(unsigned int cs); + + /* + * Release the SPI bus. + */ + void (*release_bus)(void); + + /* + * Set transfer speed. + * + * @hz: The transfer speed in Hertz. + * Returns: 0 on success, a negative error code otherwise. + */ + int (*set_speed)(unsigned int hz); + + /* + * Set the SPI mode/flags. + * + * @mode: Requested SPI mode (SPI_... flags). + * Returns: 0 on success, a negative error code otherwise. + */ + int (*set_mode)(unsigned int mode); + + /* + * Execute a SPI memory operation. + * + * @op: The memory operation to execute. + * Returns: 0 on success, a negative error code otherwise. + */ + int (*exec_op)(const struct spi_mem_op *op); +}; + +int spi_mem_exec_op(const struct spi_mem_op *op); +int spi_mem_init_slave(void *fdt, int bus_node, + const struct spi_bus_ops *ops); + +#endif /* DRIVERS_SPI_MEM_H */ -- cgit v1.2.3 From c3e57739043d8557ce21fbb6627a6e09fbd70e5c Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Wed, 25 Sep 2019 15:03:59 +0200 Subject: Add SPI-NAND framework This framework supports SPI-NAND and is based on the SPI-MEM framework for SPI operations. It uses a common high level access using the io_mtd. It is limited to the read functionalities. Default behavior is the basic one data line operation but it could be overridden by platform. Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b Signed-off-by: Lionel Debieve Signed-off-by: Christophe Kerello --- drivers/mtd/nand/spi_nand.c | 320 ++++++++++++++++++++++++++++++++++++++++++++ include/drivers/spi_nand.h | 49 +++++++ 2 files changed, 369 insertions(+) create mode 100644 drivers/mtd/nand/spi_nand.c create mode 100644 include/drivers/spi_nand.h diff --git a/drivers/mtd/nand/spi_nand.c b/drivers/mtd/nand/spi_nand.c new file mode 100644 index 000000000..d01a11963 --- /dev/null +++ b/drivers/mtd/nand/spi_nand.c @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define SPI_NAND_MAX_ID_LEN 4U +#define DELAY_US_400MS 400000U +#define MACRONIX_ID 0xC2U + +static struct spinand_device spinand_dev; + +#pragma weak plat_get_spi_nand_data +int plat_get_spi_nand_data(struct spinand_device *device) +{ + return 0; +} + +static int spi_nand_reg(bool read_reg, uint8_t reg, uint8_t *val, + enum spi_mem_data_dir dir) +{ + struct spi_mem_op op; + + zeromem(&op, sizeof(struct spi_mem_op)); + if (read_reg) { + op.cmd.opcode = SPI_NAND_OP_GET_FEATURE; + } else { + op.cmd.opcode = SPI_NAND_OP_SET_FEATURE; + } + + op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + op.addr.val = reg; + op.addr.nbytes = 1U; + op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + op.data.dir = dir; + op.data.nbytes = 1U; + op.data.buf = val; + + return spi_mem_exec_op(&op); +} + +static int spi_nand_read_reg(uint8_t reg, uint8_t *val) +{ + return spi_nand_reg(true, reg, val, SPI_MEM_DATA_IN); +} + +static int spi_nand_write_reg(uint8_t reg, uint8_t val) +{ + return spi_nand_reg(false, reg, &val, SPI_MEM_DATA_OUT); +} + +static int spi_nand_update_cfg(uint8_t mask, uint8_t val) +{ + int ret; + uint8_t cfg = spinand_dev.cfg_cache; + + cfg &= ~mask; + cfg |= val; + + if (cfg == spinand_dev.cfg_cache) { + return 0; + } + + ret = spi_nand_write_reg(SPI_NAND_REG_CFG, cfg); + if (ret == 0) { + spinand_dev.cfg_cache = cfg; + } + + return ret; +} + +static int spi_nand_ecc_enable(bool enable) +{ + return spi_nand_update_cfg(SPI_NAND_CFG_ECC_EN, + enable ? SPI_NAND_CFG_ECC_EN : 0U); +} + +static int spi_nand_quad_enable(uint8_t manufacturer_id) +{ + bool enable = false; + + if (manufacturer_id != MACRONIX_ID) { + return 0; + } + + if (spinand_dev.spi_read_cache_op.data.buswidth == + SPI_MEM_BUSWIDTH_4_LINE) { + enable = true; + } + + return spi_nand_update_cfg(SPI_NAND_CFG_QE, + enable ? SPI_NAND_CFG_QE : 0U); +} + +static int spi_nand_wait_ready(uint8_t *status) +{ + int ret; + uint64_t timeout = timeout_init_us(DELAY_US_400MS); + + while (!timeout_elapsed(timeout)) { + ret = spi_nand_read_reg(SPI_NAND_REG_STATUS, status); + if (ret != 0) { + return ret; + } + + VERBOSE("%s Status %x\n", __func__, *status); + if ((*status & SPI_NAND_STATUS_BUSY) == 0U) { + return 0; + } + } + + return -ETIMEDOUT; +} + +static int spi_nand_reset(void) +{ + struct spi_mem_op op; + uint8_t status; + int ret; + + zeromem(&op, sizeof(struct spi_mem_op)); + op.cmd.opcode = SPI_NAND_OP_RESET; + op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + + ret = spi_mem_exec_op(&op); + if (ret != 0) { + return ret; + } + + return spi_nand_wait_ready(&status); +} + +static int spi_nand_read_id(uint8_t *id) +{ + struct spi_mem_op op; + + zeromem(&op, sizeof(struct spi_mem_op)); + op.cmd.opcode = SPI_NAND_OP_READ_ID; + op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + op.data.dir = SPI_MEM_DATA_IN; + op.data.nbytes = SPI_NAND_MAX_ID_LEN; + op.data.buf = id; + op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + + return spi_mem_exec_op(&op); +} + +static int spi_nand_load_page(unsigned int page) +{ + struct spi_mem_op op; + uint32_t block_nb = page / spinand_dev.nand_dev->block_size; + uint32_t page_nb = page - (block_nb * spinand_dev.nand_dev->page_size); + uint32_t nbpages_per_block = spinand_dev.nand_dev->block_size / + spinand_dev.nand_dev->page_size; + uint32_t block_sh = __builtin_ctz(nbpages_per_block) + 1U; + + zeromem(&op, sizeof(struct spi_mem_op)); + op.cmd.opcode = SPI_NAND_OP_LOAD_PAGE; + op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + op.addr.val = (block_nb << block_sh) | page_nb; + op.addr.nbytes = 3U; + op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + + return spi_mem_exec_op(&op); +} + +static int spi_nand_read_from_cache(unsigned int page, unsigned int offset, + uint8_t *buffer, unsigned int len) +{ + uint32_t nbpages_per_block = spinand_dev.nand_dev->block_size / + spinand_dev.nand_dev->page_size; + uint32_t block_nb = page / nbpages_per_block; + uint32_t page_sh = __builtin_ctz(spinand_dev.nand_dev->page_size) + 1U; + + spinand_dev.spi_read_cache_op.addr.val = offset; + + if ((spinand_dev.nand_dev->nb_planes > 1U) && ((block_nb % 2U) == 1U)) { + spinand_dev.spi_read_cache_op.addr.val |= 1U << page_sh; + } + + spinand_dev.spi_read_cache_op.data.buf = buffer; + spinand_dev.spi_read_cache_op.data.nbytes = len; + + return spi_mem_exec_op(&spinand_dev.spi_read_cache_op); +} + +static int spi_nand_read_page(unsigned int page, unsigned int offset, + uint8_t *buffer, unsigned int len, + bool ecc_enabled) +{ + uint8_t status; + int ret; + + ret = spi_nand_ecc_enable(ecc_enabled); + if (ret != 0) { + return ret; + } + + ret = spi_nand_load_page(page); + if (ret != 0) { + return ret; + } + + ret = spi_nand_wait_ready(&status); + if (ret != 0) { + return ret; + } + + ret = spi_nand_read_from_cache(page, offset, buffer, len); + if (ret != 0) { + return ret; + } + + if (ecc_enabled && ((status & SPI_NAND_STATUS_ECC_UNCOR) != 0U)) { + return -EBADMSG; + } + + return 0; +} + +static int spi_nand_mtd_block_is_bad(unsigned int block) +{ + unsigned int nbpages_per_block = spinand_dev.nand_dev->block_size / + spinand_dev.nand_dev->page_size; + uint8_t bbm_marker[2]; + int ret; + + ret = spi_nand_read_page(block * nbpages_per_block, + spinand_dev.nand_dev->page_size, + bbm_marker, sizeof(bbm_marker), false); + if (ret != 0) { + return ret; + } + + if ((bbm_marker[0] != GENMASK_32(7, 0)) || + (bbm_marker[1] != GENMASK_32(7, 0))) { + WARN("Block %i is bad\n", block); + return 1; + } + + return 0; +} + +static int spi_nand_mtd_read_page(struct nand_device *nand, unsigned int page, + uintptr_t buffer) +{ + return spi_nand_read_page(page, 0, (uint8_t *)buffer, + spinand_dev.nand_dev->page_size, true); +} + +int spi_nand_init(unsigned long long *size, unsigned int *erase_size) +{ + uint8_t id[SPI_NAND_MAX_ID_LEN]; + int ret; + + spinand_dev.nand_dev = get_nand_device(); + if (spinand_dev.nand_dev == NULL) { + return -EINVAL; + } + + spinand_dev.nand_dev->mtd_block_is_bad = spi_nand_mtd_block_is_bad; + spinand_dev.nand_dev->mtd_read_page = spi_nand_mtd_read_page; + spinand_dev.nand_dev->nb_planes = 1; + + spinand_dev.spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE; + spinand_dev.spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + spinand_dev.spi_read_cache_op.addr.nbytes = 2U; + spinand_dev.spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + spinand_dev.spi_read_cache_op.dummy.nbytes = 1U; + spinand_dev.spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + spinand_dev.spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + + if (plat_get_spi_nand_data(&spinand_dev) != 0) { + return -EINVAL; + } + + ret = spi_nand_reset(); + if (ret != 0) { + return ret; + } + + ret = spi_nand_read_id(id); + if (ret != 0) { + return ret; + } + + ret = spi_nand_read_reg(SPI_NAND_REG_CFG, &spinand_dev.cfg_cache); + if (ret != 0) { + return ret; + } + + ret = spi_nand_quad_enable(id[0]); + if (ret != 0) { + return ret; + } + + VERBOSE("SPI_NAND Detected ID 0x%x 0x%x\n", id[0], id[1]); + + VERBOSE("Page size %i, Block size %i, size %lli\n", + spinand_dev.nand_dev->page_size, + spinand_dev.nand_dev->block_size, + spinand_dev.nand_dev->size); + + *size = spinand_dev.nand_dev->size; + *erase_size = spinand_dev.nand_dev->block_size; + + return 0; +} diff --git a/include/drivers/spi_nand.h b/include/drivers/spi_nand.h new file mode 100644 index 000000000..40e206375 --- /dev/null +++ b/include/drivers/spi_nand.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_SPI_NAND_H +#define DRIVERS_SPI_NAND_H + +#include +#include + +#define SPI_NAND_OP_GET_FEATURE 0x0FU +#define SPI_NAND_OP_SET_FEATURE 0x1FU +#define SPI_NAND_OP_READ_ID 0x9FU +#define SPI_NAND_OP_LOAD_PAGE 0x13U +#define SPI_NAND_OP_RESET 0xFFU +#define SPI_NAND_OP_READ_FROM_CACHE 0x03U +#define SPI_NAND_OP_READ_FROM_CACHE_2X 0x3BU +#define SPI_NAND_OP_READ_FROM_CACHE_4X 0x6BU + +/* Configuration register */ +#define SPI_NAND_REG_CFG 0xB0U +#define SPI_NAND_CFG_ECC_EN BIT(4) +#define SPI_NAND_CFG_QE BIT(0) + +/* Status register */ +#define SPI_NAND_REG_STATUS 0xC0U +#define SPI_NAND_STATUS_BUSY BIT(0) +#define SPI_NAND_STATUS_ECC_UNCOR BIT(5) + +struct spinand_device { + struct nand_device *nand_dev; + struct spi_mem_op spi_read_cache_op; + uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */ +}; + +int spi_nand_init(unsigned long long *size, unsigned int *erase_size); + +/* + * Platform can implement this to override default SPI-NAND instance + * configuration. + * + * @device: target SPI-NAND instance. + * Return 0 on success, negative value otherwise. + */ +int plat_get_spi_nand_data(struct spinand_device *device); + +#endif /* DRIVERS_SPI_NAND_H */ -- cgit v1.2.3 From a13550d0ec5d5ad5035bb7120d8ddac4a4fb2113 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Tue, 24 Sep 2019 17:39:14 +0200 Subject: Add SPI-NOR framework SPI-NOR framework is based on SPI-MEM framework using spi_mem_op execution interface. It implements read functions and allows NOR configuration up to quad mode. Default management is 1 data line but it can be overridden by platform. It also includes specific quad mode configuration for Spansion, Micron and Macronix memories. Change-Id: If49502b899b4a75f6ebc3190f6bde1013651197f Signed-off-by: Lionel Debieve Signed-off-by: Christophe Kerello --- drivers/mtd/nor/spi_nor.c | 387 ++++++++++++++++++++++++++++++++++++++++++++++ include/drivers/spi_nor.h | 58 +++++++ 2 files changed, 445 insertions(+) create mode 100644 drivers/mtd/nor/spi_nor.c create mode 100644 include/drivers/spi_nor.h diff --git a/drivers/mtd/nor/spi_nor.c b/drivers/mtd/nor/spi_nor.c new file mode 100644 index 000000000..22d3ae3d9 --- /dev/null +++ b/drivers/mtd/nor/spi_nor.c @@ -0,0 +1,387 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include +#include +#include + +#define SR_WIP BIT(0) /* Write in progress */ +#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ +#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ +#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ + +/* Defined IDs for supported memories */ +#define SPANSION_ID 0x01U +#define MACRONIX_ID 0xC2U +#define MICRON_ID 0x2CU + +#define BANK_SIZE 0x1000000U + +#define SPI_READY_TIMEOUT_US 40000U + +static struct nor_device nor_dev; + +#pragma weak plat_get_nor_data +int plat_get_nor_data(struct nor_device *device) +{ + return 0; +} + +static int spi_nor_reg(uint8_t reg, uint8_t *buf, size_t len, + enum spi_mem_data_dir dir) +{ + struct spi_mem_op op; + + zeromem(&op, sizeof(struct spi_mem_op)); + op.cmd.opcode = reg; + op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + op.data.dir = dir; + op.data.nbytes = len; + op.data.buf = buf; + + return spi_mem_exec_op(&op); +} + +static inline int spi_nor_read_id(uint8_t *id) +{ + return spi_nor_reg(SPI_NOR_OP_READ_ID, id, 1U, SPI_MEM_DATA_IN); +} + +static inline int spi_nor_read_cr(uint8_t *cr) +{ + return spi_nor_reg(SPI_NOR_OP_READ_CR, cr, 1U, SPI_MEM_DATA_IN); +} + +static inline int spi_nor_read_sr(uint8_t *sr) +{ + return spi_nor_reg(SPI_NOR_OP_READ_SR, sr, 1U, SPI_MEM_DATA_IN); +} + +static inline int spi_nor_read_fsr(uint8_t *fsr) +{ + return spi_nor_reg(SPI_NOR_OP_READ_FSR, fsr, 1U, SPI_MEM_DATA_IN); +} + +static inline int spi_nor_write_en(void) +{ + return spi_nor_reg(SPI_NOR_OP_WREN, NULL, 0U, SPI_MEM_DATA_OUT); +} + +/* + * Check if device is ready. + * + * Return 0 if ready, 1 if busy or a negative error code otherwise + */ +static int spi_nor_ready(void) +{ + uint8_t sr; + int ret; + + ret = spi_nor_read_sr(&sr); + if (ret != 0) { + return ret; + } + + if ((nor_dev.flags & SPI_NOR_USE_FSR) != 0U) { + uint8_t fsr; + + ret = spi_nor_read_fsr(&fsr); + if (ret != 0) { + return ret; + } + + return (((fsr & FSR_READY) != 0U) && ((sr & SR_WIP) == 0U)) ? + 0 : 1; + } + + return (((sr & SR_WIP) != 0U) ? 1 : 0); +} + +static int spi_nor_wait_ready(void) +{ + int ret; + uint64_t timeout = timeout_init_us(SPI_READY_TIMEOUT_US); + + while (!timeout_elapsed(timeout)) { + ret = spi_nor_ready(); + if (ret <= 0) { + return ret; + } + } + + return -ETIMEDOUT; +} + +static int spi_nor_macronix_quad_enable(void) +{ + uint8_t sr; + int ret; + + ret = spi_nor_read_sr(&sr); + if (ret != 0) { + return ret; + } + + if ((sr & SR_QUAD_EN_MX) == 0U) { + return 0; + } + + ret = spi_nor_write_en(); + if (ret != 0) { + return ret; + } + + sr |= SR_QUAD_EN_MX; + ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1, SPI_MEM_DATA_OUT); + if (ret != 0) { + return ret; + } + + ret = spi_nor_wait_ready(); + if (ret != 0) { + return ret; + } + + ret = spi_nor_read_sr(&sr); + if ((ret != 0) || ((sr & SR_QUAD_EN_MX) == 0U)) { + return -EINVAL; + } + + return 0; +} + +static int spi_nor_write_sr_cr(uint8_t *sr_cr) +{ + int ret; + + ret = spi_nor_write_en(); + if (ret != 0) { + return ret; + } + + ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2, SPI_MEM_DATA_OUT); + if (ret != 0) { + return -EINVAL; + } + + ret = spi_nor_wait_ready(); + if (ret != 0) { + return ret; + } + + return 0; +} + +static int spi_nor_quad_enable(void) +{ + uint8_t sr_cr[2]; + int ret; + + ret = spi_nor_read_cr(&sr_cr[1]); + if (ret != 0) { + return ret; + } + + if ((sr_cr[1] & CR_QUAD_EN_SPAN) != 0U) { + return 0; + } + + sr_cr[1] |= CR_QUAD_EN_SPAN; + ret = spi_nor_read_sr(&sr_cr[0]); + if (ret != 0) { + return ret; + } + + ret = spi_nor_write_sr_cr(sr_cr); + if (ret != 0) { + return ret; + } + + ret = spi_nor_read_cr(&sr_cr[1]); + if ((ret != 0) || ((sr_cr[1] & CR_QUAD_EN_SPAN) == 0U)) { + return -EINVAL; + } + + return 0; +} + +static int spi_nor_clean_bar(void) +{ + int ret; + + if (nor_dev.selected_bank == 0U) { + return 0; + } + + nor_dev.selected_bank = 0U; + + ret = spi_nor_write_en(); + if (ret != 0) { + return ret; + } + + return spi_nor_reg(nor_dev.bank_write_cmd, &nor_dev.selected_bank, + 1, SPI_MEM_DATA_OUT); +} + +static int spi_nor_write_bar(uint32_t offset) +{ + uint8_t selected_bank = offset / BANK_SIZE; + int ret; + + if (selected_bank == nor_dev.selected_bank) { + return 0; + } + + ret = spi_nor_write_en(); + if (ret != 0) { + return ret; + } + + ret = spi_nor_reg(nor_dev.bank_write_cmd, &selected_bank, + 1, SPI_MEM_DATA_OUT); + if (ret != 0) { + return ret; + } + + nor_dev.selected_bank = selected_bank; + + return 0; +} + +static int spi_nor_read_bar(void) +{ + uint8_t selected_bank = 0; + int ret; + + ret = spi_nor_reg(nor_dev.bank_read_cmd, &selected_bank, + 1, SPI_MEM_DATA_IN); + if (ret != 0) { + return ret; + } + + nor_dev.selected_bank = selected_bank; + + return 0; +} + +int spi_nor_read(unsigned int offset, uintptr_t buffer, size_t length, + size_t *length_read) +{ + size_t remain_len; + int ret; + + *length_read = 0; + nor_dev.read_op.addr.val = offset; + nor_dev.read_op.data.buf = (void *)buffer; + + VERBOSE("%s offset %i length %zu\n", __func__, offset, length); + + while (length != 0U) { + if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) { + ret = spi_nor_write_bar(nor_dev.read_op.addr.val); + if (ret != 0) { + return ret; + } + + remain_len = (BANK_SIZE * (nor_dev.selected_bank + 1)) - + nor_dev.read_op.addr.val; + nor_dev.read_op.data.nbytes = MIN(length, remain_len); + } else { + nor_dev.read_op.data.nbytes = length; + } + + ret = spi_mem_exec_op(&nor_dev.read_op); + if (ret != 0) { + spi_nor_clean_bar(); + return ret; + } + + length -= nor_dev.read_op.data.nbytes; + nor_dev.read_op.addr.val += nor_dev.read_op.data.nbytes; + nor_dev.read_op.data.buf += nor_dev.read_op.data.nbytes; + *length_read += nor_dev.read_op.data.nbytes; + } + + if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) { + ret = spi_nor_clean_bar(); + if (ret != 0) { + return ret; + } + } + + return 0; +} + +int spi_nor_init(unsigned long long *size, unsigned int *erase_size) +{ + int ret = 0; + uint8_t id; + + /* Default read command used */ + nor_dev.read_op.cmd.opcode = SPI_NOR_OP_READ; + nor_dev.read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + nor_dev.read_op.addr.nbytes = 3U; + nor_dev.read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + nor_dev.read_op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + nor_dev.read_op.data.dir = SPI_MEM_DATA_IN; + + if (plat_get_nor_data(&nor_dev) != 0) { + return -EINVAL; + } + + assert(nor_dev.size != 0); + + if (nor_dev.size > BANK_SIZE) { + nor_dev.flags |= SPI_NOR_USE_BANK; + } + + *size = nor_dev.size; + + ret = spi_nor_read_id(&id); + if (ret != 0) { + return ret; + } + + if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) { + switch (id) { + case SPANSION_ID: + nor_dev.bank_read_cmd = SPINOR_OP_BRRD; + nor_dev.bank_write_cmd = SPINOR_OP_BRWR; + break; + default: + nor_dev.bank_read_cmd = SPINOR_OP_RDEAR; + nor_dev.bank_write_cmd = SPINOR_OP_WREAR; + break; + } + } + + if (nor_dev.read_op.data.buswidth == 4U) { + switch (id) { + case MACRONIX_ID: + WARN("Enable Macronix quad support\n"); + ret = spi_nor_macronix_quad_enable(); + break; + case MICRON_ID: + break; + default: + ret = spi_nor_quad_enable(); + break; + } + } + + if ((ret == 0) && ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U)) { + ret = spi_nor_read_bar(); + } + + return ret; +} diff --git a/include/drivers/spi_nor.h b/include/drivers/spi_nor.h new file mode 100644 index 000000000..72cfe5b34 --- /dev/null +++ b/include/drivers/spi_nor.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_SPI_NOR_H +#define DRIVERS_SPI_NOR_H + +#include + +/* OPCODE */ +#define SPI_NOR_OP_WREN 0x06U /* Write enable */ +#define SPI_NOR_OP_WRSR 0x01U /* Write status register 1 byte */ +#define SPI_NOR_OP_READ_ID 0x9FU /* Read JEDEC ID */ +#define SPI_NOR_OP_READ_CR 0x35U /* Read configuration register */ +#define SPI_NOR_OP_READ_SR 0x05U /* Read status register */ +#define SPI_NOR_OP_READ_FSR 0x70U /* Read flag status register */ +#define SPINOR_OP_RDEAR 0xC8U /* Read Extended Address Register */ +#define SPINOR_OP_WREAR 0xC5U /* Write Extended Address Register */ + +/* Used for Spansion flashes only. */ +#define SPINOR_OP_BRWR 0x17U /* Bank register write */ +#define SPINOR_OP_BRRD 0x16U /* Bank register read */ + +#define SPI_NOR_OP_READ 0x03U /* Read data bytes (low frequency) */ +#define SPI_NOR_OP_READ_FAST 0x0BU /* Read data bytes (high frequency) */ +#define SPI_NOR_OP_READ_1_1_2 0x3BU /* Read data bytes (Dual Output SPI) */ +#define SPI_NOR_OP_READ_1_2_2 0xBBU /* Read data bytes (Dual I/O SPI) */ +#define SPI_NOR_OP_READ_1_1_4 0x6BU /* Read data bytes (Quad Output SPI) */ +#define SPI_NOR_OP_READ_1_4_4 0xEBU /* Read data bytes (Quad I/O SPI) */ + +/* Flags for NOR specific configuration */ +#define SPI_NOR_USE_FSR BIT(0) +#define SPI_NOR_USE_BANK BIT(1) + +struct nor_device { + struct spi_mem_op read_op; + uint32_t size; + uint32_t flags; + uint8_t selected_bank; + uint8_t bank_write_cmd; + uint8_t bank_read_cmd; +}; + +int spi_nor_read(unsigned int offset, uintptr_t buffer, size_t length, + size_t *length_read); +int spi_nor_init(unsigned long long *device_size, unsigned int *erase_size); + +/* + * Platform can implement this to override default NOR instance configuration. + * + * @device: target NOR instance. + * Return 0 on success, negative value otherwise. + */ +int plat_get_nor_data(struct nor_device *device); + +#endif /* DRIVERS_SPI_NOR_H */ -- cgit v1.2.3 From 162fc183cf439efe029a581fbde8e4f936815f6d Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Wed, 2 Oct 2019 09:52:11 +0200 Subject: compiler_rt: Import popcountdi2.c and popcountsi2.c files Imported from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). This is to get the __popcountsi2(si_int a) and __popcountdi2(di_int a) builtin which are required by a driver that uses a __builtin_popcount(). Change-Id: I8e0d97cebdd90d224690c8ce1b02e657acdddb25 Signed-off-by: Lionel Debieve --- lib/compiler-rt/builtins/popcountdi2.c | 36 ++++++++++++++++++++++++++++++++++ lib/compiler-rt/builtins/popcountsi2.c | 33 +++++++++++++++++++++++++++++++ lib/compiler-rt/compiler-rt.mk | 5 ++++- 3 files changed, 73 insertions(+), 1 deletion(-) create mode 100644 lib/compiler-rt/builtins/popcountdi2.c create mode 100644 lib/compiler-rt/builtins/popcountsi2.c diff --git a/lib/compiler-rt/builtins/popcountdi2.c b/lib/compiler-rt/builtins/popcountdi2.c new file mode 100644 index 000000000..5e8a62f07 --- /dev/null +++ b/lib/compiler-rt/builtins/popcountdi2.c @@ -0,0 +1,36 @@ +/* ===-- popcountdi2.c - Implement __popcountdi2 ----------------------------=== + * + * The LLVM Compiler Infrastructure + * + * This file is dual licensed under the MIT and the University of Illinois Open + * Source Licenses. See LICENSE.TXT for details. + * + * ===----------------------------------------------------------------------=== + * + * This file implements __popcountdi2 for the compiler_rt library. + * + * ===----------------------------------------------------------------------=== + */ + +#include "int_lib.h" + +/* Returns: count of 1 bits */ + +COMPILER_RT_ABI si_int +__popcountdi2(di_int a) +{ + du_int x2 = (du_int)a; + x2 = x2 - ((x2 >> 1) & 0x5555555555555555uLL); + /* Every 2 bits holds the sum of every pair of bits (32) */ + x2 = ((x2 >> 2) & 0x3333333333333333uLL) + (x2 & 0x3333333333333333uLL); + /* Every 4 bits holds the sum of every 4-set of bits (3 significant bits) (16) */ + x2 = (x2 + (x2 >> 4)) & 0x0F0F0F0F0F0F0F0FuLL; + /* Every 8 bits holds the sum of every 8-set of bits (4 significant bits) (8) */ + su_int x = (su_int)(x2 + (x2 >> 32)); + /* The lower 32 bits hold four 16 bit sums (5 significant bits). */ + /* Upper 32 bits are garbage */ + x = x + (x >> 16); + /* The lower 16 bits hold two 32 bit sums (6 significant bits). */ + /* Upper 16 bits are garbage */ + return (x + (x >> 8)) & 0x0000007F; /* (7 significant bits) */ +} diff --git a/lib/compiler-rt/builtins/popcountsi2.c b/lib/compiler-rt/builtins/popcountsi2.c new file mode 100644 index 000000000..44544ff49 --- /dev/null +++ b/lib/compiler-rt/builtins/popcountsi2.c @@ -0,0 +1,33 @@ +/* ===-- popcountsi2.c - Implement __popcountsi2 ---------------------------=== + * + * The LLVM Compiler Infrastructure + * + * This file is dual licensed under the MIT and the University of Illinois Open + * Source Licenses. See LICENSE.TXT for details. + * + * ===----------------------------------------------------------------------=== + * + * This file implements __popcountsi2 for the compiler_rt library. + * + * ===----------------------------------------------------------------------=== + */ + +#include "int_lib.h" + +/* Returns: count of 1 bits */ + +COMPILER_RT_ABI si_int +__popcountsi2(si_int a) +{ + su_int x = (su_int)a; + x = x - ((x >> 1) & 0x55555555); + /* Every 2 bits holds the sum of every pair of bits */ + x = ((x >> 2) & 0x33333333) + (x & 0x33333333); + /* Every 4 bits holds the sum of every 4-set of bits (3 significant bits) */ + x = (x + (x >> 4)) & 0x0F0F0F0F; + /* Every 8 bits holds the sum of every 8-set of bits (4 significant bits) */ + x = (x + (x >> 16)); + /* The lower 16 bits hold two 8 bit sums (5 significant bits).*/ + /* Upper 16 bits are garbage */ + return (x + (x >> 8)) & 0x0000003F; /* (6 significant bits) */ +} diff --git a/lib/compiler-rt/compiler-rt.mk b/lib/compiler-rt/compiler-rt.mk index 1ffc9d678..40c669f98 100644 --- a/lib/compiler-rt/compiler-rt.mk +++ b/lib/compiler-rt/compiler-rt.mk @@ -28,8 +28,11 @@ # POSSIBILITY OF SUCH DAMAGE. # +COMPILER_RT_SRCS := lib/compiler-rt/builtins/popcountdi2.c \ + lib/compiler-rt/builtins/popcountsi2.c + ifeq (${ARCH},aarch32) -COMPILER_RT_SRCS := lib/compiler-rt/builtins/arm/aeabi_ldivmod.S \ +COMPILER_RT_SRCS += lib/compiler-rt/builtins/arm/aeabi_ldivmod.S \ lib/compiler-rt/builtins/arm/aeabi_uldivmod.S \ lib/compiler-rt/builtins/ctzdi2.c \ lib/compiler-rt/builtins/divdi3.c \ -- cgit v1.2.3 From e76d9fc422698a88cee13e960154e185670861dc Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 2 Jan 2020 11:14:16 +0100 Subject: lib: utils_def: add CLAMP macro Add the standard CLAMP macro. It ensures that x is between the limits set by low and high. If low is greater than high the result is undefined. Signed-off-by: Lionel Debieve Change-Id: Ia173bb9ca51bc8d9a8ec573bbc15636a94f881f4 --- include/lib/utils_def.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 35ae33a68..23f59bdc3 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -77,6 +77,15 @@ _x > _y ? _x : _y; \ }) +#define CLAMP(x, min, max) __extension__ ({ \ + __typeof__(x) _x = (x); \ + __typeof__(min) _min = (min); \ + __typeof__(max) _max = (max); \ + (void)(&_x == &_min); \ + (void)(&_x == &_max); \ + (_x > _max ? _max : (_x < _min ? _min : _x)); \ +}) + /* * The round_up() macro rounds up a value to the given boundary in a * type-agnostic yet type-safe manner. The boundary must be a power of two. -- cgit v1.2.3 From 46554b6470350ece72578d9bc4b9fd1d7cd41258 Mon Sep 17 00:00:00 2001 From: Nicolas Le Bayon Date: Tue, 3 Sep 2019 09:52:05 +0200 Subject: stm32mp1: add compilation flags for boot devices Adds compilation flags to specify which drivers will be embedded in the generated firmware. Change-Id: Ie9decc89c3f26cf17e7148a3a4cf337fd35940f7 Signed-off-by: Nicolas Le Bayon Signed-off-by: Lionel Debieve --- plat/st/common/bl2_io_storage.c | 16 +++++++++++++--- plat/st/stm32mp1/platform.mk | 15 +++++++++++++++ 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c index 38b2a0bd7..d7f53ceec 100644 --- a/plat/st/common/bl2_io_storage.c +++ b/plat/st/common/bl2_io_storage.c @@ -30,7 +30,9 @@ static uintptr_t dummy_dev_handle; static uintptr_t dummy_dev_spec; static uintptr_t image_dev_handle; +static uintptr_t storage_dev_handle; +#if STM32MP_SDMMC || STM32MP_EMMC static io_block_spec_t gpt_block_spec = { .offset = 0, .length = 34 * MMC_BLOCK_SIZE, /* Size of GPT table */ @@ -51,8 +53,8 @@ static const io_block_dev_spec_t mmc_block_dev_spec = { .block_size = MMC_BLOCK_SIZE, }; -static uintptr_t storage_dev_handle; static const io_dev_connector_t *mmc_dev_con; +#endif /* STM32MP_SDMMC || STM32MP_EMMC */ #ifdef AARCH32_SP_OPTEE static const struct stm32image_part_info optee_header_partition_spec = { @@ -96,7 +98,7 @@ enum { IMG_IDX_NUM }; -static struct stm32image_device_info stm32image_dev_info_spec = { +static struct stm32image_device_info stm32image_dev_info_spec __unused = { .lba_size = MMC_BLOCK_SIZE, .part_info[IMG_IDX_BL33] = { .name = BL33_IMAGE_NAME, @@ -123,7 +125,7 @@ static io_block_spec_t stm32image_block_spec = { .length = 0, }; -static const io_dev_connector_t *stm32image_dev_con; +static const io_dev_connector_t *stm32image_dev_con __unused; static int open_dummy(const uintptr_t spec); static int open_image(const uintptr_t spec); @@ -169,11 +171,13 @@ static const struct plat_io_policy policies[] = { .image_spec = (uintptr_t)&bl33_partition_spec, .check = open_image }, +#if STM32MP_SDMMC || STM32MP_EMMC [GPT_IMAGE_ID] = { .dev_handle = &storage_dev_handle, .image_spec = (uintptr_t)&gpt_block_spec, .check = open_storage }, +#endif [STM32_IMAGE_ID] = { .dev_handle = &storage_dev_handle, .image_spec = (uintptr_t)&stm32image_block_spec, @@ -216,6 +220,7 @@ static void print_boot_device(boot_api_context_t *boot_context) } } +#if STM32MP_SDMMC || STM32MP_EMMC static void boot_mmc(enum mmc_device_type mmc_dev_type, uint16_t boot_interface_instance) { @@ -305,6 +310,7 @@ static void boot_mmc(enum mmc_device_type mmc_dev_type, &image_dev_handle); assert(io_result == 0); } +#endif /* STM32MP_SDMMC || STM32MP_EMMC */ void stm32mp_io_setup(void) { @@ -328,14 +334,18 @@ void stm32mp_io_setup(void) assert(io_result == 0); switch (boot_context->boot_interface_selected) { +#if STM32MP_SDMMC case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: dmbsy(); boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); break; +#endif +#if STM32MP_EMMC case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: dmbsy(); boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); break; +#endif default: ERROR("Boot interface %d not supported\n", diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index 90b3e3c1e..a14a9abbb 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -24,6 +24,19 @@ PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 1))) endif $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) +# Boot devices +STM32MP_EMMC ?= 0 +STM32MP_SDMMC ?= 0 + +ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) +$(error "No boot device driver is enabled") +endif + +$(eval $(call assert_boolean,STM32MP_EMMC)) +$(eval $(call assert_boolean,STM32MP_SDMMC)) +$(eval $(call add_define,STM32MP_EMMC)) +$(eval $(call add_define,STM32MP_SDMMC)) + PLAT_INCLUDES := -Iplat/st/common/include/ PLAT_INCLUDES += -Iplat/st/stm32mp1/include/ @@ -77,11 +90,13 @@ BL2_SOURCES += drivers/io/io_block.c \ plat/st/common/bl2_io_storage.c \ plat/st/stm32mp1/bl2_plat_setup.c +ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) BL2_SOURCES += drivers/mmc/mmc.c \ drivers/partition/gpt.c \ drivers/partition/partition.c \ drivers/st/io/io_mmc.c \ drivers/st/mmc/stm32_sdmmc2.c +endif BL2_SOURCES += drivers/st/ddr/stm32mp1_ddr.c \ drivers/st/ddr/stm32mp1_ram.c -- cgit v1.2.3 From dd85e572f1cb9159de68d4d93cfba5bf200bd76c Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Tue, 24 Sep 2019 17:41:11 +0200 Subject: stm32mp: add DT helper for reg by name Add a new entry to find register properties by name and include new assert functions to limit address cells to 1 and size cells to 1. Change-Id: Ide59a795a05fb2af36bd07fec15e5a3adf196226 Signed-off-by: Lionel Debieve --- plat/st/common/include/stm32mp_dt.h | 2 + plat/st/common/stm32mp_dt.c | 92 +++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+) diff --git a/plat/st/common/include/stm32mp_dt.h b/plat/st/common/include/stm32mp_dt.h index 74b01b3aa..a29d9148d 100644 --- a/plat/st/common/include/stm32mp_dt.h +++ b/plat/st/common/include/stm32mp_dt.h @@ -32,6 +32,8 @@ uint32_t fdt_read_uint32_default(int node, const char *prop_name, uint32_t dflt_value); int fdt_read_uint32_array(int node, const char *prop_name, uint32_t *array, uint32_t count); +int fdt_get_reg_props_by_name(int node, const char *name, uintptr_t *base, + size_t *size); int dt_set_stdout_pinctrl(void); void dt_fill_device_info(struct dt_node_info *info, int node); int dt_get_node(struct dt_node_info *info, int offset, const char *compat); diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c index 17da4904a..4fa796f0c 100644 --- a/plat/st/common/stm32mp_dt.c +++ b/plat/st/common/stm32mp_dt.c @@ -92,6 +92,46 @@ uint8_t fdt_get_status(int node) return status; } +/******************************************************************************* + * This function returns the address cells from the node parent. + * Returns: + * - #address-cells value if success. + * - invalid value if error. + * - a default value if undefined #address-cells property as per libfdt + * implementation. + ******************************************************************************/ +int fdt_get_node_parent_address_cells(int node) +{ + int parent; + + parent = fdt_parent_offset(fdt, node); + if (parent < 0) { + return -FDT_ERR_NOTFOUND; + } + + return fdt_address_cells(fdt, parent); +} + +/******************************************************************************* + * This function returns the size cells from the node parent. + * Returns: + * - #size-cells value if success. + * - invalid value if error. + * - a default value if undefined #size-cells property as per libfdt + * implementation. + ******************************************************************************/ +int fdt_get_node_parent_size_cells(int node) +{ + int parent; + + parent = fdt_parent_offset(fdt, node); + if (parent < 0) { + return -FDT_ERR_NOTFOUND; + } + + return fdt_size_cells(fdt, parent); +} + /******************************************************************************* * This function reads a value of a node property (generic use of fdt * library). @@ -145,6 +185,46 @@ int fdt_read_uint32_array(int node, const char *prop_name, uint32_t *array, return 0; } +/******************************************************************************* + * This function fills reg node info (base & size) with an index found by + * checking the reg-names node. + * Returns 0 on success and a negative FDT error code on failure. + ******************************************************************************/ +int fdt_get_reg_props_by_name(int node, const char *name, uintptr_t *base, + size_t *size) +{ + const fdt32_t *cuint; + int index, len; + + assert((fdt_get_node_parent_address_cells(node) == 1) && + (fdt_get_node_parent_size_cells(node) == 1)); + + index = fdt_stringlist_search(fdt, node, "reg-names", name); + if (index < 0) { + return index; + } + + cuint = fdt_getprop(fdt, node, "reg", &len); + if (cuint == NULL) { + return -FDT_ERR_NOTFOUND; + } + + if ((index * (int)sizeof(uint32_t)) > len) { + return -FDT_ERR_BADVALUE; + } + + cuint += index << 1; + if (base != NULL) { + *base = fdt32_to_cpu(*cuint); + } + cuint++; + if (size != NULL) { + *size = fdt32_to_cpu(*cuint); + } + + return 0; +} + /******************************************************************************* * This function gets the stdout path node. * It reads the value indicated inside the device tree. @@ -215,6 +295,8 @@ void dt_fill_device_info(struct dt_node_info *info, int node) { const fdt32_t *cuint; + assert(fdt_get_node_parent_address_cells(node) == 1); + cuint = fdt_getprop(fdt, node, "reg", NULL); if (cuint != NULL) { info->base = fdt32_to_cpu(*cuint); @@ -309,6 +391,9 @@ uintptr_t dt_get_ddrctrl_base(void) return 0; } + assert((fdt_get_node_parent_address_cells(node) == 1) && + (fdt_get_node_parent_size_cells(node) == 1)); + if (fdt_read_uint32_array(node, "reg", array, 4) < 0) { return 0; } @@ -331,6 +416,9 @@ uintptr_t dt_get_ddrphyc_base(void) return 0; } + assert((fdt_get_node_parent_address_cells(node) == 1) && + (fdt_get_node_parent_size_cells(node) == 1)); + if (fdt_read_uint32_array(node, "reg", array, 4) < 0) { return 0; } @@ -353,6 +441,8 @@ uintptr_t dt_get_pwr_base(void) return 0; } + assert(fdt_get_node_parent_address_cells(node) == 1); + cuint = fdt_getprop(fdt, node, "reg", NULL); if (cuint == NULL) { return 0; @@ -415,6 +505,8 @@ uintptr_t dt_get_syscfg_base(void) return 0; } + assert(fdt_get_node_parent_address_cells(node) == 1); + cuint = fdt_getprop(fdt, node, "reg", NULL); if (cuint == NULL) { return 0; -- cgit v1.2.3 From b8718d1f4fb294bec6f3ad02c952dc007ddd3b74 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Tue, 24 Sep 2019 17:46:37 +0200 Subject: io: stm32image: fix device_size type Device size could be more than 4GB, we must define size as unsigned long long. Change-Id: I52055cf5c1c15ff18ab9e157aa9b73c8b4fb7b63 Signed-off-by: Lionel Debieve --- include/drivers/st/io_stm32image.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drivers/st/io_stm32image.h b/include/drivers/st/io_stm32image.h index 68060558b..f9fa3630c 100644 --- a/include/drivers/st/io_stm32image.h +++ b/include/drivers/st/io_stm32image.h @@ -23,7 +23,7 @@ struct stm32image_part_info { struct stm32image_device_info { struct stm32image_part_info part_info[STM32_PART_NUM]; - uint32_t device_size; + unsigned long long device_size; uint32_t lba_size; }; -- cgit v1.2.3 From e98f594a8f250715ae8ebea323f6dc7b1e2e71ef Mon Sep 17 00:00:00 2001 From: Nicolas Le Bayon Date: Fri, 27 Sep 2019 11:05:31 +0200 Subject: stm32mp1: Reduce MAX_XLAT_TABLES to 4 For STM32MP1, the address space is 4GB, which can be first divided in 4 parts of 1GB. This LVL1 table is already mapped regardless of MAX_XLAT_TABLES. Fixing typo: Replace Ko to KB. BL2/sp_min for platform STM32MP1 requires 4 MMU translation tables: - a level2 table and a level3 table for identity mapped SYSRAM - a level2 table mapping 2MB of BootROM runtime resources - a level2 table mapping 2MB of secure DDR (case BL32 is OP-TEE) Change-Id: If80cbd4fccc7689b39dd540d6649b1313557f326 Signed-off-by: Yann Gautier Signed-off-by: Lionel Debieve --- plat/st/stm32mp1/stm32mp1_def.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index a40852bde..5ec730f4b 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -74,7 +74,7 @@ enum ddr_type { #endif /* Section used inside TF binaries */ -#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */ +#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ /* 256 Octets reserved for header */ #define STM32MP_HEADER_SIZE U(0x00000100) @@ -95,9 +95,9 @@ enum ddr_type { STM32MP_OPTEE_BASE) #else #if STACK_PROTECTOR_ENABLED -#define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */ +#define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */ #else -#define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */ +#define STM32MP_BL32_SIZE U(0x00011000) /* 68 KB for BL32 */ #endif #endif @@ -107,23 +107,23 @@ enum ddr_type { #ifdef AARCH32_SP_OPTEE #if STACK_PROTECTOR_ENABLED -#define STM32MP_BL2_SIZE U(0x00019000) /* 100 Ko for BL2 */ +#define STM32MP_BL2_SIZE U(0x00019000) /* 100 KB for BL2 */ #else -#define STM32MP_BL2_SIZE U(0x00017000) /* 92 Ko for BL2 */ +#define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */ #endif #else #if STACK_PROTECTOR_ENABLED -#define STM32MP_BL2_SIZE U(0x00018000) /* 96 Ko for BL2 */ +#define STM32MP_BL2_SIZE U(0x00018000) /* 96 KB for BL2 */ #else -#define STM32MP_BL2_SIZE U(0x00016000) /* 88 Ko for BL2 */ +#define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */ #endif #endif #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ STM32MP_BL2_SIZE) -/* BL2 and BL32/sp_min require 5 tables */ -#define MAX_XLAT_TABLES 5 +/* BL2 and BL32/sp_min require 4 tables */ +#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ /* * MAX_MMAP_REGIONS is usually: @@ -137,7 +137,7 @@ enum ddr_type { #endif /* DTB initialization value */ -#define STM32MP_DTB_SIZE U(0x00005000) /* 20Ko for DTB */ +#define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ STM32MP_DTB_SIZE) -- cgit v1.2.3 From 695f7df85299fa4f9cad1b6b1c94a9e4d81049ee Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Tue, 24 Sep 2019 17:39:49 +0200 Subject: fmc: stm32_fmc2_nand: Add FMC2 driver support Add fmc2_nand driver support. The driver implements only read interface for NAND devices. Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522 Signed-off-by: Lionel Debieve Signed-off-by: Christophe Kerello --- drivers/st/fmc/stm32_fmc2_nand.c | 877 +++++++++++++++++++++++++++++++++++ include/drivers/st/stm32_fmc2_nand.h | 12 + 2 files changed, 889 insertions(+) create mode 100644 drivers/st/fmc/stm32_fmc2_nand.c create mode 100644 include/drivers/st/stm32_fmc2_nand.h diff --git a/drivers/st/fmc/stm32_fmc2_nand.c b/drivers/st/fmc/stm32_fmc2_nand.c new file mode 100644 index 000000000..b694fff6b --- /dev/null +++ b/drivers/st/fmc/stm32_fmc2_nand.c @@ -0,0 +1,877 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* FMC2 Compatibility */ +#define DT_FMC2_COMPAT "st,stm32mp15-fmc2" +#define MAX_CS 2U + +/* FMC2 Controller Registers */ +#define FMC2_BCR1 0x00U +#define FMC2_PCR 0x80U +#define FMC2_SR 0x84U +#define FMC2_PMEM 0x88U +#define FMC2_PATT 0x8CU +#define FMC2_HECCR 0x94U +#define FMC2_BCHISR 0x254U +#define FMC2_BCHDSR0 0x27CU +#define FMC2_BCHDSR1 0x280U +#define FMC2_BCHDSR2 0x284U +#define FMC2_BCHDSR3 0x288U +#define FMC2_BCHDSR4 0x28CU + +/* FMC2_BCR1 register */ +#define FMC2_BCR1_FMC2EN BIT(31) +/* FMC2_PCR register */ +#define FMC2_PCR_PWAITEN BIT(1) +#define FMC2_PCR_PBKEN BIT(2) +#define FMC2_PCR_PWID_MASK GENMASK_32(5, 4) +#define FMC2_PCR_PWID(x) (((x) << 4) & FMC2_PCR_PWID_MASK) +#define FMC2_PCR_PWID_8 0x0U +#define FMC2_PCR_PWID_16 0x1U +#define FMC2_PCR_ECCEN BIT(6) +#define FMC2_PCR_ECCALG BIT(8) +#define FMC2_PCR_TCLR_MASK GENMASK_32(12, 9) +#define FMC2_PCR_TCLR(x) (((x) << 9) & FMC2_PCR_TCLR_MASK) +#define FMC2_PCR_TCLR_DEFAULT 0xFU +#define FMC2_PCR_TAR_MASK GENMASK_32(16, 13) +#define FMC2_PCR_TAR(x) (((x) << 13) & FMC2_PCR_TAR_MASK) +#define FMC2_PCR_TAR_DEFAULT 0xFU +#define FMC2_PCR_ECCSS_MASK GENMASK_32(19, 17) +#define FMC2_PCR_ECCSS(x) (((x) << 17) & FMC2_PCR_ECCSS_MASK) +#define FMC2_PCR_ECCSS_512 0x1U +#define FMC2_PCR_ECCSS_2048 0x3U +#define FMC2_PCR_BCHECC BIT(24) +#define FMC2_PCR_WEN BIT(25) +/* FMC2_SR register */ +#define FMC2_SR_NWRF BIT(6) +/* FMC2_PMEM register*/ +#define FMC2_PMEM_MEMSET(x) (((x) & GENMASK_32(7, 0)) << 0) +#define FMC2_PMEM_MEMWAIT(x) (((x) & GENMASK_32(7, 0)) << 8) +#define FMC2_PMEM_MEMHOLD(x) (((x) & GENMASK_32(7, 0)) << 16) +#define FMC2_PMEM_MEMHIZ(x) (((x) & GENMASK_32(7, 0)) << 24) +#define FMC2_PMEM_DEFAULT 0x0A0A0A0AU +/* FMC2_PATT register */ +#define FMC2_PATT_ATTSET(x) (((x) & GENMASK_32(7, 0)) << 0) +#define FMC2_PATT_ATTWAIT(x) (((x) & GENMASK_32(7, 0)) << 8) +#define FMC2_PATT_ATTHOLD(x) (((x) & GENMASK_32(7, 0)) << 16) +#define FMC2_PATT_ATTHIZ(x) (((x) & GENMASK_32(7, 0)) << 24) +#define FMC2_PATT_DEFAULT 0x0A0A0A0AU +/* FMC2_BCHISR register */ +#define FMC2_BCHISR_DERF BIT(1) +/* FMC2_BCHDSR0 register */ +#define FMC2_BCHDSR0_DUE BIT(0) +#define FMC2_BCHDSR0_DEF BIT(1) +#define FMC2_BCHDSR0_DEN_MASK GENMASK_32(7, 4) +#define FMC2_BCHDSR0_DEN_SHIFT 4U +/* FMC2_BCHDSR1 register */ +#define FMC2_BCHDSR1_EBP1_MASK GENMASK_32(12, 0) +#define FMC2_BCHDSR1_EBP2_MASK GENMASK_32(28, 16) +#define FMC2_BCHDSR1_EBP2_SHIFT 16U +/* FMC2_BCHDSR2 register */ +#define FMC2_BCHDSR2_EBP3_MASK GENMASK_32(12, 0) +#define FMC2_BCHDSR2_EBP4_MASK GENMASK_32(28, 16) +#define FMC2_BCHDSR2_EBP4_SHIFT 16U +/* FMC2_BCHDSR3 register */ +#define FMC2_BCHDSR3_EBP5_MASK GENMASK_32(12, 0) +#define FMC2_BCHDSR3_EBP6_MASK GENMASK_32(28, 16) +#define FMC2_BCHDSR3_EBP6_SHIFT 16U +/* FMC2_BCHDSR4 register */ +#define FMC2_BCHDSR4_EBP7_MASK GENMASK_32(12, 0) +#define FMC2_BCHDSR4_EBP8_MASK GENMASK_32(28, 16) +#define FMC2_BCHDSR4_EBP8_SHIFT 16U + +/* Timings */ +#define FMC2_THIZ 0x01U +#define FMC2_TIO 8000U +#define FMC2_TSYNC 3000U +#define FMC2_PCR_TIMING_MASK GENMASK_32(3, 0) +#define FMC2_PMEM_PATT_TIMING_MASK GENMASK_32(7, 0) + +#define FMC2_BBM_LEN 2U +#define FMC2_MAX_ECC_BYTES 14U +#define TIMEOUT_US_10_MS 10000U +#define FMC2_PSEC_PER_MSEC (1000UL * 1000UL * 1000UL) + +enum stm32_fmc2_ecc { + FMC2_ECC_HAM = 1U, + FMC2_ECC_BCH4 = 4U, + FMC2_ECC_BCH8 = 8U +}; + +struct stm32_fmc2_cs_reg { + uintptr_t data_base; + uintptr_t cmd_base; + uintptr_t addr_base; +}; + +struct stm32_fmc2_nand_timings { + uint8_t tclr; + uint8_t tar; + uint8_t thiz; + uint8_t twait; + uint8_t thold_mem; + uint8_t tset_mem; + uint8_t thold_att; + uint8_t tset_att; +}; + +struct stm32_fmc2_nfc { + uintptr_t reg_base; + struct stm32_fmc2_cs_reg cs[MAX_CS]; + unsigned long clock_id; + unsigned int reset_id; + uint8_t cs_sel; +}; + +static struct stm32_fmc2_nfc stm32_fmc2; + +static uintptr_t fmc2_base(void) +{ + return stm32_fmc2.reg_base; +} + +static void stm32_fmc2_nand_setup_timing(void) +{ + struct stm32_fmc2_nand_timings tims; + unsigned long hclk = stm32mp_clk_get_rate(stm32_fmc2.clock_id); + unsigned long hclkp = FMC2_PSEC_PER_MSEC / (hclk / 1000U); + unsigned long timing, tar, tclr, thiz, twait; + unsigned long tset_mem, tset_att, thold_mem, thold_att; + uint32_t pcr, pmem, patt; + + tar = MAX(hclkp, NAND_TAR_MIN); + timing = div_round_up(tar, hclkp) - 1U; + tims.tar = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); + + tclr = MAX(hclkp, NAND_TCLR_MIN); + timing = div_round_up(tclr, hclkp) - 1U; + tims.tclr = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); + + tims.thiz = FMC2_THIZ; + thiz = (tims.thiz + 1U) * hclkp; + + /* + * tWAIT > tRP + * tWAIT > tWP + * tWAIT > tREA + tIO + */ + twait = MAX(hclkp, NAND_TRP_MIN); + twait = MAX(twait, NAND_TWP_MIN); + twait = MAX(twait, NAND_TREA_MAX + FMC2_TIO); + timing = div_round_up(twait, hclkp); + tims.twait = CLAMP(timing, 1UL, + (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); + + /* + * tSETUP_MEM > tCS - tWAIT + * tSETUP_MEM > tALS - tWAIT + * tSETUP_MEM > tDS - (tWAIT - tHIZ) + */ + tset_mem = hclkp; + if ((twait < NAND_TCS_MIN) && (tset_mem < (NAND_TCS_MIN - twait))) { + tset_mem = NAND_TCS_MIN - twait; + } + if ((twait < NAND_TALS_MIN) && (tset_mem < (NAND_TALS_MIN - twait))) { + tset_mem = NAND_TALS_MIN - twait; + } + if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) && + (tset_mem < (NAND_TDS_MIN - (twait - thiz)))) { + tset_mem = NAND_TDS_MIN - (twait - thiz); + } + timing = div_round_up(tset_mem, hclkp); + tims.tset_mem = CLAMP(timing, 1UL, + (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); + + /* + * tHOLD_MEM > tCH + * tHOLD_MEM > tREH - tSETUP_MEM + * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) + */ + thold_mem = MAX(hclkp, NAND_TCH_MIN); + if ((tset_mem < NAND_TREH_MIN) && + (thold_mem < (NAND_TREH_MIN - tset_mem))) { + thold_mem = NAND_TREH_MIN - tset_mem; + } + if (((tset_mem + twait) < NAND_TRC_MIN) && + (thold_mem < (NAND_TRC_MIN - (tset_mem + twait)))) { + thold_mem = NAND_TRC_MIN - (tset_mem + twait); + } + if (((tset_mem + twait) < NAND_TWC_MIN) && + (thold_mem < (NAND_TWC_MIN - (tset_mem + twait)))) { + thold_mem = NAND_TWC_MIN - (tset_mem + twait); + } + timing = div_round_up(thold_mem, hclkp); + tims.thold_mem = CLAMP(timing, 1UL, + (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); + + /* + * tSETUP_ATT > tCS - tWAIT + * tSETUP_ATT > tCLS - tWAIT + * tSETUP_ATT > tALS - tWAIT + * tSETUP_ATT > tRHW - tHOLD_MEM + * tSETUP_ATT > tDS - (tWAIT - tHIZ) + */ + tset_att = hclkp; + if ((twait < NAND_TCS_MIN) && (tset_att < (NAND_TCS_MIN - twait))) { + tset_att = NAND_TCS_MIN - twait; + } + if ((twait < NAND_TCLS_MIN) && (tset_att < (NAND_TCLS_MIN - twait))) { + tset_att = NAND_TCLS_MIN - twait; + } + if ((twait < NAND_TALS_MIN) && (tset_att < (NAND_TALS_MIN - twait))) { + tset_att = NAND_TALS_MIN - twait; + } + if ((thold_mem < NAND_TRHW_MIN) && + (tset_att < (NAND_TRHW_MIN - thold_mem))) { + tset_att = NAND_TRHW_MIN - thold_mem; + } + if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) && + (tset_att < (NAND_TDS_MIN - (twait - thiz)))) { + tset_att = NAND_TDS_MIN - (twait - thiz); + } + timing = div_round_up(tset_att, hclkp); + tims.tset_att = CLAMP(timing, 1UL, + (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); + + /* + * tHOLD_ATT > tALH + * tHOLD_ATT > tCH + * tHOLD_ATT > tCLH + * tHOLD_ATT > tCOH + * tHOLD_ATT > tDH + * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM + * tHOLD_ATT > tADL - tSETUP_MEM + * tHOLD_ATT > tWH - tSETUP_MEM + * tHOLD_ATT > tWHR - tSETUP_MEM + * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT) + * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) + */ + thold_att = MAX(hclkp, NAND_TALH_MIN); + thold_att = MAX(thold_att, NAND_TCH_MIN); + thold_att = MAX(thold_att, NAND_TCLH_MIN); + thold_att = MAX(thold_att, NAND_TCOH_MIN); + thold_att = MAX(thold_att, NAND_TDH_MIN); + if (((NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC) > tset_mem) && + (thold_att < (NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem))) { + thold_att = NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem; + } + if ((tset_mem < NAND_TADL_MIN) && + (thold_att < (NAND_TADL_MIN - tset_mem))) { + thold_att = NAND_TADL_MIN - tset_mem; + } + if ((tset_mem < NAND_TWH_MIN) && + (thold_att < (NAND_TWH_MIN - tset_mem))) { + thold_att = NAND_TWH_MIN - tset_mem; + } + if ((tset_mem < NAND_TWHR_MIN) && + (thold_att < (NAND_TWHR_MIN - tset_mem))) { + thold_att = NAND_TWHR_MIN - tset_mem; + } + if (((tset_att + twait) < NAND_TRC_MIN) && + (thold_att < (NAND_TRC_MIN - (tset_att + twait)))) { + thold_att = NAND_TRC_MIN - (tset_att + twait); + } + if (((tset_att + twait) < NAND_TWC_MIN) && + (thold_att < (NAND_TWC_MIN - (tset_att + twait)))) { + thold_att = NAND_TWC_MIN - (tset_att + twait); + } + timing = div_round_up(thold_att, hclkp); + tims.thold_att = CLAMP(timing, 1UL, + (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); + + VERBOSE("NAND timings: %u - %u - %u - %u - %u - %u - %u - %u\n", + tims.tclr, tims.tar, tims.thiz, tims.twait, + tims.thold_mem, tims.tset_mem, + tims.thold_att, tims.tset_att); + + /* Set tclr/tar timings */ + pcr = mmio_read_32(fmc2_base() + FMC2_PCR); + pcr &= ~FMC2_PCR_TCLR_MASK; + pcr |= FMC2_PCR_TCLR(tims.tclr); + pcr &= ~FMC2_PCR_TAR_MASK; + pcr |= FMC2_PCR_TAR(tims.tar); + + /* Set tset/twait/thold/thiz timings in common bank */ + pmem = FMC2_PMEM_MEMSET(tims.tset_mem); + pmem |= FMC2_PMEM_MEMWAIT(tims.twait); + pmem |= FMC2_PMEM_MEMHOLD(tims.thold_mem); + pmem |= FMC2_PMEM_MEMHIZ(tims.thiz); + + /* Set tset/twait/thold/thiz timings in attribute bank */ + patt = FMC2_PATT_ATTSET(tims.tset_att); + patt |= FMC2_PATT_ATTWAIT(tims.twait); + patt |= FMC2_PATT_ATTHOLD(tims.thold_att); + patt |= FMC2_PATT_ATTHIZ(tims.thiz); + + mmio_write_32(fmc2_base() + FMC2_PCR, pcr); + mmio_write_32(fmc2_base() + FMC2_PMEM, pmem); + mmio_write_32(fmc2_base() + FMC2_PATT, patt); +} + +static void stm32_fmc2_set_buswidth_16(bool set) +{ + mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_PWID_MASK, + (set ? FMC2_PCR_PWID(FMC2_PCR_PWID_16) : 0U)); +} + +static void stm32_fmc2_set_ecc(bool enable) +{ + mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_ECCEN, + (enable ? FMC2_PCR_ECCEN : 0U)); +} + +static int stm32_fmc2_ham_correct(uint8_t *buffer, uint8_t *eccbuffer, + uint8_t *ecc) +{ + uint8_t xor_ecc_ones; + uint16_t xor_ecc_1b, xor_ecc_2b, xor_ecc_3b; + union { + uint32_t val; + uint8_t bytes[4]; + } xor_ecc; + + /* Page size--------ECC_Code Size + * 256---------------22 bits LSB (ECC_CODE & 0x003FFFFF) + * 512---------------24 bits (ECC_CODE & 0x00FFFFFF) + * 1024--------------26 bits (ECC_CODE & 0x03FFFFFF) + * 2048--------------28 bits (ECC_CODE & 0x0FFFFFFF) + * 4096--------------30 bits (ECC_CODE & 0x3FFFFFFF) + * 8192--------------32 bits (ECC_CODE & 0xFFFFFFFF) + */ + + /* For Page size 512, ECC_Code size 24 bits */ + xor_ecc_1b = ecc[0] ^ eccbuffer[0]; + xor_ecc_2b = ecc[1] ^ eccbuffer[1]; + xor_ecc_3b = ecc[2] ^ eccbuffer[2]; + + xor_ecc.val = 0L; + xor_ecc.bytes[2] = xor_ecc_3b; + xor_ecc.bytes[1] = xor_ecc_2b; + xor_ecc.bytes[0] = xor_ecc_1b; + + if (xor_ecc.val == 0U) { + return 0; /* No Error */ + } + + xor_ecc_ones = __builtin_popcount(xor_ecc.val); + if (xor_ecc_ones < 23U) { + if (xor_ecc_ones == 12U) { + uint16_t bit_address, byte_address; + + /* Correctable ERROR */ + bit_address = ((xor_ecc_1b >> 1) & BIT(0)) | + ((xor_ecc_1b >> 2) & BIT(1)) | + ((xor_ecc_1b >> 3) & BIT(2)); + + byte_address = ((xor_ecc_1b >> 7) & BIT(0)) | + ((xor_ecc_2b) & BIT(1)) | + ((xor_ecc_2b >> 1) & BIT(2)) | + ((xor_ecc_2b >> 2) & BIT(3)) | + ((xor_ecc_2b >> 3) & BIT(4)) | + ((xor_ecc_3b << 4) & BIT(5)) | + ((xor_ecc_3b << 3) & BIT(6)) | + ((xor_ecc_3b << 2) & BIT(7)) | + ((xor_ecc_3b << 1) & BIT(8)); + + /* Correct bit error in the data */ + buffer[byte_address] = + buffer[byte_address] ^ BIT(bit_address); + VERBOSE("Hamming: 1 ECC error corrected\n"); + + return 0; + } + + /* Non Correctable ERROR */ + ERROR("%s: Uncorrectable ECC Errors\n", __func__); + return -1; + } + + /* ECC ERROR */ + ERROR("%s: Hamming correction error\n", __func__); + return -1; +} + + +static int stm32_fmc2_ham_calculate(uint8_t *buffer, uint8_t *ecc) +{ + uint32_t heccr; + uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS); + + while ((mmio_read_32(fmc2_base() + FMC2_SR) & FMC2_SR_NWRF) == 0U) { + if (timeout_elapsed(timeout)) { + return -ETIMEDOUT; + } + } + + heccr = mmio_read_32(fmc2_base() + FMC2_HECCR); + + ecc[0] = heccr; + ecc[1] = heccr >> 8; + ecc[2] = heccr >> 16; + + /* Disable ECC */ + stm32_fmc2_set_ecc(false); + + return 0; +} + +static int stm32_fmc2_bch_correct(uint8_t *buffer, unsigned int eccsize) +{ + uint32_t bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4; + uint16_t pos[8]; + int i, den; + uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS); + + while ((mmio_read_32(fmc2_base() + FMC2_BCHISR) & + FMC2_BCHISR_DERF) == 0U) { + if (timeout_elapsed(timeout)) { + return -ETIMEDOUT; + } + } + + bchdsr0 = mmio_read_32(fmc2_base() + FMC2_BCHDSR0); + bchdsr1 = mmio_read_32(fmc2_base() + FMC2_BCHDSR1); + bchdsr2 = mmio_read_32(fmc2_base() + FMC2_BCHDSR2); + bchdsr3 = mmio_read_32(fmc2_base() + FMC2_BCHDSR3); + bchdsr4 = mmio_read_32(fmc2_base() + FMC2_BCHDSR4); + + /* Disable ECC */ + stm32_fmc2_set_ecc(false); + + /* No error found */ + if ((bchdsr0 & FMC2_BCHDSR0_DEF) == 0U) { + return 0; + } + + /* Too many errors detected */ + if ((bchdsr0 & FMC2_BCHDSR0_DUE) != 0U) { + return -EBADMSG; + } + + pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK; + pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT; + pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK; + pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT; + pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK; + pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT; + pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK; + pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT; + + den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT; + for (i = 0; i < den; i++) { + if (pos[i] < (eccsize * 8U)) { + uint8_t bitmask = BIT(pos[i] % 8U); + uint32_t offset = pos[i] / 8U; + + *(buffer + offset) ^= bitmask; + } + } + + return 0; +} + +static void stm32_fmc2_hwctl(struct nand_device *nand) +{ + stm32_fmc2_set_ecc(false); + + if (nand->ecc.max_bit_corr != FMC2_ECC_HAM) { + mmio_clrbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_WEN); + } + + stm32_fmc2_set_ecc(true); +} + +static int stm32_fmc2_read_page(struct nand_device *nand, + unsigned int page, uintptr_t buffer) +{ + unsigned int eccsize = nand->ecc.size; + unsigned int eccbytes = nand->ecc.bytes; + unsigned int eccsteps = nand->page_size / eccsize; + uint8_t ecc_corr[FMC2_MAX_ECC_BYTES]; + uint8_t ecc_cal[FMC2_MAX_ECC_BYTES] = {0U}; + uint8_t *p; + unsigned int i; + unsigned int s; + int ret; + + VERBOSE(">%s page %i buffer %lx\n", __func__, page, buffer); + + ret = nand_read_page_cmd(page, 0U, 0U, 0U); + if (ret != 0) { + return ret; + } + + for (s = 0U, i = nand->page_size + FMC2_BBM_LEN, p = (uint8_t *)buffer; + s < eccsteps; + s++, i += eccbytes, p += eccsize) { + stm32_fmc2_hwctl(nand); + + /* Read the NAND page sector (512 bytes) */ + ret = nand_change_read_column_cmd(s * eccsize, (uintptr_t)p, + eccsize); + if (ret != 0) { + return ret; + } + + if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) { + ret = stm32_fmc2_ham_calculate(p, ecc_cal); + if (ret != 0) { + return ret; + } + } + + /* Read the corresponding ECC bytes */ + ret = nand_change_read_column_cmd(i, (uintptr_t)ecc_corr, + eccbytes); + if (ret != 0) { + return ret; + } + + /* Correct the data */ + if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) { + ret = stm32_fmc2_ham_correct(p, ecc_corr, ecc_cal); + } else { + ret = stm32_fmc2_bch_correct(p, eccsize); + } + + if (ret != 0) { + return ret; + } + } + + return 0; +} + +static void stm32_fmc2_read_data(struct nand_device *nand, + uint8_t *buff, unsigned int length, + bool use_bus8) +{ + uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; + + if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { + stm32_fmc2_set_buswidth_16(false); + } + + if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) { + *buff = mmio_read_8(data_base); + buff += sizeof(uint8_t); + length -= sizeof(uint8_t); + } + + if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) && + (length >= sizeof(uint16_t))) { + *(uint16_t *)buff = mmio_read_16(data_base); + buff += sizeof(uint16_t); + length -= sizeof(uint16_t); + } + + /* 32bit aligned */ + while (length >= sizeof(uint32_t)) { + *(uint32_t *)buff = mmio_read_32(data_base); + buff += sizeof(uint32_t); + length -= sizeof(uint32_t); + } + + /* Read remaining bytes */ + if (length >= sizeof(uint16_t)) { + *(uint16_t *)buff = mmio_read_16(data_base); + buff += sizeof(uint16_t); + length -= sizeof(uint16_t); + } + + if (length != 0U) { + *buff = mmio_read_8(data_base); + } + + if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { + /* Reconfigure bus width to 16-bit */ + stm32_fmc2_set_buswidth_16(true); + } +} + +static void stm32_fmc2_write_data(struct nand_device *nand, + uint8_t *buff, unsigned int length, + bool use_bus8) +{ + uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; + + if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { + /* Reconfigure bus width to 8-bit */ + stm32_fmc2_set_buswidth_16(false); + } + + if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) { + mmio_write_8(data_base, *buff); + buff += sizeof(uint8_t); + length -= sizeof(uint8_t); + } + + if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) && + (length >= sizeof(uint16_t))) { + mmio_write_16(data_base, *(uint16_t *)buff); + buff += sizeof(uint16_t); + length -= sizeof(uint16_t); + } + + /* 32bits aligned */ + while (length >= sizeof(uint32_t)) { + mmio_write_32(data_base, *(uint32_t *)buff); + buff += sizeof(uint32_t); + length -= sizeof(uint32_t); + } + + /* Read remaining bytes */ + if (length >= sizeof(uint16_t)) { + mmio_write_16(data_base, *(uint16_t *)buff); + buff += sizeof(uint16_t); + length -= sizeof(uint16_t); + } + + if (length != 0U) { + mmio_write_8(data_base, *buff); + } + + if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { + /* Reconfigure bus width to 16-bit */ + stm32_fmc2_set_buswidth_16(true); + } +} + +static void stm32_fmc2_ctrl_init(void) +{ + uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR); + uint32_t bcr1 = mmio_read_32(fmc2_base() + FMC2_BCR1); + + /* Enable wait feature and NAND flash memory bank */ + pcr |= FMC2_PCR_PWAITEN; + pcr |= FMC2_PCR_PBKEN; + + /* Set buswidth to 8 bits mode for identification */ + pcr &= ~FMC2_PCR_PWID_MASK; + + /* ECC logic is disabled */ + pcr &= ~FMC2_PCR_ECCEN; + + /* Default mode */ + pcr &= ~FMC2_PCR_ECCALG; + pcr &= ~FMC2_PCR_BCHECC; + pcr &= ~FMC2_PCR_WEN; + + /* Set default ECC sector size */ + pcr &= ~FMC2_PCR_ECCSS_MASK; + pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048); + + /* Set default TCLR/TAR timings */ + pcr &= ~FMC2_PCR_TCLR_MASK; + pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT); + pcr &= ~FMC2_PCR_TAR_MASK; + pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT); + + /* Enable FMC2 controller */ + bcr1 |= FMC2_BCR1_FMC2EN; + + mmio_write_32(fmc2_base() + FMC2_BCR1, bcr1); + mmio_write_32(fmc2_base() + FMC2_PCR, pcr); + mmio_write_32(fmc2_base() + FMC2_PMEM, FMC2_PMEM_DEFAULT); + mmio_write_32(fmc2_base() + FMC2_PATT, FMC2_PATT_DEFAULT); +} + +static int stm32_fmc2_exec(struct nand_req *req) +{ + int ret = 0; + + switch (req->type & NAND_REQ_MASK) { + case NAND_REQ_CMD: + VERBOSE("Write CMD %x\n", (uint8_t)req->type); + mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].cmd_base, + (uint8_t)req->type); + break; + case NAND_REQ_ADDR: + VERBOSE("Write ADDR %x\n", *(req->addr)); + mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].addr_base, + *(req->addr)); + break; + case NAND_REQ_DATAIN: + VERBOSE("Read data\n"); + stm32_fmc2_read_data(req->nand, req->addr, req->length, + ((req->type & NAND_REQ_BUS_WIDTH_8) != + 0U)); + break; + case NAND_REQ_DATAOUT: + VERBOSE("Write data\n"); + stm32_fmc2_write_data(req->nand, req->addr, req->length, + ((req->type & NAND_REQ_BUS_WIDTH_8) != + 0U)); + break; + case NAND_REQ_WAIT: + VERBOSE("WAIT Ready\n"); + ret = nand_wait_ready(req->delay_ms); + break; + default: + ret = -EINVAL; + break; + }; + + return ret; +} + +static void stm32_fmc2_setup(struct nand_device *nand) +{ + uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR); + + /* Set buswidth */ + pcr &= ~FMC2_PCR_PWID_MASK; + if (nand->buswidth == NAND_BUS_WIDTH_16) { + pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_16); + } + + if (nand->ecc.mode == NAND_ECC_HW) { + nand->mtd_read_page = stm32_fmc2_read_page; + + pcr &= ~FMC2_PCR_ECCALG; + pcr &= ~FMC2_PCR_BCHECC; + + pcr &= ~FMC2_PCR_ECCSS_MASK; + pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512); + + switch (nand->ecc.max_bit_corr) { + case FMC2_ECC_HAM: + nand->ecc.bytes = 3; + break; + case FMC2_ECC_BCH8: + pcr |= FMC2_PCR_ECCALG; + pcr |= FMC2_PCR_BCHECC; + nand->ecc.bytes = 13; + break; + default: + /* Use FMC2 ECC BCH4 */ + pcr |= FMC2_PCR_ECCALG; + nand->ecc.bytes = 7; + break; + } + + if ((nand->buswidth & NAND_BUS_WIDTH_16) != 0) { + nand->ecc.bytes++; + } + } + + mmio_write_32(stm32_fmc2.reg_base + FMC2_PCR, pcr); +} + +static const struct nand_ctrl_ops ctrl_ops = { + .setup = stm32_fmc2_setup, + .exec = stm32_fmc2_exec +}; + +int stm32_fmc2_init(void) +{ + int fmc_node; + int fmc_subnode = 0; + int nchips = 0; + unsigned int i; + void *fdt = NULL; + const fdt32_t *cuint; + struct dt_node_info info; + + if (fdt_get_address(&fdt) == 0) { + return -FDT_ERR_NOTFOUND; + } + + fmc_node = dt_get_node(&info, -1, DT_FMC2_COMPAT); + if (fmc_node == -FDT_ERR_NOTFOUND) { + WARN("No FMC2 node found\n"); + return fmc_node; + } + + if (info.status == DT_DISABLED) { + return -FDT_ERR_NOTFOUND; + } + + stm32_fmc2.reg_base = info.base; + + if ((info.clock < 0) || (info.reset < 0)) { + return -FDT_ERR_BADVALUE; + } + + stm32_fmc2.clock_id = (unsigned long)info.clock; + stm32_fmc2.reset_id = (unsigned int)info.reset; + + cuint = fdt_getprop(fdt, fmc_node, "reg", NULL); + if (cuint == NULL) { + return -FDT_ERR_BADVALUE; + } + + cuint += 2; + + for (i = 0U; i < MAX_CS; i++) { + stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*cuint); + stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 2)); + stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 4)); + cuint += 6; + } + + /* Pinctrl initialization */ + if (dt_set_pinctrl_config(fmc_node) != 0) { + return -FDT_ERR_BADVALUE; + } + + /* Parse flash nodes */ + fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) { + nchips++; + } + + if (nchips != 1) { + WARN("Only one SLC NAND device supported\n"); + return -FDT_ERR_BADVALUE; + } + + fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) { + /* Get chip select */ + cuint = fdt_getprop(fdt, fmc_subnode, "reg", NULL); + if (cuint == NULL) { + WARN("Chip select not well defined\n"); + return -FDT_ERR_BADVALUE; + } + stm32_fmc2.cs_sel = fdt32_to_cpu(*cuint); + VERBOSE("NAND CS %i\n", stm32_fmc2.cs_sel); + } + + /* Enable Clock */ + stm32mp_clk_enable(stm32_fmc2.clock_id); + + /* Reset IP */ + stm32mp_reset_assert(stm32_fmc2.reset_id); + stm32mp_reset_deassert(stm32_fmc2.reset_id); + + /* Setup default IP registers */ + stm32_fmc2_ctrl_init(); + + /* Setup default timings */ + stm32_fmc2_nand_setup_timing(); + + /* Init NAND RAW framework */ + nand_raw_ctrl_init(&ctrl_ops); + + return 0; +} diff --git a/include/drivers/st/stm32_fmc2_nand.h b/include/drivers/st/stm32_fmc2_nand.h new file mode 100644 index 000000000..81d5b9de1 --- /dev/null +++ b/include/drivers/st/stm32_fmc2_nand.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32_FMC2_NAND_H +#define STM32_FMC2_NAND_H + +int stm32_fmc2_init(void); + +#endif /* STM32_FMC2_NAND_H */ -- cgit v1.2.3 From 12e21dfde236407b8253fcde6937f11ca44cb8b0 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Mon, 4 Nov 2019 12:28:15 +0100 Subject: stm32mp1: Add support for raw NAND boot device STM32MP1 platform is able to boot from raw NAND devices. These modifications add this support using the new raw NAND framework. Change-Id: I9e9c2b03930f98a5ac23f2b6b41945bef43e5043 Signed-off-by: Lionel Debieve --- plat/st/common/bl2_io_storage.c | 76 ++++++++++++++ plat/st/stm32mp1/include/boot_api.h | 3 + plat/st/stm32mp1/include/platform_def.h | 1 + plat/st/stm32mp1/include/stm32mp1_boot_device.h | 14 +++ plat/st/stm32mp1/platform.mk | 17 +++- plat/st/stm32mp1/stm32mp1_boot_device.c | 125 ++++++++++++++++++++++++ plat/st/stm32mp1/stm32mp1_def.h | 59 ++++++++++- 7 files changed, 290 insertions(+), 5 deletions(-) create mode 100644 plat/st/stm32mp1/include/stm32mp1_boot_device.h create mode 100644 plat/st/stm32mp1/stm32mp1_boot_device.c diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c index d7f53ceec..e2629fa5d 100644 --- a/plat/st/common/bl2_io_storage.c +++ b/plat/st/common/bl2_io_storage.c @@ -14,11 +14,14 @@ #include #include #include +#include #include #include #include +#include #include #include +#include #include #include #include @@ -56,6 +59,17 @@ static const io_block_dev_spec_t mmc_block_dev_spec = { static const io_dev_connector_t *mmc_dev_con; #endif /* STM32MP_SDMMC || STM32MP_EMMC */ +#if STM32MP_RAW_NAND +static io_mtd_dev_spec_t nand_dev_spec = { + .ops = { + .init = nand_raw_init, + .read = nand_read, + }, +}; + +static const io_dev_connector_t *nand_dev_con; +#endif + #ifdef AARCH32_SP_OPTEE static const struct stm32image_part_info optee_header_partition_spec = { .name = OPTEE_HEADER_IMAGE_NAME, @@ -209,6 +223,9 @@ static void print_boot_device(boot_api_context_t *boot_context) case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: INFO("Using EMMC\n"); break; + case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: + INFO("Using FMC NAND\n"); + break; default: ERROR("Boot interface not found\n"); panic(); @@ -312,6 +329,59 @@ static void boot_mmc(enum mmc_device_type mmc_dev_type, } #endif /* STM32MP_SDMMC || STM32MP_EMMC */ +#if STM32MP_RAW_NAND +static void boot_fmc2_nand(boot_api_context_t *boot_context) +{ + int io_result __unused; + uint8_t idx; + struct stm32image_part_info *part; + + io_result = stm32_fmc2_init(); + assert(io_result == 0); + + /* Register the IO device on this platform */ + io_result = register_io_dev_mtd(&nand_dev_con); + assert(io_result == 0); + + /* Open connections to device */ + io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, + &storage_dev_handle); + assert(io_result == 0); + + stm32image_dev_info_spec.device_size = nand_dev_spec.device_size; + + idx = IMG_IDX_BL33; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NAND_BL33_OFFSET; + part->bkp_offset = nand_dev_spec.erase_size; + +#ifdef AARCH32_SP_OPTEE + idx = IMG_IDX_OPTEE_HEADER; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NAND_TEEH_OFFSET; + part->bkp_offset = nand_dev_spec.erase_size; + + idx = IMG_IDX_OPTEE_PAGED; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NAND_TEED_OFFSET; + part->bkp_offset = nand_dev_spec.erase_size; + + idx = IMG_IDX_OPTEE_PAGER; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NAND_TEEX_OFFSET; + part->bkp_offset = nand_dev_spec.erase_size; +#endif + + io_result = register_io_dev_stm32image(&stm32image_dev_con); + assert(io_result == 0); + + io_result = io_dev_open(stm32image_dev_con, + (uintptr_t)&stm32image_dev_info_spec, + &image_dev_handle); + assert(io_result == 0); +} +#endif /* STM32MP_RAW_NAND */ + void stm32mp_io_setup(void) { int io_result __unused; @@ -346,6 +416,12 @@ void stm32mp_io_setup(void) boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); break; #endif +#if STM32MP_RAW_NAND + case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: + dmbsy(); + boot_fmc2_nand(boot_context); + break; +#endif default: ERROR("Boot interface %d not supported\n", diff --git a/plat/st/stm32mp1/include/boot_api.h b/plat/st/stm32mp1/include/boot_api.h index c80aef6dd..ba5d22fa2 100644 --- a/plat/st/stm32mp1/include/boot_api.h +++ b/plat/st/stm32mp1/include/boot_api.h @@ -33,6 +33,9 @@ /* Boot occurred on EMMC */ #define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC 0x2U +/* Boot occurred on FMC */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U + /** * @brief Possible value of boot context field 'EmmcXferStatus' */ diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h index 263e6d6e1..450a9d404 100644 --- a/plat/st/stm32mp1/include/platform_def.h +++ b/plat/st/stm32mp1/include/platform_def.h @@ -51,6 +51,7 @@ #define MAX_IO_DEVICES U(4) #define MAX_IO_HANDLES U(4) #define MAX_IO_BLOCK_DEVICES U(1) +#define MAX_IO_MTD_DEVICES U(1) /******************************************************************************* * BL2 specific defines. diff --git a/plat/st/stm32mp1/include/stm32mp1_boot_device.h b/plat/st/stm32mp1/include/stm32mp1_boot_device.h new file mode 100644 index 000000000..ae6b02beb --- /dev/null +++ b/plat/st/stm32mp1/include/stm32mp1_boot_device.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_BOOT_DEVICE_H +#define STM32MP1_BOOT_DEVICE_H + +#include + +int plat_get_raw_nand_data(struct rawnand_device *device); + +#endif /* STM32MP1_BOOT_DEVICE_H */ diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index a14a9abbb..71b39168d 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -27,15 +27,18 @@ $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) # Boot devices STM32MP_EMMC ?= 0 STM32MP_SDMMC ?= 0 +STM32MP_RAW_NAND ?= 0 -ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) +ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC} ${STM32MP_RAW_NAND}),) $(error "No boot device driver is enabled") endif $(eval $(call assert_boolean,STM32MP_EMMC)) $(eval $(call assert_boolean,STM32MP_SDMMC)) +$(eval $(call assert_boolean,STM32MP_RAW_NAND)) $(eval $(call add_define,STM32MP_EMMC)) $(eval $(call add_define,STM32MP_SDMMC)) +$(eval $(call add_define,STM32MP_RAW_NAND)) PLAT_INCLUDES := -Iplat/st/common/include/ PLAT_INCLUDES += -Iplat/st/stm32mp1/include/ @@ -83,6 +86,7 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \ BL2_SOURCES += drivers/io/io_block.c \ drivers/io/io_dummy.c \ + drivers/io/io_mtd.c \ drivers/io/io_storage.c \ drivers/st/crypto/stm32_hash.c \ drivers/st/io/io_stm32image.c \ @@ -98,6 +102,17 @@ BL2_SOURCES += drivers/mmc/mmc.c \ drivers/st/mmc/stm32_sdmmc2.c endif +ifeq (${STM32MP_RAW_NAND},1) +$(eval $(call add_define_val,NAND_ONFI_DETECT,1)) +BL2_SOURCES += drivers/mtd/nand/raw_nand.c \ + drivers/st/fmc/stm32_fmc2_nand.c +endif + +ifneq ($(filter 1,${STM32MP_RAW_NAND}),) +BL2_SOURCES += drivers/mtd/nand/core.c \ + plat/st/stm32mp1/stm32mp1_boot_device.c +endif + BL2_SOURCES += drivers/st/ddr/stm32mp1_ddr.c \ drivers/st/ddr/stm32mp1_ram.c diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c new file mode 100644 index 000000000..8b1f07f6d --- /dev/null +++ b/plat/st/stm32mp1/stm32mp1_boot_device.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +#define SZ_512 0x200U + +#if STM32MP_RAW_NAND +static int get_data_from_otp(struct nand_device *nand_dev) +{ + int result; + uint32_t nand_param; + + /* Check if NAND parameters are stored in OTP */ + result = bsec_shadow_read_otp(&nand_param, NAND_OTP); + if (result != BSEC_OK) { + ERROR("BSEC: NAND_OTP Error %i\n", result); + return -EACCES; + } + + if (nand_param == 0U) { + return 0; + } + + if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) { + goto ecc; + } + + /* NAND parameter shall be read from OTP */ + if ((nand_param & NAND_WIDTH_MASK) != 0U) { + nand_dev->buswidth = NAND_BUS_WIDTH_16; + } else { + nand_dev->buswidth = NAND_BUS_WIDTH_8; + } + + switch ((nand_param & NAND_PAGE_SIZE_MASK) >> NAND_PAGE_SIZE_SHIFT) { + case NAND_PAGE_SIZE_2K: + nand_dev->page_size = 0x800U; + break; + + case NAND_PAGE_SIZE_4K: + nand_dev->page_size = 0x1000U; + break; + + case NAND_PAGE_SIZE_8K: + nand_dev->page_size = 0x2000U; + break; + + default: + ERROR("Cannot read NAND page size\n"); + return -EINVAL; + } + + switch ((nand_param & NAND_BLOCK_SIZE_MASK) >> NAND_BLOCK_SIZE_SHIFT) { + case NAND_BLOCK_SIZE_64_PAGES: + nand_dev->block_size = 64U * nand_dev->page_size; + break; + + case NAND_BLOCK_SIZE_128_PAGES: + nand_dev->block_size = 128U * nand_dev->page_size; + break; + + case NAND_BLOCK_SIZE_256_PAGES: + nand_dev->block_size = 256U * nand_dev->page_size; + break; + + default: + ERROR("Cannot read NAND block size\n"); + return -EINVAL; + } + + nand_dev->size = ((nand_param & NAND_BLOCK_NB_MASK) >> + NAND_BLOCK_NB_SHIFT) * + NAND_BLOCK_NB_UNIT * nand_dev->block_size; + +ecc: + switch ((nand_param & NAND_ECC_BIT_NB_MASK) >> + NAND_ECC_BIT_NB_SHIFT) { + case NAND_ECC_BIT_NB_1_BITS: + nand_dev->ecc.max_bit_corr = 1U; + break; + + case NAND_ECC_BIT_NB_4_BITS: + nand_dev->ecc.max_bit_corr = 4U; + break; + + case NAND_ECC_BIT_NB_8_BITS: + nand_dev->ecc.max_bit_corr = 8U; + break; + + case NAND_ECC_ON_DIE: + nand_dev->ecc.mode = NAND_ECC_ONDIE; + break; + + default: + if (nand_dev->ecc.max_bit_corr == 0U) { + ERROR("No valid eccbit number\n"); + return -EINVAL; + } + } + + VERBOSE("OTP: Block %i Page %i Size %lli\n", nand_dev->block_size, + nand_dev->page_size, nand_dev->size); + + return 0; +} +#endif + +#if STM32MP_RAW_NAND +int plat_get_raw_nand_data(struct rawnand_device *device) +{ + device->nand_dev->ecc.mode = NAND_ECC_HW; + device->nand_dev->ecc.size = SZ_512; + + return get_data_from_otp(device->nand_dev); +} +#endif + diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 5ec730f4b..7ac9b5fe4 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #endif @@ -107,15 +108,15 @@ enum ddr_type { #ifdef AARCH32_SP_OPTEE #if STACK_PROTECTOR_ENABLED -#define STM32MP_BL2_SIZE U(0x00019000) /* 100 KB for BL2 */ +#define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */ #else -#define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */ +#define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */ #endif #else #if STACK_PROTECTOR_ENABLED -#define STM32MP_BL2_SIZE U(0x00018000) /* 96 KB for BL2 */ +#define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */ #else -#define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */ +#define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */ #endif #endif @@ -144,6 +145,19 @@ enum ddr_type { #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) +/* Define maximum page size for NAND devices */ +#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) + +/******************************************************************************* + * STM32MP1 RAW partition offset for MTD devices + ******************************************************************************/ +#define STM32MP_NAND_BL33_OFFSET U(0x00200000) +#ifdef AARCH32_SP_OPTEE +#define STM32MP_NAND_TEEH_OFFSET U(0x00600000) +#define STM32MP_NAND_TEED_OFFSET U(0x00680000) +#define STM32MP_NAND_TEEX_OFFSET U(0x00700000) +#endif + /******************************************************************************* * STM32MP1 device/io map related constants (used for MMU) ******************************************************************************/ @@ -266,6 +280,7 @@ enum ddr_type { /* OTP offsets */ #define DATA0_OTP U(0) #define PART_NUMBER_OTP U(1) +#define NAND_OTP U(9) #define PACKAGE_OTP U(16) #define HW2_OTP U(18) @@ -289,6 +304,42 @@ enum ddr_type { /* HW2 OTP */ #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) +/* NAND OTP */ +/* NAND parameter storage flag */ +#define NAND_PARAM_STORED_IN_OTP BIT(31) + +/* NAND page size in bytes */ +#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) +#define NAND_PAGE_SIZE_SHIFT 29 +#define NAND_PAGE_SIZE_2K U(0) +#define NAND_PAGE_SIZE_4K U(1) +#define NAND_PAGE_SIZE_8K U(2) + +/* NAND block size in pages */ +#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) +#define NAND_BLOCK_SIZE_SHIFT 27 +#define NAND_BLOCK_SIZE_64_PAGES U(0) +#define NAND_BLOCK_SIZE_128_PAGES U(1) +#define NAND_BLOCK_SIZE_256_PAGES U(2) + +/* NAND number of block (in unit of 256 blocs) */ +#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) +#define NAND_BLOCK_NB_SHIFT 19 +#define NAND_BLOCK_NB_UNIT U(256) + +/* NAND bus width in bits */ +#define NAND_WIDTH_MASK BIT(18) +#define NAND_WIDTH_SHIFT 18 + +/* NAND number of ECC bits per 512 bytes */ +#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) +#define NAND_ECC_BIT_NB_SHIFT 15 +#define NAND_ECC_BIT_NB_UNSET U(0) +#define NAND_ECC_BIT_NB_1_BITS U(1) +#define NAND_ECC_BIT_NB_4_BITS U(2) +#define NAND_ECC_BIT_NB_8_BITS U(3) +#define NAND_ECC_ON_DIE U(4) + /******************************************************************************* * STM32MP1 TAMP ******************************************************************************/ -- cgit v1.2.3 From 7e51e887a71dbdb17c1d666b75c88eacfe8b7903 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Tue, 24 Sep 2019 17:49:12 +0200 Subject: fdts: stm32mp1: update for FMC2 pin muxing Include the required FMC2 pinmux definition for the NAND management. Change-Id: I80333deacdf3444b2f21f17f2fb5919e569a3591 Signed-off-by: Lionel Debieve --- fdts/stm32mp157-pinctrl.dtsi | 27 ++++++++++++++++++++++++++- fdts/stm32mp157c-ev1.dts | 7 +++---- 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/fdts/stm32mp157-pinctrl.dtsi b/fdts/stm32mp157-pinctrl.dtsi index 8e480b2c1..7fd902bd2 100644 --- a/fdts/stm32mp157-pinctrl.dtsi +++ b/fdts/stm32mp157-pinctrl.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ #include @@ -135,6 +135,31 @@ status = "disabled"; }; + fmc_pins_a: fmc-0 { + pins1 { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_A16_FMC_CLE */ + , /* FMC_A17_FMC_ALE */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + ; /* FMC_NE2_FMC_NCE */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* FMC_NWAIT */ + bias-pull-up; + }; + }; + qspi_bk1_pins_a: qspi-bk1-0 { pins1 { pinmux = , /* QSPI_BK1_IO0 */ diff --git a/fdts/stm32mp157c-ev1.dts b/fdts/stm32mp157c-ev1.dts index cfde8ed90..51500fadb 100644 --- a/fdts/stm32mp157c-ev1.dts +++ b/fdts/stm32mp157c-ev1.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ /dts-v1/; @@ -21,15 +21,14 @@ }; &fmc { + pinctrl-names = "default"; + pinctrl-0 = <&fmc_pins_a>; status = "okay"; #address-cells = <1>; #size-cells = <0>; nand: nand@0 { reg = <0>; - nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <1>; }; }; -- cgit v1.2.3 From 0581a8877845d472f9bf6a2171e79050b8363fa7 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Tue, 24 Sep 2019 17:44:28 +0200 Subject: spi: stm32_qspi: Add QSPI support Add QSPI support (limited to read interface). Implements the memory map and indirect modes. Low level driver based on SPI-MEM operations. Change-Id: Ied698e6de3c17d977f8b497c81f2e4a0a27c0961 Signed-off-by: Lionel Debieve Signed-off-by: Christophe Kerello --- drivers/st/spi/stm32_qspi.c | 500 ++++++++++++++++++++++++++++++++++++++++ include/drivers/st/stm32_qspi.h | 12 + 2 files changed, 512 insertions(+) create mode 100644 drivers/st/spi/stm32_qspi.c create mode 100644 include/drivers/st/stm32_qspi.h diff --git a/drivers/st/spi/stm32_qspi.c b/drivers/st/spi/stm32_qspi.c new file mode 100644 index 000000000..188d2ff80 --- /dev/null +++ b/drivers/st/spi/stm32_qspi.c @@ -0,0 +1,500 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +/* QUADSPI registers */ +#define QSPI_CR 0x00U +#define QSPI_DCR 0x04U +#define QSPI_SR 0x08U +#define QSPI_FCR 0x0CU +#define QSPI_DLR 0x10U +#define QSPI_CCR 0x14U +#define QSPI_AR 0x18U +#define QSPI_ABR 0x1CU +#define QSPI_DR 0x20U +#define QSPI_PSMKR 0x24U +#define QSPI_PSMAR 0x28U +#define QSPI_PIR 0x2CU +#define QSPI_LPTR 0x30U + +/* QUADSPI control register */ +#define QSPI_CR_EN BIT(0) +#define QSPI_CR_ABORT BIT(1) +#define QSPI_CR_DMAEN BIT(2) +#define QSPI_CR_TCEN BIT(3) +#define QSPI_CR_SSHIFT BIT(4) +#define QSPI_CR_DFM BIT(6) +#define QSPI_CR_FSEL BIT(7) +#define QSPI_CR_FTHRES_SHIFT 8U +#define QSPI_CR_TEIE BIT(16) +#define QSPI_CR_TCIE BIT(17) +#define QSPI_CR_FTIE BIT(18) +#define QSPI_CR_SMIE BIT(19) +#define QSPI_CR_TOIE BIT(20) +#define QSPI_CR_APMS BIT(22) +#define QSPI_CR_PMM BIT(23) +#define QSPI_CR_PRESCALER_MASK GENMASK_32(31, 24) +#define QSPI_CR_PRESCALER_SHIFT 24U + +/* QUADSPI device configuration register */ +#define QSPI_DCR_CKMODE BIT(0) +#define QSPI_DCR_CSHT_MASK GENMASK_32(10, 8) +#define QSPI_DCR_CSHT_SHIFT 8U +#define QSPI_DCR_FSIZE_MASK GENMASK_32(20, 16) +#define QSPI_DCR_FSIZE_SHIFT 16U + +/* QUADSPI status register */ +#define QSPI_SR_TEF BIT(0) +#define QSPI_SR_TCF BIT(1) +#define QSPI_SR_FTF BIT(2) +#define QSPI_SR_SMF BIT(3) +#define QSPI_SR_TOF BIT(4) +#define QSPI_SR_BUSY BIT(5) + +/* QUADSPI flag clear register */ +#define QSPI_FCR_CTEF BIT(0) +#define QSPI_FCR_CTCF BIT(1) +#define QSPI_FCR_CSMF BIT(3) +#define QSPI_FCR_CTOF BIT(4) + +/* QUADSPI communication configuration register */ +#define QSPI_CCR_DDRM BIT(31) +#define QSPI_CCR_DHHC BIT(30) +#define QSPI_CCR_SIOO BIT(28) +#define QSPI_CCR_FMODE_SHIFT 26U +#define QSPI_CCR_DMODE_SHIFT 24U +#define QSPI_CCR_DCYC_SHIFT 18U +#define QSPI_CCR_ABSIZE_SHIFT 16U +#define QSPI_CCR_ABMODE_SHIFT 14U +#define QSPI_CCR_ADSIZE_SHIFT 12U +#define QSPI_CCR_ADMODE_SHIFT 10U +#define QSPI_CCR_IMODE_SHIFT 8U +#define QSPI_CCR_IND_WRITE 0U +#define QSPI_CCR_IND_READ 1U +#define QSPI_CCR_MEM_MAP 3U + +#define QSPI_MAX_CHIP 2U + +#define QSPI_FIFO_TIMEOUT_US 30U +#define QSPI_CMD_TIMEOUT_US 1000U +#define QSPI_BUSY_TIMEOUT_US 100U +#define QSPI_ABT_TIMEOUT_US 100U + +#define DT_QSPI_COMPAT "st,stm32f469-qspi" + +#define FREQ_100MHZ 100000000U + +struct stm32_qspi_ctrl { + uintptr_t reg_base; + uintptr_t mm_base; + size_t mm_size; + unsigned long clock_id; + unsigned int reset_id; +}; + +static struct stm32_qspi_ctrl stm32_qspi; + +static uintptr_t qspi_base(void) +{ + return stm32_qspi.reg_base; +} + +static int stm32_qspi_wait_for_not_busy(void) +{ + uint64_t timeout = timeout_init_us(QSPI_BUSY_TIMEOUT_US); + + while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_BUSY) != 0U) { + if (timeout_elapsed(timeout)) { + ERROR("%s: busy timeout\n", __func__); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int stm32_qspi_wait_cmd(const struct spi_mem_op *op) +{ + int ret = 0; + uint64_t timeout; + + if (op->data.nbytes == 0U) { + return stm32_qspi_wait_for_not_busy(); + } + + timeout = timeout_init_us(QSPI_CMD_TIMEOUT_US); + while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TCF) == 0U) { + if (timeout_elapsed(timeout)) { + ret = -ETIMEDOUT; + break; + } + } + + if (ret == 0) { + if ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TEF) != 0U) { + ERROR("%s: transfer error\n", __func__); + ret = -EIO; + } + } else { + ERROR("%s: cmd timeout\n", __func__); + } + + /* Clear flags */ + mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF | QSPI_FCR_CTEF); + + return ret; +} + +static void stm32_qspi_read_fifo(uint8_t *val, uintptr_t addr) +{ + *val = mmio_read_8(addr); +} + +static void stm32_qspi_write_fifo(uint8_t *val, uintptr_t addr) +{ + mmio_write_8(addr, *val); +} + +static int stm32_qspi_poll(const struct spi_mem_op *op) +{ + void (*fifo)(uint8_t *val, uintptr_t addr); + uint32_t len = op->data.nbytes; + uint8_t *buf; + uint64_t timeout; + + if (op->data.dir == SPI_MEM_DATA_IN) { + fifo = stm32_qspi_read_fifo; + } else { + fifo = stm32_qspi_write_fifo; + } + + buf = (uint8_t *)op->data.buf; + + for (len = op->data.nbytes; len != 0U; len--) { + timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US); + while ((mmio_read_32(qspi_base() + QSPI_SR) & + QSPI_SR_FTF) == 0U) { + if (timeout_elapsed(timeout)) { + ERROR("%s: fifo timeout\n", __func__); + return -ETIMEDOUT; + } + } + + fifo(buf++, qspi_base() + QSPI_DR); + } + + return 0; +} + +static int stm32_qspi_mm(const struct spi_mem_op *op) +{ + memcpy(op->data.buf, + (void *)(stm32_qspi.mm_base + (size_t)op->addr.val), + op->data.nbytes); + + return 0; +} + +static int stm32_qspi_tx(const struct spi_mem_op *op, uint8_t mode) +{ + if (op->data.nbytes == 0U) { + return 0; + } + + if (mode == QSPI_CCR_MEM_MAP) { + return stm32_qspi_mm(op); + } + + return stm32_qspi_poll(op); +} + +static unsigned int stm32_qspi_get_mode(uint8_t buswidth) +{ + if (buswidth == 4U) { + return 3U; + } + + return buswidth; +} + +static int stm32_qspi_exec_op(const struct spi_mem_op *op) +{ + uint64_t timeout; + uint32_t ccr; + size_t addr_max; + uint8_t mode = QSPI_CCR_IND_WRITE; + int ret; + + VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addr:%llx len:%x\n", + __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, + op->dummy.buswidth, op->data.buswidth, + op->addr.val, op->data.nbytes); + + ret = stm32_qspi_wait_for_not_busy(); + if (ret != 0) { + return ret; + } + + addr_max = op->addr.val + op->data.nbytes + 1U; + + if ((op->data.dir == SPI_MEM_DATA_IN) && (op->data.nbytes != 0U)) { + if ((addr_max < stm32_qspi.mm_size) && + (op->addr.buswidth != 0U)) { + mode = QSPI_CCR_MEM_MAP; + } else { + mode = QSPI_CCR_IND_READ; + } + } + + if (op->data.nbytes != 0U) { + mmio_write_32(qspi_base() + QSPI_DLR, op->data.nbytes - 1U); + } + + ccr = mode << QSPI_CCR_FMODE_SHIFT; + ccr |= op->cmd.opcode; + ccr |= stm32_qspi_get_mode(op->cmd.buswidth) << QSPI_CCR_IMODE_SHIFT; + + if (op->addr.nbytes != 0U) { + ccr |= (op->addr.nbytes - 1U) << QSPI_CCR_ADSIZE_SHIFT; + ccr |= stm32_qspi_get_mode(op->addr.buswidth) << + QSPI_CCR_ADMODE_SHIFT; + } + + if ((op->dummy.buswidth != 0U) && (op->dummy.nbytes != 0U)) { + ccr |= (op->dummy.nbytes * 8U / op->dummy.buswidth) << + QSPI_CCR_DCYC_SHIFT; + } + + if (op->data.nbytes != 0U) { + ccr |= stm32_qspi_get_mode(op->data.buswidth) << + QSPI_CCR_DMODE_SHIFT; + } + + mmio_write_32(qspi_base() + QSPI_CCR, ccr); + + if ((op->addr.nbytes != 0U) && (mode != QSPI_CCR_MEM_MAP)) { + mmio_write_32(qspi_base() + QSPI_AR, op->addr.val); + } + + ret = stm32_qspi_tx(op, mode); + + /* + * Abort in: + * - Error case. + * - Memory mapped read: prefetching must be stopped if we read the last + * byte of device (device size - fifo size). If device size is not + * known then prefetching is always stopped. + */ + if ((ret != 0) || (mode == QSPI_CCR_MEM_MAP)) { + goto abort; + } + + /* Wait end of TX in indirect mode */ + ret = stm32_qspi_wait_cmd(op); + if (ret != 0) { + goto abort; + } + + return 0; + +abort: + mmio_setbits_32(qspi_base() + QSPI_CR, QSPI_CR_ABORT); + + /* Wait clear of abort bit by hardware */ + timeout = timeout_init_us(QSPI_ABT_TIMEOUT_US); + while ((mmio_read_32(qspi_base() + QSPI_CR) & QSPI_CR_ABORT) != 0U) { + if (timeout_elapsed(timeout)) { + ret = -ETIMEDOUT; + break; + } + } + + mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF); + + if (ret != 0) { + ERROR("%s: exec op error\n", __func__); + } + + return ret; +} + +static int stm32_qspi_claim_bus(unsigned int cs) +{ + uint32_t cr; + + if (cs >= QSPI_MAX_CHIP) { + return -ENODEV; + } + + /* Set chip select and enable the controller */ + cr = QSPI_CR_EN; + if (cs == 1U) { + cr |= QSPI_CR_FSEL; + } + + mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_FSEL, cr); + + return 0; +} + +static void stm32_qspi_release_bus(void) +{ + mmio_clrbits_32(qspi_base() + QSPI_CR, QSPI_CR_EN); +} + +static int stm32_qspi_set_speed(unsigned int hz) +{ + unsigned long qspi_clk = stm32mp_clk_get_rate(stm32_qspi.clock_id); + uint32_t prescaler = UINT8_MAX; + uint32_t csht; + int ret; + + if (qspi_clk == 0U) { + return -EINVAL; + } + + if (hz > 0U) { + prescaler = div_round_up(qspi_clk, hz) - 1U; + if (prescaler > UINT8_MAX) { + prescaler = UINT8_MAX; + } + } + + csht = div_round_up((5U * qspi_clk) / (prescaler + 1U), FREQ_100MHZ); + csht = ((csht - 1U) << QSPI_DCR_CSHT_SHIFT) & QSPI_DCR_CSHT_MASK; + + ret = stm32_qspi_wait_for_not_busy(); + if (ret != 0) { + return ret; + } + + mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_PRESCALER_MASK, + prescaler << QSPI_CR_PRESCALER_SHIFT); + + mmio_clrsetbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CSHT_MASK, csht); + + VERBOSE("%s: speed=%lu\n", __func__, qspi_clk / (prescaler + 1U)); + + return 0; +} + +static int stm32_qspi_set_mode(unsigned int mode) +{ + int ret; + + ret = stm32_qspi_wait_for_not_busy(); + if (ret != 0) { + return ret; + } + + if ((mode & SPI_CS_HIGH) != 0U) { + return -ENODEV; + } + + if (((mode & SPI_CPHA) != 0U) && ((mode & SPI_CPOL) != 0U)) { + mmio_setbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE); + } else if (((mode & SPI_CPHA) == 0U) && ((mode & SPI_CPOL) == 0U)) { + mmio_clrbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE); + } else { + return -ENODEV; + } + + VERBOSE("%s: mode=0x%x\n", __func__, mode); + + if ((mode & SPI_RX_QUAD) != 0U) { + VERBOSE("rx: quad\n"); + } else if ((mode & SPI_RX_DUAL) != 0U) { + VERBOSE("rx: dual\n"); + } else { + VERBOSE("rx: single\n"); + } + + if ((mode & SPI_TX_QUAD) != 0U) { + VERBOSE("tx: quad\n"); + } else if ((mode & SPI_TX_DUAL) != 0U) { + VERBOSE("tx: dual\n"); + } else { + VERBOSE("tx: single\n"); + } + + return 0; +} + +static const struct spi_bus_ops stm32_qspi_bus_ops = { + .claim_bus = stm32_qspi_claim_bus, + .release_bus = stm32_qspi_release_bus, + .set_speed = stm32_qspi_set_speed, + .set_mode = stm32_qspi_set_mode, + .exec_op = stm32_qspi_exec_op, +}; + +int stm32_qspi_init(void) +{ + size_t size; + int qspi_node; + struct dt_node_info info; + void *fdt = NULL; + int ret; + + if (fdt_get_address(&fdt) == 0) { + return -FDT_ERR_NOTFOUND; + } + + qspi_node = dt_get_node(&info, -1, DT_QSPI_COMPAT); + if (qspi_node < 0) { + ERROR("No QSPI ctrl found\n"); + return -FDT_ERR_NOTFOUND; + } + + if (info.status == DT_DISABLED) { + return -FDT_ERR_NOTFOUND; + } + + ret = fdt_get_reg_props_by_name(qspi_node, "qspi", + &stm32_qspi.reg_base, &size); + if (ret != 0) { + return ret; + } + + ret = fdt_get_reg_props_by_name(qspi_node, "qspi_mm", + &stm32_qspi.mm_base, + &stm32_qspi.mm_size); + if (ret != 0) { + return ret; + } + + if (dt_set_pinctrl_config(qspi_node) != 0) { + return -FDT_ERR_BADVALUE; + } + + if ((info.clock < 0) || (info.reset < 0)) { + return -FDT_ERR_BADVALUE; + } + + stm32_qspi.clock_id = (unsigned long)info.clock; + stm32_qspi.reset_id = (unsigned int)info.reset; + + stm32mp_clk_enable(stm32_qspi.clock_id); + + stm32mp_reset_assert(stm32_qspi.reset_id); + stm32mp_reset_deassert(stm32_qspi.reset_id); + + mmio_write_32(qspi_base() + QSPI_CR, QSPI_CR_SSHIFT); + mmio_write_32(qspi_base() + QSPI_DCR, QSPI_DCR_FSIZE_MASK); + + return spi_mem_init_slave(fdt, qspi_node, &stm32_qspi_bus_ops); +}; diff --git a/include/drivers/st/stm32_qspi.h b/include/drivers/st/stm32_qspi.h new file mode 100644 index 000000000..f47fca445 --- /dev/null +++ b/include/drivers/st/stm32_qspi.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32_QSPI_H +#define STM32_QSPI_H + +int stm32_qspi_init(void); + +#endif /* STM32_QSPI_H */ -- cgit v1.2.3 From 570442281400c3fea280ef45fdc4c92ec864e494 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Tue, 24 Sep 2019 18:30:12 +0200 Subject: stm32mp1: Add support for SPI-NAND boot device STM32MP1 platform is able to boot from SPI-NAND devices. These modifications add this support using the new SPI-NAND framework. Change-Id: I0d5448bdc4bde153c1209e8043846c0f935ae5ba Signed-off-by: Lionel Debieve --- plat/st/common/bl2_io_storage.c | 76 ++++++++++++++++++++++++ plat/st/stm32mp1/include/boot_api.h | 3 + plat/st/stm32mp1/include/stm32mp1_boot_device.h | 2 + plat/st/stm32mp1/platform.mk | 17 +++++- plat/st/stm32mp1/stm32mp1_boot_device.c | 78 ++++++++++++++++--------- plat/st/stm32mp1/stm32mp1_def.h | 3 + 6 files changed, 151 insertions(+), 28 deletions(-) diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c index e2629fa5d..d0bc60576 100644 --- a/plat/st/common/bl2_io_storage.c +++ b/plat/st/common/bl2_io_storage.c @@ -19,9 +19,11 @@ #include #include #include +#include #include #include #include +#include #include #include #include @@ -70,6 +72,17 @@ static io_mtd_dev_spec_t nand_dev_spec = { static const io_dev_connector_t *nand_dev_con; #endif +#if STM32MP_SPI_NAND +static io_mtd_dev_spec_t spi_nand_dev_spec = { + .ops = { + .init = spi_nand_init, + .read = nand_read, + }, +}; + +static const io_dev_connector_t *spi_dev_con; +#endif + #ifdef AARCH32_SP_OPTEE static const struct stm32image_part_info optee_header_partition_spec = { .name = OPTEE_HEADER_IMAGE_NAME, @@ -226,6 +239,9 @@ static void print_boot_device(boot_api_context_t *boot_context) case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: INFO("Using FMC NAND\n"); break; + case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: + INFO("Using SPI NAND\n"); + break; default: ERROR("Boot interface not found\n"); panic(); @@ -382,6 +398,60 @@ static void boot_fmc2_nand(boot_api_context_t *boot_context) } #endif /* STM32MP_RAW_NAND */ +#if STM32MP_SPI_NAND +static void boot_spi_nand(boot_api_context_t *boot_context) +{ + int io_result __unused; + uint8_t idx; + struct stm32image_part_info *part; + + io_result = stm32_qspi_init(); + assert(io_result == 0); + + io_result = register_io_dev_mtd(&spi_dev_con); + assert(io_result == 0); + + /* Open connections to device */ + io_result = io_dev_open(spi_dev_con, + (uintptr_t)&spi_nand_dev_spec, + &storage_dev_handle); + assert(io_result == 0); + + stm32image_dev_info_spec.device_size = + spi_nand_dev_spec.device_size; + + idx = IMG_IDX_BL33; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NAND_BL33_OFFSET; + part->bkp_offset = spi_nand_dev_spec.erase_size; + +#ifdef AARCH32_SP_OPTEE + idx = IMG_IDX_OPTEE_HEADER; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NAND_TEEH_OFFSET; + part->bkp_offset = spi_nand_dev_spec.erase_size; + + idx = IMG_IDX_OPTEE_PAGED; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NAND_TEED_OFFSET; + part->bkp_offset = spi_nand_dev_spec.erase_size; + + idx = IMG_IDX_OPTEE_PAGER; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NAND_TEEX_OFFSET; + part->bkp_offset = spi_nand_dev_spec.erase_size; +#endif + + io_result = register_io_dev_stm32image(&stm32image_dev_con); + assert(io_result == 0); + + io_result = io_dev_open(stm32image_dev_con, + (uintptr_t)&stm32image_dev_info_spec, + &image_dev_handle); + assert(io_result == 0); +} +#endif /* STM32MP_SPI_NAND */ + void stm32mp_io_setup(void) { int io_result __unused; @@ -422,6 +492,12 @@ void stm32mp_io_setup(void) boot_fmc2_nand(boot_context); break; #endif +#if STM32MP_SPI_NAND + case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: + dmbsy(); + boot_spi_nand(boot_context); + break; +#endif default: ERROR("Boot interface %d not supported\n", diff --git a/plat/st/stm32mp1/include/boot_api.h b/plat/st/stm32mp1/include/boot_api.h index ba5d22fa2..1f05d0b26 100644 --- a/plat/st/stm32mp1/include/boot_api.h +++ b/plat/st/stm32mp1/include/boot_api.h @@ -36,6 +36,9 @@ /* Boot occurred on FMC */ #define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U +/* Boot occurred on QSPI NAND */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI 0x7U + /** * @brief Possible value of boot context field 'EmmcXferStatus' */ diff --git a/plat/st/stm32mp1/include/stm32mp1_boot_device.h b/plat/st/stm32mp1/include/stm32mp1_boot_device.h index ae6b02beb..db80f9338 100644 --- a/plat/st/stm32mp1/include/stm32mp1_boot_device.h +++ b/plat/st/stm32mp1/include/stm32mp1_boot_device.h @@ -8,7 +8,9 @@ #define STM32MP1_BOOT_DEVICE_H #include +#include int plat_get_raw_nand_data(struct rawnand_device *device); +int plat_get_spi_nand_data(struct spinand_device *device); #endif /* STM32MP1_BOOT_DEVICE_H */ diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index 71b39168d..d25f3b3ac 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -28,17 +28,21 @@ $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) STM32MP_EMMC ?= 0 STM32MP_SDMMC ?= 0 STM32MP_RAW_NAND ?= 0 +STM32MP_SPI_NAND ?= 0 -ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC} ${STM32MP_RAW_NAND}),) +ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC} ${STM32MP_RAW_NAND} \ + ${STM32MP_SPI_NAND}),) $(error "No boot device driver is enabled") endif $(eval $(call assert_boolean,STM32MP_EMMC)) $(eval $(call assert_boolean,STM32MP_SDMMC)) $(eval $(call assert_boolean,STM32MP_RAW_NAND)) +$(eval $(call assert_boolean,STM32MP_SPI_NAND)) $(eval $(call add_define,STM32MP_EMMC)) $(eval $(call add_define,STM32MP_SDMMC)) $(eval $(call add_define,STM32MP_RAW_NAND)) +$(eval $(call add_define,STM32MP_SPI_NAND)) PLAT_INCLUDES := -Iplat/st/common/include/ PLAT_INCLUDES += -Iplat/st/stm32mp1/include/ @@ -108,7 +112,16 @@ BL2_SOURCES += drivers/mtd/nand/raw_nand.c \ drivers/st/fmc/stm32_fmc2_nand.c endif -ifneq ($(filter 1,${STM32MP_RAW_NAND}),) +ifeq (${STM32MP_SPI_NAND},1) +BL2_SOURCES += drivers/mtd/nand/spi_nand.c +endif + +ifeq (${STM32MP_SPI_NAND},1) +BL2_SOURCES += drivers/mtd/spi-mem/spi_mem.c \ + drivers/st/spi/stm32_qspi.c +endif + +ifneq ($(filter 1,${STM32MP_RAW_NAND} ${STM32MP_SPI_NAND}),) BL2_SOURCES += drivers/mtd/nand/core.c \ plat/st/stm32mp1/stm32mp1_boot_device.c endif diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c index 8b1f07f6d..fa352f341 100644 --- a/plat/st/stm32mp1/stm32mp1_boot_device.c +++ b/plat/st/stm32mp1/stm32mp1_boot_device.c @@ -12,8 +12,8 @@ #define SZ_512 0x200U -#if STM32MP_RAW_NAND -static int get_data_from_otp(struct nand_device *nand_dev) +#if STM32MP_RAW_NAND || STM32MP_SPI_NAND +static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc) { int result; uint32_t nand_param; @@ -81,28 +81,37 @@ static int get_data_from_otp(struct nand_device *nand_dev) NAND_BLOCK_NB_UNIT * nand_dev->block_size; ecc: - switch ((nand_param & NAND_ECC_BIT_NB_MASK) >> - NAND_ECC_BIT_NB_SHIFT) { - case NAND_ECC_BIT_NB_1_BITS: - nand_dev->ecc.max_bit_corr = 1U; - break; - - case NAND_ECC_BIT_NB_4_BITS: - nand_dev->ecc.max_bit_corr = 4U; - break; - - case NAND_ECC_BIT_NB_8_BITS: - nand_dev->ecc.max_bit_corr = 8U; - break; - - case NAND_ECC_ON_DIE: - nand_dev->ecc.mode = NAND_ECC_ONDIE; - break; - - default: - if (nand_dev->ecc.max_bit_corr == 0U) { - ERROR("No valid eccbit number\n"); - return -EINVAL; + if (is_slc) { + switch ((nand_param & NAND_ECC_BIT_NB_MASK) >> + NAND_ECC_BIT_NB_SHIFT) { + case NAND_ECC_BIT_NB_1_BITS: + nand_dev->ecc.max_bit_corr = 1U; + break; + + case NAND_ECC_BIT_NB_4_BITS: + nand_dev->ecc.max_bit_corr = 4U; + break; + + case NAND_ECC_BIT_NB_8_BITS: + nand_dev->ecc.max_bit_corr = 8U; + break; + + case NAND_ECC_ON_DIE: + nand_dev->ecc.mode = NAND_ECC_ONDIE; + break; + + default: + if (nand_dev->ecc.max_bit_corr == 0U) { + ERROR("No valid eccbit number\n"); + return -EINVAL; + } + } + } else { + /* Selected multiple plane NAND */ + if ((nand_param & NAND_PLANE_BIT_NB_MASK) != 0U) { + nand_dev->nb_planes = 2U; + } else { + nand_dev->nb_planes = 1U; } } @@ -111,7 +120,7 @@ ecc: return 0; } -#endif +#endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */ #if STM32MP_RAW_NAND int plat_get_raw_nand_data(struct rawnand_device *device) @@ -119,7 +128,24 @@ int plat_get_raw_nand_data(struct rawnand_device *device) device->nand_dev->ecc.mode = NAND_ECC_HW; device->nand_dev->ecc.size = SZ_512; - return get_data_from_otp(device->nand_dev); + return get_data_from_otp(device->nand_dev, true); +} +#endif + +#if STM32MP_SPI_NAND +int plat_get_spi_nand_data(struct spinand_device *device) +{ + zeromem(&device->spi_read_cache_op, sizeof(struct spi_mem_op)); + device->spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE_4X; + device->spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + device->spi_read_cache_op.addr.nbytes = 2U; + device->spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + device->spi_read_cache_op.dummy.nbytes = 1U; + device->spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + device->spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE; + device->spi_read_cache_op.data.dir = SPI_MEM_DATA_IN; + + return get_data_from_otp(device->nand_dev, false); } #endif diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 7ac9b5fe4..a427dcf7d 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -340,6 +340,9 @@ enum ddr_type { #define NAND_ECC_BIT_NB_8_BITS U(3) #define NAND_ECC_ON_DIE U(4) +/* NAND number of planes */ +#define NAND_PLANE_BIT_NB_MASK BIT(14) + /******************************************************************************* * STM32MP1 TAMP ******************************************************************************/ -- cgit v1.2.3 From b1b218fb1bfc1e2ea028137a492ba4e54ed54173 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Wed, 25 Sep 2019 09:11:31 +0200 Subject: stm32mp1: Add support for SPI-NOR boot device STM32MP1 platform is able to boot from SPI-NOR devices. These modifications add this support using the new SPI-NOR framework. Change-Id: I75ff9eba4661f9fb87ce24ced2bacbf8558ebe44 Signed-off-by: Lionel Debieve --- plat/st/common/bl2_io_storage.c | 74 +++++++++++++++++++++++++ plat/st/stm32mp1/include/boot_api.h | 3 + plat/st/stm32mp1/include/stm32mp1_boot_device.h | 2 + plat/st/stm32mp1/platform.mk | 18 ++++-- plat/st/stm32mp1/stm32mp1_boot_device.c | 19 +++++++ plat/st/stm32mp1/stm32mp1_def.h | 7 +++ 6 files changed, 119 insertions(+), 4 deletions(-) diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c index d0bc60576..3ec7d4048 100644 --- a/plat/st/common/bl2_io_storage.c +++ b/plat/st/common/bl2_io_storage.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -61,6 +62,15 @@ static const io_block_dev_spec_t mmc_block_dev_spec = { static const io_dev_connector_t *mmc_dev_con; #endif /* STM32MP_SDMMC || STM32MP_EMMC */ +#if STM32MP_SPI_NOR +static io_mtd_dev_spec_t spi_nor_dev_spec = { + .ops = { + .init = spi_nor_init, + .read = spi_nor_read, + }, +}; +#endif + #if STM32MP_RAW_NAND static io_mtd_dev_spec_t nand_dev_spec = { .ops = { @@ -79,7 +89,9 @@ static io_mtd_dev_spec_t spi_nand_dev_spec = { .read = nand_read, }, }; +#endif +#if STM32MP_SPI_NAND || STM32MP_SPI_NOR static const io_dev_connector_t *spi_dev_con; #endif @@ -236,6 +248,9 @@ static void print_boot_device(boot_api_context_t *boot_context) case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: INFO("Using EMMC\n"); break; + case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: + INFO("Using QSPI NOR\n"); + break; case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: INFO("Using FMC NAND\n"); break; @@ -345,6 +360,59 @@ static void boot_mmc(enum mmc_device_type mmc_dev_type, } #endif /* STM32MP_SDMMC || STM32MP_EMMC */ +#if STM32MP_SPI_NOR +static void boot_spi_nor(boot_api_context_t *boot_context) +{ + int io_result __unused; + uint8_t idx; + struct stm32image_part_info *part; + + io_result = stm32_qspi_init(); + assert(io_result == 0); + + io_result = register_io_dev_mtd(&spi_dev_con); + assert(io_result == 0); + + /* Open connections to device */ + io_result = io_dev_open(spi_dev_con, + (uintptr_t)&spi_nor_dev_spec, + &storage_dev_handle); + assert(io_result == 0); + + stm32image_dev_info_spec.device_size = spi_nor_dev_spec.device_size; + + idx = IMG_IDX_BL33; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NOR_BL33_OFFSET; + part->bkp_offset = 0U; + +#ifdef AARCH32_SP_OPTEE + idx = IMG_IDX_OPTEE_HEADER; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NOR_TEEH_OFFSET; + part->bkp_offset = 0U; + + idx = IMG_IDX_OPTEE_PAGED; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NOR_TEED_OFFSET; + part->bkp_offset = 0U; + + idx = IMG_IDX_OPTEE_PAGER; + part = &stm32image_dev_info_spec.part_info[idx]; + part->part_offset = STM32MP_NOR_TEEX_OFFSET; + part->bkp_offset = 0U; +#endif + + io_result = register_io_dev_stm32image(&stm32image_dev_con); + assert(io_result == 0); + + io_result = io_dev_open(stm32image_dev_con, + (uintptr_t)&stm32image_dev_info_spec, + &image_dev_handle); + assert(io_result == 0); +} +#endif /* STM32MP_SPI_NOR */ + #if STM32MP_RAW_NAND static void boot_fmc2_nand(boot_api_context_t *boot_context) { @@ -486,6 +554,12 @@ void stm32mp_io_setup(void) boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); break; #endif +#if STM32MP_SPI_NOR + case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: + dmbsy(); + boot_spi_nor(boot_context); + break; +#endif #if STM32MP_RAW_NAND case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: dmbsy(); diff --git a/plat/st/stm32mp1/include/boot_api.h b/plat/st/stm32mp1/include/boot_api.h index 1f05d0b26..c16639ac4 100644 --- a/plat/st/stm32mp1/include/boot_api.h +++ b/plat/st/stm32mp1/include/boot_api.h @@ -36,6 +36,9 @@ /* Boot occurred on FMC */ #define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U +/* Boot occurred on QSPI NOR */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI 0x4U + /* Boot occurred on QSPI NAND */ #define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI 0x7U diff --git a/plat/st/stm32mp1/include/stm32mp1_boot_device.h b/plat/st/stm32mp1/include/stm32mp1_boot_device.h index db80f9338..a74598395 100644 --- a/plat/st/stm32mp1/include/stm32mp1_boot_device.h +++ b/plat/st/stm32mp1/include/stm32mp1_boot_device.h @@ -9,8 +9,10 @@ #include #include +#include int plat_get_raw_nand_data(struct rawnand_device *device); int plat_get_spi_nand_data(struct spinand_device *device); +int plat_get_nor_data(struct nor_device *device); #endif /* STM32MP1_BOOT_DEVICE_H */ diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index d25f3b3ac..b86287b66 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -29,9 +29,10 @@ STM32MP_EMMC ?= 0 STM32MP_SDMMC ?= 0 STM32MP_RAW_NAND ?= 0 STM32MP_SPI_NAND ?= 0 +STM32MP_SPI_NOR ?= 0 ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC} ${STM32MP_RAW_NAND} \ - ${STM32MP_SPI_NAND}),) + ${STM32MP_SPI_NAND} ${STM32MP_SPI_NOR}),) $(error "No boot device driver is enabled") endif @@ -39,10 +40,12 @@ $(eval $(call assert_boolean,STM32MP_EMMC)) $(eval $(call assert_boolean,STM32MP_SDMMC)) $(eval $(call assert_boolean,STM32MP_RAW_NAND)) $(eval $(call assert_boolean,STM32MP_SPI_NAND)) +$(eval $(call assert_boolean,STM32MP_SPI_NOR)) $(eval $(call add_define,STM32MP_EMMC)) $(eval $(call add_define,STM32MP_SDMMC)) $(eval $(call add_define,STM32MP_RAW_NAND)) $(eval $(call add_define,STM32MP_SPI_NAND)) +$(eval $(call add_define,STM32MP_SPI_NOR)) PLAT_INCLUDES := -Iplat/st/common/include/ PLAT_INCLUDES += -Iplat/st/stm32mp1/include/ @@ -116,14 +119,21 @@ ifeq (${STM32MP_SPI_NAND},1) BL2_SOURCES += drivers/mtd/nand/spi_nand.c endif -ifeq (${STM32MP_SPI_NAND},1) +ifeq (${STM32MP_SPI_NOR},1) +BL2_SOURCES += drivers/mtd/nor/spi_nor.c +endif + +ifneq ($(filter 1,${STM32MP_SPI_NAND} ${STM32MP_SPI_NOR}),) BL2_SOURCES += drivers/mtd/spi-mem/spi_mem.c \ drivers/st/spi/stm32_qspi.c endif ifneq ($(filter 1,${STM32MP_RAW_NAND} ${STM32MP_SPI_NAND}),) -BL2_SOURCES += drivers/mtd/nand/core.c \ - plat/st/stm32mp1/stm32mp1_boot_device.c +BL2_SOURCES += drivers/mtd/nand/core.c +endif + +ifneq ($(filter 1,${STM32MP_RAW_NAND} ${STM32MP_SPI_NAND} ${STM32MP_SPI_NOR}),) +BL2_SOURCES += plat/st/stm32mp1/stm32mp1_boot_device.c endif BL2_SOURCES += drivers/st/ddr/stm32mp1_ddr.c \ diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c index fa352f341..2d8eccff7 100644 --- a/plat/st/stm32mp1/stm32mp1_boot_device.c +++ b/plat/st/stm32mp1/stm32mp1_boot_device.c @@ -11,6 +11,7 @@ #include #define SZ_512 0x200U +#define SZ_64M 0x4000000U #if STM32MP_RAW_NAND || STM32MP_SPI_NAND static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc) @@ -149,3 +150,21 @@ int plat_get_spi_nand_data(struct spinand_device *device) } #endif +#if STM32MP_SPI_NOR +int plat_get_nor_data(struct nor_device *device) +{ + device->size = SZ_64M; + + zeromem(&device->read_op, sizeof(struct spi_mem_op)); + device->read_op.cmd.opcode = SPI_NOR_OP_READ_1_1_4; + device->read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + device->read_op.addr.nbytes = 3U; + device->read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + device->read_op.dummy.nbytes = 1U; + device->read_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE; + device->read_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE; + device->read_op.data.dir = SPI_MEM_DATA_IN; + + return 0; +} +#endif diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index a427dcf7d..11b01ab88 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -151,6 +151,13 @@ enum ddr_type { /******************************************************************************* * STM32MP1 RAW partition offset for MTD devices ******************************************************************************/ +#define STM32MP_NOR_BL33_OFFSET U(0x00080000) +#ifdef AARCH32_SP_OPTEE +#define STM32MP_NOR_TEEH_OFFSET U(0x00280000) +#define STM32MP_NOR_TEED_OFFSET U(0x002C0000) +#define STM32MP_NOR_TEEX_OFFSET U(0x00300000) +#endif + #define STM32MP_NAND_BL33_OFFSET U(0x00200000) #ifdef AARCH32_SP_OPTEE #define STM32MP_NAND_TEEH_OFFSET U(0x00600000) -- cgit v1.2.3 From 46e9b7a09139870dae775e1c0d37d5fccf40fff2 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Wed, 25 Sep 2019 09:09:57 +0200 Subject: fdts: stm32mp1: remove second QSPI flash instance Remove second flash node as only one must be used by QSPI NOR driver. Change-Id: I48189f2fdf4e0455aabe7d4cd9b2f3d36bb9cfb5 Signed-off-by: Lionel Debieve --- fdts/stm32mp157c-ev1.dts | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/fdts/stm32mp157c-ev1.dts b/fdts/stm32mp157c-ev1.dts index 51500fadb..50c0b939b 100644 --- a/fdts/stm32mp157c-ev1.dts +++ b/fdts/stm32mp157c-ev1.dts @@ -34,7 +34,7 @@ &qspi { pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; @@ -48,15 +48,6 @@ #address-cells = <1>; #size-cells = <1>; }; - - flash1: mx66l51235l@1 { - compatible = "jedec,spi-nor"; - reg = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; }; &usart3 { -- cgit v1.2.3 From ac7764bbcb366167436df9dd5c331755fbe2fc8f Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 17 Oct 2019 15:12:13 +0200 Subject: doc: stm32mp1: Update build command line Add new flags for storage support that must be used in the build command line. Add the complete build steps for an OP-TEE configuration. Signed-off-by: Lionel Debieve Change-Id: I0c682f6eb0aab83aa929f4ba734d3151c264aeed --- docs/plat/stm32mp1.rst | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst index 88251d6af..2c372a6a3 100644 --- a/docs/plat/stm32mp1.rst +++ b/docs/plat/stm32mp1.rst @@ -76,21 +76,34 @@ ROM code -> BL2 (compiled with BL2_AT_EL3) -> OP-TEE -> BL33 (U-Boot) Build Instructions ------------------ +Boot media(s) supported by BL2 must be specified in the build command. +Available storage medias are: +- ``STM32MP_SDMMC`` +- ``STM32MP_EMMC`` +- ``STM32MP_RAW_NAND`` +- ``STM32MP_SPI_NAND`` +- ``STM32MP_SPI_NOR`` -To build with SP_min: +To build with SP_min and support for all bootable devices: .. code:: bash - make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb + make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=sp_min STM32MP_SDMMC=1 STM32MP_EMMC=1 STM32MP_RAW_NAND=1 STM32MP_SPI_NAND=1 + STM32MP_SPI_NOR=1 DTB_FILE_NAME=stm32mp157c-ev1.dtb cd make stm32mp15_trusted_defconfig make DEVICE_TREE=stm32mp157c-ev1 all -To build TF-A with with Op-TEE support: - +To build TF-A with OP-TEE support for all bootable devices: .. code:: bash - make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=optee + make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=optee STM32MP_SDMMC=1 STM32MP_EMMC=1 STM32MP_RAW_NAND=1 STM32MP_SPI_NAND=1 STM32MP_SPI_NOR=1 DTB_FILE_NAME=stm32mp157c-ev1.dtb + cd + make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts + cd + make stm32mp15_optee_defconfig + make DEVICE_TREE=stm32mp157c-ev1 all + The following build options are supported: -- cgit v1.2.3 From ddb4c9e04cc5849dc035c9db382fc2d113df928f Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 27 Oct 2019 17:30:15 -0500 Subject: allwinner: Clean up MMU setup Remove the general BL31 mmap region: it duplicates the existing static mapping for the entire SRAM region. Use the helper definitions when applicable to simplify the code and add the MT_EXECUTE_NEVER flag. Signed-off-by: Samuel Holland Change-Id: I7a6b79e50e4b5c698774229530dd3d2a89e94a6d --- plat/allwinner/common/include/platform_def.h | 2 +- plat/allwinner/common/sunxi_common.c | 11 ++++------- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h index 0a0007667..4de8b0bc4 100644 --- a/plat/allwinner/common/include/platform_def.h +++ b/plat/allwinner/common/include/platform_def.h @@ -32,7 +32,7 @@ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) -#define MAX_MMAP_REGIONS (4 + PLATFORM_MMAP_REGIONS) +#define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) #define MAX_XLAT_TABLES 1 #define PLAT_MAX_PWR_LVL_STATES U(2) diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c index cff826819..3759c285e 100644 --- a/plat/allwinner/common/sunxi_common.c +++ b/plat/allwinner/common/sunxi_common.c @@ -20,15 +20,15 @@ static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, - MT_MEMORY | MT_RW | MT_SECURE), + MT_RW_DATA | MT_SECURE), MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), + MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, - MT_MEMORY | MT_RW | MT_SECURE), + MT_RW_DATA | MT_SECURE), MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET, SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE, SUNXI_DRAM_MAP_SIZE, - MT_MEMORY | MT_RO | MT_NS), + MT_RO_DATA | MT_NS), {}, }; @@ -48,9 +48,6 @@ uintptr_t plat_get_ns_image_entrypoint(void) void sunxi_configure_mmu_el3(int flags) { - mmap_add_region(BL31_BASE, BL31_BASE, - BL31_LIMIT - BL31_BASE, - MT_MEMORY | MT_RW | MT_SECURE); mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_SECURE); -- cgit v1.2.3 From 76d84cbc60ab3ee7bf40d53487f85ed7417bdcc3 Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Thu, 16 Jan 2020 22:21:33 -0600 Subject: Changes necessary to support SEPARATE_NOBITS_REGION feature Since BL31 PROGBITS and BL31 NOBITS sections are going to be in non-adjacent memory regions, potentially far from each other, some fixes are needed to support it completely. 1. adr instruction only allows computing the effective address of a location only within 1MB range of the PC. However, adrp instruction together with an add permits position independent address of any location with 4GB range of PC. 2. Since BL31 _RW_END_ marks the end of BL31 image, care must be taken that it is aligned to page size since we map this memory region in BL31 using xlat_v2 lib utils which mandate alignment of image size to page granularity. Change-Id: Ic745c5a130fe4239fa2742142d083b2bdc4e8b85 Signed-off-by: Madhukar Pappireddy --- bl31/aarch64/bl31_entrypoint.S | 14 +++++++++----- bl31/aarch64/runtime_exceptions.S | 5 +++-- bl31/bl31.ld.S | 3 ++- lib/el3_runtime/aarch64/cpu_data.S | 5 +++-- 4 files changed, 17 insertions(+), 10 deletions(-) diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 665a05e88..2d672dd12 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -110,13 +110,17 @@ func bl31_entrypoint * caches and participate in coherency. * -------------------------------------------------------------------- */ - adr x0, __DATA_START__ - adr x1, __DATA_END__ + adrp x0, __DATA_START__ + add x0, x0, :lo12:__DATA_START__ + adrp x1, __DATA_END__ + add x1, x1, :lo12:__DATA_END__ sub x1, x1, x0 bl clean_dcache_range - adr x0, __BSS_START__ - adr x1, __BSS_END__ + adrp x0, __BSS_START__ + add x0, x0, :lo12:__BSS_START__ + adrp x1, __BSS_END__ + add x1, x1, :lo12:__BSS_END__ sub x1, x1, x0 bl clean_dcache_range diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 51f5b7b34..1619914b8 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -414,7 +414,8 @@ smc_handler64: orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH /* Load descriptor index from array of indices */ - adr x14, rt_svc_descs_indices + adrp x14, rt_svc_descs_indices + add x14, x14, :lo12:rt_svc_descs_indices ldrb w15, [x14, x16] /* Any index greater than 127 is invalid. Check bit 7. */ diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 42227f0f3..86fe23608 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -208,6 +208,7 @@ SECTIONS * Define a linker symbol to mark end of the RW memory area for this * image. */ + . = ALIGN(PAGE_SIZE); __RW_END__ = .; __BL31_END__ = .; diff --git a/lib/el3_runtime/aarch64/cpu_data.S b/lib/el3_runtime/aarch64/cpu_data.S index 2edf22559..2392d6b90 100644 --- a/lib/el3_runtime/aarch64/cpu_data.S +++ b/lib/el3_runtime/aarch64/cpu_data.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,7 +41,8 @@ endfunc init_cpu_data_ptr func _cpu_data_by_index mov_imm x1, CPU_DATA_SIZE mul x0, x0, x1 - adr x1, percpu_data + adrp x1, percpu_data + add x1, x1, :lo12:percpu_data add x0, x0, x1 ret endfunc _cpu_data_by_index -- cgit v1.2.3 From d433bbdd459c222e5bf5ca87319807465b246d8c Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Thu, 16 Jan 2020 17:35:36 -0600 Subject: plat/arm: Add support for SEPARATE_NOBITS_REGION In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate the build to require that ARM_BL31_IN_DRAM is enabled as well. Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code cannot be reclaimed to be used for runtime data such as secondary cpu stacks. Memory map for BL31 NOBITS region also has to be created. Change-Id: Ibd480f82c1dc74e9cbb54eec07d7a8fecbf25433 Signed-off-by: Madhukar Pappireddy --- include/plat/arm/common/arm_def.h | 12 ++++++++++-- plat/arm/common/arm_bl31_setup.c | 13 ++++++++++++- plat/arm/common/arm_common.mk | 19 ++++++++++++++++++- 3 files changed, 40 insertions(+), 4 deletions(-) diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index b419c853e..5bd53f3b5 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -395,13 +395,21 @@ /******************************************************************************* * BL31 specific defines. ******************************************************************************/ -#if ARM_BL31_IN_DRAM +#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION /* * Put BL31 at the bottom of TZC secured DRAM */ #define BL31_BASE ARM_AP_TZC_DRAM1_BASE #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ PLAT_ARM_MAX_BL31_SIZE) +/* + * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. + * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. + */ +#if SEPARATE_NOBITS_REGION +#define BL31_NOBITS_BASE BL2_BASE +#define BL31_NOBITS_LIMIT BL2_LIMIT +#endif /* SEPARATE_NOBITS_REGION */ #elif (RESET_TO_BL31) /* Ensure Position Independent support (PIE) is enabled for this config.*/ # if !ENABLE_PIE diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index 939885f98..7a3ca7177 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -56,6 +56,14 @@ IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_INIT_CODE_END); MT_CODE | MT_SECURE) #endif +#if SEPARATE_NOBITS_REGION +#define MAP_BL31_NOBITS MAP_REGION_FLAT( \ + BL31_NOBITS_BASE, \ + BL31_NOBITS_LIMIT \ + - BL31_NOBITS_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#endif /******************************************************************************* * Return a pointer to the 'entry_point_info' structure of the next image for the * security state specified. BL33 corresponds to the non-secure image type @@ -294,6 +302,9 @@ void __init arm_bl31_plat_arch_setup(void) MAP_BL31_TOTAL, #if RECLAIM_INIT_CODE MAP_BL_INIT_CODE, +#endif +#if SEPARATE_NOBITS_REGION + MAP_BL31_NOBITS, #endif ARM_MAP_BL_RO, #if USE_ROMLIB diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 9d4f05e9e..ab33e1ded 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -125,6 +125,23 @@ ENABLE_PMF := 1 # mapping the former as executable and the latter as execute-never. SEPARATE_CODE_AND_RODATA := 1 +# On ARM platforms, disable SEPARATE_NOBITS_REGION by default. Both PROGBITS +# and NOBITS sections of BL31 image are adjacent to each other and loaded +# into Trusted SRAM. +SEPARATE_NOBITS_REGION := 0 + +# In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load +# BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate +# the build to require that ARM_BL31_IN_DRAM is enabled as well. +ifeq ($(SEPARATE_NOBITS_REGION),1) + ifneq ($(ARM_BL31_IN_DRAM),1) + $(error For SEPARATE_NOBITS_REGION, ARM_BL31_IN_DRAM must be enabled) + endif + ifneq ($(RECLAIM_INIT_CODE),0) + $(error For SEPARATE_NOBITS_REGION, RECLAIM_INIT_CODE cannot be supported) + endif +endif + # Disable ARM Cryptocell by default ARM_CRYPTOCELL_INTEG := 0 $(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG)) -- cgit v1.2.3 From feb358b65151f7c4d6656a4ee52199f205798ce8 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 16 Sep 2019 16:50:57 +0100 Subject: FDT helper functions: Fix MISRA issues Moving the FDT helper functions to the common/ directory exposed the file to MISRA checking, which is mandatory for common code. Fix the complaints that the test suite reported. Change-Id: Ica8c8a95218bba5a3fd92a55407de24df58e8476 Signed-off-by: Andre Przywara --- common/fdt_fixup.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/common/fdt_fixup.c b/common/fdt_fixup.c index 99d0eee98..d518eb2a4 100644 --- a/common/fdt_fixup.c +++ b/common/fdt_fixup.c @@ -95,7 +95,7 @@ int dt_add_psci_node(void *fdt) * or none have to be patched in the first place. * Returns 1 if *one* such subnode has been found and successfully changed * to "psci". - * Returns -1 on error. + * Returns negative values on error. * * Call in a loop until it returns 0. Recalculate the node offset after * it has returned 1. @@ -109,20 +109,23 @@ static int dt_update_one_cpu_node(void *fdt, int offset) offs = fdt_next_subnode(fdt, offs)) { const char *prop; int len; + int ret; prop = fdt_getprop(fdt, offs, "device_type", &len); - if (!prop) + if (prop == NULL) continue; - if (memcmp(prop, "cpu", 4) != 0 || len != 4) + if ((strcmp(prop, "cpu") != 0) || (len != 4)) continue; /* Ignore any nodes which already use "psci". */ prop = fdt_getprop(fdt, offs, "enable-method", &len); - if (prop && memcmp(prop, "psci", 5) == 0 && len == 5) + if ((prop != NULL) && + (strcmp(prop, "psci") == 0) && (len == 5)) continue; - if (fdt_setprop_string(fdt, offs, "enable-method", "psci")) - return -1; + ret = fdt_setprop_string(fdt, offs, "enable-method", "psci"); + if (ret < 0) + return ret; /* * Subnode found and patched. * Restart to accommodate potentially changed offsets. -- cgit v1.2.3 From c3fc368a5a3c0f05ea7258582ff15391ade5dbd5 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 26 Dec 2019 17:58:52 +0900 Subject: xlat_tables_v2: simplify end address checks in mmap_add_region_check() Use end_va and end_pa defined at the beginning of this function. Change-Id: I0e8b3b35fceb87b5d35397eb892d4fe92ba90b4c Signed-off-by: Masahiro Yamada --- lib/xlat_tables_v2/xlat_tables_core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c index 3c0865b81..b2259e5f3 100644 --- a/lib/xlat_tables_v2/xlat_tables_core.c +++ b/lib/xlat_tables_v2/xlat_tables_core.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -688,10 +688,10 @@ static int mmap_add_region_check(const xlat_ctx_t *ctx, const mmap_region_t *mm) if ((base_pa > end_pa) || (base_va > end_va)) return -ERANGE; - if ((base_va + (uintptr_t)size - (uintptr_t)1) > ctx->va_max_address) + if (end_va > ctx->va_max_address) return -ERANGE; - if ((base_pa + (unsigned long long)size - 1ULL) > ctx->pa_max_address) + if (end_pa > ctx->pa_max_address) return -ERANGE; /* Check that there is space in the ctx->mmap array */ -- cgit v1.2.3 From 67878cb0e5e6bb7fa62499491dc4f0adc6a6a3f7 Mon Sep 17 00:00:00 2001 From: Norbert Werner Date: Sun, 19 Jan 2020 14:51:01 +0100 Subject: Xilinx zynqmp: add missing pin control group for ethernet 0. Signed-off-by: Norbert Werner Change-Id: I3264515e5901689328861964ff664ff08b6e852c --- plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c index a900057e8..4b8dfb614 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -1477,6 +1477,7 @@ static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = { }, [PINCTRL_PIN_26] = { .groups = &((uint16_t []) { + PINCTRL_GRP_ETHERNET0_0, PINCTRL_GRP_GEMTSU0_0, PINCTRL_GRP_NAND0_1_CE, PINCTRL_GRP_PMU0_0, -- cgit v1.2.3 From 7949041f589f92fecfb215859e308f15f26079ff Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Wed, 22 Jan 2020 10:05:59 -0600 Subject: Ignore the ctags file Signed-off-by: Deepika Bhavnani Change-Id: Ic78bda00aba0e350095c3dcd59f688f4a27ed1d4 --- .gitignore | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.gitignore b/.gitignore index 2abfffb40..64b389b12 100644 --- a/.gitignore +++ b/.gitignore @@ -34,3 +34,7 @@ GPATH GRTAGS GSYMS GTAGS + +# Ctags +tags + -- cgit v1.2.3 From f461fe346b728d0e88142fd7b8f2816415af18bc Mon Sep 17 00:00:00 2001 From: Anthony Steinhauser Date: Tue, 7 Jan 2020 15:44:06 -0800 Subject: Prevent speculative execution past ERET Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS: https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8 https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61 https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2 https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f --- bl1/aarch64/bl1_exceptions.S | 4 ++-- bl2/aarch64/bl2_el3_entrypoint.S | 4 ++-- bl31/aarch64/runtime_exceptions.S | 2 +- bl32/tsp/aarch64/tsp_exceptions.S | 4 ++-- include/arch/aarch64/asm_macros.S | 11 ++++++++++- lib/cpus/aarch64/cortex_a76.S | 4 ++-- lib/cpus/aarch64/neoverse_n1.S | 4 ++-- lib/cpus/aarch64/wa_cve_2017_5715_mmu.S | 4 ++-- lib/el3_runtime/aarch64/context.S | 2 +- plat/renesas/rcar/aarch64/plat_helpers.S | 4 ++-- services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S | 4 ++-- 11 files changed, 28 insertions(+), 19 deletions(-) diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index 9bba6eef3..9dc9e6cd5 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -202,7 +202,7 @@ debug_loop: ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] - eret + exception_return endfunc smc_handler64 unexpected_sync_exception: diff --git a/bl2/aarch64/bl2_el3_entrypoint.S b/bl2/aarch64/bl2_el3_entrypoint.S index f97121ef0..2ca6acf28 100644 --- a/bl2/aarch64/bl2_el3_entrypoint.S +++ b/bl2/aarch64/bl2_el3_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -95,5 +95,5 @@ func bl2_run_next_image ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] - eret + exception_return endfunc bl2_run_next_image diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 51f5b7b34..7f739a9aa 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -456,7 +456,7 @@ smc_unknown: smc_prohibited: ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] mov x0, #SMC_UNK - eret + exception_return #if DEBUG rt_svc_fw_critical_error: diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S index ad4b64887..4c6a56a59 100644 --- a/bl32/tsp/aarch64/tsp_exceptions.S +++ b/bl32/tsp/aarch64/tsp_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,7 +64,7 @@ smc #0 interrupt_exit_\label: restore_caller_regs_and_lr - eret + exception_return .endm .globl tsp_exceptions diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S index 79e0ad7f3..a7d5a3dd6 100644 --- a/include/arch/aarch64/asm_macros.S +++ b/include/arch/aarch64/asm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -218,4 +218,13 @@ ret .endm + /* + * Macro for mitigating against speculative execution beyond ERET. + */ + .macro exception_return + eret + dsb nsh + isb + .endm + #endif /* ASM_MACROS_S */ diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 868667ebc..baefa4676 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -85,7 +85,7 @@ bic x3, x2, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE csel x3, x3, x1, eq msr CORTEX_A76_CPUACTLR2_EL1, x3 - eret /* ERET implies ISB */ + exception_return /* exception_return contains ISB */ .endif 1: /* diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index faf53a848..d058d98df 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -553,7 +553,7 @@ func neoverse_n1_errata_ic_trap_handler */ esb #endif - eret + exception_return 1: ret endfunc neoverse_n1_errata_ic_trap_handler diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S index 9277cc624..5134ee3f1 100644 --- a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S +++ b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -48,7 +48,7 @@ vector_base wa_cve_2017_5715_mmu_vbar ccmp w0, w1, #0, eq /* Static predictor will predict a fall through */ bne 1f - eret + exception_return 1: .endif diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 1bbd61005..9bd25bac9 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -534,6 +534,6 @@ func el3_exit */ esb #endif - eret + exception_return endfunc el3_exit diff --git a/plat/renesas/rcar/aarch64/plat_helpers.S b/plat/renesas/rcar/aarch64/plat_helpers.S index 61dd62287..138d98807 100644 --- a/plat/renesas/rcar/aarch64/plat_helpers.S +++ b/plat/renesas/rcar/aarch64/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -189,7 +189,7 @@ func bl2_enter_bl31 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] msr elr_el3, x0 msr spsr_el3, x1 - eret + exception_return endfunc bl2_enter_bl31 /* ----------------------------------------------------- diff --git a/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S b/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S index dab615012..be4084cfb 100644 --- a/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S +++ b/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -87,7 +87,7 @@ vector_entry SynchronousExceptionA64, .spm_shim_exceptions do_smc: mrs x30, tpidr_el1 smc #0 - eret + exception_return /* AArch64 system instructions trap are handled as a panic for now */ handle_sys_trap: -- cgit v1.2.3 From 3b5454efacb481817efee8ac3bbd6d20cdd50153 Mon Sep 17 00:00:00 2001 From: Mark Dykes Date: Wed, 22 Jan 2020 21:52:44 +0000 Subject: Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature" This reverts commit 76d84cbc60ab3ee7bf40d53487f85ed7417bdcc3. Change-Id: I867af7af3d9f5e568101f79b9ebea578e5cb2a4b --- bl31/aarch64/bl31_entrypoint.S | 14 +++++--------- bl31/aarch64/runtime_exceptions.S | 5 ++--- bl31/bl31.ld.S | 3 +-- lib/el3_runtime/aarch64/cpu_data.S | 5 ++--- 4 files changed, 10 insertions(+), 17 deletions(-) diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 2d672dd12..665a05e88 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -110,17 +110,13 @@ func bl31_entrypoint * caches and participate in coherency. * -------------------------------------------------------------------- */ - adrp x0, __DATA_START__ - add x0, x0, :lo12:__DATA_START__ - adrp x1, __DATA_END__ - add x1, x1, :lo12:__DATA_END__ + adr x0, __DATA_START__ + adr x1, __DATA_END__ sub x1, x1, x0 bl clean_dcache_range - adrp x0, __BSS_START__ - add x0, x0, :lo12:__BSS_START__ - adrp x1, __BSS_END__ - add x1, x1, :lo12:__BSS_END__ + adr x0, __BSS_START__ + adr x1, __BSS_END__ sub x1, x1, x0 bl clean_dcache_range diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 1619914b8..51f5b7b34 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -414,8 +414,7 @@ smc_handler64: orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH /* Load descriptor index from array of indices */ - adrp x14, rt_svc_descs_indices - add x14, x14, :lo12:rt_svc_descs_indices + adr x14, rt_svc_descs_indices ldrb w15, [x14, x16] /* Any index greater than 127 is invalid. Check bit 7. */ diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 86fe23608..42227f0f3 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -208,7 +208,6 @@ SECTIONS * Define a linker symbol to mark end of the RW memory area for this * image. */ - . = ALIGN(PAGE_SIZE); __RW_END__ = .; __BL31_END__ = .; diff --git a/lib/el3_runtime/aarch64/cpu_data.S b/lib/el3_runtime/aarch64/cpu_data.S index 2392d6b90..2edf22559 100644 --- a/lib/el3_runtime/aarch64/cpu_data.S +++ b/lib/el3_runtime/aarch64/cpu_data.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,8 +41,7 @@ endfunc init_cpu_data_ptr func _cpu_data_by_index mov_imm x1, CPU_DATA_SIZE mul x0, x0, x1 - adrp x1, percpu_data - add x1, x1, :lo12:percpu_data + adr x1, percpu_data add x0, x0, x1 ret endfunc _cpu_data_by_index -- cgit v1.2.3 From 4d9f825a5616e15975abc0e8ffef4fd8afe09634 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Tue, 7 Jan 2020 03:25:16 -0700 Subject: xilinx: common: Move ATF handover to common file ATF handover can be used by Xilinx platforms, so move it to common file from platform specific files. Signed-off-by: Venkatesh Yadav Abbarapu Change-Id: I5f0839351f534619de581d1953c8427a079487e0 --- plat/xilinx/common/include/plat_startup.h | 22 +++ plat/xilinx/common/plat_startup.c | 270 +++++++++++++++++++++++++++++ plat/xilinx/zynqmp/bl31_zynqmp_setup.c | 11 +- plat/xilinx/zynqmp/include/plat_private.h | 12 +- plat/xilinx/zynqmp/plat_startup.c | 272 ------------------------------ plat/xilinx/zynqmp/platform.mk | 2 +- 6 files changed, 303 insertions(+), 286 deletions(-) create mode 100644 plat/xilinx/common/include/plat_startup.h create mode 100644 plat/xilinx/common/plat_startup.c delete mode 100644 plat/xilinx/zynqmp/plat_startup.c diff --git a/plat/xilinx/common/include/plat_startup.h b/plat/xilinx/common/include/plat_startup.h new file mode 100644 index 000000000..66e793373 --- /dev/null +++ b/plat/xilinx/common/include/plat_startup.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_STARTUP_H +#define PLAT_STARTUP_H + +/* For FSBL handover */ +enum fsbl_handoff { + FSBL_HANDOFF_SUCCESS = 0, + FSBL_HANDOFF_NO_STRUCT, + FSBL_HANDOFF_INVAL_STRUCT, + FSBL_HANDOFF_TOO_MANY_PARTS +}; + +enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32_image_ep_info, + entry_point_info_t *bl33_image_ep_info, + uint64_t atf_handoff_addr); + +#endif /* PLAT_STARTUP_H */ diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c new file mode 100644 index 000000000..8c9a049dd --- /dev/null +++ b/plat/xilinx/common/plat_startup.c @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + + +/* + * ATFHandoffParams + * Parameter bitfield encoding + * ----------------------------------------------------------------------------- + * Exec State 0 0 -> Aarch64, 1-> Aarch32 + * endianness 1 0 -> LE, 1 -> BE + * secure (TZ) 2 0 -> Non secure, 1 -> secure + * EL 3:4 00 -> EL0, 01 -> EL1, 10 -> EL2, 11 -> EL3 + * CPU# 5:6 00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3 + */ + +#define FSBL_FLAGS_ESTATE_SHIFT 0 +#define FSBL_FLAGS_ESTATE_MASK (1 << FSBL_FLAGS_ESTATE_SHIFT) +#define FSBL_FLAGS_ESTATE_A64 0 +#define FSBL_FLAGS_ESTATE_A32 1 + +#define FSBL_FLAGS_ENDIAN_SHIFT 1 +#define FSBL_FLAGS_ENDIAN_MASK (1 << FSBL_FLAGS_ENDIAN_SHIFT) +#define FSBL_FLAGS_ENDIAN_LE 0 +#define FSBL_FLAGS_ENDIAN_BE 1 + +#define FSBL_FLAGS_TZ_SHIFT 2 +#define FSBL_FLAGS_TZ_MASK (1 << FSBL_FLAGS_TZ_SHIFT) +#define FSBL_FLAGS_NON_SECURE 0 +#define FSBL_FLAGS_SECURE 1 + +#define FSBL_FLAGS_EL_SHIFT 3 +#define FSBL_FLAGS_EL_MASK (3 << FSBL_FLAGS_EL_SHIFT) +#define FSBL_FLAGS_EL0 0 +#define FSBL_FLAGS_EL1 1 +#define FSBL_FLAGS_EL2 2 +#define FSBL_FLAGS_EL3 3 + +#define FSBL_FLAGS_CPU_SHIFT 5 +#define FSBL_FLAGS_CPU_MASK (3 << FSBL_FLAGS_CPU_SHIFT) +#define FSBL_FLAGS_A53_0 0 +#define FSBL_FLAGS_A53_1 1 +#define FSBL_FLAGS_A53_2 2 +#define FSBL_FLAGS_A53_3 3 + +#define FSBL_MAX_PARTITIONS 8 + +/* Structure corresponding to each partition entry */ +struct xfsbl_partition { + uint64_t entry_point; + uint64_t flags; +}; + +/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */ +struct xfsbl_atf_handoff_params { + uint8_t magic[4]; + uint32_t num_entries; + struct xfsbl_partition partition[FSBL_MAX_PARTITIONS]; +}; + +/** + * @partition: Pointer to partition struct + * + * Get the target CPU for @partition. + * + * Return: FSBL_FLAGS_A53_0, FSBL_FLAGS_A53_1, FSBL_FLAGS_A53_2 or FSBL_FLAGS_A53_3 + */ +static int get_fsbl_cpu(const struct xfsbl_partition *partition) +{ + uint64_t flags = partition->flags & FSBL_FLAGS_CPU_MASK; + + return flags >> FSBL_FLAGS_CPU_SHIFT; +} + +/** + * @partition: Pointer to partition struct + * + * Get the target exception level for @partition. + * + * Return: FSBL_FLAGS_EL0, FSBL_FLAGS_EL1, FSBL_FLAGS_EL2 or FSBL_FLAGS_EL3 + */ +static int get_fsbl_el(const struct xfsbl_partition *partition) +{ + uint64_t flags = partition->flags & FSBL_FLAGS_EL_MASK; + + return flags >> FSBL_FLAGS_EL_SHIFT; +} + +/** + * @partition: Pointer to partition struct + * + * Get the target security state for @partition. + * + * Return: FSBL_FLAGS_NON_SECURE or FSBL_FLAGS_SECURE + */ +static int get_fsbl_ss(const struct xfsbl_partition *partition) +{ + uint64_t flags = partition->flags & FSBL_FLAGS_TZ_MASK; + + return flags >> FSBL_FLAGS_TZ_SHIFT; +} + +/** + * @partition: Pointer to partition struct + * + * Get the target endianness for @partition. + * + * Return: SPSR_E_LITTLE or SPSR_E_BIG + */ +static int get_fsbl_endian(const struct xfsbl_partition *partition) +{ + uint64_t flags = partition->flags & FSBL_FLAGS_ENDIAN_MASK; + + flags >>= FSBL_FLAGS_ENDIAN_SHIFT; + + if (flags == FSBL_FLAGS_ENDIAN_BE) + return SPSR_E_BIG; + else + return SPSR_E_LITTLE; +} + +/** + * @partition: Pointer to partition struct + * + * Get the target execution state for @partition. + * + * Return: FSBL_FLAGS_ESTATE_A32 or FSBL_FLAGS_ESTATE_A64 + */ +static int get_fsbl_estate(const struct xfsbl_partition *partition) +{ + uint64_t flags = partition->flags & FSBL_FLAGS_ESTATE_MASK; + + return flags >> FSBL_FLAGS_ESTATE_SHIFT; +} + +/** + * Populates the bl32 and bl33 image info structures + * @bl32: BL32 image info structure + * @bl33: BL33 image info structure + * atf_handoff_addr: ATF handoff address + * + * Process the handoff paramters from the FSBL and populate the BL32 and BL33 + * image info structures accordingly. + * + * Return: Return the status of the handoff. The value will be from the + * fsbl_handoff enum. + */ +enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32, + entry_point_info_t *bl33, + uint64_t atf_handoff_addr) +{ + const struct xfsbl_atf_handoff_params *ATFHandoffParams; + assert((atf_handoff_addr < BL31_BASE) || + (atf_handoff_addr > (uint64_t)&__BL31_END__)); + if (!atf_handoff_addr) { + WARN("BL31: No ATF handoff structure passed\n"); + return FSBL_HANDOFF_NO_STRUCT; + } + + ATFHandoffParams = (struct xfsbl_atf_handoff_params *)atf_handoff_addr; + if ((ATFHandoffParams->magic[0] != 'X') || + (ATFHandoffParams->magic[1] != 'L') || + (ATFHandoffParams->magic[2] != 'N') || + (ATFHandoffParams->magic[3] != 'X')) { + ERROR("BL31: invalid ATF handoff structure at %llx\n", + atf_handoff_addr); + return FSBL_HANDOFF_INVAL_STRUCT; + } + + VERBOSE("BL31: ATF handoff params at:0x%llx, entries:%u\n", + atf_handoff_addr, ATFHandoffParams->num_entries); + if (ATFHandoffParams->num_entries > FSBL_MAX_PARTITIONS) { + ERROR("BL31: ATF handoff params: too many partitions (%u/%u)\n", + ATFHandoffParams->num_entries, FSBL_MAX_PARTITIONS); + return FSBL_HANDOFF_TOO_MANY_PARTS; + } + + /* + * we loop over all passed entries but only populate two image structs + * (bl32, bl33). I.e. the last applicable images in the handoff + * structure will be used for the hand off + */ + for (size_t i = 0; i < ATFHandoffParams->num_entries; i++) { + entry_point_info_t *image; + int target_estate, target_secure; + int target_cpu, target_endianness, target_el; + + VERBOSE("BL31: %zd: entry:0x%llx, flags:0x%llx\n", i, + ATFHandoffParams->partition[i].entry_point, + ATFHandoffParams->partition[i].flags); + + target_cpu = get_fsbl_cpu(&ATFHandoffParams->partition[i]); + if (target_cpu != FSBL_FLAGS_A53_0) { + WARN("BL31: invalid target CPU (%i)\n", target_cpu); + continue; + } + + target_el = get_fsbl_el(&ATFHandoffParams->partition[i]); + if ((target_el == FSBL_FLAGS_EL3) || + (target_el == FSBL_FLAGS_EL0)) { + WARN("BL31: invalid exception level (%i)\n", target_el); + continue; + } + + target_secure = get_fsbl_ss(&ATFHandoffParams->partition[i]); + if (target_secure == FSBL_FLAGS_SECURE && + target_el == FSBL_FLAGS_EL2) { + WARN("BL31: invalid security state (%i) for exception level (%i)\n", + target_secure, target_el); + continue; + } + + target_estate = get_fsbl_estate(&ATFHandoffParams->partition[i]); + target_endianness = get_fsbl_endian(&ATFHandoffParams->partition[i]); + + if (target_secure == FSBL_FLAGS_SECURE) { + image = bl32; + + if (target_estate == FSBL_FLAGS_ESTATE_A32) + bl32->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, + target_endianness, + DISABLE_ALL_EXCEPTIONS); + else + bl32->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + } else { + image = bl33; + + if (target_estate == FSBL_FLAGS_ESTATE_A32) { + if (target_el == FSBL_FLAGS_EL2) + target_el = MODE32_hyp; + else + target_el = MODE32_sys; + + bl33->spsr = SPSR_MODE32(target_el, SPSR_T_ARM, + target_endianness, + DISABLE_ALL_EXCEPTIONS); + } else { + if (target_el == FSBL_FLAGS_EL2) + target_el = MODE_EL2; + else + target_el = MODE_EL1; + + bl33->spsr = SPSR_64(target_el, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + } + } + + VERBOSE("Setting up %s entry point to:%llx, el:%x\n", + target_secure == FSBL_FLAGS_SECURE ? "BL32" : "BL33", + ATFHandoffParams->partition[i].entry_point, + target_el); + image->pc = ATFHandoffParams->partition[i].entry_point; + + if (target_endianness == SPSR_E_BIG) + EP_SET_EE(image->h.attr, EP_EE_BIG); + else + EP_SET_EE(image->h.attr, EP_EE_LITTLE); + } + + return FSBL_HANDOFF_SUCCESS; +} diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index 285a4eb8b..6e0e811d4 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,8 +13,11 @@ #include #include #include +#include +#include #include +#include static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; @@ -57,6 +60,7 @@ static inline void bl31_set_default_config(void) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { + uint64_t atf_handoff_addr; /* Register the console to provide early debug support */ static console_cdns_t bl31_boot_console; (void)console_cdns_register(ZYNQMP_UART_BASE, @@ -86,12 +90,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); + if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { bl31_set_default_config(); } else { /* use parameters from FSBL */ enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, - &bl33_image_ep_info); + &bl33_image_ep_info, + atf_handoff_addr); if (ret == FSBL_HANDOFF_NO_STRUCT) bl31_set_default_config(); else if (ret != FSBL_HANDOFF_SUCCESS) diff --git a/plat/xilinx/zynqmp/include/plat_private.h b/plat/xilinx/zynqmp/include/plat_private.h index 8bdf42967..288cc5301 100644 --- a/plat/xilinx/zynqmp/include/plat_private.h +++ b/plat/xilinx/zynqmp/include/plat_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,13 +21,6 @@ unsigned int zynqmp_calc_core_pos(u_register_t mpidr); unsigned int zynqmp_get_uart_clk(void); unsigned int zynqmp_get_bootmode(void); -/* For FSBL handover */ -enum fsbl_handoff { - FSBL_HANDOFF_SUCCESS = 0, - FSBL_HANDOFF_NO_STRUCT, - FSBL_HANDOFF_INVAL_STRUCT, - FSBL_HANDOFF_TOO_MANY_PARTS, -}; #if ZYNQMP_WDT_RESTART /* @@ -37,7 +30,4 @@ enum fsbl_handoff { int request_intr_type_el3(uint32_t, interrupt_type_handler_t); #endif -enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32_image_ep_info, - entry_point_info_t *bl33_image_ep_info); - #endif /* PLAT_PRIVATE_H */ diff --git a/plat/xilinx/zynqmp/plat_startup.c b/plat/xilinx/zynqmp/plat_startup.c deleted file mode 100644 index cd2c3bac6..000000000 --- a/plat/xilinx/zynqmp/plat_startup.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include -#include - -#include "zynqmp_def.h" - -/* - * ATFHandoffParams - * Parameter bitfield encoding - * ----------------------------------------------------------------------------- - * Exec State 0 0 -> Aarch64, 1-> Aarch32 - * endianness 1 0 -> LE, 1 -> BE - * secure (TZ) 2 0 -> Non secure, 1 -> secure - * EL 3:4 00 -> EL0, 01 -> EL1, 10 -> EL2, 11 -> EL3 - * CPU# 5:6 00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3 - */ - -#define FSBL_FLAGS_ESTATE_SHIFT 0 -#define FSBL_FLAGS_ESTATE_MASK (1 << FSBL_FLAGS_ESTATE_SHIFT) -#define FSBL_FLAGS_ESTATE_A64 0 -#define FSBL_FLAGS_ESTATE_A32 1 - -#define FSBL_FLAGS_ENDIAN_SHIFT 1 -#define FSBL_FLAGS_ENDIAN_MASK (1 << FSBL_FLAGS_ENDIAN_SHIFT) -#define FSBL_FLAGS_ENDIAN_LE 0 -#define FSBL_FLAGS_ENDIAN_BE 1 - -#define FSBL_FLAGS_TZ_SHIFT 2 -#define FSBL_FLAGS_TZ_MASK (1 << FSBL_FLAGS_TZ_SHIFT) -#define FSBL_FLAGS_NON_SECURE 0 -#define FSBL_FLAGS_SECURE 1 - -#define FSBL_FLAGS_EL_SHIFT 3 -#define FSBL_FLAGS_EL_MASK (3 << FSBL_FLAGS_EL_SHIFT) -#define FSBL_FLAGS_EL0 0 -#define FSBL_FLAGS_EL1 1 -#define FSBL_FLAGS_EL2 2 -#define FSBL_FLAGS_EL3 3 - -#define FSBL_FLAGS_CPU_SHIFT 5 -#define FSBL_FLAGS_CPU_MASK (3 << FSBL_FLAGS_CPU_SHIFT) -#define FSBL_FLAGS_A53_0 0 -#define FSBL_FLAGS_A53_1 1 -#define FSBL_FLAGS_A53_2 2 -#define FSBL_FLAGS_A53_3 3 - -#define FSBL_MAX_PARTITIONS 8 - -/* Structure corresponding to each partition entry */ -struct xfsbl_partition { - uint64_t entry_point; - uint64_t flags; -}; - -/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */ -struct xfsbl_atf_handoff_params { - uint8_t magic[4]; - uint32_t num_entries; - struct xfsbl_partition partition[FSBL_MAX_PARTITIONS]; -}; - -/** - * @partition: Pointer to partition struct - * - * Get the target CPU for @partition. - * - * Return: FSBL_FLAGS_A53_0, FSBL_FLAGS_A53_1, FSBL_FLAGS_A53_2 or FSBL_FLAGS_A53_3 - */ -static int get_fsbl_cpu(const struct xfsbl_partition *partition) -{ - uint64_t flags = partition->flags & FSBL_FLAGS_CPU_MASK; - - return flags >> FSBL_FLAGS_CPU_SHIFT; -} - -/** - * @partition: Pointer to partition struct - * - * Get the target exception level for @partition. - * - * Return: FSBL_FLAGS_EL0, FSBL_FLAGS_EL1, FSBL_FLAGS_EL2 or FSBL_FLAGS_EL3 - */ -static int get_fsbl_el(const struct xfsbl_partition *partition) -{ - uint64_t flags = partition->flags & FSBL_FLAGS_EL_MASK; - - return flags >> FSBL_FLAGS_EL_SHIFT; -} - -/** - * @partition: Pointer to partition struct - * - * Get the target security state for @partition. - * - * Return: FSBL_FLAGS_NON_SECURE or FSBL_FLAGS_SECURE - */ -static int get_fsbl_ss(const struct xfsbl_partition *partition) -{ - uint64_t flags = partition->flags & FSBL_FLAGS_TZ_MASK; - - return flags >> FSBL_FLAGS_TZ_SHIFT; -} - -/** - * @partition: Pointer to partition struct - * - * Get the target endianness for @partition. - * - * Return: SPSR_E_LITTLE or SPSR_E_BIG - */ -static int get_fsbl_endian(const struct xfsbl_partition *partition) -{ - uint64_t flags = partition->flags & FSBL_FLAGS_ENDIAN_MASK; - - flags >>= FSBL_FLAGS_ENDIAN_SHIFT; - - if (flags == FSBL_FLAGS_ENDIAN_BE) - return SPSR_E_BIG; - else - return SPSR_E_LITTLE; -} - -/** - * @partition: Pointer to partition struct - * - * Get the target execution state for @partition. - * - * Return: FSBL_FLAGS_ESTATE_A32 or FSBL_FLAGS_ESTATE_A64 - */ -static int get_fsbl_estate(const struct xfsbl_partition *partition) -{ - uint64_t flags = partition->flags & FSBL_FLAGS_ESTATE_MASK; - - return flags >> FSBL_FLAGS_ESTATE_SHIFT; -} - -/** - * Populates the bl32 and bl33 image info structures - * @bl32: BL32 image info structure - * @bl33: BL33 image info structure - * - * Process the handoff paramters from the FSBL and populate the BL32 and BL33 - * image info structures accordingly. - * - * Return: Return the status of the handoff. The value will be from the - * fsbl_handoff enum. - */ -enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32, entry_point_info_t *bl33) -{ - uint64_t atf_handoff_addr; - const struct xfsbl_atf_handoff_params *ATFHandoffParams; - - atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); - assert((atf_handoff_addr < BL31_BASE) || - (atf_handoff_addr > (uint64_t)&__BL31_END__)); - if (!atf_handoff_addr) { - WARN("BL31: No ATF handoff structure passed\n"); - return FSBL_HANDOFF_NO_STRUCT; - } - - ATFHandoffParams = (struct xfsbl_atf_handoff_params *)atf_handoff_addr; - if ((ATFHandoffParams->magic[0] != 'X') || - (ATFHandoffParams->magic[1] != 'L') || - (ATFHandoffParams->magic[2] != 'N') || - (ATFHandoffParams->magic[3] != 'X')) { - ERROR("BL31: invalid ATF handoff structure at %llx\n", - atf_handoff_addr); - return FSBL_HANDOFF_INVAL_STRUCT; - } - - VERBOSE("BL31: ATF handoff params at:0x%llx, entries:%u\n", - atf_handoff_addr, ATFHandoffParams->num_entries); - if (ATFHandoffParams->num_entries > FSBL_MAX_PARTITIONS) { - ERROR("BL31: ATF handoff params: too many partitions (%u/%u)\n", - ATFHandoffParams->num_entries, FSBL_MAX_PARTITIONS); - return FSBL_HANDOFF_TOO_MANY_PARTS; - } - - /* - * we loop over all passed entries but only populate two image structs - * (bl32, bl33). I.e. the last applicable images in the handoff - * structure will be used for the hand off - */ - for (size_t i = 0; i < ATFHandoffParams->num_entries; i++) { - entry_point_info_t *image; - int target_estate, target_secure; - int target_cpu, target_endianness, target_el; - - VERBOSE("BL31: %zd: entry:0x%llx, flags:0x%llx\n", i, - ATFHandoffParams->partition[i].entry_point, - ATFHandoffParams->partition[i].flags); - - target_cpu = get_fsbl_cpu(&ATFHandoffParams->partition[i]); - if (target_cpu != FSBL_FLAGS_A53_0) { - WARN("BL31: invalid target CPU (%i)\n", target_cpu); - continue; - } - - target_el = get_fsbl_el(&ATFHandoffParams->partition[i]); - if ((target_el == FSBL_FLAGS_EL3) || - (target_el == FSBL_FLAGS_EL0)) { - WARN("BL31: invalid exception level (%i)\n", target_el); - continue; - } - - target_secure = get_fsbl_ss(&ATFHandoffParams->partition[i]); - if (target_secure == FSBL_FLAGS_SECURE && - target_el == FSBL_FLAGS_EL2) { - WARN("BL31: invalid security state (%i) for exception level (%i)\n", - target_secure, target_el); - continue; - } - - target_estate = get_fsbl_estate(&ATFHandoffParams->partition[i]); - target_endianness = get_fsbl_endian(&ATFHandoffParams->partition[i]); - - if (target_secure == FSBL_FLAGS_SECURE) { - image = bl32; - - if (target_estate == FSBL_FLAGS_ESTATE_A32) - bl32->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, - target_endianness, - DISABLE_ALL_EXCEPTIONS); - else - bl32->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); - } else { - image = bl33; - - if (target_estate == FSBL_FLAGS_ESTATE_A32) { - if (target_el == FSBL_FLAGS_EL2) - target_el = MODE32_hyp; - else - target_el = MODE32_sys; - - bl33->spsr = SPSR_MODE32(target_el, SPSR_T_ARM, - target_endianness, - DISABLE_ALL_EXCEPTIONS); - } else { - if (target_el == FSBL_FLAGS_EL2) - target_el = MODE_EL2; - else - target_el = MODE_EL1; - - bl33->spsr = SPSR_64(target_el, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); - } - } - - VERBOSE("Setting up %s entry point to:%llx, el:%x\n", - target_secure == FSBL_FLAGS_SECURE ? "BL32" : "BL33", - ATFHandoffParams->partition[i].entry_point, - target_el); - image->pc = ATFHandoffParams->partition[i].entry_point; - - if (target_endianness == SPSR_E_BIG) - EP_SET_EE(image->h.attr, EP_EE_BIG); - else - EP_SET_EE(image->h.attr, EP_EE_LITTLE); - } - - return FSBL_HANDOFF_SUCCESS; -} diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index de4bf3a0b..44f20f69f 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -82,10 +82,10 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ plat/common/plat_psci_common.c \ plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ plat/xilinx/common/pm_service/pm_ipi.c \ + plat/xilinx/common/plat_startup.c \ plat/xilinx/zynqmp/bl31_zynqmp_setup.c \ plat/xilinx/zynqmp/plat_psci.c \ plat/xilinx/zynqmp/plat_zynqmp.c \ - plat/xilinx/zynqmp/plat_startup.c \ plat/xilinx/zynqmp/plat_topology.c \ plat/xilinx/zynqmp/sip_svc_setup.c \ plat/xilinx/zynqmp/pm_service/pm_svc_main.c \ -- cgit v1.2.3 From 31ce893ec29197c51e3814648ad0dd2acf4a31a7 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Wed, 22 Jan 2020 21:23:20 -0700 Subject: xilinx: versal: PLM to ATF handover Parse the parameter structure the PLM populates, to populate the bl32 and bl33 image structures. Signed-off-by: Venkatesh Yadav Abbarapu Change-Id: I317072d1086f6cc6f90883c1b8b6d086ff57b443 --- docs/plat/xilinx-versal.rst | 8 +++++++ plat/xilinx/versal/aarch64/versal_common.c | 10 +-------- plat/xilinx/versal/bl31_versal_setup.c | 34 ++++++++++++++++++++++++------ plat/xilinx/versal/include/platform_def.h | 6 +++--- plat/xilinx/versal/include/versal_def.h | 6 +++++- plat/xilinx/versal/platform.mk | 4 +++- 6 files changed, 47 insertions(+), 21 deletions(-) diff --git a/docs/plat/xilinx-versal.rst b/docs/plat/xilinx-versal.rst index 95c89a8b2..57a363bc9 100644 --- a/docs/plat/xilinx-versal.rst +++ b/docs/plat/xilinx-versal.rst @@ -33,3 +33,11 @@ Xilinx Versal platform specific build options * `VERSAL_PLATFORM`: Select the platform. Options: - `versal_virt` : Versal Virtual platform + +# PLM->TF-A Parameter Passing +------------------------------ +The PLM populates a data structure with image information for the TF-A. The TF-A +uses that data to hand off to the loaded images. The address of the handoff +data structure is passed in the ```PMC_GLOBAL_GLOB_GEN_STORAGE4``` register. +The register is free to be used by other software once the TF-A is bringing up +further firmware images. diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c index 825421e29..2fa847658 100644 --- a/plat/xilinx/versal/aarch64/versal_common.c +++ b/plat/xilinx/versal/aarch64/versal_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,11 +67,3 @@ unsigned int plat_get_syscnt_freq2(void) return VERSAL_CPU_CLOCK; } -uintptr_t plat_get_ns_image_entrypoint(void) -{ -#ifdef PRELOADED_BL33_BASE - return PRELOADED_BL33_BASE; -#else - return PLAT_VERSAL_NS_IMAGE_OFFSET; -#endif -} diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c index 6b56307af..a5cf05e9a 100644 --- a/plat/xilinx/versal/bl31_versal_setup.c +++ b/plat/xilinx/versal/bl31_versal_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,8 +13,12 @@ #include #include #include +#include #include #include +#include +#include +#include static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; @@ -36,6 +40,18 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) return &bl32_image_ep_info; } +/* + * Set the build time defaults,if we can't find any config data. + */ +static inline void bl31_set_default_config(void) +{ + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); +} + /* * Perform any BL31 specific platform actions. Here is an opportunity to copy * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they @@ -45,6 +61,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { + uint64_t atf_handoff_addr; /* Initialize the console to provide early debug support */ int rc = console_pl011_register(VERSAL_UART_BASE, @@ -76,12 +93,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); - /* use build time defaults in JTAG boot mode */ - bl32_image_ep_info.pc = BL32_BASE; - bl32_image_ep_info.spsr = 0; - bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); - bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); + atf_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); + enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, + &bl33_image_ep_info, + atf_handoff_addr); + if (ret == FSBL_HANDOFF_NO_STRUCT) { + bl31_set_default_config(); + } else if (ret != FSBL_HANDOFF_SUCCESS) { + panic(); + } NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h index bcc7a9364..9f8392ce9 100644 --- a/plat/xilinx/versal/include/platform_def.h +++ b/plat/xilinx/versal/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -56,9 +56,9 @@ * BL33 specific defines. ******************************************************************************/ #ifndef PRELOADED_BL33_BASE -# define PLAT_VERSAL_NS_IMAGE_OFFSET 0x8000000 +# define PLAT_ARM_NS_IMAGE_BASE 0x8000000 #else -# define PLAT_VERSAL_NS_IMAGE_OFFSET PRELOADED_BL33_BASE +# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE #endif /******************************************************************************* diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h index 94bd321b8..9a9b7c017 100644 --- a/plat/xilinx/versal/include/versal_def.h +++ b/plat/xilinx/versal/include/versal_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -121,6 +121,10 @@ #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 +/* PMC registers and bitfields */ +#define PMC_GLOBAL_BASE 0xF1110000 +#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40) + /* IPI registers and bitfields */ #define IPI0_REG_BASE 0xFF330000 #define IPI0_TRIG_BIT (1 << 2) diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk index 7a8bfa31a..1e231cce8 100644 --- a/plat/xilinx/versal/platform.mk +++ b/plat/xilinx/versal/platform.mk @@ -1,4 +1,4 @@ -# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -55,6 +55,7 @@ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ drivers/arm/pl011/aarch64/pl011_console.S \ plat/common/aarch64/crash_console_helpers.S \ plat/arm/common/arm_cci.c \ + plat/arm/common/arm_common.c \ plat/common/plat_gicv3.c \ plat/xilinx/versal/aarch64/versal_helpers.S \ plat/xilinx/versal/aarch64/versal_common.c @@ -64,6 +65,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ lib/cpus/aarch64/cortex_a72.S \ plat/common/plat_psci_common.c \ plat/xilinx/common/ipi.c \ + plat/xilinx/common/plat_startup.c \ plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ plat/xilinx/common/pm_service/pm_ipi.c \ plat/xilinx/versal/bl31_versal_setup.c \ -- cgit v1.2.3 From 09035d109d36b12164e8775a41c894066e926eae Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Wed, 22 Jan 2020 16:02:57 +0000 Subject: spm-mm: correcting instructions to build SPM for FVP Out of two possible implementation of Secure Partition Manager(SPM) currently only Management mode (MM) design is supported and the support for SPM based on SPCI Alpha 1 prototype has been removed. Earlier both implementation used common build flag "ENABLE_SPM" but it has since been decoupled and MM uses a separate build FLAG "SPM_MM". Instructions to build it for FVP was still using "ENABLE_SPM", which has beend corrected in this patch. Signed-off-by: Manish Pandey Change-Id: I505b98173d6051816436aa602ced6dbec4efc776 --- docs/components/secure-partition-manager-design.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/components/secure-partition-manager-design.rst b/docs/components/secure-partition-manager-design.rst index 9aba95450..52b1c03e8 100644 --- a/docs/components/secure-partition-manager-design.rst +++ b/docs/components/secure-partition-manager-design.rst @@ -119,7 +119,7 @@ Interface). This will be referred to as the *Standalone MM Secure Partition* in the rest of this document. To enable SPM support in TF-A, the source code must be compiled with the build -flag ``ENABLE_SPM=1``, along with ``EL3_EXCEPTION_HANDLING=1``. On Arm +flag ``SPM_MM=1``, along with ``EL3_EXCEPTION_HANDLING=1``. On Arm platforms the build option ``ARM_BL31_IN_DRAM`` must be set to 1. Also, the location of the binary that contains the BL32 image (``BL32=path/to/image.bin``) must be specified. @@ -133,7 +133,7 @@ image in the FIP: .. code:: shell BL32=path/to/standalone/mm/sp BL33=path/to/bl33.bin \ - make PLAT=fvp ENABLE_SPM=1 ARM_BL31_IN_DRAM=1 fip all + make PLAT=fvp SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ARM_BL31_IN_DRAM=1 all fip Describing Secure Partition resources ------------------------------------- -- cgit v1.2.3 From 74464d5b51954b500a1a656539a88a58e70d9b8a Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Wed, 15 Jan 2020 14:11:31 +0000 Subject: qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address. This lets the Linux kernel or any other image which expects an FDT in x0 be loaded directly as BL33 without a separate bootloader on QEMU. Signed-off-by: Andrew Walbran Change-Id: Ia8eb4710a3d97cdd877af3b8aae36a2de7cfc654 --- docs/plat/qemu.rst | 4 ++++ plat/qemu/common/qemu_bl2_setup.c | 21 ++++++++++++++++++--- plat/qemu/qemu/platform.mk | 8 ++++++++ plat/qemu/qemu_sbsa/platform.mk | 8 ++++++++ 4 files changed, 38 insertions(+), 3 deletions(-) diff --git a/docs/plat/qemu.rst b/docs/plat/qemu.rst index 4ebe64b85..a4c5bec71 100644 --- a/docs/plat/qemu.rst +++ b/docs/plat/qemu.rst @@ -10,6 +10,10 @@ loop to be released by normal world via PSCI. BL2 edits the Flattened Device Tree, FDT, generated by QEMU at run-time to add a node describing PSCI and also enable methods for the CPUs. +If ``ARM_LINUX_KERNEL_AS_BL33`` is set to 1 then this FDT will be passed to BL33 +via register x0, as expected by a Linux kernel. This allows a Linux kernel image +to be booted directly as BL33 rather than using a bootloader. + An ARM64 defconfig v4.5 Linux kernel is known to boot, FDT doesn't need to be provided as it's generated by QEMU. diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c index 166d2454e..3e289fc6b 100644 --- a/plat/qemu/common/qemu_bl2_setup.c +++ b/plat/qemu/common/qemu_bl2_setup.c @@ -51,7 +51,7 @@ static void security_setup(void) static void update_dt(void) { int ret; - void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE; + void *fdt = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE; ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE); if (ret < 0) { @@ -172,12 +172,12 @@ static int qemu_bl2_handle_post_image_load(unsigned int image_id) * OP-TEE expect to receive DTB address in x2. * This will be copied into x2 by dispatcher. */ - bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE; + bl_mem_params->ep_info.args.arg3 = ARM_PRELOADED_DTB_BASE; #else /* case AARCH32_SP_OPTEE */ bl_mem_params->ep_info.args.arg0 = bl_mem_params->ep_info.args.arg1; bl_mem_params->ep_info.args.arg1 = 0; - bl_mem_params->ep_info.args.arg2 = PLAT_QEMU_DT_BASE; + bl_mem_params->ep_info.args.arg2 = ARM_PRELOADED_DTB_BASE; bl_mem_params->ep_info.args.arg3 = 0; #endif #endif @@ -192,8 +192,23 @@ static int qemu_bl2_handle_post_image_load(unsigned int image_id) pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; #endif +#if ARM_LINUX_KERNEL_AS_BL33 + /* + * According to the file ``Documentation/arm64/booting.txt`` of + * the Linux kernel tree, Linux expects the physical address of + * the device tree blob (DTB) in x0, while x1-x3 are reserved + * for future use and must be 0. + */ + bl_mem_params->ep_info.args.arg0 = + (u_register_t)ARM_PRELOADED_DTB_BASE; + bl_mem_params->ep_info.args.arg1 = 0U; + bl_mem_params->ep_info.args.arg2 = 0U; + bl_mem_params->ep_info.args.arg3 = 0U; +#else /* BL33 expects to receive the primary CPU MPID (through r0) */ bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); +#endif + bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry(); break; default: diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk index 5fda2cd47..eaeb72cf9 100644 --- a/plat/qemu/qemu/platform.mk +++ b/plat/qemu/qemu/platform.mk @@ -186,5 +186,13 @@ endif # Process flags $(eval $(call add_define,BL32_RAM_LOCATION_ID)) +# Don't have the Linux kernel as a BL33 image by default +ARM_LINUX_KERNEL_AS_BL33 := 0 +$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) +$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) + +ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE +$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) + # Do not enable SVE ENABLE_SVE_FOR_NS := 0 diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk index 0d6047da1..f34c7e1fe 100644 --- a/plat/qemu/qemu_sbsa/platform.mk +++ b/plat/qemu/qemu_sbsa/platform.mk @@ -97,5 +97,13 @@ PRELOADED_BL33_BASE ?= 0x10000000 BL32_RAM_LOCATION_ID = SEC_SRAM_ID $(eval $(call add_define,BL32_RAM_LOCATION_ID)) +# Don't have the Linux kernel as a BL33 image by default +ARM_LINUX_KERNEL_AS_BL33 := 0 +$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) +$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) + +ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE +$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) + # Do not enable SVE ENABLE_SVE_FOR_NS := 0 -- cgit v1.2.3 From 61cbd41d7914032d3df1e49c1c1efbe2f9cb4c39 Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Wed, 15 Jan 2020 14:18:04 +0000 Subject: qemu: Implement qemu_system_off via semihosting. This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has semihosting enabled, but that is already assumed by the image loader. Signed-off-by: Andrew Walbran Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03 --- include/lib/semihosting.h | 2 ++ lib/semihosting/semihosting.c | 34 +++++++++++++++++++++++----------- plat/qemu/common/qemu_pm.c | 6 +++++- plat/qemu/qemu/platform.mk | 2 ++ plat/qemu/qemu_sbsa/platform.mk | 2 ++ 5 files changed, 34 insertions(+), 12 deletions(-) diff --git a/include/lib/semihosting.h b/include/lib/semihosting.h index 006c7b750..24b030cfd 100644 --- a/include/lib/semihosting.h +++ b/include/lib/semihosting.h @@ -23,6 +23,7 @@ #define SEMIHOSTING_SYS_REMOVE 0x0E #define SEMIHOSTING_SYS_SYSTEM 0x12 #define SEMIHOSTING_SYS_ERRNO 0x13 +#define SEMIHOSTING_SYS_EXIT 0x18 #define FOPEN_MODE_R 0x0 #define FOPEN_MODE_RB 0x1 @@ -54,5 +55,6 @@ long semihosting_download_file(const char *file_name, void semihosting_write_char(char character); void semihosting_write_string(char *string); char semihosting_read_char(void); +void semihosting_exit(uint32_t reason, uint32_t subcode); #endif /* SEMIHOSTING_H */ diff --git a/lib/semihosting/semihosting.c b/lib/semihosting/semihosting.c index 051dd008b..60fc52a00 100644 --- a/lib/semihosting/semihosting.c +++ b/lib/semihosting/semihosting.c @@ -15,7 +15,7 @@ #endif long semihosting_call(unsigned long operation, - void *system_block_address); + uintptr_t system_block_address); typedef struct { const char *file_name; @@ -53,7 +53,7 @@ long semihosting_file_open(const char *file_name, size_t mode) open_block.name_length = strlen(file_name); return semihosting_call(SEMIHOSTING_SYS_OPEN, - (void *) &open_block); + (uintptr_t) &open_block); } long semihosting_file_seek(long file_handle, ssize_t offset) @@ -65,7 +65,7 @@ long semihosting_file_seek(long file_handle, ssize_t offset) seek_block.location = offset; result = semihosting_call(SEMIHOSTING_SYS_SEEK, - (void *) &seek_block); + (uintptr_t) &seek_block); if (result) result = semihosting_call(SEMIHOSTING_SYS_ERRNO, 0); @@ -86,7 +86,7 @@ long semihosting_file_read(long file_handle, size_t *length, uintptr_t buffer) read_block.length = *length; result = semihosting_call(SEMIHOSTING_SYS_READ, - (void *) &read_block); + (uintptr_t) &read_block); if (result == *length) { return -EINVAL; @@ -112,7 +112,7 @@ long semihosting_file_write(long file_handle, write_block.length = *length; result = semihosting_call(SEMIHOSTING_SYS_WRITE, - (void *) &write_block); + (uintptr_t) &write_block); *length = result; @@ -122,28 +122,28 @@ long semihosting_file_write(long file_handle, long semihosting_file_close(long file_handle) { return semihosting_call(SEMIHOSTING_SYS_CLOSE, - (void *) &file_handle); + (uintptr_t) &file_handle); } long semihosting_file_length(long file_handle) { return semihosting_call(SEMIHOSTING_SYS_FLEN, - (void *) &file_handle); + (uintptr_t) &file_handle); } char semihosting_read_char(void) { - return semihosting_call(SEMIHOSTING_SYS_READC, NULL); + return semihosting_call(SEMIHOSTING_SYS_READC, 0); } void semihosting_write_char(char character) { - semihosting_call(SEMIHOSTING_SYS_WRITEC, (void *) &character); + semihosting_call(SEMIHOSTING_SYS_WRITEC, (uintptr_t) &character); } void semihosting_write_string(char *string) { - semihosting_call(SEMIHOSTING_SYS_WRITE0, (void *) string); + semihosting_call(SEMIHOSTING_SYS_WRITE0, (uintptr_t) string); } long semihosting_system(char *command_line) @@ -154,7 +154,7 @@ long semihosting_system(char *command_line) system_block.command_length = strlen(command_line); return semihosting_call(SEMIHOSTING_SYS_SYSTEM, - (void *) &system_block); + (uintptr_t) &system_block); } long semihosting_get_flen(const char *file_name) @@ -216,3 +216,15 @@ semihosting_fail: semihosting_file_close(file_handle); return ret; } + +void semihosting_exit(uint32_t reason, uint32_t subcode) +{ +#ifdef __aarch64__ + uint64_t parameters[] = {reason, subcode}; + + (void) semihosting_call(SEMIHOSTING_SYS_EXIT, (uintptr_t) ¶meters); +#else + /* The subcode is not supported on AArch32. */ + (void) semihosting_call(SEMIHOSTING_SYS_EXIT, reason); +#endif +} diff --git a/plat/qemu/common/qemu_pm.c b/plat/qemu/common/qemu_pm.c index a199688df..116211c51 100644 --- a/plat/qemu/common/qemu_pm.c +++ b/plat/qemu/common/qemu_pm.c @@ -10,10 +10,13 @@ #include #include #include +#include #include #include "qemu_private.h" +#define ADP_STOPPED_APPLICATION_EXIT 0x20026 + /* * The secure entry point to be used on warm reset. */ @@ -191,7 +194,8 @@ void qemu_pwr_domain_suspend_finish(const psci_power_state_t *target_state) ******************************************************************************/ static void __dead2 qemu_system_off(void) { - ERROR("QEMU System Off: operation not handled.\n"); + semihosting_exit(ADP_STOPPED_APPLICATION_EXIT, 0); + ERROR("QEMU System Off: semihosting call unexpectedly returned.\n"); panic(); } diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk index eaeb72cf9..b95bf5a51 100644 --- a/plat/qemu/qemu/platform.mk +++ b/plat/qemu/qemu/platform.mk @@ -151,6 +151,8 @@ ifeq (${ARM_ARCH_MAJOR},8) BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ + lib/semihosting/semihosting.c \ + lib/semihosting/${ARCH}/semihosting_call.S \ plat/common/plat_psci_common.c \ ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \ ${PLAT_QEMU_COMMON_PATH}/topology.c \ diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk index f34c7e1fe..51832d0ff 100644 --- a/plat/qemu/qemu_sbsa/platform.mk +++ b/plat/qemu/qemu_sbsa/platform.mk @@ -71,6 +71,8 @@ QEMU_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \ BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ + lib/semihosting/semihosting.c \ + lib/semihosting/${ARCH}/semihosting_call.S \ plat/common/plat_psci_common.c \ ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \ ${PLAT_QEMU_COMMON_PATH}/topology.c \ -- cgit v1.2.3 From dbafda7cdae778fb9672cdefd256188b056e1ea6 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Wed, 22 Jan 2020 13:30:39 -0600 Subject: Errata workarounds N1 1043202, 1315703 default off Setting errata workarounds for N1 1043202 and 1315703 to 0 since they should be turned off by default. Signed-off-by: Lauren Wehrmeister Change-Id: I116673a4ddcf64436e90d70133f035a133989ed9 --- lib/cpus/cpu-ops.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index c9b9b387e..398edf9dc 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -240,7 +240,7 @@ ERRATA_HERCULES_1688305 ?=0 # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. -ERRATA_N1_1043202 ?=1 +ERRATA_N1_1043202 ?=0 # Flag to apply erratum 1073348 workaround during reset. This erratum applies # only to revision r0p0 and r1p0 of the Neoverse N1 cpu. @@ -280,7 +280,7 @@ ERRATA_N1_1275112 ?=0 # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. -ERRATA_N1_1315703 ?=1 +ERRATA_N1_1315703 ?=0 # Flag to apply erratum 1542419 workaround during reset. This erratum applies # to revisions r3p0 - r4p0 of the Neoverse N1 cpu. -- cgit v1.2.3 From 3c6ec8f1220242c16b0930916e72783b85b15472 Mon Sep 17 00:00:00 2001 From: Mark Dykes Date: Wed, 22 Jan 2020 21:52:52 +0000 Subject: Revert "plat/arm: Add support for SEPARATE_NOBITS_REGION" This reverts commit d433bbdd459c222e5bf5ca87319807465b246d8c. Change-Id: I46c69dce704a1ce1b50452dd4d62425c4a67f7f0 --- include/plat/arm/common/arm_def.h | 12 ++---------- plat/arm/common/arm_bl31_setup.c | 13 +------------ plat/arm/common/arm_common.mk | 19 +------------------ 3 files changed, 4 insertions(+), 40 deletions(-) diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 5bd53f3b5..b419c853e 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -395,21 +395,13 @@ /******************************************************************************* * BL31 specific defines. ******************************************************************************/ -#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION +#if ARM_BL31_IN_DRAM /* * Put BL31 at the bottom of TZC secured DRAM */ #define BL31_BASE ARM_AP_TZC_DRAM1_BASE #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ PLAT_ARM_MAX_BL31_SIZE) -/* - * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. - * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. - */ -#if SEPARATE_NOBITS_REGION -#define BL31_NOBITS_BASE BL2_BASE -#define BL31_NOBITS_LIMIT BL2_LIMIT -#endif /* SEPARATE_NOBITS_REGION */ #elif (RESET_TO_BL31) /* Ensure Position Independent support (PIE) is enabled for this config.*/ # if !ENABLE_PIE diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index 7a3ca7177..939885f98 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -56,14 +56,6 @@ IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_INIT_CODE_END); MT_CODE | MT_SECURE) #endif -#if SEPARATE_NOBITS_REGION -#define MAP_BL31_NOBITS MAP_REGION_FLAT( \ - BL31_NOBITS_BASE, \ - BL31_NOBITS_LIMIT \ - - BL31_NOBITS_BASE, \ - MT_MEMORY | MT_RW | MT_SECURE) - -#endif /******************************************************************************* * Return a pointer to the 'entry_point_info' structure of the next image for the * security state specified. BL33 corresponds to the non-secure image type @@ -302,9 +294,6 @@ void __init arm_bl31_plat_arch_setup(void) MAP_BL31_TOTAL, #if RECLAIM_INIT_CODE MAP_BL_INIT_CODE, -#endif -#if SEPARATE_NOBITS_REGION - MAP_BL31_NOBITS, #endif ARM_MAP_BL_RO, #if USE_ROMLIB diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index ab33e1ded..9d4f05e9e 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -125,23 +125,6 @@ ENABLE_PMF := 1 # mapping the former as executable and the latter as execute-never. SEPARATE_CODE_AND_RODATA := 1 -# On ARM platforms, disable SEPARATE_NOBITS_REGION by default. Both PROGBITS -# and NOBITS sections of BL31 image are adjacent to each other and loaded -# into Trusted SRAM. -SEPARATE_NOBITS_REGION := 0 - -# In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load -# BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate -# the build to require that ARM_BL31_IN_DRAM is enabled as well. -ifeq ($(SEPARATE_NOBITS_REGION),1) - ifneq ($(ARM_BL31_IN_DRAM),1) - $(error For SEPARATE_NOBITS_REGION, ARM_BL31_IN_DRAM must be enabled) - endif - ifneq ($(RECLAIM_INIT_CODE),0) - $(error For SEPARATE_NOBITS_REGION, RECLAIM_INIT_CODE cannot be supported) - endif -endif - # Disable ARM Cryptocell by default ARM_CRYPTOCELL_INTEG := 0 $(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG)) -- cgit v1.2.3 From fdc8021a046a5b961e1428e5d00549a956efeebd Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 10 Jan 2020 16:52:23 -0800 Subject: Tegra: bpmp: fix header file paths This patch fixes the header file paths to include debug.h from the right location. Signed-off-by: Varun Wadekar Change-Id: If303792d2169158f436ae6aa5b6d7a4f88e28f7b --- plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c | 4 ++-- plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c index 68b450e52..ae899c424 100644 --- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c +++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include #include -#include +#include #include #include #include diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c index 4212eca1d..57daf6aeb 100644 --- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c +++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include #include -#include +#include #include #include #include -- cgit v1.2.3 From d11f5e05092b23efed0e46c61b3f6f510e7bbb2f Mon Sep 17 00:00:00 2001 From: steven kao Date: Tue, 2 Jan 2018 19:09:04 -0800 Subject: Tegra194: toggle SE clock during context save/restore This patch adds support to toggle SE clock, using the bpmp_ipc interface, to enable SE context save/restore. The SE sequence mostly gets called during System Suspend/Resume. Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7 Signed-off-by: steven kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 15 +++++++++++++++ plat/nvidia/tegra/soc/t194/drivers/se/se.c | 21 ++++++++++++++++++++- plat/nvidia/tegra/soc/t194/plat_setup.c | 4 ++++ plat/nvidia/tegra/soc/t194/platform_t194.mk | 2 ++ 4 files changed, 41 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index a98aa2da8..da8056bb6 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -151,6 +151,14 @@ #define TEGRA_RNG1_BASE U(0x03AE0000) #define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) +/******************************************************************************* + * Tegra HSP doorbell #0 constants + ******************************************************************************/ +#define TEGRA_HSP_DBELL_BASE U(0x03C90000) +#define HSP_DBELL_1_ENABLE U(0x104) +#define HSP_DBELL_3_TRIGGER U(0x300) +#define HSP_DBELL_3_ENABLE U(0x304) + /******************************************************************************* * Tegra hardware synchronization primitives for the SPE engine ******************************************************************************/ @@ -206,6 +214,13 @@ #define TEGRA_TZRAM_BASE U(0x40000000) #define TEGRA_TZRAM_SIZE U(0x40000) +/******************************************************************************* + * Tegra CCPLEX-BPMP IPC constants + ******************************************************************************/ +#define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x4004C000) +#define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x4004D000) +#define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */ + /******************************************************************************* * Tegra Clock and Reset Controller constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c index a9f461071..3a2e959d0 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/se/se.c +++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -181,6 +182,12 @@ int32_t tegra_se_suspend(void) { int32_t ret = 0; + /* initialise communication channel with BPMP */ + assert(tegra_bpmp_ipc_init() == 0); + + /* Enable SE clock before SE context save */ + tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE); + /* save SE registers */ se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT); se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL); @@ -193,6 +200,9 @@ int32_t tegra_se_suspend(void) ERROR("%s: context save failed (%d)\n", __func__, ret); } + /* Disable SE clock after SE context save */ + tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE); + return ret; } @@ -201,6 +211,12 @@ int32_t tegra_se_suspend(void) */ void tegra_se_resume(void) { + /* initialise communication channel with BPMP */ + assert(tegra_bpmp_ipc_init() == 0); + + /* Enable SE clock before SE context restore */ + tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE); + /* * When TZ takes over after System Resume, TZ should first reconfigure * SE_MUTEX_WATCHDOG_NS_LIMIT, PKA1_MUTEX_WATCHDOG_NS_LIMIT, @@ -211,4 +227,7 @@ void tegra_se_resume(void) mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]); mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]); mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]); + + /* Disable SE clock after SE context restore */ + tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE); } diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 3b582444c..38c737d92 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -86,6 +86,8 @@ static const mmap_region_t tegra_mmap[] = { (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ @@ -94,6 +96,8 @@ static const mmap_region_t tegra_mmap[] = { MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), #endif + MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index f114b7e5b..1389f8f23 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -38,6 +38,8 @@ PLAT_INCLUDES += -I${SOC_DIR}/drivers/include BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ + ${COMMON_DIR}/drivers/bpmp_ipc/intf.c \ + ${COMMON_DIR}/drivers/bpmp_ipc/ivc.c \ ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ ${COMMON_DIR}/drivers/smmu/smmu.c \ ${SOC_DIR}/drivers/mce/mce.c \ -- cgit v1.2.3 From 1a7a1dcd13f8513b7e33addcc5af0209bebb921a Mon Sep 17 00:00:00 2001 From: Vignesh Radhakrishnan Date: Wed, 27 Dec 2017 21:04:49 -0800 Subject: Tegra194: Request CG7 from last core in cluster - SC7 requires all the cluster groups to be in CG7 state, else is_sc7_allowed will get denied - As a WAR while requesting CC6, request CG7 as well - CG7 request will not be honored if it is not last core in Cluster group - This is just to satisfy MCE for now as CG7 is going to be defeatured Change-Id: Ibf2f8a365a2e46bd427abd563da772b6b618350f Signed-off-by: Vignesh Radhakrishnan --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index b7e370336..5e27455ec 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -251,6 +251,8 @@ static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t * /* Enable CC6 state and turn off wake mask */ cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6; + cstate_info.ccplex = (uint32_t)TEGRA_NVG_CG_CG7; + cstate_info.system_state_force = 1; cstate_info.update_wake_mask = 1U; mce_update_cstate_info(&cstate_info); -- cgit v1.2.3 From 21e22fe301e61ea25ab11c6fee8ed83a2fefeb0a Mon Sep 17 00:00:00 2001 From: Puneet Saxena Date: Tue, 2 Jan 2018 11:13:01 +0530 Subject: Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent Force memory transactions from seswr and sesrd as coherent_snoop from no-override. This is necessary as niso clients should use coherent path. Presently its set as FORCE_COHERENT_SNOOP. Once SE+TZ is enabled with SMMU, this needs to be replaced by FORCE_COHERENT. Change-Id: I8b50722de743b9028129b4715769ef93deab73b5 Signed-off-by: Puneet Saxena --- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 57186503b..07c05c8b1 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -388,6 +388,7 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_tsa_w_passthrough(SDMMCW); mc_set_tsa_w_passthrough(SDMMCWA); mc_set_tsa_w_passthrough(SDMMCWAB); + mc_set_tsa_w_passthrough(SESWR); mc_set_tsa_w_passthrough(TSECSWR); mc_set_tsa_w_passthrough(TSECSWRB); mc_set_tsa_w_passthrough(UFSHCW); @@ -467,8 +468,11 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE); - mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE); + /* + * TO DO: make SESRD/WR FORCE_COHERENT once SE+TZ with SMMU is enabled. + */ + mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); -- cgit v1.2.3 From a0cacc955a68a5340dac179b92b821b61da4b283 Mon Sep 17 00:00:00 2001 From: Arto Merilainen Date: Thu, 18 Jan 2018 19:47:36 +0200 Subject: Tegra194: memctrl: Disable PVARDC coalescer Due to a hardware bug PVA may perform memory transactions which cause coalescer faults. This change works around the issue by disabling coalescer for PVA0RDC and PVA1RDC. Change-Id: I27d1f6e7bc819fb303dae98079d9277fa346a1d3 Signed-off-by: Arto Merilainen --- plat/nvidia/tegra/include/t194/tegra_mc_def.h | 5 ++++- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 9 +++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h index 09dcce3c0..5da770f2e 100644 --- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -531,7 +531,10 @@ #define MC_CLIENT_HOTRESET_STATUS2 0x1898U #define MC_COALESCE_CTRL 0x2930U -#define MC_COALESCE_CTRL_COALESCER_ENABLE (1U << 31) +#define MC_COALESCE_CTRL_COALESCER_ENABLE (1U << 31) +#define MC_COALESCE_CONFIG_6_0 0x294cU +#define MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED (1U << 8) +#define MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED (1U << 14) /******************************************************************************* * Tegra TSA Controller constants diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 07c05c8b1..0f8092224 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -618,6 +618,15 @@ static void tegra194_memctrl_reconfig_mss_clients(void) reg_val = MC_COALESCE_CTRL_COALESCER_ENABLE; tegra_mc_write_32(MC_COALESCE_CTRL, reg_val); + + /* + * WAR to hardware bug 1953865: Coalescer must be disabled + * for PVA0RDC and PVA1RDC interfaces. + */ + reg_val = tegra_mc_read_32(MC_COALESCE_CONFIG_6_0); + reg_val &= ~(MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED | + MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED); + tegra_mc_write_32(MC_COALESCE_CONFIG_6_0, reg_val); } /******************************************************************************* -- cgit v1.2.3 From 1296da6d859ce1a51c212c1469a763529247dc5f Mon Sep 17 00:00:00 2001 From: Puneet Saxena Date: Fri, 5 Jan 2018 07:04:35 -0800 Subject: Tegra194: memctrl: update mss reprogramming as HW PROD settings Memory clients are divided in to ISO/NonISO/Order/Unordered/Low BW/High BW. Based on the client types, HW team recommends, different memory ordering settings, IO coherency settings and SMMU register settings for optimized performance of the MC clients. For example ordered ISO clients should be set as strongly ordered and should bypass SCF and directly access MC hence set as FORCE_NON_COHERENT. Like this there are multiple recommendations for all of the MC clients. This change sets all these MC registers as per HW spec file. Change-Id: I8a8a0887cd86bf6fe8ac7835df6c888855738cd9 Signed-off-by: Puneet Saxena Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra_mc_def.h | 23 ++- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 239 ++++++++++++++++---------- 2 files changed, 164 insertions(+), 98 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h index 5da770f2e..6911ba194 100644 --- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -18,14 +18,14 @@ #define MC_CLIENT_ORDER_ID_27 U(0x2a6c) #define MC_CLIENT_ORDER_ID_27_RESET_VAL 0x00000000U #define MC_CLIENT_ORDER_ID_27_PCIE0W_MASK (0x3U << 4) -#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (1U << 4) +#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (2U << 4) #define MC_CLIENT_ORDER_ID_28 U(0x2a70) #define MC_CLIENT_ORDER_ID_28_RESET_VAL 0x00000000U #define MC_CLIENT_ORDER_ID_28_PCIE4W_MASK (0x3U << 4) #define MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID (3U << 4) #define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12) -#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (2U << 12) +#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (1U << 12) #define mc_client_order_id(val, id, client) \ ((val & ~MC_CLIENT_ORDER_ID_##id##_##client##_MASK) | \ @@ -53,6 +53,11 @@ #define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28) #define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28) +#define MC_HUB_PC_VC_ID_12 U(0x2aa8) +#define MC_HUB_PC_VC_ID_12_RESET_VAL 0x11001011U +#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID_MASK (0x3U << 12) +#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID (VC_NISO << 12) + #define mc_hub_vc_id(val, id, client) \ ((val & ~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK) | \ MC_HUB_PC_VC_ID_##id##_##client##_VC_ID) @@ -105,7 +110,7 @@ #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK (1U << 7) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1U << 15) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0U << 15) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17) @@ -652,5 +657,17 @@ #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) +#define TSA_CONFIG_CSW_SO_DEV_HUBID_MASK (ULL(0x3) << 15) +#define TSA_CONFIG_CSW_SO_DEV_HUB2 (ULL(2) << 15) + +#define tsa_read_32(client) \ + mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client) + +#define mc_set_tsa_hub2(val, client) \ + { \ + mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ + ((val & ~TSA_CONFIG_CSW_SO_DEV_HUBID_MASK) | \ + TSA_CONFIG_CSW_SO_DEV_HUB2)); \ + } #endif /* TEGRA_MC_DEF_H */ diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 0f8092224..d9ea50e62 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -381,10 +381,12 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_tsa_w_passthrough(AXISW); mc_set_tsa_w_passthrough(BPMPDMAW); mc_set_tsa_w_passthrough(BPMPW); + mc_set_tsa_w_passthrough(EQOSW); mc_set_tsa_w_passthrough(ETRW); - mc_set_tsa_w_passthrough(SCEDMAW); mc_set_tsa_w_passthrough(RCEDMAW); mc_set_tsa_w_passthrough(RCEW); + mc_set_tsa_w_passthrough(SCEDMAW); + mc_set_tsa_w_passthrough(SCEW); mc_set_tsa_w_passthrough(SDMMCW); mc_set_tsa_w_passthrough(SDMMCWA); mc_set_tsa_w_passthrough(SDMMCWAB); @@ -394,6 +396,25 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_tsa_w_passthrough(UFSHCW); mc_set_tsa_w_passthrough(VICSWR); mc_set_tsa_w_passthrough(VIFALW); + /* + * set HUB2 as SO_DEV_HUBID + */ + reg_val = tsa_read_32(PCIE0W); + mc_set_tsa_hub2(reg_val, PCIE0W); + reg_val = tsa_read_32(PCIE1W); + mc_set_tsa_hub2(reg_val, PCIE1W); + reg_val = tsa_read_32(PCIE2AW); + mc_set_tsa_hub2(reg_val, PCIE2AW); + reg_val = tsa_read_32(PCIE3W); + mc_set_tsa_hub2(reg_val, PCIE3W); + reg_val = tsa_read_32(PCIE4W); + mc_set_tsa_hub2(reg_val, PCIE4W); + reg_val = tsa_read_32(SATAW); + mc_set_tsa_hub2(reg_val, SATAW); + reg_val = tsa_read_32(XUSB_DEVW); + mc_set_tsa_hub2(reg_val, XUSB_DEVW); + reg_val = tsa_read_32(XUSB_HOSTW); + mc_set_tsa_hub2(reg_val, XUSB_HOSTW); /* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3 * ISO clients(DISP, VI, EQOS) should never snoop caches and @@ -429,112 +450,141 @@ static void tegra194_memctrl_reconfig_mss_clients(void) * between A01 and A02, tegra_memctrl_set_overrides() programs * CGID_TAG_ADR for the necessary clients on A02. */ - mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + if (tegra_platform_is_silicon()) { + mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + } + mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); /* * TO DO: make SESRD/WR FORCE_COHERENT once SE+TZ with SMMU is enabled. - */ + */ mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); - mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); - if (tegra_platform_is_silicon()) { - mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - } + mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(AXIAPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AXIAPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0FALRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0FALWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1FALRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1FALWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(ISPFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPRA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDB1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDB1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + /* - * At this point, ordering can occur at ROC. So, remove PCFIFO's + * At this point, ordering can occur at SCF. So, remove PCFIFO's * control over ordering requests. * * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for * boot and strongly ordered MSS clients */ - /* SATAW is ordered client */ - reg_val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL | - mc_set_pcfifo_ordered_boot_so_mss(1, SATAW); - tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, reg_val); - reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL & mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) & mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR); - /* XUSB_DEVW has PCFIFO enabled. */ - reg_val |= mc_set_pcfifo_ordered_boot_so_mss(2, XUSB_DEVW); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val); reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL & @@ -558,7 +608,7 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) & mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); /* EQOSW has PCFIFO order enabled. */ - reg_val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW); + reg_val |= mc_set_pcfifo_unordered_boot_so_mss(4, EQOSW); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val); reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & @@ -570,10 +620,6 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) & mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) & mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W); - /* PCIE1, PCIE2 and PCI3 has PCFIFO enabled. */ - reg_val |= mc_set_pcfifo_ordered_boot_so_mss(6, PCIE1W) | - mc_set_pcfifo_ordered_boot_so_mss(6, PCIE2W) | - mc_set_pcfifo_ordered_boot_so_mss(6, PCIE3W); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val); reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL & @@ -607,6 +653,9 @@ static void tegra194_memctrl_reconfig_mss_clients(void) reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_4_RESET_VAL, 4, NIC); tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val); + reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_12_RESET_VAL, 12, UFSHCPC2); + tegra_mc_write_32(MC_HUB_PC_VC_ID_12, reg_val); + wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); -- cgit v1.2.3 From 90dce0f9c0a70732a9c25c14ab31d171494fef87 Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Thu, 8 Feb 2018 16:08:58 +0530 Subject: Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULT - All SoC clients should use CGID_TAG_ADR to improve perf - Remove tegra194_txn_override_cfgs array that is not getting used. Change-Id: I9130ef5ae8659ed5f9d843ab9a0ecf58b5ce9c74 Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 276 +++++++++++++----------------- 1 file changed, 119 insertions(+), 157 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index d9ea50e62..7a9e240ec 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -269,38 +269,6 @@ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE), }; -/******************************************************************************* - * Array to hold the transaction override configs - ******************************************************************************/ -const static mc_txn_override_cfg_t tegra194_txn_override_cfgs[] = { - mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR), - mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR), - mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR), - mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR), - mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR), - mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(APEW, CGID_TAG_ADR), - mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR), - mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR), - mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR), - mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR), - mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR), - mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR), - mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(AONW, CGID_TAG_ADR), - mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR), -}; - /* To be called by common memctrl_v2.c */ static void tegra194_memctrl_reconfig_mss_clients(void) { @@ -445,135 +413,131 @@ static void tegra194_memctrl_reconfig_mss_clients(void) * - MMIO's can be early acked and AXI ensures dev memory ordering, * Client ensures read/write direction change ordering. * - See Bug 200312466 for more details. - * - * CGID_TAG_ADR is only present from T186 A02. As this code is common - * between A01 and A02, tegra_memctrl_set_overrides() programs - * CGID_TAG_ADR for the necessary clients on A02. */ - mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(AONDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(APEDMAR, CGID_TAG_ADR, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APEDMAW, CGID_TAG_ADR, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(AXISR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AXISW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(EQOSR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(EQOSW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(ETRR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ETRW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(HOST1XDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDISPLAYR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(NVDISPLAYR1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(PCIE0R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE0R1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE0W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE1R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE1W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); if (tegra_platform_is_silicon()) { - mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE2AR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE2AW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE3R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE3W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE4R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE4W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5R1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); } - mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCEDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCEDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SATAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SATAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SCEDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCEDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCRAB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCWA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCWAB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); /* * TO DO: make SESRD/WR FORCE_COHERENT once SE+TZ with SMMU is enabled. */ - mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(AXIAPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(AXIAPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(DLA0FALRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(DLA0FALWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(DLA0RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(DLA0RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(DLA0WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(DLA1FALRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(DLA1FALWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(DLA1RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(DLA1RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(DLA1WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(ISPFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(ISPFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(ISPRA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVDEC1SRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVDEC1SRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVDEC1SWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVENC1SRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVENC1SRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVENC1SWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVENCSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA0RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA0RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA0RDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA0RDB1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA0RDC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA0WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA0WRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA0WRC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA1RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA1RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA1RDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA1RDB1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA1RDC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA1WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA1WRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(PVA1WRC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); - mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SESRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SESWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(TSECSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(UFSHCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(UFSHCW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VIFALR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(VIFALW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(XUSB_DEVR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_DEVW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_HOSTR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_HOSTW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(AXIAPR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AXIAPW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0FALRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0FALWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1FALRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1FALWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(HDAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(HDAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(ISPFALR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPFALW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPRA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPWA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPWB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVJPGSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVJPGSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDB1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDB1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VIW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); /* * At this point, ordering can occur at SCF. So, remove PCFIFO's @@ -686,8 +650,6 @@ static tegra_mc_settings_t tegra194_mc_settings = { .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), .streamid_security_cfg = tegra194_streamid_sec_cfgs, .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), - .txn_override_cfg = tegra194_txn_override_cfgs, - .num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_txn_override_cfgs), .reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients }; -- cgit v1.2.3 From eb41fee452a8e6286a7a3369ee0b2f552d44aa2c Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Thu, 1 Mar 2018 17:41:36 +0530 Subject: Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU -PTCR is ISO client so setting it to FORCE_NON_COHERENT. -MPCORER, MPCOREW and MIU0R/W to MIU7R/W clients itself will provide ordering so no need to override from mc. -MIU0R/W to MIU7R/W clients registers are not implemented in tegrasim so skipping it for simulation. -All the clients need to set CGID_TAG_ADR to maintain request ordering within a 4K boundary. Change-Id: Iaa3189a1f3e40fb4cef28be36bc4baeb5ac8f9ca Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 7a9e240ec..78e652776 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -433,6 +433,8 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_txn_override(ETRR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); mc_set_txn_override(ETRW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); mc_set_txn_override(HOST1XDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(MPCORER, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MPCOREW, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(NVDISPLAYR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); mc_set_txn_override(NVDISPLAYR1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); mc_set_txn_override(PCIE0R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); @@ -451,6 +453,7 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_txn_override(PCIE5W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); mc_set_txn_override(PCIE5R1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); } + mc_set_txn_override(PTCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); mc_set_txn_override(RCEDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); mc_set_txn_override(RCEDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); mc_set_txn_override(RCER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); @@ -539,6 +542,25 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_txn_override(PVA1WRC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); mc_set_txn_override(VIW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + if (tegra_platform_is_silicon()) { + mc_set_txn_override(MIU0R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU0W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU1R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU1W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU2R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU2W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU3R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU3W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU4R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU4W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU5R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU5W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU6R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU6W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU7R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU7W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + } + /* * At this point, ordering can occur at SCF. So, remove PCFIFO's * control over ordering requests. -- cgit v1.2.3 From 34a6610aeb8e1e976c3afc65155210e919633927 Mon Sep 17 00:00:00 2001 From: Puneet Saxena Date: Wed, 7 Mar 2018 14:06:30 +0530 Subject: Tegra194: memctrl: set reorder depth limit for PCIE blocks HW bug in third party PCIE IP - PCIE datapath hangs when there are more than 28 outstanding requests on data backbone for x1 controller. Suggested SW WAR is to limit reorder_depth_limit to 16 for PCIE 1W/2AW/3W clients. Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067 Signed-off-by: Puneet Saxena --- plat/nvidia/tegra/include/t194/tegra_mc_def.h | 12 ++++++++++++ plat/nvidia/tegra/soc/t194/plat_memctrl.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h index 6911ba194..34bdd7557 100644 --- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -660,6 +660,10 @@ #define TSA_CONFIG_CSW_SO_DEV_HUBID_MASK (ULL(0x3) << 15) #define TSA_CONFIG_CSW_SO_DEV_HUB2 (ULL(2) << 15) +#define REORDER_DEPTH_LIMIT 16 +#define TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK (ULL(0x7FF) << 21) +#define reorder_depth_limit(limit) (ULL(limit) << 21) + #define tsa_read_32(client) \ mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client) @@ -670,4 +674,12 @@ TSA_CONFIG_CSW_SO_DEV_HUB2)); \ } +#define mc_set_tsa_depth_limit(limit, client) \ + { \ + uint32_t val = mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client); \ + mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ + ((val & ~TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK) | \ + reorder_depth_limit(limit))); \ + } + #endif /* TEGRA_MC_DEF_H */ diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 78e652776..3ec07f22e 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -384,6 +384,18 @@ static void tegra194_memctrl_reconfig_mss_clients(void) reg_val = tsa_read_32(XUSB_HOSTW); mc_set_tsa_hub2(reg_val, XUSB_HOSTW); + /* + * Hw Bug: 200385660, 200394107 + * PCIE datapath hangs when there are more than 28 outstanding + * requests on data backbone for x1 controller. This is seen + * on third party PCIE IP, C1 - PCIE1W, C2 - PCIE2AW and C3 - PCIE3W. + * + * Setting Reorder depth limit, 16 which is < 28. + */ + mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE1W); + mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE2AW); + mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE3W); + /* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3 * ISO clients(DISP, VI, EQOS) should never snoop caches and * don't need ROC/PCFIFO ordering. -- cgit v1.2.3 From 33a8ba6a38a4518732e83d55c7afbd5c9ef0e86d Mon Sep 17 00:00:00 2001 From: Steven Kao Date: Fri, 9 Feb 2018 21:35:20 +0800 Subject: Tegra194: support for boot params wider than 32-bits The previous bootloader is not able to pass boot params wider than 32-bits due to an oversight in the scratch register being used. A new secure scratch register #75 has been assigned to pass the higher bits. This patch adds support to parse the higher bits from scratch #75 and use them in calculating the base address for the location of the boot params. Scratch #75 format ==================== 31:16 - bl31_plat_params high address 15:0 - bl31_params high address Change-Id: Id53c45f70a9cb370c776ed7c82ad3f2258576a80 Signed-off-by: Steven Kao --- plat/nvidia/tegra/include/t194/tegra_def.h | 11 +++++++++-- plat/nvidia/tegra/soc/t194/plat_setup.c | 14 ++++++++++---- 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index da8056bb6..6eb58b970 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -180,6 +180,7 @@ * Tegra scratch registers constants ******************************************************************************/ #define TEGRA_SCRATCH_BASE U(0x0C390000) +#define SECURE_SCRATCH_RSV75 U(0x2BC) #define SECURE_SCRATCH_RSV81_LO U(0x2EC) #define SECURE_SCRATCH_RSV81_HI U(0x2F0) #define SECURE_SCRATCH_RSV97 U(0x36C) @@ -188,8 +189,14 @@ #define SECURE_SCRATCH_RSV109_LO U(0x3CC) #define SECURE_SCRATCH_RSV109_HI U(0x3D0) -#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV81_LO -#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV81_HI +#define SCRATCH_BL31_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 +#define SCRATCH_BL31_PARAMS_HI_ADDR_MASK U(0xFFFF) +#define SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT U(0) +#define SCRATCH_BL31_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_LO +#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 +#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK U(0xFFFF0000) +#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16) +#define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97 #define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO #define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 38c737d92..ead6bf552 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -276,9 +276,12 @@ void plat_gic_setup(void) ******************************************************************************/ struct tegra_bl31_params *plat_get_bl31_params(void) { - uint32_t val; + uint64_t val; - val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR); + val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) & + SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT; + val <<= 32; + val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR); return (struct tegra_bl31_params *)(uintptr_t)val; } @@ -288,9 +291,12 @@ struct tegra_bl31_params *plat_get_bl31_params(void) ******************************************************************************/ plat_params_from_bl2_t *plat_get_bl31_plat_params(void) { - uint32_t val; + uint64_t val; - val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR); + val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) & + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT; + val <<= 32; + val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR); return (plat_params_from_bl2_t *)(uintptr_t)val; } -- cgit v1.2.3 From 939fd3db83886925972e4847e42557ca58ce58f9 Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Fri, 9 Mar 2018 10:15:17 +0530 Subject: Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1 PCIE0R1 does not program stream IDs, so allow the stream ID to be overriden by the MC. Change-Id: I4dbd71e1ce24b11e646de421ef68c762818c2667 Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 3ec07f22e..bb1dd6706 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -130,6 +130,7 @@ const static uint32_t tegra194_streamid_override_regs[] = { MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, MC_STREAMID_OVERRIDE_CFG_ISPRA1, + MC_STREAMID_OVERRIDE_CFG_PCIE0R1, MC_STREAMID_OVERRIDE_CFG_MIU0R, MC_STREAMID_OVERRIDE_CFG_MIU0W, MC_STREAMID_OVERRIDE_CFG_MIU1R, @@ -259,6 +260,7 @@ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE), -- cgit v1.2.3 From ceb12020fb05001777b0868b5e064dd26fd4895a Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 23 Jan 2018 14:51:40 -0800 Subject: Tegra194: organize the memory/mmio map to make it linear This patch organizes the platform memory/mmio map, so that the base addresses for the apertures line up in ascending order. This makes it easier for the xlat_tables_v2 library to create mappings for each mmap_add_region call. Change-Id: Ie1938ba043820625c9fea904009a3d2ccd29f7b3 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra_def.h | 32 ++++++++++++------------ plat/nvidia/tegra/soc/t194/plat_setup.c | 40 ++++++++++++++---------------- 2 files changed, 35 insertions(+), 37 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 6eb58b970..9737a2941 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -126,6 +126,18 @@ #define TEGRA_UARTF_BASE U(0x03150000) #define TEGRA_UARTG_BASE U(0x0C290000) +/******************************************************************************* + * XUSB PADCTL + ******************************************************************************/ +#define TEGRA_XUSB_PADCTL_BASE U(0x03520000) +#define TEGRA_XUSB_PADCTL_SIZE U(0x10000) +#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c) +#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c) + /******************************************************************************* * Tegra Fuse Controller related constants ******************************************************************************/ @@ -154,10 +166,10 @@ /******************************************************************************* * Tegra HSP doorbell #0 constants ******************************************************************************/ -#define TEGRA_HSP_DBELL_BASE U(0x03C90000) -#define HSP_DBELL_1_ENABLE U(0x104) -#define HSP_DBELL_3_TRIGGER U(0x300) -#define HSP_DBELL_3_ENABLE U(0x304) +#define TEGRA_HSP_DBELL_BASE U(0x03C90000) +#define HSP_DBELL_1_ENABLE U(0x104) +#define HSP_DBELL_3_TRIGGER U(0x300) +#define HSP_DBELL_3_ENABLE U(0x304) /******************************************************************************* * Tegra hardware synchronization primitives for the SPE engine @@ -237,18 +249,6 @@ #define GPU_RESET_BIT (U(1) << 0) #define GPU_SET_BIT (U(1) << 0) -/******************************************************************************* - * XUSB PADCTL - ******************************************************************************/ -#define TEGRA_XUSB_PADCTL_BASE U(0x3520000) -#define TEGRA_XUSB_PADCTL_SIZE U(0x10000) -#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c) -#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c) - /******************************************************************************* * XUSB STREAMIDs ******************************************************************************/ diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index ead6bf552..d4918d2e2 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -64,13 +64,13 @@ const uint8_t *plat_get_power_domain_tree_desc(void) * Table of regions to map using the MMU. */ static const mmap_region_t tegra_mmap[] = { - MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), #if !ENABLE_CONSOLE_SPE MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ @@ -80,39 +80,37 @@ static const mmap_region_t tegra_mmap[] = { MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), #endif - MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */ + MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), #if ENABLE_CONSOLE_SPE - MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), #endif - MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */ - (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ + MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */ + MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */ - (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), {0} }; -- cgit v1.2.3 From db891f32f6c2100beb6c7d8eedcab2df57df632f Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 23 Mar 2018 10:44:40 -0700 Subject: Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms Many simulation/emulation platforms do not support this hardware block leading to SErrors during register accesses. This patch conditionally accesses the registers from this block only on actual Si and FPGA platforms. Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 27 ++++++++++++++----------- plat/nvidia/tegra/soc/t194/plat_setup.c | 27 ++++++++++++++----------- 2 files changed, 30 insertions(+), 24 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 5e27455ec..cc8be128a 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -430,18 +430,21 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) * in above registers to support both virtualization and * non-virtualization platforms */ - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); + if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { + + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); + } /* * Reset power state info for the last core doing SC7 diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index d4918d2e2..c064bdf77 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -233,18 +233,21 @@ void plat_early_platform_setup(void) * above registers to support both virtualization and * non-virtualization platforms */ - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); + if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { + + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); + } } /* Secure IRQs for Tegra194 */ -- cgit v1.2.3 From 4a9026d413d1d97f8ef4a7c7a3d39ac25cfa03c6 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 3 Apr 2018 13:10:48 -0700 Subject: Tegra194: enable driver for general purpose DMA engine This patch enables the GPCDMA for all Tegra194 platforms to help accelerate all the memory copy operations. Change-Id: I8cbec99be6ebe4da74221245668b321ba9693479 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra_def.h | 7 +++++++ plat/nvidia/tegra/soc/t194/plat_setup.c | 2 ++ plat/nvidia/tegra/soc/t194/platform_t194.mk | 6 +++++- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 9737a2941..df1d65630 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -53,6 +53,11 @@ #define BOARD_SHIFT_BITS U(24) #define MISCREG_PFCFG U(0x200C) +/******************************************************************************* + * Tegra General Purpose Centralised DMA constants + ******************************************************************************/ +#define TEGRA_GPCDMA_BASE U(0x02610000) + /******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ @@ -248,6 +253,8 @@ #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C) #define GPU_RESET_BIT (U(1) << 0) #define GPU_SET_BIT (U(1) << 0) +#define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) +#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) /******************************************************************************* * XUSB STREAMIDs diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index c064bdf77..912dcc6f9 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -68,6 +68,8 @@ static const mmap_region_t tegra_mmap[] = { (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */ diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 1389f8f23..1e49e51da 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -8,9 +8,12 @@ ENABLE_CONSOLE_SPE := 0 $(eval $(call add_define,ENABLE_CONSOLE_SPE)) -ENABLE_STRICT_CHECKING_MODE := 1 +ENABLE_STRICT_CHECKING_MODE := 1 $(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE)) +USE_GPC_DMA := 1 +$(eval $(call add_define,USE_GPC_DMA)) + RESET_TO_BL31 := 1 PROGRAMMABLE_RESET_ADDRESS := 1 @@ -40,6 +43,7 @@ BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ ${COMMON_DIR}/drivers/bpmp_ipc/intf.c \ ${COMMON_DIR}/drivers/bpmp_ipc/ivc.c \ + ${COMMON_DIR}/drivers/gpcdma/gpcdma.c \ ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ ${COMMON_DIR}/drivers/smmu/smmu.c \ ${SOC_DIR}/drivers/mce/mce.c \ -- cgit v1.2.3 From 844e6cc5e73d081f0709d6cf39de6c4b0ff9c08b Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Thu, 19 Apr 2018 13:11:43 +0530 Subject: Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list PCIE0R1 security and override registers need to be preserved across system suspend. Adding them to system suspend save register list. Due to addition of above registers, increasing context save memory by 2 bytes. Change-Id: I1b3a56aee31f3c11e3edc2fb0a6da146eec1a30d Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/soc/t194/plat_smmu.c | 4 +++- plat/nvidia/tegra/soc/t194/plat_trampoline.S | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index 640ef4deb..3b4a3803c 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -139,6 +139,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { mc_make_sid_security_cfg(NVENCSRD1), mc_make_sid_security_cfg(NVENC1SRD1), mc_make_sid_security_cfg(ISPRA1), + mc_make_sid_security_cfg(PCIE0R1), mc_make_sid_security_cfg(MIU0R), mc_make_sid_security_cfg(MIU0W), mc_make_sid_security_cfg(MIU1R), @@ -262,6 +263,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { mc_make_sid_override_cfg(NVENCSRD1), mc_make_sid_override_cfg(NVENC1SRD1), mc_make_sid_override_cfg(ISPRA1), + mc_make_sid_override_cfg(PCIE0R1), mc_make_sid_override_cfg(MIU0R), mc_make_sid_override_cfg(MIU0W), mc_make_sid_override_cfg(MIU1R), diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S index 696a5774e..540c2019c 100644 --- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,7 @@ #define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7 #define TEGRA194_STATE_SYSTEM_RESUME 0x600D -#define TEGRA194_SMMU_CTX_SIZE 0x80B +#define TEGRA194_SMMU_CTX_SIZE 0x80D .align 4 .globl tegra194_cpu_reset_handler -- cgit v1.2.3 From 54990e377c22005343be474d76882500a6a6a782 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 10 Apr 2018 15:49:57 -0700 Subject: Tegra194: support for NVG interface v6.6 This patch updates the NVG interface header file to v6.6. Change-Id: I2f5df274bf820ba1c5df47d8dcbf7f5f056ff45f Signed-off-by: Varun Wadekar --- .../tegra/soc/t194/drivers/include/t194_nvg.h | 290 +++++++++++++-------- 1 file changed, 188 insertions(+), 102 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h index 06cbb4a2e..ccc46655a 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h @@ -20,61 +20,65 @@ */ enum { TEGRA_NVG_VERSION_MAJOR = 6, - TEGRA_NVG_VERSION_MINOR = 4 + TEGRA_NVG_VERSION_MINOR = 6 }; typedef enum { - TEGRA_NVG_CHANNEL_VERSION = 0, - TEGRA_NVG_CHANNEL_POWER_PERF = 1, - TEGRA_NVG_CHANNEL_POWER_MODES = 2, - TEGRA_NVG_CHANNEL_WAKE_TIME = 3, - TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, - TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, - TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, - TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, - TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, - TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, - TEGRA_NVG_CHANNEL_SHUTDOWN = 42, - TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, - TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, - TEGRA_NVG_CHANNEL_CC3_CTRL = 45, - TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, - TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, - TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, - TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, - TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, - TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, - TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, - TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, - TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, - TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60, - TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61, - TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62, - TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76, - TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77, - TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78, - TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79, + TEGRA_NVG_CHANNEL_VERSION = 0, + TEGRA_NVG_CHANNEL_POWER_PERF = 1, + TEGRA_NVG_CHANNEL_POWER_MODES = 2, + TEGRA_NVG_CHANNEL_WAKE_TIME = 3, + TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, + TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, + TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, + TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, + TEGRA_NVG_CHANNEL_NUM_CORES = 20, + TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID = 21, + TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING = 22, + TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR = 23, + TEGRA_NVG_CHANNEL_SHUTDOWN = 42, + TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, + TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, + TEGRA_NVG_CHANNEL_CC3_CTRL = 45, + TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, + TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, + TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, + TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, + TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, + TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, + TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60, + TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76, + TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77, + TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78, + TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79, TEGRA_NVG_CHANNEL_LAST_INDEX } tegra_nvg_channel_id_t; typedef enum { - NVG_STAT_QUERY_SC7_ENTRIES = 1, - NVG_STAT_QUERY_CC6_ENTRIES = 6, - NVG_STAT_QUERY_CG7_ENTRIES = 7, + NVG_STAT_QUERY_SC7_ENTRIES = 1, + NVG_STAT_QUERY_CC6_ENTRIES = 6, + NVG_STAT_QUERY_CG7_ENTRIES = 7, NVG_STAT_QUERY_C6_ENTRIES = 10, NVG_STAT_QUERY_C7_ENTRIES = 14, NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, @@ -112,8 +116,14 @@ typedef enum { TEGRA_NVG_CORE_WARMRSTREQ = 8 } tegra_nvg_core_sleep_state_t; +typedef enum { + TEGRA_NVG_SHUTDOWN = 0U, + TEGRA_NVG_REBOOT = 1U +} tegra_nvg_shutdown_reboot_state_t; + typedef enum { TEGRA_NVG_CLUSTER_CC0 = 0, + TEGRA_NVG_CLUSTER_AUTO_CC1 = 1, TEGRA_NVG_CLUSTER_CC6 = 6 } tegra_nvg_cluster_sleep_state_t; @@ -128,11 +138,6 @@ typedef enum { TEGRA_NVG_SYSTEM_SC8 = 8 } tegra_nvg_system_sleep_state_t; -typedef enum { - TEGRA_NVG_SHUTDOWN = 0U, - TEGRA_NVG_REBOOT = 1U, -} tegra_nvg_shutdown_reboot_state_t; - // --------------------------------------------------------------------------- // NVG Data subformats // --------------------------------------------------------------------------- @@ -206,18 +211,31 @@ typedef union { typedef union { uint64_t flat; struct nvg_cstate_info_channel_t { - uint32_t cluster_state : 3; - uint32_t reserved_6_3 : 4; - uint32_t update_cluster : 1; - uint32_t cg_cstate : 3; - uint32_t reserved_14_11 : 4; - uint32_t update_cg : 1; - uint32_t system_cstate : 4; - uint32_t reserved_22_20 : 3; - uint32_t update_system : 1; - uint32_t reserved_30_24 : 7; - uint32_t update_wake_mask : 1; - uint32_t wake_mask : 32; + uint32_t cluster_state : 3; + uint32_t reserved_6_3 : 4; + uint32_t update_cluster : 1; + uint32_t cg_cstate : 3; + uint32_t reserved_14_11 : 4; + uint32_t update_cg : 1; + uint32_t system_cstate : 4; + uint32_t reserved_22_20 : 3; + uint32_t update_system : 1; + uint32_t reserved_30_24 : 7; + uint32_t update_wake_mask : 1; + union { + uint32_t flat : 32; + struct { + uint32_t vfiq : 1; + uint32_t virq : 1; + uint32_t fiq : 1; + uint32_t irq : 1; + uint32_t serror : 1; + uint32_t reserved_10_5 : 6; + uint32_t fiqout : 1; + uint32_t irqout : 1; + uint32_t reserved_31_13 : 19; + } carmel; + } wake_mask; } bits; } nvg_cstate_info_channel_t; @@ -239,6 +257,52 @@ typedef union { } bits; } nvg_cstate_stat_query_channel_t; +typedef union { + uint64_t flat; + struct nvg_num_cores_channel_t { + uint32_t num_cores : 4; + uint32_t reserved_31_4 : 28; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_num_cores_channel_t; + +typedef union { + uint64_t flat; + struct nvg_unique_logical_id_channel_t { + uint32_t unique_core_id : 3; + uint32_t reserved_31_3 : 29; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_unique_logical_id_channel_t; + +typedef union { + uint64_t flat; + struct nvg_logical_to_physical_mappings_channel_t { + uint32_t lcore0_pcore_id : 4; + uint32_t lcore1_pcore_id : 4; + uint32_t lcore2_pcore_id : 4; + uint32_t lcore3_pcore_id : 4; + uint32_t lcore4_pcore_id : 4; + uint32_t lcore5_pcore_id : 4; + uint32_t lcore6_pcore_id : 4; + uint32_t lcore7_pcore_id : 4; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_logical_to_physical_mappings_channel_t; + +typedef union { + uint64_t flat; + struct nvg_logical_to_mpidr_channel_write_t { + uint32_t lcore_id : 3; + uint32_t reserved_31_3 : 29; + uint32_t reserved_63_32 : 32; + } write; + struct nvg_logical_to_mpidr_channel_read_t { + uint32_t mpidr : 32; + uint32_t reserved_63_32 : 32; + } read; +} nvg_logical_to_mpidr_channel_t; + typedef union { uint64_t flat; struct nvg_is_sc7_allowed_channel_t { @@ -260,50 +324,50 @@ typedef union { typedef union { uint64_t flat; struct nvg_cc3_control_channel_t { - uint32_t freq_req : 8; - uint32_t reserved_30_8 : 23; + uint32_t freq_req : 9; + uint32_t reserved_30_9 : 22; uint32_t enable : 1; uint32_t reserved_63_32 : 32; } bits; } nvg_cc3_control_channel_t; typedef enum { - TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0, - TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1, - TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2, - TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6, - TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9, - TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, - TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, - TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, - TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, - TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, - TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, - TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, - TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, - TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, - TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, + TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0, + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1, + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2, + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6, + TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9, + TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, + TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, + TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, + TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, + TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, + TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, + TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX } tegra_nvg_channel_update_gsc_gsc_enum_t; @@ -335,4 +399,26 @@ typedef union { } bits; } nvg_shutdown_t; +typedef union { + uint64_t flat; + struct nvg_debug_config_channel_t { + uint32_t enter_debug_state_on_mca : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_debug_config_t; + +typedef union { + uint64_t flat; + struct nvg_hsm_error_ctrl_channel_t { + uint32_t uncorr : 1; + uint32_t corr : 1; + uint32_t reserved_31_2 : 30; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_hsm_error_ctrl_channel_t; + +extern nvg_debug_config_t nvg_debug_config; + #endif + -- cgit v1.2.3 From 532df956306d31ba04235cf05abb88683d3836d0 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 14 May 2018 15:54:59 -0700 Subject: Tegra194: mce: remove unused NVG functions This patch removes unused functions from the NVG driver. * nvg_enable_power_perf_mode * nvg_disable_power_perf_mode * nvg_enable_power_saver_modes * nvg_disable_power_saver_modes * nvg_roc_clean_cache * nvg_roc_flush_cache Change-Id: I0387a40dec35686deaad623a8350de89acfe9393 Signed-off-by: Varun Wadekar --- .../tegra/soc/t194/drivers/include/mce_private.h | 15 ++-- plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 90 ---------------------- 2 files changed, 6 insertions(+), 99 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 9741d084f..b6572fffb 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -45,10 +45,6 @@ /* declarations for NVG handler functions */ uint64_t nvg_get_version(void); -int32_t nvg_enable_power_perf_mode(void); -int32_t nvg_disable_power_perf_mode(void); -int32_t nvg_enable_power_saver_modes(void); -int32_t nvg_disable_power_saver_modes(void); void nvg_set_wake_time(uint32_t wake_time); void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask); @@ -57,19 +53,20 @@ uint64_t nvg_get_cstate_stat_query_value(void); int32_t nvg_is_sc7_allowed(void); int32_t nvg_online_core(uint32_t core); int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); -int32_t nvg_roc_clean_cache(void); -int32_t nvg_roc_flush_cache(void); int32_t nvg_roc_clean_cache_trbits(void); int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); +int32_t nvg_roc_clean_cache_trbits(void); +void nvg_enable_strict_checking_mode(void); +void nvg_system_shutdown(void); +void nvg_system_reboot(void); + +/* declarations for assembly functions */ void nvg_set_request_data(uint64_t req, uint64_t data); void nvg_set_request(uint64_t req); uint64_t nvg_get_result(void); uint64_t nvg_cache_clean(void); uint64_t nvg_cache_clean_inval(void); uint64_t nvg_cache_inval_all(void); -void nvg_enable_strict_checking_mode(void); -void nvg_system_shutdown(void); -void nvg_system_reboot(void); /* MCE helper functions */ void mce_enable_strict_checking(void); diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index a095fdd07..1012cdf11 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -30,54 +30,6 @@ uint64_t nvg_get_version(void) return (uint64_t)nvg_get_result(); } -/* - * Enable the perf per watt mode. - * - * NVGDATA[0]: SW(RW), 1 = enable perf per watt mode - */ -int32_t nvg_enable_power_perf_mode(void) -{ - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U); - - return 0; -} - -/* - * Disable the perf per watt mode. - * - * NVGDATA[0]: SW(RW), 0 = disable perf per watt mode - */ -int32_t nvg_disable_power_perf_mode(void) -{ - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U); - - return 0; -} - -/* - * Enable the battery saver mode. - * - * NVGDATA[2]: SW(RW), 1 = enable battery saver mode - */ -int32_t nvg_enable_power_saver_modes(void) -{ - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U); - - return 0; -} - -/* - * Disable the battery saver mode. - * - * NVGDATA[2]: SW(RW), 0 = disable battery saver mode - */ -int32_t nvg_disable_power_saver_modes(void) -{ - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U); - - return 0; -} - /* * Set the expected wake time in TSC ticks for the next low-power state the * core enters. @@ -197,48 +149,6 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) return ret; } -/* - * Cache clean operation for all CCPLEX caches. - */ -int32_t nvg_roc_clean_cache(void) -{ - int32_t ret = 0; - - /* check if cache flush through mts is supported */ - if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & - ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { - if (nvg_cache_clean() == 0U) { - ERROR("%s: failed\n", __func__); - ret = -ENODEV; - } - } else { - ret = -ENOTSUP; - } - - return ret; -} - -/* - * Cache clean and invalidate operation for all CCPLEX caches. - */ -int32_t nvg_roc_flush_cache(void) -{ - int32_t ret = 0; - - /* check if cache flush through mts is supported */ - if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & - ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { - if (nvg_cache_clean_inval() == 0U) { - ERROR("%s: failed\n", __func__); - ret = -ENODEV; - } - } else { - ret = -ENOTSUP; - } - - return ret; -} - /* * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches. */ -- cgit v1.2.3 From 28abb2c2371d321f7bacb4d0fbcf3b5cba1b12f1 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:49:20 -0600 Subject: hisilicon: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: I327a8a2ab0f0e49bd62f413296c3b326393422b6 --- plat/hisilicon/hikey/include/platform_def.h | 8 ++++---- plat/hisilicon/hikey960/include/platform_def.h | 8 ++++---- plat/hisilicon/poplar/include/platform_def.h | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h index 2537ac66b..04ea71f67 100644 --- a/plat/hisilicon/hikey/include/platform_def.h +++ b/plat/hisilicon/hikey/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,13 +28,13 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_CACHE_LINE_SIZE 64 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CORE_COUNT_PER_CLUSTER 4 +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_CORE_COUNT_PER_CLUSTER) #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ - PLATFORM_CLUSTER_COUNT + 1) + PLATFORM_CLUSTER_COUNT + U(1)) #define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_OFF_STATE U(2) diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h index f6edad668..215eebe1b 100644 --- a/plat/hisilicon/hikey960/include/platform_def.h +++ b/plat/hisilicon/hikey960/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,12 +25,12 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_CACHE_LINE_SIZE 64 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CORE_COUNT_PER_CLUSTER 4 +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_CORE_COUNT_PER_CLUSTER) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 -#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ PLATFORM_CLUSTER_COUNT + 1) #define PLAT_MAX_RET_STATE U(1) diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h index 9783f8d2d..ce0fbbca0 100644 --- a/plat/hisilicon/poplar/include/platform_def.h +++ b/plat/hisilicon/poplar/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -34,9 +34,9 @@ #define BOOT_EMMC_NAME "l-loader.bin" #define PLATFORM_CACHE_LINE_SIZE (64) -#define PLATFORM_CLUSTER_COUNT (1) -#define PLATFORM_CORE_COUNT (4) -#define PLATFORM_MAX_CPUS_PER_CLUSTER (4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CORE_COUNT U(4) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) /* IO framework user */ #define MAX_IO_DEVICES (4) -- cgit v1.2.3 From 7a57188b9498aedb597349fb806f87911b2bfb50 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:47:06 -0600 Subject: imx: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: I8b19e833a4e1067e1cfcc9bfaede7854e0e63004 --- plat/imx/imx7/picopi/include/platform_def.h | 8 ++++---- plat/imx/imx7/warp7/include/platform_def.h | 8 ++++---- plat/imx/imx8m/imx8mm/include/platform_def.h | 10 +++++----- plat/imx/imx8m/imx8mq/include/platform_def.h | 10 +++++----- plat/imx/imx8qm/include/platform_def.h | 12 ++++++------ plat/imx/imx8qx/include/platform_def.h | 14 +++++++------- 6 files changed, 31 insertions(+), 31 deletions(-) diff --git a/plat/imx/imx7/picopi/include/platform_def.h b/plat/imx/imx7/picopi/include/platform_def.h index 1af1d0cfc..141571c67 100644 --- a/plat/imx/imx7/picopi/include/platform_def.h +++ b/plat/imx/imx7/picopi/include/platform_def.h @@ -13,15 +13,15 @@ #define PLATFORM_STACK_SIZE 0x1000 -#define PLATFORM_MAX_CPUS_PER_CLUSTER 2 -#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) +#define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT -#define PICOPI_PRIMARY_CPU 0 +#define PICOPI_PRIMARY_CPU U(0) -#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 diff --git a/plat/imx/imx7/warp7/include/platform_def.h b/plat/imx/imx7/warp7/include/platform_def.h index 4f719083e..4afcb5497 100644 --- a/plat/imx/imx7/warp7/include/platform_def.h +++ b/plat/imx/imx7/warp7/include/platform_def.h @@ -13,15 +13,15 @@ #define PLATFORM_STACK_SIZE 0x1000 -#define PLATFORM_MAX_CPUS_PER_CLUSTER 2 -#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) +#define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ PLATFORM_CLUSTER1_CORE_COUNT) -#define WARP7_PRIMARY_CPU 0 +#define WARP7_PRIMARY_CPU U(0) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index fc35dac14..56caab7ce 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -10,11 +10,11 @@ #define PLATFORM_STACK_SIZE 0xB00 #define CACHE_WRITEBACK_GRANULE 64 -#define PLAT_PRIMARY_CPU 0x0 -#define PLATFORM_MAX_CPU_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) #define IMX_PWR_LVL0 MPIDR_AFFLVL0 diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h index 9aa759fd3..9db3a137a 100644 --- a/plat/imx/imx8m/imx8mq/include/platform_def.h +++ b/plat/imx/imx8m/imx8mq/include/platform_def.h @@ -10,11 +10,11 @@ #define PLATFORM_STACK_SIZE 0x800 #define CACHE_WRITEBACK_GRANULE 64 -#define PLAT_PRIMARY_CPU 0x0 -#define PLATFORM_MAX_CPU_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) #define IMX_PWR_LVL0 MPIDR_AFFLVL0 diff --git a/plat/imx/imx8qm/include/platform_def.h b/plat/imx/imx8qm/include/platform_def.h index 138a4e1d3..b54943da0 100644 --- a/plat/imx/imx8qm/include/platform_def.h +++ b/plat/imx/imx8qm/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,11 +15,11 @@ #define PLATFORM_STACK_SIZE 0X400 #define CACHE_WRITEBACK_GRANULE 64 -#define PLAT_PRIMARY_CPU 0x0 -#define PLATFORM_MAX_CPU_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 2 +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(2) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ PLATFORM_CLUSTER1_CORE_COUNT) diff --git a/plat/imx/imx8qx/include/platform_def.h b/plat/imx/imx8qx/include/platform_def.h index 108627f66..41475ffeb 100644 --- a/plat/imx/imx8qx/include/platform_def.h +++ b/plat/imx/imx8qx/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,12 +15,12 @@ #define PLATFORM_STACK_SIZE 0x400 #define CACHE_WRITEBACK_GRANULE 64 -#define PLAT_PRIMARY_CPU 0x0 -#define PLATFORM_MAX_CPU_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CORE_COUNT 4 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CORE_COUNT U(4) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PWR_DOMAIN_AT_MAX_LVL U(1) #define PLAT_MAX_PWR_LVL U(2) -- cgit v1.2.3 From e0b4cc7584476f4b9da8590789a59f5a27ca0bd6 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:48:27 -0600 Subject: allwinner: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: I7aea86891e54522c88af5ff16795a575f9a9322d --- plat/allwinner/common/include/platform_def.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h index 4de8b0bc4..32a7c0408 100644 --- a/plat/allwinner/common/include/platform_def.h +++ b/plat/allwinner/common/include/platform_def.h @@ -40,17 +40,17 @@ #define PLAT_MAX_OFF_STATE U(2) #define PLAT_MAX_PWR_LVL U(2) -#define PLAT_NUM_PWR_DOMAINS (1 + \ +#define PLAT_NUM_PWR_DOMAINS (U(1) + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) -#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_MAX_CPUS_PER_CLUSTER) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_MMAP_REGIONS 4 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) -- cgit v1.2.3 From ed7a56361cb2b922fbc7c1694c6e8f88c463fdd8 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:48:54 -0600 Subject: rockchip: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: I624c15d569db477506a74964bc828e1a932181d4 --- plat/rockchip/px30/include/platform_def.h | 8 ++++---- plat/rockchip/rk3288/include/platform_def.h | 10 +++++----- plat/rockchip/rk3328/include/platform_def.h | 6 +++--- plat/rockchip/rk3368/include/platform_def.h | 10 +++++----- plat/rockchip/rk3399/include/platform_def.h | 12 ++++++------ 5 files changed, 23 insertions(+), 23 deletions(-) diff --git a/plat/rockchip/px30/include/platform_def.h b/plat/rockchip/px30/include/platform_def.h index 2f4f672a0..a11f84f42 100644 --- a/plat/rockchip/px30/include/platform_def.h +++ b/plat/rockchip/px30/include/platform_def.h @@ -39,10 +39,10 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) diff --git a/plat/rockchip/rk3288/include/platform_def.h b/plat/rockchip/rk3288/include/platform_def.h index e24aeffac..85ec3fb88 100644 --- a/plat/rockchip/rk3288/include/platform_def.h +++ b/plat/rockchip/rk3288/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -36,11 +36,11 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h index e9eb3fafb..6579756e0 100644 --- a/plat/rockchip/rk3328/include/platform_def.h +++ b/plat/rockchip/rk3328/include/platform_def.h @@ -37,9 +37,9 @@ #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 #define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h index 2abd56b0b..12115b4f0 100644 --- a/plat/rockchip/rk3368/include/platform_def.h +++ b/plat/rockchip/rk3368/include/platform_def.h @@ -37,13 +37,13 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 4 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/rockchip/rk3399/include/platform_def.h b/plat/rockchip/rk3399/include/platform_def.h index 2861a7dd4..78269b632 100644 --- a/plat/rockchip/rk3399/include/platform_def.h +++ b/plat/rockchip/rk3399/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -38,13 +38,13 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 2 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(2) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) -- cgit v1.2.3 From ac2f6d4353a7b817df97c7f120d13bd6157f7931 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:50:07 -0600 Subject: marvell: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: I7d660d5a9d7e44601353c77e9b6ee4096a277d76 --- plat/marvell/a3700/common/include/platform_def.h | 4 ++-- plat/marvell/a8k/common/include/platform_def.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/marvell/a3700/common/include/platform_def.h b/plat/marvell/a3700/common/include/platform_def.h index 591f04585..e6660d407 100644 --- a/plat/marvell/a3700/common/include/platform_def.h +++ b/plat/marvell/a3700/common/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2016-2019 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -78,7 +78,7 @@ (PLAT_MARVELL_ATF_LOAD_ADDR + 0x20000) #define PLAT_MARVELL_FIP_MAX_SIZE 0x4000000 -#define PLAT_MARVELL_CLUSTER_CORE_COUNT 2 +#define PLAT_MARVELL_CLUSTER_CORE_COUNT U(2) /* DRAM[2MB..66MB] is used as Trusted ROM */ #define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR /* 64 MB TODO: reduce this to minimum needed according to fip image size*/ diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/a8k/common/include/platform_def.h index b9c2e0ed7..ec1c9036c 100644 --- a/plat/marvell/a8k/common/include/platform_def.h +++ b/plat/marvell/a8k/common/include/platform_def.h @@ -86,8 +86,8 @@ #define PLAT_MARVELL_NORTHB_COUNT 1 -#define PLAT_MARVELL_CLUSTER_COUNT 2 -#define PLAT_MARVELL_CLUSTER_CORE_COUNT 2 +#define PLAT_MARVELL_CLUSTER_COUNT U(2) +#define PLAT_MARVELL_CLUSTER_CORE_COUNT U(2) #define PLAT_MARVELL_CORE_COUNT (PLAT_MARVELL_CLUSTER_COUNT * \ PLAT_MARVELL_CLUSTER_CORE_COUNT) -- cgit v1.2.3 From dc2d366fac42f0698650a6479298a44cd357bacb Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:50:36 -0600 Subject: intel: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: Id3d3efc7e7711d19f0223da823713b8390ad2f47 --- plat/intel/soc/common/include/platform_def.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index 8d04479df..8a681e69d 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -57,13 +57,13 @@ #define PLAT_MAX_PWR_LVL 1 #define PLAT_MAX_RET_STATE 1 #define PLAT_MAX_OFF_STATE 2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) /* Interrupt related constant */ -- cgit v1.2.3 From 4dc3a9612285d82aba9873e116a771a33ee7b65c Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:50:55 -0600 Subject: mediatek: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: Iee98ded027c049d9f12d4bb5888c0496b3251b4e --- plat/mediatek/mt6795/include/platform_def.h | 12 ++++++------ plat/mediatek/mt8173/include/platform_def.h | 12 ++++++------ plat/mediatek/mt8183/include/platform_def.h | 10 +++++----- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/plat/mediatek/mt6795/include/platform_def.h b/plat/mediatek/mt6795/include/platform_def.h index 301610d4c..b353a3d3b 100644 --- a/plat/mediatek/mt6795/include/platform_def.h +++ b/plat/mediatek/mt6795/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -145,13 +145,13 @@ #define PLAT_MAX_OFF_STATE U(2) #define PLATFORM_CACHE_LINE_SIZE 64 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 4 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/mediatek/mt8173/include/platform_def.h b/plat/mediatek/mt8173/include/platform_def.h index 205e26387..22129db13 100644 --- a/plat/mediatek/mt8173/include/platform_def.h +++ b/plat/mediatek/mt8173/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,13 +40,13 @@ #define PLAT_MAX_PWR_LVL U(2) #define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_OFF_STATE U(2) -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 2 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(2) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h index ad81a3331..49a0f805e 100644 --- a/plat/mediatek/mt8183/include/platform_def.h +++ b/plat/mediatek/mt8183/include/platform_def.h @@ -268,13 +268,13 @@ INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ #define PLAT_MAX_OFF_STATE U(2) #define PLATFORM_CACHE_LINE_SIZE 64 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 4 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) -- cgit v1.2.3 From 50dae22e250f1f7f3506098521ed831fb4a7e3e5 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:51:28 -0600 Subject: socionext: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: Iad91e99e9d13254de23eb10e5f655253f253cf0d --- plat/socionext/synquacer/include/platform_def.h | 6 +++--- plat/socionext/uniphier/include/platform_def.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/plat/socionext/synquacer/include/platform_def.h b/plat/socionext/synquacer/include/platform_def.h index 7e54b39d8..7158bfaf3 100644 --- a/plat/socionext/synquacer/include/platform_def.h +++ b/plat/socionext/synquacer/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,8 +11,8 @@ #include /* CPU topology */ -#define PLAT_MAX_CORES_PER_CLUSTER 2 -#define PLAT_CLUSTER_COUNT 12 +#define PLAT_MAX_CORES_PER_CLUSTER U(2) +#define PLAT_CLUSTER_COUNT U(12) #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ PLAT_MAX_CORES_PER_CLUSTER) diff --git a/plat/socionext/uniphier/include/platform_def.h b/plat/socionext/uniphier/include/platform_def.h index d4db3f5b0..f5e761122 100644 --- a/plat/socionext/uniphier/include/platform_def.h +++ b/plat/socionext/uniphier/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,8 +17,8 @@ #define CACHE_WRITEBACK_GRANULE (1 << (CACHE_WRITEBACK_SHIFT)) /* topology */ -#define UNIPHIER_MAX_CPUS_PER_CLUSTER 4 -#define UNIPHIER_CLUSTER_COUNT 2 +#define UNIPHIER_MAX_CPUS_PER_CLUSTER U(4) +#define UNIPHIER_CLUSTER_COUNT U(2) #define PLATFORM_CORE_COUNT \ ((UNIPHIER_MAX_CPUS_PER_CLUSTER) * (UNIPHIER_CLUSTER_COUNT)) -- cgit v1.2.3 From 645ac02dd6f17fe7e59d5d858529e13be2c97df5 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:52:14 -0600 Subject: qemu: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: I460b35f5a4ec47b13d4e811bb20881ce314e9259 --- plat/qemu/qemu/include/platform_def.h | 12 ++++++------ plat/qemu/qemu_sbsa/include/platform_def.h | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h index c6b4db506..cce992ff9 100644 --- a/plat/qemu/qemu/include/platform_def.h +++ b/plat/qemu/qemu/include/platform_def.h @@ -18,20 +18,20 @@ #define PLATFORM_STACK_SIZE 0x1000 #if ARM_ARCH_MAJOR == 7 -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #else -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(2) #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #endif #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ PLATFORM_CLUSTER1_CORE_COUNT) -#define QEMU_PRIMARY_CPU 0 +#define QEMU_PRIMARY_CPU U(0) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h index 333b21cc1..f44b9f6e0 100644 --- a/plat/qemu/qemu_sbsa/include/platform_def.h +++ b/plat/qemu/qemu_sbsa/include/platform_def.h @@ -15,14 +15,14 @@ #define PLATFORM_STACK_SIZE 0x1000 -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(2) #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ PLATFORM_CLUSTER1_CORE_COUNT) -#define QEMU_PRIMARY_CPU 0 +#define QEMU_PRIMARY_CPU U(0) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) -- cgit v1.2.3 From 08a64471aaf67830da2232eb7735e24e4f1fa332 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:52:43 -0600 Subject: layerscape: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: Ib9f97be1972405e54dc9550266f5b8a6a55b93bf --- plat/layerscape/board/ls1043/include/platform_def.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/plat/layerscape/board/ls1043/include/platform_def.h b/plat/layerscape/board/ls1043/include/platform_def.h index b6130001c..8b0a94ae3 100644 --- a/plat/layerscape/board/ls1043/include/platform_def.h +++ b/plat/layerscape/board/ls1043/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,18 +19,18 @@ #define FIRMWARE_WELCOME_STR_LS1043_BL32 "Welcome to LS1043 BL32 Phase, TSP\n" /* Required platform porting definitions */ -#define PLAT_PRIMARY_CPU 0x0 +#define PLAT_PRIMARY_CPU U(0x0) #define PLAT_MAX_PWR_LVL LS_PWR_LVL1 -#define PLATFORM_CORE_COUNT 4 +#define PLATFORM_CORE_COUNT U(4) #define COUNTER_FREQUENCY 25000000 /* 25MHz */ /* * Required LS standard platform porting definitions */ -#define PLAT_LS_CLUSTER_COUNT 1 -#define PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX 4 -#define LS1043_CLUSTER_COUNT 1 -#define LS1043_MAX_CPUS_PER_CLUSTER 4 +#define PLAT_LS_CLUSTER_COUNT U(1) +#define PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX U(4) +#define LS1043_CLUSTER_COUNT U(1) +#define LS1043_MAX_CPUS_PER_CLUSTER U(4) #define LS_DRAM1_BASE 0x80000000 #define LS_DRAM2_BASE 0x880000000 -- cgit v1.2.3 From f4f1d88dff3b614e9cd1d654139b2c4398bf8415 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:53:12 -0600 Subject: st: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: I3421336230981d4cda301fa2cef24b94b08353b1 --- plat/st/stm32mp1/include/platform_def.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h index 450a9d404..27ba6f7f9 100644 --- a/plat/st/stm32mp1/include/platform_def.h +++ b/plat/st/stm32mp1/include/platform_def.h @@ -41,7 +41,7 @@ #define STM32MP_PRIMARY_CPU U(0x0) #define STM32MP_SECONDARY_CPU U(0x1) -#define PLATFORM_CLUSTER_COUNT ULL(1) +#define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CLUSTER0_CORE_COUNT U(2) #define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ -- cgit v1.2.3 From 79fadd8f36f90b29386d3dd7d23bae016d4b8671 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:53:34 -0600 Subject: ti: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: Ia7072d82116b03904c1b3982f37d96347203e621 --- plat/ti/k3/board/generic/include/board_def.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h index 490b975f4..c1a5966d5 100644 --- a/plat/ti/k3/board/generic/include/board_def.h +++ b/plat/ti/k3/board/generic/include/board_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +10,10 @@ #include /* The ports must be in order and contiguous */ -#define K3_CLUSTER0_CORE_COUNT 2 -#define K3_CLUSTER1_CORE_COUNT 2 -#define K3_CLUSTER2_CORE_COUNT 2 -#define K3_CLUSTER3_CORE_COUNT 2 +#define K3_CLUSTER0_CORE_COUNT U(2) +#define K3_CLUSTER1_CORE_COUNT U(2) +#define K3_CLUSTER2_CORE_COUNT U(2) +#define K3_CLUSTER3_CORE_COUNT U(2) /* * This RAM will be used for the bootloader including code, bss, and stacks. -- cgit v1.2.3 From d986bae4e2a8bf0f4e31009d6b4a37809e9a4809 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:44:20 +0900 Subject: Build: support per-BL LDFLAGS make_helpers/build_macros.mk supports per-BL CFLAGS. For example, you can pass compiler flags only to BL31 by using BL31_CFLAGS. This commit adds per-BL LDFLAGS support, which is useful as well. My main motivation of this addition is to use it for ENABLE_PIE. When ENABLE_PIE is enabled, some linker flags are added to TF_LDFLAGS, which affects all the TF images. It will make more sense to pass the relevant options only to BL images that support it. Change-Id: I203acaab0091db5ae0ea6e66460ee7dc8d9c4d75 Signed-off-by: Masahiro Yamada --- make_helpers/build_macros.mk | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index 6b72cfd0d..1fa26cc2b 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -412,6 +412,7 @@ bl${1}_dirs: | ${OBJ_DIRS} $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES),$(1))) $(eval $(call MAKE_LD,$(LINKERFILE),$(BL_LINKERFILE),$(1))) +$(eval BL_LDFLAGS := $(BL$(call uppercase,$(1))_LDFLAGS)) ifeq ($(USE_ROMLIB),1) $(ELF): romlib.bin @@ -427,7 +428,7 @@ else $$(CC) $$(TF_CFLAGS) $$(CFLAGS) -xc -c - -o $(BUILD_DIR)/build_message.o endif ifneq ($(findstring armlink,$(notdir $(LD))),) - $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) --entry=bl${1}_entrypoint \ + $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) --entry=bl${1}_entrypoint \ --predefine="-D__LINKER__=$(__LINKER__)" \ --predefine="-DTF_CFLAGS=$(TF_CFLAGS)" \ --map --list="$(MAPFILE)" --scatter=${PLAT_DIR}/scat/bl${1}.scat \ @@ -438,7 +439,7 @@ else ifneq ($(findstring gcc,$(notdir $(LD))),) -Wl,-T$(LINKERFILE) $(BUILD_DIR)/build_message.o \ $(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) else - $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) -Map=$(MAPFILE) \ + $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) -Map=$(MAPFILE) \ --script $(LINKERFILE) $(BUILD_DIR)/build_message.o \ $(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) endif -- cgit v1.2.3 From 320920c15f7b828e34f874c4afb8fa78a3dccb71 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:44:37 +0900 Subject: PIE: pass PIE options only to BL31 docs/getting_started/build-options.rst clearly says ENABLE_PIE is currently only supported in BL31, but in fact, it has a stronger limitation: Defining ENABLE_PIE may corrupt BL1 and BL2. So, ENABLE_PIE is supported only for platforms where BL31 is the only image built in the TF-A tree. Currently, ENABLE_PIE is enabled by two platforms, plat/arm/common/arm_common.mk and ti/k3/common/plat_common.mk, both of which enable ENABLE_PIE together with RESET_TO_BL31. For platforms with the full boot sequence, ENABLE_PIE may break earlier BL stages. For example, if I build PLAT=qemu with ENABLE_PIE=1, it fails in BL1. When ENABLE_PIE is enabled, PIE options are added to TF_CFLAGS and TF_LDFLAGS, so all BL images are affected. It is problematic because currently only the BL31 linker script handles it. Even if BL1/BL2 works, the image size would increase needlessly, at least. Pass the PIE options only to BL images that support it. Change-Id: I550e95148aa3c63571c8ad2081082c554a848f57 Signed-off-by: Masahiro Yamada --- Makefile | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/Makefile b/Makefile index c740993f4..89653b72d 100644 --- a/Makefile +++ b/Makefile @@ -452,18 +452,20 @@ ifeq (${ARM_ARCH_MAJOR},7) include make_helpers/armv7-a-cpus.mk endif -ifeq ($(ENABLE_PIE),1) - TF_CFLAGS += -fpie - ifneq ($(findstring gcc,$(notdir $(LD))),) - TF_LDFLAGS += -Wl,-pie -Wl,--no-dynamic-linker - else - TF_LDFLAGS += -pie --no-dynamic-linker - endif +PIE_FOUND := $(findstring --enable-default-pie,${GCC_V_OUTPUT}) +ifneq ($(PIE_FOUND),) + TF_CFLAGS += -fno-PIE +endif + +ifneq ($(findstring gcc,$(notdir $(LD))),) + PIE_LDFLAGS += -Wl,-pie -Wl,--no-dynamic-linker else - PIE_FOUND := $(findstring --enable-default-pie,${GCC_V_OUTPUT}) - ifneq ($(PIE_FOUND),) - TF_CFLAGS += -fno-PIE - endif + PIE_LDFLAGS += -pie --no-dynamic-linker +endif + +ifeq ($(ENABLE_PIE),1) + BL31_CFLAGS += -fpie + BL31_LDFLAGS += $(PIE_LDFLAGS) endif # Include the CPU specific operations makefile, which provides default -- cgit v1.2.3 From 511046eaa28f89d0ae1d8577bc940ad02d129f19 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:44:50 +0900 Subject: BL31: discard .dynsym .dynstr .hash sections to make ENABLE_PIE work When I tried ENABLE_PIE for my PLAT=uniphier platform, BL31 crashed at its entry. When it is built with ENABLE_PIE=1, some sections are inserted before the executable code. $ make PLAT=uniphier CROSS_COMPILE=aarch64-linux-gnu- ENABLE_PIE=1 bl31 $ aarch64-linux-gnu-objdump -h build/uniphier/release/bl31/bl31.elf | head -n 13 build/uniphier/release/bl31/bl31.elf: file format elf64-littleaarch64 Sections: Idx Name Size VMA LMA File off Algn 0 .dynsym 000002a0 0000000081000000 0000000081000000 00010000 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .dynstr 000002a0 00000000810002a0 00000000810002a0 000102a0 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 2 .hash 00000124 0000000081000540 0000000081000540 00010540 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 ro 0000699c 0000000081000664 0000000081000664 00010664 2**11 CONTENTS, ALLOC, LOAD, CODE The previous stage loader generally jumps over to the base address of BL31, where no valid instruction exists. I checked the linker script of Linux (arch/arm64/kernel/vmlinux.lds.S) and U-Boot (arch/arm/cpu/armv8/u-boot.lds), both of which support relocation. They simply discard those sections. Do similar in TF-A too. Change-Id: I6c33e9143856765d4ffa24f3924b0ab51a17cde9 Signed-off-by: Masahiro Yamada --- bl31/bl31.ld.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 42227f0f3..c7185a893 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -339,6 +339,10 @@ SECTIONS __RW_END__ = .; __BL31_END__ = .; + /DISCARD/ : { + *(.dynsym .dynstr .hash .gnu.hash) + } + ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") #endif } -- cgit v1.2.3 From 69af7fcf99bcce85ed218c97df0b76c377b3ed16 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:45:02 +0900 Subject: BL2_AT_EL3: add PIE support This implementation simply mimics that of BL31. I did not implement the ENABLE_PIE support for BL2_IN_XIP_MEM=1 case. It would make the linker script a bit uglier. Change-Id: If3215abd99f2758dfb232e44b50320d04eba808b Signed-off-by: Masahiro Yamada --- Makefile | 6 ++++++ bl2/aarch64/bl2_el3_entrypoint.S | 10 +++++++++- bl2/bl2_el3.ld.S | 35 ++++++++++++++++++++++++++++++++++ docs/getting_started/build-options.rst | 2 +- 4 files changed, 51 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 89653b72d..0193c2983 100644 --- a/Makefile +++ b/Makefile @@ -464,6 +464,12 @@ else endif ifeq ($(ENABLE_PIE),1) +ifeq ($(BL2_AT_EL3),1) +ifneq ($(BL2_IN_XIP_MEM),1) + BL2_CFLAGS += -fpie + BL2_LDFLAGS += $(PIE_LDFLAGS) +endif +endif BL31_CFLAGS += -fpie BL31_LDFLAGS += $(PIE_LDFLAGS) endif diff --git a/bl2/aarch64/bl2_el3_entrypoint.S b/bl2/aarch64/bl2_el3_entrypoint.S index 2ca6acf28..4eab39cd3 100644 --- a/bl2/aarch64/bl2_el3_entrypoint.S +++ b/bl2/aarch64/bl2_el3_entrypoint.S @@ -4,6 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include + #include #include #include @@ -13,6 +15,12 @@ .globl bl2_el3_run_image .globl bl2_run_next_image +#if BL2_IN_XIP_MEM +#define FIXUP_SIZE 0 +#else +#define FIXUP_SIZE ((BL2_LIMIT) - (BL2_BASE)) +#endif + func bl2_entrypoint /* Save arguments x0-x3 from previous Boot loader */ mov x20, x0 @@ -27,7 +35,7 @@ func bl2_entrypoint _init_memory=1 \ _init_c_runtime=1 \ _exception_vectors=bl2_el3_exceptions \ - _pie_fixup_size=0 + _pie_fixup_size=FIXUP_SIZE /* --------------------------------------------- * Restore parameters of boot rom diff --git a/bl2/bl2_el3.ld.S b/bl2/bl2_el3.ld.S index dc398eb02..b6570ee3e 100644 --- a/bl2/bl2_el3.ld.S +++ b/bl2/bl2_el3.ld.S @@ -69,6 +69,16 @@ SECTIONS KEEP(*(cpu_ops)) __CPU_OPS_END__ = .; + /* + * Keep the .got section in the RO section as it is patched + * prior to enabling the MMU and having the .got in RO is better for + * security. GOT is a table of addresses so ensure 8-byte alignment. + */ + . = ALIGN(8); + __GOT_START__ = .; + *(.got) + __GOT_END__ = .; + . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; } >ROM @@ -100,6 +110,16 @@ SECTIONS KEEP(*(.img_parser_lib_descs)) __PARSER_LIB_DESCS_END__ = .; + /* + * Keep the .got section in the RO section as it is patched + * prior to enabling the MMU and having the .got in RO is better for + * security. GOT is a table of addresses so ensure 8-byte alignment. + */ + . = ALIGN(8); + __GOT_START__ = .; + *(.got) + __GOT_END__ = .; + *(.vectors) __RO_END_UNALIGNED__ = .; /* @@ -139,6 +159,17 @@ SECTIONS __DATA_RAM_END__ = .; } >RAM AT>ROM + /* + * .rela.dyn needs to come after .data for the read-elf utility to parse + * this section correctly. Ensure 8-byte alignment so that the fields of + * RELA data structure are aligned. + */ + . = ALIGN(8); + __RELA_START__ = .; + .rela.dyn . : { + } >RAM + __RELA_END__ = .; + stacks (NOLOAD) : { __STACKS_START__ = .; *(tzfw_normal_stacks) @@ -195,6 +226,10 @@ SECTIONS __RW_END__ = .; __BL2_END__ = .; + /DISCARD/ : { + *(.dynsym .dynstr .hash .gnu.hash) + } + #if BL2_IN_XIP_MEM __BL2_RAM_START__ = ADDR(.data); __BL2_RAM_END__ = .; diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index d7bb0449e..cac7e316b 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -213,7 +213,7 @@ Common build options - ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) support within generic code in TF-A. This option is currently only supported - in BL31. Default is 0. + in BL2_AT_EL3 and BL31. Default is 0. - ``ENABLE_PMF``: Boolean option to enable support for optional Performance Measurement Framework(PMF). Default is 0. -- cgit v1.2.3 From d974301d221762a7a0c24bf1d682fa8fe198a83d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:45:14 +0900 Subject: TSP: add PIE support This implementation simply mimics that of BL31. Change-Id: Ibbaa4ca012d38ac211c52b0b3e97449947160e07 Signed-off-by: Masahiro Yamada --- Makefile | 4 ++++ bl32/tsp/aarch64/tsp_entrypoint.S | 22 ++++++++++++++++++- bl32/tsp/tsp.ld.S | 40 +++++++++++++++++++++++++++++++++- docs/getting_started/build-options.rst | 2 +- 4 files changed, 65 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 0193c2983..bd52c0bd7 100644 --- a/Makefile +++ b/Makefile @@ -472,6 +472,10 @@ endif endif BL31_CFLAGS += -fpie BL31_LDFLAGS += $(PIE_LDFLAGS) +ifeq ($(ARCH),aarch64) + BL32_CFLAGS += -fpie + BL32_LDFLAGS += $(PIE_LDFLAGS) +endif endif # Include the CPU specific operations makefile, which provides default diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 1d3ec21a7..ebc5c2c3d 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -1,9 +1,11 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include + #include #include #include @@ -46,6 +48,24 @@ func tsp_entrypoint _align=3 +#if ENABLE_PIE + /* + * ------------------------------------------------------------ + * If PIE is enabled fixup the Global descriptor Table only + * once during primary core cold boot path. + * + * Compile time base address, required for fixup, is calculated + * using "pie_fixup" label present within first page. + * ------------------------------------------------------------ + */ + pie_fixup: + ldr x0, =pie_fixup + and x0, x0, #~(PAGE_SIZE - 1) + mov_imm x1, (BL32_LIMIT - BL32_BASE) + add x1, x1, x0 + bl fixup_gdt_reloc +#endif /* ENABLE_PIE */ + /* --------------------------------------------- * Set the exception vector to something sane. * --------------------------------------------- diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index e9a1df168..592e24557 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -36,6 +36,17 @@ SECTIONS .rodata . : { __RODATA_START__ = .; *(.rodata*) + + /* + * Keep the .got section in the RO section as it is patched + * prior to enabling the MMU and having the .got in RO is better for + * security. GOT is a table of addresses so ensure 8-byte alignment. + */ + . = ALIGN(8); + __GOT_START__ = .; + *(.got) + __GOT_END__ = .; + . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; } >RAM @@ -45,7 +56,19 @@ SECTIONS *tsp_entrypoint.o(.text*) *(.text*) *(.rodata*) + + /* + * Keep the .got section in the RO section as it is patched + * prior to enabling the MMU and having the .got in RO is better for + * security. GOT is a table of addresses so ensure 8-byte alignment. + */ + . = ALIGN(8); + __GOT_START__ = .; + *(.got) + __GOT_END__ = .; + *(.vectors) + __RO_END_UNALIGNED__ = .; /* * Memory page(s) mapped to this section will be marked as @@ -69,6 +92,17 @@ SECTIONS __DATA_END__ = .; } >RAM + /* + * .rela.dyn needs to come after .data for the read-elf utility to parse + * this section correctly. Ensure 8-byte alignment so that the fields of + * RELA data structure are aligned. + */ + . = ALIGN(8); + __RELA_START__ = .; + .rela.dyn . : { + } >RAM + __RELA_END__ = .; + #ifdef TSP_PROGBITS_LIMIT ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.") #endif @@ -129,6 +163,10 @@ SECTIONS __RW_END__ = .; __BL32_END__ = .; + /DISCARD/ : { + *(.dynsym .dynstr .hash .gnu.hash) + } + __BSS_SIZE__ = SIZEOF(.bss); #if USE_COHERENT_MEM __COHERENT_RAM_UNALIGNED_SIZE__ = diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index cac7e316b..fc4545571 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -213,7 +213,7 @@ Common build options - ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) support within generic code in TF-A. This option is currently only supported - in BL2_AT_EL3 and BL31. Default is 0. + in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0. - ``ENABLE_PMF``: Boolean option to enable support for optional Performance Measurement Framework(PMF). Default is 0. -- cgit v1.2.3 From 66b9d8890c6deaa017ea010b5883f61e6f253b4c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:45:32 +0900 Subject: uniphier: turn on ENABLE_PIE Now that various issues in the PIE support have been fixed, this platform can enable ENABLE_PIE. I tested BL2_AT_EL3, BL31, TSP, and all of them worked. Change-Id: Ibc499c6bad30b7f81a42bfa7e435ce25f820bd9c Signed-off-by: Masahiro Yamada --- plat/socionext/uniphier/platform.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk index d31fbe88f..3c74fe651 100644 --- a/plat/socionext/uniphier/platform.mk +++ b/plat/socionext/uniphier/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -9,6 +9,7 @@ override COLD_BOOT_SINGLE_CPU := 1 override PROGRAMMABLE_RESET_ADDRESS := 1 override USE_COHERENT_MEM := 1 override ENABLE_SVE_FOR_NS := 0 +override ENABLE_PIE := 1 # Cortex-A53 revision r0p4-51rel0 # needed for LD20, unneeded for LD11, PXs3 (no ACE) -- cgit v1.2.3 From 2c74a29d554826a82f162044ae554f1c6af9bead Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:45:47 +0900 Subject: bl_common: add BL_END macro Currently, the end address macros are defined per BL, like BL2_END, BL31_END, BL32_END. They are not handy in the common code shared between multiple BL stages. This commit introduces BL_END, which is equivalent to BL{2,31,32}_END, and will be useful for the BL-common code. Change-Id: I3c39bf6096d99ce920a5b9fa21c0f65456fbfe8a Signed-off-by: Masahiro Yamada --- include/common/bl_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 896a03f0a..77fb1f679 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -106,6 +106,7 @@ IMPORT_SYM(uintptr_t, __RODATA_END__, BL_RO_DATA_END); IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(uintptr_t, __RO_END__, BL_CODE_END); #endif +IMPORT_SYM(uintptr_t, __RW_END__, BL_END); #if defined(IMAGE_BL1) IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END); -- cgit v1.2.3 From b5dd85f2c999caa7302d638e516858549ea049ad Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:46:02 +0900 Subject: uniphier: use more mmap_add_dynamic_region() for loading images Currently, uniphier_bl2_mmap hard-codes the memory region needed for loading other images. Towards the goal of making this really position-independent, call mmap_add_dynamic_region() before that region gets accessed. Change-Id: Ieb505b91ccf2483e5f1a280accda564b33f19f11 Signed-off-by: Masahiro Yamada --- plat/socionext/uniphier/include/platform_def.h | 11 ++----- plat/socionext/uniphier/uniphier.h | 14 ++------- plat/socionext/uniphier/uniphier_bl2_setup.c | 40 +++++++++++++++++--------- plat/socionext/uniphier/uniphier_io_storage.c | 9 +++++- 4 files changed, 40 insertions(+), 34 deletions(-) diff --git a/plat/socionext/uniphier/include/platform_def.h b/plat/socionext/uniphier/include/platform_def.h index f5e761122..30e0924b5 100644 --- a/plat/socionext/uniphier/include/platform_def.h +++ b/plat/socionext/uniphier/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,11 +33,6 @@ /* 0x80080000-0x81000000: reserved for DSP */ -#define UNIPHIER_SEC_DRAM_BASE 0x81000000ULL -#define UNIPHIER_SEC_DRAM_LIMIT 0x82000000ULL -#define UNIPHIER_SEC_DRAM_SIZE ((UNIPHIER_SEC_DRAM_LIMIT) - \ - (UNIPHIER_SEC_DRAM_BASE)) - #define BL31_BASE ULL(0x81000000) #define BL31_LIMIT ULL(0x81080000) @@ -48,8 +43,8 @@ #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_XLAT_TABLES_DYNAMIC 1 -#define MAX_XLAT_TABLES 7 -#define MAX_MMAP_REGIONS 7 +#define MAX_XLAT_TABLES 9 +#define MAX_MMAP_REGIONS 13 #define MAX_IO_HANDLES 2 #define MAX_IO_DEVICES 2 diff --git a/plat/socionext/uniphier/uniphier.h b/plat/socionext/uniphier/uniphier.h index 648c2b94c..1d3651a03 100644 --- a/plat/socionext/uniphier/uniphier.h +++ b/plat/socionext/uniphier/uniphier.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,12 +67,7 @@ void uniphier_gic_pcpu_init(void); unsigned int uniphier_calc_core_pos(u_register_t mpidr); -#define UNIPHIER_NS_DRAM_BASE 0x84000000 -#define UNIPHIER_NS_DRAM_LIMIT 0x85000000 -#define UNIPHIER_NS_DRAM_SIZE ((UNIPHIER_NS_DRAM_LIMIT) - \ - (UNIPHIER_NS_DRAM_BASE)) - -#define UNIPHIER_BL33_BASE (UNIPHIER_NS_DRAM_BASE) +#define UNIPHIER_BL33_BASE 0x84000000 #define UNIPHIER_BL33_MAX_SIZE 0x00100000 #define UNIPHIER_SCP_BASE ((UNIPHIER_BL33_BASE) + \ @@ -83,9 +78,4 @@ unsigned int uniphier_calc_core_pos(u_register_t mpidr); (UNIPHIER_SCP_MAX_SIZE)) #define UNIPHIER_BLOCK_BUF_SIZE 0x00100000 -#define UNIPHIER_IMAGE_BUF_BASE ((UNIPHIER_BLOCK_BUF_BASE) + \ - (UNIPHIER_BLOCK_BUF_SIZE)) -#define UNIPHIER_IMAGE_BUF_SIZE ((UNIPHIER_NS_DRAM_LIMIT) - \ - (UNIPHIER_IMAGE_BUF_BASE)) - #endif /* UNIPHIER_H */ diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c index 787b3ac3d..74d4fa235 100644 --- a/plat/socionext/uniphier/uniphier_bl2_setup.c +++ b/plat/socionext/uniphier/uniphier_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,6 +23,9 @@ #define BL2_SIZE ((BL2_END) - (BL2_BASE)) +#define UNIPHIER_IMAGE_BUF_BASE 0x84300000UL +#define UNIPHIER_IMAGE_BUF_SIZE 0x00100000UL + static int uniphier_bl2_kick_scp; void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, @@ -31,23 +34,13 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, uniphier_console_setup(); } -static const struct mmap_region uniphier_bl2_mmap[] = { - /* for BL31, BL32 */ - MAP_REGION_FLAT(UNIPHIER_SEC_DRAM_BASE, UNIPHIER_SEC_DRAM_SIZE, - MT_MEMORY | MT_RW | MT_SECURE), - /* for SCP, BL33 */ - MAP_REGION_FLAT(UNIPHIER_NS_DRAM_BASE, UNIPHIER_NS_DRAM_SIZE, - MT_MEMORY | MT_RW | MT_NS), - { .size = 0 }, -}; - void bl2_el3_plat_arch_setup(void) { unsigned int soc; int skip_scp = 0; int ret; - uniphier_mmap_setup(BL2_BASE, BL2_SIZE, uniphier_bl2_mmap); + uniphier_mmap_setup(BL2_BASE, BL2_SIZE, NULL); enable_mmu_el3(0); soc = uniphier_get_soc_id(); @@ -119,6 +112,15 @@ bl_params_t *plat_get_next_bl_params(void) void bl2_plat_preload_setup(void) { #ifdef UNIPHIER_DECOMPRESS_GZIP + int ret; + + ret = mmap_add_dynamic_region(UNIPHIER_IMAGE_BUF_BASE, + UNIPHIER_IMAGE_BUF_BASE, + UNIPHIER_IMAGE_BUF_SIZE, + MT_MEMORY | MT_RW | MT_NS); + if (ret) + plat_error_handler(ret); + image_decompress_init(UNIPHIER_IMAGE_BUF_BASE, UNIPHIER_IMAGE_BUF_SIZE, gunzip); @@ -127,8 +129,20 @@ void bl2_plat_preload_setup(void) int bl2_plat_handle_pre_image_load(unsigned int image_id) { + struct image_info *image_info; + int ret; + + image_info = uniphier_get_image_info(image_id); + + ret = mmap_add_dynamic_region(image_info->image_base, + image_info->image_base, + image_info->image_max_size, + MT_MEMORY | MT_RW | MT_NS); + if (ret) + return ret; + #ifdef UNIPHIER_DECOMPRESS_GZIP - image_decompress_prepare(uniphier_get_image_info(image_id)); + image_decompress_prepare(image_info); #endif return 0; } diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c index b456bc538..c039acc86 100644 --- a/plat/socionext/uniphier/uniphier_io_storage.c +++ b/plat/socionext/uniphier/uniphier_io_storage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -195,6 +195,13 @@ static int uniphier_io_block_setup(size_t fip_offset, uintptr_t block_dev_spec) uniphier_fip_spec.offset = fip_offset; + ret = mmap_add_dynamic_region(UNIPHIER_BLOCK_BUF_BASE, + UNIPHIER_BLOCK_BUF_BASE, + UNIPHIER_BLOCK_BUF_SIZE, + MT_MEMORY | MT_RW | MT_NS); + if (ret) + return ret; + ret = register_io_dev_block(&uniphier_backend_dev_con); if (ret) return ret; -- cgit v1.2.3 From b79b3177d3c0eaf18a595feed82b250ac391a87f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:46:13 +0900 Subject: uniphier: set buffer offset and length for io_block dynamically Currently, the .buffer field in io_block_dev_spec is statically set, which is not handy for PIE. Towards the goal of making this really position-independent, set the buffer length and length in the uniphier_io_block_setup() function. Change-Id: I22b20d7b58d6ffd38f64f967a2820fca4bd7dade Signed-off-by: Masahiro Yamada --- plat/socionext/uniphier/uniphier.h | 12 +++----- plat/socionext/uniphier/uniphier_emmc.c | 12 +++----- plat/socionext/uniphier/uniphier_io_storage.c | 44 ++++++++++++++++----------- plat/socionext/uniphier/uniphier_nand.c | 10 ++---- plat/socionext/uniphier/uniphier_usb.c | 11 +++---- 5 files changed, 42 insertions(+), 47 deletions(-) diff --git a/plat/socionext/uniphier/uniphier.h b/plat/socionext/uniphier/uniphier.h index 1d3651a03..6ccd422de 100644 --- a/plat/socionext/uniphier/uniphier.h +++ b/plat/socionext/uniphier/uniphier.h @@ -36,9 +36,11 @@ unsigned int uniphier_get_boot_master(unsigned int soc); void uniphier_console_setup(void); -int uniphier_emmc_init(uintptr_t *block_dev_spec); -int uniphier_nand_init(uintptr_t *block_dev_spec); -int uniphier_usb_init(unsigned int soc, uintptr_t *block_dev_spec); +struct io_block_dev_spec; +int uniphier_emmc_init(struct io_block_dev_spec **block_dev_spec); +int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec); +int uniphier_usb_init(unsigned int soc, + struct io_block_dev_spec **block_dev_spec); int uniphier_io_setup(unsigned int soc); @@ -74,8 +76,4 @@ unsigned int uniphier_calc_core_pos(u_register_t mpidr); (UNIPHIER_BL33_MAX_SIZE)) #define UNIPHIER_SCP_MAX_SIZE 0x00020000 -#define UNIPHIER_BLOCK_BUF_BASE ((UNIPHIER_SCP_BASE) + \ - (UNIPHIER_SCP_MAX_SIZE)) -#define UNIPHIER_BLOCK_BUF_SIZE 0x00100000 - #endif /* UNIPHIER_H */ diff --git a/plat/socionext/uniphier/uniphier_emmc.c b/plat/socionext/uniphier/uniphier_emmc.c index 4ac1f5108..d666ba781 100644 --- a/plat/socionext/uniphier/uniphier_emmc.c +++ b/plat/socionext/uniphier/uniphier_emmc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -225,11 +225,7 @@ static size_t uniphier_emmc_read(int lba, uintptr_t buf, size_t size) return ret ? 0 : size; } -static const struct io_block_dev_spec uniphier_emmc_dev_spec = { - .buffer = { - .offset = UNIPHIER_BLOCK_BUF_BASE, - .length = UNIPHIER_BLOCK_BUF_SIZE, - }, +static struct io_block_dev_spec uniphier_emmc_dev_spec = { .ops = { .read = uniphier_emmc_read, }, @@ -278,7 +274,7 @@ static int uniphier_emmc_hw_init(void) return 0; } -int uniphier_emmc_init(uintptr_t *block_dev_spec) +int uniphier_emmc_init(struct io_block_dev_spec **block_dev_spec) { int ret; @@ -286,7 +282,7 @@ int uniphier_emmc_init(uintptr_t *block_dev_spec) if (ret) return ret; - *block_dev_spec = (uintptr_t)&uniphier_emmc_dev_spec; + *block_dev_spec = &uniphier_emmc_dev_spec; return 0; } diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c index c039acc86..d15191474 100644 --- a/plat/socionext/uniphier/uniphier_io_storage.c +++ b/plat/socionext/uniphier/uniphier_io_storage.c @@ -26,6 +26,9 @@ #define UNIPHIER_OCM_REGION_BASE 0x30000000ULL #define UNIPHIER_OCM_REGION_SIZE 0x00040000ULL +#define UNIPHIER_BLOCK_BUF_BASE 0x84200000UL +#define UNIPHIER_BLOCK_BUF_SIZE 0x00100000UL + static const io_dev_connector_t *uniphier_fip_dev_con; static uintptr_t uniphier_fip_dev_handle; @@ -189,15 +192,20 @@ static const struct uniphier_io_policy uniphier_io_policies[] = { #endif }; -static int uniphier_io_block_setup(size_t fip_offset, uintptr_t block_dev_spec) +static int uniphier_io_block_setup(size_t fip_offset, + struct io_block_dev_spec *block_dev_spec, + size_t buffer_offset) { int ret; uniphier_fip_spec.offset = fip_offset; - ret = mmap_add_dynamic_region(UNIPHIER_BLOCK_BUF_BASE, - UNIPHIER_BLOCK_BUF_BASE, - UNIPHIER_BLOCK_BUF_SIZE, + block_dev_spec->buffer.offset = buffer_offset; + block_dev_spec->buffer.length = UNIPHIER_BLOCK_BUF_SIZE; + + ret = mmap_add_dynamic_region(block_dev_spec->buffer.offset, + block_dev_spec->buffer.offset, + block_dev_spec->buffer.length, MT_MEMORY | MT_RW | MT_NS); if (ret) return ret; @@ -206,7 +214,7 @@ static int uniphier_io_block_setup(size_t fip_offset, uintptr_t block_dev_spec) if (ret) return ret; - return io_dev_open(uniphier_backend_dev_con, block_dev_spec, + return io_dev_open(uniphier_backend_dev_con, (uintptr_t)block_dev_spec, &uniphier_backend_dev_handle); } @@ -241,38 +249,38 @@ static int uniphier_io_fip_setup(void) return io_dev_open(uniphier_fip_dev_con, 0, &uniphier_fip_dev_handle); } -static int uniphier_io_emmc_setup(unsigned int soc_id) +static int uniphier_io_emmc_setup(unsigned int soc_id, size_t buffer_offset) { - uintptr_t block_dev_spec; + struct io_block_dev_spec *block_dev_spec; int ret; ret = uniphier_emmc_init(&block_dev_spec); if (ret) return ret; - return uniphier_io_block_setup(0x20000, block_dev_spec); + return uniphier_io_block_setup(0x20000, block_dev_spec, buffer_offset); } -static int uniphier_io_nand_setup(unsigned int soc_id) +static int uniphier_io_nand_setup(unsigned int soc_id, size_t buffer_offset) { - uintptr_t block_dev_spec; + struct io_block_dev_spec *block_dev_spec; int ret; ret = uniphier_nand_init(&block_dev_spec); if (ret) return ret; - return uniphier_io_block_setup(0x20000, block_dev_spec); + return uniphier_io_block_setup(0x20000, block_dev_spec, buffer_offset); } -static int uniphier_io_nor_setup(unsigned int soc_id) +static int uniphier_io_nor_setup(unsigned int soc_id, size_t buffer_offset) { return uniphier_io_memmap_setup(0x70000); } -static int uniphier_io_usb_setup(unsigned int soc_id) +static int uniphier_io_usb_setup(unsigned int soc_id, size_t buffer_offset) { - uintptr_t block_dev_spec; + struct io_block_dev_spec *block_dev_spec; int ret; /* use ROM API for loading images from USB storage */ @@ -299,10 +307,10 @@ static int uniphier_io_usb_setup(unsigned int soc_id) if (ret) return ret; - return uniphier_io_block_setup(0x20000, block_dev_spec); + return uniphier_io_block_setup(0x20000, block_dev_spec, buffer_offset); } -static int (* const uniphier_io_setup_table[])(unsigned int) = { +static int (* const uniphier_io_setup_table[])(unsigned int, size_t) = { [UNIPHIER_BOOT_DEVICE_EMMC] = uniphier_io_emmc_setup, [UNIPHIER_BOOT_DEVICE_NAND] = uniphier_io_nand_setup, [UNIPHIER_BOOT_DEVICE_NOR] = uniphier_io_nor_setup, @@ -311,7 +319,7 @@ static int (* const uniphier_io_setup_table[])(unsigned int) = { int uniphier_io_setup(unsigned int soc_id) { - int (*io_setup)(unsigned int soc_id); + int (*io_setup)(unsigned int soc_id, size_t buffer_offset); unsigned int boot_dev; int ret; @@ -320,7 +328,7 @@ int uniphier_io_setup(unsigned int soc_id) return -EINVAL; io_setup = uniphier_io_setup_table[boot_dev]; - ret = io_setup(soc_id); + ret = io_setup(soc_id, UNIPHIER_BLOCK_BUF_BASE); if (ret) return ret; diff --git a/plat/socionext/uniphier/uniphier_nand.c b/plat/socionext/uniphier/uniphier_nand.c index 27e10e4b7..3925177ed 100644 --- a/plat/socionext/uniphier/uniphier_nand.c +++ b/plat/socionext/uniphier/uniphier_nand.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -224,10 +224,6 @@ static size_t uniphier_nand_read(int lba, uintptr_t buf, size_t size) } static struct io_block_dev_spec uniphier_nand_dev_spec = { - .buffer = { - .offset = UNIPHIER_BLOCK_BUF_BASE, - .length = UNIPHIER_BLOCK_BUF_SIZE, - }, .ops = { .read = uniphier_nand_read, }, @@ -259,7 +255,7 @@ static int uniphier_nand_hw_init(struct uniphier_nand *nand) return 0; } -int uniphier_nand_init(uintptr_t *block_dev_spec) +int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec) { int ret; @@ -269,7 +265,7 @@ int uniphier_nand_init(uintptr_t *block_dev_spec) uniphier_nand_dev_spec.block_size = uniphier_nand.page_size; - *block_dev_spec = (uintptr_t)&uniphier_nand_dev_spec; + *block_dev_spec = &uniphier_nand_dev_spec; return 0; } diff --git a/plat/socionext/uniphier/uniphier_usb.c b/plat/socionext/uniphier/uniphier_usb.c index ef7079a5f..7469ad1cc 100644 --- a/plat/socionext/uniphier/uniphier_usb.c +++ b/plat/socionext/uniphier/uniphier_usb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -158,17 +158,14 @@ static size_t uniphier_usb_read(int lba, uintptr_t buf, size_t size) } static struct io_block_dev_spec uniphier_usb_dev_spec = { - .buffer = { - .offset = UNIPHIER_BLOCK_BUF_BASE, - .length = UNIPHIER_BLOCK_BUF_SIZE, - }, .ops = { .read = uniphier_usb_read, }, .block_size = 512, }; -int uniphier_usb_init(unsigned int soc, uintptr_t *block_dev_spec) +int uniphier_usb_init(unsigned int soc, + struct io_block_dev_spec **block_dev_spec) { const struct uniphier_usb_rom_param *param; @@ -180,7 +177,7 @@ int uniphier_usb_init(unsigned int soc, uintptr_t *block_dev_spec) __uniphier_usb_read = param->read; - *block_dev_spec = (uintptr_t)&uniphier_usb_dev_spec; + *block_dev_spec = &uniphier_usb_dev_spec; return 0; } -- cgit v1.2.3 From 577b24411accd329d11c7d918d9104498d9a4e1a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:46:23 +0900 Subject: uniphier: pass SCP base address as a function parameter Currently, UNIPHIER_SCP_BASE is hard-coded in uniphier_scp_start(), which is not handy for PIE. Towards the goal of making this really position-independent, pass in image_info->image_base. Change-Id: I88e020a1919c607b1d5ce70b116201d95773bb63 Signed-off-by: Masahiro Yamada --- plat/socionext/uniphier/uniphier.h | 2 +- plat/socionext/uniphier/uniphier_bl2_setup.c | 6 ++---- plat/socionext/uniphier/uniphier_scp.c | 6 +++--- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/plat/socionext/uniphier/uniphier.h b/plat/socionext/uniphier/uniphier.h index 6ccd422de..698f3ebd9 100644 --- a/plat/socionext/uniphier/uniphier.h +++ b/plat/socionext/uniphier/uniphier.h @@ -48,7 +48,7 @@ struct image_info; struct image_info *uniphier_get_image_info(unsigned int image_id); int uniphier_scp_is_running(void); -void uniphier_scp_start(void); +void uniphier_scp_start(uint32_t scp_base); void uniphier_scp_open_com(void); void uniphier_scp_system_off(void); void uniphier_scp_system_reset(void); diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c index 74d4fa235..2132bdd0d 100644 --- a/plat/socionext/uniphier/uniphier_bl2_setup.c +++ b/plat/socionext/uniphier/uniphier_bl2_setup.c @@ -149,12 +149,10 @@ int bl2_plat_handle_pre_image_load(unsigned int image_id) int bl2_plat_handle_post_image_load(unsigned int image_id) { + struct image_info *image_info = uniphier_get_image_info(image_id); #ifdef UNIPHIER_DECOMPRESS_GZIP - struct image_info *image_info; int ret; - image_info = uniphier_get_image_info(image_id); - if (!(image_info->h.attr & IMAGE_ATTRIB_SKIP_LOADING)) { ret = image_decompress(uniphier_get_image_info(image_id)); if (ret) @@ -163,7 +161,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) #endif if (image_id == SCP_BL2_IMAGE_ID && uniphier_bl2_kick_scp) - uniphier_scp_start(); + uniphier_scp_start(image_info->image_base); return 0; } diff --git a/plat/socionext/uniphier/uniphier_scp.c b/plat/socionext/uniphier/uniphier_scp.c index c608a255a..8a12d5d8d 100644 --- a/plat/socionext/uniphier/uniphier_scp.c +++ b/plat/socionext/uniphier/uniphier_scp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,11 +28,11 @@ int uniphier_scp_is_running(void) return mmio_read_32(UNIPHIER_STMBE2COM) == UNIPHIER_SCP_READY_MAGIC; } -void uniphier_scp_start(void) +void uniphier_scp_start(uint32_t scp_base) { uint32_t tmp; - mmio_write_32(UNIPHIER_STMBE2COM + 4, UNIPHIER_SCP_BASE); + mmio_write_32(UNIPHIER_STMBE2COM + 4, scp_base); mmio_write_32(UNIPHIER_STMBE2COM, UNIPHIER_SCP_READY_MAGIC); do { -- cgit v1.2.3 From c64873ab94cbb7cc7860ed348f0c55a9dec146e4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:46:38 +0900 Subject: uniphier: make uniphier_mmap_setup() work with PIE BL2_BASE, BL31_BASE, and BL32_BASE are defined in platform_def.h, that is, determined at link-time. On the other hand, BL2_END, BL31_END, and BL32_END are derived from the symbols produced by the linker scripts. So, they are fixed-up at run-time if ENABLE_PIE is enabled. To make it work in a position-indepenent manner, use BL_CODE_BASE and BL_END, both of which are relocatable. Change-Id: Ic179a7c60eb64c5f3024b178690b3ac7cbd7521b Signed-off-by: Masahiro Yamada --- plat/socionext/uniphier/tsp/uniphier_tsp_setup.c | 6 ++---- plat/socionext/uniphier/uniphier.h | 4 +--- plat/socionext/uniphier/uniphier_bl2_setup.c | 4 +--- plat/socionext/uniphier/uniphier_bl31_setup.c | 6 ++---- plat/socionext/uniphier/uniphier_xlat_setup.c | 15 +++++---------- 5 files changed, 11 insertions(+), 24 deletions(-) diff --git a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c index 0b232e067..4f58b683c 100644 --- a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c +++ b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,8 +11,6 @@ #include "../uniphier.h" -#define BL32_SIZE ((BL32_END) - (BL32_BASE)) - void tsp_early_platform_setup(void) { uniphier_console_setup(); @@ -24,6 +22,6 @@ void tsp_platform_setup(void) void tsp_plat_arch_setup(void) { - uniphier_mmap_setup(BL32_BASE, BL32_SIZE, NULL); + uniphier_mmap_setup(); enable_mmu_el1(0); } diff --git a/plat/socionext/uniphier/uniphier.h b/plat/socionext/uniphier/uniphier.h index 698f3ebd9..bbbcf7ee3 100644 --- a/plat/socionext/uniphier/uniphier.h +++ b/plat/socionext/uniphier/uniphier.h @@ -53,9 +53,7 @@ void uniphier_scp_open_com(void); void uniphier_scp_system_off(void); void uniphier_scp_system_reset(void); -struct mmap_region; -void uniphier_mmap_setup(uintptr_t total_base, size_t total_size, - const struct mmap_region *mmap); +void uniphier_mmap_setup(void); void uniphier_cci_init(unsigned int soc); void uniphier_cci_enable(void); diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c index 2132bdd0d..15022b3ea 100644 --- a/plat/socionext/uniphier/uniphier_bl2_setup.c +++ b/plat/socionext/uniphier/uniphier_bl2_setup.c @@ -21,8 +21,6 @@ #include "uniphier.h" -#define BL2_SIZE ((BL2_END) - (BL2_BASE)) - #define UNIPHIER_IMAGE_BUF_BASE 0x84300000UL #define UNIPHIER_IMAGE_BUF_SIZE 0x00100000UL @@ -40,7 +38,7 @@ void bl2_el3_plat_arch_setup(void) int skip_scp = 0; int ret; - uniphier_mmap_setup(BL2_BASE, BL2_SIZE, NULL); + uniphier_mmap_setup(); enable_mmu_el3(0); soc = uniphier_get_soc_id(); diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c index 440e6aa11..47f2378bc 100644 --- a/plat/socionext/uniphier/uniphier_bl31_setup.c +++ b/plat/socionext/uniphier/uniphier_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,8 +19,6 @@ #include "uniphier.h" -#define BL31_SIZE ((BL31_END) - (BL31_BASE)) - static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; @@ -81,6 +79,6 @@ void bl31_platform_setup(void) void bl31_plat_arch_setup(void) { - uniphier_mmap_setup(BL31_BASE, BL31_SIZE, NULL); + uniphier_mmap_setup(); enable_mmu_el3(0); } diff --git a/plat/socionext/uniphier/uniphier_xlat_setup.c b/plat/socionext/uniphier/uniphier_xlat_setup.c index 0faebc993..18d2f9e93 100644 --- a/plat/socionext/uniphier/uniphier_xlat_setup.c +++ b/plat/socionext/uniphier/uniphier_xlat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,13 +12,12 @@ #define UNIPHIER_REG_REGION_BASE 0x50000000ULL #define UNIPHIER_REG_REGION_SIZE 0x20000000ULL -void uniphier_mmap_setup(uintptr_t total_base, size_t total_size, - const struct mmap_region *mmap) +void uniphier_mmap_setup(void) { VERBOSE("Trusted RAM seen by this BL image: %p - %p\n", - (void *)total_base, (void *)(total_base + total_size)); - mmap_add_region(total_base, total_base, - total_size, + (void *)BL_CODE_BASE, (void *)BL_END); + mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, + round_up(BL_END, PAGE_SIZE) - BL_CODE_BASE, MT_MEMORY | MT_RW | MT_SECURE); /* remap the code section */ @@ -40,9 +39,5 @@ void uniphier_mmap_setup(uintptr_t total_base, size_t total_size, UNIPHIER_REG_REGION_SIZE, MT_DEVICE | MT_RW | MT_SECURE); - /* additional regions if needed */ - if (mmap) - mmap_add(mmap); - init_xlat_tables(); } -- cgit v1.2.3 From 7af2131787ed1e5a4fea17f17d13967d13f7d9ee Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Jan 2020 13:46:48 +0900 Subject: uniphier: make all BL images completely position-independent This platform supports multiple SoCs. The next SoC will still keep quite similar architecture, but the memory base will be changed. The ENABLE_PIE improves the maintainability and usability. You can reuse a single set of BL images for other SoC/board without re-compiling TF-A at all. This will also keep the code cleaner because it avoids #ifdef around various base addresses. By defining ENABLE_PIE, BL2_AT_EL3, BL31, and BL32 (TSP) are really position-independent now. You can load them anywhere irrespective of their link address. Change-Id: I8d5e3124ee30012f5b3bfa278b0baff8efd2fff7 Signed-off-by: Masahiro Yamada --- plat/socionext/uniphier/include/platform_def.h | 34 ++++++++++++++++----- plat/socionext/uniphier/platform.mk | 3 ++ plat/socionext/uniphier/uniphier.h | 10 ++----- plat/socionext/uniphier/uniphier_bl2_setup.c | 18 ++++++----- plat/socionext/uniphier/uniphier_image_desc.c | 41 +++++++++++++++++++------- plat/socionext/uniphier/uniphier_io_storage.c | 6 ++-- 6 files changed, 77 insertions(+), 35 deletions(-) diff --git a/plat/socionext/uniphier/include/platform_def.h b/plat/socionext/uniphier/include/platform_def.h index 30e0924b5..7c6341d14 100644 --- a/plat/socionext/uniphier/include/platform_def.h +++ b/plat/socionext/uniphier/include/platform_def.h @@ -28,16 +28,36 @@ #define PLAT_MAX_OFF_STATE U(2) #define PLAT_MAX_RET_STATE U(1) -#define BL2_BASE ULL(0x80000000) -#define BL2_LIMIT ULL(0x80080000) +#define UNIPHIER_BL2_OFFSET UL(0x00000000) +#define UNIPHIER_BL2_MAX_SIZE UL(0x00080000) -/* 0x80080000-0x81000000: reserved for DSP */ +/* 0x00080000-0x01000000: reserved for DSP */ -#define BL31_BASE ULL(0x81000000) -#define BL31_LIMIT ULL(0x81080000) +#define UNIPHIER_BL31_OFFSET UL(0x01000000) +#define UNIPHIER_BL31_MAX_SIZE UL(0x00080000) -#define BL32_BASE ULL(0x81080000) -#define BL32_LIMIT ULL(0x81180000) +#define UNIPHIER_BL32_OFFSET UL(0x01080000) +#define UNIPHIER_BL32_MAX_SIZE UL(0x00100000) + +/* + * The link addresses are determined by UNIPHIER_MEM_BASE + offset. + * When ENABLE_PIE is set, all the TF images can be loaded anywhere, so + * UNIPHIER_MEM_BASE is arbitrary. + * + * When ENABLE_PIE is unset, UNIPHIER_MEM_BASE should be chosen so that + * BL2_BASE matches to the physical address where BL2 is loaded, that is, + * UNIPHIER_MEM_BASE should be the base address of the DRAM region. + */ +#define UNIPHIER_MEM_BASE UL(0x00000000) + +#define BL2_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET) +#define BL2_LIMIT (BL2_BASE + UNIPHIER_BL2_MAX_SIZE) + +#define BL31_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL31_OFFSET) +#define BL31_LIMIT (BL31_BASE + UNIPHIER_BL31_MAX_SIZE) + +#define BL32_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL32_OFFSET) +#define BL32_LIMIT (BL32_BASE + UNIPHIER_BL32_MAX_SIZE) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk index 3c74fe651..8e96b68bb 100644 --- a/plat/socionext/uniphier/platform.mk +++ b/plat/socionext/uniphier/platform.mk @@ -9,6 +9,9 @@ override COLD_BOOT_SINGLE_CPU := 1 override PROGRAMMABLE_RESET_ADDRESS := 1 override USE_COHERENT_MEM := 1 override ENABLE_SVE_FOR_NS := 0 + +# Disabling ENABLE_PIE saves memory footprint a lot, but you need to adjust +# UNIPHIER_MEM_BASE so that all TF images are loaded at their link addresses. override ENABLE_PIE := 1 # Cortex-A53 revision r0p4-51rel0 diff --git a/plat/socionext/uniphier/uniphier.h b/plat/socionext/uniphier/uniphier.h index bbbcf7ee3..729dc5caa 100644 --- a/plat/socionext/uniphier/uniphier.h +++ b/plat/socionext/uniphier/uniphier.h @@ -42,8 +42,9 @@ int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec); int uniphier_usb_init(unsigned int soc, struct io_block_dev_spec **block_dev_spec); -int uniphier_io_setup(unsigned int soc); +int uniphier_io_setup(unsigned int soc, uintptr_t mem_base); +void uniphier_init_image_descs(uintptr_t mem_base); struct image_info; struct image_info *uniphier_get_image_info(unsigned int image_id); @@ -67,11 +68,4 @@ void uniphier_gic_pcpu_init(void); unsigned int uniphier_calc_core_pos(u_register_t mpidr); -#define UNIPHIER_BL33_BASE 0x84000000 -#define UNIPHIER_BL33_MAX_SIZE 0x00100000 - -#define UNIPHIER_SCP_BASE ((UNIPHIER_BL33_BASE) + \ - (UNIPHIER_BL33_MAX_SIZE)) -#define UNIPHIER_SCP_MAX_SIZE 0x00020000 - #endif /* UNIPHIER_H */ diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c index 15022b3ea..11d837cf4 100644 --- a/plat/socionext/uniphier/uniphier_bl2_setup.c +++ b/plat/socionext/uniphier/uniphier_bl2_setup.c @@ -21,9 +21,10 @@ #include "uniphier.h" -#define UNIPHIER_IMAGE_BUF_BASE 0x84300000UL +#define UNIPHIER_IMAGE_BUF_OFFSET 0x04300000UL #define UNIPHIER_IMAGE_BUF_SIZE 0x00100000UL +static uintptr_t uniphier_mem_base = UNIPHIER_MEM_BASE; static int uniphier_bl2_kick_scp; void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, @@ -41,13 +42,16 @@ void bl2_el3_plat_arch_setup(void) uniphier_mmap_setup(); enable_mmu_el3(0); + /* add relocation offset (run-time-address - link-address) */ + uniphier_mem_base += BL_CODE_BASE - BL2_BASE; + soc = uniphier_get_soc_id(); if (soc == UNIPHIER_SOC_UNKNOWN) { ERROR("unsupported SoC\n"); plat_error_handler(-ENOTSUP); } - ret = uniphier_io_setup(soc); + ret = uniphier_io_setup(soc, uniphier_mem_base); if (ret) { ERROR("failed to setup io devices\n"); plat_error_handler(ret); @@ -110,19 +114,19 @@ bl_params_t *plat_get_next_bl_params(void) void bl2_plat_preload_setup(void) { #ifdef UNIPHIER_DECOMPRESS_GZIP + uintptr_t buf_base = uniphier_mem_base + UNIPHIER_IMAGE_BUF_OFFSET; int ret; - ret = mmap_add_dynamic_region(UNIPHIER_IMAGE_BUF_BASE, - UNIPHIER_IMAGE_BUF_BASE, + ret = mmap_add_dynamic_region(buf_base, buf_base, UNIPHIER_IMAGE_BUF_SIZE, MT_MEMORY | MT_RW | MT_NS); if (ret) plat_error_handler(ret); - image_decompress_init(UNIPHIER_IMAGE_BUF_BASE, - UNIPHIER_IMAGE_BUF_SIZE, - gunzip); + image_decompress_init(buf_base, UNIPHIER_IMAGE_BUF_SIZE, gunzip); #endif + + uniphier_init_image_descs(uniphier_mem_base); } int bl2_plat_handle_pre_image_load(unsigned int image_id) diff --git a/plat/socionext/uniphier/uniphier_image_desc.c b/plat/socionext/uniphier/uniphier_image_desc.c index 817029a2c..8c232ba31 100644 --- a/plat/socionext/uniphier/uniphier_image_desc.c +++ b/plat/socionext/uniphier/uniphier_image_desc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,13 +13,19 @@ #include "uniphier.h" +#define UNIPHIER_BL33_OFFSET 0x04000000UL +#define UNIPHIER_BL33_MAX_SIZE 0x00100000UL + +#define UNIPHIER_SCP_OFFSET 0x04100000UL +#define UNIPHIER_SCP_MAX_SIZE 0x00020000UL + static struct bl_mem_params_node uniphier_image_descs[] = { { .image_id = SCP_BL2_IMAGE_ID, SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = UNIPHIER_SCP_BASE, + .image_info.image_base = UNIPHIER_SCP_OFFSET, .image_info.image_max_size = UNIPHIER_SCP_MAX_SIZE, SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, @@ -33,13 +39,13 @@ static struct bl_mem_params_node uniphier_image_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + .image_info.image_base = UNIPHIER_BL31_OFFSET, + .image_info.image_max_size = UNIPHIER_BL31_MAX_SIZE, SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, entry_point_info_t, SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, + .ep_info.pc = UNIPHIER_BL31_OFFSET, .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), @@ -55,13 +61,13 @@ static struct bl_mem_params_node uniphier_image_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + .image_info.image_base = UNIPHIER_BL32_OFFSET, + .image_info.image_max_size = UNIPHIER_BL32_MAX_SIZE, SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), - .ep_info.pc = BL32_BASE, + .ep_info.pc = UNIPHIER_BL32_OFFSET, .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), @@ -73,13 +79,13 @@ static struct bl_mem_params_node uniphier_image_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = UNIPHIER_BL33_BASE, + .image_info.image_base = UNIPHIER_BL33_OFFSET, .image_info.image_max_size = UNIPHIER_BL33_MAX_SIZE, SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), - .ep_info.pc = UNIPHIER_BL33_BASE, + .ep_info.pc = UNIPHIER_BL33_OFFSET, .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), @@ -88,6 +94,21 @@ static struct bl_mem_params_node uniphier_image_descs[] = { }; REGISTER_BL_IMAGE_DESCS(uniphier_image_descs) +/* + * image_info.image_base and ep_info.pc are the offset from the memory base. + * When ENABLE_PIE is set, we never know the real memory base at link-time. + * Fix-up the addresses by adding the run-time detected base. + */ +void uniphier_init_image_descs(uintptr_t mem_base) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(uniphier_image_descs); i++) { + uniphier_image_descs[i].image_info.image_base += mem_base; + uniphier_image_descs[i].ep_info.pc += mem_base; + } +} + struct image_info *uniphier_get_image_info(unsigned int image_id) { struct bl_mem_params_node *desc; diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c index d15191474..89c8718b4 100644 --- a/plat/socionext/uniphier/uniphier_io_storage.c +++ b/plat/socionext/uniphier/uniphier_io_storage.c @@ -26,7 +26,7 @@ #define UNIPHIER_OCM_REGION_BASE 0x30000000ULL #define UNIPHIER_OCM_REGION_SIZE 0x00040000ULL -#define UNIPHIER_BLOCK_BUF_BASE 0x84200000UL +#define UNIPHIER_BLOCK_BUF_OFFSET 0x04200000UL #define UNIPHIER_BLOCK_BUF_SIZE 0x00100000UL static const io_dev_connector_t *uniphier_fip_dev_con; @@ -317,7 +317,7 @@ static int (* const uniphier_io_setup_table[])(unsigned int, size_t) = { [UNIPHIER_BOOT_DEVICE_USB] = uniphier_io_usb_setup, }; -int uniphier_io_setup(unsigned int soc_id) +int uniphier_io_setup(unsigned int soc_id, uintptr_t mem_base) { int (*io_setup)(unsigned int soc_id, size_t buffer_offset); unsigned int boot_dev; @@ -328,7 +328,7 @@ int uniphier_io_setup(unsigned int soc_id) return -EINVAL; io_setup = uniphier_io_setup_table[boot_dev]; - ret = io_setup(soc_id, UNIPHIER_BLOCK_BUF_BASE); + ret = io_setup(soc_id, mem_base + UNIPHIER_BLOCK_BUF_OFFSET); if (ret) return ret; -- cgit v1.2.3 From 6cdef9ba1144776c14bebe2846391cec74594865 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Fri, 13 Dec 2019 10:53:56 -0600 Subject: xilinx: Unify Platform specific defines for PSCI module PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani Change-Id: I76f5535f1cbdaf3fc1235cd824111d9afe8f7e1b --- plat/xilinx/versal/include/platform_def.h | 2 +- plat/xilinx/zynqmp/include/platform_def.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h index 9f8392ce9..4cdaea219 100644 --- a/plat/xilinx/versal/include/platform_def.h +++ b/plat/xilinx/versal/include/platform_def.h @@ -17,7 +17,7 @@ /* Size of cacheable stacks */ #define PLATFORM_STACK_SIZE 0x440 -#define PLATFORM_CORE_COUNT 2 +#define PLATFORM_CORE_COUNT U(2) #define PLAT_MAX_PWR_LVL 1 #define PLAT_MAX_RET_STATE 1 #define PLAT_MAX_OFF_STATE 2 diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index 7b062fcaa..27968409e 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,8 +21,8 @@ /* Size of cacheable stacks */ #define PLATFORM_STACK_SIZE 0x440 -#define PLATFORM_CORE_COUNT 4 -#define PLAT_NUM_POWER_DOMAINS 5 +#define PLATFORM_CORE_COUNT U(4) +#define PLAT_NUM_POWER_DOMAINS U(5) #define PLAT_MAX_PWR_LVL U(1) #define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_OFF_STATE U(2) -- cgit v1.2.3 From f2aa4e882b7769851ae9089a0be1fd77f8de50cf Mon Sep 17 00:00:00 2001 From: Chris Kay Date: Tue, 23 Apr 2019 16:31:06 +0100 Subject: plat/sgm: Always use SCMI for SGM platforms As on SGI platforms, SCPI is unsupported on SGM platforms. Change-Id: I556ed095b9eb55b72447230ee2725d3c76160a08 Signed-off-by: Chris Kay --- plat/arm/css/sgm/sgm-common.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/plat/arm/css/sgm/sgm-common.mk b/plat/arm/css/sgm/sgm-common.mk index 34e78b2f4..ac34450a7 100644 --- a/plat/arm/css/sgm/sgm-common.mk +++ b/plat/arm/css/sgm/sgm-common.mk @@ -4,6 +4,8 @@ # SPDX-License-Identifier: BSD-3-Clause # +CSS_USE_SCMI_SDS_DRIVER := 1 + CSS_SGM_BASE := plat/arm/css/sgm PLAT_INCLUDES := -I${CSS_SGM_BASE}/include -- cgit v1.2.3 From a9fbf13e049e77743a46ff7a2eca4c18570661ba Mon Sep 17 00:00:00 2001 From: Vijayenthiran Subramaniam Date: Fri, 27 Dec 2019 19:27:57 +0530 Subject: plat/arm/sgi: move topology information to board folder The platform topology description of the upcoming Arm's RD platforms have different topology than those listed in the sgi_topology.c file. So instead of adding platform specific topology into existing sgi_topology.c file, those can be added to respective board files. In order to maintain consistency with the upcoming platforms, move the existing platform topology description to respective board files. Change-Id: I4689c7d24cd0c75a3dc234370c34a85c08598abb Signed-off-by: Vijayenthiran Subramaniam --- plat/arm/board/rde1edge/platform.mk | 3 +- plat/arm/board/rde1edge/rde1edge_topology.c | 33 +++++++++++++++ plat/arm/board/rdn1edge/platform.mk | 3 +- plat/arm/board/rdn1edge/rdn1edge_topology.c | 32 +++++++++++++++ plat/arm/board/sgi575/platform.mk | 3 +- plat/arm/board/sgi575/sgi575_topology.c | 32 +++++++++++++++ plat/arm/css/sgi/sgi_topology.c | 63 ++--------------------------- 7 files changed, 107 insertions(+), 62 deletions(-) create mode 100644 plat/arm/board/rde1edge/rde1edge_topology.c create mode 100644 plat/arm/board/rdn1edge/rdn1edge_topology.c create mode 100644 plat/arm/board/sgi575/sgi575_topology.c diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk index db41e0eda..43c37ffc1 100644 --- a/plat/arm/board/rde1edge/platform.mk +++ b/plat/arm/board/rde1edge/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2019, Arm Limited. All rights reserved. +# Copyright (c) 2018-2020, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -24,6 +24,7 @@ BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \ BL31_SOURCES += ${SGI_CPU_SOURCES} \ ${RDE1EDGE_BASE}/rde1edge_plat.c \ + ${RDE1EDGE_BASE}/rde1edge_topology.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/arm/board/rde1edge/rde1edge_topology.c b/plat/arm/board/rde1edge/rde1edge_topology.c new file mode 100644 index 000000000..0b56f208a --- /dev/null +++ b/plat/arm/board/rde1edge/rde1edge_topology.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/****************************************************************************** + * The power domain tree descriptor. + ******************************************************************************/ +static const unsigned char rde1edge_pd_tree_desc[] = { + PLAT_ARM_CLUSTER_COUNT, + CSS_SGI_MAX_CPUS_PER_CLUSTER, + CSS_SGI_MAX_CPUS_PER_CLUSTER +}; + +/****************************************************************************** + * This function returns the topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return rde1edge_pd_tree_desc; +} + +/******************************************************************************* + * The array mapping platform core position (implemented by plat_my_core_pos()) + * to the SCMI power domain ID implemented by SCP. + ******************************************************************************/ +const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 +}; diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk index b44c70a3b..ca1e95eaf 100644 --- a/plat/arm/board/rdn1edge/platform.mk +++ b/plat/arm/board/rdn1edge/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -24,6 +24,7 @@ BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_plat.c \ BL31_SOURCES += ${SGI_CPU_SOURCES} \ ${RDN1EDGE_BASE}/rdn1edge_plat.c \ + ${RDN1EDGE_BASE}/rdn1edge_topology.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/arm/board/rdn1edge/rdn1edge_topology.c b/plat/arm/board/rdn1edge/rdn1edge_topology.c new file mode 100644 index 000000000..687ae3595 --- /dev/null +++ b/plat/arm/board/rdn1edge/rdn1edge_topology.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/****************************************************************************** + * The power domain tree descriptor. + ******************************************************************************/ +static const unsigned char rdn1edge_pd_tree_desc[] = { + PLAT_ARM_CLUSTER_COUNT, + CSS_SGI_MAX_CPUS_PER_CLUSTER, + CSS_SGI_MAX_CPUS_PER_CLUSTER +}; + +/******************************************************************************* + * This function returns the topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return rdn1edge_pd_tree_desc; +} + +/******************************************************************************* + * The array mapping platform core position (implemented by plat_my_core_pos()) + * to the SCMI power domain ID implemented by SCP. + ******************************************************************************/ +const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { + 0, 1, 2, 3, 4, 5, 6, 7 +}; diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk index b9fa0995d..ce2717fe0 100644 --- a/plat/arm/board/sgi575/platform.mk +++ b/plat/arm/board/sgi575/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -24,6 +24,7 @@ BL2_SOURCES += ${SGI575_BASE}/sgi575_plat.c \ BL31_SOURCES += ${SGI_CPU_SOURCES} \ ${SGI575_BASE}/sgi575_plat.c \ + ${SGI575_BASE}/sgi575_topology.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/arm/board/sgi575/sgi575_topology.c b/plat/arm/board/sgi575/sgi575_topology.c new file mode 100644 index 000000000..f7c385673 --- /dev/null +++ b/plat/arm/board/sgi575/sgi575_topology.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/****************************************************************************** + * The power domain tree descriptor. + ******************************************************************************/ +static const unsigned char sgi575_pd_tree_desc[] = { + PLAT_ARM_CLUSTER_COUNT, + CSS_SGI_MAX_CPUS_PER_CLUSTER, + CSS_SGI_MAX_CPUS_PER_CLUSTER +}; + +/******************************************************************************* + * This function returns the topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return sgi575_pd_tree_desc; +} + +/******************************************************************************* + * The array mapping platform core position (implemented by plat_my_core_pos()) + * to the SCMI power domain ID implemented by SCP. + ******************************************************************************/ +const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { + 0, 1, 2, 3, 4, 5, 6, 7 +}; diff --git a/plat/arm/css/sgi/sgi_topology.c b/plat/arm/css/sgi/sgi_topology.c index 7aa9e40d3..1c3b5bfc8 100644 --- a/plat/arm/css/sgi/sgi_topology.c +++ b/plat/arm/css/sgi/sgi_topology.c @@ -1,62 +1,14 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include -#include -#include - -/* Topology */ /* - * The power domain tree descriptor. The cluster power domains are - * arranged so that when the PSCI generic code creates the power domain tree, - * the indices of the CPU power domain nodes it allocates match the linear - * indices returned by plat_core_pos_by_mpidr(). + * Common topology related methods for SGI and RD based platforms */ -const unsigned char sgi_pd_tree_desc[] = { - PLAT_ARM_CLUSTER_COUNT, - CSS_SGI_MAX_CPUS_PER_CLUSTER, - CSS_SGI_MAX_CPUS_PER_CLUSTER -}; - -/* RD-E1-Edge platform consists of 16 physical CPUS and 32 threads */ -const unsigned char rd_e1_edge_pd_tree_desc[] = { - PLAT_ARM_CLUSTER_COUNT, - CSS_SGI_MAX_CPUS_PER_CLUSTER, - CSS_SGI_MAX_CPUS_PER_CLUSTER, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU -}; - -/******************************************************************************* - * This function returns the topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM && - sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID) - return rd_e1_edge_pd_tree_desc; - else - return sgi_pd_tree_desc; -} - /******************************************************************************* * This function returns the core count within the cluster corresponding to * `mpidr`. @@ -66,15 +18,7 @@ unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) return CSS_SGI_MAX_CPUS_PER_CLUSTER; } -/******************************************************************************* - * The array mapping platform core position (implemented by plat_my_core_pos()) - * to the SCMI power domain ID implemented by SCP. - ******************************************************************************/ -const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[32] = { - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 -}; - +#if ARM_PLAT_MT /****************************************************************************** * Return the number of PE's supported by the CPU. *****************************************************************************/ @@ -82,3 +26,4 @@ unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr) { return CSS_SGI_MAX_PE_PER_CPU; } +#endif -- cgit v1.2.3 From f2d6b4ee5740245a92fd511180f7eebc6736a80b Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Fri, 24 Jan 2020 11:54:44 +0000 Subject: Neovers N1: added support to update presence of External LLC CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363 --- docs/design/cpu-specific-build-macros.rst | 5 +++++ include/lib/cpus/aarch64/neoverse_n1.h | 3 ++- lib/cpus/aarch64/neoverse_n1.S | 7 +++++++ lib/cpus/cpu-ops.mk | 9 ++++++++- 4 files changed, 22 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 7fa027f42..f3096b418 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -324,6 +324,11 @@ architecture that can be enabled by the platform as desired. as recommended in section "4.7 Non-Temporal Loads/Stores" of the `Cortex-A57 Software Optimization Guide`_. +- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last + level cache(LLC) is present in the system, and that the DataSource field + on the master CHI interface indicates when data is returned from the LLC. + This is used to control how the LL_CACHE* PMU events count. + -------------- *Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.* diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index fa733ce1b..b50befa8d 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,6 +35,7 @@ #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) +#define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) /******************************************************************************* * CPU Auxiliary Control register specific definitions. diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index d058d98df..d537ed6a8 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -465,6 +465,13 @@ func neoverse_n1_reset_func msr CPUAMCNTENSET_EL0, x0 #endif +#if NEOVERSE_N1_EXTERNAL_LLC + /* Some system may have External LLC, core needs to be made aware */ + mrs x0, NEOVERSE_N1_CPUECTLR_EL1 + orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT + msr NEOVERSE_N1_CPUECTLR_EL1, x0 +#endif + #if ERRATA_DSU_936184 bl errata_dsu_936184_wa #endif diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 398edf9dc..e3bfc2f2e 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -20,6 +20,10 @@ WORKAROUND_CVE_2017_5715 ?=1 WORKAROUND_CVE_2018_3639 ?=1 DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0 +# Flag to indicate internal or external Last level cache +# By default internal +NEOVERSE_N1_EXTERNAL_LLC ?=0 + # Process SKIP_A57_L1_FLUSH_PWR_DWN flag $(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) $(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) @@ -43,6 +47,9 @@ $(eval $(call add_define,WORKAROUND_CVE_2018_3639)) $(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639)) $(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639)) +$(eval $(call assert_boolean,NEOVERSE_N1_EXTERNAL_LLC)) +$(eval $(call add_define,NEOVERSE_N1_EXTERNAL_LLC)) + ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0) ifeq (${WORKAROUND_CVE_2018_3639},0) $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1") -- cgit v1.2.3 From c0018913b4e1139ffa575488a58530614ff490d1 Mon Sep 17 00:00:00 2001 From: Raghu Krishnamurthy Date: Sat, 25 Jan 2020 19:20:45 -0800 Subject: T589: Fix insufficient ordering guarantees in bakery lock bakery_lock_get() uses DMB LD after lock acquisition and bakery_lock_release() uses DMB ST before releasing the lock. This is insufficient in both cases. With just DMB LD, stores in the critical section can be reordered before the DMB LD which could mean writes in the critical section completing before the lock has been acquired successfully. Similarly, with just DMB ST, a load in the critical section could be reordered after the the DMB ST. DMB is the least expensive barrier that can provide the required ordering. Signed-off-by: Raghu Krishnamurthy Change-Id: Ieb74cbf5b76b09e1789331b71f37f7c660221b0e --- lib/locks/bakery/bakery_lock_coherent.c | 16 ++++++++++------ lib/locks/bakery/bakery_lock_normal.c | 16 ++++++++++------ 2 files changed, 20 insertions(+), 12 deletions(-) diff --git a/lib/locks/bakery/bakery_lock_coherent.c b/lib/locks/bakery/bakery_lock_coherent.c index 1634e3af6..748eeddf4 100644 --- a/lib/locks/bakery/bakery_lock_coherent.c +++ b/lib/locks/bakery/bakery_lock_coherent.c @@ -137,10 +137,11 @@ void bakery_lock_get(bakery_lock_t *bakery) } /* - * Lock acquired. Ensure that any reads from a shared resource in the - * critical section read values after the lock is acquired. + * Lock acquired. Ensure that any reads and writes from a shared + * resource in the critical section read/write values after the lock is + * acquired. */ - dmbld(); + dmbish(); } @@ -154,11 +155,14 @@ void bakery_lock_release(bakery_lock_t *bakery) /* * Ensure that other observers see any stores in the critical section - * before releasing the lock. Release the lock by resetting ticket. - * Then signal other waiting contenders. + * before releasing the lock. Also ensure all loads in the critical + * section are complete before releasing the lock. Release the lock by + * resetting ticket. Then signal other waiting contenders. */ - dmbst(); + dmbish(); bakery->lock_data[me] = 0U; + + /* Required to ensure ordering of the following sev */ dsb(); sev(); } diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c index f906f51ea..caced8f46 100644 --- a/lib/locks/bakery/bakery_lock_normal.c +++ b/lib/locks/bakery/bakery_lock_normal.c @@ -219,10 +219,11 @@ void bakery_lock_get(bakery_lock_t *lock) } /* - * Lock acquired. Ensure that any reads from a shared resource in the - * critical section read values after the lock is acquired. + * Lock acquired. Ensure that any reads and writes from a shared + * resource in the critical section read/write values after the lock is + * acquired. */ - dmbld(); + dmbish(); } void bakery_lock_release(bakery_lock_t *lock) @@ -240,11 +241,14 @@ void bakery_lock_release(bakery_lock_t *lock) /* * Ensure that other observers see any stores in the critical section - * before releasing the lock. Release the lock by resetting ticket. - * Then signal other waiting contenders. + * before releasing the lock. Also ensure all loads in the critical + * section are complete before releasing the lock. Release the lock by + * resetting ticket. Then signal other waiting contenders. */ - dmbst(); + dmbish(); my_bakery_info->lock_data = 0U; write_cache_op((uintptr_t)my_bakery_info, is_cached); + + /* This sev is ordered by the dsbish in write_cahce_op */ sev(); } -- cgit v1.2.3 From 9f49a177c61aced991339668766843fdc93ff2bf Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Thu, 16 Jan 2020 16:05:43 -0600 Subject: ti: k3: common: Rename device IDs to be more consistent The core number is called 'core_id' but the processor and device IDs are called 'proc' and 'device'. Rename these to make them less confusing. Signed-off-by: Andrew F. Davis Change-Id: I3d7c6dddd7aa37b5dee1aa9689ce31730e9c3b59 --- plat/ti/k3/common/k3_psci.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c index de9cefe5b..15bdc3e25 100644 --- a/plat/ti/k3/common/k3_psci.c +++ b/plat/ti/k3/common/k3_psci.c @@ -37,30 +37,30 @@ static void k3_cpu_standby(plat_local_state_t cpu_state) static int k3_pwr_domain_on(u_register_t mpidr) { - int core_id, proc, device, ret; + int core, proc_id, device_id, ret; - core_id = plat_core_pos_by_mpidr(mpidr); - if (core_id < 0) { - ERROR("Could not get target core id: %d\n", core_id); + core = plat_core_pos_by_mpidr(mpidr); + if (core < 0) { + ERROR("Could not get target core id: %d\n", core); return PSCI_E_INTERN_FAIL; } - proc = PLAT_PROC_START_ID + core_id; - device = PLAT_PROC_DEVICE_START_ID + core_id; + proc_id = PLAT_PROC_START_ID + core; + device_id = PLAT_PROC_DEVICE_START_ID + core; - ret = ti_sci_proc_request(proc); + ret = ti_sci_proc_request(proc_id); if (ret) { ERROR("Request for processor failed: %d\n", ret); return PSCI_E_INTERN_FAIL; } - ret = ti_sci_proc_set_boot_cfg(proc, k3_sec_entrypoint, 0, 0); + ret = ti_sci_proc_set_boot_cfg(proc_id, k3_sec_entrypoint, 0, 0); if (ret) { ERROR("Request to set core boot address failed: %d\n", ret); return PSCI_E_INTERN_FAIL; } - ret = ti_sci_device_get(device); + ret = ti_sci_device_get(device_id); if (ret) { ERROR("Request to start core failed: %d\n", ret); return PSCI_E_INTERN_FAIL; @@ -71,17 +71,17 @@ static int k3_pwr_domain_on(u_register_t mpidr) void k3_pwr_domain_off(const psci_power_state_t *target_state) { - int core_id, proc, device, ret; + int core, proc_id, device_id, ret; /* Prevent interrupts from spuriously waking up this cpu */ k3_gic_cpuif_disable(); - core_id = plat_my_core_pos(); - proc = PLAT_PROC_START_ID + core_id; - device = PLAT_PROC_DEVICE_START_ID + core_id; + core = plat_my_core_pos(); + proc_id = PLAT_PROC_START_ID + core; + device_id = PLAT_PROC_DEVICE_START_ID + core; /* Start by sending wait for WFI command */ - ret = ti_sci_proc_wait_boot_status_no_wait(proc, + ret = ti_sci_proc_wait_boot_status_no_wait(proc_id, /* * Wait maximum time to give us the best chance to get * to WFI before this command timeouts @@ -95,7 +95,7 @@ void k3_pwr_domain_off(const psci_power_state_t *target_state) } /* Now queue up the core shutdown request */ - ret = ti_sci_device_put_no_wait(device); + ret = ti_sci_device_put_no_wait(device_id); if (ret) { ERROR("Sending core shutdown message failed (%d)\n", ret); return; -- cgit v1.2.3 From 586621f110b082e6a812ce8e9acbd21ca3d162cd Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Mon, 11 Feb 2019 16:12:31 -0600 Subject: ti: k3: common: Enable ARM cluster power down When all cores in a cluster are powered down the parent cluster can be also powered down. When the last core has requested powering down follow by sending the cluster power down sequence to the system power controller firmware. Signed-off-by: Andrew F. Davis Change-Id: I0ffeb339852c66ef62743aecd3e17ca20bad6216 --- plat/ti/k3/board/generic/include/board_def.h | 1 + plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h | 9 +- plat/ti/k3/common/k3_psci.c | 95 +++++++++++++++++++++- 3 files changed, 103 insertions(+), 2 deletions(-) diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h index c1a5966d5..0d451167e 100644 --- a/plat/ti/k3/board/generic/include/board_def.h +++ b/plat/ti/k3/board/generic/include/board_def.h @@ -27,5 +27,6 @@ #define PLAT_PROC_START_ID 32 #define PLAT_PROC_DEVICE_START_ID 202 +#define PLAT_CLUSTER_DEVICE_START_ID 198 #endif /* BOARD_DEF_H */ diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h index a921e512a..2d23f9a9c 100644 --- a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h +++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h @@ -563,8 +563,13 @@ struct ti_sci_msg_req_set_proc_boot_config { uint32_t config_flags_clear; } __packed; +/* ARMV8 Control Flags */ +#define PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM 0x00000001 +#define PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS 0x00000002 +#define PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ 0x00000100 + /* R5 Control Flags */ -#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 +#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 /** * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags @@ -618,6 +623,8 @@ struct ti_sci_msg_req_get_proc_boot_status { /* ARMv8 Status Flags */ #define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002 +#define PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE 0x00000010 +#define PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2 0x00000020 /* R5 Status Flags */ #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001 diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c index 15bdc3e25..cf0a21d01 100644 --- a/plat/ti/k3/common/k3_psci.c +++ b/plat/ti/k3/common/k3_psci.c @@ -17,6 +17,10 @@ #include #include +#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) +#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) +#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) + uintptr_t k3_sec_entrypoint; static void k3_cpu_standby(plat_local_state_t cpu_state) @@ -60,6 +64,16 @@ static int k3_pwr_domain_on(u_register_t mpidr) return PSCI_E_INTERN_FAIL; } + /* sanity check these are off before starting a core */ + ret = ti_sci_proc_set_boot_ctrl(proc_id, + 0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ | + PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS | + PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM); + if (ret) { + ERROR("Request to clear boot configuration failed: %d\n", ret); + return PSCI_E_INTERN_FAIL; + } + ret = ti_sci_device_get(device_id); if (ret) { ERROR("Request to start core failed: %d\n", ret); @@ -71,14 +85,32 @@ static int k3_pwr_domain_on(u_register_t mpidr) void k3_pwr_domain_off(const psci_power_state_t *target_state) { - int core, proc_id, device_id, ret; + int core, cluster, proc_id, device_id, cluster_id, ret; + + /* At very least the local core should be powering down */ + assert(CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); /* Prevent interrupts from spuriously waking up this cpu */ k3_gic_cpuif_disable(); core = plat_my_core_pos(); + cluster = MPIDR_AFFLVL1_VAL(read_mpidr_el1()); proc_id = PLAT_PROC_START_ID + core; device_id = PLAT_PROC_DEVICE_START_ID + core; + cluster_id = PLAT_CLUSTER_DEVICE_START_ID + (cluster * 2); + + /* + * If we are the last core in the cluster then we take a reference to + * the cluster device so that it does not get shutdown before we + * execute the entire cluster L2 cleaning sequence below. + */ + if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { + ret = ti_sci_device_get(cluster_id); + if (ret) { + ERROR("Request to get cluster failed: %d\n", ret); + return; + } + } /* Start by sending wait for WFI command */ ret = ti_sci_proc_wait_boot_status_no_wait(proc_id, @@ -100,6 +132,67 @@ void k3_pwr_domain_off(const psci_power_state_t *target_state) ERROR("Sending core shutdown message failed (%d)\n", ret); return; } + + /* If our cluster is not going down we stop here */ + if (CLUSTER_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) + return; + + /* set AINACTS */ + ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id, + PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS, 0); + if (ret) { + ERROR("Sending set control message failed (%d)\n", ret); + return; + } + + /* set L2FLUSHREQ */ + ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id, + PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ, 0); + if (ret) { + ERROR("Sending set control message failed (%d)\n", ret); + return; + } + + /* wait for L2FLUSHDONE*/ + ret = ti_sci_proc_wait_boot_status_no_wait(proc_id, + UINT8_MAX, 2, UINT8_MAX, UINT8_MAX, + PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE, 0, 0, 0); + if (ret) { + ERROR("Sending wait message failed (%d)\n", ret); + return; + } + + /* clear L2FLUSHREQ */ + ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id, + 0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ); + if (ret) { + ERROR("Sending set control message failed (%d)\n", ret); + return; + } + + /* set ACINACTM */ + ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id, + PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM, 0); + if (ret) { + ERROR("Sending set control message failed (%d)\n", ret); + return; + } + + /* wait for STANDBYWFIL2 */ + ret = ti_sci_proc_wait_boot_status_no_wait(proc_id, + UINT8_MAX, 2, UINT8_MAX, UINT8_MAX, + PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2, 0, 0, 0); + if (ret) { + ERROR("Sending wait message failed (%d)\n", ret); + return; + } + + /* Now queue up the cluster shutdown request */ + ret = ti_sci_device_put_no_wait(cluster_id); + if (ret) { + ERROR("Sending cluster shutdown message failed (%d)\n", ret); + return; + } } void k3_pwr_domain_on_finish(const psci_power_state_t *target_state) -- cgit v1.2.3 From 592ede258dc109f3a153ca040f005b5c4dd224ce Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Thu, 16 Jan 2020 15:34:31 -0600 Subject: ti: k3: drivers: ti_sci: Remove indirect structure of const data The 'info' structure contained what is only static data for this implementation of TI-SCI. Remove this indirection and remove the struct. Signed-off-by: Andrew F. Davis Change-Id: I2328fddf388bf7d56a56bd673c080e78c86fe072 --- plat/ti/k3/common/drivers/ti_sci/ti_sci.c | 59 +++++++++---------------------- 1 file changed, 17 insertions(+), 42 deletions(-) diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c index ac33278a9..d5bcee8c7 100644 --- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c +++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c @@ -20,32 +20,7 @@ #include "ti_sci_protocol.h" #include "ti_sci.h" -/** - * struct ti_sci_desc - Description of SoC integration - * @host_id: Host identifier representing the compute entity - * @max_msg_size: Maximum size of data per message that can be handled - */ -struct ti_sci_desc { - uint8_t host_id; - int max_msg_size; -}; - -/** - * struct ti_sci_info - Structure representing a TI SCI instance - * @desc: SoC description for this instance - * @seq: Seq id used for verification for tx and rx message - */ -struct ti_sci_info { - const struct ti_sci_desc desc; - uint8_t seq; -}; - -static struct ti_sci_info info = { - .desc = { - .host_id = TI_SCI_HOST_ID, - .max_msg_size = TI_SCI_MAX_MESSAGE_SIZE, - }, -}; +static uint8_t message_sequence; /** * struct ti_sci_xfer - Structure representing a message flow @@ -82,16 +57,16 @@ static int ti_sci_setup_one_xfer(uint16_t msg_type, uint32_t msg_flags, struct ti_sci_msg_hdr *hdr; /* Ensure we have sane transfer sizes */ - if (rx_message_size > info.desc.max_msg_size || - tx_message_size > info.desc.max_msg_size || + if (rx_message_size > TI_SCI_MAX_MESSAGE_SIZE || + tx_message_size > TI_SCI_MAX_MESSAGE_SIZE || rx_message_size < sizeof(*hdr) || tx_message_size < sizeof(*hdr)) return -ERANGE; hdr = (struct ti_sci_msg_hdr *)tx_buf; - hdr->seq = ++info.seq; + hdr->seq = ++message_sequence; hdr->type = msg_type; - hdr->host = info.desc.host_id; + hdr->host = TI_SCI_HOST_ID; hdr->flags = msg_flags | TI_SCI_FLAG_REQ_ACK_ON_PROCESSED; xfer->tx_message.buf = tx_buf; @@ -131,7 +106,7 @@ static inline int ti_sci_get_response(struct ti_sci_xfer *xfer, hdr = (struct ti_sci_msg_hdr *)msg->buf; /* Sanity check for message response */ - if (hdr->seq == info.seq) + if (hdr->seq == message_sequence) break; else WARN("Message with sequence ID %u is not expected\n", hdr->seq); @@ -141,9 +116,9 @@ static inline int ti_sci_get_response(struct ti_sci_xfer *xfer, return -EINVAL; } - if (msg->len > info.desc.max_msg_size) { + if (msg->len > TI_SCI_MAX_MESSAGE_SIZE) { ERROR("Unable to handle %lu xfer (max %d)\n", - msg->len, info.desc.max_msg_size); + msg->len, TI_SCI_MAX_MESSAGE_SIZE); return -EINVAL; } @@ -425,13 +400,13 @@ int ti_sci_device_put_no_wait(uint32_t id) int ret; /* Ensure we have sane transfer size */ - if (sizeof(req) > info.desc.max_msg_size) + if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE) return -ERANGE; hdr = (struct ti_sci_msg_hdr *)&req; - hdr->seq = ++info.seq; + hdr->seq = ++message_sequence; hdr->type = TI_SCI_MSG_SET_DEVICE_STATE; - hdr->host = info.desc.host_id; + hdr->host = TI_SCI_HOST_ID; /* Setup with NORESPONSE flag to keep response queue clean */ hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE; @@ -1408,13 +1383,13 @@ int ti_sci_proc_set_boot_ctrl_no_wait(uint8_t proc_id, int ret; /* Ensure we have sane transfer size */ - if (sizeof(req) > info.desc.max_msg_size) + if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE) return -ERANGE; hdr = (struct ti_sci_msg_hdr *)&req; - hdr->seq = ++info.seq; + hdr->seq = ++message_sequence; hdr->type = TISCI_MSG_SET_PROC_BOOT_CTRL; - hdr->host = info.desc.host_id; + hdr->host = TI_SCI_HOST_ID; /* Setup with NORESPONSE flag to keep response queue clean */ hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE; @@ -1650,13 +1625,13 @@ int ti_sci_proc_wait_boot_status_no_wait(uint8_t proc_id, int ret; /* Ensure we have sane transfer size */ - if (sizeof(req) > info.desc.max_msg_size) + if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE) return -ERANGE; hdr = (struct ti_sci_msg_hdr *)&req; - hdr->seq = ++info.seq; + hdr->seq = ++message_sequence; hdr->type = TISCI_MSG_WAIT_PROC_BOOT_STATUS; - hdr->host = info.desc.host_id; + hdr->host = TI_SCI_HOST_ID; /* Setup with NORESPONSE flag to keep response queue clean */ hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE; -- cgit v1.2.3 From 32967a379c9fde59370a3cb2d53be085951202bf Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Thu, 16 Jan 2020 15:58:34 -0600 Subject: ti: k3: drivers: ti_sci: Put sequence number in coherent memory The current message sequence number is accessed both with caches on and off so put this memory in the un-cached coherent section so accesses are consistent and coherency is maintained. Signed-off-by: Andrew F. Davis Change-Id: Ieeefefeaffc691e4e4c4de7c74490d50ff9de807 --- plat/ti/k3/common/drivers/ti_sci/ti_sci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c index d5bcee8c7..e390efee6 100644 --- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c +++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c @@ -20,6 +20,9 @@ #include "ti_sci_protocol.h" #include "ti_sci.h" +#if USE_COHERENT_MEM +__section("tzfw_coherent_mem") +#endif static uint8_t message_sequence; /** -- cgit v1.2.3 From ffd58cca83b4d7f4521a0ee5b74ea7ca8411cb48 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 1 Dec 2017 09:24:12 -0800 Subject: Tegra194: enable spe-console functionality This patch enables the config to switch to the console provided by the SPE firmware. Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/platform_t194.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 1e49e51da..78766fcbe 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -5,7 +5,7 @@ # # platform configs -ENABLE_CONSOLE_SPE := 0 +ENABLE_CONSOLE_SPE := 1 $(eval $(call add_define,ENABLE_CONSOLE_SPE)) ENABLE_STRICT_CHECKING_MODE := 1 -- cgit v1.2.3 From f1be00da0b0acf90355558e01d5f8e1f79c0d481 Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Fri, 24 Jan 2020 13:30:28 +0000 Subject: Use correct type when reading SCR register The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt --- bl31/interrupt_mgmt.c | 20 ++++++++++---------- drivers/arm/gic/v3/gicv3_main.c | 6 +++--- include/bl31/interrupt_mgmt.h | 4 ++-- include/lib/el3_runtime/context_mgmt.h | 4 ++-- lib/el3_runtime/aarch64/context_mgmt.c | 22 +++++++++++----------- plat/arm/common/arm_common.c | 4 ++-- plat/mediatek/mt8173/plat_pm.c | 4 ++-- plat/mediatek/mt8183/plat_pm.c | 4 ++-- plat/renesas/rcar/plat_pm.c | 4 ++-- plat/rockchip/common/plat_pm.c | 4 ++-- plat/socionext/synquacer/sq_psci.c | 4 ++-- plat/ti/k3/common/k3_psci.c | 4 ++-- 12 files changed, 42 insertions(+), 42 deletions(-) diff --git a/bl31/interrupt_mgmt.c b/bl31/interrupt_mgmt.c index e6efad3e0..b8cc3de08 100644 --- a/bl31/interrupt_mgmt.c +++ b/bl31/interrupt_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,6 +17,11 @@ * registered interrupt handlers for each interrupt type. * The field descriptions are: * + * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the + * value of the SCR_EL3.IRQ or FIQ bit for each security state. + * There are two instances of this field corresponding to the + * two security states. + * * 'flags' : Bit[0], Routing model for this interrupt type when execution is * not in EL3 in the secure state. '1' implies that this * interrupt will be routed to EL3. '0' implies that this @@ -28,16 +33,11 @@ * interrupt will be routed to the current exception level. * * All other bits are reserved and SBZ. - * - * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the - * value of the SCR_EL3.IRQ or FIQ bit for each security state. - * There are two instances of this field corresponding to the - * two security states. ******************************************************************************/ typedef struct intr_type_desc { interrupt_type_handler_t handler; + u_register_t scr_el3[2]; uint32_t flags; - uint32_t scr_el3[2]; } intr_type_desc_t; static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES]; @@ -78,9 +78,9 @@ static int32_t validate_routing_model(uint32_t type, uint32_t flags) * routing model (expressed through the IRQ and FIQ bits) for a security state * which was stored through a call to 'set_routing_model()' earlier. ******************************************************************************/ -uint32_t get_scr_el3_from_routing_model(uint32_t security_state) +u_register_t get_scr_el3_from_routing_model(uint32_t security_state) { - uint32_t scr_el3; + u_register_t scr_el3; assert(sec_state_is_valid(security_state)); scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state]; @@ -103,7 +103,7 @@ static void set_scr_el3_from_rm(uint32_t type, flag = get_interrupt_rm_flag(interrupt_type_flags, security_state); bit_pos = plat_interrupt_type_to_line(type, security_state); - intr_type_descs[type].scr_el3[security_state] = flag << bit_pos; + intr_type_descs[type].scr_el3[security_state] = (u_register_t)flag << bit_pos; /* * Update scr_el3 only if there is a context available. If not, it diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index fb49a579d..a672b18f3 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -235,7 +235,7 @@ void gicv3_rdistif_on(unsigned int proc_num) void gicv3_cpuif_enable(unsigned int proc_num) { uintptr_t gicr_base; - unsigned int scr_el3; + u_register_t scr_el3; unsigned int icc_sre_el3; assert(gicv3_driver_data != NULL); @@ -258,7 +258,7 @@ void gicv3_cpuif_enable(unsigned int proc_num) icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); - scr_el3 = (uint32_t) read_scr_el3(); + scr_el3 = read_scr_el3(); /* * Switch to NS state to write Non secure ICC_SRE_EL1 and diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h index 8bb1bab24..935bf7766 100644 --- a/include/bl31/interrupt_mgmt.h +++ b/include/bl31/interrupt_mgmt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -134,7 +134,7 @@ typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, /******************************************************************************* * Function & variable prototypes ******************************************************************************/ -uint32_t get_scr_el3_from_routing_model(uint32_t security_state); +u_register_t get_scr_el3_from_routing_model(uint32_t security_state); int32_t set_routing_model(uint32_t type, uint32_t flags); int32_t register_interrupt_type_handler(uint32_t type, interrupt_type_handler_t handler, diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h index 7c996d124..17955e3a8 100644 --- a/include/lib/el3_runtime/context_mgmt.h +++ b/include/lib/el3_runtime/context_mgmt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -45,7 +45,7 @@ void cm_write_scr_el3_bit(uint32_t security_state, uint32_t bit_pos, uint32_t value); void cm_set_next_eret_context(uint32_t security_state); -uint32_t cm_get_scr_el3(uint32_t security_state); +u_register_t cm_get_scr_el3(uint32_t security_state); /* Inline definitions */ diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index b7908adec..dc4717abe 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -66,7 +66,7 @@ void __init cm_init(void) void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) { unsigned int security_state; - uint32_t scr_el3; + u_register_t scr_el3; el3_state_t *state; gp_regs_t *gp_regs; u_register_t sctlr_elx, actlr_elx; @@ -87,7 +87,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) * the required value depending on the state of the SPSR_EL3 and the * Security state and entrypoint attributes of the next EL. */ - scr_el3 = (uint32_t)read_scr(); + scr_el3 = read_scr(); scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | SCR_ST_BIT | SCR_HCE_BIT); /* @@ -326,7 +326,7 @@ void cm_init_my_context(const entry_point_info_t *ep) ******************************************************************************/ void cm_prepare_el3_exit(uint32_t security_state) { - uint32_t sctlr_elx, scr_el3, mdcr_el2; + u_register_t sctlr_elx, scr_el3, mdcr_el2; cpu_context_t *ctx = cm_get_context(security_state); bool el2_unused = false; uint64_t hcr_el2 = 0U; @@ -334,11 +334,11 @@ void cm_prepare_el3_exit(uint32_t security_state) assert(ctx != NULL); if (security_state == NON_SECURE) { - scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx), + scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); if ((scr_el3 & SCR_HCE_BIT) != 0U) { /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ - sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx), + sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); sctlr_elx &= SCTLR_EE_BIT; sctlr_elx |= SCTLR_EL2_RES1; @@ -618,7 +618,7 @@ void cm_write_scr_el3_bit(uint32_t security_state, { cpu_context_t *ctx; el3_state_t *state; - uint32_t scr_el3; + u_register_t scr_el3; ctx = cm_get_context(security_state); assert(ctx != NULL); @@ -634,9 +634,9 @@ void cm_write_scr_el3_bit(uint32_t security_state, * and set it to its new value. */ state = get_el3state_ctx(ctx); - scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); + scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); scr_el3 &= ~(1U << bit_pos); - scr_el3 |= value << bit_pos; + scr_el3 |= (u_register_t)value << bit_pos; write_ctx_reg(state, CTX_SCR_EL3, scr_el3); } @@ -644,7 +644,7 @@ void cm_write_scr_el3_bit(uint32_t security_state, * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the * given security state. ******************************************************************************/ -uint32_t cm_get_scr_el3(uint32_t security_state) +u_register_t cm_get_scr_el3(uint32_t security_state) { cpu_context_t *ctx; el3_state_t *state; @@ -654,7 +654,7 @@ uint32_t cm_get_scr_el3(uint32_t security_state) /* Populate EL3 state so that ERET jumps to the correct entry */ state = get_el3state_ctx(ctx); - return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); + return read_ctx_reg(state, CTX_SCR_EL3); } /******************************************************************************* diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 03d842a51..255e6b421 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -173,7 +173,7 @@ unsigned int plat_get_syscnt_freq2(void) int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) { uint64_t par, pa; - uint32_t scr_el3; + u_register_t scr_el3; /* Doing Non-secure address translation requires SCR_EL3.NS set */ scr_el3 = read_scr_el3(); diff --git a/plat/mediatek/mt8173/plat_pm.c b/plat/mediatek/mt8173/plat_pm.c index c8d45993f..67f1c731b 100644 --- a/plat/mediatek/mt8173/plat_pm.c +++ b/plat/mediatek/mt8173/plat_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -236,7 +236,7 @@ static void mt_platform_restore_context(unsigned long mpidr) static void plat_cpu_standby(plat_local_state_t cpu_state) { - unsigned int scr; + u_register_t scr; scr = read_scr_el3(); write_scr_el3(scr | SCR_IRQ_BIT); diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c index 2358ec6c4..6094a17be 100644 --- a/plat/mediatek/mt8183/plat_pm.c +++ b/plat/mediatek/mt8183/plat_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * Copyright (c) 2019-2020, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -197,7 +197,7 @@ static void plat_cluster_pwron_common(uint64_t mpidr, int cluster) static void plat_cpu_standby(plat_local_state_t cpu_state) { - unsigned int scr; + u_register_t scr; scr = read_scr_el3(); write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); diff --git a/plat/renesas/rcar/plat_pm.c b/plat/renesas/rcar/plat_pm.c index e678da5dc..6fc47b95c 100644 --- a/plat/renesas/rcar/plat_pm.c +++ b/plat/renesas/rcar/plat_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -56,7 +56,7 @@ static void rcar_program_mailbox(uint64_t mpidr, uint64_t address) static void rcar_cpu_standby(plat_local_state_t cpu_state) { - uint32_t scr_el3 = read_scr_el3(); + u_register_t scr_el3 = read_scr_el3(); write_scr_el3(scr_el3 | SCR_IRQ_BIT); dsb(); diff --git a/plat/rockchip/common/plat_pm.c b/plat/rockchip/common/plat_pm.c index c9563c9ed..69268870d 100644 --- a/plat/rockchip/common/plat_pm.c +++ b/plat/rockchip/common/plat_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -182,7 +182,7 @@ void rockchip_get_sys_suspend_power_state(psci_power_state_t *req_state) ******************************************************************************/ void rockchip_cpu_standby(plat_local_state_t cpu_state) { - unsigned int scr; + u_register_t scr; assert(cpu_state == PLAT_MAX_RET_STATE); diff --git a/plat/socionext/synquacer/sq_psci.c b/plat/socionext/synquacer/sq_psci.c index 731b19a32..0c97fcf79 100644 --- a/plat/socionext/synquacer/sq_psci.c +++ b/plat/socionext/synquacer/sq_psci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -155,7 +155,7 @@ void __dead2 sq_system_reset(void) void sq_cpu_standby(plat_local_state_t cpu_state) { - unsigned int scr; + u_register_t scr; assert(cpu_state == SQ_LOCAL_STATE_RET); diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c index de9cefe5b..58588b055 100644 --- a/plat/ti/k3/common/k3_psci.c +++ b/plat/ti/k3/common/k3_psci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,7 +21,7 @@ uintptr_t k3_sec_entrypoint; static void k3_cpu_standby(plat_local_state_t cpu_state) { - unsigned int scr; + u_register_t scr; scr = read_scr_el3(); /* Enable the Non secure interrupt to wake the CPU */ -- cgit v1.2.3 From 8c105290f3733eafb789e17da4a0649e85c7b360 Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Thu, 23 Jan 2020 14:27:38 +0000 Subject: Measured Boot: add function for hash calculation This patch adds 'calc_hash' function using Mbed TLS library required for Measured Boot support. Change-Id: Ifc5aee0162d04db58ec6391e0726a526f29a52bb Signed-off-by: Alexei Fedorov --- Makefile | 10 ++++++++++ docs/getting_started/build-options.rst | 5 +++++ drivers/auth/crypto_mod.c | 23 ++++++++++++++++++++++- drivers/auth/mbedtls/mbedtls_crypto.c | 27 ++++++++++++++++++++++++++- include/drivers/auth/crypto_mod.h | 24 +++++++++++++++++++++++- make_helpers/defaults.mk | 5 ++++- 6 files changed, 90 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index bd52c0bd7..72db2a74a 100644 --- a/Makefile +++ b/Makefile @@ -604,6 +604,14 @@ ifeq ($(CTX_INCLUDE_MTE_REGS),1) endif endif +ifeq ($(MEASURED_BOOT),1) + ifneq (${TRUSTED_BOARD_BOOT},1) + $(error MEASURED_BOOT requires TRUSTED_BOARD_BOOT=1") + else + $(info MEASURED_BOOT is an experimental feature) + endif +endif + ################################################################################ # Process platform overrideable behaviour ################################################################################ @@ -751,6 +759,7 @@ $(eval $(call assert_boolean,GENERATE_COT)) $(eval $(call assert_boolean,GICV2_G0_FOR_EL3)) $(eval $(call assert_boolean,HANDLE_EA_EL3_FIRST)) $(eval $(call assert_boolean,HW_ASSISTED_COHERENCY)) +$(eval $(call assert_boolean,MEASURED_BOOT)) $(eval $(call assert_boolean,NS_TIMER_SWITCH)) $(eval $(call assert_boolean,OVERRIDE_LIBC)) $(eval $(call assert_boolean,PL011_GENERIC_UART)) @@ -817,6 +826,7 @@ $(eval $(call add_define,GICV2_G0_FOR_EL3)) $(eval $(call add_define,HANDLE_EA_EL3_FIRST)) $(eval $(call add_define,HW_ASSISTED_COHERENCY)) $(eval $(call add_define,LOG_LEVEL)) +$(eval $(call add_define,MEASURED_BOOT)) $(eval $(call add_define,NS_TIMER_SWITCH)) $(eval $(call add_define,PL011_GENERIC_UART)) $(eval $(call add_define,PLAT_${PLAT})) diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index fc4545571..b702c34de 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -387,6 +387,11 @@ Common build options All log output up to and including the selected log level is compiled into the build. The default value is 40 in debug builds and 20 in release builds. +- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot + feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set. + This option defaults to 0 and is an experimental feature in the stage of + development. + - ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the Non-Trusted World private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key. diff --git a/drivers/auth/crypto_mod.c b/drivers/auth/crypto_mod.c index 5e5ac2b03..110c5045f 100644 --- a/drivers/auth/crypto_mod.c +++ b/drivers/auth/crypto_mod.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -103,3 +103,24 @@ int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, return crypto_lib_desc.verify_hash(data_ptr, data_len, digest_info_ptr, digest_info_len); } + +#if MEASURED_BOOT +/* + * Calculate a hash + * + * Parameters: + * + * alg: message digest algorithm + * data_ptr, data_len: data to be hashed + * output: resulting hash + */ +int crypto_mod_calc_hash(unsigned int alg, void *data_ptr, + unsigned int data_len, unsigned char *output) +{ + assert(data_ptr != NULL); + assert(data_len != 0); + assert(output != NULL); + + return crypto_lib_desc.calc_hash(alg, data_ptr, data_len, output); +} +#endif /* MEASURED_BOOT */ diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c index 33420fbbd..04fbc648b 100644 --- a/drivers/auth/mbedtls/mbedtls_crypto.c +++ b/drivers/auth/mbedtls/mbedtls_crypto.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -205,7 +205,32 @@ static int verify_hash(void *data_ptr, unsigned int data_len, return CRYPTO_SUCCESS; } +#if MEASURED_BOOT +/* + * Calculate a hash + * + * output points to the computed hash + */ +int calc_hash(unsigned int alg, void *data_ptr, + unsigned int data_len, unsigned char *output) +{ + const mbedtls_md_info_t *md_info; + + md_info = mbedtls_md_info_from_type((mbedtls_md_type_t)alg); + if (md_info == NULL) { + return CRYPTO_ERR_HASH; + } + + /* Calculate the hash of the data */ + return mbedtls_md(md_info, data_ptr, data_len, output); +} +#endif /* MEASURED_BOOT */ + /* * Register crypto library descriptor */ +#if MEASURED_BOOT +REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash); +#else REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash); +#endif /* MEASURED_BOOT */ diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h index 3a4210569..f211035d7 100644 --- a/include/drivers/auth/crypto_mod.h +++ b/include/drivers/auth/crypto_mod.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,6 +37,13 @@ typedef struct crypto_lib_desc_s { /* Verify a hash. Return one of the 'enum crypto_ret_value' options */ int (*verify_hash)(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); + +#if MEASURED_BOOT + /* Calculate a hash. Return hash value */ + int (*calc_hash)(unsigned int alg, void *data_ptr, + unsigned int data_len, unsigned char *output); +#endif /* MEASURED_BOOT */ + } crypto_lib_desc_t; /* Public functions */ @@ -48,7 +55,21 @@ int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len, int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); +#if MEASURED_BOOT +int crypto_mod_calc_hash(unsigned int alg, void *data_ptr, + unsigned int data_len, unsigned char *output); + /* Macro to register a cryptographic library */ +#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \ + _calc_hash) \ + const crypto_lib_desc_t crypto_lib_desc = { \ + .name = _name, \ + .init = _init, \ + .verify_signature = _verify_signature, \ + .verify_hash = _verify_hash, \ + .calc_hash = _calc_hash \ + } +#else #define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash) \ const crypto_lib_desc_t crypto_lib_desc = { \ .name = _name, \ @@ -56,6 +77,7 @@ int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, .verify_signature = _verify_signature, \ .verify_hash = _verify_hash \ } +#endif /* MEASURED_BOOT */ extern const crypto_lib_desc_t crypto_lib_desc; diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 53832c561..4af1da6b2 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -139,6 +139,9 @@ HW_ASSISTED_COHERENCY := 0 # Set the default algorithm for the generation of Trusted Board Boot keys KEY_ALG := rsa +# Option to build TF with Measured Boot support +MEASURED_BOOT := 0 + # NS timer register save and restore NS_TIMER_SWITCH := 0 -- cgit v1.2.3 From ca661a0092c8ead5ac7df57c55fffcc835d9c0b9 Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Mon, 23 Dec 2019 14:49:52 -0600 Subject: Enable -Wredundant-decls warning check This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy --- Makefile | 3 +-- plat/imx/imx8qm/imx8qm_bl31_setup.c | 13 +++++++------ plat/imx/imx8qx/imx8qx_bl31_setup.c | 13 +++++++------ plat/intel/soc/common/include/socfpga_system_manager.h | 3 +-- plat/nvidia/tegra/common/tegra_bl31_setup.c | 13 +++++++------ .../tegra/soc/t194/drivers/include/mce_private.h | 1 - plat/renesas/rcar/bl2_plat_setup.c | 17 ++++++++++++----- plat/renesas/rcar/bl31_plat_setup.c | 10 +++++----- plat/st/stm32mp1/include/stm32mp1_boot_device.h | 18 ------------------ plat/st/stm32mp1/stm32mp1_boot_device.c | 3 +++ plat/st/stm32mp1/stm32mp1_def.h | 1 - 11 files changed, 43 insertions(+), 52 deletions(-) delete mode 100644 plat/st/stm32mp1/include/stm32mp1_boot_device.h diff --git a/Makefile b/Makefile index bd52c0bd7..34e695e0d 100644 --- a/Makefile +++ b/Makefile @@ -255,7 +255,7 @@ ASFLAGS_aarch64 = $(march64-directive) # General warnings WARNINGS := -Wall -Wmissing-include-dirs -Wunused \ -Wdisabled-optimization -Wvla -Wshadow \ - -Wno-unused-parameter + -Wno-unused-parameter -Wredundant-decls # Additional warnings # Level 1 @@ -274,7 +274,6 @@ WARNING3 += -Wcast-qual WARNING3 += -Wconversion WARNING3 += -Wpacked WARNING3 += -Wpointer-arith -WARNING3 += -Wredundant-decls WARNING3 += -Wswitch-default ifeq (${W},1) diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c index c76de6461..9232cbc2d 100644 --- a/plat/imx/imx8qm/imx8qm_bl31_setup.c +++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,12 +27,13 @@ #include #include -IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); -IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); -IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START); -IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END); +static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE; +static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END; +static const unsigned long BL31_RO_START = BL_CODE_BASE; +static const unsigned long BL31_RO_END = BL_CODE_END; +static const unsigned long BL31_RW_END = BL_END; + IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); -IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c index bfe405284..58c82ce60 100644 --- a/plat/imx/imx8qx/imx8qx_bl31_setup.c +++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,12 +27,13 @@ #include #include -IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); -IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); -IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START); -IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END); +static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE; +static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END; +static const unsigned long BL31_RO_START = BL_CODE_BASE; +static const unsigned long BL31_RO_END = BL_CODE_END; +static const unsigned long BL31_RW_END = BL_END; + IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); -IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h index f1637aed3..68e30b894 100644 --- a/plat/intel/soc/common/include/socfpga_system_manager.h +++ b/plat/intel/soc/common/include/socfpga_system_manager.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -106,7 +106,6 @@ #define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 #define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 -void enable_nonsecure_access(void); void enable_ns_peripheral_access(void); void enable_ns_bridge_access(void); diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 25fd84cdc..cbe3377b0 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -42,11 +42,12 @@ extern void memcpy16(void *dest, const void *src, unsigned int length); ******************************************************************************/ IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); -IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END); -IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE); -IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END); -IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START); -IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END); + +static const uint64_t BL31_RW_END = BL_END; +static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE; +static const uint64_t BL31_RODATA_END = BL_RO_DATA_END; +static const uint64_t TEXT_START = BL_CODE_BASE; +static const uint64_t TEXT_END = BL_CODE_END; extern uint64_t tegra_bl31_phys_base; diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index b6572fffb..1fe3aad39 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -53,7 +53,6 @@ uint64_t nvg_get_cstate_stat_query_value(void); int32_t nvg_is_sc7_allowed(void); int32_t nvg_online_core(uint32_t core); int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); -int32_t nvg_roc_clean_cache_trbits(void); int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); int32_t nvg_roc_clean_cache_trbits(void); void nvg_enable_strict_checking_mode(void); diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 193d80e70..578892eb3 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,12 +39,19 @@ #include "rcar_version.h" #include "rom_api.h" -IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) -IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) +#if RCAR_BL2_DCACHE == 1 +/* + * Following symbols are only used during plat_arch_setup() only + * when RCAR_BL2_DCACHE is enabled. + */ +static const uint64_t BL2_RO_BASE = BL_CODE_BASE; +static const uint64_t BL2_RO_LIMIT = BL_CODE_END; #if USE_COHERENT_MEM -IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) -IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) +static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; +static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; +#endif + #endif extern void plat_rcar_gic_driver_init(void); diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c index bd83c415e..7bc0d8e27 100644 --- a/plat/renesas/rcar/bl31_plat_setup.c +++ b/plat/renesas/rcar/bl31_plat_setup.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,12 +22,12 @@ #include "rcar_private.h" #include "rcar_version.h" -IMPORT_SYM(uint64_t, __RO_START__, BL31_RO_BASE) -IMPORT_SYM(uint64_t, __RO_END__, BL31_RO_LIMIT) +static const uint64_t BL31_RO_BASE = BL_CODE_BASE; +static const uint64_t BL31_RO_LIMIT = BL_CODE_END; #if USE_COHERENT_MEM -IMPORT_SYM(uint64_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_BASE) -IMPORT_SYM(uint64_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_LIMIT) +static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; +static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; #endif extern void plat_rcar_gic_driver_init(void); diff --git a/plat/st/stm32mp1/include/stm32mp1_boot_device.h b/plat/st/stm32mp1/include/stm32mp1_boot_device.h deleted file mode 100644 index a74598395..000000000 --- a/plat/st/stm32mp1/include/stm32mp1_boot_device.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STM32MP1_BOOT_DEVICE_H -#define STM32MP1_BOOT_DEVICE_H - -#include -#include -#include - -int plat_get_raw_nand_data(struct rawnand_device *device); -int plat_get_spi_nand_data(struct spinand_device *device); -int plat_get_nor_data(struct nor_device *device); - -#endif /* STM32MP1_BOOT_DEVICE_H */ diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c index 2d8eccff7..997335d0d 100644 --- a/plat/st/stm32mp1/stm32mp1_boot_device.c +++ b/plat/st/stm32mp1/stm32mp1_boot_device.c @@ -7,6 +7,9 @@ #include #include +#include +#include +#include #include #include diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 11b01ab88..5dc520625 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #endif -- cgit v1.2.3 From 33e8c56973b553ae28075e928db79a1c90a34aa3 Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Thu, 23 Jan 2020 16:22:44 +0000 Subject: qemu: Implement PSCI_CPU_OFF. This is based on the rpi implementation from https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746. Signed-off-by: Andrew Walbran Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1 --- lib/psci/psci_common.c | 2 +- plat/qemu/common/aarch32/plat_helpers.S | 8 +++++++- plat/qemu/common/aarch64/plat_helpers.S | 6 ++++++ plat/qemu/common/qemu_gicv2.c | 5 +++++ plat/qemu/common/qemu_gicv3.c | 6 ++++++ plat/qemu/common/qemu_pm.c | 14 ++++++++++++-- plat/qemu/common/qemu_private.h | 1 + 7 files changed, 38 insertions(+), 4 deletions(-) diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index ea1a01de9..5ab15c6ee 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -775,7 +775,7 @@ void psci_warmboot_entrypoint(void) * suspend. */ if (psci_get_aff_info_state() == AFF_STATE_OFF) { - ERROR("Unexpected affinity info state"); + ERROR("Unexpected affinity info state.\n"); panic(); } diff --git a/plat/qemu/common/aarch32/plat_helpers.S b/plat/qemu/common/aarch32/plat_helpers.S index aebcfa78f..15e860b42 100644 --- a/plat/qemu/common/aarch32/plat_helpers.S +++ b/plat/qemu/common/aarch32/plat_helpers.S @@ -72,8 +72,14 @@ func plat_secondary_cold_boot_setup /* Wait until we have a go */ poll_mailbox: ldr r1, [r2, r0] - cmp r1, #0 + cmp r1, #PLAT_QEMU_HOLD_STATE_WAIT beq 1f + + /* Clear the mailbox again ready for next time. */ + mov r1, #PLAT_QEMU_HOLD_STATE_WAIT + str r1, [r2, r0] + + /* Jump to the provided entrypoint. */ mov_imm r0, PLAT_QEMU_TRUSTED_MAILBOX_BASE ldr r1, [r0] bx r1 diff --git a/plat/qemu/common/aarch64/plat_helpers.S b/plat/qemu/common/aarch64/plat_helpers.S index 13a5ee461..dbcdc2d39 100644 --- a/plat/qemu/common/aarch64/plat_helpers.S +++ b/plat/qemu/common/aarch64/plat_helpers.S @@ -70,6 +70,12 @@ func plat_secondary_cold_boot_setup poll_mailbox: ldr x1, [x2, x0] cbz x1, 1f + + /* Clear the mailbox again ready for next time. */ + mov x1, #PLAT_QEMU_HOLD_STATE_WAIT + str x1, [x2, x0] + + /* Jump to the provided entrypoint. */ mov_imm x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE ldr x1, [x0] br x1 diff --git a/plat/qemu/common/qemu_gicv2.c b/plat/qemu/common/qemu_gicv2.c index fb566227a..2c358ea1a 100644 --- a/plat/qemu/common/qemu_gicv2.c +++ b/plat/qemu/common/qemu_gicv2.c @@ -37,3 +37,8 @@ void qemu_pwr_gic_on_finish(void) /* Enable the gic cpu interface */ gicv2_cpuif_enable(); } + +void qemu_pwr_gic_off(void) +{ + gicv2_cpuif_disable(); +} diff --git a/plat/qemu/common/qemu_gicv3.c b/plat/qemu/common/qemu_gicv3.c index 28572c5ef..0d35446bd 100644 --- a/plat/qemu/common/qemu_gicv3.c +++ b/plat/qemu/common/qemu_gicv3.c @@ -44,3 +44,9 @@ void qemu_pwr_gic_on_finish(void) gicv3_rdistif_init(plat_my_core_pos()); gicv3_cpuif_enable(plat_my_core_pos()); } + +void qemu_pwr_gic_off(void) +{ + gicv3_cpuif_disable(plat_my_core_pos()); + gicv3_rdistif_off(plat_my_core_pos()); +} diff --git a/plat/qemu/common/qemu_pm.c b/plat/qemu/common/qemu_pm.c index 116211c51..cf800096f 100644 --- a/plat/qemu/common/qemu_pm.c +++ b/plat/qemu/common/qemu_pm.c @@ -152,9 +152,18 @@ static int qemu_pwr_domain_on(u_register_t mpidr) * Platform handler called when a power domain is about to be turned off. The * target_state encodes the power state that each level should transition to. ******************************************************************************/ -void qemu_pwr_domain_off(const psci_power_state_t *target_state) +static void qemu_pwr_domain_off(const psci_power_state_t *target_state) { - assert(0); + qemu_pwr_gic_off(); +} + +void __dead2 plat_secondary_cold_boot_setup(void); + +static void __dead2 +qemu_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) +{ + disable_mmu_el3(); + plat_secondary_cold_boot_setup(); } /******************************************************************************* @@ -209,6 +218,7 @@ static const plat_psci_ops_t plat_qemu_psci_pm_ops = { .cpu_standby = qemu_cpu_standby, .pwr_domain_on = qemu_pwr_domain_on, .pwr_domain_off = qemu_pwr_domain_off, + .pwr_domain_pwr_down_wfi = qemu_pwr_domain_pwr_down_wfi, .pwr_domain_suspend = qemu_pwr_domain_suspend, .pwr_domain_on_finish = qemu_pwr_domain_on_finish, .pwr_domain_suspend_finish = qemu_pwr_domain_suspend_finish, diff --git a/plat/qemu/common/qemu_private.h b/plat/qemu/common/qemu_private.h index 71ea4de10..4dc62f539 100644 --- a/plat/qemu/common/qemu_private.h +++ b/plat/qemu/common/qemu_private.h @@ -32,5 +32,6 @@ void qemu_console_init(void); void plat_qemu_gic_init(void); void qemu_pwr_gic_on_finish(void); +void qemu_pwr_gic_off(void); #endif /* QEMU_PRIVATE_H */ -- cgit v1.2.3 From 6de32378f67f9a1368000a94defa8956c3c7319d Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Tue, 28 Jan 2020 12:41:20 -0600 Subject: Add support for documentation build as a target in Makefile Command to build HTML-formatted pages from docs: make doc Change-Id: I4103c804b3564fe67d8fc5a3373679daabf3f2e9 Signed-off-by: Madhukar Pappireddy --- Makefile | 10 +++++++++- docs/change-log-upcoming.rst | 2 +- docs/getting_started/docs-build.rst | 21 ++++++++++++++------- 3 files changed, 24 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index bd52c0bd7..b8de647d3 100644 --- a/Makefile +++ b/Makefile @@ -695,6 +695,9 @@ PYTHON ?= python3 PRINT_MEMORY_MAP_PATH ?= tools/memory PRINT_MEMORY_MAP ?= ${PRINT_MEMORY_MAP_PATH}/print_memory_map.py +# Variables for use with documentation build using Sphinx tool +DOCS_PATH ?= docs + ################################################################################ # Include BL specific makefiles ################################################################################ @@ -869,7 +872,7 @@ endif # Build targets ################################################################################ -.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip fwu_fip certtool dtbs memmap +.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip fwu_fip certtool dtbs memmap doc .SUFFIXES: all: msg_start @@ -1067,6 +1070,10 @@ romlib.bin: libraries memmap: all ${Q}${PYTHON} $(PRINT_MEMORY_MAP) $(BUILD_PLAT) +doc: + @echo " BUILD DOCUMENTATION" + ${Q}${MAKE} --no-print-directory -C ${DOCS_PATH} html + cscope: @echo " CSCOPE" ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files @@ -1107,6 +1114,7 @@ help: @echo " sptool Build the Secure Partition Package creation tool" @echo " dtbs Build the Device Tree Blobs (if required for the platform)" @echo " memmap Print the memory map of the built binaries" + @echo " doc Build html based documentation using Sphinx tool" @echo "" @echo "Note: most build targets require PLAT to be set to a specific platform." @echo "" diff --git a/docs/change-log-upcoming.rst b/docs/change-log-upcoming.rst index 3d7d5094d..14280cbf7 100644 --- a/docs/change-log-upcoming.rst +++ b/docs/change-log-upcoming.rst @@ -23,7 +23,7 @@ New Features - Example: "Add support for Branch Target Identification (BTI)" - Build System - - Example: "Add support for default stack-protector flag" + - Add support for documentation build as a target in Makefile - CPU Support - Example: "cortex-a55: Workaround for erratum 1221012" diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst index c5625e98d..91b1b3a39 100644 --- a/docs/getting_started/docs-build.rst +++ b/docs/getting_started/docs-build.rst @@ -56,21 +56,28 @@ as root or using ``sudo``. Building rendered documentation ------------------------------- -From the ``docs`` directory of the project, run the following commands. It is -important to note that you will not get the correct result if the commands are -run from the project root directory, as that would invoke the top-level Makefile -for |TF-A| itself. +Documents can be built into HTML-formatted pages from project root directory by +running the following command. .. code:: shell - make clean - make html + make doc Output from the build process will be placed in: :: - /docs/build/html/ + docs/build/html/ + +We also support building documentation in other formats. From the ``docs`` +directory of the project, run the following command to see the supported +formats. It is important to note that you will not get the correct result if +the command is run from the project root directory, as that would invoke the +top-level Makefile for |TF-A| itself. + +.. code:: shell + + make help -------------- -- cgit v1.2.3 From 3b24b66edc8bc875b26cd5d52357f46afab974b8 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Tue, 14 Jan 2020 18:06:38 +0100 Subject: cert_create: Introduce TBBR CoT makefile Move all TBBR-specific stuff out of the tool's makefile into a sub-makefile. This will make it easier to define and select an alternate chain of trust in the future. Change-Id: I92e366a1999b74cf51127d1771b64b807cd94b29 Signed-off-by: Sandrine Bailleux --- tools/cert_create/Makefile | 39 +++++++++++--------------------------- tools/cert_create/src/tbbr/tbbr.mk | 29 ++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+), 28 deletions(-) create mode 100644 tools/cert_create/src/tbbr/tbbr.mk diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile index c03629a00..76de6660b 100644 --- a/tools/cert_create/Makefile +++ b/tools/cert_create/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -10,53 +10,36 @@ V ?= 0 DEBUG := 0 BINARY := ${PROJECT}${BIN_EXT} OPENSSL_DIR := /usr -USE_TBBR_DEFS := 1 +MAKE_HELPERS_DIRECTORY := ../../make_helpers/ +include ${MAKE_HELPERS_DIRECTORY}build_macros.mk +include ${MAKE_HELPERS_DIRECTORY}build_env.mk + +# Common source files. OBJECTS := src/cert.o \ src/cmd_opt.o \ src/ext.o \ src/key.o \ src/main.o \ - src/sha.o \ - src/tbbr/tbb_cert.o \ - src/tbbr/tbb_ext.o \ - src/tbbr/tbb_key.o + src/sha.o -HOSTCCFLAGS := -Wall -std=c99 - -MAKE_HELPERS_DIRECTORY := ../../make_helpers/ -include ${MAKE_HELPERS_DIRECTORY}build_macros.mk -include ${MAKE_HELPERS_DIRECTORY}build_env.mk +# TBBR chain of trust definitions. +include src/tbbr/tbbr.mk -ifeq (${USE_TBBR_DEFS},1) -# In this case, cert_tool is platform-independent -PLAT_MSG := TBBR Generic -PLAT_INCLUDE := ../../include/tools_share -else -PLAT_MSG := ${PLAT} - -TF_PLATFORM_ROOT := ../../plat/ -include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk - -PLAT_INCLUDE := $(wildcard ${PLAT_DIR}include) - -ifeq ($(PLAT_INCLUDE),) - $(error "Error: Invalid platform '${PLAT}' has no include directory.") -endif -endif +HOSTCCFLAGS := -Wall -std=c99 ifeq (${DEBUG},1) HOSTCCFLAGS += -g -O0 -DDEBUG -DLOG_LEVEL=40 else HOSTCCFLAGS += -O2 -DLOG_LEVEL=20 endif + ifeq (${V},0) Q := @ else Q := endif -$(eval $(call add_define,USE_TBBR_DEFS)) HOSTCCFLAGS += ${DEFINES} # Make soft links and include from local directory otherwise wrong headers diff --git a/tools/cert_create/src/tbbr/tbbr.mk b/tools/cert_create/src/tbbr/tbbr.mk new file mode 100644 index 000000000..ee82d31e3 --- /dev/null +++ b/tools/cert_create/src/tbbr/tbbr.mk @@ -0,0 +1,29 @@ +# +# Copyright (c) 2020, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +USE_TBBR_DEFS := 1 +$(eval $(call add_define,USE_TBBR_DEFS)) + +ifeq (${USE_TBBR_DEFS},1) +# In this case, cert_tool is platform-independent +PLAT_MSG := TBBR Generic +PLAT_INCLUDE := ../../include/tools_share +else +PLAT_MSG := ${PLAT} + +TF_PLATFORM_ROOT := ../../plat/ +include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk + +PLAT_INCLUDE := $(wildcard ${PLAT_DIR}include) + +ifeq ($(PLAT_INCLUDE),) + $(error "Error: Invalid platform '${PLAT}' has no include directory.") +endif +endif + +OBJECTS += src/tbbr/tbb_cert.o \ + src/tbbr/tbb_ext.o \ + src/tbbr/tbb_key.o -- cgit v1.2.3 From 43743ea57d97c8bc92b13abc30ac0b89effd4424 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Wed, 15 Jan 2020 10:11:07 +0100 Subject: cert_create: Introduce COT build option It allows to select the desired chain of trust. Right now, only the TBBR CoT is available. At this stage, this build option only affects the tool itself. It is not plugged into the rest of the build system yet. To use it: > make -C tools/cert_create COT=tbbr Change-Id: I4484418f76d3c7b330d8653c978499a181534dcd Signed-off-by: Sandrine Bailleux --- tools/cert_create/Makefile | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile index 76de6660b..eff929ef0 100644 --- a/tools/cert_create/Makefile +++ b/tools/cert_create/Makefile @@ -10,6 +10,7 @@ V ?= 0 DEBUG := 0 BINARY := ${PROJECT}${BIN_EXT} OPENSSL_DIR := /usr +COT := tbbr MAKE_HELPERS_DIRECTORY := ../../make_helpers/ include ${MAKE_HELPERS_DIRECTORY}build_macros.mk @@ -23,8 +24,12 @@ OBJECTS := src/cert.o \ src/main.o \ src/sha.o -# TBBR chain of trust definitions. -include src/tbbr/tbbr.mk +# Chain of trust. +ifeq (${COT},tbbr) + include src/tbbr/tbbr.mk +else + $(error Unknown chain of trust ${COT}) +endif HOSTCCFLAGS := -Wall -std=c99 -- cgit v1.2.3 From 067f7e9c52f5aa19bac2cb91a96e6e4f9dee6cb9 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Wed, 15 Jan 2020 11:01:25 +0100 Subject: cert_create: Remove references to TBBR in common code In preparation of supporting alternate chains of trust, reword comments and error messages that explicitly mentioned TBBR. Change-Id: I85a0b08e16d0cd82f3b767fcc092d1f20f45939f Signed-off-by: Sandrine Bailleux --- tools/cert_create/src/ext.c | 6 +++--- tools/cert_create/src/main.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/cert_create/src/ext.c b/tools/cert_create/src/ext.c index 57fb47d1d..d9a92bb10 100644 --- a/tools/cert_create/src/ext.c +++ b/tools/cert_create/src/ext.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,11 +33,11 @@ DECLARE_ASN1_FUNCTIONS(HASH) IMPLEMENT_ASN1_FUNCTIONS(HASH) /* - * This function adds the TBB extensions to the internal extension list + * This function adds the CoT extensions to the internal extension list * maintained by OpenSSL so they can be used later. * * It also initializes the methods to print the contents of the extension. If an - * alias is specified in the TBB extension, we reuse the methods of the alias. + * alias is specified in the CoT extension, we reuse the methods of the alias. * Otherwise, only methods for V_ASN1_INTEGER and V_ASN1_OCTET_STRING are * provided. Any other type will be printed as a raw ascii string. * diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c index 863db7b6e..2ba110132 100644 --- a/tools/cert_create/src/main.c +++ b/tools/cert_create/src/main.c @@ -47,7 +47,7 @@ do { \ v = OBJ_txt2nid(oid); \ if (v == NID_undef) { \ - ERROR("Cannot find TBB extension %s\n", oid); \ + ERROR("Cannot find extension %s\n", oid); \ exit(1); \ } \ } while (0) @@ -335,7 +335,7 @@ int main(int argc, char *argv[]) /* Initialize the new types and register OIDs for the extensions */ if (ext_init() != 0) { - ERROR("Cannot initialize TBB extensions\n"); + ERROR("Cannot initialize extensions\n"); exit(1); } -- cgit v1.2.3 From 3bff910dc16ad5ed97d470064b25481d3674732b Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Wed, 15 Jan 2020 10:23:25 +0100 Subject: Introduce COT build option Allows to select the chain of trust to use when the Trusted Boot feature is enabled. This affects both the cert_create tool and the firmware itself. Right now, the only available CoT is TBBR. Change-Id: I7ab54e66508a1416cb3fcd3dfb0f055696763b3d Signed-off-by: Sandrine Bailleux --- Makefile | 2 +- docs/getting_started/build-options.rst | 3 +++ make_helpers/defaults.mk | 5 ++++- plat/arm/common/arm_common.mk | 10 ++++++++-- 4 files changed, 16 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index bd52c0bd7..249a4860d 100644 --- a/Makefile +++ b/Makefile @@ -1009,7 +1009,7 @@ certtool: ${CRTTOOL} .PHONY: ${CRTTOOL} ${CRTTOOL}: - ${Q}${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} --no-print-directory -C ${CRTTOOLPATH} + ${Q}${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} COT=${COT} --no-print-directory -C ${CRTTOOLPATH} @${ECHO_BLANK_LINE} @echo "Built $@ successfully" @${ECHO_BLANK_LINE} diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index fc4545571..f4e8cbe95 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -128,6 +128,9 @@ Common build options ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need to be implemented in this case. +- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. + Defaults to ``tbbr``. + - ``CRASH_REPORTING``: A non-zero value enables a console dump of processor register state when an unexpected exception occurs during execution of BL31. This option defaults to the value of ``DEBUG`` - i.e. by default diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 53832c561..a211f6606 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -201,6 +201,9 @@ USE_DEBUGFS := 0 # Build option to choose whether Trusted Firmware uses library at ROM USE_ROMLIB := 0 +# Chain of trust. +COT := tbbr + # Use tbbr_oid.h instead of platform_oid.h USE_TBBR_DEFS := 1 diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 9d4f05e9e..c8b7ab448 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -254,7 +254,13 @@ ifneq (${TRUSTED_BOARD_BOOT},0) AUTH_SOURCES := drivers/auth/auth_mod.c \ drivers/auth/crypto_mod.c \ drivers/auth/img_parser_mod.c \ - drivers/auth/tbbr/tbbr_cot.c \ + + # Include the selected chain of trust sources. + ifeq (${COT},tbbr) + AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot.c + else + $(error Unknown chain of trust ${COT}) + endif BL1_SOURCES += ${AUTH_SOURCES} \ bl1/tbbr/tbbr_img_desc.c \ -- cgit v1.2.3 From 62038be731dbb94b27bd571caeead070e9597344 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 26 Dec 2019 13:26:49 +0900 Subject: doc: qemu: fix and update documentation The current URL for QEMU_EFI.fd is not found. Update the link to point to the new one. If you run the shell command as instructed, you will see this error: qemu-system-aarch64: keep_bootcon: Could not open 'keep_bootcon': No such file or directory The part "console=ttyAMA0,38400 keep_bootcon root=/dev/vda2" is the kernel parameter, so it must be quoted. As of writing, QEMU v4.2.0 is the latest, but it does not work for TF-A (It has been fixed in the mainline.) QEMU v4.1.0 works fine. With those issues addressed, I succeeded in booting the latest kernel. Tested with QEMU v4.1.0 and Linux 5.5 (defconfig with no modification). Update the tested versions. Change-Id: Ic85db0e688d67b1803ff890047d37de3f3db2daa Signed-off-by: Masahiro Yamada --- docs/plat/qemu.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/plat/qemu.rst b/docs/plat/qemu.rst index a4c5bec71..88196bc93 100644 --- a/docs/plat/qemu.rst +++ b/docs/plat/qemu.rst @@ -14,7 +14,7 @@ If ``ARM_LINUX_KERNEL_AS_BL33`` is set to 1 then this FDT will be passed to BL33 via register x0, as expected by a Linux kernel. This allows a Linux kernel image to be booted directly as BL33 rather than using a bootloader. -An ARM64 defconfig v4.5 Linux kernel is known to boot, FDT doesn't need to be +An ARM64 defconfig v5.5 Linux kernel is known to boot, FDT doesn't need to be provided as it's generated by QEMU. Current limitations: @@ -24,7 +24,7 @@ Current limitations: - No instructions for how to load a BL32 (Secure Payload) ``QEMU_EFI.fd`` can be dowloaded from -http://snapshots.linaro.org/components/kernel/leg-virt-tianocore-edk2-upstream/latest/QEMU-KERNEL-AARCH64/RELEASE_GCC49/QEMU_EFI.fd +http://snapshots.linaro.org/components/kernel/leg-virt-tianocore-edk2-upstream/latest/QEMU-KERNEL-AARCH64/RELEASE_GCC5/QEMU_EFI.fd Boot binaries, except BL1, are primarily loaded via semi-hosting so all binaries has to reside in the same directory as QEMU is started from. This @@ -33,7 +33,7 @@ is conveniently achieved with symlinks the local names as: - ``bl2.bin`` -> BL2 - ``bl31.bin`` -> BL31 - ``bl33.bin`` -> BL33 (``QEMU_EFI.fd``) -- ``Image`` -> linux/Image +- ``Image`` -> linux/arch/arm64/boot/Image To build: @@ -41,12 +41,12 @@ To build: make CROSS_COMPILE=aarch64-none-elf- PLAT=qemu -To start (QEMU v2.6.0): +To start (QEMU v4.1.0): .. code:: shell qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57 \ -kernel Image \ - -append console=ttyAMA0,38400 keep_bootcon root=/dev/vda2 \ + -append "console=ttyAMA0,38400 keep_bootcon root=/dev/vda2" \ -initrd rootfs-arm64.cpio.gz -smp 2 -m 1024 -bios bl1.bin \ -d unimp -semihosting-config enable,target=native -- cgit v1.2.3 From 0a2ab6e63520dceb81b622dd6b7f4ff30cfed08e Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Wed, 29 Jan 2020 16:21:28 +0000 Subject: FDT wrappers: add functions for read/write bytes This patch adds 'fdtw_read_bytes' and 'fdtw_write_inplace_bytes' functions for read/write array of bytes from/to a given property. It also adds 'fdt_setprop_inplace_namelen_partial' to jmptbl.i files for builds with USE_ROMLIB=1 option. Change-Id: Ied7b5c8b38a0e21d508aa7bcf5893e656028b14d Signed-off-by: Alexei Fedorov --- common/fdt_wrappers.c | 79 ++++++++++++++++++++++++++++++++++++++++++- include/common/fdt_wrappers.h | 6 +++- lib/romlib/jmptbl.i | 3 +- plat/arm/board/fvp/jmptbl.i | 3 +- plat/arm/board/juno/jmptbl.i | 3 +- 5 files changed, 89 insertions(+), 5 deletions(-) diff --git a/common/fdt_wrappers.c b/common/fdt_wrappers.c index e67fdb005..ca5b4556d 100644 --- a/common/fdt_wrappers.c +++ b/common/fdt_wrappers.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -102,6 +102,41 @@ int fdtw_read_array(const void *dtb, int node, const char *prop, return 0; } +/* + * Read bytes from a given property of the given node. Any number of + * bytes of the property can be read. The fdt pointer is updated. + * Returns 0 on success, and -1 on error. + */ +int fdtw_read_bytes(const void *dtb, int node, const char *prop, + unsigned int length, void *value) +{ + const void *ptr; + int value_len; + + assert(dtb != NULL); + assert(prop != NULL); + assert(value != NULL); + assert(node >= 0); + + /* Access property and obtain its length (in bytes) */ + ptr = fdt_getprop_namelen(dtb, node, prop, (int)strlen(prop), + &value_len); + if (ptr == NULL) { + WARN("Couldn't find property %s in dtb\n", prop); + return -1; + } + + /* Verify that property length is not less than number of bytes */ + if ((unsigned int)value_len < length) { + WARN("Property length mismatch\n"); + return -1; + } + + (void)memcpy(value, ptr, length); + + return 0; +} + /* * Read string from a given property of the given node. Up to 'size - 1' * characters are read, and a NUL terminator is added. Returns 0 on success, @@ -167,3 +202,45 @@ int fdtw_write_inplace_cells(void *dtb, int node, const char *prop, return 0; } + +/* + * Write bytes in place to a given property of the given node. + * Any number of bytes of the property can be written. + * Returns 0 on success, and < 0 on error. + */ +int fdtw_write_inplace_bytes(void *dtb, int node, const char *prop, + unsigned int length, const void *data) +{ + const void *ptr; + int namelen, value_len, err; + + assert(dtb != NULL); + assert(prop != NULL); + assert(data != NULL); + assert(node >= 0); + + namelen = (int)strlen(prop); + + /* Access property and obtain its length in bytes */ + ptr = fdt_getprop_namelen(dtb, node, prop, namelen, &value_len); + if (ptr == NULL) { + WARN("Couldn't find property %s in dtb\n", prop); + return -1; + } + + /* Verify that property length is not less than number of bytes */ + if ((unsigned int)value_len < length) { + WARN("Property length mismatch\n"); + return -1; + } + + /* Set property value in place */ + err = fdt_setprop_inplace_namelen_partial(dtb, node, prop, + namelen, 0, + data, (int)length); + if (err != 0) { + WARN("Set property %s failed with error %d\n", prop, err); + } + + return err; +} diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h index 79d001d28..f467958b7 100644 --- a/include/common/fdt_wrappers.h +++ b/include/common/fdt_wrappers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,5 +20,9 @@ int fdtw_read_string(const void *dtb, int node, const char *prop, char *str, size_t size); int fdtw_write_inplace_cells(void *dtb, int node, const char *prop, unsigned int cells, void *value); +int fdtw_read_bytes(const void *dtb, int node, const char *prop, + unsigned int length, void *value); +int fdtw_write_inplace_bytes(void *dtb, int node, const char *prop, + unsigned int length, const void *data); #endif /* FDT_WRAPPERS_H */ diff --git a/lib/romlib/jmptbl.i b/lib/romlib/jmptbl.i index a7280d0d6..33710f581 100644 --- a/lib/romlib/jmptbl.i +++ b/lib/romlib/jmptbl.i @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -17,6 +17,7 @@ fdt fdt_getprop_namelen fdt fdt_setprop_inplace fdt fdt_check_header fdt fdt_node_offset_by_compatible +fdt fdt_setprop_inplace_namelen_partial mbedtls mbedtls_asn1_get_alg mbedtls mbedtls_asn1_get_alg_null mbedtls mbedtls_asn1_get_bitstring_null diff --git a/plat/arm/board/fvp/jmptbl.i b/plat/arm/board/fvp/jmptbl.i index bfa9b561f..6ccdd283f 100644 --- a/plat/arm/board/fvp/jmptbl.i +++ b/plat/arm/board/fvp/jmptbl.i @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -19,6 +19,7 @@ fdt fdt_getprop_namelen fdt fdt_setprop_inplace fdt fdt_check_header fdt fdt_node_offset_by_compatible +fdt fdt_setprop_inplace_namelen_partial mbedtls mbedtls_asn1_get_alg mbedtls mbedtls_asn1_get_alg_null mbedtls mbedtls_asn1_get_bitstring_null diff --git a/plat/arm/board/juno/jmptbl.i b/plat/arm/board/juno/jmptbl.i index bfa9b561f..6ccdd283f 100644 --- a/plat/arm/board/juno/jmptbl.i +++ b/plat/arm/board/juno/jmptbl.i @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -19,6 +19,7 @@ fdt fdt_getprop_namelen fdt fdt_setprop_inplace fdt fdt_check_header fdt fdt_node_offset_by_compatible +fdt fdt_setprop_inplace_namelen_partial mbedtls mbedtls_asn1_get_alg mbedtls mbedtls_asn1_get_alg_null mbedtls mbedtls_asn1_get_bitstring_null -- cgit v1.2.3