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* Merge pull request #1745 from svenauhagen/bugfix/a8kAntonio Niño Díaz2019-01-311-3/+3
|\ | | | | Armada8k GPIO Register macro fix
| * Armada8k GPIO Register macro fixSven Auhagen2019-01-091-3/+3
| | | | | | | | | | | | | | The macro has n > 32. It has to be n > 31 since GPIO 0-31 are on Register 0 and 32-63 on Register 1. Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
* | Merge pull request #1793 from marex/arm/master/fixes-v2.0.0Antonio Niño Díaz2019-01-314-6/+10
|\ \ | | | | | | Arm/master/fixes v2.0.0
| * | rcar_gen3: plat: Add missing cpu_on_check() implementationMarek Vasut2019-01-291-1/+1
| | | | | | | | | | | | | | | | | | | | | The ATF code fails to build with PMIC_ROHM_BD9571=0, add the missing function into the PWRC code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * | rcar_gen3: plat: Allow E3 auto-detectionMarek Vasut2019-01-291-2/+8
| | | | | | | | | | | | | | | | | | Allow auto-detecting E3 when RCAR_LSI is set to RCAR_AUTO. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * | rcar_gen3: plat: Drop unused macroMarek Vasut2019-01-291-2/+0
| | | | | | | | | | | | | | | | | | The macro is not used, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * | Revert "rcar_gen3: plat: Enable programmable CPU reset address"Marek Vasut2019-01-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d48536e2f92d47ebb92cf12b35133c3be2d0e459, which misbehaves on R-Car H3 ES2.0. Until the reason for that misbehavior is understood, revert the commit. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* | | Merge pull request #1791 from antonio-nino-diaz-arm/an/rk-gicAntonio Niño Díaz2019-01-303-17/+12
|\ \ \ | | | | | | | | rockchip: Fix GICv2 interrupts
| * | | rockchip: Fix GICv2 interruptsAntonio Nino Diaz2019-01-283-17/+12
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the removal of deprecated interfaces in TF 2.0 the migration to the new GIC driver interfaces was done incorrectly in rk3328 and rk3368: 2d6f1f01b141 ("rockchip: Migrate to new interfaces"). In the GICv2 driver it is mandated that all interrupts are Group 0 interrupts. This patch simply moves all Group 1 interrupts to Group 0. Change-Id: I224c0135603eb5b81bd512976361500c0d129a91 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1789 from Anson-Huang/lpmAntonio Niño Díaz2019-01-3013-110/+444
|\ \ \ | | | | | | | | Add power optimization for i.MX8QM/i.MX8QX
| * | | imx: power optimization for i.mx8qxAnson Huang2019-01-294-27/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation of i.MX8QX power management related features does NOT optimize power number, all system resources like CCI, DDR, and A cluster etc. are kept in STBY mode (powered ON) when system suspend or CPU hotplug. To lower the power number, OFF mode should be adopted for those system resources whenever they can be OFF, A cluster will be OFF if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF if system suspend, IRQ steer can be OFF if the wakeup source is belonged to system controller partition, so wakeup source runtime check is used to determine if IRQ steer can be OFF before system suspend. If resources are powered off for suspend, they should be restored properly after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| * | | imx: power optimization for i.mx8qmAnson Huang2019-01-299-83/+290
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation of i.MX8QM power management related features does NOT optimize power number, all system resources like CCI, DDR, and A cluster etc. are kept in STBY mode (powered ON) when system suspend or CPU hotplug. To lower the power number, OFF mode should be adopted for those system resources whenever they can be OFF, A cluster will be OFF if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF if system suspend, IRQ steer can be OFF if the wakeup source is belonged to system controller partition, so wakeup source runtime check is used to determine if IRQ steer can be OFF before system suspend. If resources are powered off for suspend, they should be restored properly after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* | | Merge pull request #1788 from laroche/rpi3_duplicate_initializationAntonio Niño Díaz2019-01-292-6/+1
|\ \ \ | |/ / |/| | rpi3: Remove duplicate initialization for BL32_IMAGE_ID and mark one more function as static.
| * | rpi3: mark one more function as staticFlorian La Roche2019-01-281-1/+1
| | | | | | | | | | | | Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
| * | rpi3: remove duplicate initialization for BL32_IMAGE_IDFlorian La Roche2019-01-281-5/+0
| | | | | | | | | | | | Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
* | | Merge pull request #1773 from grandpaul/rpi3-gpio-driverAntonio Niño Díaz2019-01-283-0/+29
|\ \ \ | | | | | | | | Rpi3 gpio driver
| * | | rpi3: Enable GPIO in BL2Ying-Chun Liu (PaulLiu)2019-01-263-0/+29
| |/ / | | | | | | | | | | | | | | | | | | This patch inits the GPIO in BL2 earlysetup. So BL2 can start operating GPIO pins. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
* | | fvp: pwrc: Move to drivers/ folderAntonio Nino Diaz2019-01-259-146/+10
| | | | | | | | | | | | | | | Change-Id: I670ea80e0331c2d4b2ccfa563a45469a43f6902d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | plat/arm: sds: Move to drivers/ folderAntonio Nino Diaz2019-01-258-581/+6
| | | | | | | | | | | | | | | Change-Id: Ia601d5ad65ab199e747fb60af4979b7db477d249 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | plat/arm: scp: Move to drivers/ folderAntonio Nino Diaz2019-01-2510-953/+18
| | | | | | | | | | | | | | | Change-Id: Ida5dae39478654405d0ee31a6cbddb4579e76a7f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | plat/arm: scpi: Move to drivers/ folderAntonio Nino Diaz2019-01-256-384/+12
| | | | | | | | | | | | | | | Change-Id: Icc59cdaf2b56f6936e9847f1894594c671db2e94 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | plat/arm: mhu: Move to drivers/ folderAntonio Nino Diaz2019-01-2512-226/+20
| | | | | | | | | | | | | | | Change-Id: I656753a1825ea7340a3708b950fa6b57455e9056 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | plat/arm: scmi: Move to drivers/ folderAntonio Nino Diaz2019-01-2516-792/+16
| | | | | | | | | | | | | | | Change-Id: I8989d2aa0258bf3b50a856c5b81532d578600124 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | plat/arm: Move dynamic xlat enable logic to makefileAntonio Nino Diaz2019-01-254-26/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PLAT_XLAT_TABLES_DYNAMIC build option, defined in platform_def.h in Arm platforms, is checked by several headers, affecting their behaviour. To avoid issues around the include ordering of the headers, the definition should be moved to the platform's makefile. Change-Id: I0e12365c8d66309122e8a20790e1641a4f480a10 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | plat/arm: Sanitise includesAntonio Nino Diaz2019-01-2588-180/+131
|/ / | | | | | | | | | | | | | | | | | | | | Use full include paths like it is done for common includes. This cleanup was started in commit d40e0e08283a ("Sanitise includes across codebase"), but it only cleaned common files and drivers. This patch does the same to Arm platforms. Change-Id: If982e6450bbe84dceb56d464e282bcf5d6d9ab9b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1761 from satheesbalya-arm/sb1/sb1_2661_bl31_overlayAntonio Niño Díaz2019-01-253-12/+57
|\ \ | | | | | | plat/arm: Save BL2 descriptors to reserved memory.
| * | plat/arm: Save BL2 descriptors to reserved memory.Sathees Balya2019-01-233-12/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM platforms, the BL2 memory can be overlaid by BL31/BL32. The memory descriptors describing the list of executable images are created in BL2 R/W memory, which could be possibly corrupted later on by BL31/BL32 due to overlay. This patch creates a reserved location in SRAM for these descriptors and are copied over by BL2 before handing over to next BL image. Also this patch increases the PLAT_ARM_MAX_BL2_SIZE for juno when TBBR is enabled. Fixes ARM-Software/tf-issues#626 Change-Id: I755735706fa702024b4032f51ed4895b3687377f Signed-off-by: Sathees Balya <sathees.balya@arm.com>
* | | Merge pull request #1766 from Anson-Huang/masterAntonio Niño Díaz2019-01-259-1/+1261
|\ \ \ | | | | | | | | Add more SIP runtime service for i.MX8
| * | | imx: add i.MX8 SoCs build info SIP(silicon provider) service supportAnson Huang2019-01-183-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NXP i.MX8 SoCs' build info SIP support for easy debug. With this function enabled, TF-A's commit hash can be showed in u-boot debug console when booting up, when there is any issue which could be related to TF-A, users can use the commit hash value to easily identify which commit introduces the issue. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| * | | imx: add i.MX8 SoCs thermal alarm SIP(silicon provider) service supportAnson Huang2019-01-183-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For NXP's i.MX8 SoCs with system controller inside, thermal sensors are maintained by SCFW, Linux needs to call SMC to trap to TF-A for thermal alarm operation etc. by calling SCFW API. This patch adds temperature alarm SIP service support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| * | | imx: add i.MX8 SoCs OTP SIP(silicon provider) service supportAnson Huang2019-01-183-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For NXP's i.MX8 SoCs with system controller inside, OTP is maintained by SCFW, Linux needs to call SMC to trap to TF-A for OTP read/write etc. operations by calling SCFW API. This patch adds OTP SIP service support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| * | | imx: support for i.MX8 SoCs misc IPCAnson Huang2019-01-185-1/+1124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NXP's i.MX8 SoCs have system controller (M4 core) which takes control of misc functions like temperature alarm, dma etc., other Cortex-A clusters can send out command via MU (Message Unit) to system controller for misc operation etc.. This patch adds misc IPC(inter-processor communication) support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| * | | imx: add wakeup source SIP runtime service supportAnson Huang2019-01-184-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On i.MX8QM/i.MX8QX with system controller inside, the wakeup source is managed in SCFW(system controller firmware), if the wakeup source is belonged to system controller partition, then before Linux suspend, the wakeup source should be set to SC_PM_WAKE_SRC_SCU, and if the wakeup source is belonged to Cortex-A partition, the wakeup source should be set to SC_PM_WAKE_SRC_IRQSTEER, so need to add wakeup source SIP runtime service to get Linux kernel's wakeup source and set the correct wakeup source for system controller. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* | | | Merge pull request #1777 from glneo/runtime-gicrAntonio Niño Díaz2019-01-254-9/+25
|\ \ \ \ | | | | | | | | | | ti: k3: common: Add support for runtime detection of GICR base address
| * | | | ti: k3: common: Add support for runtime detection of GICR base addressAndrew F. Davis2019-01-224-9/+25
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Valid addresses for GICR base are always a set calculable distance from the GICD and is based on the number of cores a given instance of GICv3 IP can support. The formula for the number of address bits is given by the ARM GIC-500 TRM section 3.2 as 2^(18+log2(cores)) with the MSB set to one for GICR instances. Holes in the GIC address space are also guaranteed to safely return 0 on reads. This allows us to support runtime detection of the GICR base address by starting from GIC base address plus BIT(18) and walking until the GICR ID register (IIDR) is detected. We stop searching after BIT(20) to prevent searching out into space if something goes wrong. This can be extended out if we ever have a device with 16 or more cores. Signed-off-by: Andrew F. Davis <afd@ti.com>
* | | | Merge pull request #1779 from Anson-Huang/a53_errataAntonio Niño Díaz2019-01-252-0/+8
|\ \ \ \ | | | | | | | | | | Enable necessary A53 erratas for i.MX8QM and i.MX8MQ
| * | | | imx: enable necessary errata for i.mx8qmAnson Huang2019-01-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NXP's i.MX8QM uses Cortex-A53 r0p4, enable necessary erratas for it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| * | | | imx: enable necessary errata for i.mx8mqAnson Huang2019-01-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NXP's i.MX8MQ uses Cortex-A53 r0p4, enable necessary erratas for it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* | | | | Tegra186: remove RELOCATE_TO_BL31_BASE configVarun Wadekar2019-01-231-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes this unused config option from the Tegra186 platform makefiles. Change-Id: Idcdf6854332a26599323a247289c2d3ce19f475f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | | Tegra: memctrl_v2: remove usage of ENABLE_SMMU_DEVICE configVarun Wadekar2019-01-232-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the usage of this platform config, as it is always enabled by all the supported platforms. Change-Id: Ie7adb641adeb3604b177b6960b797722d60addfa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | | Tegra: add 'late' platform setup handlerDilan Lee2019-01-232-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a platform setup handler that gets called after the MMU is enabled. Platforms wanting to make use of this handler should declare 'plat_late_platform_setup' handler in their platform files, to override the default weakly defined handler. Change-Id: Ibc97a2e5a24608ddea856d0bd543a9d5876f604c Signed-off-by: Dilan Lee <dilee@nvidia.com>
* | | | | Tegra: spe: shared console for Tegra platformsVarun Wadekar2019-01-231-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are Tegra platforms which have limited UART ports and so all the components have to share the console. The SPE helps out by collecting all the logs in such cases and prints them on the shared UART port. This patch adds a driver to communicate with the SPE driver, which in turn provides the console. Change-Id: Ie750520b936b8bed0ab1d876f03fc0a3490a85a3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | | Tegra: console driver compilation from platform makefilesVarun Wadekar2019-01-234-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the console driver from individual platform makefiles and removes it from tegra_common.mk. This allows future platforms to include consoles of their choice. Change-Id: I7506562bfac78421a80fb6782ac8472fbef6cfb0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | | Tegra: smmu: change exit criteria for context size calculationVarun Wadekar2019-01-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra SoCs currently do not have a SMMU register at address 0xFFFFFFFF. This patch changes the search criteria, to look for this marker, to calculate the size of the saved context. Change-Id: I15d91945ecb78267f91c45f37985dbb2327ca3ae Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | | Tegra: memctrl_v2: platform handler for TZDRAM setupSteven Kao2019-01-232-18/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra memctrl driver sets up the TZDRAM fence during boot and system suspend exit. This patch provides individual platforms with handlers to perform custom steps during TZDRAM setup. Change-Id: Iee094d6ca189c6dd24f1147003c33c99ff3a953b Signed-off-by: Steven Kao <skao@nvidia.com>
* | | | | Tegra186: save system suspend entry marker to TZDRAMVarun Wadekar2019-01-233-10/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to save the system suspend entry and exit markers to TZDRAM to help the trampoline code decide if the current warmboot is actually an exit from System Suspend. The Tegra186 platform handler sets the system suspend entry marker before entering SC7 state and the trampoline flips the state back to system resume, on exiting SC7. Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | | Tegra186: helper functions for CPU rst handler and SMMU ctx offsetVarun Wadekar2019-01-233-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a helper function to get the SMMU context's offset and uses another helper function to get the CPU trampoline offset. These helper functions are used by the System Suspend entry sequence to save the SMMU context and CPU reset handler to TZDRAM. Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | | Tegra: bpmp: return error if BPMP init failsVarun Wadekar2019-01-232-27/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch returns error if BPMP initialization fails. The platform code marks the cluster as "runnning" since we wont be able to get it into the low power state without BPMP. Change-Id: I86f51d478626240bb7b4ccede8907674290c5dc1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | | Tegra: rename secure scratch register macrosSteven Kao2019-01-236-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch renames all the secure scratch registers to reflect their usage. This is a list of all the macros being renamed: - SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_* - SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG - SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_* - SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_* - SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_* NOTE: Future SoCs will have to define these macros to keep the drivers functioning. Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987 Signed-off-by: Steven Kao <skao@nvidia.com>
* | | | | Tegra: memctrl_v2: platform handler for TZDRAM settingsVarun Wadekar2019-01-233-17/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra memctrl driver sets up the TZDRAM fence during boot and system suspend exit. This patch provides individual platforms with handlers to perform platform specific steps, e.g. enable encryption, save base/size to secure scratch registers. Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 08:09:42 +0000