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* allwinner: regulators: pick correct DT subnodeAndre Przywara2019-03-081-4/+8
| | | | | | | | | | | | | | So far the DT node describing the AXP803 PMIC used in many Allwinner A64 boards had only one subnode, so our code just entering the first subnode to find all regulators worked fine. However recent DT updates in the Linux kernel add more subnodes *before* that, so we need to make sure to explicitly enter the "regulators" subnode to find the information we are after. Improve some DT node parsing error handling on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* zynqmp: pm: Add support for setting PMU configuration objectLuca Ceresoli2019-03-081-1/+4
| | | | | | | | | Allow EL2 (e.g. U-Boot) to load the configuration object at runtime into the Xilinx ZynqMP PMU firmware. This allows booting with U-Boot and U-Boot SPL with PMU FW without hard-coding the configuration object. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
* Merge pull request #1863 from thloh85-intel/mmc_fixesDimitris Papastamos2019-03-081-0/+1
|\ | | | | drivers: mmc: Fix some issues with MMC stack
| * plat: intel: Add MMC OCR voltage information for initializationTien Hock, Loh2019-03-081-0/+1
| | | | | | | | | | | | | | MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
* | Merge pull request #1864 from hadi-asyrafi/mailbox_fixDimitris Papastamos2019-03-071-5/+10
|\ \ | | | | | | intel: Mailbox service un-accessible
| * | intel: Mailbox service un-accessibleMuhammad Hadi Asyrafi Abdul Halim2019-03-071-5/+10
| | | | | | | | | | | | | | | | | | Change map region for device 2 from non-secure to secure Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
* | | Merge pull request #1862 from thloh85-intel/s10_bl2Dimitris Papastamos2019-03-071-1/+2
|\ \ \ | | | | | | | | plat: intel: Improve ECC scrubbing performance
| * | | plat: intel: Improve ECC scrubbing performanceTien Hock, Loh2019-03-071-1/+2
| | |/ | |/| | | | | | | | | | | | | | | | We should be using zeromem to scrub memory instead of memset. This would improve the performance by 200x Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
* | | stm32mp1: zeromem device_info structYann Gautier2019-03-071-1/+2
| |/ |/| | | | | | | | | | | | | | | | | The change of the structure highlighted the fact that all fields are not correctly initialized with zeroes. Replace the other memset in the function with zeromem, as it is faster. Change-Id: I27f45a64e34637f79fa519f486bf5936721ef396 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | Merge pull request #1847 from jts-arm/mbedtlsAntonio Niño Díaz2019-03-051-23/+1
|\ \ | | | | | | Remove Mbed TLS dependency from plat_bl_common.c
| * | Remove Mbed TLS dependency from plat_bl_common.cJohn Tsichritzis2019-02-281-23/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the shared Mbed TLS heap optimisation introduced in 6d01a463, common code files were depending on Mbed TLS specific headers. This dependency is now removed by moving the default, unoptimised heap implementation inside the Mbed TLS specific files. Change-Id: I11ea3eb4474f0d9b6cb79a2afd73a51a4a9b8994 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | | Merge pull request #1853 from vwadekar/dummy_io_storageAntonio Niño Díaz2019-03-054-3/+30
|\ \ \ | | | | | | | | Tegra: dummy support for the io_storage backend
| * | | Tegra: dummy support for the io_storage backendVarun Wadekar2019-03-014-3/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides dummy macros and platform files to compile the io_storage driver backend. This patch is necessary to remove the "--unresolved=el3_panic" linker flag from Tegra's makefiles and allow us to revert this workaround, previously suggested by the ARM toolchain team. The "--unresolved=el3_panic" flag actually was a big hammer that allowed Tegra platforms to work with armlink previously but it masks legit errors with the code as well. Change-Id: I0421d35657823215229f84231896b84167f90548 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | rcar_gen3: Add M3-W 3.0 supportMarek Vasut2019-03-044-5/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the M3W 3.0 SoC and synchronize the upstream ATF with Renesas downstream ATF release v2.0.1. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* | | | Merge pull request #1844 from chandnich/rename_sgiclarkAntonio Niño Díaz2019-03-043-17/+17
|\ \ \ \ | | | | | | | | | | css/sgi: replace all uses of Clark with new product names
| * | | | css/sgi: replace all uses of Clark with new product namesChandni Cherukuri2019-02-283-17/+17
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace all uses of 'SGI_CLARK' with 'RD_N1E1_EDGE' and 'SGI_CLARK_HELIOS' with 'RD_E1_EDGE' as per the updated product names Change-Id: Ib8136e421b1a46da1e5df58c6b1432d5c78d279b Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | | Merge pull request #1837 from spencercw/masterAntonio Niño Díaz2019-03-042-0/+10
|\ \ \ \ | |_|/ / |/| | | imx: Configure CAAM job rings master ID for i.MX8MQ
| * | | imx: Configure CAAM job rings master ID for i.MX8MQChris Spencer2019-02-222-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For i.MX8MQ B0 revision the default configuration of JRaMID is not valid to allow the kernel to use the CAAM job rings. This patch sets the master ID of the Cortex A in the JRaMID registers. Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk>
* | | | Merge pull request #1815 from Anson-Huang/gicAntonio Niño Díaz2019-03-011-0/+21
|\ \ \ \ | | | | | | | | | | gic: make sure ProcessorSleep bit clear successfully
| * | | | imx: make sure GIC redistributor is awake before initializationAnson Huang2019-03-011-0/+21
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GICR_WAKER.ProcessorSleep can only be set to zero when: — GICR_WAKER.Sleep bit[0] == 0. — GICR_WAKER.Quiescent bit[31] == 0. On some platforms, when system reboot with GIC in sleep mode but with power ON, such as on NXP's i.MX8QM, Linux kernel enters suspend but could be requested to reboot, and GIC is in sleep mode and it is inside a power domain which is ON in this scenario, when CPU reset, the GIC driver trys to set CORE's redistributor interface to awake, with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] both set, the ProcessorSleep bit[1] will never be clear and cause system hang. This patch makes sure GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] are both zeor before clearing ProcessorSleep bit[1]. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* | | | Merge pull request #1751 from vwadekar/tegra-scatter-file-supportAntonio Niño Díaz2019-03-012-0/+299
|\ \ \ \ | | | | | | | | | | Tegra scatter file support
| * | | | Tegra: Support for scatterfile for the BL31 imageVarun Wadekar2019-02-272-0/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support for using the scatterfile format as the linker script with the 'armlink' linker for Tegra platforms. In order to enable the scatterfile usage the following changes have been made: * provide mapping for ld.S symbols in bl_common.h * include bl_common.h from all the affected files * update the makefile rules to use the scatterfile and armlink to compile BL31 * update pubsub.h to add sections to the scatterfile NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY. Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | | Merge pull request #1845 from ambroise-arm/av/errataAntonio Niño Díaz2019-03-011-0/+5
|\ \ \ \ \ | | | | | | | | | | | | Apply workarounds for errata of Cortex-A53, A55 and A57
| * | | | | juno: Enable CPU errata workaroundsAmbroise Vincent2019-02-281-0/+5
| | |/ / / | |/| | | | | | | | | | | | | | | | | | Change-Id: I7593f5ed89b9ef13b510e2259c909838c64ec56c Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* / | | | Minor changes to documentation and commentsAntonio Nino Diaz2019-02-281-7/+7
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | Fix some typos and clarify some sentences. Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | Merge pull request #1829 from antonio-nino-diaz-arm/an/pauthAntonio Niño Díaz2019-02-272-0/+37
|\ \ \ \ | | | | | | | | | | Add Pointer Authentication (ARMv8.3-PAuth) support to the TF
| * | | | plat/arm: Implement ARMv8.3-PAuth interfacesAntonio Nino Diaz2019-02-272-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature is only supported on FVP. Change-Id: I4e265610211d92a84bd2773c34acfbe02a1a1826 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | | Merge pull request #1840 from grandpaul/rpi3-sdhost-improve1Antonio Niño Díaz2019-02-271-2/+2
|\ \ \ \ \ | | | | | | | | | | | | RaspberryPi3 sdhost driver improvement.
| * | | | | rpi3: sdhost: SDHost driver improvementYing-Chun Liu (PaulLiu)2019-02-271-2/+2
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit improves the SDHost driver for RPi3 as following: * Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on block reading. * In some low probability that SEND_OP_COND might results CRC7 error. We can consider that the command runs correctly. We don't need to retry this command so removing the code for retry. * Using MMC_BUS_WIDTH_1 as MMC default value to improve the stability. * Increase the clock to 50Mhz in data mode to speed up the io. * Change the pull resistors configuration to gain more stability. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
* | | | | Merge pull request #1838 from chandnich/renameAntonio Niño Díaz2019-02-2714-104/+104
|\ \ \ \ \ | |_|/ / / |/| | | | Apply official names to SGI-Clark Platforms
| * | | | board/rde1edge: rename sgiclarkh to rde1edgeChandni Cherukuri2019-02-277-52/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarkh' with 'rde1edge' as per the updated product names. Change-Id: I14e9b0332851798531de21d70eb54f1e5557a7bd Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | | | board/rdn1edge: rename sgiclarka to rdn1edgeChandni Cherukuri2019-02-277-52/+52
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarka' with 'rdn1edge' as per the updated product names. Change-Id: Idbc157c73477ec32f507ba2d4a4e907d8813374c Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | | Merge pull request #1834 from thloh85-intel/s10_bl31Antonio Niño Díaz2019-02-2710-19/+1214
|\ \ \ \ | | |_|/ | |/| | plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
| * | | plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platformTien Hock, Loh2019-02-2610-19/+1214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
* | | | Merge pull request #1826 from smaeul/allwinnerAntonio Niño Díaz2019-02-277-25/+34
|\ \ \ \ | |_|/ / |/| | | allwinner: A few minor improvements
| * | | allwinner: Clean up CPU ops functionsSamuel Holland2019-02-174-21/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert them to take an mpidr instead of a (cluster, core) pair. This simplifies all of the call sites, and actually makes the functions a bit smaller. Signed-off-by: Samuel Holland <samuel@sholland.org>
| * | | allwinner: Constify data structuresSamuel Holland2019-02-173-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | This maximizes the amount of data protected by the MMU. Signed-off-by: Samuel Holland <samuel@sholland.org>
* | | | Merge pull request #1836 from Yann-lms/docs_and_m4Antonio Niño Díaz2019-02-223-0/+5
|\ \ \ \ | | | | | | | | | | Update documentation for STM32MP1 and add Cortex-M4 support
| * | | | stm32mp1: add minimal support for co-processor Cortex-M4Yann Gautier2019-02-203-0/+5
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4. The support for Cortex-M4 clocks is added when configuring the clock tree. Some minimal security features to allow communications between A7 and M4 are also added. Change-Id: I60417e244a476f60a2758f4969700b2684056665 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | | Merge pull request #1835 from jts-arm/renameAntonio Niño Díaz2019-02-226-22/+22
|\ \ \ \ | |_|_|/ |/| | | Apply official names to new Arm Neoverse cores
| * | | Rename Cortex-Helios to Neoverse E1John Tsichritzis2019-02-191-2/+2
| | | | | | | | | | | | | | | | | | | | Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
| * | | Rename Cortex-Ares to Neoverse N1John Tsichritzis2019-02-195-20/+20
| |/ / | | | | | | | | | | | | Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | | Merge pull request #1828 from uarif1/masterAntonio Niño Díaz2019-02-2120-18/+900
|\ \ \ | | | | | | | | Introduce Versatile Express FVP platform to arm-trusted-firmware.
| * | | plat/arm: Support for Cortex A5 in FVP Versatile Express platformUsama Arif2019-02-192-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex A5 doesnt support VFP, Large Page addressing and generic timer which are addressed in this patch. The device tree for Cortex a5 is also included. Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678 Signed-off-by: Usama Arif <usama.arif@arm.com>
| * | | plat/arm: Introduce FVP Versatile Express platform.Usama Arif2019-02-1918-6/+882
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Versatile express FVP (Fast models). Versatile express is a family of platforms that are based on ARM v7. Currently this port has only been tested on Cortex A7, although it should work with other ARM V7 cores that support LPAE, generic timers, VFP and hardware divide. Future patches will support other cores like Cortex A5 that dont support features like LPAE and hardware divide. This platform is tested on and only expected to work on single core models. Change-Id: I10893af65b8bb64da7b3bd851cab8231718e61dd Signed-off-by: Usama Arif <usama.arif@arm.com>
| * | | Rename PLAT_ARM_BL31_RUN_UART* variableUsama Arif2019-02-183-12/+12
| |/ / | | | | | | | | | | | | | | | | | | | | | The variable is renamed to PLAT_ARM_RUN_UART as the UART is used outside BL31 as well. Change-Id: I00e3639dfb2001758b7d24548c11236c6335f64a Signed-off-by: Usama Arif <usama.arif@arm.com>
* / / rcar_gen3: plat: Prevent PCIe hang during L1X config accessMarek Vasut2019-02-202-2/+74
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the PCIe controller receives a L1_Enter_PM DLLP, it will disable the internal PLLs. The system software cannot predict it and can attempt to perform device config space access across the PCIe link while the controller is in this transitional state. If such condition happens, the PCIe controller register access will trigger ARM64 SError exception. This patch adds checks for which PCIe controller is enabled, checks whether the PCIe controller is in such a transitional state and if so, first completes the transition and then restarts the instruction which caused the SError. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* | Merge pull request #1824 from antonio-nino-diaz-arm/an/move-dyn-xlatAntonio Niño Díaz2019-02-181-1/+4
|\ \ | | | | | | fvp: trusty: Move dynamic xlat enable to platform
| * | fvp: trusty: Move dynamic xlat enable to platformAntonio Nino Diaz2019-02-121-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than letting the Trusty makefile set the option to enable dynamic translation tables, make platforms do it themselves. This also allows platforms to replace the implementation of the translation tables library as long as they use the same function prototypes. Change-Id: Ia60904f61709ac323addcb57f7a83391d9e21cd0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | stm32mp1: update clock driverYann Gautier2019-02-147-37/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove useless private structure in function prototypes. Add a reference counter on clocks. Prepare for future secured/shared/non-secured clocks. Change-Id: I3dbed81721da5ceff5e10b2c4155b1e340c036ee Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
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