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* ti: k3: common: Rename device IDs to be more consistentAndrew F. Davis2020-01-271-15/+15
* Merge "plat/sgm: Always use SCMI for SGM platforms" into integrationManish Pandey2020-01-271-0/+2
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| * plat/sgm: Always use SCMI for SGM platformsChris Kay2020-01-241-0/+2
* | Merge "xilinx: Unify Platform specific defines for PSCI module" into integrationMark Dykes2020-01-242-4/+4
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| * xilinx: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-242-4/+4
* | ti: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-241-5/+5
* | st: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-241-1/+1
* | layerscape: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-241-7/+7
* | qemu: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-242-9/+9
* | socionext: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-242-6/+6
* | mediatek: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-243-17/+17
* | intel: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-241-5/+5
* | marvell: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-242-4/+4
* | rockchip: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-245-23/+23
* | allwinner: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-241-3/+3
* | imx: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-246-31/+31
* | hisilicon: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-243-12/+12
* | Merge changes from topic "tegra-downstream-01202020" into integrationSoby Mathew2020-01-2414-410/+569
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| * | Tegra194: mce: remove unused NVG functionsVarun Wadekar2020-01-232-99/+6
| * | Tegra194: support for NVG interface v6.6Varun Wadekar2020-01-231-102/+188
| * | Tegra194: smmu: add PCIE0R1 mc reg to system suspend save listPritesh Raithatha2020-01-232-3/+5
| * | Tegra194: enable driver for general purpose DMA engineVarun Wadekar2020-01-233-1/+14
| * | Tegra194: access XUSB_PADCTL registers on Si/FPGA platformsVarun Wadekar2020-01-232-24/+30
| * | Tegra194: organize the memory/mmio map to make it linearVarun Wadekar2020-01-232-37/+35
| * | Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1Pritesh Raithatha2020-01-231-0/+2
| * | Tegra194: support for boot params wider than 32-bitsSteven Kao2020-01-232-6/+19
| * | Tegra194: memctrl: set reorder depth limit for PCIE blocksPuneet Saxena2020-01-232-0/+24
| * | Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIUPritesh Raithatha2020-01-231-0/+22
| * | Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULTPritesh Raithatha2020-01-231-157/+119
| * | Tegra194: memctrl: update mss reprogramming as HW PROD settingsPuneet Saxena2020-01-232-98/+164
| * | Tegra194: memctrl: Disable PVARDC coalescerArto Merilainen2020-01-232-1/+13
| * | Tegra194: memctrl: force seswr/rd transactions as passsthru & coherentPuneet Saxena2020-01-231-2/+6
| * | Tegra194: Request CG7 from last core in clusterVignesh Radhakrishnan2020-01-231-0/+2
| * | Tegra194: toggle SE clock during context save/restoresteven kao2020-01-234-1/+41
| * | Tegra: bpmp: fix header file pathsVarun Wadekar2020-01-232-4/+4
* | | Merge "Prevent speculative execution past ERET" into integrationSoby Mathew2020-01-241-2/+2
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| * | | Prevent speculative execution past ERETAnthony Steinhauser2020-01-221-2/+2
* | | | Merge "Xilinx zynqmp: add missing pin control group for ethernet 0." into int...Manish Pandey2020-01-241-1/+2
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| * | | Xilinx zynqmp: add missing pin control group for ethernet 0.Norbert Werner2020-01-221-1/+2
* | | | Merge changes from topic "bridge-en" into integrationManish Pandey2020-01-2328-719/+551
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| * | | | intel: Add function to check fpga readinessHadi Asyrafi2020-01-165-23/+28
| * | | | intel: Add bridge control for FPGA reconfigHadi Asyrafi2020-01-163-0/+18
| * | | | intel: FPGA config_isdone() status queryHadi Asyrafi2020-01-161-3/+8
| * | | | intel: System Manager refactoringHadi Asyrafi2020-01-1616-410/+258
| * | | | intel: Refactor reset manager driverHadi Asyrafi2020-01-1615-507/+268
| * | | | intel: Enable bridge access in Intel platformHadi Asyrafi2020-01-1611-9/+175
| * | | | intel: Modify non secure access functionHadi Asyrafi2020-01-165-2/+31
* | | | | Merge "xilinx: versal: PLM to ATF handover" into integrationAlexei Fedorov2020-01-235-21/+39
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| * | | | | xilinx: versal: PLM to ATF handoverVenkatesh Yadav Abbarapu2020-01-235-21/+39
* | | | | | Merge "xilinx: common: Move ATF handover to common file" into integrationAlexei Fedorov2020-01-235-22/+39
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