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| | * | SPE: Fix feature detectionAndre Przywara2020-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the feature test for the SPE extension requires the feature bits in the ID_AA64DFR0 register to read exactly 0b0001. However the architecture guarantees that any values greater than 0 indicate the presence of a feature, which is what we are after in our spe_supported() function. Change the comparison to include all values greater than 0. This fixes SPE support in non-secure world on implementations which include the Scalable Vector Extension (SVE), for instance on Zeus cores. Change-Id: If6cbd1b72d6abb8a303e2c0a7839d508f071cdbe Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | lib: fconf: Implement a parser to populate CoTManish V Badarkhe2020-09-151-0/+497
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implemented a parser which populates the properties of the CoT descriptors as per the binding document [1]. 'COT_DESC_IN_DTB' build option is disabled by default and can be enabled in future for all Arm platforms by making necessary changes in the memory map. Currently, this parser is tested only for FVP platform. [1]: https://trustedfirmware-a.readthedocs.io/en/latest/components/cot-binding.html Change-Id: I2f911206087a1a2942aa728de151d2ac269d27cc Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
| * | | Merge "libc: Import strlcat from FreeBSD project" into integrationMark Dykes2020-09-111-0/+56
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| | * | | libc: Import strlcat from FreeBSD projectMadhukar Pappireddy2020-09-091-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b Made small changes to fit into TF-A project Change-Id: I07fd7fe1037857f6b299c35367c104fb51fa5cfa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | | | Merge "libc: Add support for vsnprintf()" into integrationMark Dykes2020-09-111-7/+37
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| | * | | | libc: Add support for vsnprintf()Madhukar Pappireddy2020-09-111-7/+37
| | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | It uses the existing implementation of snprintf() function Change-Id: Ie59418564c2e415222e819cf322c34e9a4d1f336 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | | | Merge "Workaround for Neoverse N1 erratum 1868343" into integrationMadhukar Pappireddy2020-09-112-0/+46
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| | * | | Workaround for Neoverse N1 erratum 1868343johpow012020-09-102-0/+46
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse N1 erratum 1868343 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. SDEN can be found here: https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844
| * | | Merge "libc: memset: improve performance by avoiding single byte writes" ↵Mark Dykes2020-09-091-2/+32
| |\ \ \ | | |/ / | |/| | | | | | into integration
| | * | libc: memset: improve performance by avoiding single byte writesAndre Przywara2020-09-031-2/+32
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently our memset() implementation is safe, but slow. The main reason for that seems to be the single byte writes that it issues, which can show horrible performance, depending on the implementation of the load/store subsystem. Improve the algorithm by trying to issue 64-bit writes. As this only works with aligned pointers, have a head and a tail section which covers unaligned pointers, and leave the bulk of the work to the middle section that does use 64-bit writes. Put through some unit tests, which exercise all combinations of nasty input parameters (pointers with various alignments, various odd and even sizes, corner cases of content to write (-1, 256)). Change-Id: I28ddd3d388cc4989030f1a70447581985368d5bb Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | Merge "lib: cpu: Check SCU presence in DSU before accessing DSU registers" ↵Manish Pandey2020-09-032-10/+41
| |\ \ | | | | | | | | | | | | into integration
| | * | lib: cpu: Check SCU presence in DSU before accessing DSU registersPramod Kumar2020-09-022-10/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DSU contains system control registers in the SCU and L3 logic to control the functionality of the cluster. If "DIRECT CONNECT" L3 memory system variant is used, there won't be any L3 cache, snoop filter, and SCU logic present hence no system control register will be present. Hence check SCU presence before accessing DSU register for DSU_936184 errata. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63
| * | | psci: utility api to invoke stop for other coresSandeep Tripathy2020-09-031-0/+47
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | The API can be used to invoke a 'stop_func' callback for all other cores from any initiating core. Optionally it can also wait for other cores to power down. There may be various use of such API by platform. Ex: Platform may use this to power down all other cores from a crashed core. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Change-Id: I4f9dc8a38d419f299c021535d5f1bcc6883106f9
| * | cpus: denver: skip DCO enable/disable for recent SKUsVarun Wadekar2020-08-311-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | DCO is not supported by the SKUs released after MIDR_PN4. This patch skips enabling or disabling the DCO on these SKUs. Change-Id: Ic31a829de3ae560314d0fb5c5e867689d4ba243b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | lib: cpus: denver: add MIDR PN9 variantHemant Nigam2020-08-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces support for PN9 variant for some Denver based platforms. Original change by: Hemant Nigam <hnigam@nvidia.com> Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Change-Id: I331cd3a083721fd1cd1b03f4a11b32fd306a21f3
| * | cpus: denver: introduce macro to declare cpu_opsVarun Wadekar2020-08-311-62/+19
| | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a macro to declare cpu_op for all Denver SKUs. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ibcf88c3256fc5dcaa1be855749ebd2c5c396c977
| * | Add support for hexadecimal and pointer format specifiers to snprintf()Javier Almansa Sobrino2020-08-261-16/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of snprintf() does not support pointer and hexadecimal format specifiers, which can be needed, for instance, for DTB manipulations. This patch adds that functionality by borrowing some code from the printf() implementation. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I2076ea46693a73a04890982bf20e3c633c2767fb
| * | lib: cpus: sanity check pointers before useVarun Wadekar2020-08-241-0/+24
| |/ | | | | | | | | | | | | | | | | | | | | | | | | The cpu_ops structure contains a lot of function pointers. It is a good idea to verify that the function pointer is not NULL before executing it. This patch sanity checks each pointer before use to prevent any unforeseen crashes. These checks have been enabled for debug builds only. Change-Id: Ib208331c20e60f0c7c582a20eb3d8cc40fb99d21 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * Merge "Revert "libc/memset: Implement function in assembler"" into integrationMark Dykes2020-08-214-160/+20
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| | * Revert "libc/memset: Implement function in assembler"Mark Dykes2020-08-214-160/+20
| | | | | | | | | | | | | | | | | | | | | This reverts commit e7d344de01ad11b856233634717aafe9312697e4. This reverts the patch https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5313 due to a timing issue with the merge. The merge occurred at the same time as the additional comments and thusly were were not seen until the merge was done. This reverts the change and additional patches from Alexei will follow to address the concerns expressed in the orignal patch. Change-Id: Iae5f6403c93ac13ceeda29463883fcd4c437f2b7
| * | Merge changes from topic "at_errata_fix" into integrationOlivier Deprez2020-08-206-4/+129
| |\ \ | | |/ | |/| | | | | | | | | | | | | * changes: doc: Update description for AT speculative workaround lib/cpus: Report AT speculative erratum workaround Add wrapper for AT instruction
| | * lib/cpus: Report AT speculative erratum workaroundManish V Badarkhe2020-08-186-4/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reported the status (applies, missing) of AT speculative workaround which is applicable for below CPUs. +---------+--------------+ | Errata | CPU | +=========+==============+ | 1165522 | Cortex-A76 | +---------+--------------+ | 1319367 | Cortex-A72 | +---------+--------------+ | 1319537 | Cortex-A57 | +---------+--------------+ | 1530923 | Cortex-A55 | +---------+--------------+ | 1530924 | Cortex-A53 | +---------+--------------+ Also, changes are done to enable common macro 'ERRATA_SPECULATIVE_AT' if AT speculative errata workaround is enabled for any of the above CPUs using 'ERRATA_*' CPU specific build macro. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I3e6a5316a2564071f3920c3ce9ae9a29adbe435b
| * | libc/memset: Implement function in assemblerAlexei Fedorov2020-08-194-20/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trace analysis of FVP_Base_AEMv8A model running in Aarch32 mode with the build options listed below: TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem shows that when auth_signature() gets called 71.84% of CPU execution time is spent in memset() function written in C using single byte write operations, see lib\libc\memset.c. This patch replaces C memset() implementation with assembler version giving the following results: - for Aarch32 in auth_signature() call memset() CPU time reduced to 24.84%. - Number of CPU instructions executed during TF-A boot stage before start of BL33 in RELEASE builds: ---------------------------------------------- | Arch | C | assembler | % | ---------------------------------------------- | Aarch32 | 2073275460 | 1487400003 | -28.25 | | Aarch64 | 2056807158 | 1244898303 | -39.47 | ---------------------------------------------- The patch also replaces memset.c with aarch64/memset.S in plat\nvidia\tegra\platform.mk. Change-Id: Ifbf085a2f577a25491e2d28446ee95a4ac891597 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
| * | SPM: Change condition on saving/restoring EL2 registersRuari Phipps2020-08-191-2/+2
| |/ | | | | | | | | | | | | | | Make this more scalable by explicitly checking internal and hardware states at run_time Signed-off-by: Ruari Phipps <ruari.phipps@arm.com> Change-Id: I1c6ed1c1badb3538a93bff3ac5b5189b59cccfa1
| * runtime_exceptions: Update AT speculative workaroundManish V Badarkhe2020-08-181-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per latest mailing communication [1], we decided to update AT speculative workaround implementation in order to disable page table walk for lower ELs(EL1 or EL0) immediately after context switching to EL3 from lower ELs. Previous implementation of AT speculative workaround is available here: 45aecff00 AT speculative workaround is updated as below: 1. Avoid saving and restoring of SCTLR and TCR registers for EL1 in context save and restore routine respectively. 2. On EL3 entry, save SCTLR and TCR registers for EL1. 3. On EL3 entry, update EL1 system registers to disable stage 1 page table walk for lower ELs (EL1 and EL0) and enable EL1 MMU. 4. On EL3 exit, restore SCTLR and TCR registers for EL1 which are saved in step 2. [1]: https://lists.trustedfirmware.org/pipermail/tf-a/2020-July/000586.html Change-Id: Iee8de16f81dc970a8f492726f2ddd57e7bd9ffb5 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
| * el3_runtime: Rearrange context offset of EL1 sys registersManish V Badarkhe2020-08-181-6/+6
| | | | | | | | | | | | | | | | | | | | | | SCTLR and TCR registers of EL1 plays role in enabling/disabling of page table walk for lower ELs (EL0 and EL1). Hence re-arranged EL1 context offsets to have SCTLR and TCR registers values one after another in the stack so that these registers values can be saved and restored using stp and ldp instruction respectively. Change-Id: Iaa28fd9eba82a60932b6b6d85ec8857a9acd5f8b Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
| * el3_runtime: Update context save and restore routines for EL1 and EL2Manish V Badarkhe2020-08-181-132/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | As per latest mailing communication [1], we decided not to update SCTLR and TCR registers in EL1 and EL2 context restore routine when AT speculative workaround is enabled hence reverted the changes done as part of this commit: 45aecff00. [1]: https://lists.trustedfirmware.org/pipermail/tf-a/2020-July/000586.html Change-Id: I8c5f31d81fcd53770a610e302a5005d98772b71f Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
| * Merge "lib: cpus: denver: add some MIDR values" into integrationVarun Wadekar2020-08-141-0/+28
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| | * lib: cpus: denver: add some MIDR valuesAlex Van Brunt2020-08-081-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for additional Denver MIDRs to cover all the current SKUs. Change-Id: I85d0ffe9b3cb351f430ca7d7065a2609968a7a28 Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | Merge changes from topic "sp_dual_signing" into integrationSandrine Bailleux2020-08-141-1/+2
| |\ \ | | | | | | | | | | | | | | | | | | | | * changes: dualroot: add chain of trust for Platform owned SPs cert_create: add Platform owned secure partitions support
| | * | cert_create: add Platform owned secure partitions supportManish Pandey2020-08-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to generate a certificate named "plat-sp-cert" for Secure Partitions(SP) owned by Platform. Earlier a single certificate file "sip-sp-cert" was generated which contained hash of all 8 SPs, with this change SPs are divided into two categories viz "SiP owned" and "Plat owned" containing 4 SPs each. Platform RoT key pair is used for signing. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I5bd493cfce4cf3fc14b87c8ed1045f633d0c92b6
| * | | Merge "lib: cpus: denver: mark exception vectors as private" into integrationMark Dykes2020-08-131-2/+0
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| | * | lib: cpus: denver: mark exception vectors as privateVarun Wadekar2020-08-081-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the 'workaround_bpflush_runtime_exceptions' exception vector table base address from the globals list as it gets used only by the Denver CPU implementation. Change-Id: I6ef94989f6dc4535d464493cc8621d32795ee1f6 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | TF-A AMU: remove AMU enable info printOlivier Deprez2020-08-132-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following f3ccf036ecb1ae1628 the INFO print in amu_enable is causing a lot of print outs on UART1 in DEBUG mode especially on PSCI test cases because CPU_ON or SUSPEND operations call: cm_prepare_el3_exit => enable_extensions_nonsecure => amu_enable. PSCI SUSPEND is also very frequent in linux boot cases causing test timeout failures. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I63581f8fa489d44b3b1d10af3b7f6fdf3af44720
| * | | TF-A AMU extension: fix detection of group 1 counters.Alexei Fedorov2020-08-102-102/+245
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the bug when AMUv1 group1 counters was always assumed being implemented without checking for its presence which was causing exception otherwise. The AMU extension code was also modified as listed below: - Added detection of AMUv1 for ARMv8.6 - 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now calculated based on 'AMU_GROUP1_COUNTERS_MASK' value - Added bit fields definitions and access functions for AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers - Unification of amu.c Aarch64 and Aarch32 source files - Bug fixes and TF-A coding style compliant changes. Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
| * | Merge "MISRA cleanup in mem_region and semihosting files" into integrationMadhukar Pappireddy2020-08-092-52/+60
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| | * MISRA cleanup in mem_region and semihosting filesjohpow012020-08-072-52/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MISRA defect cleanup and general code cleanup in mem_region.c and semihosting.c. This task also called for cleanup of the ARM NOR flash driver but that was removed at some point since the Jira task was created. This patch fixes all MISRA defects in these files except for a few "Calling function "console_flush()" which returns error information without testing the error information." errors which can't really be avoided. Defects Fixed File Line Rule lib/semihosting/semihosting.c 70 MISRA C-2012 Rule 14.4 (required) lib/semihosting/semihosting.c 197 MISRA C-2012 Rule 14.3 (required) lib/semihosting/semihosting.c 210 MISRA C-2012 Rule 14.4 (required) lib/utils/mem_region.c 128 MISRA C-2012 Rule 12.1 (advisory) Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I21a039d1cfccd6aa4301da09daec15e373305a80
| * | Merge "Use abspath to dereference $BUILD_BASE" into integrationAlexei Fedorov2020-08-051-4/+4
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| | * | Use abspath to dereference $BUILD_BASEGrant Likely2020-08-041-4/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the user tries to change BUILD_BASE to put the build products outside the build tree the compile will fail due to hard coded assumptions that $BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE)) to rationalize to an absolute path every time and remove the relative path assumptions. This patch also adds documentation that BUILD_BASE can be specified by the user. Signed-off-by: Grant Likely <grant.likely@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
| * | Merge "TF-A Aarch32: optimise memcpy4()" into integrationManish Pandey2020-08-031-6/+5
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| | * | TF-A Aarch32: optimise memcpy4()Alexei Fedorov2020-07-231-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes optimisation of Aarch32 memcpy4() function. Change-Id: If9cdaa4a1224f88fb14df8a308a645344b6c4f1c Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
| * | | Aarch32 xlat_tables lib: Fix MISRA-2012 defectsAlexei Fedorov2020-07-291-89/+104
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes violation of Rules 2.1, 7.3, 10.1, 10.4, 12.1, 14.3, 14.4, 17.7, 20.9 reported by MISRA-2012 scan and adds braces for conditional statements according to the TF-A coding style. Change-Id: Ib2463601fb43d955c3d901102b6dceaaad6614f3 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
| * | Merge "Revert workaround for Neoverse N1 erratum 1800710" into integrationLauren Wehrmeister2020-07-232-43/+0
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| | * | Revert workaround for Neoverse N1 erratum 1800710johpow012020-07-232-43/+0
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 11af40b6308ac75c83e874129bb79bc3a58060bf, reversing changes made to 2afcf1d4b845272791b75c8285108c4dcd91e2b9. This errata workaround did not work as intended so we are reverting this change. In the future, when the corrected workaround is published in an SDEN, we will push a new workaround. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97
| * | lib/fconf: Update 'set_fw_config_info' functionManish V Badarkhe2020-07-231-39/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated the function 'set_fw_config_info' to make it generic by doing below changes: 1. Rename function name from 'set_fw_config_info' to 'set_config_info' 2. Take image_id as an argument so that this function can set any config information. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Icf29e19d3e9996d8154d84dbbbc76712fab0f0c1
| * | lib/fconf: Update data type of config max sizeManish V Badarkhe2020-07-232-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the data type of the member 'config_max_size' present in the structure 'dyn_cfg_dtb_info_t' to uint32_t. This change is being done so that dyn_cfg_dtb_info_t and image_info structure should use same data type for maximum size. Change-Id: I9b5927a47eb8351bbf3664b8b1e047ae1ae5a260 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
| * | TF-A: Add support for Measured Boot driver to FCONFAlexei Fedorov2020-07-212-15/+35
| |/ | | | | | | | | | | | | | | This patch adds support for Measured Boot driver functionality to FCONF library code. Change-Id: I81cdb06f1950f7e6e58f938a1b9c2f74f7cfdf88 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
| * Merge "Upgrade libfdt source files" into integrationSandrine Bailleux2020-07-0810-626/+759
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| | * Upgrade libfdt source filesMadhukar Pappireddy2020-06-2710-626/+759
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This version corresponds to the following commit <7be250b> libfdt: Correct condition for reordering blocks Also, updated the Juno romlib jumptable with fdt APIs. Change-Id: Ib6d28c1aea81c2144a263958f0792cc4daea7a1f Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | Merge "Workaround for Neoverse N1 erratum 1800710" into integrationLauren Wehrmeister2020-07-012-0/+43
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