aboutsummaryrefslogtreecommitdiffstats
path: root/lib
Commit message (Collapse)AuthorAgeFilesLines
* AMU: Implement support for aarch32Dimitris Papastamos2017-11-292-0/+36
| | | | | | | | | The `ENABLE_AMU` build option can be used to enable the architecturally defined AMU counters. At present, there is no support for the auxiliary counter group. Change-Id: Ifc7532ef836f83e629f2a146739ab61e75c4abc8 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* AMU: Implement support for aarch64Dimitris Papastamos2017-11-292-0/+45
| | | | | | | | | The `ENABLE_AMU` build option can be used to enable the architecturally defined AMU counters. At present, there is no support for the auxiliary counter group. Change-Id: I7ea0c0a00327f463199d1b0a481f01dadb09d312 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Implement support for the Activity Monitor Unit on Cortex A75Dimitris Papastamos2017-11-291-1/+28
| | | | | | | | | | | | The Cortex A75 has 5 AMU counters. The first three counters are fixed and the remaining two are programmable. A new build option is introduced, `ENABLE_AMU`. When set, the fixed counters will be enabled for use by lower ELs. The programmable counters are currently disabled. Change-Id: I4bd5208799bb9ed7d2596e8b0bfc87abbbe18740 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Merge pull request #1145 from etienne-lms/rfc-armv7-2davidcunado-arm2017-11-2312-0/+711
|\ | | | | Support ARMv7 architectures
| * ARMv7: division support for missing __aeabi_*divmodEtienne Carriere2017-11-082-0/+233
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv7-A architectures that do not support the Virtualization extensions do not support instructions for the 32bit division. This change provides a software implementation for 32bit division. The division implementation is dumped from the OP-TEE project http://github.com/OP-TEE/optee_os. The code was slightly modified to pass trusted firmware checkpatch requirements and copyright is given to the ARM trusted firmware initiative and its contributors. Change-Id: Idae0c7b80a0d75eac9bd41ae121921d4c5af3fa3 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7 may not support Generic Timer ExtensionEtienne Carriere2017-11-081-0/+2
| | | | | | | | | | | | | | | | If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform shall define ARMV7_SUPPORTS_GENERIC_TIMER to enable generic timer support. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7 may not support large page addressingEtienne Carriere2017-11-082-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | ARCH_SUPPORTS_LARGE_PAGE_ADDRESSING allows build environment to handle specific case when target ARMv7 core only supports 32bit MMU descriptor mode. If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform shall define ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING to enable large page addressing support. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A12Etienne Carriere2017-11-081-0/+75
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A17Etienne Carriere2017-11-081-0/+75
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A7Etienne Carriere2017-11-081-0/+75
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A5Etienne Carriere2017-11-081-0/+75
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A9Etienne Carriere2017-11-081-0/+75
| | | | | | | | | | | | | | | | | | As Cortex-A9 needs to manually enable program flow prediction, do not reset SCTLR[Z] at entry. Platform should enable it only once MMU is enabled. Change-Id: I34e1ee2da73221903f7767f23bc6fc10ad01e3de Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A15Etienne Carriere2017-11-081-0/+81
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7 does not support STL instructionEtienne Carriere2017-11-081-0/+12
| | | | | | | | | | | | | | Also need to add a SEV instruction in ARMv7 spin_unlock which is implicit in ARMv8. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* | Merge pull request #1164 from robertovargas-arm/psci-affinitydavidcunado-arm2017-11-231-0/+17
|\ \ | | | | | | Flush the affinity data in psci_affinity_info
| * | Flush the affinity data in psci_affinity_infoRoberto Vargas2017-11-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is an edge case where the cache maintaince done in psci_do_cpu_off may not seen by some cores. This case is handled in psci_cpu_on_start but it hasn't handled in psci_affinity_info. Change-Id: I4d64f3d1ca9528e364aea8d04e2d254f201e1702 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | Merge pull request #1163 from antonio-nino-diaz-arm/an/parangedavidcunado-arm2017-11-232-2/+8
|\ \ \ | | | | | | | | Add ARMv8.2 ID_AA64MMFR0_EL1.PARange value
| * | | Add ARMv8.2 ID_AA64MMFR0_EL1.PARange valueAntonio Nino Diaz2017-11-172-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an implementation of ARMv8.2 includes ARMv8.2-LPA, the value 0b0110 is permitted in ID_AA64MMFR0_EL1.PARange, which means that the Physical Address range supported is 52 bits (4 PiB). It is a reserved value otherwise. Change-Id: Ie0147218e9650aa09f0034a9ee03c1cca8db908a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | Refactor Statistical Profiling Extensions implementationDimitris Papastamos2017-11-203-55/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out SPE operations in a separate file. Use the publish subscribe framework to drain the SPE buffers before entering secure world. Additionally, enable SPE before entering normal world. A side effect of this change is that the profiling buffers are now only drained when a transition from normal world to secure world happens. Previously they were drained also on return from secure world, which is unnecessary as SPE is not supported in S-EL1. Change-Id: I17582c689b4b525770dbb6db098b3a0b5777b70a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | | | Factor out extension enabling to a separate functionDimitris Papastamos2017-11-202-0/+30
| |/ / |/| | | | | | | | | | | | | | | | | | | | Factor out extension enabling to a separate function that is called before exiting from EL3 for first entry into Non-secure world. Change-Id: Ic21401ebba531134d08643c0a1ca9de0fc590a1b Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | | Move FPEXC32_EL2 to FP ContextDavid Cunado2017-11-151-6/+8
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FPEXC32_EL2 register controls SIMD and FP functionality when the lower ELs are executing in AArch32 mode. It is architecturally mapped to AArch32 system register FPEXC. This patch removes FPEXC32_EL2 register from the System Register context and adds it to the floating-point context. EL3 only saves / restores the floating-point context if the build option CTX_INCLUDE_FPREGS is set to 1. The rationale for this change is that if the Secure world is using FP functionality and EL3 is not managing the FP context, then the Secure world will save / restore the appropriate FP registers. NOTE - this is a break in behaviour in the unlikely case that CTX_INCLUDE_FPREGS is set to 0 and the platform contains an AArch32 Secure Payload that modifies FPEXC, but does not save and restore this register Change-Id: Iab80abcbfe302752d52b323b4abcc334b585c184 Signed-off-by: David Cunado <david.cunado@arm.com>
* | Merge pull request #1148 from antonio-nino-diaz-arm/an/spmdavidcunado-arm2017-11-091-3/+2
|\ \ | | | | | | Introduce Secure Partition Manager
| * | xlat: Make function to calculate TCR PA bits publicAntonio Nino Diaz2017-11-081-3/+2
| |/ | | | | | | | | | | | | | | | | | | This function can be useful to setup TCR_ELx by callers that don't use the translation tables library to setup the system registers related to them. By making it common, it can be reused whenever it is needed without duplicating code. Change-Id: Ibfada9e846d2a6cd113b1925ac911bb27327d375 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* / Fix PSCI STAT time stamp collectionSoby Mathew2017-11-032-11/+7
|/ | | | | | | | | | | | | | | | | | | | | This patch includes various fixes for PSCI STAT functionality relating to timestamp collection: 1. The PSCI stat accounting for retention states for higher level power domains were done outside the locks which could lead to spurious values in some race conditions. This is moved inside the locks. Also, the call to start the stat accounting was redundant which is now removed. 2. The timestamp wrap-around case when calculating residency did not cater for AArch32. This is now fixed. 3. In the warm boot path, `plat_psci_stat_accounting_stop()` was getting invoked prior to population of target power states. This is now corrected. Change-Id: I851526455304fb74ff0a724f4d5318cd89e19589 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* aarch64: Add PubSub events to capture security state transitionsDimitris Papastamos2017-10-311-3/+17
| | | | | | | | | | | Add events that trigger before entry to normal/secure world. The events trigger after the normal/secure context has been restored. Similarly add events that trigger after leaving normal/secure world. The events trigger after the normal/secure context has been saved. Change-Id: I1b48a7ea005d56b1f25e2b5313d77e67d2f02bc5 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* PSCI: Publish CPU ON eventJeenu Viswambharan2017-10-231-0/+3
| | | | | | | | | | This allows other EL3 components to subscribe to CPU on events. Update Firmware Design guide to list psci_cpu_on_finish as an available event. Change-Id: Ida774afe0f9cdce4021933fcc33a9527ba7aaae2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Merge pull request #1136 from antonio-nino-diaz-arm/an/xlat-get-set-attrdavidcunado-arm2017-10-203-8/+373
|\ | | | | Add APIs to get and modify attributes of memory regions
| * Introduce functions to disable the MMU in EL1Antonio Nino Diaz2017-10-171-3/+27
| | | | | | | | | | | | | | The implementation is the same as those used to disable it in EL3. Change-Id: Ibfe7e69034a691fbf57477c5a76a8cdca28f6b26 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * xlat: Introduce API to change memory attributes of a regionSandrine Bailleux2017-10-172-4/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new API in the translation tables library (v2), that allows to change the memory attributes of a memory region. It may be used to change its execution permissions and data access permissions. As a prerequisite, the memory must be already mapped. Moreover, it must be mapped at the finest granularity (currently 4 KB). Change-Id: I242a8c6f0f3ef2b0a81a61e28706540462faca3c Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * xlat: Introduce API to get memory attributes of a regionSandrine Bailleux2017-10-171-1/+193
| | | | | | | | | | | | | | | | | | | | | | This patch introduces a new API in the translation tables library (v2), that allows to query the memory attributes of a memory block or a memory page. Change-Id: I45a8b39a53da39e7617cbac4bff5658dc1b20a11 Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1127 from davidcunado-arm/dc/pmrc_initdavidcunado-arm2017-10-172-2/+32
|\ \ | | | | | | Init and save / restore of PMCR_EL0 / PMCR
| * | Init and save / restore of PMCR_EL0 / PMCRDavid Cunado2017-10-132-2/+32
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently TF does not initialise the PMCR_EL0 register in the secure context or save/restore the register. In particular, the DP field may not be set to one to prohibit cycle counting in the secure state, even though event counting generally is prohibited via the default setting of MDCR_EL3.SMPE to 0. This patch initialises PMCR_EL0.DP to one in the secure state to prohibit cycle counting and also initialises other fields that have an architectually UNKNOWN reset value. Additionally, PMCR_EL0 is added to the list of registers that are saved and restored during a world switch. Similar changes are made for PMCR for the AArch32 execution state. NOTE: secure world code at lower ELs that assume other values in PMCR_EL0 will be impacted. Change-Id: Iae40e8c0a196d74053accf97063ebc257b4d2f3a Signed-off-by: David Cunado <david.cunado@arm.com>
* | Merge pull request #1126 from robertovargas-arm/psci-v1.1davidcunado-arm2017-10-171-1/+2
|\ \ | | | | | | Update PSCI to v1.1
| * | mem_protect: Fix PSCI FEATURES API for MEM_PROTECT_CHECKRoberto Vargas2017-10-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | With this patch the PSCI_FEATURES API correctly reports availability of the PSCI_MEM_PROTECT_CHECK API - PSCI_MEM_CHK_RANGE_AARCH64 is added to the PSCI capabilities mask, PSCI_CAP_64BIT_MASK Change-Id: Ic90ee804deaadf0f948dc2d46ac5fe4121ef77ae Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | Merge pull request #1123 from robertovargas-arm/reset2davidcunado-arm2017-10-164-1/+42
|\| | | |/ |/| Integration of reset2 PSCI v1.1 functionality
| * reset2: Add PSCI system_reset2 functionRoberto Vargas2017-10-134-1/+42
| | | | | | | | | | | | | | | | | | | | | | | | This patch implements PSCI_SYSTEM_RESET2 API as defined in PSCI v1.1 specification. The specification allows architectural and vendor-specific resets via this API. In the current specification, there is only one architectural reset, the warm reset. This reset is intended to provide a fast reboot path that guarantees not to reset system main memory. Change-Id: I057bb81a60cd0fe56465dbb5791d8e1cca025bd3 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | Merge pull request #1117 from antonio-nino-diaz-arm/an/xlat-improvementsdavidcunado-arm2017-10-097-90/+231
|\ \ | |/ |/| Improvements to the translation tables library v2
| * xlat: Add support for EL0 and EL1 mappingsAntonio Nino Diaz2017-10-057-71/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the ability of the xlat tables library to manage EL0 and EL1 mappings from a higher exception level. Attributes MT_USER and MT_PRIVILEGED have been added to allow the user specify the target EL in the translation regime EL1&0. REGISTER_XLAT_CONTEXT2 macro is introduced to allow creating a xlat_ctx_t that targets a given translation regime (EL1&0 or EL3). A new member is added to xlat_ctx_t to represent the translation regime the xlat_ctx_t manages. The execute_never mask member is removed as it is computed from existing information. Change-Id: I95e14abc3371d7a6d6a358cc54c688aa9975c110 Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * xlat: Introduce function xlat_arch_tlbi_va_regime()Douglas Raillard2017-10-053-10/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a variant of the TLB invalidation helper function that allows the targeted translation regime to be specified, rather than defaulting to the current one. This new function is useful in the context of EL3 software managing translation tables for the S-EL1&0 translation regime, as then it might need to invalidate S-EL1&0 TLB entries rather than EL3 ones. Define a new enumeration to be able to represent translation regimes in the xlat tables library. Change-Id: Ibe4438dbea2d7a6e7470bfb68ff805d8bf6b07e5 Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * xlat: Always compile TLB invalidation functionsSandrine Bailleux2017-10-052-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TLB invalidation functions used to be conditionally compiled in. They were enabled only when using the dynamic mapping feature. because only then would we need to modify page tables on the fly. Actually there are other use cases where invalidating TLBs is required. When changing memory attributes in existing translation descriptors for example. These other use cases do not necessarily depend on the dynamic mapping feature. This patch removes this dependency and always compile TLB invalidation functions in. If they're not used, they will be removed from the binary at link-time anyway so there's no consequence on the memory footprint if these functions are not called. Change-Id: I1c33764ae900eb00073ee23b7d0d53d4efa4dd21 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
| * xlat: Introduce MAP_REGION2() macroSandrine Bailleux2017-10-051-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of the memory mapping API favours mapping memory regions using the biggest possible block size in order to reduce the number of translation tables needed. In some cases, this behaviour might not be desirable. When translation tables are edited at run-time, coarse-grain mappings like that might need splitting into finer-grain tables. This operation has a performance cost. The MAP_REGION2() macro allows to specify the granularity of translation tables used for the initial mapping of a memory region. This might increase performance for memory regions that are likely to be edited in the future, at the expense of a potentially increased memory footprint. The Translation Tables Library Design Guide has been updated to explain the use case for this macro. Also added a few intermediate titles to make the guide easier to digest. Change-Id: I04de9302e0ee3d326b8877043a9f638766b81b7b Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1109 from robertovargas-arm/mem_protectdavidcunado-arm2017-10-046-0/+135
|\ \ | |/ |/| Mem protect
| * Add mem_region utility functionsRoberto Vargas2017-09-251-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces a new type (mem_region_t) used to describe memory regions and it adds two utility functions: - clear_mem_regions: This function clears (write 0) to a set of regions described with an array of mem_region_t. - mem_region_in_array_chk This function checks if a region is covered by some of the regions described with an array of mem_region_t. Change-Id: I12ce549f5e81dd15ac0981645f6e08ee7c120811 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
| * mem_protect: Add mem_protect APIRoberto Vargas2017-09-255-0/+57
| | | | | | | | | | | | | | | | | | | | This patch adds the generic code that links the psci smc handler with the platform function that implements the mem_protect and mem_check_range functionalities. These functions are optional APIs added in PSCI v1.1 (ARM DEN022D). Change-Id: I3bac1307a5ce2c7a196ace76db8317e8d8c8bb3f Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | Set TCR_EL1.EPD1 bit to 1Antonio Nino Diaz2017-09-212-2/+10
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | In the S-EL1&0 translation regime we aren't using the higher VA range, whose translation table base address is held in TTBR1_EL1. The bit TCR_EL1.EPD1 can be used to disable translations using TTBR1_EL1, but the code wasn't setting it to 1. Additionally, other fields in TCR1_EL1 associated with the higher VA range (TBI1, TG1, SH1, ORGN1, IRGN1 and A1) weren't set correctly as they were left as 0. In particular, 0 is a reserved value for TG1. Also, TBBR1_EL1 was not explicitly set and its reset value is UNKNOWN. Therefore memory accesses to the higher VA range would result in unpredictable behaviour as a translation table walk would be attempted using an UNKNOWN value in TTBR1_EL1. On the FVP and Juno platforms accessing the higher VA range resulted in a translation fault, but this may not always be the case on all platforms. This patch sets the bit TCR_EL1.EPD1 to 1 so that any kind of unpredictable behaviour is prevented. This bug only affects the AArch64 version of the code, the AArch32 version sets this bit to 1 as expected. Change-Id: I481c000deda5bc33a475631301767b9e0474a303 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* xlat: simplify mmap_add_region_check parameters (#1101)Douglas Raillard2017-09-211-30/+51
| | | | | | | | | | | Use a mmap_region_t as parameter instead of getting a parameter for each structure member. This reduces the scope of changes when adding members to mmap_region_t. Also align on the convention of using mm_cursor as a variable name for the currently inspected region when iterating on the region array. Change-Id: If40bc4351b56c64b214e60dda27276d11ce9dbb3 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
* Merge pull request #1099 from douglas-raillard-arm/dr/fix_mm_copydavidcunado-arm2017-09-191-8/+3
|\ | | | | xlat: fix mm copy when adding a region
| * xlat: fix mm copy when adding a regionDouglas Raillard2017-09-141-8/+3
| | | | | | | | | | | | | | | | | | mmap_add_region_ctx and mmap_add_dynamic_region_ctx are clearing members that they are not aware of by copying each member one by one. Replace this by structure assignment. Change-Id: I7c70cb408c8a8eb551402a5d8d956c1fb7f32b55 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
* | Merge pull request #1094 from ↵davidcunado-arm2017-09-151-12/+2
|\ \ | |/ |/| | | | | douglas-raillard-arm/dr/fix_mmap_add_dynamic_region xlat: Use MAP_REGION macro as compatibility layer
| * xlat: Use MAP_REGION macro as compatibility layerDouglas Raillard2017-09-111-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the MAP_REGION to build the mmap_region_t argument in wrappers like mmap_add_region(). Evolution of the mmap_region_t might require adding new members with a non-zero default value. Users of MAP_REGION are protected against such evolution. This commit also protects users of mmap_add_region() and mmap_add_dynamic_region() functions against these evolutions. Also make the MAP_REGION macro implementation more explicit and make it a mmap_region_t compound literal to make it useable as a function parameter on its own and to prevent using it in initialization of variables of different type. Change-Id: I7bfc4689f6dd4dd23c895b65f628d8ee991fc161 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-14 21:04:07 +0000