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* compiler_rt: Import lshrdi3.c fileSandrine Bailleux2018-11-062-1/+47
| | | | | | | | | | | Imported from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). This is to get the __aeabi_llsr() builtin, which is required by a subsequent patch that uses a logical right shift operator in AArch32. Change-Id: I9884139a12855a8a87206fb572aaa7dd35582b09 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* compiler_rt: Import latest changes on int_lib.hSandrine Bailleux2018-11-061-6/+7
| | | | | | | | Imported from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). Change-Id: I058cfb5894daf1d12e1ef971c0ba36b0aa089be5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* libc: Adapt strlcpy to this codebaseAntonio Nino Diaz2018-11-022-5/+5
| | | | | Change-Id: I2f5f64aaf90caae936510e1179392a8835f493e0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* libc: Import strlcpy from FreeBSDAntonio Nino Diaz2018-11-021-0/+53
| | | | | | | | | From commit aafd1cf4235d78ce85b76d7da63e9589039344b3: - lib/libc/strlcpy.c Change-Id: Iaa7028fcc26706bdd6ee3f1e4bd55dd5873a30c6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* bakery: Fix MISRA defectsAntonio Nino Diaz2018-11-012-39/+50
| | | | | Change-Id: I600bc13522ae977db355b6dc5a1695bce39ec130 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* context_mgmt: Fix MISRA defectsAntonio Nino Diaz2018-11-012-34/+34
| | | | | | | | The macro EL_IMPLEMENTED() has been deprecated in favour of the new function el_implemented(). Change-Id: Ic9b1b81480b5e019b50a050e8c1a199991bf0ca9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1657 from antonio-nino-diaz-arm/an/libfdtAntonio Niño Díaz2018-11-017-373/+90
|\ | | | | libfdt: Downgrade to version 1.4.6-9
| * libfdt: Downgrade to version 1.4.6-9Antonio Nino Diaz2018-10-307-373/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Version 1.4.7 introduces a big performance hit to functions that access the FDT. Downgrade the library to version 1.4.6-9, before the changes that introduce the problem. Version 1.4.6 isn't used because one of the libfdt files (fdt_overlay.c) is missing the license header. This problem is also fixed in 1.4.6-9. This version corresponds to commit <aadd0b65c987> checks: centralize printing of property names in failure messages. Fixes ARM-software/tf-issues#643 Change-Id: I73c05f2b1f994bcdcc4366131ce0647553cdcfb8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Fix MISRA defects in PMFAntonio Nino Diaz2018-10-292-9/+11
| | | | | | | | | | | | | | No functional changes. Change-Id: I64abd72026082218a40b1a4b8f7dc26ff2478ba6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Fix MISRA defects in workaround and errata frameworkAntonio Nino Diaz2018-10-293-9/+14
| | | | | | | | | | | | | | No functional changes. Change-Id: Iaab0310848be587b635ce5339726e92a50f534e0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Fix MISRA defects in extension libsAntonio Nino Diaz2018-10-298-74/+84
|/ | | | | | | No functional changes. Change-Id: I2f28f20944f552447ac4e9e755493cd7c0ea1192 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* PIE: Position Independant Executable support for BL31Soby Mathew2018-10-292-3/+118
| | | | | | | | | | | | | | | | | | | | | This patch introduces Position Independant Executable(PIE) support in TF-A. As a initial prototype, only BL31 can support PIE. A trivial dynamic linker is implemented which supports fixing up Global Offset Table(GOT) and Dynamic relocations(.rela.dyn). The fixup_gdt_reloc() helper function implements this linker and this needs to be called early in the boot sequence prior to invoking C functions. The GOT is placed in the RO section of BL31 binary for improved security and the BL31 linker script is modified to export the appropriate symbols required for the dynamic linker. The C compiler always generates PC relative addresses to linker symbols and hence referencing symbols exporting constants are a problem when relocating the binary. Hence the reference to the `__PERCPU_TIMESTAMP_SIZE__` symbol in PMF is removed and is now calculated at runtime based on start and end addresses. Change-Id: I1228583ff92cf432963b7cef052e95d995cca93d Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* Make errata reporting mandatory for CPU filesSoby Mathew2018-10-299-0/+84
| | | | | | | | | | | | | Previously the errata reporting was optional for CPU operation files and this was achieved by making use of weak reference to resolve to 0 if the symbol is not defined. This is error prone when adding new CPU operation files and weak references are problematic when fixing up dynamic relocations. Hence this patch removes the weak reference and makes it mandatory for the CPU operation files to define the errata reporting function. Change-Id: I8af192e19b85b7cd8c7579e52f8f05a4294e5396 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* PIE: Use PC relative adrp/adr for symbol referenceSoby Mathew2018-10-292-6/+13
| | | | | | | | | | | | | | | | | | | This patch fixes up the AArch64 assembly code to use adrp/adr instructions instead of ldr instruction for reference to symbols. This allows these assembly sequences to be Position Independant. Note that the the reference to sizes have been replaced with calculation of size at runtime. This is because size is a constant value and does not depend on execution address and using PC relative instructions for loading them makes them relative to execution address. Also we cannot use `ldr` instruction to load size as it generates a dynamic relocation entry which must *not* be fixed up and it is difficult for a dynamic loader to differentiate which entries need to be skipped. Change-Id: I8bf4ed5c58a9703629e5498a27624500ef40a836 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* xlat: Fix compatibility between v1 and v2Antonio Nino Diaz2018-10-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | There are several platforms using arm_setup_page_tables(), which is supposed to be Arm platform only. This creates several dependency problems between platforms. This patch adds the definition XLAT_TABLES_LIB_V2 to the xlat tables lib v2 makefile. This way it is possible to detect from C code which version is being used and include the correct header. The file arm_xlat_tables.h has been renamed to xlat_tables_compat.h and moved to a common folder. This way, when in doubt, this header can be used to guarantee compatibility, as it includes the correct header based on XLAT_TABLES_LIB_V2. This patch also removes the usage of ARM_XLAT_TABLES_V1 from QEMU (so that is now locked in xlat lib v2) and ZynqMP (where it was added as a workaround). Change-Id: Ie1e22a23b44c549603d1402a237a70d0120d3e04 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1643 from antonio-nino-diaz-arm/an/libfdtAntonio Niño Díaz2018-10-2412-204/+1554
|\ | | | | Update libfdt to version 1.4.7
| * libfdt: Import version v1.4.7Antonio Nino Diaz2018-10-2310-0/+3542
| | | | | | | | | | Change-Id: Iad7adaf0b16a3d086594cb3432210ac2c4e207f8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * libfdt: Remove current versionAntonio Nino Diaz2018-10-239-2242/+0
| | | | | | | | | | | | | | | | | | The current version of libfdt (1.4.2) has been modified to integrate it in this repository. In order to do a clean import it is needed to remove the current version first. Change-Id: I2cab8c8e5632280d282fa7a2f2339768a0ad1e0f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * libc: Integrate strrchr in libcAntonio Nino Diaz2018-10-232-9/+2
| | | | | | | | | | Change-Id: I3ddc07cb02d73cd7614af7a5b21827aae155f9a0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * libc: Import strrchr from FreeBSDAntonio Nino Diaz2018-10-231-0/+57
| | | | | | | | | | | | | | | | | | Imported from lib/libc/string/strrchr.c from commit: 59fd2fb98e4cc7e9bfc89598e28e21d405fd470c Change-Id: I898206c6f0372d4d211c149ec0fb9522d0a5b01c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1641 from jeenu-arm/ptrauthAntonio Niño Díaz2018-10-241-6/+14
|\ \ | |/ |/| AArch64: Enable lower ELs to use pointer authentication
| * AArch64: Enable lower ELs to use pointer authenticationJeenu Viswambharan2018-10-161-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pointer authentication is an Armv8.3 feature that introduces instructions that can be used to authenticate and verify pointers. Pointer authentication instructions are allowed to be accessed from all ELs but only when EL3 explicitly allows for it; otherwise, their usage will trap to EL3. Since EL3 doesn't have trap handling in place, this patch unconditionally disables all related traps to EL3 to avoid potential misconfiguration leading to an unhandled EL3 exception. Fixes ARM-software/tf-issues#629 Change-Id: I9bd2efe0dc714196f503713b721ffbf05672c14d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | ti: k3: common: Do not disable cache on TI K3 core powerdownAndrew F. Davis2018-10-161-0/+4
|/ | | | | | | | | Leave the caches on and explicitly flush any data that may be stale when the core is powered down. This prevents non-coherent interconnect access which has negative side- effects on AM65x. Signed-off-by: Andrew F. Davis <afd@ti.com>
* Merge pull request #1624 from glneo/less-cache-flushingSoby Mathew2018-10-121-11/+8
|\ | | | | PSCI cache flush and comment fixup
| * PSCI: Do not flush cache when unneededAndrew F. Davis2018-10-101-2/+2
| | | | | | | | | | | | | | | | When a platform enables its caches before it accesses the psci_non_cpu_pd_nodes structure then explicit cache maintenance is not needed. Signed-off-by: Andrew F. Davis <afd@ti.com>
| * PSCI: Update comment on MMU disablementAndrew F. Davis2018-10-101-9/+6
| | | | | | | | | | | | | | | | The MMU is not disabled in this path, update the comment to reflect this. Also clarify that both paths call prepare_cpu_pwr_dwn(), but the second path does stack cache maintenance. Signed-off-by: Andrew F. Davis <afd@ti.com>
* | psci: platform control of SYSTEM_SUSPEND entryldts2018-10-111-1/+7
|/ | | | | | | | Some platforms can only resume from system suspend from the boot CPU, hence they should only enter that state from that same core. The following commit presents an interface that allows the platform to reject system suspend entry near its very last stage (last CPU).
* xlat: Fix checks in mmap_add() and mmap_add_ctx()Antonio Nino Diaz2018-10-082-2/+2
| | | | | | | | | | | | | | | | | Commit 79621f0038b789de23ecc8891024f7cf6aa65999 broke sgi575. It is possible to have a region with 0 as value for the attributes. It means device memory, read only, secure, executable. This is legitimate if the code is in flash and the code is executed from there. This is the case for SGI_MAP_FLASH0_RO, defined in the file plat/arm/css/sgi/sgi_plat.c. This problem is solved by checking both size and attributes in xlat v1. In xlat v2, it is enough to check the granularity, as it can never be 0. Change-Id: I7be11f1b0e51c4c2ffd560b4a6cdfbf15de2c276 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1603 from antonio-nino-diaz-arm/db/reclaim-initSoby Mathew2018-10-047-11/+11
|\ | | | | Reclaim BL31 initialization code memory for runtime data
| * Mark xlat tables initialization codeDaniel Boulby2018-10-032-2/+2
| | | | | | | | | | | | | | | | Mark the xlat tables code only used in BL31 initialization as __init to be reclaimed once no longer needed Change-Id: I3106bfd994706a57c578624573bcfa525fbbd3c4 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
| * Mark BL31 initialization functionsDaniel Boulby2018-10-034-7/+7
| | | | | | | | | | | | | | | | | | Mark the initialization functions in BL31, such as context management, EHF, RAS and PSCI as __init so that they can be reclaimed by the platform when no longer needed Change-Id: I7446aeee3dde8950b0f410cb766b7a2312c20130 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
| * xlat: Change check in mmap_add and mmap_add_ctx()Daniel Boulby2018-10-032-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Depending on the build flags it is possible that some of the memory regions mapped in page table setup could have a size of 0. In this case we simply want to do nothing but still wish to map the other regions in the array. Therefore we cannot only use size == 0 as the termination logic for the loop. Since an attributes field with value 0 means that the region is device memory, read only, secure and executable. Device memory can't be executable, so this combination should never be used and it is safe to use as a terminator value. Therefore by changing the termination logic to use attributes instead of size we prevent terminating the loop when we don't intend to. Change-Id: I92fc7f689ab08543497be6be4896dace2ed7b66a Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | Merge pull request #1584 from danielboulby-arm/db/SwitchesSoby Mathew2018-10-032-0/+3
|\ \ | |/ |/| Ensure the flow through switch statements is clear
| * Ensure the flow through switch statements is clearDaniel Boulby2018-09-212-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure case clauses: * Terminate with an unconditional break, return or goto statement. * Use conditional break, return or goto statements as long as the end of the case clause is unreachable; such case clauses must terminate with assert(0) /* Unreachable */ or an unconditional __dead2 function call * Only fallthough when doing otherwise would result in less readable/maintainable code; such case clauses must terminate with a /* Fallthrough */ comment to make it clear this is the case and indicate that a fallthrough is intended. This reduces the chance of bugs appearing due to unintended flow through a switch statement Change-Id: I70fc2d1f4fd679042397dec12fd1982976646168 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | Remove all other deprecated interfaces and filesAntonio Nino Diaz2018-09-283-28/+0
| | | | | | | | | | Change-Id: Icd1cdd42afdc78895a9be6c46b414b0a155cfa63 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | xlat: Remove deprecated interfacesAntonio Nino Diaz2018-09-284-77/+0
| | | | | | | | | | Change-Id: I83de2ae3e0795e6fec3c1e5b37c441b64b0c9cb6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | PSCI: Remove deprecated file plat_psci_common.cAntonio Nino Diaz2018-09-281-3/+0
| | | | | | | | | | Change-Id: I9fd8016527ad7706494f34356fdae8efacef5f72 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | PSCI: Remove platform compatibility layerRoberto Vargas2018-09-281-78/+0
|/ | | | | | Change-Id: I40d040aa05bcbf11536a96ce59827711456b93a8 Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1568 from soby-mathew/sm/fix_ares_err_reportSoby Mathew2018-09-101-2/+2
|\ | | | | Fix the Cortex-ares errata reporting function name
| * Fix the Cortex-ares errata reporting function nameSoby Mathew2018-09-101-2/+2
| | | | | | | | | | | | | | | | This patch fixes the name of the Cortex-ares errata function which was previously named `cortex_a72_errata_report` which was an error. Change-Id: Ia124df4628261021baa8d9a30308bc286d45712b Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | RAS: Fix assert conditionJeenu Viswambharan2018-09-071-1/+1
|/ | | | | Change-Id: Ia02a2dbfd4e25547776e78bed40a91f3452553d7 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Add missing barriers to Bakery LocksJeenu Viswambharan2018-09-052-5/+23
| | | | | | | | | | | | With the current implementation, it's possible for a contender to observe accesses in the Critical Section before acquiring or releasing the lock. Insert fencing in the locking and release codes to prevent any reorder. Fixes ARM-software/tf-issues#609 Change-Id: I773b82aa41dd544a2d3dbacb9a4b42c9eb767bbb Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* cpus: denver: Implement static workaround for CVE-2018-3639Varun Wadekar2018-09-041-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Denver CPUs, this approach enables the mitigation during EL3 initialization, following every PE reset. No mechanism is provided to disable the mitigation at runtime. This approach permanently mitigates the EL3 software stack only. Other software components are responsible to enable it for their exception levels. TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN3 and earlier: * By setting bit 11 (Disable speculative store buffering) of `ACTLR_EL3` * By setting bit 9 (Disable speculative memory disambiguation) of `ACTLR_EL3` TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN4 and later: * By setting bit 18 (Disable speculative store buffering) of `ACTLR_EL3` * By setting bit 17 (Disable speculative memory disambiguation) of `ACTLR_EL3` Change-Id: If1de96605ce3f7b0aff5fab2c828e5aecb687555 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* cpus: denver: reset power state to 'C1' on bootVarun Wadekar2018-09-041-0/+9
| | | | | | | | | Denver CPUs expect the power state field to be reset to 'C1' during boot. This patch updates the reset handler to reset the ACTLR_.PMSTATE field to 'C1' state during CPU boot. Change-Id: I7cb629627a4dd1a30ec5cbb3a5e90055244fe30c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* denver: use plat_my_core_pos() to get core positionVarun Wadekar2018-09-041-4/+7
| | | | | | | | | | | | | | | The current functions to disable and enable Dynamic Code Optimizer (DCO) assume that all denver cores are in the same cluster. They ignore AFF1 field of the mpidr_el1 register, which leads to incorect logical core id calculation. This patch calls the platform handler, plat_my_core_pos(), to get the logical core id to disable/enable DCO for the core. Original change by: Krishna Sitaraman <ksitaraman@nvidia.com> Change-Id: I45fbd1f1eb032cc1db677a4fdecc554548b4a830 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* Merge pull request #1484 from nathan-menhorn/tee-validate-header-603Soby Mathew2018-09-031-8/+15
|\ | | | | Update optee_utils.c to fix ARM-software/tf-issues#603
| * Fixed ARM-software/tf-issues#603nathan-menhorn2018-08-231-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated optee_utils.c to fix ARM-software/tf-issues#603 related to the tee-validate-header bug. Minor updates to the header valid checking logic. It would never make sense to have less than 1 image to load so this is now checked. Changed OPTEE_MAX_IMAGE_NUM to OPTEE_MAX_NUM_IMAGES to clarify its definition. OPTEE_MAX_IMAGE_NUM sounds like an ID assigned to the last image to load. OPTEE_MAX_NUM_IMAGES sounds like the maximum number of images to load. Signed-off-by: Nathan Menhorn <nathan.menhorn@xilinx.com>
* | libc: Fix some MISRA defectsAntonio Nino Diaz2018-08-304-54/+74
| | | | | | | | | | | | | | No functional changes. Change-Id: I907aa47565af2a6c435a5560041fd2b59e65c25c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1544 from jwerner-chromium/JW_handle_eaDimitris Papastamos2018-08-301-1/+1
|\ \ | | | | | | context_mgmt: Fix HANDLE_EA_EL3_FIRST implementation
| * | context_mgmt: Fix HANDLE_EA_EL3_FIRST implementationJulius Werner2018-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug in the context management code that causes it to ignore the HANDLE_EA_EL3_FIRST compile-time option and instead always configure SCR_EL3 to force all external aborts to trap into EL3. The code used #ifdef to read compile-time option declared with add_define in the Makefile... however, those options are always defined, they're just defined to either 0 or 1, so #if is the correct syntax to check for them. Also update the documentation to match. This bug has existed since the Nov 2017 commit 76454abf4 (AArch64: Introduce External Abort handling), which changed the HANDLE_EA_EL3_FIRST option to use add_define. Change-Id: I7189f41d0daee78fa2fcf4066323e663e1e04d3d Signed-off-by: Julius Werner <jwerner@chromium.org>
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