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* Merge changes from topic "db/unsigned_long" into integrationSandrine Bailleux2019-09-181-1/+1
|\ | | | | | | | | | | * changes: Unsigned long should not be used as per coding guidelines SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64
| * SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64Deepika Bhavnani2019-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | AArch64 System register SCTLR_EL1[31:0] is architecturally mapped to AArch32 System register SCTLR[31:0] AArch64 System register ACTLR_EL1[31:0] is architecturally mapped to AArch32 System register ACTLR[31:0]. `u_register_t` should be used when it's important to store the contents of a register in its native size Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I0055422f8cc0454405e011f53c1c4ddcaceb5779
* | Merge "Refactor ARMv8.3 Pointer Authentication support code" into integrationSoby Mathew2019-09-134-257/+321
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| * Refactor ARMv8.3 Pointer Authentication support codeAlexei Fedorov2019-09-134-257/+321
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides the following features and makes modifications listed below: - Individual APIAKey key generation for each CPU. - New key generation on every BL31 warm boot and TSP CPU On event. - Per-CPU storage of APIAKey added in percpu_data[] of cpu_data structure. - `plat_init_apiakey()` function replaced with `plat_init_apkey()` which returns 128-bit value and uses Generic timer physical counter value to increase the randomness of the generated key. The new function can be used for generation of all ARMv8.3-PAuth keys - ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`. - New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively; pauth_disable_el1()` and `pauth_disable_el3()` functions disable PAuth for EL1 and EL3 respectively; `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from cpu-data structure. - Combined `save_gp_pauth_registers()` function replaces calls to `save_gp_registers()` and `pauth_context_save()`; `restore_gp_pauth_registers()` replaces `pauth_context_restore()` and `restore_gp_registers()` calls. - `restore_gp_registers_eret()` function removed with corresponding code placed in `el3_exit()`. - Fixed the issue when `pauth_t pauth_ctx` structure allocated space for 12 uint64_t PAuth registers instead of 10 by removal of macro CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h` and assigning its value to CTX_PAUTH_REGS_END. - Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions in `msr spsel` instruction instead of hard-coded values. - Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI. Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Merge "Assert if power level value greater then PSCI_INVALID_PWR_LVL" into ↵Soby Mathew2019-09-131-0/+1
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| * | Assert if power level value greater then PSCI_INVALID_PWR_LVLDeepika Bhavnani2019-09-091-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I4a496d5a8e7a9a127cd6224c968539eb74932fca
* | | Merge "Unify type of "cpu_idx" across PSCI module." into integrationSoby Mathew2019-09-132-17/+19
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| * | Unify type of "cpu_idx" across PSCI module.Deepika Bhavnani2019-09-132-17/+19
| |/ | | | | | | | | | | | | | | | | | | | | | | cpu_idx is used as mix of `unsigned int` and `signed int` in code with typecasting at some places. This change is to unify the cpu_idx as `unsigned int` as underlying API;s `plat_my_core_pos` returns `unsigned int` It was discovered via coverity issue CID 354715 Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I4f0adb0c596ff1177210c5fe803bff853f2e54ce
* | Merge "libc: fix sparse warning for __assert()" into integrationSoby Mathew2019-09-121-4/+5
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| * | libc: fix sparse warning for __assert()Masahiro Yamada2019-09-111-4/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Sparse warns this: lib/libc/assert.c:29:6: error: symbol '__assert' redeclared with different type (originally declared at include/lib/libc/assert.h:36) - different modifiers Add __dead2 to match the header declaration and C definition. I also changed '__dead2 void' to 'void __dead2' for the consistency with other parts. Change-Id: Iefa4f0e787c24fa7e7e499d2e7baf54d4deb49ef Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge changes from topic "jc/mte_enable" into integrationSoby Mathew2019-09-122-8/+42
|\ \ | | | | | | | | | | | | | | | * changes: Add documentation for CTX_INCLUDE_MTE_REGS Enable MTE support in both secure and non-secure worlds
| * | Enable MTE support in both secure and non-secure worldsJustin Chadwell2019-09-092-8/+42
| |/ | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the new Memory Tagging Extension arriving in ARMv8.5. MTE support is now enabled by default on systems that support at EL0. To enable it at ELx for both the non-secure and the secure world, the compiler flag CTX_INCLUDE_MTE_REGS includes register saving and restoring when necessary in order to prevent register leakage between the worlds. Change-Id: I2d4ea993d6b11654ea0d4757d00ca20d23acf36c Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* / Zeus: apply the MSR SSBS instructionJohn Tsichritzis2019-09-111-1/+11
|/ | | | | | | | | Zeus supports the SSBS mechanism and also the new MSR instruction to immediately apply the mitigation. Hence, the new instruction is utilised in the Zeus-specific reset function. Change-Id: I962747c28afe85a15207a0eba4146f9a115b27e7 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Merge "AArch64: Disable Secure Cycle Counter" into integrationPaul Beesley2019-08-232-39/+96
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| * AArch64: Disable Secure Cycle CounterAlexei Fedorov2019-08-212-39/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an issue when secure world timing information can be leaked because Secure Cycle Counter is not disabled. For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR_EL0.DP bit. 'include\aarch64\arch.h' header file was tided up and new ARMv8.5-PMU related definitions were added. Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Merge "Fix for N1 1043202 Errata Workaround" into integrationAlexei Fedorov2019-08-201-0/+1
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| * | Fix for N1 1043202 Errata Workaroundlaurenw-arm2019-08-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ISB instruction was removed from the N1 1043202 Errata Workaround [1], this fix is adding the ISB instruction back in. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I74eac7f6ad38991c36d423ad6aa44558033ad388
* | | Merge "Coverity fix: Remove GGC ignore -Warray-bounds" into integrationPaul Beesley2019-08-201-11/+11
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| * | | Coverity fix: Remove GGC ignore -Warray-boundsDeepika Bhavnani2019-08-161-11/+11
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC diagnostics were added to ignore array boundaries, instead of ignoring GCC warning current code will check for array boundaries and perform and array update only for valid elements. Resolves: `CID 246574` `CID 246710` `CID 246651` Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I7530ecf7a1707351c6ee87e90cc3d33574088f57
* / / FVP_Base_AEMv8A platform: Fix cache maintenance operationsAlexei Fedorov2019-08-161-5/+33
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes FVP_Base_AEMv8A model hang issue with ARMv8.4+ with cache modelling enabled configuration. Incorrect L1 cache flush operation to PoU, using CLIDR_EL1 LoUIS field, which is required by the architecture to be zero for ARMv8.4-A with ARMv8.4-S2FWB feature is replaced with L1 to L2 and L2 to L3 (if L3 is present) cache flushes. FVP_Base_AEMv8A model can be configured with L3 enabled by setting `cluster0.l3cache-size` and `cluster1.l3cache-size` to non-zero values, and presence of L3 is checked in `aem_generic_core_pwr_dwn` function by reading CLIDR_EL1.Ctype3 field value. Change-Id: If3de3d4eb5ed409e5b4ccdbc2fe6d5a01894a9af Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Merge changes from topic "jc/coverity-fixes" into integrationPaul Beesley2019-08-133-51/+6
|\ \ | |/ |/| | | | | | | | | | | * changes: Fix Coverity #261967, Infinite loop Fix Coverity #343017, Missing unlock Fix Coverity #343008, Side affect in assertion Fix Coverity #342970, Uninitialized scalar variable
| * Fix Coverity #261967, Infinite loopJustin Chadwell2019-08-061-47/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coverity has identified that the __aeabi_imod function will loop forever if the denominator is not a power of 2, which is probably not the desired behaviour. The functions in the rest of the file are compiler implementations of division if ARMv7 does not implement division which is permitted by the spec. However, while most of the functions in the file are documented and referenced in other places online, __aeabi_uimod and __aeabi_imod are not. For this reason, these functions have been removed from the code base, which also removes the Coverity error. Change-Id: I20066d72365329a8b03a5536d865c4acaa2139ae Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
| * Fix Coverity #343008, Side affect in assertionJustin Chadwell2019-08-061-2/+3
| | | | | | | | | | | | | | | | | | This patch simply splits off the increment of next_xlat into a separate statement to ensure consistent behaviour if the assert was to ever be removed. Change-Id: I827f601ccea55f4da9442048419c9b8cc0c5d22e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
| * Fix Coverity #342970, Uninitialized scalar variableJustin Chadwell2019-08-061-2/+3
| | | | | | | | | | | | | | | | This ensures that probe_data starts with a reasonable default, as opposed to whatever was left on the stack. Change-Id: I5550efea5e2bec7717f9fa063cb11e6a7005cce5 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* | Switch AARCH32/AARCH64 to __aarch64__Julius Werner2019-08-016-76/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org>
* | Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__Julius Werner2019-08-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
* | Enable AMU for Cortex-HerculesBalint Dobszay2019-07-311-1/+36
|/ | | | | Change-Id: Ie0a94783d0c8e111ae19fd592304e6485f04ca29 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
* Merge "Romlib makefile refactoring and script rewriting" into integrationSoby Mathew2019-07-2513-179/+370
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| * Romlib makefile refactoring and script rewritingImre Kis2019-07-2213-179/+370
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The features of the previously existing gentbl, genvar and genwrappers scripts were reimplemented in the romlib_generator.py Python script. This resulted in more readable and maintainable code and the script introduces additional features that help dependency handling in makefiles. The assembly templates were separated from the script logic and were collected in the 'templates' directory. The targets and their dependencies were reorganized in the makefile and the dependency handling of included index files is possible now. Incremental build is available in case of modifying the index files. Signed-off-by: Imre Kis <imre.kis@arm.com> Change-Id: I79f65fab9dc5c70d1f6fc8f57b2a3009bf842dc5
* | Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into ↵Soby Mathew2019-07-251-0/+33
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | integration * changes: plat/mediatek/mt81*: Use new bl31_params_parse() helper plat/rockchip: Use new bl31_params_parse_helper() Add helper to parse BL31 parameters (both versions) Factor out cross-BL API into export headers suitable for 3rd party code Use explicit-width data types in AAPCS parameter structs plat/rockchip: Switch to use new common BL aux parameter library Introduce lightweight BL platform parameter library
| * | Introduce lightweight BL platform parameter libraryJulius Werner2019-07-181-0/+33
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds some common helper code to support a lightweight platform parameter passing framework between BLs that has already been used on Rockchip platforms but is more widely useful to others as well. It can be used as an implementation for the SoC firmware configuration file mentioned in the docs, and is primarily intended for platforms that only require a handful of values to be passed and want to get by without a libfdt dependency. Parameters are stored in a linked list and the parameter space is split in generic and vendor-specific parameter types. Generic types will be handled by this code whereas vendor-specific types have to be handled by a vendor-specific handler function that gets passed in. Change-Id: If3413d44e86b99d417294ce8d33eb2fc77a6183f Signed-off-by: Julius Werner <jwerner@chromium.org>
* | Merge "Cortex_hercules: Introduce preliminary cpu support" into integrationSoby Mathew2019-07-231-0/+65
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| * | Cortex_hercules: Introduce preliminary cpu supportLouis Mayencourt2019-07-161-0/+65
| | | | | | | | | | | | | | | Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | Merge "Enable MTE support unilaterally for Normal World" into integrationSoby Mathew2019-07-231-0/+13
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| * | Enable MTE support unilaterally for Normal WorldSoby Mathew2019-07-121-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | This patch enables MTE for Normal world if the CPU suppors it. Enabling MTE for secure world will be done later. Change-Id: I9ef64460beaba15e9a9c20ab02da4fb2208b6f7d Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | | Merge changes from topic "jc/shift-overflow" into integrationSoby Mathew2019-07-161-2/+2
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: Enable -Wshift-overflow=2 to check for undefined shift behavior Update base code to not rely on undefined overflow behaviour Update hisilicon drivers to not rely on undefined overflow behaviour Update synopsys drivers to not rely on undefined overflow behaviour Update imx platform to not rely on undefined overflow behaviour Update mediatek platform to not rely on undefined overflow behaviour Update layerscape platform to not rely on undefined overflow behaviour Update intel platform to not rely on undefined overflow behaviour Update rockchip platform to not rely on undefined overflow behaviour Update renesas platform to not rely on undefined overflow behaviour Update meson platform to not rely on undefined overflow behaviour Update marvell platform to not rely on undefined overflow behaviour
| * | Update base code to not rely on undefined overflow behaviourJustin Chadwell2019-07-121-2/+2
| |/ | | | | | | | | | | | | | | This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Iddd6f38139a4c6e500468b4fc48d04e0939f574e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* / Rename Cortex-Deimos to Cortex-A77Balint Dobszay2019-07-101-20/+20
|/ | | | | Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
* Removing redundant ISB instructionslauwal012019-07-021-15/+1
| | | | | | | | Replacing ISB instructions in each Errata workaround with a single ISB instruction before the RET in the reset handler. Change-Id: I08afabc5b98986a6fe81664cd13822b36cab786f Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* Workaround for Neoverse N1 erratum 1275112lauwal012019-07-022-0/+41
| | | | | | | | | | | | | Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* Workaround for Neoverse N1 erratum 1262888lauwal012019-07-022-0/+41
| | | | | | | | | | | | Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* Workaround for Neoverse N1 erratum 1262606lauwal012019-07-022-0/+41
| | | | | | | | | | | | | Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* Workaround for Neoverse N1 erratum 1257314lauwal012019-07-022-0/+41
| | | | | | | | | | | | | Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* Workaround for Neoverse N1 erratum 1220197lauwal012019-07-022-0/+41
| | | | | | | | | | | | Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* Workaround for Neoverse N1 erratum 1207823lauwal012019-07-022-0/+41
| | | | | | | | | | | | Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* Workaround for Neoverse N1 erratum 1165347lauwal012019-07-022-0/+42
| | | | | | | | | | | | Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* Workaround for Neoverse N1 erratum 1130799lauwal012019-07-022-0/+41
| | | | | | | | | | | | Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* Workaround for Neoverse N1 erratum 1073348lauwal012019-07-022-0/+41
| | | | | | | | | | | | Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* libc: fix memchr implementationAmbroise Vincent2019-06-201-2/+2
| | | | | | | | The previous implementation could behave incorrectly because of the sign extension of the char when compared to the int. Change-Id: I397838b0ec87a6f1af6972d022a8c19a5184b447 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Merge "DSU: Apply erratum 936184 for Neoverse N1/E1" into integrationJohn Tsichritzis2019-06-172-1/+34
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