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* Merge changes from topic "mp/strto_libc" into integrationMadhukar Pappireddy2021-02-116-4/+507
|\ | | | | | | | | | | | | | | * changes: libc: Import strtoull from FreeBSD project libc: Import strtoll from FreeBSD project libc: Import strtoul from FreeBSD project libc: Import strtol from FreeBSD project
| * libc: Import strtoull from FreeBSD projectMadhukar Pappireddy2021-02-033-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: I2e94a0b227ec39f6f4530dc50bb477999d27730f Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * libc: Import strtoll from FreeBSD projectMadhukar Pappireddy2021-02-033-0/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: I9cb581574d46de73c3d6917ebf78935fc5ac075a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * libc: Import strtoul from FreeBSD projectMadhukar Pappireddy2021-02-033-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: I8c3b92751d1ce226c966f7c81fedd83f0846865e Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * libc: Import strtol from FreeBSD projectMadhukar Pappireddy2021-02-033-4/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: Ica95bf5da722913834fe90bf3fe743aa34e01e80 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | rainier: remove cpu workaround for errata 1542419Manoj Kumar2021-02-051-89/+1
|/ | | | | | | | This patch removes the Neoverse N1 CPU errata workaround for bug 1542419 as the bug is not present in Rainier R0P0 core. Change-Id: Icaca299b13ef830b2ee5129576aae655a6288e69 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
* Fix exception handlers in BL31: Use DSB to synchronize pending EAMadhukar Pappireddy2021-01-291-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For SoCs which do not implement RAS, use DSB as a barrier to synchronize pending external aborts at the entry and exit of exception handlers. This is needed to isolate the SErrors to appropriate context. However, this introduces an unintended side effect as discussed in the https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/3440 A summary of the side effect and a quick workaround is provided as part of this patch and summarized here: The explicit DSB at the entry of various exception vectors in BL31 for handling exceptions from lower ELs can inadvertently trigger an SError exception in EL3 due to pending asyncrhonouus aborts in lower ELs. This will end up being handled by serror_sp_elx in EL3 which will ultimately panic and die. The way to workaround is to update a flag to indicate if the exception truly came from EL3. This flag is allocated in the cpu_context structure. This is not a bullet proof solution to the problem at hand because we assume the instructions following "isb" that help to update the flag (lines 100-102 & 139-141) execute without causing further exceptions. Change-Id: I4d345b07d746a727459435ddd6abb37fda24a9bf Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* Merge "DebugFS: Check channel index before calling clone function" into ↵Olivier Deprez2021-01-222-4/+13
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| * DebugFS: Check channel index before calling clone functionZelalem2021-01-212-4/+13
| | | | | | | | | | | | | | | | | | To avoid a potential out-of-bounds access, check whether a device exists on a channel before calling the corresponding clone function. Signed-off-by: Zelalem <zelalem.aweke@arm.com> Change-Id: Ia0dd66b331d3fa8a33109a02369e1bc9ae0fdd5b
* | libc/snprintf: use macro to reduce duplicated codeHeyi Guo2021-01-201-22/+14
| | | | | | | | | | | | | | | | | | Add macro CHECK_AND_PUT_CHAR to check buffer capacity, save one character to buffer, and then increase character counter by one in one single statement, so that 4 similar code pieces can be cleaned. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I2add6b4bd6c24ea3c0d2499a44924e3e8db0f4d1
* | libc/snprintf: add support to print "%" characterHeyi Guo2021-01-201-1/+8
| | | | | | | | | | | | | | | | | | Enable snprintf()/vsnprintf() in TF-A to print "%" character as C standard, which may be used in platform porting to print percentage information. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I9b296372a1002046eabac1df5e8eb99a27efd4a8
* | libc/printf: add support to print "%" characterHeyi Guo2021-01-201-1/+4
|/ | | | | | | | Enable printf() in TF-A to print "%" character as C standard, which may be used in platform porting to print percentage information. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I7af2f1d153548e426f423fce15dc48b0da56c622
* Workaround for Cortex N1 erratum 1946160johpow012021-01-132-1/+73
| | | | | | | | | | | | | | | Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present starting from r0p0 but this workaround applies to revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
* Workaround for Cortex A78 erratum 1951500johpow012021-01-132-0/+69
| | | | | | | | | | | | | Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This workaround works on revisions r1p0 and r1p1, in r0p0 there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
* Workaround for Cortex A78 erratum 1941498johpow012021-01-122-3/+45
| | | | | | | | | | | | Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
* AArch64: Fix assertions in processing dynamic relocationsAlexei Fedorov2021-01-061-19/+29
| | | | | | | | | | | | | | | | | | | This patch provides the following changes in fixup_gdt_reloc() function: - Fixes assertions in processing dynamic relocations, when relocation entries not matching R_AARCH64_RELATIVE type are found. Linker might generate entries of relocation type R_AARCH64_NONE (code 0), which should be ignored to make the code boot. Similar issue was fixed in OP-TEE (see optee_os/ldelf/ta_elf_rel.c commit 7a4dc765c133125428136a496a7644c6fec9b3c2) - Fixes bug when "b.ge" (signed greater than or equal) condition codes were used instead of "b.hs" (greater than or equal) for comparison of absolute addresses. - Adds optimisation which skips fixing Global Object Table (GOT) entries when offset value is 0. Change-Id: I35e34e055b7476843903859be947b883a1feb1b5 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* PSCI: fix limit of 256 CPUs caused by cast to unsigned charGraeme Gregory2020-12-222-4/+19
| | | | | | | | | | | | | | | | | | | | In psci_setup.c psci_init_pwr_domain_node() takes an unsigned char as node_idx which limits it to initialising only the first 256 CPUs. As the calling function does not check for a limit of 256 I think this is a bug so change the unsigned char to uint16_t and change the cast from the calling site in populate_power_domain_tree(). Also update the non_cpu_pwr_domain_node structure lock_index to uint16_t and update the function signature for psci_lock_init() appropriately. Finally add a define PSCI_MAX_CPUS_INDEX to psci_private.h and add a CASSERT to psci_setup.c to make sure PLATFORM_CORE_COUNT cannot exceed the index value. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I9e26842277db7483fd698b46bbac62aa86e71b45
* Workaround for Cortex A76 erratum 1946160johpow012020-12-182-0/+69
| | | | | | | | | | | | | | Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions of the A76 processor core. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present in revisions r0p0 - r4p1 but this workaround only applies to revisions r3p0 - r4p1, there is no workaround for older versions. SDEN can be found here: https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327
* Add support for FEAT_MTPMU for Armv8.6Javier Almansa Sobrino2020-12-112-0/+201
| | | | | | | | | | | | | | | | | If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented as well, it is possible to control whether PMU counters take into account events happening on other threads. If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit leaving it to effective state of 0 regardless of any write to it. This patch introduces the DISABLE_MTPMU flag, which allows to diable multithread event count from EL3 (or EL2). The flag is disabled by default so the behavior is consistent with those architectures that do not implement FEAT_MTPMU. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
* Aarch64: Add support for FEAT_MTE3Alexei Fedorov2020-12-021-14/+17
| | | | | | | | | This patch provides the following changes: - Adds definition for FEAT_MTE3 value in ID_AA64PFR1_EL1 register - Enables Memory Tagging Extension for FEAT_MTE3. Change-Id: I735988575466fdc083892ec12c1aee89b5faa472 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Add support for Neoverse-N2 CPUs.Javier Almansa Sobrino2020-11-304-20/+142
| | | | | | | Enable basic support for Neoverse-N2 CPUs. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
* Revert workaround for A77 erratum 1800714johpow012020-11-122-43/+0
| | | | | | | | | | | This errata workaround did not work as intended and was revised in subsequent SDEN releases so we are reverting this change. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe
* Revert workaround for A76 erratum 1800710johpow012020-11-122-43/+0
| | | | | | | | | | | This errata workaround did not work as intended and was revised in subsequent SDEN releases so we are reverting this change. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0
* lib: el3_runtime: Fix SPE system registers in el2_sysregs_contextArunachalam Ganapathy2020-10-201-1/+9
| | | | | | | | | Include EL2 registers related to SPE in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: Ie01a2c38fa5f6c907276eddec120fdfb222561a6 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
* lib: el3_runtime: Conditionally save/restore EL2 NEVE registersArunachalam Ganapathy2020-10-201-0/+4
| | | | | | | | | Include EL2 registers related to Nested Virtualization in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
* lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_contextArunachalam Ganapathy2020-10-201-1/+13
| | | | | | | | | | AArch64-only platforms do not implement AArch32 at EL1 and higher ELs. In such cases the build option CTX_INCLUDE_AARCH32_REGS is set to 0. So don't save/restore aarch32 system registers in el2_sysregs_context save/restore routines if CTX_INCLUDE_AARCH32_REGS is set to 0. Change-Id: I229cdd46136c4b4bc9623b02eb444d904e09ce5a Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
* Merge "Increase type widths to satisfy width requirements" into integrationJoanna Farley2020-10-184-11/+13
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| * Increase type widths to satisfy width requirementsJimmy Brisson2020-10-124-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Usually, C has no problem up-converting types to larger bit sizes. MISRA rule 10.7 requires that you not do this, or be very explicit about this. This resolves the following required rule: bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None> The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U | 0x3c0U" (32 bits) is less that the right hand operand "18446744073709547519ULL" (64 bits). This also resolves MISRA defects such as: bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)] In the expression "3U << 20", shifting more than 7 bits, the number of bits in the essential type of the left expression, "3U", is not allowed. Further, MISRA requires that all shifts don't overflow. The definition of PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues. This fixes the violation by changing the definition to 1UL << 12. Since this uses 32bits, it should not create any issues for aarch32. This patch also contains a fix for a build failure in the sun50i_a64 platform. Specifically, these misra fixes removed a single and instruction, 92407e73 and x19, x19, #0xffffffff from the cm_setup_context function caused a relocation in psci_cpus_on_start to require a linker-generated stub. This increased the size of the .text section and caused an alignment later on to go over a page boundary and round up to the end of RAM before placing the .data section. This sectionn is of non-zero size and therefore causes a link error. The fix included in this reorders the functions during link time without changing their ording with respect to alignment. Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* | Merge changes Iba51bff1,I3f563cff into integrationMadhukar Pappireddy2020-10-161-3/+5
|\ \ | | | | | | | | | | | | | | | * changes: plat:qti Mandate SMC implementaion and bug fix Update in coreboot_get_memory_type API to include size as well
| * | Update in coreboot_get_memory_type API to include size as wellSaurabh Gorecha2020-10-161-3/+5
| |/ | | | | | | | | Change-Id: I3f563cffd58b0591b433c85c0ff6b71e486eb2c8 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
* | Merge "Don't return error information from console_flush" into integrationMark Dykes2020-10-142-8/+8
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| * Don't return error information from console_flushJimmy Brisson2020-10-092-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* | Workaround for Cortex A77 erratum 1925769johpow012020-10-072-0/+43
|/ | | | | | | | | | | | | Cortex A77 erratum 1925769 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9
* Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into ↵Madhukar Pappireddy2020-10-062-45/+45
|\ | | | | | | | | | | | | | | integration * changes: Rename Neoverse Zeus to Neoverse V1 Rename Cortex Hercules AE to Cortex 78 AE
| * Rename Neoverse Zeus to Neoverse V1Jimmy Brisson2020-10-051-24/+24
| | | | | | | | | | Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
| * Rename Cortex Hercules AE to Cortex 78 AEJimmy Brisson2020-10-051-21/+21
| | | | | | | | | | Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* | Merge "Workaround for Cortex A76 erratum 1868343" into integrationMadhukar Pappireddy2020-10-052-40/+60
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| * Workaround for Cortex A76 erratum 1868343johpow012020-10-032-40/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex A76 erratum 1868343 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. This workaround is the same as workarounds for errata 1262606 and 1275112, so all 3 have been combined into one function call. SDEN can be found here: https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d
* | libfdt: Upgrade libfdt source filesAndre Przywara2020-10-027-37/+54
|/ | | | | | | | | | | Update the libfdt source files, the upstream commit is 73e0f143b73d ("libfdt: fdt_strerror(): Fix comparison warning"). This brings us the fixes for the signed/unsigned comparison warnings, so platforms can enable -Wsign-compare now. Change-Id: I303d891c82ffea0acefdde27289339db5ac5a289 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge "Workaround for Cortex A77 erratum 1508412" into integrationMadhukar Pappireddy2020-09-292-0/+78
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| * Workaround for Cortex A77 erratum 1508412laurenw-arm2020-09-252-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0. The workaround is a write sequence to several implementation defined registers based on A77 revision. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
* | Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integrationManish Pandey2020-09-291-0/+218
|\ \ | | | | | | | | | | | | | | | | | | * changes: plat/arm: Add platform support for Morello fdts: add device tree sources for morello platform lib/cpus: add support for Morello Rainier CPUs
| * | lib/cpus: add support for Morello Rainier CPUsManoj Kumar2020-09-281-0/+218
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds CPU support for the Rainier CPU which is derived from Neoverse N1 r4p0 CPU and implements the Morello capability architecture. Change-Id: Ic6b796481da5a66504ecb0648879446edf4c69fb Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
* | | Merge "arm_fpga: Add support for unknown MPIDs" into integrationAndré Przywara2020-09-282-10/+129
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| * | arm_fpga: Add support for unknown MPIDsJavier Almansa Sobrino2020-09-252-10/+129
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows the system to fallback to a default CPU library in case the MPID does not match with any of the supported ones. This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build option to 1 (enabled by default only on arm_fpga platform). This feature can be very dangerous on a production image and therefore it MUST be disabled for Release images. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba
* | Merge "plat/arm: Introduce and use libc_asm.mk makefile" into integrationOlivier Deprez2020-09-243-0/+176
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| * | plat/arm: Introduce and use libc_asm.mk makefileAlexei Fedorov2020-09-023-0/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trace analysis of FVP_Base_AEMv8A 0.0/6063 model running in Aarch32 mode with the build options listed below: TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem shows that when auth_signature() gets called 71.99% of CPU execution time is spent in memset() function written in C using single byte write operations, see lib\libc\memset.c. This patch introduces new libc_asm.mk makefile which replaces C memset() implementation with assembler version giving the following results: - for Aarch32 in auth_signature() call memset() CPU time reduced to 20.56%. The number of CPU instructions (Inst) executed during TF-A boot stage before start of BL33 in RELEASE builds for different versions is presented in the tables below, where: - C TF-A: existing TF-A C code; - C musl: "lightweight code" C "implementation of the standard library for Linux-based systems" https://git.musl-libc.org/cgit/musl/tree/src/string/memset.c - Asm Opt: assemler version from "Arm Optimized Routines" project https://github.com/ARM-software/optimized-routines/blob/ master/string/arm/memset.S - Asm Linux: assembler version from Linux kernel https://github.com/torvalds/linux/blob/master/arch/arm/lib/memset.S - Asm TF-A: assembler version from this patch Aarch32: +-----------+------+------+--------------+----------+ | Variant | Set | Size | Inst | Ratio | +-----------+------+------+--------------+----------+ | C TF-A | T32 | 16 | 2122110003 | 1.000000 | | C musl | T32 | 156 | 1643917668 | 0.774662 | | Asm Opt | T32 | 84 | 1604810003 | 0.756233 | | Asm Linux | A32 | 168 | 1566255018 | 0.738065 | | Asm TF-A | A32 | 160 | 1525865101 | 0.719032 | +-----------+------+------+--------------+----------+ AArch64: +-----------+------+------------+----------+ | Variant | Size | Inst | Ratio | +-----------+------+------------+----------+ | C TF-A | 28 | 2732497518 | 1.000000 | | C musl | 212 | 1802999999 | 0.659836 | | Asm TF-A | 140 | 1680260003 | 0.614917 | +-----------+------+------------+----------+ This patch modifies 'plat\arm\common\arm_common.mk' by overriding libc.mk makefile with libc_asm.mk and does not effect other platforms. Change-Id: Ie89dd0b74ba1079420733a0d76b7366ad0157c2e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | | libc: Import strtok_r from FreeBSD projectMadhukar Pappireddy2020-09-181-0/+83
| |/ |/| | | | | | | | | | | | | From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b Made small changes to fit into TF-A project Change-Id: I991f653a7ace04f9c84bcda78ad8d7114ea18e93 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | Merge "SPE: Fix feature detection" into integrationMadhukar Pappireddy2020-09-151-1/+1
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| * | SPE: Fix feature detectionAndre Przywara2020-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the feature test for the SPE extension requires the feature bits in the ID_AA64DFR0 register to read exactly 0b0001. However the architecture guarantees that any values greater than 0 indicate the presence of a feature, which is what we are after in our spe_supported() function. Change the comparison to include all values greater than 0. This fixes SPE support in non-secure world on implementations which include the Scalable Vector Extension (SVE), for instance on Zeus cores. Change-Id: If6cbd1b72d6abb8a303e2c0a7839d508f071cdbe Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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