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* Merge pull request #1357 from antonio-nino-diaz-arm/an/fix-misraDimitris Papastamos2018-04-181-7/+8
|\ | | | | Fix some MISRA defects in SPM code
| * Fix some MISRA defects in SPM codeAntonio Nino Diaz2018-04-171-7/+8
| | | | | | | | | | Change-Id: I989c1f4aef8e3cb20d5d19e6347575e6449bb60b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Check presence of fix for errata 835769 in Cortex-A53Jonathan Wright2018-04-121-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | A fix for errata 835769 may be available in revisions r0p2, r0p3 or r0p4 of the Cortex-A53 processor. The presence of the fix is determined by checking bit 7 in the REVIDR register. If the fix is present we report ERRATA_NOT_APPLIES which silences the erroneous 'missing workaround' warning. Change-Id: Ib75b008e755e9ac648554ca9398024fdbea4a91a Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
* | Check presence of fix for errata 843419 in Cortex-A53Jonathan Wright2018-04-122-3/+22
|/ | | | | | | | | | | | A fix for errata 843419 may be available in revision r0p4 of the Cortex-A53 processor. The presence of the fix is determined by checking bit 8 in the REVIDR register. If the fix is present we report ERRATA_NOT_APPLIES which silences the erroneous 'missing workaround' warning. Change-Id: Ibd2a478df3e2a6325442a6a48a0bb0259dcfc1d7 Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
* lib: xlat_tables_v2: reduce time required to add a mmap regionVarun Wadekar2018-04-091-2/+18
| | | | | | | | | | | | | | | | | | | | The last entry in the mapping table is not necessarily the same as the end of the table. This patch loops through the table to find the last entry marker, on every new mmap addition. The memove operation then has to only move the memory between current entry and the last entry. For platforms that arrange their MMIO map properly, this opearation turns out to be a NOP. The previous implementation added significant overhead per mmap addition as the memmove operation always moved the difference between the current mmap entry and the end of the table. Tested on Tegra platforms and this new approach improves the memory mapping time by ~75%, thus significantly reducing boot time on some platforms. Change-Id: Ie3478fa5942379282ef58bee2085da799137e2ca Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statementsDimitris Papastamos2018-03-292-10/+4
|\ | | | | Fix switch statements to comply with MISRA rules
| * lib: fix switch statements to comply with MISRA rulesJonathan Wright2018-03-262-10/+4
| | | | | | | | | | | | | | | | Ensure (where possible) that switch statements in lib comply with MISRA rules 16.1 - 16.7. Change-Id: I52bc896fb7094d2b7569285686ee89f39f1ddd84 Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
* | Merge pull request #1335 from JoelHutton/jh/cleanup_void_pointersDimitris Papastamos2018-03-292-14/+11
|\ \ | | | | | | Clean usage of void pointers to access symbols
| * | Clean usage of void pointers to access symbolsJoel Hutton2018-03-272-14/+11
| |/ | | | | | | | | | | | | | | | | | | | | Void pointers have been used to access linker symbols, by declaring an extern pointer, then taking the address of it. This limits symbols values to aligned pointer values. To remove this restriction an IMPORT_SYM macro has been introduced, which declares it as a char pointer and casts it to the required type. Change-Id: I89877fc3b13ed311817bb8ba79d4872b89bfd3b0 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
* / psci: initialize array fully to comply with MISRAJonathan Wright2018-03-271-1/+6
|/ | | | | | | | | | | Initializes each element of the last_cpu_in_non_cpu_pd array in PSCI stat implementation to -1, the reset value. This satisfies MISRA rule 9.3. Previously, only the first element of the array was initialized to -1. Change-Id: I666c71e6c073710c67c6d24c07a219b1feb5b773 Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
* Merge pull request #1311 from jonathanwright-ARM/jw/MISRA-EOF-usagedavidcunado-arm2018-03-221-13/+7
|\ | | | | stdlib: remove comparison with EOF macro to comply with MISRA
| * stdlib: remove comparison with EOF macro to comply with MISRAJonathan Wright2018-03-151-13/+7
| | | | | | | | | | | | | | Ensures compliance with MISRA C-2012 Rule 22.7 Change-Id: Ifbe0926a24ba0dca18174e1aa87313a63bba50fb Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
* | Rename 'smcc' to 'smccc'Antonio Nino Diaz2018-03-214-7/+7
|/ | | | | | | | | | | | | When the source code says 'SMCC' it is talking about the SMC Calling Convention. The correct acronym is SMCCC. This affects a few definitions and file names. Some files have been renamed (smcc.h, smcc_helpers.h and smcc_macros.S) but the old files have been kept for compatibility, they include the new ones with an ERROR_DEPRECATED guard. Change-Id: I78f94052a502436fdd97ca32c0fe86bd58173f2f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Fixup `SMCCC_ARCH_FEATURES` semanticsDimitris Papastamos2018-03-145-9/+42
| | | | | | | | | | | | | | | | When querying `SMCCC_ARCH_WORKAROUND_1` through `SMCCC_ARCH_FEATURES`, return either: * -1 to indicate the PE on which `SMCCC_ARCH_FEATURES` is called requires firmware mitigation for CVE-2017-5715 but the mitigation is not compiled in. * 0 to indicate that firmware mitigation is required, or * 1 to indicate that no firmware mitigation is required. This patch complies with v1.2 of the firmware interfaces specification (ARM DEN 0070A). Change-Id: Ibc32d6620efdac6c340758ec502d95554a55f02a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Use PFR0 to identify need for mitigation of CVE-2017-5715Dimitris Papastamos2018-03-143-18/+14
| | | | | | | | | If the CSV2 field reads as 1 then branch targets trained in one context cannot affect speculative execution in a different context. In that case skip the workaround on Cortex A72 and A73. Change-Id: Ide24fb6efc77c548e4296295adc38dca87d042ee Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Merge pull request #1282 from robertovargas-arm/misra-changesdavidcunado-arm2018-02-287-9/+13
|\ | | | | Misra changes
| * Fix MISRA rule 8.4 Part 1Roberto Vargas2018-02-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all Change-Id: I7c2ad3f5c015411c202605851240d5347e4cc8c7 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
| * Fix MISRA rule 8.4 in common codeRoberto Vargas2018-02-284-4/+8
| | | | | | | | | | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined. Change-Id: I26e042cb251a6f9590afa1340fdac73e42f23979 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
| * Fix MISRA rule 8.3 in common codeRoberto Vargas2018-02-282-5/+5
| | | | | | | | | | | | | | | | Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers. Change-Id: Iff384187c74a598a4e73f350a1893b60e9d16cec Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | Merge pull request #1287 from davidcunado-arm/dc/fix_misradavidcunado-arm2018-02-283-3/+3
|\ \ | | | | | | Update ULL() macro and instances of ull to comply with MISRA
| * | Update ULL() macro and instances of ull to comply with MISRADavid Cunado2018-02-273-3/+3
| |/ | | | | | | | | | | | | | | | | | | MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
* | Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatchdavidcunado-arm2018-02-282-2/+46
|\ \ | | | | | | Clarify comments in xlat tables lib and fixes related to the TLB
| * | Invalidate TLB entries during warm bootAntonio Nino Diaz2018-02-272-2/+46
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the warm boot sequence: 1. The MMU is enabled with the data cache disabled. The MMU table walker is set up to access the translation tables as in cacheable memory, but its accesses are non-cacheable because SCTLR_EL3.C controls them as well. 2. The interconnect is set up and the CPU enters coherency with the rest of the system. 3. The data cache is enabled. If the support for dynamic translation tables is enabled and another CPU makes changes to a region, the changes may only be present in the data cache, not in RAM. The CPU that is booting isn't in coherency with the rest of the system, so the table walker of that CPU isn't either. This means that it may read old entries from RAM and it may have invalid TLB entries corresponding to the dynamic mappings. This is not a problem for the boot code because the mapping is 1:1 and the regions are static. However, the code that runs after the boot sequence may need to access the dynamically mapped regions. This patch invalidates all TLBs during warm boot when the dynamic translation tables support is enabled to prevent this problem. Change-Id: I80264802dc0aa1cb3edd77d0b66b91db6961af3d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1274 from dp-arm/dp/a75davidcunado-arm2018-02-274-156/+185
|\ \ | | | | | | AMU fixes for Cortex-A75
| * | MISRA fixes for Cortex A75 AMU implementationDimitris Papastamos2018-02-272-7/+7
| | | | | | | | | | | | | | | Change-Id: I61c9fdfda0c0b3c3ec6249519db23602cf4c2100 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
| * | Refactor AMU support for Cortex A75Dimitris Papastamos2018-02-273-156/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch also fixes the assumption that the counters are disabled on the resume path. This is incorrect as the AMU counters are enabled early in the CPU reset function before `cpuamu_context_restore()` runs. Change-Id: I38a94eb166a523f00de18e86860434ffccff2131 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
| * | Factor out CPU AMU helpersDimitris Papastamos2018-02-271-0/+107
| |/ | | | | | | | | | | | | | | This patch also fixes `cpuamu_write_cpuamcntenclr_el0()` to use an MSR instruction instead of an MRS instruction. Change-Id: Ia6531f64b5ebc60ba432124eaa8d8eaccba40ed0 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | MISRA fixes for AMU/SPE and SVEDimitris Papastamos2018-02-274-24/+22
| | | | | | | | | | Change-Id: I38470528111410cf12b187eb1397d87b812c9416 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | aarch32: Fix multiple bugs in amu_helpers.SDimitris Papastamos2018-02-271-85/+89
| | | | | | | | | | | | | | | | | | | | | | | | AArch32 uses odd-even pairs when passing 64-bit arguments to functions. For example in `amu_group0_cnt_write_internal()` the second argument is a uint64_t which is passed in r2 and r3. In `amu_group1_set_evtype_internal()` the value that needs to be written to the system register is in r1 not in r0. Change-Id: I20196268fdb1dc9ef6c4ebe61e761fba9623b3f2 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | Assert that group0/group1 counter config is what we expectDimitris Papastamos2018-02-271-2/+3
| | | | | | | | | | | | | | | | | | Before suspend the AMU counters should be enabled and after resume they should be disabled. Assert that to be consistent with the AArch64 implementation of `amu_context_{save,restore}()`. Change-Id: Ia46f77e4062b93afb93721a2890a9b9d2a7f300e Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | Implement {spe,sve}_supported() helpers and refactor codeDimitris Papastamos2018-02-272-131/+135
|/ | | | | | | | | Implement helpers to test if the core supports SPE/SVE. We have a similar helper for AMU and this patch makes all extensions consistent in their implementation. Change-Id: I3e6f7522535ca358259ad142550b19fcb883ca67 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Fixup AArch32 errata printing frameworkSoby Mathew2018-02-221-2/+3
| | | | | | | | | The AArch32 assembly implementation of `print_errata_status` did not save a register which was getting clobbered by a `get_cpu_ops_ptr`. This patch fixes that. Change-Id: Id0711e46b7c685a18a10328d4b513e952a5d860b Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* Merge pull request #1258 from vchong/optee_dbgdavidcunado-arm2018-02-161-9/+9
|\ | | | | optee: print header info before validate
| * optee: print header info before validateVictor Chong2018-02-081-9/+9
| | | | | | | | | | | | | | | | Currently optee header info is only printed after it is validated, but this does not help with debugging in case of error, so print it before. Signed-off-by: Victor Chong <victor.chong@linaro.org>
* | Merge pull request #1260 from sandrine-bailleux-arm/topics/sb/fix-zlib-builddavidcunado-arm2018-02-091-2/+2
|\ \ | | | | | | zlib: Fix build error when LOG_LEVEL=50
| * | zlib: Fix build error when LOG_LEVEL=50Sandrine Bailleux2018-02-081-2/+2
| |/ | | | | | | | | | | | | | | When enabling VERBOSE() traces, the zlib library fails to compile because of an incompatible format specifier string. Fix that. Change-Id: I74ff1c8dc2e6157ee982f7754bce4504599e3013 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | Merge pull request #1254 from masahir0y/bl2-at-el3davidcunado-arm2018-02-081-1/+1
|\ \ | |/ |/| Fix zero_normalmem() for BL2_AT_EL3
| * misc_helpers: fix zero_normalmem() for BL2_AT_EL3Masahiro Yamada2018-02-011-1/+1
| | | | | | | | | | | | | | The assertion in zero_normalmem() fails for BL2_AT_EL3. This mode is executed in EL3, so it should check sctlr_el3 instead of sctlr_el1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge pull request #1173 from etienne-lms/armv7-qemudavidcunado-arm2018-02-071-4/+13
|\ \ | | | | | | support to boot OP-TEE on AArch32/Armv7+example with Cortex-A15/Qemu
| * | aarch32: optee: define the OP-TEE secure payloadEtienne Carriere2018-02-051-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AArch32 only platforms can boot the OP-TEE secure firmware as a BL32 secure payload. Such configuration can be defined through AARCH32_SP=optee. The source files can rely on AARCH32_SP_OPTEE to condition OP-TEE boot specific instruction sequences. OP-TEE does not expect ARM Trusted Firmware formatted structure as boot argument. Load sequence is expected to have already loaded to OP-TEE boot arguments into the bl32 entrypoint info structure. Last, AArch32 platform can only boot AArch32 OP-TEE images. Change-Id: Ic28eec5004315fc9111051add6bb1a1d607fc815 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* | | Merge pull request #1224 from masahir0y/gzipdavidcunado-arm2018-02-0616-0/+6717
|\ \ \ | | | | | | | | Support GZIP-compressed images for faster loading and verification
| * | | zlib: add gunzip() supportMasahiro Yamada2018-02-022-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds some more files to use zlib from TF. To use zlib, ->zalloc and ->zfree hooks are needed. The implementation depends on the system. For user-space, the libc provides malloc() and friends. Unfortunately, ARM Trusted Firmware does not provide malloc() or any concept of dynamic memory allocation. I implemented very simple calloc() and free() for this. Stupidly, zfree() never frees memory, but it works enough for this. The purpose of using zlib is to implement gunzip() - this function takes compressed data from in_buf, then dumps the decompressed data to oub_buf. The work_buf is used for memory allocation during the decompress. Upon exit, it updates in_buf and out_buf. If successful, in_buf points to the end of input data, out_buf to the end of the decompressed data. To use this feature, you need to do: - include lib/zlib/zlib.mk from your platform.mk - add $(ZLIB_SOURCES) to your BL*_SOURCES Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | zlib: import zlib files from zlib 1.2.11Masahiro Yamada2018-02-0214-0/+6591
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import the following files from zlib 1.2.11: adler32.c crc32.c crc32.h inffast.c inffast.h inffixed.h inflate.c inflate.h inftrees.c inftrees.h zconf.h zlib.h zutil.c zutil.h The original tarball is available from http://zlib.net/ The zlib is free software, distributed under the zlib license. The license text is included in the "zlib.h" file. It should be compatible with BSD-3-Clause. The zlib license is included in the SPDX license list available at https://spdx.org/licenses/, but I did not add the SPDX license tag to the imported files above, to keep them as they are in the upstream project. This seems the general policy for ARM Trusted Firmware, as SPDX License Identifier was not added to files imported from FreeBSD. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | Merge pull request #1253 from dp-arm/dp/amu32davidcunado-arm2018-02-024-21/+340
|\ \ \ | |_|/ |/| | AMUv1 support for AArch32
| * | AMU: Implement context save/restore for aarch32Joel Hutton2018-01-313-21/+75
| | | | | | | | | | | | | | | | | | | | | Add amu_context_save() and amu_context_restore() functions for aarch32 Change-Id: I4df83d447adeaa9d9f203e16dc5a919ffc04d87a Signed-off-by: Joel Hutton <joel.hutton@arm.com>
| * | AMU: Add assembler helper functions for aarch32Joel Hutton2018-01-311-0/+265
| |/ | | | | | | | | Change-Id: Id6dfe885a63561b1d2649521bd020367b96ae1af Signed-off-by: Joel Hutton <joel.hutton@arm.com>
* | Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75Dimitris Papastamos2018-01-292-14/+67
| | | | | | | | | | | | | | | | | | | | | | | | This patch implements a fast path for this SMC call on affected PEs by detecting and returning immediately after executing the workaround. NOTE: The MMU disable/enable workaround now assumes that the MMU was enabled on entry to EL3. This is a valid assumption as the code turns on the MMU after reset and leaves it on until the core powers off. Change-Id: I13c336d06a52297620a9760fb2461b4d606a30b3 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | Optimize/cleanup BPIALL workaroundDimitris Papastamos2018-01-291-121/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | In the initial implementation of this workaround we used a dedicated workaround context to save/restore state. This patch reduces the footprint as no additional context is needed. Additionally, this patch reduces the memory loads and stores by 20%, reduces the instruction count and exploits static branch prediction to optimize the SMC path. Change-Id: Ia9f6bf06fbf8a9037cfe7f1f1fb32e8aec38ec7d Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | Add support for SMCCC_VERSION in PSCI featuresDimitris Papastamos2018-01-291-1/+5
|/ | | | | | | | On some platforms it may be necessary to discover the SMCCC version via a PSCI features call. Change-Id: I95281ac2263ca9aefda1809eb03464fbdb8ac24d Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Merge pull request #1228 from dp-arm/dp/cve_2017_5715davidcunado-arm2018-01-2510-10/+223
|\ | | | | Workarounds for CVE-2017-5715 on A9/A15 and A17 + serial console reporting
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