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* locks: bakery: add a DMB to the 'read_cache_op' macroVarun Wadekar2020-03-061-0/+3
| | | | | | | | | | | | | | | | | ARM has a weak memory ordering model. This means that without explicit barriers, memory accesses can be observed differently than program order. In this case, the cache invalidate instruction can be observed after the subsequent read to address. To solve this, a DMB instruction is required between the cache invalidate and the read. This ensures that the cache invalidate completes before all memory accesses in program order after the DMB. This patch updates the 'read_cache_op' macro to issue a DMB after the cache invalidate instruction to fix this anomaly. Change-Id: Iac9a90d228c57ba8bcdca7e409ea6719546ab441 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* T589: Fix insufficient ordering guarantees in bakery lockRaghu Krishnamurthy2020-01-272-12/+20
| | | | | | | | | | | | | | bakery_lock_get() uses DMB LD after lock acquisition and bakery_lock_release() uses DMB ST before releasing the lock. This is insufficient in both cases. With just DMB LD, stores in the critical section can be reordered before the DMB LD which could mean writes in the critical section completing before the lock has been acquired successfully. Similarly, with just DMB ST, a load in the critical section could be reordered after the the DMB ST. DMB is the least expensive barrier that can provide the required ordering. Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@icloud.com> Change-Id: Ieb74cbf5b76b09e1789331b71f37f7c660221b0e
* Fix the CAS spinlock implementationSoby Mathew2019-10-041-35/+18
| | | | | | | | | | | | | | | | | Make the spinlock implementation use ARMv8.1-LSE CAS instruction based on a platform build option. The CAS-based implementation used to be unconditionally selected for all ARM8.1+ platforms. The previous CAS spinlock implementation had a bug wherein the spin_unlock() implementation had an `sev` after `stlr` which is not sufficient. A dsb is needed to ensure that the stlr completes prior to the sev. Having a dsb is heavyweight and a better solution would be to use load exclusive semantics to monitor the lock and wake up from wfe when a store happens to the lock. The patch implements the same. Change-Id: I5283ce4a889376e4cc01d1b9d09afa8229a2e522 Signed-off-by: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
* Switch AARCH32/AARCH64 to __aarch64__Julius Werner2019-08-011-6/+6
| | | | | | | | | | | | | | | | | NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org>
* Remove .arch directives from spinlock.SAlexei Fedorov2019-05-131-5/+1
| | | | | | | | | | | | This patch removes .arch "arm8.1-a" and "armv8-a" directives which overwrite ASFLAGS_aarch64 option based on ARM_ARCH_MINOR passed to Makefile and cause translation errors like "selected processor does not support `bti jc'" for armv8.5-a targets when BTI support is enabled. Change-Id: Idca5b66ed1e5d86e2188b0c0f16c3819990957c4 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* locks: linker variables to calculate per-cpu bakery lock sizeVarun Wadekar2019-02-071-1/+3
| | | | | | | | | | | This patch introduces explicit linker variables to mark the start and end of the per-cpu bakery lock section to help bakery_lock_normal.c calculate the size of the section. This patch removes the previously used '__PERCPU_BAKERY_LOCK_SIZE__' linker variable to make the code uniform across GNU linker and ARM linker. Change-Id: Ie0c51702cbc0fe8a2076005344a1fcebb48e7cca Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* Sanitise includes across codebaseAntonio Nino Diaz2019-01-042-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* bakery: Fix MISRA defectsAntonio Nino Diaz2018-11-012-39/+50
| | | | | Change-Id: I600bc13522ae977db355b6dc5a1695bce39ec130 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Remove all other deprecated interfaces and filesAntonio Nino Diaz2018-09-281-9/+0
| | | | | Change-Id: Icd1cdd42afdc78895a9be6c46b414b0a155cfa63 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Add missing barriers to Bakery LocksJeenu Viswambharan2018-09-052-5/+23
| | | | | | | | | | | | With the current implementation, it's possible for a contender to observe accesses in the Critical Section before acquiring or releasing the lock. Insert fencing in the locking and release codes to prevent any reorder. Fixes ARM-software/tf-issues#609 Change-Id: I773b82aa41dd544a2d3dbacb9a4b42c9eb767bbb Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Fix MISRA Rule 5.3 Part 4Daniel Boulby2018-06-121-7/+7
| | | | | | | | | | | | | | Use a _ prefix for macro arguments to prevent that argument from hiding variables of the same name in the outer scope Rule 5.3: An identifier declared in an inner scope shall not hide an identifier declared in an outer scope Fixed For: make PLAT=fvp USE_COHERENT_MEM=0 Change-Id: If50c583d3b63799ee6852626b15be00c0f6b10a0 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* Fix MISRA Rule 5.3 Part 2Daniel Boulby2018-06-121-3/+3
| | | | | | | | | | | | | | Use a _ prefix for Macro arguments to prevent that argument from hiding variables of the same name in the outer scope Rule 5.3: An identifier declared in an inner scope shall not hide an identifier declared in an outer scope Fixed For: make LOG_LEVEL=50 PLAT=fvp Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* Clean usage of void pointers to access symbolsJoel Hutton2018-03-271-3/+3
| | | | | | | | | | | Void pointers have been used to access linker symbols, by declaring an extern pointer, then taking the address of it. This limits symbols values to aligned pointer values. To remove this restriction an IMPORT_SYM macro has been introduced, which declares it as a char pointer and casts it to the required type. Change-Id: I89877fc3b13ed311817bb8ba79d4872b89bfd3b0 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
* ARMv7 does not support STL instructionEtienne Carriere2017-11-081-0/+12
| | | | | | | Also need to add a SEV instruction in ARMv7 spin_unlock which is implicit in ARMv8. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* Add macro to test for minimum architecture versionJeenu Viswambharan2017-08-241-1/+1
| | | | | | | | | | | The macro concisely expresses and requires architecture version to be at least as required by its arguments. This would be useful when extending Trusted Firmware functionality for future architecture revisions. Replace similar usage in the current code base with the new macro. Change-Id: I9dcd0aa71a663eabd02ed9632b8ce87611fa5a57 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Use SPDX license identifiersdp-arm2017-05-035-125/+5
| | | | | | | | | | | | To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
* AArch32: Fix normal memory bakery compilationSoby Mathew2017-03-021-2/+9
| | | | | | | | This patch fixes a compilation issue with bakery locks when PSCI library is compiled with USE_COHERENT_MEM = 0 build option. Change-Id: Ic7f6cf9f2bb37f8a946eafbee9cbc3bf0dc7e900 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* Introduce locking primitives using CAS instructionJeenu Viswambharan2017-02-141-1/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARMv8v.1 architecture extension has introduced support for far atomics, which includes compare-and-swap. Compare and Swap instruction is only available for AArch64. Introduce build options to choose the architecture versions to target ARM Trusted Firmware: - ARM_ARCH_MAJOR: selects the major version of target ARM Architecture. Default value is 8. - ARM_ARCH_MINOR: selects the minor version of target ARM Architecture. Default value is 0. When: (ARM_ARCH_MAJOR > 8) || ((ARM_ARCH_MAJOR == 8) && (ARM_ARCH_MINOR >= 1)), for AArch64, Compare and Swap instruction is used to implement spin locks. Otherwise, the implementation falls back to using load-/store-exclusive instructions. Update user guide, and introduce a section in Firmware Design guide to summarize support for features introduced in ARMv8 Architecture Extensions. Change-Id: I73096a0039502f7aef9ec6ab3ae36680da033f16 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Fix normal memory bakery lock implementationSoby Mathew2016-11-211-8/+21
| | | | | | | | | | | | | | | This patch fixes an issue in the normal memory bakery lock implementation. During assertion of lock status, there is a possibility that the assertion could fail. This is because the previous update done to the lock status by the owning CPU when not participating in cache coherency could result in stale data in the cache due to cache maintenance operations not propagating to all the caches. This patch fixes this issue by doing an extra read cache maintenance operation prior to the assertion. Fixes ARM-software/tf-issues#402 Change-Id: I0f38a7c52476a4f58e17ebe0141d256d198be88d Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* AArch32: Add support in TF librariesSoby Mathew2016-08-101-0/+55
| | | | | | | | | | This patch adds AArch32 support to cpu ops, context management, per-cpu data and spinlock libraries. The `entrypoint_info` structure is modified to add support for AArch32 register arguments. The CPU operations for AEM generic cpu in AArch32 mode is also added. Change-Id: I1e52e79f498661d8f31f1e7b3a29e222bc7a4483
* Move spinlock library code to AArch64 folderSoby Mathew2016-08-092-23/+56
| | | | | | | | | | | This patch moves the assembly exclusive lock library code `spinlock.S` into architecture specific folder `aarch64`. A stub file which includes the file from new location is retained at the original location for compatibility. The BL makefiles are also modified to include the file from the new location. Change-Id: Ide0b601b79c439e390c3a017d93220a66be73543
* Rework type usage in Trusted FirmwareSoby Mathew2016-07-181-3/+3
| | | | | | | | | | | | | | | | | | This patch reworks type usage in generic code, drivers and ARM platform files to make it more portable. The major changes done with respect to type usage are as listed below: * Use uintptr_t for storing address instead of uint64_t or unsigned long. * Review usage of unsigned long as it can no longer be assumed to be 64 bit. * Use u_register_t for register values whose width varies depending on whether AArch64 or AArch32. * Use generic C types where-ever possible. In addition to the above changes, this patch also modifies format specifiers in print invocations so that they are AArch64/AArch32 agnostic. Only files related to upcoming feature development have been reworked. Change-Id: I9f8c78347c5a52ba7027ff389791f1dad63ee5f8
* Re-design bakery lock memory allocation and algorithmAndrew Thoelke2015-09-112-23/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch unifies the bakery lock api's across coherent and normal memory implementation of locks by using same data type `bakery_lock_t` and similar arguments to functions. A separate section `bakery_lock` has been created and used to allocate memory for bakery locks using `DEFINE_BAKERY_LOCK`. When locks are allocated in normal memory, each lock for a core has to spread across multiple cache lines. By using the total size allocated in a separate cache line for a single core at compile time, the memory for other core locks is allocated at link time by multiplying the single core locks size with (PLATFORM_CORE_COUNT - 1). The normal memory lock algorithm now uses lock address instead of the `id` in the per_cpu_data. For locks allocated in coherent memory, it moves locks from tzfw_coherent_memory to bakery_lock section. The bakery locks are allocated as part of bss or in coherent memory depending on usage of coherent memory. Both these regions are initialised to zero as part of run_time_init before locks are used. Hence, bakery_lock_init() is made an empty function as the lock memory is already initialised to zero. The above design lead to the removal of psci bakery locks from non_cpu_power_pd_node to psci_locks. NOTE: THE BAKERY LOCK API WHEN USE_COHERENT_MEM IS NOT SET HAS CHANGED. THIS IS A BREAKING CHANGE FOR ALL PLATFORM PORTS THAT ALLOCATE BAKERY LOCKS IN NORMAL MEMORY. Change-Id: Ic3751c0066b8032dcbf9d88f1d4dc73d15f61d8b
* PSCI: Migrate TF to the new platform API and CM helpersSoby Mathew2015-08-132-3/+3
| | | | | | | | | This patch migrates the rest of Trusted Firmware excluding Secure Payload and the dispatchers to the new platform and context management API. The per-cpu data framework APIs which took MPIDRs as their arguments are deleted and only the ones which take core index as parameter are retained. Change-Id: I839d05ad995df34d2163a1cfed6baa768a5a595d
* Add support to indicate size and end of assembly functionsKévin Petit2015-04-081-0/+2
| | | | | | | | | | | | | | | | | | In order for the symbol table in the ELF file to contain the size of functions written in assembly, it is necessary to report it to the assembler using the .size directive. To fulfil the above requirements, this patch introduces an 'endfunc' macro which contains the .endfunc and .size directives. It also adds a .func directive to the 'func' assembler macro. The .func/.endfunc have been used so the assembler can fail if endfunc is omitted. Fixes ARM-Software/tf-issues#295 Change-Id: If8cb331b03d7f38fe7e3694d4de26f1075b278fc Signed-off-by: Kévin Petit <kevin.petit@arm.com>
* Remove the `owner` field in bakery_lock_t data structureSoby Mathew2015-03-272-10/+16
| | | | | | | | | | | This patch removes the `owner` field in bakery_lock_t structure which is the data structure used in the bakery lock implementation that uses coherent memory. The assertions to protect against recursive lock acquisition were based on the 'owner' field. They are now done based on the bakery lock ticket number. These assertions are also added to the bakery lock implementation that uses normal memory as well. Change-Id: If4850a00dffd3977e218c0f0a8d145808f36b470
* Optimize the bakery lock structure for coherent memorySoby Mathew2015-03-272-32/+16
| | | | | | | | | | | | This patch optimizes the data structure used with the bakery lock implementation for coherent memory to save memory and minimize memory accesses. These optimizations were already part of the bakery lock implementation for normal memory and this patch now implements it for the coherent memory implementation as well. Also included in the patch is a cleanup to use the do-while loop while waiting for other contenders to finish choosing their tickets. Change-Id: Iedb305473133dc8f12126726d8329b67888b70f1
* Move bakery algorithm implementation out of coherent memorySoby Mathew2015-01-222-1/+220
| | | | | | | | | | | | | | | | This patch moves the bakery locks out of coherent memory to normal memory. This implies that the lock information needs to be placed on a separate cache line for each cpu. Hence the bakery_lock_info_t structure is allocated in the per-cpu data so as to minimize memory wastage. A similar platform per-cpu data is introduced for the platform locks. As a result of the above changes, the bakery lock api is completely changed. Earlier, a reference to the lock structure was passed to the lock implementation. Now a unique-id (essentially an index into the per-cpu data array) and an offset into the per-cpu data for bakery_info_t needs to be passed to the lock implementation. Change-Id: I1e76216277448713c6c98b4c2de4fb54198b39e0
* Remove the wfe() for bounded wait in bakery_lockSoby Mathew2015-01-221-3/+1
| | | | | | | | | | | | This patch is an optimization in the bakery_lock_get() function which removes the wfe() when waiting for other contenders to choose their ticket i.e when their `entering` flag is set. Since the time taken to execute bakery_get_ticket() by other contenders is bounded, this wait is a bounded time wait. Hence the removal of wfe() and the corresponding sev() and dsb() in bakery_get_ticket() may result in better time performance during lock acquisition. Change-Id: I141bb21294226b54cb6e89e7cac0175c553afd8d
* Precede a 'sev' with a 'dsb' in bakery lock codeAchin Gupta2014-11-101-0/+2
| | | | | | | | | | | This patch fixes a bug in the bakery lock implementation where a data synchronisation barrier instruction is not issued before sending an event as mandated by the ARMv8 ARM. This can cause a event to be signalled before the related memory accesses have completed resulting in erroneous execution. Fixes ARM-software/tf-issues#272 Change-Id: I5ce02bf70afb001d967b9fa4c3f77442931d5349
* Remove calling CPU mpidr from bakery lock APIAndrew Thoelke2014-06-231-4/+4
| | | | | | | | | | | | | | | | | The bakery lock code currently expects the calling code to pass the MPIDR_EL1 of the current CPU. This is not always done correctly. Also the change to provide inline access to system registers makes it more efficient for the bakery lock code to obtain the MPIDR_EL1 directly. This change removes the mpidr parameter from the bakery lock interface, and results in a code reduction of 160 bytes for the ARM FVP port. Fixes ARM-software/tf-issues#213 Change-Id: I7ec7bd117bcc9794a0d948990fcf3336a367d543
* Split platform.h into separate headersDan Handley2014-05-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | Previously, platform.h contained many declarations and definitions used for different purposes. This file has been split so that: * Platform definitions used by common code that must be defined by the platform are now in platform_def.h. The exact include path is exported through $PLAT_INCLUDES in the platform makefile. * Platform definitions specific to the FVP platform are now in /plat/fvp/fvp_def.h. * Platform API declarations specific to the FVP platform are now in /plat/fvp/fvp_private.h. * The remaining platform API declarations that must be ported by each platform are still in platform.h but this file has been moved to /include/plat/common since this can be shared by all platforms. Change-Id: Ieb3bb22fbab3ee8027413c6b39a783534aee474a
* Reduce deep nesting of header filesDan Handley2014-05-061-3/+2
| | | | | | | | | | | | | | Reduce the number of header files included from other header files as much as possible without splitting the files. Use forward declarations where possible. This allows removal of some unnecessary "#ifndef __ASSEMBLY__" statements. Also, review the .c and .S files for which header files really need including and reorder the #include statements alphabetically. Fixes ARM-software/tf-issues#31 Change-Id: Iec92fb976334c77453e010b60bcf56f3be72bd3e
* Always use named structs in header filesDan Handley2014-05-061-4/+4
| | | | | | | | | | | | | | | | | Add tag names to all unnamed structs in header files. This allows forward declaration of structs, which is necessary to reduce header file nesting (to be implemented in a subsequent commit). Also change the typedef names across the codebase to use the _t suffix to be more conformant with the Linux coding style. The coding style actually prefers us not to use typedefs at all but this is considered a step too far for Trusted Firmware. Also change the IO framework structs defintions to use typedef'd structs to be consistent with the rest of the codebase. Change-Id: I722b2c86fc0d92e4da3b15e5cab20373dd26786f
* Move include and source files to logical locationsDan Handley2014-05-062-0/+243
Move almost all system include files to a logical sub-directory under ./include. The only remaining system include directories not under ./include are specific to the platform. Move the corresponding source files to match the include directory structure. Also remove pm.h as it is no longer used. Change-Id: Ie5ea6368ec5fad459f3e8a802ad129135527f0b3
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