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* Neoverse N1: Forces cacheable atomic to nearLouis Mayencourt2019-04-181-0/+6
| | | | | | | | This patch forces all cacheable atomic instructions to be near, which improves performance in highly contended parallelized use-cases. Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* DSU: Implement workaround for errata 798953Louis Mayencourt2019-04-175-1/+78
| | | | | | | | | Under certain near idle conditions, DSU may miss response transfers on the ACE master or Peripheral port, leading to deadlock. This workaround disables high-level clock gating of the DSU to prevent this. Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* DSU: Small fix and reformat on errata frameworkLouis Mayencourt2019-04-171-22/+22
| | | | | Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* Cortex-A35: Implement workaround for errata 855472Louis Mayencourt2019-04-172-2/+57
| | | | | | | | | Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* Cortex A9:errata 794073 workaroundJoel Hutton2019-04-122-0/+17
| | | | | | | | | | | | | On Cortex A9 an errata can cause the processor to violate the rules for speculative fetches when the MMU is off but branch prediction has not been disabled. The workaround for this is to execute an Invalidate Entire Branch Prediction Array (BPIALL) followed by a DSB. see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf for more details. Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93 Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
* Add support for Cortex-A76AE CPUAlexei Fedorov2019-04-081-0/+56
| | | | | Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Merge pull request #1887 from ambroise-arm/av/a76-cveDimitris Papastamos2019-03-201-13/+16
|\ | | | | Cortex-A76: Optimize CVE_2018_3639 workaround
| * Cortex-A76: Optimize CVE_2018_3639 workaroundAmbroise Vincent2019-03-141-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Switched from a static check to a runtime assert to make sure a workaround is implemented for CVE_2018_3639. This allows platforms that know they have the SSBS hardware workaround in the CPU to compile out code under DYNAMIC_WORKAROUND_CVE_2018_3639. The gain in memory size without the dynamic workaround is 4KB in bl31. Change-Id: I61bb7d87c59964b0c7faac5d6bc7fc5c4651cbf3 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * Cortex-A76: fix spellingAmbroise Vincent2019-03-141-6/+6
| | | | | | | | | | Change-Id: I6adf7c14e8a974a7d40d51615b5e69eab1a7436f Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Merge pull request #1888 from jts-arm/zeusDimitris Papastamos2019-03-151-0/+60
|\ \ | | | | | | Introduce preliminary support for Neoverse Zeus
| * | Introduce preliminary support for Neoverse ZeusJohn Tsichritzis2019-03-141-0/+60
| |/ | | | | | | | | Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* / Apply variant 4 mitigation for Neoverse N1John Tsichritzis2019-03-141-0/+4
|/ | | | | | | | | This patch applies the new MSR instruction to directly set the PSTATE.SSBS bit which controls speculative loads. This new instruction is available at Neoverse N1 core so it's utilised. Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Cortex-A17: Implement workaround for errata 852423Ambroise Vincent2019-03-132-0/+44
| | | | | Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Cortex-A17: Implement workaround for errata 852421Ambroise Vincent2019-03-132-1/+47
| | | | | Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Cortex-A15: Implement workaround for errata 827671Ambroise Vincent2019-03-132-0/+47
| | | | | | | | | | This erratum can only be worked around on revisions >= r3p0 because the register that needs to be accessed only exists in those revisions[1]. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Cortex-A15: Implement workaround for errata 816470Ambroise Vincent2019-03-132-1/+31
| | | | | Change-Id: I9755252725be25bfd0147839d7df56888424ff84 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Fixup register handling in aarch32 reset_handlerHeiko Stuebner2019-03-081-3/+3
| | | | | | | | | | | | | | | | The BL handover interface stores the bootloader arguments in registers r9-r12, so when the reset_handler stores the lr pointer in r10 it clobers one of the arguments. Adapt to use r8 and adapt the comment about registers allowed to clober. I've checked aarch32 reset_handlers and none seem to use higher registers as far as I can tell. Fixes: a6f340fe58b9 ("Introduce the new BL handover interface") Cc: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* Merge pull request #1751 from vwadekar/tegra-scatter-file-supportAntonio Niño Díaz2019-03-012-2/+4
|\ | | | | Tegra scatter file support
| * Tegra: Support for scatterfile for the BL31 imageVarun Wadekar2019-02-272-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support for using the scatterfile format as the linker script with the 'armlink' linker for Tegra platforms. In order to enable the scatterfile usage the following changes have been made: * provide mapping for ld.S symbols in bl_common.h * include bl_common.h from all the affected files * update the makefile rules to use the scatterfile and armlink to compile BL31 * update pubsub.h to add sections to the scatterfile NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY. Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Merge pull request #1849 from loumay-arm/lm/a73_errataAntonio Niño Díaz2019-03-012-0/+44
|\ \ | | | | | | Cortex-A73: Implement workaround for errata 852427
| * | Cortex-A73: Implement workaround for errata 852427Louis Mayencourt2019-02-282-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | In AArch32, execution of 2 instructions with opposite condition code might lead to either a data corruption or a CPU deadlock. Set the bit 12 of the Diagnostic Register to prevent this. Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | Merge pull request #1845 from ambroise-arm/av/errataAntonio Niño Díaz2019-03-016-5/+488
|\ \ \ | |/ / |/| | Apply workarounds for errata of Cortex-A53, A55 and A57
| * | Cortex-A53: Workarounds for 819472, 824069 and 827319Ambroise Vincent2019-02-283-2/+122
| | | | | | | | | | | | | | | | | | | | | | | | The workarounds for these errata are so closely related that it is better to only have one patch to make it easier to understand. Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A57: Implement workaround for erratum 817169Ambroise Vincent2019-02-283-0/+52
| | | | | | | | | | | | | | | Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A57: Implement workaround for erratum 814670Ambroise Vincent2019-02-283-2/+79
| | | | | | | | | | | | | | | Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A55: Implement workaround for erratum 903758Ambroise Vincent2019-02-282-0/+42
| | | | | | | | | | | | | | | Change-Id: I07e69061ba7a918cdfaaa83fa3a42dee910887d7 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A55: Implement workaround for erratum 846532Ambroise Vincent2019-02-282-0/+46
| | | | | | | | | | | | | | | Change-Id: Iacb6331c1f6b27340e71279f92f147ebbc71862f Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A55: Implement workaround for erratum 798797Ambroise Vincent2019-02-282-0/+42
| | | | | | | | | | | | | | | Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A55: Implement workaround for erratum 778703Ambroise Vincent2019-02-282-0/+57
| | | | | | | | | | | | | | | Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A55: Implement workaround for erratum 768277Ambroise Vincent2019-02-282-1/+48
| |/ | | | | | | | | Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Add workaround for errata 1073348 for Cortex-A76Louis Mayencourt2019-02-262-0/+42
| | | | | | | | | | | | | | | | | | Concurrent instruction TLB miss and mispredicted return instruction might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to prevent this. Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Add workaround for errata 1220197 for Cortex-A76Louis Mayencourt2019-02-262-0/+44
| | | | | | | | | | | | | | | | | | Streaming store under specific conditions might cause deadlock or data corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write streaming to the L2 to prevent this. Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Add workaround for errata 1130799 for Cortex-A76Louis Mayencourt2019-02-262-1/+48
| | | | | | | | | | | | | | | | | | | | TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page aggregated address translation data in the L2 TLB might cause corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to prevent this. Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Add workaround for errata 790748 for Cortex-A75Louis Mayencourt2019-02-262-0/+44
| | | | | | | | | | | | | | | | Internal timing conditions might cause the CPU to stop processing interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this. Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Add workaround for errata 764081 of Cortex-A75Louis Mayencourt2019-02-262-1/+48
| | | | | | | | | | | | | | | | | | Implicit Error Synchronization Barrier (IESB) might not be correctly generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all expection levels. Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Add workaround for errata 855423 of Cortex-A73Louis Mayencourt2019-02-262-2/+51
|/ | | | | | | | Broadcast maintainance operations might not be correctly synchronized between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this. Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* Rename Cortex-Helios to Neoverse E1John Tsichritzis2019-02-191-18/+18
| | | | | Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Rename Cortex-Helios filenames to Neoverse E1John Tsichritzis2019-02-191-0/+0
| | | | | Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Rename Cortex-Ares to Neoverse N1John Tsichritzis2019-02-193-48/+48
| | | | | Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Rename Cortex-Ares filenames to Neoverse N1John Tsichritzis2019-02-192-0/+0
| | | | | Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Sanitise includes across codebaseAntonio Nino Diaz2019-01-0420-33/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* AArch64: Use SSBS for CVE_2018_3639 mitigationJeenu Viswambharan2018-12-101-2/+11
| | | | | | | | | | | | | | | | | | | | | | | The Armv8.5 extensions introduces PSTATE.SSBS (Speculation Store Bypass Safe) bit to mitigate against Variant 4 vulnerabilities. Although an Armv8.5 feature, this can be implemented by CPUs implementing earlier version of the architecture. With this patch, when both PSTATE.SSBS is implemented and DYNAMIC_WORKAROUND_CVE_2018_3639 is active, querying for SMCCC_ARCH_WORKAROUND_2 via. SMCCC_ARCH_FEATURES call would return 1 to indicate that mitigation on the PE is either permanently enabled or not required. When SSBS is implemented, SCTLR_EL3.DSSBS is initialized to 0 at reset of every BL stage. This means that EL3 always executes with mitigation applied. For Cortex A76, if the PE implements SSBS, the existing mitigation (by using a different vector table, and tweaking CPU ACTLR2) is not used. Change-Id: Ib0386c5714184144d4747951751c2fc6ba4242b6 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Fix MISRA defects in workaround and errata frameworkAntonio Nino Diaz2018-10-293-9/+14
| | | | | | | No functional changes. Change-Id: Iaab0310848be587b635ce5339726e92a50f534e0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Fix MISRA defects in extension libsAntonio Nino Diaz2018-10-291-2/+2
| | | | | | | No functional changes. Change-Id: I2f28f20944f552447ac4e9e755493cd7c0ea1192 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Make errata reporting mandatory for CPU filesSoby Mathew2018-10-299-0/+84
| | | | | | | | | | | | | Previously the errata reporting was optional for CPU operation files and this was achieved by making use of weak reference to resolve to 0 if the symbol is not defined. This is error prone when adding new CPU operation files and weak references are problematic when fixing up dynamic relocations. Hence this patch removes the weak reference and makes it mandatory for the CPU operation files to define the errata reporting function. Change-Id: I8af192e19b85b7cd8c7579e52f8f05a4294e5396 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* ti: k3: common: Do not disable cache on TI K3 core powerdownAndrew F. Davis2018-10-161-0/+4
| | | | | | | | | Leave the caches on and explicitly flush any data that may be stale when the core is powered down. This prevents non-coherent interconnect access which has negative side- effects on AM65x. Signed-off-by: Andrew F. Davis <afd@ti.com>
* Fix the Cortex-ares errata reporting function nameSoby Mathew2018-09-101-2/+2
| | | | | | | | This patch fixes the name of the Cortex-ares errata function which was previously named `cortex_a72_errata_report` which was an error. Change-Id: Ia124df4628261021baa8d9a30308bc286d45712b Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* cpus: denver: Implement static workaround for CVE-2018-3639Varun Wadekar2018-09-041-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Denver CPUs, this approach enables the mitigation during EL3 initialization, following every PE reset. No mechanism is provided to disable the mitigation at runtime. This approach permanently mitigates the EL3 software stack only. Other software components are responsible to enable it for their exception levels. TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN3 and earlier: * By setting bit 11 (Disable speculative store buffering) of `ACTLR_EL3` * By setting bit 9 (Disable speculative memory disambiguation) of `ACTLR_EL3` TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN4 and later: * By setting bit 18 (Disable speculative store buffering) of `ACTLR_EL3` * By setting bit 17 (Disable speculative memory disambiguation) of `ACTLR_EL3` Change-Id: If1de96605ce3f7b0aff5fab2c828e5aecb687555 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* cpus: denver: reset power state to 'C1' on bootVarun Wadekar2018-09-041-0/+9
| | | | | | | | | Denver CPUs expect the power state field to be reset to 'C1' during boot. This patch updates the reset handler to reset the ACTLR_.PMSTATE field to 'C1' state during CPU boot. Change-Id: I7cb629627a4dd1a30ec5cbb3a5e90055244fe30c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* denver: use plat_my_core_pos() to get core positionVarun Wadekar2018-09-041-4/+7
| | | | | | | | | | | | | | | The current functions to disable and enable Dynamic Code Optimizer (DCO) assume that all denver cores are in the same cluster. They ignore AFF1 field of the mpidr_el1 register, which leads to incorect logical core id calculation. This patch calls the platform handler, plat_my_core_pos(), to get the logical core id to disable/enable DCO for the core. Original change by: Krishna Sitaraman <ksitaraman@nvidia.com> Change-Id: I45fbd1f1eb032cc1db677a4fdecc554548b4a830 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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