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* Sanitise includes across codebaseAntonio Nino Diaz2019-01-0424-68/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* plat/arm: Always define TSP memory regionAntonio Nino Diaz2019-01-041-2/+0
| | | | | | | | | Even though this is not used unless SPD=tspd, only defining it when SPD_tspd is defined doesn't have any advantage and it makes it harder to read the code. Change-Id: I3d93135e05f39be071d16f8a47394a9a3ff54bc8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* FVP: Change BL31_BASE when RESET_TO_BL31=1Soby Mathew2018-12-171-4/+8
| | | | | | | | | This patch defines BL31_BASE to 0x0 when RESET_TO_BL31=1 as the executable is built with PIE support and can be loaded anywhere in SRAM for execution. Change-Id: I4007f4626322f1200a6304c9c565987d3357986c Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* SPM: Implement global response buffer helpersAntonio Nino Diaz2018-12-111-0/+1
| | | | | | | | This buffer is where all the responses from Secure Partitions are stored until they are requested. Change-Id: Iafeb8f0848c5ff6f3e187060cd3a47702484dc45 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* SPM: Implement SPCI open/close handle SMCsAntonio Nino Diaz2018-12-111-0/+2
| | | | | | | | Introduce SMCs that open and close handles according to the SPCI specification. Change-Id: I65f365f15612e01aa445e783e96e48ae275c39fd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* SPM: Support multiple partitionsAntonio Nino Diaz2018-12-111-0/+2
| | | | | Change-Id: I6673a5f8c2f6afa7780483e0ce8d4dad4c8dc8ea Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* SPM: Load image and RD from SP packageAntonio Nino Diaz2018-12-112-2/+27
| | | | | | | | Load SP and RD from package instead of relying on RD being already loaded in memory and the SP being loaded as a BL32 image. Change-Id: I18d4fbf4597656c6a7e878e1d7c01a8a324f3f8a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* SPM: Remove SP memory mappings definitionsAntonio Nino Diaz2018-12-102-1/+6
| | | | | | | | This information is retrieved from the resource description now. Change-Id: Iaae23945eb2c45305cdc6442853e42f4e04fe094 Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* SPM: Introduce functions to load DTB filesAntonio Nino Diaz2018-12-102-0/+10
| | | | | | | | Introduce helpers to create resource description struct, as well as code to load the information from DTB files. Change-Id: I0f5bb94eb8b01c6cb53fe807a9db0c05a70d7a43 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* plat/arm/common: add an additional platform power levelChandni Cherukuri2018-11-271-0/+1
| | | | | | | | | | | For platforms using multi-threaded CPUs, there can be upto four platform power domain levels. At present, there are three platform power domain levels that are defined for the CSS platforms. Define a fourth level 'ARM_PWR_LVL3' as well to provide support for an additional platform power domain level. Change-Id: I40cc17a10f4690a560776f504364fd7277a7e72a Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* plat/css: allow platforms to define the system power domain levelChandni Cherukuri2018-11-271-3/+0
| | | | | | | | | | | | | | | The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the system power domain level can be different for CSS platforms that use multi-threaded CPUs. So, in preparation towards adding support for platforms that use multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the CSS platform. Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* plat/marvell: Migrate to multi-console APIKonstantin Porotchkin2018-11-152-0/+12
| | | | | | | | Migrate Marvell platforms from legacy console API to multi-console API. Change-Id: I647f5f49148b463a257a747af05b5f0c967f267c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* Standardise header guards across codebaseAntonio Nino Diaz2018-11-0825-80/+76
| | | | | | | | | | | | | | | | | | All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Arm platforms: Fix DRAM address macrosSandrine Bailleux2018-11-071-2/+2
| | | | | | | | | | | | | | | On AArch32, ARM_DRAM1_BASE and ARM_DRAM1_SIZE constants are currently 32-bit values (because they are suffixed with UL and the value 0x80000000 fits in a unsigned long int, i.e. a 32-bit value). When summing them up, the result overflows the maximum value that can be encoded in a 32-bit value so it wraps around and does not result in the expected value. This patch changes the suffix of these constants into ULL so that they always are 64-bit values. Change-Id: I3b19b1805e35cc7e43050458df379081b1e882d5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* plat/arm: Fix MISRA defects in dyn configAntonio Nino Diaz2018-11-011-3/+3
| | | | | Change-Id: Iae6758ca6395560131d1e1a69a1ecfe50ca8bf83 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* plat/arm: Fix types of constants in headersAntonio Nino Diaz2018-11-012-29/+29
| | | | | Change-Id: I33eaee8e7c983b3042635a448cb8d689ea4e3a12 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1623 from MISL-EBU-System-SW/a3700-supportAntonio Niño Díaz2018-11-017-5/+372
|\ | | | | Add support for Armada 3700 and COMPHY porting layer
| * plat: marvell: Add support for Armada-37xx SoC platformKonstantin Porotchkin2018-10-316-3/+370
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add supprot for Marvell platforms based on Armada-37xx SoC. This includes support for the official Armada-3720 modular development board and EspressoBin community board. The Armada-37xx SoC contains dual Cortex-A53 Application CPU, single secure CPU (Cortex-M3) and the following interfaces: - SATA 3.0 - USB 3.0 and USB 2.0 - PCIe - SDIO (supports boot from eMMC) - SPI - UART - I2c - Gigabit Ethernet Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * plat: marvell: Fix the wrong include protectorKonstantin Porotchkin2018-10-181-2/+2
| | | | | | | | | | | | Fix the include protector to be in sync with file name Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* | Merge pull request #1650 from chandnich/sgiclark-ares-supportAntonio Niño Díaz2018-10-311-0/+7
|\ \ | | | | | | Sgiclark ares support
| * | plat/arm/css: Add SID registers for SGx platformsChandni Cherukuri2018-10-261-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Some of the SGx platforms use System Identification (SID) registers for platform identification. Add support for these registers in css. Change-Id: If00b18744a31ff2cf14338f18c8c680eb69c9027 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | plat/arm: Fix MISRA defects in SiP SVC handlerAntonio Nino Diaz2018-10-292-14/+16
| | | | | | | | | | | | | | | | | | | | | No functional changes. Change-Id: I9b9f8d3dfde08d57706ad5450de6ff858a55ac01 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Convert arm_setup_page_tables into a generic helperRoberto Vargas2018-10-261-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This function is not related to Arm platforms and can be reused by other platforms if needed. Change-Id: Ia9c328ce57ce7e917b825a9e09a42b0abb1a53e8 Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | xlat: Fix compatibility between v1 and v2Antonio Nino Diaz2018-10-263-14/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several platforms using arm_setup_page_tables(), which is supposed to be Arm platform only. This creates several dependency problems between platforms. This patch adds the definition XLAT_TABLES_LIB_V2 to the xlat tables lib v2 makefile. This way it is possible to detect from C code which version is being used and include the correct header. The file arm_xlat_tables.h has been renamed to xlat_tables_compat.h and moved to a common folder. This way, when in doubt, this header can be used to guarantee compatibility, as it includes the correct header based on XLAT_TABLES_LIB_V2. This patch also removes the usage of ARM_XLAT_TABLES_V1 from QEMU (so that is now locked in xlat lib v2) and ZynqMP (where it was added as a workaround). Change-Id: Ie1e22a23b44c549603d1402a237a70d0120d3e04 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* / tzc: Fix MISRA defectsAntonio Nino Diaz2018-10-232-16/+16
|/ | | | | | | | | | | | | | The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been fixed. The types tzc_region_attributes_t and tzc_action_t have been removed and replaced by unsigned int because it is not allowed to do logical operations on enums. Also, fix some address definitions in arm_def.h. Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1629 from robertovargas-arm/hw-assisted-coherency-lockSoby Mathew2018-10-181-0/+9
|\ | | | | Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled
| * scmi: Optimize bakery locks when HW_ASSISTED_COHERENCY is enabledRoberto Vargas2018-10-161-0/+9
| | | | | | | | | | | | | | | | When HW_ASSISTED_COHERENCY is enabled we can use spinlocks instead of using the more complex and slower bakery algorithm. Change-Id: I9d791a70050d599241169b9160a67e57d5506564 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | Merge pull request #1628 from antonio-nino-diaz-arm/an/sharingSoby Mathew2018-10-183-63/+17
|\ \ | |/ |/| plat/arm: Small reorganization of platform code
| * plat/arm: Remove file arm_board_def.hAntonio Nino Diaz2018-10-113-63/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This file is shared between FVP and all CSS platforms. While it may be true that some definitions can be common, it doesn't make sense conceptually. For example, the stack size depends on the platform and so does the SRAM size. After removing them, there are not enough common definitions to justify having this header, so the other definitions have been moved to the platform_def.h of FVP, board_css_def.h and arm_def.h. Change-Id: Ifbf4b017227f9dfefa1a430f67d7d6baae6a4ba1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1619 from antonio-nino-diaz-arm/an/norflashSoby Mathew2018-10-111-46/+0
|\ \ | | | | | | plat/arm: Move norflash driver to drivers/ folder
| * | plat/arm: Move norflash driver to drivers/ folderAntonio Nino Diaz2018-10-101-46/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | This way it can be reused by other platforms if needed. Note that this driver is designed to work with the Versatile Express NOR flash of Juno and FVP. In said platforms, the memory is organized as an interleaved memory of two chips with a 16 bit word. Any platform that wishes to reuse it with a different configuration will need to modify the driver so that it is more generic. Change-Id: Ic721758425864e0cf42b7b9b04bf0d9513b6022e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1614 from MISL-EBU-System-SW/integration-fixSoby Mathew2018-10-101-0/+2
|\ \ | | | | | | Fix service CPU image load at BL2 stage and update maintainers list
| * | plat: marvell: invoke platform specific scp_bl2 image handlerGrzegorz Jaszczyk2018-10-071-0/+2
| |/ | | | | | | | | | | | | | | Before switching to new API the scp_bl2 handler was invoked from bl2/bl2_image_load.c which was removed. Invoke the platform specific scp_bl2 handler in analogy to ARM and HiSilicon. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
* / Fix misra warnings in SMC and power mgmt codeSathees Balya2018-10-091-24/+24
|/ | | | | Change-Id: Ia00eba2b18804e6498d935d33ec104953e0e5e03 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
* Remove some MISRA defects in common codeAntonio Nino Diaz2018-10-041-4/+5
| | | | | | | No functional changes. Change-Id: I9638e02acb9b22eb794ebf45aad84348a710287e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* FVP: Reclaim init code for the stackDaniel Boulby2018-10-034-4/+46
| | | | | | | | | | | | | | | | Map the initialization code for BL31 to overlap with the memory required for the secondary cores stack. Once BL31 has been initialized the memory can be remapped to RW data so that it can be used for secondary cores stacks. By moving code from .text to .text.init the size of the BL31 image is decreased by a page. Split arm_common.ld.S into two linker scripts, one for tzc_dram (arm_tzc_dram.ld.S) and one for reclaiming initialization code (arm_reclaim_init.ld.S) so that platforms can chose which memory regions they wish to include. Change-Id: I648e88f3eda1aa71765744cf34343ecda9320b32 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* plat/arm: Remove option ARM_BOARD_OPTIMISE_MEMAntonio Nino Diaz2018-10-021-85/+0
| | | | | | | | | | | | | | | This option makes it hard to optimize the memory definitions of all Arm platforms because any change in the common defines must work in all of them. The best thing to do is to remove it and move the definition to each platform's header. FVP, SGI and SGM were using the definitions in board_arm_def.h. The definitions have been copied to each platform's platform_def.h. Juno was already using the ones in platform_def.h, so there have been no changes. Change-Id: I9aecd11bbc72a3d0d7aad1ef9934d8df21dcfaf2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* marvell: Migrate to new interfacesAntonio Nino Diaz2018-09-282-4/+11
| | | | | | | | | | | - Migrate to bl2_early_platform_setup2(). - Remove references to removed build options. - Use private definition of bl31_params_t. This is an incomplete migration, the platform doesn't currently compile. Change-Id: I1ae477b1f2489f49b651528050fdf06e4a55e425 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* plat/arm: Migrate to new interfacesAntonio Nino Diaz2018-09-282-23/+0
| | | | | | | | | - Remove references to removed build options. - Remove support for legacy GIC driver. - Remove support for LOAD_IMAGE_V2=0. Change-Id: I72f8c05620bdf4a682765e6e53e2c04ca749a3d5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Remove all other deprecated interfaces and filesAntonio Nino Diaz2018-09-281-1/+0
| | | | | Change-Id: Icd1cdd42afdc78895a9be6c46b414b0a155cfa63 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Remove deprecated bl1_init_bl2_mem_layout()Antonio Nino Diaz2018-09-281-4/+0
| | | | | Change-Id: I8ec8b4439ca1d7606aae069c2c576a9a8b18c92c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Remove deprecated early platform setup interfacesAntonio Nino Diaz2018-09-281-7/+0
| | | | | | | | The affected interfaces are bl31_early_platform_setup(), sp_min_early_platform_setup() and bl2_early_platform_setup(). Change-Id: I50c01ec68bcbe97fe4e5d101bcd0f763358b8e1e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Remove build option LOAD_IMAGE_V2Roberto Vargas2018-09-282-81/+0
| | | | | | | | The code of LOAD_IMAGE_V2=0 has been removed. Change-Id: Iea03e5bebb90c66889bdb23f85c07d0c9717fffe Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* PSCI: Remove platform compatibility layerRoberto Vargas2018-09-281-23/+0
| | | | | | Change-Id: I40d040aa05bcbf11536a96ce59827711456b93a8 Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1565 from satheesbalya-arm/sb1_2332_fwu_sds_registerDimitris Papastamos2018-09-072-0/+5
|\ | | | | juno: Revert FWU update detect mechanism
| * juno: Revert FWU update detect mechanismSathees Balya2018-09-072-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch 7b56928 unified the FWU mechanism on FVP and Juno platforms due to issues with MCC firmware not preserving the NVFLAGS. With MCCv150 firmware, this issue is resolved. Also writing to the NOR flash while executing from the same flash in Bypass mode had some stability issues. Hence, since the MCC firmware issue is resolved, this patch reverts to the NVFLAGS mechanism to detect FWU. Also, with the introduction of SDS (Shared Data Structure) by the SCP, the reset syndrome needs to queried from the appropriate SDS field. Change-Id: If9c08f1afaaa4fcf197f3186887068103855f554 Signed-off-by: Sathees Balya <sathees.balya@arm.com> Signed-off-by: Soby Mathew <Soby.Mathew@arm.com>
* | Readjust BL2 size after sharing Mbed TLS heapJohn Tsichritzis2018-09-071-1/+1
|/ | | | | | | | | After introducing the Mbed TLS shared heap optimisation, reducing BL2 size by 3 pages didn't leave enough space for growth. We give 1 page back to maximum BL2 size. Change-Id: I4f05432f00b923693160f69a4e4ec310a37a2b16 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Merge pull request #1554 from jts-arm/mbedDimitris Papastamos2018-09-055-2/+21
|\ | | | | Mbed TLS shared heap
| * Reduce BL2 size for FVPJohn Tsichritzis2018-09-041-1/+1
| | | | | | | | | | | | | | | | | | This patch reduces BL2 size by 12kB. Thanks to the shared Mbed TLS heap between BL1 and BL2, BL2 now requires less memory since it doesn't need to allocate a heap anymore. Change-Id: I58a15f8c424273650c9f55112abe88105b6cdbae Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
| * Support shared Mbed TLS heap for FVPJohn Tsichritzis2018-09-043-1/+19
| | | | | | | | | | | | | | | | | | | | | | This patch introduces the shared Mbed TLS heap optimisation for Arm platforms. The objective is the Mbed TLS heap to be shared between BL1 and BL2 so as to not allocate the heap memory twice. To achieve that, the patch introduces all the necessary helpers for implementing this optimisation. It also applies it for FVP. Change-Id: I6d85eaa1361517b7490956b2ac50f5fa0d0bb008 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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