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* Merge pull request #1145 from etienne-lms/rfc-armv7-2davidcunado-arm2017-11-231-1/+13
|\ | | | | Support ARMv7 architectures
| * ARMv7: GICv2 driver can manage GICv1 with security extensionEtienne Carriere2017-11-081-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SoCs integrate a GIC in version 1 that is currently not supported by the trusted firmware. This change hijacks GICv2 driver to handle the GICv1 as GICv1 is compatible enough with GICv2 as far as the platform does not attempt to play with virtualization support or some GICv2 specific power features. Note that current trusted firmware does not use these GICv2 features that are not available in GICv1 Security Extension. Change-Id: Ic2cb3055f1319a83455571d6d918661da583f179 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* | tbbr: Add build flag HASH_ALG to let the user to select the SHAQixiang Xu2017-11-213-3/+26
| | | | | | | | | | | | | | | | | | | | The flag support the following values: - sha256 (default) - sha384 - sha512 Change-Id: I7a49d858c361e993949cf6ada0a86575c3291066 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
* | GIC: Fix Group 0 enablingJeenu Viswambharan2017-11-134-6/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | At present, the GIC drivers enable Group 0 interrupts only if there are Secure SPIs listed in the interrupt properties/list. This means that, even if there are Group 0 SGIs/PPIs configured, the group remained disabled in the absence of a Group 0 SPI. Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when corresponding SGIs/PPIs are present. Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | GICv2: Fix populating PE target dataJeenu Viswambharan2017-11-131-3/+20
|/ | | | | | | | | | | | | This patch brings in the following fixes: - The per-PE target data initialized during power up needs to be flushed so as to be visible to other PEs. - Setup per-PE target data for the primary PE as well. At present, this was only setup for secondary PEs when they were powered on. Change-Id: Ibe3a57c14864e37b2326dd7ab321a5c7bf80e8af Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Allow specifying interrupt propertiesJeenu Viswambharan2017-10-166-59/+356
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC driver initialization currently allows an array of interrupts to be configured as secure. Future use cases would require more interrupt configuration other than just security, such as priority. This patch introduces a new interrupt property array as part of both GICv2 and GICv3 driver data. The platform can populate the array with interrupt numbers and respective properties. The corresponding driver initialization iterates through the array, and applies interrupt configuration as required. This capability, and the current way of supplying array (or arrays, in case of GICv3) of secure interrupts, are however mutually exclusive. Henceforth, the platform should supply either: - A list of interrupts to be mapped as secure (the current way). Platforms that do this will continue working as they were. With this patch, this scheme is deprecated. - A list of interrupt properties (properties include interrupt group). Individual interrupt properties are specified via. descriptors of type 'interrupt_prop_desc_t', which can be populated with the macro INTR_PROP_DESC(). A run time assert checks that the platform doesn't specify both. Henceforth the old scheme of providing list of secure interrupts is deprecated. When built with ERROR_DEPRECATED=1, GIC drivers will require that the interrupt properties are supplied instead of an array of secure interrupts. Add a section to firmware design about configuring secure interrupts. Fixes ARM-software/tf-issues#262 Change-Id: I8eec29e72eb69dbb6bce77879febf32c95376942 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add helpers to set interrupt configurationJeenu Viswambharan2017-10-163-0/+45
| | | | | | | | | The helpers perform read-modify-write on GIC*_ICFGR registers, but don't serialise callers. Any serialisation must be taken care of by the callers. Change-Id: I71995f82ff2c7f70d37af0ede30d6ee18682fd3f Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add API to set priority maskJeenu Viswambharan2017-10-162-0/+46
| | | | | | | API documentation updated. Change-Id: I40feec1fe67a960d035061b54dd55610bc34ce1d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add API to set/clear interrupt pendingJeenu Viswambharan2017-10-164-0/+119
| | | | | | | | API documentation updated. Change-Id: I14e33cfc7dfa93257c82d76fae186b17a1b6d266 Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add API to set interrupt routingJeenu Viswambharan2017-10-164-10/+85
| | | | | | | | | | | SPIs can be routed to either a specific PE, or to any one of all available PEs. API documentation updated. Change-Id: I28675f634568aaf4ea1aa8aa7ebf25b419a963ed Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add API to raise secure SGIJeenu Viswambharan2017-10-163-0/+82
| | | | | | | API documentation updated. Change-Id: I129725059299af6cc612bafa8d74817f779d7c4f Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add APIs to set interrupt type and query supportJeenu Viswambharan2017-10-162-0/+101
| | | | | | | | | | | | | | | | | | | | | | | The back end GIC driver converts and assigns the interrupt type to suitable group. For GICv2, a build option GICV2_G0_FOR_EL3 is introduced, which determines to which type Group 0 interrupts maps to. - When the build option is set 0 (the default), Group 0 interrupts are meant for Secure EL1. This is presently the case. - Otherwise, Group 0 interrupts are meant for EL3. This means the SPD will have to synchronously hand over the interrupt to Secure EL1. The query API allows the platform to query whether the platform supports interrupts of a given type. API documentation updated. Change-Id: I60fdb4053ffe0bd006b3b20914914ebd311fc858 Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add API to set interrupt priorityJeenu Viswambharan2017-10-162-0/+36
| | | | | | | | API documentation updated. Change-Id: Ib700eb1b8ca65503aeed0ac4ce0e7b934df67ff9 Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add APIs to enable and disable interruptJeenu Viswambharan2017-10-164-0/+110
| | | | | | | | API documentation updated. Change-Id: Ice7511f8df5356851001d2f7dc2a46cfe318f9ba Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add API to get interrupt active statusJeenu Viswambharan2017-10-166-3/+65
| | | | | | | | API documentation updated. Change-Id: I6d61785af0d5330930c709de971a904dc7c3516c Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GICv2: Add driver API to set PE target maskJeenu Viswambharan2017-10-161-0/+23
| | | | | | | | | | | | | | | | | | | | | The PE target mask is used to translate linear PE index (returned by platform core position) to a bit mask used when targeting interrupts to a PE, viz. when raising SGIs and routing SPIs. The platform shall: - Populate the driver data with a pointer to array that's to contain per-PE target masks. - Invoke the new driver API 'gicv2_set_pe_target_mask()' during per-CPU initialization so that the driver populates the target mask for that CPU. Platforms that don't intend to target interrupts or raise SGIs need not populate this. Change-Id: Ic0db54da86915e9dccd82fff51479bc3c1fdc968 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* GIC: Add API to get running priorityJeenu Viswambharan2017-10-163-1/+27
| | | | | | | | Document the API in separate platform interrupt controller API document. Change-Id: If18f208e10a8a243f5c59d226fcf48e985941949 Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Fix assertion in GIC ITS helperSoby Mathew2017-10-061-1/+1
| | | | | | | This patch fixes an assertion check in the GICv3 ITS helper function. Change-Id: I75f50d7bf6d87c12c6e24a07c9a9889e5facf4a5 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* GICv3: ITS architectural save and restore helpersSoby Mathew2017-10-052-0/+124
| | | | | | | | | | | | | | | | | This patch adds functions to save and restore GICv3 ITS registers during system suspend. Please note that the power management of GIC ITS is implementation defined. These functions only implements the architectural part of the ITS power management and they do not restore memory structures or register content required to support ITS. Even if the ITS implementation stores structures in memory, an implementation defined power down sequence is likely to be required to flush some internal ITS caches to memory. If such implementation defined sequence is not followed, the platform must ensure that the ITS is not power gated during system suspend. Change-Id: I5f31e5541975aa7dcaab69b0b7f67583c0e27678 Signed-off-by: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
* GICv3: add functions for save and restoreSoby Mathew2017-10-055-3/+513
| | | | | | | | | | | | | | | | | | | | | During system suspend, the GICv3 Distributor and Redistributor context can be lost due to power gating of the system power domain. This means that the GICv3 context needs to be saved prior to system suspend and restored on wakeup. Currently the consensus is that the Firmware should be in charge of this. See tf-issues#464 for more details. This patch introduces helper APIs in the GICv3 driver to save and restore the Distributor and Redistributor contexts. The GICv3 ITS context is not considered in this patch because the specification says that the details of ITS power management is implementation-defined. These APIs are expected to be appropriately invoked by the platform layer during system suspend. Fixes ARM-software/tf-issues#464 Change-Id: Iebb9c6770ab8c4d522546f161fa402d2fe02ec00 Signed-off-by: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
* GICv3: turn some macros into inline functionsDouglas Raillard2017-10-051-23/+25
| | | | | | | | | Tidy up the code a bit by turning some macros into inline functions which allows to remove the do/while(0) idiom and backslashes at the end of the line. Change-Id: Ie41a4ea4a4da507f7b925247b53e85019101d717 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
* GICv3: Fix gic600.c indentationDouglas Raillard2017-10-051-7/+7
| | | | | | | | | Reindent the file using tabs as the mix of spaces and tabs confuses some editors and leads them to use spaces instead of tabs for new code although the coding style mandates tabs. Change-Id: I87fa4a5d368a048340054b9b3622325f3f7befba Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
* Merge pull request #1107 from geesun/qx/add_ecdsa_supportdavidcunado-arm2017-10-022-10/+19
|\ | | | | Add support for TBBR using ECDSA keys in ARM platforms
| * Dynamic selection of ECDSA or RSAQixiang Xu2017-09-222-9/+18
| | | | | | | | | | | | | | | | Add new option rsa+ecdsa for TF_MBEDTLS_KEY_ALG, which selects rsa or ecdsa depending on the certificate used. Change-Id: I08d9e99bdbba361ed2ec5624248dc382c750ad47 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
| * Add support for TBBR using ECDSA keys in ARM platformsQixiang Xu2017-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | - fixed compile error when KEY_ALG=ecdsa - add new option ecdsa for TF_MBEDTLS_KEY_ALG - add new option devel_ecdsa for ARM_ROTPK_LOCATION - add ecdsa key at plat/arm/board/common/rotpk/ - reduce the mbedtls heap memory size to 13k Change-Id: I3f7a6170af93fdbaaa7bf2fffb4680a9f6113c13 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
* | Fix type of `unsigned long` constantsAntonio Nino Diaz2017-09-212-5/+5
|/ | | | | | | | | | | | | | | | | | | | | | | The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in AArch64. This is inconsistent and that's why we avoid using it as per the Coding Guidelines. This patch changes all `UL` occurrences to `U` or `ULL` depending on the context so that the size of the constant is clear. This problem affected the macro `BIT(nr)`. As long as this macro is used to fill fields of registers, that's not a problem, since all registers are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the macro is used to fill the fields of a 64-bit integer, it won't be able to set the upper 32 bits in AArch32. By changing the type of this macro to `unsigned long long` the behaviour is always the same regardless of the architecture, as this type is 64-bit wide in both cases. Some Tegra platform files have been modified by this patch. Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* cert_tool: Support for legacy RSA PKCS#1 v1.5Soby Mathew2017-08-311-1/+1
| | | | | | | | | | | | | | | | This patch enables choice of RSA version at run time to be used for generating signatures by the cert_tool. The RSA PSS as defined in PKCS#1 v2.1 becomes the default version and this patch enables to specify the RSA PKCS#1 v1.5 algorithm to `cert_create` through the command line -a option. Also, the build option `KEY_ALG` can be used to pass this option from the build system. Please note that RSA PSS is mandated by Trusted Board Boot requirements (TBBR) and legacy RSA support is being added for compatibility reasons. Fixes ARM-Software/tf-issues#499 Change-Id: Ifaa3f2f7c9b43f3d7b3effe2cde76bf6745a5d73 Co-Authored-By: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* Export KEY_ALG as a user build optionSoby Mathew2017-08-311-2/+8
| | | | | | | | | | | | | The `KEY_ALG` variable is used to select the algorithm for key generation by `cert_create` tool for signing the certificates. This variable was previously undocumented and did not have a global default value. This patch corrects this and also adds changes to derive the value of `TF_MBEDTLS_KEY_ALG` based on `KEY_ALG` if it not set by the platform. The corresponding assignment of these variables are also now removed from the `arm_common.mk` makefile. Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I78e2d6f4fc04ed5ad35ce2266118afb63127a5a4
* Merge pull request #1040 from sliai/support-opteed-headerdanh-arm2017-08-141-0/+48
|\ | | | | Support opteed header
| * Support Trusted OS firmware extra images in TF toolsSummer Qin2017-08-091-0/+48
| | | | | | | | | | | | | | | | | | | | | | Since Trusted OS firmware may have extra images, need to assign new uuid and image id for them. The TBBR chain of trust has been extended to add support for the new images within the existing Trusted OS firmware content certificate. Change-Id: I678dac7ba1137e85c5779b05e0c4331134c10e06 Signed-off-by: Summer Qin <summer.qin@arm.com>
* | Add SMMUv3 driverJeenu Viswambharan2017-08-011-0/+55
| | | | | | | | | | | | | | | | | | The driver has only one API: to initialize an SMMUv3 device. This operates on a device that implements secure state, by invalidating secure caches and TLBs. Change-Id: Ief32800419ddf0f1fe38c8f0da8f5ba75c72c826 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | CCI: Adapt for specific product at run timeJeenu Viswambharan2017-08-011-32/+82
|/ | | | | | | | | | | | | | | | | The current build system and driver requires the CCI product to be specified at build time. The device constraints can be determined at run time from its ID registers, obviating the need for specifying them ahead. This patch adds changes to identify and validate CCI at run time. Some global variables are renamed to be in line with the rest of the code base. The build option ARM_CCI_PRODUCT_ID is now removed, and user guide is updated. Change-Id: Ibb765e349d3bc95ff3eb9a64bde1207ab710a93d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Fix order of #includesIsla Mitchell2017-07-124-5/+6
| | | | | | | | | | This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions in order to retain header groupings, minimise changes to imported headers, and where there are headers within the #if and #ifndef statements. Change-Id: I65085a142ba6a83792b26efb47df1329153f1624 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
* Do basic CryptoCell LCS checkSoby Mathew2017-06-281-0/+14
| | | | | | | | | | This patch implements the basic lifecycle state check when CryptoCell SBROM is initialized. Currently the check ensures that if the lifecycle state is Security Disabled (SD), the boot process does not proceed further. Change-Id: I5101335453cd3ea413e97bcfb9138a96c05e1aea Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* Add CC crypto driver to the Auth moduleSoby Mathew2017-06-282-0/+318
| | | | | | | | | | | | | This patch adds a crypto driver which utilizes the ARM® TrustZone® CryptoCell-712 to verify signature and hash during Trusted Board Boot. Along with this driver, the CryptoCell SBROM library is required to successfully build the BL image. The path to this library is specified via the `CCSBROM_LIB_PATH` variable. Please note that, mbedTLS is still required to do the X509 certificate ASN.1 parsing and CryptoCell is only utilized for signature and hash verification. Change-Id: If82dfbae0d7772ba1c64839f0b27850c103fe253 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* io_dummy: correct sparse warningsEtienne Carriere2017-06-231-1/+2
| | | | | | | | Include io_dummy.h header file. Use static for device_type_dummy function. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
* io_storage: use unsigned int for indexEtienne Carriere2017-06-231-1/+1
| | | | | | | This change avoids warning about type conversion. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
* delay_timer: correct sparse issues and warningsEtienne Carriere2017-06-232-4/+5
| | | | | | | | Use NULL instead of 0 where required. Include headers to have the prototype of the functions. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
* ufs: fix the and operatorHaojian Zhuang2017-06-131-3/+3
| | | | | | Should use AND (&), not &&. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* Merge pull request #968 from antonio-nino-diaz-arm/an/snprintf-altdavidcunado-arm2017-06-091-0/+3
|\ | | | | mbedtls: Don't use tf_snprintf if option not defined
| * mbedtls: Don't use tf_snprintf if option not definedAntonio Nino Diaz2017-06-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If `MBEDTLS_PLATFORM_SNPRINTF_ALT` isn't used, the function `mbedtls_platform_set_snprintf()` isn't defined. In case a platform uses a different mbed TLS configuration file than the one provided by the Trusted Firmware, and it doesn't define the mentioned build option, this will result in a build error. This patch modifies the initialization code so that `mbedtls_platform_set_snprintf()` is only used if `MBEDTLS_PLATFORM_SNPRINTF_ALT` is defined, allowing platforms to use it or not depending on their needs. Change-Id: I1d5c86d57e9b2871ba463030bf89210ebec5178e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #964 from soby-mathew/sm/rsapss_supdanh-arm2017-06-052-9/+12
|\ \ | | | | | | Add support for RSASSAPSS algorithm
| * | Add support for RSASSAPSS algorithm in mbedtls crypto driverSoby Mathew2017-06-051-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for RSASSA-PSS Signature Algorithm for X509 certificates in mbedtls crypto driver. Now the driver supports RSA PKCS2_1 standard as mandated by TBBR. NOTE: With this patch, the PKCS1_5 standard compliant RSA signature is deprecated. Change-Id: I9cf6d073370b710cc36a7b374a55ec96c0496461 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * | Increase heapsize for mbedtls librarySoby Mathew2017-06-051-1/+1
| |/ | | | | | | | | | | | | | | | | The mbedTLS library requires larger heap memory for verification of RSASSA-PSS signature in certificates during Trusted Board Boot. This patch increases the heap memory for the same. Change-Id: I3c3123d7142b7b7b01463516ec436734895da159 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* / Introduce ARM GIC-600 driverJeenu Viswambharan2017-06-013-53/+174
|/ | | | | | | | | | | | | | | | | | ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame. This register must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same. The driver provides APIs for Redistributor power management, and overrides those in the generic GICv3 driver. The driver data is shared between generic GICv3 driver and that of GIC-600. For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600. Also update user guide. Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Merge pull request #958 from antonio-nino-diaz-arm/an/mbedtls-heap-sizedanh-arm2017-05-311-1/+1
|\ | | | | mbedtls: Define optimized mbed TLS heap size
| * mbedtls: Define optimized mbed TLS heap sizeAntonio Nino Diaz2017-05-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mbed TLS provides the debug API `mbedtls_memory_buffer_alloc_status()` to analyse the RAM usage of the library. When RSA is selected as algorithm, the maximum heap usage in FVP and Juno has been determined empirically to be approximately 5.5 KiB. However, The default heap size used when RSA is selected is 8 KiB. This patch reduces the buffer from 8 KiB to 6 KiB so that the BSS sections of both BL1 and BL2 are 2 KiB smaller when the firmware is compiled with TBB support. Change-Id: I43878a4e7af50c97be9c8d027c728c8483f24fbf Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #955 from hzhuang1/ufsdanh-arm2017-05-312-0/+949
|\ \ | |/ |/| Add ufs stack and designware phy
| * drivers: add designware ufs driverHaojian Zhuang2017-05-311-0/+190
| | | | | | | | | | | | Initialized the designware UFS PHY. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * drivers: add ufs stackHaojian Zhuang2017-05-311-0/+759
| | | | | | | | | | | | | | | | | | | | | | | | | | If UFS device is initialized, we could just make it out of hibernation by UFS_FLAGS_SKIPINIT. And vendor's dirver is always focus on PHY setting. We could use UFS driver directly if it exits from hibernation. There're eight LUNs in UFS device. The UFS driver only provides the read/write API with LUN. User could define his own read/write since user may want to access different LUNs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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