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* Standardise header guards across codebaseAntonio Nino Diaz2018-11-0853-166/+163
| | | | | | | | | | | | | | | | | | All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1668 from ldts/rcar_gen3/e3_buildSoby Mathew2018-11-073-6/+6
|\ | | | | rcar_gen3: E3 target: fix compilation issues
| * rcar_gen3: E3 target: fix compilation issuesldts2018-11-063-6/+6
| | | | | | | | | | | | Target builds but has not been tested. Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>
* | Remove _tzc_get_max_top_addr() functionSandrine Bailleux2018-11-063-38/+3
|/ | | | | | | | | This function was needed at the time where we didn't have the compiler_rt lib. An AArch32-specific variant was provided to handle the 64-bit shift operation in 32-bit. This is no longer needed. Change-Id: Ibab709a95e3a723ae2eeaddf873dba70ff2012b3 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* Merge pull request #1623 from MISL-EBU-System-SW/a3700-supportAntonio Niño Díaz2018-11-019-286/+2230
|\ | | | | Add support for Armada 3700 and COMPHY porting layer
| * drivers: marvell Add support for Armada-37xx UARTKonstantin Porotchkin2018-10-222-0/+223
| | | | | | | | | | | | Introduce driver for Marvell Armada-37xx UART console Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * drivers: marvell Add Armada-37xx COMPHY driverKonstantin Porotchkin2018-10-222-0/+1233
| | | | | | | | | | | | | | Add support for Marvell Armada-3700 COMPHY driver Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * mvebu: cp110: introduce COMPHY porting layerGrzegorz Jaszczyk2018-10-185-286/+774
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of COMPHY parameters depends on the hw connection between the SoC and the PHY, which can vary on different boards e.g. due to different wires length. Define the "porting layer" with some defaults parameters. It ease updating static values which needs to be updated due to board differences, which are now grouped in one place. Example porting layer for a8k-db is under: plat/marvell/a8k/a80x0/board/phy-porting-layer.h If for some boards parameters are not defined (missing phy-porting-layer.h), the default values are used (drivers/marvell/comphy/phy-default-porting-layer.h) and the following compilation warning is show: "Using default comphy params - you may need to suit them to your board". The common COMPHY driver code is extracted in order to be shared with future COMPHY driver for A3700 SoC platforms Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* | Merge pull request #1646 from Andre-ARM/allwinner/pmic-v2Antonio Niño Díaz2018-10-311-0/+136
|\ \ | | | | | | Allwinner/pmic v2
| * | allwinner: Add RSB driverAndre Przywara2018-10-201-0/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "Reduced Serial Bus" is an Allwinner specific bus, bearing many similarities with I2C. It sports a much higher bus frequency, though, (typically 3 MHz) and requires much less handholding for the typical task of manipulating slave registers (fire-and-forget). On most A64 boards this bus is used to connect the PMIC to the SoC. This driver provides basic primitives to read and write slave registers, it will be later used by the PMIC code. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | meson: console: Add missing define to fix buildAntonio Nino Diaz2018-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | It isn't possible to build this driver without adding this define. Change-Id: Iba2ced411cd8ce438787871fa01b414d32b9aa42 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | meson: console: Introduce console driverAntonio Nino Diaz2018-10-261-0/+263
| | | | | | | | | | | | | | | | | | | | | | | | It has only been tested with a system clock of 24 MHz. It has only been implemented for the multi console API. Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1640 from soby-mathew/sm/fin_con_regAntonio Niño Díaz2018-10-256-7/+18
|\ \ \ | | | | | | | | Multi-console: Deprecate the `finish_console_register` macro
| * | | Multi-console: Deprecate the `finish_console_register` macroSoby Mathew2018-10-196-7/+18
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The `finish_console_register` macro is used by the multi console framework to register the `console_t` driver callbacks. It relied on weak references to the `ldr` instruction to populate 0 to the callback in case the driver has not defined the appropriate function. Use of `ldr` instruction to load absolute address to a reference makes the binary position dependant. These instructions should be replaced with adrp/adr instruction for position independant executable(PIE). But adrp/adr instructions don't work well with weak references as described in GNU ld bugzilla issue 22589. This patch defines a new version of `finish_console_register` macro which can spcify which driver callbacks are valid and deprecates the old one. If any of the argument is not specified, then the macro populates 0 for that callback. Hence the functionality of the previous deprecated macro is preserved. The USE_FINISH_CONSOLE_REG_2 define is used to select the new variant of the macro and will be removed once the deprecated variant is removed. All the upstream console drivers have been migrated to use the new macro in this patch. NOTE: Platforms be aware that the new variant of the `finish_console_register` should be used and the old variant is deprecated. Change-Id: Ia6a67aaf2aa3ba93932992d683587bbd0ad25259 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* / / tzc: Fix MISRA defectsAntonio Nino Diaz2018-10-233-70/+72
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been fixed. The types tzc_region_attributes_t and tzc_action_t have been removed and replaced by unsigned int because it is not allowed to do logical operations on enums. Also, fix some address definitions in arm_def.h. Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1632 from Yann-lms/stm32mp1_mmcSoby Mathew2018-10-183-0/+1245
|\ \ | |/ |/| Add MMC support for STM32MP1
| * stm32mp1: add an IO to read MMC devicesYann Gautier2018-10-151-0/+126
| | | | | | | | | | | | | | | | Whereas the GPT table is read with io_block, the binaries to be loaded (e.g. BL33) cannot use it, as it is not suitable to read them block by block, or the boot time would be very bad. Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * stm32mp1: add an IO to read STM32IMAGE binariesYann Gautier2018-10-151-0/+384
| | | | | | | | | | | | | | This IO is required to read binaries with STM32 header. This header is added with the stm32image tool. Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * stm32mp1: add sdmmc2 driverYann Gautier2018-10-151-0/+735
| | | | | | | | | | | | | | | | This driver is for the STMicroelectronics sdmmc2 IP which is in STM32MP1 SoC. It uses the MMC framework, and can address either eMMC or SD-card. Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | rcar_gen3: drivers: watchdogJorge Ramirez-Ortiz2018-10-171-0/+158
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: serial controller interfaceJorge Ramirez-Ortiz2018-10-171-0/+329
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: spi multio bus controllerJorge Ramirez-Ortiz2018-10-172-0/+59
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: rom apiJorge Ramirez-Ortiz2018-10-172-0/+124
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: power controllerJorge Ramirez-Ortiz2018-10-173-0/+957
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: consoleJorge Ramirez-Ortiz2018-10-173-0/+210
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: io [emmc/mem]Jorge Ramirez-Ortiz2018-10-178-0/+1035
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: i2c dvfsJorge Ramirez-Ortiz2018-10-172-0/+591
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: emmcJorge Ramirez-Ortiz2018-10-1711-0/+3073
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: dmaJorge Ramirez-Ortiz2018-10-171-0/+147
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: micro delay generatorJorge Ramirez-Ortiz2018-10-172-0/+135
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: cpldJorge Ramirez-Ortiz2018-10-171-0/+109
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: board identificationJorge Ramirez-Ortiz2018-10-172-0/+123
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: avs [adaptive voltage scaling]Jorge Ramirez-Ortiz2018-10-172-0/+643
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: authenticationJorge Ramirez-Ortiz2018-10-171-0/+171
| | | | | | | | Signed-off-by: ldts <jramirez@baylibre.com>
* | rcar_gen3: drivers: stagingJorge Ramirez-Ortiz2018-10-1774-0/+31697
| | | | | | | | | | | | | | | | - ddr - pfc [pin function controller] - qos [bandwidth] checkpatch.pl is generating too many errors.
* | rcar-gen3: initial commit for the rcar-gen3 boardsJorge Ramirez-Ortiz2018-10-171-0/+33
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
* Merge pull request #1626 from Yann-lms/partition_verboseDimitris Papastamos2018-10-121-1/+1
|\ | | | | drivers: partition: correct compilation error in VERBOSE mode
| * drivers: partition: correct compilation error in VERBOSE modeYann Gautier2018-10-111-1/+1
| | | | | | | | Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | Merge pull request #1630 from antonio-nino-diaz-arm/an/fix-consoleDimitris Papastamos2018-10-125-10/+14
|\ \ | | | | | | pl011: cnds: cbmem: 16550: Fix comments
| * | pl011: cnds: cbmem: 16550: Fix commentsAntonio Nino Diaz2018-10-125-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | The comments with the prototypes of the register functions of the console drivers are incorrect. The arguments are wrong. This patch fixes them. Change-Id: I38c4b481ee69e840780111c42f03c0752eb6315c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1622 from bryanodonoghue/master+imx7-mmc_fixSoby Mathew2018-10-121-1/+1
|\ \ \ | |_|/ |/| | drivers: imx: mxc_usdhc: Do not set MMC_RSP_48 for MMC_RESPONSE_R2
| * | drivers: imx: mxc_usdhc: Do not set MMC_RSP_48 for MMC_RESPONSE_R2Bryan O'Donoghue2018-10-101-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 97d5db8c5cb95c7ce69ff4d36bcda2aeda143576 reverts an update to the MMC layer that accompanied the original submission of this MMC driver this is the right-thing-to-do in terms of the MMC spec. Unfortunately the reversion also breaks this driver. The issue is the i.MX controller doesn't want MMC_RSP_48 set for MMC_RESPONSE_R2. The appropriate place to place that constraint is obviously in drivers/imx/usdhc/imx_usdhc.c not in the shared MMC codebase. This patch restores the logic the i.MX controller requires without breaking it for everyone else. Fixes: 97d5db8c5cb95c7ce69ff4d36bcda2aeda143576 Fixes: 2a82a9c95f6c06079f58d69315544a6b49cf64a4 Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Jun Nie <jun.nie@linaro.org>
* / plat/arm: Move norflash driver to drivers/ folderAntonio Nino Diaz2018-10-101-0/+195
|/ | | | | | | | | | | | | | This way it can be reused by other platforms if needed. Note that this driver is designed to work with the Versatile Express NOR flash of Juno and FVP. In said platforms, the memory is organized as an interleaved memory of two chips with a 16 bit word. Any platform that wishes to reuse it with a different configuration will need to modify the driver so that it is more generic. Change-Id: Ic721758425864e0cf42b7b9b04bf0d9513b6022e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1583 from danielboulby-arm/db/AArch32_Multi_ConsoleDimitris Papastamos2018-10-044-113/+560
|\ | | | | Enable Multi Console API in AArch32
| * pl011: Add support in AArch32 for MULTI_CONSOLE_APIDaniel Boulby2018-09-211-13/+125
| | | | | | | | | | | | | | | | Allow AArch32 to use the multi console driver by adding the required functions Change-Id: I9e69f18965f320074cf75442d6b0de891aef7936 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
| * console: Port Multi Console driver to AArch32Daniel Boulby2018-09-213-100/+435
| | | | | | | | | | | | | | | | The old driver is now in deprecated_console.S, in a similar way to the AArch64 driver. Change-Id: Ib57209c322576c451d466d7406a94adbf01ab8fd Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | Mark GICV3, CCI and CCN boot time code as initDaniel Boulby2018-10-034-10/+12
| | | | | | | | | | | | | | | | Mark the GICv3, CCI and CCN code only used in Bl31 initialization with __init to be reclaimed once no longer needed. Change-Id: I3d77f36758450d9d1d87ecc60bc1c63fe4082667 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | Merge pull request #1588 from satheesbalya-arm/sb1_2596_misra_tim_consoleSoby Mathew2018-10-032-12/+13
|\ \ | | | | | | Fix misra warnings in delay timer and console drivers
| * | Fix misra warnings in delay timer and console driversSathees Balya2018-09-252-12/+13
| | | | | | | | | | | | | | | Change-Id: I43d2b3a0f672b4902edec3d3a39ffedbb0a701a3 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
* | | Merge pull request #1587 from antonio-nino-diaz-arm/an/deprecatedSoby Mathew2018-10-0218-1314/+41
|\ \ \ | | | | | | | | Remove deprecated interfaces for all platforms
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