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* Merge pull request #1246 from sandrine-bailleux-arm/topics/sb/fix-cnp-docdavidcunado-arm2018-01-291-3/+3
|\ | | | | Fix documentation for CnP bit
| * Fix documentation for CnP bitSandrine Bailleux2018-01-291-3/+3
| | | | | | | | | | | | | | | | | | The CnP bit documentation in the Firmware Design Guide incorrectly used the term "Page Entries" instead of "Processing Elements". Fix that. Change-Id: Ie44ee99c281b7b1a9ad90fba2c7d109f12425507 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | docs: hikey: Fix typoAndreas Färber2018-01-291-1/+1
|/ | | | | | The correct name of the manufacturer is LeMaker. Signed-off-by: Andreas Färber <afaerber@suse.de>
* Merge pull request #1232 from masahir0y/uniphierdavidcunado-arm2018-01-251-28/+30
|\ | | | | uniphier: migrate to BL2-AT-EL3
| * uniphier: switch to BL2-AT-EL3 and remove BL1 supportMasahiro Yamada2018-01-241-28/+30
| | | | | | | | | | | | | | | | | | | | UniPhier platform implements non-TF boot ROM. Prior to the BL2-AT-EL3 support, BL1 (worked as a pseudo ROM) was needed just for ensuring BL2 is entered at EL1-S. Now, this platform is able to avoid this waste. Enable the BL2_AT_EL3 option, and remove BL1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge pull request #1193 from jwerner-chromium/JW_corebootdavidcunado-arm2018-01-241-14/+49
|\ \ | |/ |/| New console API and coreboot support [v4]
| * Add default crash console code to hook up to new console APIJulius Werner2018-01-191-14/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch expands the weak stubs for the plat_crash_console_xxx functions in common platform code to use the new console API for crash output. This should make crash console output "just work" for most cases without the need for the platform to explicitly set up a crash console. For cases where the normal console framework doesn't work (e.g. very early crashes, before the platform can register any consoles), platforms are still able to override the functions just like before. This feature requires the MULTI_CONSOLE_API compile-time flag to work. For builds which don't have it set, this patch has no practical effect. Change-Id: I80dd161cb43f9db59a0bad2dae33c6560cfac584 Signed-off-by: Julius Werner <jwerner@chromium.org>
* | Merge pull request #1200 from robertovargas-arm/bl2-el3davidcunado-arm2018-01-193-0/+124
|\ \ | | | | | | Add BL2_AT_EL3 build option
| * | bl2-el3: Add documentation for BL2 at EL3Roberto Vargas2018-01-183-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update firmware-design.rst, porting-guide.rst and user-guide.rst with the information about BL2 at EL3. Firmware-design.rst is also update to explain how to test this feauture with FVP. Change-Id: I86d64bc64594e13eb041cea9cefa3f7f3fa745bd Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | Merge pull request #1217 from robertovargas-arm/doc-plat_try_next_boot_sourcedavidcunado-arm2018-01-151-0/+3
|\ \ \ | | | | | | | | Add documentation about plat_try_next_boot_source to bl1_platform_setup
| * | | Add documentation about plat_try_next_boot_source to bl1_platform_setupRoberto Vargas2018-01-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If boot redundancy is required in BL1 then the initialization of the boot sequence must be done in bl1_platform_setup. In BL2, we had to add a new function, bl2_preload_setup, because bl2_platform_setup is called after the images are loaded, making it invalid for the boot sequence initialization. Change-Id: I5c177ff142608ed38b4192288b06614343b2b83b Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | | Merge pull request #1197 from dp-arm/dp/amudavidcunado-arm2018-01-121-0/+16
|\ \ \ \ | | | | | | | | | | AMUv1 support
| * | | | AMU: Add plat interface to select which group 1 counters to enableDimitris Papastamos2018-01-111-0/+16
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new platform macro `PLAT_AMU_GROUP1_COUNTERS_MASK` controls which group 1 counters should be enabled. The maximum number of group 1 counters supported by AMUv1 is 16 so the mask can be at most 0xffff. If the platform does not define this mask, no group 1 counters are enabled. A related platform macro `PLAT_AMU_GROUP1_NR_COUNTERS` is used by generic code to allocate an array to save and restore the counters on CPU suspend. Change-Id: I6d135badf4846292de931a43bb563077f42bb47b Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* / / / Workaround for CVE-2017-5715 on Cortex A57 and A72Dimitris Papastamos2018-01-111-0/+10
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling and enabling the MMU. To achieve this without performing any branch instruction, a per-cpu vbar is installed which executes the workaround and then branches off to the corresponding vector entry in the main vector table. A side effect of this change is that the main vbar is configured before any reset handling. This is to allow the per-cpu reset function to override the vbar setting. This workaround is enabled by default on the affected CPUs. Change-Id: I97788d38463a5840a410e3cea85ed297a1678265 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | | Merge pull request #1204 from davidcunado-arm/rv/fip_tooldavidcunado-arm2018-01-031-3/+5
|\ \ \ | | | | | | | | Add padding at the end of the last entry
| * | | docs: Update the ToC end marker description in the documentJett Zhou2018-01-031-3/+5
| |/ / | | | | | | | | | | | | | | | Change-Id: I2e29a63f08aed3b8ea0bb10170a3d55b8d033e62 Signed-off-by: Jett Zhou <jett.zhou@arm.com> Signed-off-by: David Cunado <david.cunado@arm.com>
* | | Merge pull request #1206 from davidcunado-arm/dc/update_userguidedavidcunado-arm2018-01-031-9/+9
|\ \ \ | |/ / |/| | Update dependencies for ARM TF
| * | Update dependencies for ARM TFDavid Cunado2017-12-211-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM TF has been tested as part of its CI system with the following dependencies updated: - Linaro binaries: 17.04 --> 17.10 - mbed TLS library: 2.4.2 --> 2.6.0 The version of AEM, Cortex-A and Foundation models that ARM TF is tested on has also been updated: - v11.1 build 11.1:22 --> v11.2 build 11.2:33 - v8.9 build 0.8:8805 --> v9.0 build 0.8:9005 This patch updates the user guide documentation to reflect these changes to the dependencies. Additionally, links to Linaro resources have been updated. Change-Id: I9ea5cb76e7443c9dbb0c9525069f450a02f59e58 Signed-off-by: David Cunado <david.cunado@arm.com>
* | | Merge pull request #1203 from masahir0y/uniphierdavidcunado-arm2017-12-241-46/+38
|\ \ \ | |/ / |/| | uniphier: a bundle of fixes
| * | doc: uniphier: reformat reStructuredText manuallyMasahiro Yamada2017-12-201-46/+38
| |/ | | | | | | | | | | | | | | | | | | | | | | Commit 6f6257476754 ("Convert documentation to reStructuredText") automatically converted all documents by a tool. I see some parts were converted in an ugly way (or, at least, it is not my intention). Also, the footnote is apparently broken. I checked this document by my eyes, and reformated it so that it looks nicer both in plain text and reST form. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* / Add Secure Partition Manager (SPM) design documentAntonio Nino Diaz2017-12-154-59/+825
|/ | | | | | | | | | | | | | This patch adds documentation that describes the design of the Secure Partition Manager and the specific choices in their current implementation. The document "SPM User Guide" has been integrated into the design document. Change-Id: I0a4f21a2af631c8aa6c739d97a5b634f3cb39991 Co-authored-by: Achin Gupta <achin.gupta@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1178 from davidcunado-arm/dc/enable_svedavidcunado-arm2017-12-111-0/+11
|\ | | | | Enable SVE for Non-secure world
| * Enable SVE for Non-secure worldDavid Cunado2017-11-301-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new build option, ENABLE_SVE_FOR_NS, which when set to one EL3 will check to see if the Scalable Vector Extension (SVE) is implemented when entering and exiting the Non-secure world. If SVE is implemented, EL3 will do the following: - Entry to Non-secure world: SIMD, FP and SVE functionality is enabled. - Exit from Non-secure world: SIMD, FP and SVE functionality is disabled. As SIMD and FP registers are part of the SVE Z-registers then any use of SIMD / FP functionality would corrupt the SVE registers. The build option default is 1. The SVE functionality is only supported on AArch64 and so the build option is set to zero when the target archiecture is AArch32. This build option is not compatible with the CTX_INCLUDE_FPREGS - an assert will be raised on platforms where SVE is implemented and both ENABLE_SVE_FOR_NS and CTX_INCLUDE_FPREGS are set to 1. Also note this change prevents secure world use of FP&SIMD registers on SVE-enabled platforms. Existing Secure-EL1 Payloads will not work on such platforms unless ENABLE_SVE_FOR_NS is set to 0. Additionally, on the first entry into the Non-secure world the SVE functionality is enabled and the SVE Z-register length is set to the maximum size allowed by the architecture. This includes the use case where EL2 is implemented but not used. Change-Id: Ie2d733ddaba0b9bef1d7c9765503155188fe7dae Signed-off-by: David Cunado <david.cunado@arm.com>
* | Merge pull request #1186 from antonio-nino-diaz-arm/an/poplar-docdavidcunado-arm2017-12-091-82/+93
|\ \ | | | | | | poplar: Fix format of documentation
| * | poplar: Fix format of documentationAntonio Nino Diaz2017-12-061-82/+93
| | | | | | | | | | | | | | | | | | | | | The document was being rendered incorrectly. Change-Id: I6e243d17d7cb6247f91698bc195eb0f6efeb7d17 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1157 from antonio-nino-diaz-arm/an/rpi3davidcunado-arm2017-12-051-0/+364
|\ \ \ | |/ / |/| | Introduce AArch64 Raspberry Pi 3 port
| * | rpi3: Add documentation of Raspberry Pi 3 portAntonio Nino Diaz2017-12-011-0/+364
| |/ | | | | | | | | | | | | | | Added design documentation and usage guide for the AArch64 port of the Arm Trusted Firmware to the Raspberry Pi 3. Change-Id: I1be60fbbd54c797b48a1bcebfb944d332616a0de Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* / ARM platforms: Fixup AArch32 buildsSoby Mathew2017-11-291-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a couple of issues for AArch32 builds on ARM reference platforms : 1. The arm_def.h previously defined the same BL32_BASE value for AArch64 and AArch32 build. Since BL31 is not present in AArch32 mode, this meant that the BL31 memory is empty when built for AArch32. Hence this patch allocates BL32 to the memory region occupied by BL31 for AArch32 builds. As a side-effect of this change, the ARM_TSP_RAM_LOCATION macro cannot be used to control the load address of BL32 in AArch32 mode which was never the intention of the macro anyway. 2. A static assert is added to sp_min linker script to check that the progbits are within the bounds expected when overlaid with other images. 3. Fix specifying `SPD` when building Juno for AArch32 mode. Due to the quirks involved when building Juno for AArch32 mode, the build option SPD needed to specifed. This patch corrects this and also updates the documentation in the user-guide. 4. Exclude BL31 from the build and FIP when building Juno for AArch32 mode. As a result the previous assumption that BL31 must be always present is removed and the certificates for BL31 is only generated if `NEED_BL31` is defined. Change-Id: I1c39bbc0abd2be8fbe9f2dea2e9cb4e3e3e436a8 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* AMU: Implement support for aarch64Dimitris Papastamos2017-11-291-2/+3
| | | | | | | | | The `ENABLE_AMU` build option can be used to enable the architecturally defined AMU counters. At present, there is no support for the auxiliary counter group. Change-Id: I7ea0c0a00327f463199d1b0a481f01dadb09d312 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Implement support for the Activity Monitor Unit on Cortex A75Dimitris Papastamos2017-11-291-0/+4
| | | | | | | | | | | | The Cortex A75 has 5 AMU counters. The first three counters are fixed and the remaining two are programmable. A new build option is introduced, `ENABLE_AMU`. When set, the fixed counters will be enabled for use by lower ELs. The programmable counters are currently disabled. Change-Id: I4bd5208799bb9ed7d2596e8b0bfc87abbbe18740 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Merge pull request #1145 from etienne-lms/rfc-armv7-2davidcunado-arm2017-11-232-1/+31
|\ | | | | Support ARMv7 architectures
| * ARMv7 target is driven by ARM_ARCH_MAJOR==7Etienne Carriere2017-11-082-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | External build environment shall sets directive ARM_ARCH_MAJOR to 7 to specify a target ARMv7-A core. As ARM-TF expects AARCH to be set, ARM_ARCH_MAJOR==7 mandates AARCH=aarch32. The toolchain target architecture/cpu is delegated after the platform configuration is parsed. Platform shall define target core through ARM_CORTEX_A<x>=yes, <x> being 5, 7, 9, 12, 15 and/or 17. Platform can bypass ARM_CORTEX_A<x>=yes directive and provide straight the toolchain target directive through MARCH32_DIRECTIVE. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* | Merge pull request #1165 from geesun/qx/support-sha512davidcunado-arm2017-11-221-1/+5
|\ \ | | | | | | Add support sha512 for hash algorithm
| * | tbbr: Add build flag HASH_ALG to let the user to select the SHAQixiang Xu2017-11-211-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flag support the following values: - sha256 (default) - sha384 - sha512 Change-Id: I7a49d858c361e993949cf6ada0a86575c3291066 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
* | | Merge pull request #1161 from jeenu-arm/sdei-fixesdavidcunado-arm2017-11-223-18/+21
|\ \ \ | | | | | | | | SDEI fixes
| * | | SDEI: Update doc to clarify delegationJeenu Viswambharan2017-11-203-18/+21
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | The explicit event dispatch sequence currently depicts handling done in Secure EL1, although further error handling is typically done inside a Secure Partition. Clarify the sequence diagram to that effect. Change-Id: I53deedc6d5ee0706626890067950c2c541a62c78 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* / / Change Statistical Profiling Extensions build option handlingDimitris Papastamos2017-11-201-3/+3
|/ / | | | | | | | | | | | | | | | | | | It is not possible to detect at compile-time whether support for an optional extension such as SPE should be enabled based on the ARM_ARCH_MINOR build option value. Therefore SPE is now enabled by default. Change-Id: I670db164366aa78a7095de70a0962f7c0328ab7c Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | Move FPEXC32_EL2 to FP ContextDavid Cunado2017-11-151-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FPEXC32_EL2 register controls SIMD and FP functionality when the lower ELs are executing in AArch32 mode. It is architecturally mapped to AArch32 system register FPEXC. This patch removes FPEXC32_EL2 register from the System Register context and adds it to the floating-point context. EL3 only saves / restores the floating-point context if the build option CTX_INCLUDE_FPREGS is set to 1. The rationale for this change is that if the Secure world is using FP functionality and EL3 is not managing the FP context, then the Secure world will save / restore the appropriate FP registers. NOTE - this is a break in behaviour in the unlikely case that CTX_INCLUDE_FPREGS is set to 0 and the platform contains an AArch32 Secure Payload that modifies FPEXC, but does not save and restore this register Change-Id: Iab80abcbfe302752d52b323b4abcc334b585c184 Signed-off-by: David Cunado <david.cunado@arm.com>
* | docs: Add SDEI dispatcher documentationJeenu Viswambharan2017-11-136-0/+470
| | | | | | | | | | | | | | | | | | | | | | | | | | The document includes SDEI sequence diagrams that are generated using PlantUML [1]. A shell script is introduced to generate SVG files from PlantUML files supplied in arguments. [1] http://plantuml.com/PlantUML_Language_Reference_Guide.pdf Change-Id: I433897856810bf1927f2800a7b2b1d81827c69b2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | BL31: Add SDEI dispatcherJeenu Viswambharan2017-11-132-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation currently supports only interrupt-based SDEI events, and supports all interfaces as defined by SDEI specification version 1.0 [1]. Introduce the build option SDEI_SUPPORT to include SDEI dispatcher in BL31. Update user guide and porting guide. SDEI documentation to follow. [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf Change-Id: I758b733084e4ea3b27ac77d0259705565842241a Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | BL31: Introduce Exception Handling FrameworkJeenu Viswambharan2017-11-131-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EHF is a framework that allows dispatching of EL3 interrupts to their respective handlers in EL3. This framework facilitates the firmware-first error handling policy in which asynchronous exceptions may be routed to EL3. Such exceptions may be handed over to respective exception handlers. Individual handlers might further delegate exception handling to lower ELs. The framework associates the delegated execution to lower ELs with a priority value. For interrupts, this corresponds to the priorities programmed in GIC; for other types of exceptions, viz. SErrors or Synchronous External Aborts, individual dispatchers shall explicitly associate delegation to a secure priority. In order to prevent lower priority interrupts from preempting higher priority execution, the framework provides helpers to control preemption by virtue of programming Priority Mask register in the interrupt controller. This commit allows for handling interrupts targeted at EL3. Exception handlers own interrupts by assigning them a range of secure priorities, and registering handlers for each priority range it owns. Support for exception handling in BL31 image is enabled by setting the build option EL3_EXCEPTION_HANDLING=1. Documentation to follow. NOTE: The framework assumes the priority scheme supported by platform interrupt controller is compliant with that of ARM GIC architecture (v2 or later). Change-Id: I7224337e4cea47c6ca7d7a4ca22a3716939f7e42 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | GIC: Introduce API to get interrupt IDJeenu Viswambharan2017-11-132-5/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | Acknowledging interrupt shall return a raw value from the interrupt controller in which the actual interrupt ID may be encoded. Add a platform API to extract the actual interrupt ID from the raw value obtained from interrupt controller. Document the new function. Also clarify the semantics of interrupt acknowledge. Change-Id: I818dad7be47661658b16f9807877d259eb127405 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | SPM: FVP: Introduce port of SPMAntonio Nino Diaz2017-11-091-0/+59
|/ | | | | | | | | | | | | | This initial port of the Secure Partitions Manager to FVP supports BL31 in both SRAM and Trusted DRAM. A document with instructions to build the SPM has been added. Change-Id: I4ea83ff0a659be77f2cd72eaf2302cdf8ba98b32 Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Achin Gupta <achin.gupta@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1150 from dp-arm/dp/eventsdavidcunado-arm2017-11-011-16/+6
|\ | | | | aarch64: Add PubSub events to capture security state transitions
| * aarch64: Add PubSub events to capture security state transitionsDimitris Papastamos2017-10-311-16/+6
| | | | | | | | | | | | | | | | | | | | | | Add events that trigger before entry to normal/secure world. The events trigger after the normal/secure context has been restored. Similarly add events that trigger after leaving normal/secure world. The events trigger after the normal/secure context has been saved. Change-Id: I1b48a7ea005d56b1f25e2b5313d77e67d2f02bc5 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | Merge pull request #1149 from robertovargas-arm/fwu-testingdavidcunado-arm2017-10-311-0/+50
|\ \ | | | | | | Add FWU booting instructions to the user guide
| * | Add FWU booting instructions to the user guideRoberto Vargas2017-10-311-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | FWU uses additional images that have to be loaded, and this patch adds the documentation of how to do it in FVP and Juno. Change-Id: I1a40641c11c5a4c8db0aadeaeb2bec30c9279e28 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | Merge pull request #1141 from robertovargas-arm/boot_redundancydavidcunado-arm2017-10-311-0/+28
|\ \ \ | |_|/ |/| | Add platform hooks for boot redundancy support
| * | Add platform hooks for boot redundancy supportRoberto Vargas2017-10-241-0/+28
| |/ | | | | | | | | | | | | | | | | | | These hooks are intended to allow one platform to try load images from alternative places. There is a hook to initialize the sequence of boot locations and a hook to pass to the next sequence. Change-Id: Ia0f84c415208dc4fa4f9d060d58476db23efa5b2 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* / plat/arm: change the default option of ARM_TSP_RAM_LOCATIONQixiang Xu2017-10-251-2/+3
|/ | | | | | | | | On Arm standard platforms, it runs out of SRAM space when TBB is enabled, so the TSP default location is changed to dram when TBB is enabled. Change-Id: I516687013ad436ef454d2055d4e6fce06e467044 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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