aboutsummaryrefslogtreecommitdiffstats
path: root/docs/cpu-specific-build-macros.rst
Commit message (Collapse)AuthorAgeFilesLines
* Fixup SMCCC_FEATURES return value for SMCCC_ARCH_WORKAROUND_1Dimitris Papastamos2018-04-031-1/+5
| | | | | | | Only return -1 if the workaround for CVE-2017-5715 is not compiled in. Change-Id: I1bd07c57d22b4a13cf51b35be141a1f1ffb065ff Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Update Arm TF references to TF-ADan Handley2018-03-151-10/+9
| | | | | | | | | | | | Update Arm Trusted Firmware references in the upstream documents to Trusted Firmware-A (TF-A). This is for consistency with and disambiguation from Trusted Firmware-M (TF-M). Also update other Arm trademarks, e.g. ARM->Arm, ARMv8->Armv8-A. Change-Id: I8bb0e18af29c6744eeea2dc6c08f2c10b20ede22 Signed-off-by: Dan Handley <dan.handley@arm.com> Signed-off-by: David Cunado <david.cunado@arm.com>
* Workaround for CVE-2017-5715 on Cortex A57 and A72Dimitris Papastamos2018-01-111-0/+10
| | | | | | | | | | | | | | | Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling and enabling the MMU. To achieve this without performing any branch instruction, a per-cpu vbar is installed which executes the workaround and then branches off to the corresponding vector entry in the main vector table. A side effect of this change is that the main vbar is configured before any reset handling. This is to allow the per-cpu reset function to override the vbar setting. This workaround is enabled by default on the affected CPUs. Change-Id: I97788d38463a5840a410e3cea85ed297a1678265 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Cortex-A72: Implement workaround for erratum 859971Eleanor Bonnici2017-09-071-0/+8
| | | | | | | | | Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Cortex-A57: Implement workaround for erratum 859972Eleanor Bonnici2017-09-071-2/+6
| | | | | | | | | Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Add doc for some Cortex A53 errata workaroundsDouglas Raillard2017-07-241-0/+10
| | | | | | | | | | Add documentation for errata 835769 and 843419 workarounds introduced in commit a94cc374ab57b80d86974f8771565d65b38403ef Fixes ARM-software/tf-issues#504 Change-Id: I7f3db53dfc5f3827b32663f483d3302bc9679b19 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
* Convert documentation to reStructuredTextDouglas Raillard2017-06-291-0/+127
Due to recent issues in the rendering of the documentation on GitHub and some long-standing issues like the lack of automatic table of content in Markdown, the documentation has been converted to reStructuredText. Basic constructs looks pretty similar to Markdown. Automatically convert GitHub markdown documentation to reStructuredText using pandoc. Change-Id: If20b695acedc6d1b49c8d9fb64efd6b6ba23f4a9 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-03 01:22:57 +0000