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* Factor xlat_table sections in linker scripts out into a header fileMasahiro Yamada2020-03-112-19/+5
| | | | | | | | | | | | | | | | | | | | | TF-A has so many linker scripts, at least one linker script for each BL image, and some platforms have their own ones. They duplicate quite similar code (and comments). When we add some changes to linker scripts, we end up with touching so many files. This is not nice in the maintainability perspective. When you look at Linux kernel, the common code is macrofied in include/asm-generic/vmlinux.lds.h, which is included from each arch linker script, arch/*/kernel/vmlinux.lds.S TF-A can follow this approach. Let's factor out the common code into include/common/bl_common.ld.h As a start point, this commit factors out the xlat_table section. Change-Id: Ifa369e9b48e8e12702535d721cc2a16d12397895 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* aarch32: stop speculative execution past exception returnsMadhukar Pappireddy2020-03-011-1/+1
| | | | | | | | | | | | | aarch32 CPUs speculatively execute instructions following a ERET as if it was not a jump instruction. This could lead to cache-based side channel vulnerabilities. The software fix is to place barrier instructions following ERET. The counterpart patch for aarch64 is merged: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=f461fe346b728d0e88142fd7b8f2816415af18bc Change-Id: I2aa3105bee0b92238f389830b3a3b8650f33af3d Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* Merge changes from topic "lm/fconf" into integrationSandrine Bailleux2020-02-111-1/+11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: arm-io: Panic in case of io setup failure MISRA fix: Use boolean essential type fconf: Add documentation fconf: Move platform io policies into fconf fconf: Add mbedtls shared heap as property fconf: Add TBBR disable_authentication property fconf: Add dynamic config DTBs info as property fconf: Populate properties from dtb during bl2 setup fconf: Load config dtb from bl1 fconf: initial commit
| * fconf: initial commitLouis Mayencourt2020-02-071-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the Firmware CONfiguration Framework (fconf). The fconf is an abstraction layer for platform specific data, allowing a "property" to be queried and a value retrieved without the requesting entity knowing what backing store is being used to hold the data. The default backing store used is C structure. If another backing store has to be used, the platform integrator needs to provide a "populate()" function to fill the corresponding C structure. The "populate()" function must be registered to the fconf framework with the "FCONF_REGISTER_POPULATOR()". This ensures that the function would be called inside the "fconf_populate()" function. A two level macro is used as getter: - the first macro takes 3 parameters and converts it to a function call: FCONF_GET_PROPERTY(a,b,c) -> a__b_getter(c). - the second level defines a__b_getter(c) to the matching C structure, variable, array, function, etc.. Ex: Get a Chain of trust property: 1) FCONF_GET_PROPERY(tbbr, cot, BL2_id) -> tbbr__cot_getter(BL2_id) 2) tbbr__cot_getter(BL2_id) -> cot_desc_ptr[BL2_id] Change-Id: Id394001353ed295bc680c3f543af0cf8da549469 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | coverity: Fix MISRA null pointer violationsZelalem2020-02-051-7/+7
|/ | | | | | | | | | | Fix code that violates the MISRA rule: MISRA C-2012 Rule 11.9: Literal "0" shall not be used as null pointer constant. The fix explicitly checks whether a pointer is NULL. Change-Id: Ibc318dc0f464982be9a34783f24ccd1d44800551 Signed-off-by: Zelalem <zelalem.aweke@arm.com>
* BL2: Print ID of images we fail loadingSandrine Bailleux2020-02-031-1/+2
| | | | | | | | | | | | When Trusted Boot is enabled, images are loaded and authenticated following up the root of trust. This means that between the initial console message saying that an image is being loaded, and the final one where it says that it failed to load it, BL2 may print several messages about other images on the chain of trust being loaded, thus it is not always clear which image we failed loading at the end of the day. Change-Id: I3b189ec9d12c2a6203d16c8dbbb4fc117639c3c1 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* BL2_AT_EL3: add PIE supportMasahiro Yamada2020-01-242-1/+44
| | | | | | | | | | This implementation simply mimics that of BL31. I did not implement the ENABLE_PIE support for BL2_IN_XIP_MEM=1 case. It would make the linker script a bit uglier. Change-Id: If3215abd99f2758dfb232e44b50320d04eba808b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Prevent speculative execution past ERETAnthony Steinhauser2020-01-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS: https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8 https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61 https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2 https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser <asteinhauser@google.com> Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
* Merge "PIE: make call to GDT relocation fixup generalized" into integrationSoby Mathew2019-12-121-1/+2
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| * PIE: make call to GDT relocation fixup generalizedManish Pandey2019-12-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a Firmware is complied as Position Independent Executable it needs to request GDT fixup by passing size of the memory region to el3_entrypoint_common macro. The Global descriptor table fixup will be done early on during cold boot process of primary core. Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be compiled as PIE, it can simply pass fixup size to the common el3 entrypoint macro to fixup GDT. The reason for this patch was to overcome the bug introduced by SHA 330ead806 which called fixup routine for each core causing re-initializing of global pointers thus overwriting any changes done by the previous core. Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
* | Reduce space lost to object alignmentSamuel Holland2019-12-042-12/+12
|/ | | | | | | | | | | | | | | | | | | | | | Currently, sections within .text/.rodata/.data/.bss are emitted in the order they are seen by the linker. This leads to wasted space, when a section with a larger alignment follows one with a smaller alignment. We can avoid this wasted space by sorting the sections. To take full advantage of this, we must disable generation of common symbols, so "common" data can be sorted along with the rest of .bss. An example of the improvement, from `make DEBUG=1 PLAT=sun50i_a64 bl31`: .text => no change .rodata => 16 bytes saved .data => 11 bytes saved .bss => 576 bytes saved As a side effect, the addition of `-fno-common` in TF_CFLAGS makes it easier to spot bugs in header files. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I073630a9b0b84e7302a7a500d4bb4b547be01d51
* Refactor ARMv8.3 Pointer Authentication support codeAlexei Fedorov2019-09-133-51/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides the following features and makes modifications listed below: - Individual APIAKey key generation for each CPU. - New key generation on every BL31 warm boot and TSP CPU On event. - Per-CPU storage of APIAKey added in percpu_data[] of cpu_data structure. - `plat_init_apiakey()` function replaced with `plat_init_apkey()` which returns 128-bit value and uses Generic timer physical counter value to increase the randomness of the generated key. The new function can be used for generation of all ARMv8.3-PAuth keys - ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`. - New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively; pauth_disable_el1()` and `pauth_disable_el3()` functions disable PAuth for EL1 and EL3 respectively; `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from cpu-data structure. - Combined `save_gp_pauth_registers()` function replaces calls to `save_gp_registers()` and `pauth_context_save()`; `restore_gp_pauth_registers()` replaces `pauth_context_restore()` and `restore_gp_registers()` calls. - `restore_gp_registers_eret()` function removed with corresponding code placed in `el3_exit()`. - Fixed the issue when `pauth_t pauth_ctx` structure allocated space for 12 uint64_t PAuth registers instead of 10 by removal of macro CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h` and assigning its value to CTX_PAUTH_REGS_END. - Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions in `msr spsel` instruction instead of hard-coded values. - Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI. Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Switch AARCH32/AARCH64 to __aarch64__Julius Werner2019-08-011-9/+9
| | | | | | | | | | | | | | | | | NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org>
* bl2_el3: clean up linker scriptMasahiro Yamada2019-06-141-16/+3
| | | | | | | | | | | This linker script is so unreadable due to sprinkled #ifdef. Direct read-only data to 'ROM' and read-write data to 'RAM'. Both go to the same memory device when BL2_IN_XIP_MEM is disabled. Change-Id: Ieeac3f1a4e05e9e8599de2ec84260819c70f361e Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Add support for Branch Target IdentificationAlexei Fedorov2019-05-243-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the functionality needed for platforms to provide Branch Target Identification (BTI) extension, introduced to AArch64 in Armv8.5-A by adding BTI instruction used to mark valid targets for indirect branches. The patch sets new GP bit [50] to the stage 1 Translation Table Block and Page entries to denote guarded EL3 code pages which will cause processor to trap instructions in protected pages trying to perform an indirect branch to any instruction other than BTI. BTI feature is selected by BRANCH_PROTECTION option which supersedes the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication and is disabled by default. Enabling BTI requires compiler support and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0. The assembly macros and helpers are modified to accommodate the BTI instruction. This is an experimental feature. Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3 is now made as an internal flag and BRANCH_PROTECTION flag should be used instead to enable Pointer Authentication. Note. USE_LIBROM=1 option is currently not supported. Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Merge pull request #1878 from jts-arm/sctlrSoby Mathew2019-03-132-4/+7
|\ | | | | Apply stricter speculative load restriction
| * Apply stricter speculative load restrictionJohn Tsichritzis2019-03-122-4/+7
| | | | | | | | | | | | | | | | | | | | | | The SCTLR.DSSBS bit is zero by default thus disabling speculative loads. However, we also explicitly set it to zero for BL2 and TSP images when each image initialises its context. This is done to ensure that the image environment is initialised in a safe state, regardless of the reset value of the bit. Change-Id: If25a8396641edb640f7f298b8d3309d5cba3cd79 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | bl2-el3: Fix exit to bl32 by ensuring a more complete write to SPSRBryan O'Donoghue2019-03-131-1/+1
|/ | | | | | | | | | | | | | | | | Prior to entry into BL32 we set the SPSR by way of msr spsr, r1. This unfortunately only writes the bits f->[31:24] and c->[7:0]. This patch updates the bl2 exit path to write the x->[15:8] and c->[7:0] fields of the SPSR. For the purposes of initial setup of the SPSR the x and c fields should be sufficient and importantly will capture the necessary lower-order control bits that f:c alone do not. This is important to do to ensure the SPSR is set to the mode the platform intends prior to performing an eret. Fixes: b1d27b484f41 ("bl2-el3: Add BL2_EL3 image") Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
* BL2_AT_EL3: Enable pointer authentication supportAntonio Nino Diaz2019-02-273-15/+72
| | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +44 | +0 | +0 | +0 | | | 0.2% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +712 | +0 | +16 | +0 | | | 3.1% | | 0.9% | | +----------------------------+-------+-------+-------+--------+ The results are valid for the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ BL2_AT_EL3=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I1c0616e7dea30962a92b4fd113428bc30a018320 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* BL2: Enable pointer authentication supportAntonio Nino Diaz2019-02-274-14/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +40 | +0 | +0 | +0 | | | 0.2% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +664 | +0 | +16 | +0 | | | 3.1% | | 0.9% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 The changes for BL2_AT_EL3 aren't done in this commit. Change-Id: I8c803b40c7160525a06173bc6cdca21c4505837d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Move BL1 and BL2 private defines to bl_common.hAntonio Nino Diaz2019-01-151-16/+1
| | | | | | | | The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for platforms that may need to access them. Change-Id: Ifd1880f855ddafcb3bfcaf1ed4a4e0f121eda174 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Sanitise includes across codebaseAntonio Nino Diaz2019-01-0410-27/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* correct some missing-prototype warningsYann Gautier2018-12-102-0/+4
| | | | | | | | | | | | This avoids the following warnings: no previous prototype for 'bl2_arch_setup' [-Wmissing-prototypes] no previous prototype for 'plat_log_get_prefix' [-Wmissing-prototypes] Also correct a compilation issue if BL2_IN_XIP_MEM is enabled: uintptr_t is not defined. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
* Standardise header guards across codebaseAntonio Nino Diaz2018-11-081-3/+3
| | | | | | | | | | | | | | | | | | All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* PIE: Use PC relative adrp/adr for symbol referenceSoby Mathew2018-10-291-4/+10
| | | | | | | | | | | | | | | | | | | This patch fixes up the AArch64 assembly code to use adrp/adr instructions instead of ldr instruction for reference to symbols. This allows these assembly sequences to be Position Independant. Note that the the reference to sizes have been replaced with calculation of size at runtime. This is because size is a constant value and does not depend on execution address and using PC relative instructions for loading them makes them relative to execution address. Also we cannot use `ldr` instruction to load size as it generates a dynamic relocation entry which must *not* be fixed up and it is difficult for a dynamic loader to differentiate which entries need to be skipped. Change-Id: I8bf4ed5c58a9703629e5498a27624500ef40a836 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* Remove build option LOAD_IMAGE_V2Roberto Vargas2018-09-282-265/+0
| | | | | | | | The code of LOAD_IMAGE_V2=0 has been removed. Change-Id: Iea03e5bebb90c66889bdb23f85c07d0c9717fffe Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* DSU erratum 936184 workaroundJohn Tsichritzis2018-08-171-1/+6
| | | | | | | | | | | | | | | | If the system is in near idle conditions, this erratum could cause a deadlock or data corruption. This patch applies the workaround that prevents this. This DSU erratum affects only the DSUs that contain the ACP interface and it was fixed in r2p0. The workaround is applied only to the DSUs that are actually affected. Link to respective Arm documentation: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm138168/index.html Change-Id: I033213b3077685130fc1e3f4f79c4d15d7483ec9 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Create a library file for libmbedtlsRoberto Vargas2018-08-031-3/+1
| | | | | | | | | TF Makefile was linking all the objects files generated for the Mbed TLS library instead of creating a static library that could be used in the linking stage. Change-Id: I8e4cd843ef56033c9d3faeee71601d110b7e4c12 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* Add end_vector_entry assembler macroRoberto Vargas2018-07-111-16/+16
| | | | | | | | | | | | | | Check_vector_size checks if the size of the vector fits in the size reserved for it. This check creates problems in the Clang assembler. A new macro, end_vector_entry, is added and check_vector_size is deprecated. This new macro fills the current exception vector until the next exception vector. If the size of the current vector is bigger than 32 instructions then it gives an error. Change-Id: Ie8545cf1003a1e31656a1018dd6b4c28a4eaf671 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* Add .extab and .exidx sectionsRoberto Vargas2018-07-111-0/+9
| | | | | | | | | | These sections are required by clang when the code is compiled for aarch32. These sections are related to the unwind of the stack in exceptions, but in the way that clang defines and uses them, the garbage collector cannot get rid of them. Change-Id: I085efc0cf77eae961d522472f72c4b5bad2237ab Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* Use ALIGN instead of NEXT in linker scriptsRoberto Vargas2018-07-112-8/+8
| | | | | | | | | Clang linker doesn't support NEXT. As we are not using the MEMORY command to define discontinuous memory for the output file in any of the linker scripts, ALIGN and NEXT are equivalent. Change-Id: I867ffb9c9a76d4e81c9ca7998280b2edf10efea0 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* BL2_AT_EL3: do not try to disable MMU twice on AARCH32Yann Gautier2018-04-261-2/+1
| | | | | | | | | | If BL2_AT_EL3 is enabled, bl2_run_next_image is called at the end of BL2. This function calls disable_mmu_icache_secure. It is then useless to call it in bl2_main in that case. fixes arm-software/tf-issues#582 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* Merge pull request #1356 from robertovargas-arm/misra-changesDimitris Papastamos2018-04-162-3/+3
|\ | | | | Misra changes
| * Fix MISRA rule 8.3 Part 1Roberto Vargas2018-04-132-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers. Fixed for: make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all Change-Id: I32d6fbce03bb4830ed5bf521afe7063505c6ed79 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | Add support for BL2 in XIP memoryJiafei Pan2018-04-072-2/+69
|/ | | | | | | | | | In some use-cases BL2 will be stored in eXecute In Place (XIP) memory, like BL1. In these use-cases, it is necessary to initialize the RW sections in RAM, while leaving the RO sections in place. This patch enable this use-case with a new build option, BL2_IN_XIP_MEM. For now, this option is only supported when BL2_AT_EL3 is 1. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
* bl2-el3: Fix bl32 lr_svc used for bl33 entry addressLionel Debieve2018-03-051-0/+5
| | | | | | | | | When using BL2_EL3, we need to ensure that lr_svc is properly given to bl32 as it was previously made by bl1. Fixes ARM-Software/tf-issues#562 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
* Merge pull request #1282 from robertovargas-arm/misra-changesdavidcunado-arm2018-02-284-4/+7
|\ | | | | Misra changes
| * Fix MISRA rule 8.4 Part 1Roberto Vargas2018-02-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all Change-Id: I7c2ad3f5c015411c202605851240d5347e4cc8c7 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
| * Fix MISRA rule 8.4 in common codeRoberto Vargas2018-02-283-4/+6
| | | | | | | | | | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined. Change-Id: I26e042cb251a6f9590afa1340fdac73e42f23979 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatchdavidcunado-arm2018-02-282-4/+6
|\ \ | |/ |/| Clarify comments in xlat tables lib and fixes related to the TLB
| * Add comments about mismatched TCR_ELx and xlat tablesAntonio Nino Diaz2018-02-272-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the MMU is enabled and the translation tables are mapped, data read/writes to the translation tables are made using the attributes specified in the translation tables themselves. However, the MMU performs table walks with the attributes specified in TCR_ELx. They are completely independent, so special care has to be taken to make sure that they are the same. This has to be done manually because it is not practical to have a test in the code. Such a test would need to know the virtual memory region that contains the translation tables and check that for all of the tables the attributes match the ones in TCR_ELx. As the tables may not even be mapped at all, this isn't a test that can be made generic. The flags used by enable_mmu_xxx() have been moved to the same header where the functions are. Also, some comments in the linker scripts related to the translation tables have been fixed. Change-Id: I1754768bffdae75f53561b1c4a5baf043b45a304 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Introduce the new BL handover interfaceSoby Mathew2018-02-262-13/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new BL handover interface. It essentially allows passing 4 arguments between the different BL stages. Effort has been made so as to be compatible with the previous handover interface. The previous blx_early_platform_setup() platform API is now deprecated and the new blx_early_platform_setup2() variant is introduced. The weak compatiblity implementation for the new API is done in the `plat_bl_common.c` file. Some of the new arguments in the new API will be reserved for generic code use when dynamic configuration support is implemented. Otherwise the other registers are available for platform use. Change-Id: Ifddfe2ea8e32497fe1beb565cac155ad9d50d404 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | Add image_id to bl1_plat_handle_post/pre_image_load()Soby Mathew2018-02-261-1/+0
|/ | | | | | | | | | | | | | | | | | | | | This patch adds an argument to bl1_plat_post/pre_image_load() APIs to make it more future proof. The default implementation of these are moved to `plat_bl1_common.c` file. These APIs are now invoked appropriately in the FWU code path prior to or post image loading by BL1 and are not restricted to LOAD_IMAGE_V2. The patch also reorganizes some common platform files. The previous `plat_bl2_el3_common.c` and `platform_helpers_default.c` files are merged into a new `plat_bl_common.c` file. NOTE: The addition of an argument to the above mentioned platform APIs is not expected to have a great impact because these APIs were only recently added and are unlikely to be used. Change-Id: I0519caaee0f774dd33638ff63a2e597ea178c453 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* Merge pull request #1173 from etienne-lms/armv7-qemudavidcunado-arm2018-02-071-2/+4
|\ | | | | support to boot OP-TEE on AArch32/Armv7+example with Cortex-A15/Qemu
| * [fix] aarch32: optee: define the OP-TEE secure payloadEtienne Carriere2018-02-061-1/+1
| | | | | | | | | | | | | | As per MISRA C-2012 Rule 10.4. arg0 is a u_register_t, can be a 32bit or 64bit upon architecture. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * aarch32: optee: define the OP-TEE secure payloadEtienne Carriere2018-02-051-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AArch32 only platforms can boot the OP-TEE secure firmware as a BL32 secure payload. Such configuration can be defined through AARCH32_SP=optee. The source files can rely on AARCH32_SP_OPTEE to condition OP-TEE boot specific instruction sequences. OP-TEE does not expect ARM Trusted Firmware formatted structure as boot argument. Load sequence is expected to have already loaded to OP-TEE boot arguments into the bl32 entrypoint info structure. Last, AArch32 platform can only boot AArch32 OP-TEE images. Change-Id: Ic28eec5004315fc9111051add6bb1a1d607fc815 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* | bl2: add bl2_plat_handle_pre_image_load()Masahiro Yamada2018-02-021-1/+7
|/ | | | | | | | | There are cases where we need to manipulate image information before the load. For example, for decompressing data, we cannot load the compressed images to their final destination. Instead, we need to load them to the temporary buffer for the decompressor. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* bl2-el3: Don't compile BL1 when BL2_AT_EL3 is defined in FVPRoberto Vargas2018-01-181-1/+4
| | | | | | | | | | | | This patch modifies the makefiles to avoid the definition of BL1_SOURCES and BL2_SOURCES in the tbbr makefiles, and it lets to the platform makefiles to define them if they actually need these images. In the case of BL2_AT_EL3 BL1 will not be needed usually because the Boot ROM will jump directly to BL2. Change-Id: Ib6845a260633a22a646088629bcd7387fe35dcf9 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* bl2-el3: Mark all the assembly functions in bl2 at el3Roberto Vargas2018-01-181-2/+11
| | | | | | | | | | When BL2_AT_EL3 option is enabled some platforms are going to need a resident part in BL2 because the boot rom may jump to it after a reset. This patch introduces __TEXT_RESIDENT_START__ and __TEXT_RESIDENT_END__ linker symbols that mark the resident region. Change-Id: Ib20c1b8ee257831bcc0ca7d3df98d0cb617a04f8 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* bl2-el3: Add BL2_EL3 imageRoberto Vargas2018-01-188-2/+515
| | | | | | | | | | | This patch enables BL2 to execute at the highest exception level without any dependancy on TF BL1. This enables platforms which already have a non-TF Boot ROM to directly load and execute BL2 and subsequent BL stages without need for BL1. This is not currently possible because BL2 executes at S-EL1 and cannot jump straight to EL3. Change-Id: Ief1efca4598560b1b8c8e61fbe26d1f44e929d69 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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