diff options
Diffstat (limited to 'plat')
71 files changed, 1592 insertions, 228 deletions
diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h index 1e1b0a4d1..11668797b 100644 --- a/plat/allwinner/common/include/sunxi_private.h +++ b/plat/allwinner/common/include/sunxi_private.h @@ -9,9 +9,9 @@ void sunxi_configure_mmu_el3(int flags); -void sunxi_cpu_on(unsigned int cluster, unsigned int core); -void sunxi_cpu_off(unsigned int cluster, unsigned int core); -void sunxi_disable_secondary_cpus(unsigned int primary_cpu); +void sunxi_cpu_on(u_register_t mpidr); +void sunxi_cpu_off(u_register_t mpidr); +void sunxi_disable_secondary_cpus(u_register_t primary_mpidr); void __dead2 sunxi_power_down(void); int sunxi_pmic_setup(uint16_t socid, const void *fdt); diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c index 7ffa65821..a24527c5d 100644 --- a/plat/allwinner/common/sunxi_bl31_setup.c +++ b/plat/allwinner/common/sunxi_bl31_setup.c @@ -11,6 +11,7 @@ #include <platform_def.h> #include <arch.h> +#include <arch_helpers.h> #include <common/debug.h> #include <drivers/arm/gicv2.h> #include <drivers/console.h> @@ -101,7 +102,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); /* Turn off all secondary CPUs */ - sunxi_disable_secondary_cpus(plat_my_core_pos()); + sunxi_disable_secondary_cpus(read_mpidr()); } void bl31_plat_arch_setup(void) diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c index 6bb8968ce..3b44aab68 100644 --- a/plat/allwinner/common/sunxi_common.c +++ b/plat/allwinner/common/sunxi_common.c @@ -18,7 +18,7 @@ #include <sunxi_mmap.h> #include <sunxi_private.h> -static mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { +static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE), MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, diff --git a/plat/allwinner/common/sunxi_cpu_ops.c b/plat/allwinner/common/sunxi_cpu_ops.c index 8c086030a..b4c9fcc18 100644 --- a/plat/allwinner/common/sunxi_cpu_ops.c +++ b/plat/allwinner/common/sunxi_cpu_ops.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -45,9 +45,10 @@ static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core) mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00); } -void sunxi_cpu_off(unsigned int cluster, unsigned int core) +void sunxi_cpu_off(u_register_t mpidr) { - int corenr = cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core; + unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); + unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core); @@ -55,9 +56,9 @@ void sunxi_cpu_off(unsigned int cluster, unsigned int core) mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); /* We can't turn ourself off like this, but it works for other cores. */ - if (plat_my_core_pos() != corenr) { + if (read_mpidr() != mpidr) { /* Activate the core output clamps, but not for core 0. */ - if (corenr != 0) + if (core != 0) mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); /* Assert CPU power-on reset */ @@ -80,8 +81,11 @@ void sunxi_cpu_off(unsigned int cluster, unsigned int core) 0, BIT_32(core)); } -void sunxi_cpu_on(unsigned int cluster, unsigned int core) +void sunxi_cpu_on(u_register_t mpidr) { + unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); + unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); + VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core); /* Assert CPU core reset */ @@ -102,12 +106,18 @@ void sunxi_cpu_on(unsigned int cluster, unsigned int core) mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); } -void sunxi_disable_secondary_cpus(unsigned int primary_cpu) +void sunxi_disable_secondary_cpus(u_register_t primary_mpidr) { - for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) { - if (cpu == primary_cpu) - continue; - sunxi_cpu_off(cpu / PLATFORM_MAX_CPUS_PER_CLUSTER, - cpu % PLATFORM_MAX_CPUS_PER_CLUSTER); + unsigned int cluster; + unsigned int core; + + for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; ++cluster) { + for (core = 0; core < PLATFORM_MAX_CPUS_PER_CLUSTER; ++core) { + u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) | + (core << MPIDR_AFF0_SHIFT) | + BIT(31); + if (mpidr != primary_mpidr) + sunxi_cpu_off(mpidr); + } } } diff --git a/plat/allwinner/common/sunxi_pm.c b/plat/allwinner/common/sunxi_pm.c index 8cc715c27..1d2dc9385 100644 --- a/plat/allwinner/common/sunxi_pm.c +++ b/plat/allwinner/common/sunxi_pm.c @@ -35,7 +35,7 @@ static int sunxi_pwr_domain_on(u_register_t mpidr) if (mpidr_is_valid(mpidr) == 0) return PSCI_E_INTERN_FAIL; - sunxi_cpu_on(MPIDR_AFFLVL1_VAL(mpidr), MPIDR_AFFLVL0_VAL(mpidr)); + sunxi_cpu_on(mpidr); return PSCI_E_SUCCESS; } @@ -47,9 +47,7 @@ static void sunxi_pwr_domain_off(const psci_power_state_t *target_state) static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state) { - u_register_t mpidr = read_mpidr(); - - sunxi_cpu_off(MPIDR_AFFLVL1_VAL(mpidr), MPIDR_AFFLVL0_VAL(mpidr)); + sunxi_cpu_off(read_mpidr()); while (1) wfi(); @@ -64,7 +62,7 @@ static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state) static void __dead2 sunxi_system_off(void) { /* Turn off all secondary CPUs */ - sunxi_disable_secondary_cpus(plat_my_core_pos()); + sunxi_disable_secondary_cpus(read_mpidr()); sunxi_power_down(); } diff --git a/plat/allwinner/common/sunxi_topology.c b/plat/allwinner/common/sunxi_topology.c index 7acc77a9a..45be1e03d 100644 --- a/plat/allwinner/common/sunxi_topology.c +++ b/plat/allwinner/common/sunxi_topology.c @@ -9,7 +9,7 @@ #include <arch.h> #include <plat/common/platform.h> -static unsigned char plat_power_domain_tree_desc[PLAT_MAX_PWR_LVL + 1] = { +static const unsigned char plat_power_domain_tree_desc[PLAT_MAX_PWR_LVL + 1] = { /* One root node for the SoC */ 1, /* One node for each cluster */ diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index 706bfcecb..b4d16a068 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -175,7 +175,7 @@ static int fdt_get_regulator_millivolt(const void *fdt, int node) #define NO_SPLIT 0xff -struct axp_regulator { +static const struct axp_regulator { char *dt_name; uint16_t min_volt; uint16_t max_volt; @@ -247,7 +247,7 @@ static void setup_axp803_rails(const void *fdt) for (node = fdt_first_subnode(fdt, node); node != -FDT_ERR_NOTFOUND; node = fdt_next_subnode(fdt, node)) { - struct axp_regulator *reg; + const struct axp_regulator *reg; const char *name; int length; diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 115310175..780e6fcbf 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -173,14 +173,11 @@ #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ -#define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE -#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ +#define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE +#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ -#define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE -#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ - -#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE -#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 42a9095d9..8e693991d 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -103,7 +103,7 @@ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ lib/cpus/aarch64/cortex_a73.S \ lib/cpus/aarch64/cortex_a75.S \ lib/cpus/aarch64/cortex_a76.S \ - lib/cpus/aarch64/cortex_ares.S \ + lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/cortex_deimos.S else FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S @@ -214,7 +214,7 @@ endif ifeq (${ENABLE_AMU},1) BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ - lib/cpus/aarch64/cortex_ares_pubsub.c \ + lib/cpus/aarch64/neoverse_n1_pubsub.c \ lib/cpus/aarch64/cpuamu.c \ lib/cpus/aarch64/cpuamu_helpers.S endif diff --git a/plat/arm/board/fvp_ve/aarch32/fvp_ve_helpers.S b/plat/arm/board/fvp_ve/aarch32/fvp_ve_helpers.S new file mode 100644 index 000000000..78f6c68bd --- /dev/null +++ b/plat/arm/board/fvp_ve/aarch32/fvp_ve_helpers.S @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <platform_def.h> + + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + + /* -------------------------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * For AArch32, cold-booting secondary CPUs is not yet + * implemented and they panic. + * -------------------------------------------------------------------- + */ +func plat_secondary_cold_boot_setup +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * unsigned long plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and warm + * boot. On FVP, this information can be queried from the power + * controller. The Power Control SYS Status Register (PSYSR) indicates + * the wake-up reason for the CPU. + * + * For a cold boot, return 0. + * For a warm boot, read the mailbox and return the address it contains. + * + * TODO: PSYSR is a common register and should be + * accessed using locks. Since it is not possible + * to use locks immediately after a cold reset + * we are relying on the fact that after a cold + * reset all cpus will read the same WK field + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* TODO support warm boot */ + /* Cold reset */ + mov r0, #0 + bx lr + +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Currently configured for a sigle CPU + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mov r0, #1 + bx lr +endfunc plat_is_my_cpu_primary diff --git a/plat/arm/board/fvp_ve/fdts/fvp_ve_tb_fw_config.dts b/plat/arm/board/fvp_ve/fdts/fvp_ve_tb_fw_config.dts new file mode 100644 index 000000000..9ab2d9656 --- /dev/null +++ b/plat/arm/board/fvp_ve/fdts/fvp_ve_tb_fw_config.dts @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +/ { + /* Platform Config */ + plat_arm_bl2 { + compatible = "arm,tb_fw"; + hw_config_addr = <0x0 0x82000000>; + hw_config_max_size = <0x01000000>; + /* Disable authentication for development */ + disable_auth = <0x0>; + }; +}; diff --git a/plat/arm/board/fvp_ve/fvp_ve_bl1_setup.c b/plat/arm/board/fvp_ve/fvp_ve_bl1_setup.c new file mode 100644 index 000000000..47cd87627 --- /dev/null +++ b/plat/arm/board/fvp_ve/fvp_ve_bl1_setup.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <plat/arm/common/plat_arm.h> +#include <plat/common/platform.h> + +/******************************************************************************* + * Perform any BL1 specific platform actions. + ******************************************************************************/ +void bl1_early_platform_setup(void) +{ + arm_bl1_early_platform_setup(); +} diff --git a/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c b/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c new file mode 100644 index 000000000..25e096417 --- /dev/null +++ b/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <drivers/arm/sp804_delay_timer.h> +#include <drivers/generic_delay_timer.h> +#include <lib/mmio.h> +#include <plat/arm/common/plat_arm.h> +#include <plat/common/platform.h> +#include <platform_def.h> + +#include "fvp_ve_private.h" + +void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) +{ + arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); + + /* Initialize the platform config for future decision making */ + fvp_ve_config_setup(); +} + +void bl2_platform_setup(void) +{ + arm_bl2_platform_setup(); + +#ifdef FVP_VE_USE_SP804_TIMER + /* + * Enable the clock override for SP804 timer 0, which means that no + * clock dividers are applied and the raw (35 MHz) clock will be used + */ + mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); + + /* Initialize delay timer driver using SP804 dual timer 0 */ + sp804_timer_init(V2M_SP804_TIMER0_BASE, + SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); +#else + generic_delay_timer_init(); +#endif /* FVP_VE_USE_SP804_TIMER */ +} diff --git a/plat/arm/board/fvp_ve/fvp_ve_common.c b/plat/arm/board/fvp_ve/fvp_ve_common.c new file mode 100644 index 000000000..768dad533 --- /dev/null +++ b/plat/arm/board/fvp_ve/fvp_ve_common.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <common/debug.h> +#include <lib/mmio.h> +#include <platform_def.h> +#include <plat/arm/common/arm_config.h> +#include <plat/arm/common/plat_arm.h> + +#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ + DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#ifdef IMAGE_BL1 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH1_RW, + V2M_MAP_IOFPGA, + {0} +}; +#endif +#ifdef IMAGE_BL2 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH1_RW, + V2M_MAP_IOFPGA, + ARM_MAP_NS_DRAM1, + {0} +}; +#endif +#ifdef IMAGE_BL32 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_IOFPGA, + MAP_DEVICE0, + {0} +}; +#endif + +ARM_CASSERT_MMAP + +void __init fvp_ve_config_setup(void) +{ + unsigned int sys_id, arch; + + sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); + arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; + + if (arch != ARCH_MODEL_VE) { + ERROR("This firmware is for FVP VE models\n"); + panic(); + } +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return FVP_VE_TIMER_BASE_FREQUENCY; +} diff --git a/plat/arm/board/fvp_ve/fvp_ve_def.h b/plat/arm/board/fvp_ve/fvp_ve_def.h new file mode 100644 index 000000000..565753ae7 --- /dev/null +++ b/plat/arm/board/fvp_ve/fvp_ve_def.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FVP_VE_DEF_H +#define FVP_VE_DEF_H + +#include <lib/utils_def.h> + +/* Default cluster count for FVP VE */ +#define FVP_VE_CLUSTER_COUNT 1 + +/* Default number of CPUs per cluster on FVP VE */ +#define FVP_VE_MAX_CPUS_PER_CLUSTER 1 + +/* Default number of threads per CPU on FVP VE */ +#define FVP_VE_MAX_PE_PER_CPU 1 + +#define FVP_VE_CORE_COUNT 1 + +#define FVP_VE_PRIMARY_CPU 0x0 + +/******************************************************************************* + * FVP memory map related constants + ******************************************************************************/ + +#define FLASH1_BASE 0x0c000000 +#define FLASH1_SIZE 0x04000000 + +/* Aggregate of all devices in the first GB */ +#define DEVICE0_BASE 0x20000000 +#define DEVICE0_SIZE 0x0c200000 + +#define NSRAM_BASE 0x2e000000 +#define NSRAM_SIZE 0x10000 + +#define PCIE_EXP_BASE 0x40000000 +#define TZRNG_BASE 0x7fe60000 + +#define ARCH_MODEL_VE 0x5 + +/* FVP Power controller base address*/ +#define PWRC_BASE UL(0x1c100000) + +/* FVP SP804 timer frequency is 35 MHz*/ +#define SP804_TIMER_CLKMULT 1 +#define SP804_TIMER_CLKDIV 35 + +/* SP810 controller. FVP specific flags */ +#define FVP_SP810_CTRL_TIM0_OV (1 << 16) +#define FVP_SP810_CTRL_TIM1_OV (1 << 18) +#define FVP_SP810_CTRL_TIM2_OV (1 << 20) +#define FVP_SP810_CTRL_TIM3_OV (1 << 22) + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ +/* VE compatible GIC memory map */ +#define VE_GICD_BASE 0x2c001000 +#ifdef ARM_CORTEX_A5 +#define VE_GICC_BASE 0x2c000100 +#else +#define VE_GICC_BASE 0x2c002000 +#endif +#define VE_GICH_BASE 0x2c004000 +#define VE_GICV_BASE 0x2c006000 + +#define FVP_VE_IRQ_TZ_WDOG 56 +#define FVP_VE_IRQ_SEC_SYS_TIMER 57 + +#define V2M_FLASH1_BASE UL(0x0C000000) +#define V2M_FLASH1_SIZE UL(0x04000000) + +#define V2M_MAP_FLASH1_RW MAP_REGION_FLAT(V2M_FLASH1_BASE,\ + V2M_FLASH1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define V2M_MAP_FLASH1_RO MAP_REGION_FLAT(V2M_FLASH1_BASE,\ + V2M_FLASH1_SIZE, \ + MT_RO_DATA | MT_SECURE) + +#endif /* FVP_VE_DEF_H */ diff --git a/plat/arm/board/fvp_ve/fvp_ve_pm.c b/plat/arm/board/fvp_ve/fvp_ve_pm.c new file mode 100644 index 000000000..a4d627b1d --- /dev/null +++ b/plat/arm/board/fvp_ve/fvp_ve_pm.c @@ -0,0 +1,25 @@ +/* +* Copyright (c) 2019, Arm Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include <lib/psci/psci.h> +#include <plat/arm/common/plat_arm.h> + +/******************************************************************************* + * Export the platform handlers via fvp_ve_psci_pm_ops. The ARM Standard + * platform layer will take care of registering the handlers with PSCI. + ******************************************************************************/ +plat_psci_ops_t fvp_ve_psci_pm_ops = { + /* dummy struct */ + .validate_ns_entrypoint = NULL, +}; + +int __init plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + *psci_ops = &fvp_ve_psci_pm_ops; + + return 0; +} diff --git a/plat/arm/board/fvp_ve/fvp_ve_private.h b/plat/arm/board/fvp_ve/fvp_ve_private.h new file mode 100644 index 000000000..5d396bcc9 --- /dev/null +++ b/plat/arm/board/fvp_ve/fvp_ve_private.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FVP_VE_PRIVATE_H +#define FVP_VE_PRIVATE_H + +#include <plat/arm/common/plat_arm.h> + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ + +void fvp_ve_config_setup(void); + +#endif /* FVP_VE_PRIVATE_H */ diff --git a/plat/arm/board/fvp_ve/fvp_ve_security.c b/plat/arm/board/fvp_ve/fvp_ve_security.c new file mode 100644 index 000000000..24465cba2 --- /dev/null +++ b/plat/arm/board/fvp_ve/fvp_ve_security.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * We assume that all security programming is done by the primary core. + */ +void plat_arm_security_setup(void) +{ + /* + * The Base FVP has a TrustZone address space controller, the Foundation + * FVP does not. Trying to program the device on the foundation FVP will + * cause an abort. + * + * If the platform had additional peripheral specific security + * configurations, those would be configured here. + */ + + return; +} diff --git a/plat/arm/board/fvp_ve/fvp_ve_topology.c b/plat/arm/board/fvp_ve/fvp_ve_topology.c new file mode 100644 index 000000000..51cc9da00 --- /dev/null +++ b/plat/arm/board/fvp_ve/fvp_ve_topology.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <platform_def.h> + +#include <drivers/arm/fvp/fvp_pwrc.h> +#include <plat/arm/common/arm_config.h> +#include <plat/arm/common/plat_arm.h> +#include <plat/common/platform.h> + +/* The FVP VE power domain tree descriptor */ +static const unsigned char fvp_ve_power_domain_tree_desc[] = { + 1, + /* No of children for the root node */ + FVP_VE_CLUSTER_COUNT, + /* No of children for the first cluster node */ + FVP_VE_CORE_COUNT, +}; + +/******************************************************************************* + * This function returns the topology according to FVP_VE_CLUSTER_COUNT. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return fvp_ve_power_domain_tree_desc; +} + +/******************************************************************************* + * Currently FVP VE has only been tested with one core, therefore 0 is returned. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + return 0; +} diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h new file mode 100644 index 000000000..1870442f0 --- /dev/null +++ b/plat/arm/board/fvp_ve/include/platform_def.h @@ -0,0 +1,330 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <common/tbbr/tbbr_img_def.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <plat/arm/board/common/v2m_def.h> +#include <plat/common/common_def.h> + +#include "../fvp_ve_def.h" + +#define ARM_CACHE_WRITEBACK_SHIFT 6 + +/* Memory location options for TSP */ +#define ARM_DRAM_ID 2 + +#define ARM_DRAM1_BASE UL(0x80000000) +#define ARM_DRAM1_SIZE UL(0x80000000) +#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - 1) + +#define ARM_DRAM2_BASE UL(0x880000000) +#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE +#define ARM_DRAM2_END (ARM_DRAM2_BASE + \ + ARM_DRAM2_SIZE - 1) + +#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +/* + * The last 2MB is meant to be NOLOAD and will not be zero + * initialized. + */ +#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ + 0x00200000) + + +/* The first 4KB of NS DRAM1 are used as shared memory */ +#define FVP_VE_SHARED_RAM_BASE ARM_NS_DRAM1_BASE +#define FVP_VE_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ + +/* The next 252 kB of NS DRAM is used to load the BL images */ +#define ARM_BL_RAM_BASE (FVP_VE_SHARED_RAM_BASE + \ + FVP_VE_SHARED_RAM_SIZE) +#define ARM_BL_RAM_SIZE (PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE - \ + FVP_VE_SHARED_RAM_SIZE) + + +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE) + +#define ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE) + +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + FVP_VE_SHARED_RAM_BASE, \ + FVP_VE_SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, \ + ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ + ARM_DRAM2_BASE, \ + ARM_DRAM2_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE), \ + MAP_REGION_FLAT( \ + BL_RO_DATA_BASE, \ + BL_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) + +#if USE_COHERENT_MEM +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +/* + * The max number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#define ARM_BL_REGIONS 5 + +#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ + ARM_BL_REGIONS) + +/* Memory mapped Generic timer interfaces */ +#define FVP_VE_TIMER_BASE_FREQUENCY UL(24000000) +#define ARM_SYS_CNTREAD_BASE UL(0x2a800000) +#define ARM_SYS_CNT_BASE_S UL(0x2a820000) +#define ARM_SYS_CNT_BASE_NS UL(0x2a830000) + +#define ARM_CONSOLE_BAUDRATE 115200 + +/* Trusted Watchdog constants */ +#define ARM_SP805_TWDG_BASE UL(0x1C0F0000) +#define ARM_SP805_TWDG_CLK_HZ 32768 +/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 + * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ +#define ARM_TWDG_TIMEOUT_SEC 128 +#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ + ARM_TWDG_TIMEOUT_SEC) + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +/* + * This macro defines the deepest retention state possible. A higher state + * id will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE 1 + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE 2 + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) + +/* + * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base + * and limit. Leave enough space of BL2 meminfo. + */ +#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) +#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ******************************************************************************/ +#define BL1_RO_BASE 0x00000000 +#define BL1_RO_LIMIT PLAT_ARM_TRUSTED_ROM_SIZE +/* + * Put BL1 RW at the top of the memory allocated for BL images in NS DRAM. + */ +#define BL1_RW_BASE (ARM_BL_RAM_BASE + \ + ARM_BL_RAM_SIZE - \ + (PLAT_ARM_MAX_BL1_RW_SIZE)) +#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ + (ARM_BL_RAM_SIZE)) + + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ + +/* + * Put BL2 just below BL1. + */ +#define BL2_BASE (BL1_RW_BASE - FVP_VE_MAX_BL2_SIZE) +#define BL2_LIMIT BL1_RW_BASE + + +/* Put BL32 below BL2 in NS DRAM.*/ +#define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT + +#define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ + - PLAT_ARM_MAX_BL32_SIZE) +#define BL32_PROGBITS_LIMIT BL2_BASE +#define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) + +/* Required platform porting definitions */ +#define PLATFORM_CORE_COUNT 1 +#define PLAT_NUM_PWR_DOMAINS ((FVP_VE_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + 1) + +#define PLAT_MAX_PWR_LVL 2 + +/* + * Other platform porting definitions are provided by included headers + */ + +/* + * Required ARM standard platform porting definitions + */ + +#define PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE 0x00040000 /* 256 KB */ + +#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ + +#define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) + +/* + * Load address of BL33 for this platform port + */ +#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000)) + +/* + * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the + * plat_arm_mmap array defined for each BL stage. + */ +#if defined(IMAGE_BL32) +# define PLAT_ARM_MMAP_ENTRIES 8 +# define MAX_XLAT_TABLES 6 +#else +# define PLAT_ARM_MMAP_ENTRIES 12 +# define MAX_XLAT_TABLES 6 +#endif + +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 + +/* + * FVP_VE_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a + * little space for growth. + */ +#define FVP_VE_MAX_BL2_SIZE 0x11000 + +/* + * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is + * calculated using the current SP_MIN PROGBITS debug size plus the sizes of + * BL2 and BL1-RW + */ +#define PLAT_ARM_MAX_BL32_SIZE 0x3B000 +/* + + * Size of cacheable stacks + */ +#if defined(IMAGE_BL1) +# define PLATFORM_STACK_SIZE 0x440 +#elif defined(IMAGE_BL2) +# define PLATFORM_STACK_SIZE 0x400 +#elif defined(IMAGE_BL32) +# define PLATFORM_STACK_SIZE 0x440 +#endif + +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/* Reserve the last block of flash for PSCI MEM PROTECT flag */ +#define PLAT_ARM_FIP_BASE V2M_FLASH1_BASE +#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE) + +#define PLAT_ARM_NVM_BASE V2M_FLASH1_BASE +#define PLAT_ARM_NVM_SIZE (V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE) + +/* + * PL011 related constants + */ +#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ + +#define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE +#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ + +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ + +/* System timer related constants */ +#define PLAT_ARM_NSTIMER_FRAME_ID 1 + +/* Mailbox base address */ +#define FVP_VE_TRUSTED_MAILBOX_BASE FVP_VE_SHARED_RAM_BASE + +/* + * GIC related constants to cater for GICv2 + */ +#define PLAT_ARM_GICD_BASE VE_GICD_BASE +#define PLAT_ARM_GICC_BASE VE_GICC_BASE + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(FVP_VE_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(FVP_VE_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_LEVEL) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + +#endif /* PLATFORM_H */ diff --git a/plat/arm/board/fvp_ve/platform.mk b/plat/arm/board/fvp_ve/platform.mk new file mode 100644 index 000000000..f9ced2cc3 --- /dev/null +++ b/plat/arm/board/fvp_ve/platform.mk @@ -0,0 +1,125 @@ +# +# Copyright (c) 2019, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +ifdef ARM_CORTEX_A5 +# Use the SP804 timer instead of the generic one +FVP_VE_USE_SP804_TIMER := 1 +$(eval $(call add_define,FVP_VE_USE_SP804_TIMER)) +BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c +endif + +FVP_VE_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c \ + plat/arm/common/arm_gicv2.c + +FVP_VE_SECURITY_SOURCES := plat/arm/board/fvp_ve/fvp_ve_security.c + +PLAT_INCLUDES := -Iplat/arm/board/fvp_ve/include + +PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp_ve/fvp_ve_common.c \ + plat/arm/common/${ARCH}/arm_helpers.S \ + plat/arm/common/arm_common.c \ + plat/arm/common/arm_console.c \ + drivers/arm/pl011/${ARCH}/pl011_console.S \ + plat/arm/board/common/${ARCH}/board_arm_helpers.S + +ifdef ARM_CORTEX_A5 +FVP_VE_CPU_LIBS := lib/cpus/aarch32/cortex_a5.S +else +FVP_VE_CPU_LIBS := lib/cpus/aarch32/cortex_a7.S +endif + +BL1_SOURCES += drivers/arm/sp805/sp805.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + plat/arm/common/arm_bl1_setup.c \ + plat/arm/common/arm_err.c \ + plat/arm/common/arm_io_storage.c \ + drivers/cfi/v2m/v2m_flash.c \ + plat/arm/board/fvp_ve/${ARCH}/fvp_ve_helpers.S \ + plat/arm/board/fvp_ve/fvp_ve_bl1_setup.c \ + lib/aarch32/arm32_aeabi_divmod.c \ + lib/aarch32/arm32_aeabi_divmod_a32.S \ + ${FVP_VE_CPU_LIBS} \ + ${DYN_CFG_SOURCES} + +BL2_SOURCES += plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c \ + lib/aarch32/arm32_aeabi_divmod.c \ + lib/aarch32/arm32_aeabi_divmod_a32.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/cfi/v2m/v2m_flash.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + plat/arm/common/arm_bl2_setup.c \ + plat/arm/common/arm_err.c \ + plat/arm/common/arm_io_storage.c \ + plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c \ + plat/arm/common/arm_image_load.c \ + common/desc_image_load.c \ + ${DYN_CFG_SOURCES} \ + ${FVP_VE_SECURITY_SOURCES} + +# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) +ifdef UNIX_MK + +FDT_SOURCES += plat/arm/board/fvp_ve/fdts/fvp_ve_tb_fw_config.dts + +FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/fvp_ve_tb_fw_config.dtb + +# Add the TB_FW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config)) + +FDT_SOURCES += ${FVP_HW_CONFIG_DTS} +$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb, \ + fdts/$(notdir ${FVP_HW_CONFIG_DTS}))) +# Add the HW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config)) +endif + +NEED_BL32 := yes + +# Modification of arm_common.mk + +# Process ARM_DISABLE_TRUSTED_WDOG flag +# By default, Trusted Watchdog is always enabled unless SPIN_ON_BL1_EXIT is set +ARM_DISABLE_TRUSTED_WDOG := 0 +ifeq (${SPIN_ON_BL1_EXIT}, 1) +ARM_DISABLE_TRUSTED_WDOG := 1 +endif +$(eval $(call assert_boolean,ARM_DISABLE_TRUSTED_WDOG)) +$(eval $(call add_define,ARM_DISABLE_TRUSTED_WDOG)) + +# Use translation tables library v1 if using Cortex-A5 +ifdef ARM_CORTEX_A5 +ARM_XLAT_TABLES_LIB_V1 := 1 +else +ARM_XLAT_TABLES_LIB_V1 := 0 +endif +$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1)) +$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1)) + +MULTI_CONSOLE_API := 1 + +ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1) + # Only use nonlpae version of xlatv1 otherwise use xlat v2 + PLAT_BL_COMMON_SOURCES += lib/xlat_tables/${ARCH}/nonlpae_tables.c +else + include lib/xlat_tables_v2/xlat_tables.mk + PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} +endif + +# Add `libfdt` and Arm common helpers required for Dynamic Config +include lib/libfdt/libfdt.mk + +DYN_CFG_SOURCES += plat/arm/common/arm_dyn_cfg.c \ + plat/arm/common/arm_dyn_cfg_helpers.c \ + common/fdt_wrappers.c + diff --git a/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c b/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c new file mode 100644 index 000000000..e6a1bbec2 --- /dev/null +++ b/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <plat/arm/common/plat_arm.h> + +void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); +} diff --git a/plat/arm/board/fvp_ve/sp_min/sp_min-fvp_ve.mk b/plat/arm/board/fvp_ve/sp_min/sp_min-fvp_ve.mk new file mode 100644 index 000000000..4ca810d3f --- /dev/null +++ b/plat/arm/board/fvp_ve/sp_min/sp_min-fvp_ve.mk @@ -0,0 +1,22 @@ +# +# Copyright (c) 2019, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# SP_MIN source files specific to FVP platform +BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \ + lib/utils/mem_region.c \ + plat/arm/board/fvp_ve/aarch32/fvp_ve_helpers.S \ + drivers/arm/fvp/fvp_pwrc.c \ + plat/arm/board/fvp_ve/fvp_ve_pm.c \ + plat/arm/board/fvp_ve/fvp_ve_topology.c \ + plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c \ + lib/aarch32/arm32_aeabi_divmod.c \ + lib/aarch32/arm32_aeabi_divmod_a32.S \ + plat/arm/common/sp_min/arm_sp_min_setup.c \ + plat/common/aarch32/platform_mp_stack.S \ + plat/common/plat_psci_common.c \ + ${FVP_VE_CPU_LIBS} \ + ${FVP_VE_GIC_SOURCES} \ + ${FVP_VE_SECURITY_SOURCES} diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index 6575811a6..e44791b49 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk @@ -105,7 +105,10 @@ bl1_romlib.bin : $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/romlib/romlib.bin ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT) # Errata workarounds for Cortex-A53: +ERRATA_A53_819472 := 1 +ERRATA_A53_824069 := 1 ERRATA_A53_826319 := 1 +ERRATA_A53_827319 := 1 ERRATA_A53_835769 := 1 ERRATA_A53_836870 := 1 ERRATA_A53_843419 := 1 @@ -115,6 +118,8 @@ ERRATA_A53_855873 := 1 ERRATA_A57_806969 := 0 ERRATA_A57_813419 := 1 ERRATA_A57_813420 := 1 +ERRATA_A57_814670 := 1 +ERRATA_A57_817169 := 1 ERRATA_A57_826974 := 1 ERRATA_A57_826977 := 1 ERRATA_A57_828024 := 1 diff --git a/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S b/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S index 6eb01aa57..c03185aea 100644 --- a/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S +++ b/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S @@ -1,12 +1,12 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch.h> #include <asm_macros.S> -#include <cortex_ares.h> +#include <neoverse_n1.h> #include <cpu_macros.S> #include <platform_def.h> @@ -58,17 +58,17 @@ endfunc plat_arm_calc_core_pos */ func plat_reset_handler - jump_if_cpu_midr CORTEX_ARES_MIDR, ARES + jump_if_cpu_midr NEOVERSE_N1_MIDR, N1 ret /* ----------------------------------------------------- * Disable CPU power down bit in power control register * ----------------------------------------------------- */ -ARES: - mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 - bic x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK - msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 +N1: + mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 + bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK + msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 isb ret endfunc plat_reset_handler diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h index 7b8c367a2..83b9f52d2 100644 --- a/plat/arm/board/n1sdp/include/platform_def.h +++ b/plat/arm/board/n1sdp/include/platform_def.h @@ -15,14 +15,14 @@ #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 -#define PLAT_ARM_BL31_RUN_UART_BASE 0x2A410000 -#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 50000000 +#define PLAT_ARM_RUN_UART_BASE 0x2A410000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ 50000000 #define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000 -#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE -#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk index 2b68f657e..653d08106 100644 --- a/plat/arm/board/n1sdp/platform.mk +++ b/plat/arm/board/n1sdp/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -12,7 +12,7 @@ INTERCONNECT_SOURCES := ${N1SDP_BASE}/n1sdp_interconnect.c PLAT_INCLUDES := -I${N1SDP_BASE}/include -N1SDP_CPU_SOURCES := lib/cpus/aarch64/cortex_ares.S +N1SDP_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S N1SDP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ diff --git a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts b/plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts index 3dedf1de2..41769217a 100644 --- a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts +++ b/plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ /dts-v1/; / { /* compatible string */ - compatible = "arm,sgi-clark"; + compatible = "arm,rd-e1edge"; /* * Place holder for system-id node with default values. The diff --git a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts b/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts index 766dc00f5..766dc00f5 100644 --- a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts +++ b/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts diff --git a/plat/arm/board/sgiclarkh/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h index fe8907bee..954a1cd48 100644 --- a/plat/arm/board/sgiclarkh/include/platform_def.h +++ b/plat/arm/board/rde1edge/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,8 +18,8 @@ #define PLAT_CSS_MHU_BASE UL(0x45400000) /* Base address of DMC-620 instances */ -#define SGICLARKH_DMC620_BASE0 UL(0x4e000000) -#define SGICLARKH_DMC620_BASE1 UL(0x4e100000) +#define RDE1EDGE_DMC620_BASE0 UL(0x4e000000) +#define RDE1EDGE_DMC620_BASE1 UL(0x4e100000) #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 diff --git a/plat/arm/board/sgiclarkh/platform.mk b/plat/arm/board/rde1edge/platform.mk index 222ca6059..833bb821a 100644 --- a/plat/arm/board/sgiclarkh/platform.mk +++ b/plat/arm/board/rde1edge/platform.mk @@ -1,39 +1,39 @@ # -# Copyright (c) 2018, Arm Limited. All rights reserved. +# Copyright (c) 2018-2019, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include plat/arm/css/sgi/sgi-common.mk -SGICLARKH_BASE = plat/arm/board/sgiclarkh +RDE1EDGE_BASE = plat/arm/board/rde1edge -PLAT_INCLUDES += -I${SGICLARKH_BASE}/include/ +PLAT_INCLUDES += -I${RDE1EDGE_BASE}/include/ -SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_helios.S +SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S BL1_SOURCES += ${SGI_CPU_SOURCES} -BL2_SOURCES += ${SGICLARKH_BASE}/sgiclarkh_plat.c \ - ${SGICLARKH_BASE}/sgiclarkh_security.c \ +BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \ + ${RDE1EDGE_BASE}/rde1edge_security.c \ drivers/arm/tzc/tzc_dmc620.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c BL31_SOURCES += ${SGI_CPU_SOURCES} \ - ${SGICLARKH_BASE}/sgiclarkh_plat.c \ + ${RDE1EDGE_BASE}/rde1edge_plat.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c # Add the FDT_SOURCES and options for Dynamic Config -FDT_SOURCES += ${SGICLARKH_BASE}/fdts/${PLAT}_tb_fw_config.dts +FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb # Add the TB_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config)) -FDT_SOURCES += ${SGICLARKH_BASE}/fdts/${PLAT}_nt_fw_config.dts +FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb # Add the NT_FW_CONFIG to FIP and specify the same to certtool diff --git a/plat/arm/board/sgiclarkh/sgiclarkh_plat.c b/plat/arm/board/rde1edge/rde1edge_plat.c index a1b8d621d..a1b8d621d 100644 --- a/plat/arm/board/sgiclarkh/sgiclarkh_plat.c +++ b/plat/arm/board/rde1edge/rde1edge_plat.c diff --git a/plat/arm/board/rde1edge/rde1edge_security.c b/plat/arm/board/rde1edge/rde1edge_security.c new file mode 100644 index 000000000..2123e0931 --- /dev/null +++ b/plat/arm/board/rde1edge/rde1edge_security.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <platform_def.h> + +#include <common/debug.h> +#include <drivers/arm/tzc_dmc620.h> + +uintptr_t rde1edge_dmc_base[] = { + RDE1EDGE_DMC620_BASE0, + RDE1EDGE_DMC620_BASE1 +}; + +static const tzc_dmc620_driver_data_t rde1edge_plat_driver_data = { + .dmc_base = rde1edge_dmc_base, + .dmc_count = ARRAY_SIZE(rde1edge_dmc_base) +}; + +static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = { + { + .region_base = ARM_AP_TZC_DRAM1_BASE, + .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1, + .sec_attr = TZC_DMC620_REGION_S_RDWR + } +}; + +static const tzc_dmc620_config_data_t rde1edge_plat_config_data = { + .plat_drv_data = &rde1edge_plat_driver_data, + .plat_acc_addr_data = rde1edge_acc_addr_data, + .acc_addr_count = ARRAY_SIZE(rde1edge_acc_addr_data) +}; + +/* Initialize the secure environment */ +void plat_arm_security_setup(void) +{ + arm_tzc_dmc620_setup(&rde1edge_plat_config_data); +} diff --git a/plat/arm/board/sgiclarka/fdts/sgiclarka_nt_fw_config.dts b/plat/arm/board/rdn1edge/fdts/rdn1edge_nt_fw_config.dts index 43bd85692..fff587476 100644 --- a/plat/arm/board/sgiclarka/fdts/sgiclarka_nt_fw_config.dts +++ b/plat/arm/board/rdn1edge/fdts/rdn1edge_nt_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ /dts-v1/; / { /* compatible string */ - compatible = "arm,sgi-clark"; + compatible = "arm,rd-n1edge"; /* * Place holder for system-id node with default values. The diff --git a/plat/arm/board/sgiclarka/fdts/sgiclarka_tb_fw_config.dts b/plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts index b14d7adca..b14d7adca 100644 --- a/plat/arm/board/sgiclarka/fdts/sgiclarka_tb_fw_config.dts +++ b/plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts diff --git a/plat/arm/board/sgiclarka/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h index d2cdb4974..2ca0dd4ec 100644 --- a/plat/arm/board/sgiclarka/include/platform_def.h +++ b/plat/arm/board/rdn1edge/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,8 +18,8 @@ #define PLAT_CSS_MHU_BASE UL(0x45400000) /* Base address of DMC-620 instances */ -#define SGICLARKA_DMC620_BASE0 UL(0x4e000000) -#define SGICLARKA_DMC620_BASE1 UL(0x4e100000) +#define RDN1EDGE_DMC620_BASE0 UL(0x4e000000) +#define RDN1EDGE_DMC620_BASE1 UL(0x4e100000) /* System power domain level */ #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 diff --git a/plat/arm/board/sgiclarka/platform.mk b/plat/arm/board/rdn1edge/platform.mk index 1a8b157de..cacdaa13c 100644 --- a/plat/arm/board/sgiclarka/platform.mk +++ b/plat/arm/board/rdn1edge/platform.mk @@ -1,39 +1,39 @@ # -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include plat/arm/css/sgi/sgi-common.mk -SGICLARKA_BASE = plat/arm/board/sgiclarka +RDN1EDGE_BASE = plat/arm/board/rdn1edge -PLAT_INCLUDES += -I${SGICLARKA_BASE}/include/ +PLAT_INCLUDES += -I${RDN1EDGE_BASE}/include/ -SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_ares.S +SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S BL1_SOURCES += ${SGI_CPU_SOURCES} -BL2_SOURCES += ${SGICLARKA_BASE}/sgiclarka_plat.c \ - ${SGICLARKA_BASE}/sgiclarka_security.c \ +BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_plat.c \ + ${RDN1EDGE_BASE}/rdn1edge_security.c \ drivers/arm/tzc/tzc_dmc620.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c BL31_SOURCES += ${SGI_CPU_SOURCES} \ - ${SGICLARKA_BASE}/sgiclarka_plat.c \ + ${RDN1EDGE_BASE}/rdn1edge_plat.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c # Add the FDT_SOURCES and options for Dynamic Config -FDT_SOURCES += ${SGICLARKA_BASE}/fdts/${PLAT}_tb_fw_config.dts +FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb # Add the TB_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config)) -FDT_SOURCES += ${SGICLARKA_BASE}/fdts/${PLAT}_nt_fw_config.dts +FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb # Add the NT_FW_CONFIG to FIP and specify the same to certtool diff --git a/plat/arm/board/sgiclarka/sgiclarka_plat.c b/plat/arm/board/rdn1edge/rdn1edge_plat.c index 3b7e5ee4e..3b7e5ee4e 100644 --- a/plat/arm/board/sgiclarka/sgiclarka_plat.c +++ b/plat/arm/board/rdn1edge/rdn1edge_plat.c diff --git a/plat/arm/board/rdn1edge/rdn1edge_security.c b/plat/arm/board/rdn1edge/rdn1edge_security.c new file mode 100644 index 000000000..ffa893524 --- /dev/null +++ b/plat/arm/board/rdn1edge/rdn1edge_security.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <platform_def.h> + +#include <common/debug.h> +#include <drivers/arm/tzc_dmc620.h> + +uintptr_t rdn1edge_dmc_base[] = { + RDN1EDGE_DMC620_BASE0, + RDN1EDGE_DMC620_BASE1 +}; + +static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = { + .dmc_base = rdn1edge_dmc_base, + .dmc_count = ARRAY_SIZE(rdn1edge_dmc_base) +}; + +static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = { + { + .region_base = ARM_AP_TZC_DRAM1_BASE, + .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1, + .sec_attr = TZC_DMC620_REGION_S_RDWR + } +}; + +static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = { + .plat_drv_data = &rdn1edge_plat_driver_data, + .plat_acc_addr_data = rdn1edge_acc_addr_data, + .acc_addr_count = ARRAY_SIZE(rdn1edge_acc_addr_data) +}; + +/* Initialize the secure environment */ +void plat_arm_security_setup(void) +{ + arm_tzc_dmc620_setup(&rdn1edge_plat_config_data); +} diff --git a/plat/arm/board/sgiclarka/sgiclarka_security.c b/plat/arm/board/sgiclarka/sgiclarka_security.c deleted file mode 100644 index c455111d1..000000000 --- a/plat/arm/board/sgiclarka/sgiclarka_security.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <platform_def.h> - -#include <common/debug.h> -#include <drivers/arm/tzc_dmc620.h> - -uintptr_t sgiclarka_dmc_base[] = { - SGICLARKA_DMC620_BASE0, - SGICLARKA_DMC620_BASE1 -}; - -static const tzc_dmc620_driver_data_t sgiclarka_plat_driver_data = { - .dmc_base = sgiclarka_dmc_base, - .dmc_count = ARRAY_SIZE(sgiclarka_dmc_base) -}; - -static const tzc_dmc620_acc_addr_data_t sgiclarka_acc_addr_data[] = { - { - .region_base = ARM_AP_TZC_DRAM1_BASE, - .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1, - .sec_attr = TZC_DMC620_REGION_S_RDWR - } -}; - -static const tzc_dmc620_config_data_t sgiclarka_plat_config_data = { - .plat_drv_data = &sgiclarka_plat_driver_data, - .plat_acc_addr_data = sgiclarka_acc_addr_data, - .acc_addr_count = ARRAY_SIZE(sgiclarka_acc_addr_data) -}; - -/* Initialize the secure environment */ -void plat_arm_security_setup(void) -{ - arm_tzc_dmc620_setup(&sgiclarka_plat_config_data); -} diff --git a/plat/arm/board/sgiclarkh/sgiclarkh_security.c b/plat/arm/board/sgiclarkh/sgiclarkh_security.c deleted file mode 100644 index aaf9691ce..000000000 --- a/plat/arm/board/sgiclarkh/sgiclarkh_security.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <platform_def.h> - -#include <common/debug.h> -#include <drivers/arm/tzc_dmc620.h> - -uintptr_t sgiclarkh_dmc_base[] = { - SGICLARKH_DMC620_BASE0, - SGICLARKH_DMC620_BASE1 -}; - -static const tzc_dmc620_driver_data_t sgiclarkh_plat_driver_data = { - .dmc_base = sgiclarkh_dmc_base, - .dmc_count = ARRAY_SIZE(sgiclarkh_dmc_base) -}; - -static const tzc_dmc620_acc_addr_data_t sgiclarkh_acc_addr_data[] = { - { - .region_base = ARM_AP_TZC_DRAM1_BASE, - .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1, - .sec_attr = TZC_DMC620_REGION_S_RDWR - } -}; - -static const tzc_dmc620_config_data_t sgiclarkh_plat_config_data = { - .plat_drv_data = &sgiclarkh_plat_driver_data, - .plat_acc_addr_data = sgiclarkh_acc_addr_data, - .acc_addr_count = ARRAY_SIZE(sgiclarkh_acc_addr_data) -}; - -/* Initialize the secure environment */ -void plat_arm_security_setup(void) -{ - arm_tzc_dmc620_setup(&sgiclarkh_plat_config_data); -} diff --git a/plat/arm/common/aarch64/arm_pauth.c b/plat/arm/common/aarch64/arm_pauth.c new file mode 100644 index 000000000..c8471190a --- /dev/null +++ b/plat/arm/common/aarch64/arm_pauth.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <cdefs.h> +#include <stdint.h> + +/* + * Instruction pointer authentication key A. The low 64-bit are at [0], and the + * high bits at [1]. They are run-time constants so they are placed in the + * rodata section. They are written before MMU is turned on and the permissions + * are effective. + */ +uint64_t plat_apiakey[2] __section("rodata.apiakey"); + +/* + * This is only a toy implementation to generate a seemingly random 128-bit key + * from sp and x30 values. A production system must re-implement this function + * to generate keys from a reliable randomness source. + */ +uint64_t *plat_init_apiakey(void) +{ + uintptr_t return_addr = (uintptr_t)__builtin_return_address(0U); + uintptr_t frame_addr = (uintptr_t)__builtin_frame_address(0U); + + plat_apiakey[0] = (return_addr << 13) ^ frame_addr; + plat_apiakey[1] = (frame_addr << 15) ^ return_addr; + + return plat_apiakey; +} diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index fd4809c16..1e9edefd5 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -155,8 +155,12 @@ void arm_bl1_platform_setup(void) * Allow access to the System counter timer module and program * counter frequency for non secure images during FWU */ +#ifdef ARM_SYS_TIMCTL_BASE arm_configure_sys_timer(); +#endif +#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER) write_cntfrq_el0(plat_get_syscnt_freq2()); +#endif } void bl1_platform_setup(void) diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index f18a9af69..5e890ed17 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -236,6 +236,11 @@ BL31_SOURCES += lib/extensions/ras/std_err_record.c \ lib/extensions/ras/ras_common.c endif +# Pointer Authentication sources +ifeq (${ENABLE_PAUTH}, 1) +PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c +endif + # SPM uses libfdt in Arm platforms ifeq (${SPM_MM},0) ifeq (${ENABLE_SPM},1) diff --git a/plat/arm/common/arm_console.c b/plat/arm/common/arm_console.c index 03670858c..84886b470 100644 --- a/plat/arm/common/arm_console.c +++ b/plat/arm/common/arm_console.c @@ -61,8 +61,8 @@ void arm_console_boot_end(void) void arm_console_runtime_init(void) { #if MULTI_CONSOLE_API - int rc = console_pl011_register(PLAT_ARM_BL31_RUN_UART_BASE, - PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ, + int rc = console_pl011_register(PLAT_ARM_RUN_UART_BASE, + PLAT_ARM_RUN_UART_CLK_IN_HZ, ARM_CONSOLE_BAUDRATE, &arm_runtime_console); if (rc == 0) @@ -70,8 +70,8 @@ void arm_console_runtime_init(void) console_set_scope(&arm_runtime_console.console, CONSOLE_FLAG_RUNTIME); #else - (void)console_init(PLAT_ARM_BL31_RUN_UART_BASE, - PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ, + (void)console_init(PLAT_ARM_RUN_UART_BASE, + PLAT_ARM_RUN_UART_CLK_IN_HZ, ARM_CONSOLE_BAUDRATE); #endif /* MULTI_CONSOLE_API */ } diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c index 1c58649ba..9a5364952 100644 --- a/plat/arm/common/arm_dyn_cfg.c +++ b/plat/arm/common/arm_dyn_cfg.c @@ -243,10 +243,11 @@ void arm_bl2_dyn_cfg_init(void) if (check_uptr_overflow(image_base, image_size)) continue; +#ifdef BL31_BASE /* Ensure the configs don't overlap with BL31 */ if ((image_base > BL31_BASE) || ((image_base + image_size) > BL31_BASE)) continue; - +#endif /* Ensure the configs are loaded in a valid address */ if (image_base < ARM_BL_RAM_BASE) continue; diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c index c0ea027b8..bb69914ae 100644 --- a/plat/arm/common/sp_min/arm_sp_min_setup.c +++ b/plat/arm/common/sp_min/arm_sp_min_setup.c @@ -193,12 +193,14 @@ void sp_min_platform_setup(void) #endif /* Enable and initialize the System level generic timer */ +#ifdef ARM_SYS_CNTCTL_BASE mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0U) | CNTCR_EN); - +#endif +#ifdef ARM_SYS_TIMCTL_BASE /* Allow access to the System counter timer module */ arm_configure_sys_timer(); - +#endif /* Initialize power controller before setting up topology */ plat_arm_pwrc_setup(); } diff --git a/plat/arm/css/sgi/aarch64/sgi_helper.S b/plat/arm/css/sgi/aarch64/sgi_helper.S index d79f1aa21..b80903d06 100644 --- a/plat/arm/css/sgi/aarch64/sgi_helper.S +++ b/plat/arm/css/sgi/aarch64/sgi_helper.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,7 +8,7 @@ #include <asm_macros.S> #include <platform_def.h> #include <cortex_a75.h> -#include <cortex_ares.h> +#include <neoverse_n1.h> #include <cpu_macros.S> .globl plat_arm_calc_core_pos @@ -59,7 +59,7 @@ endfunc plat_arm_calc_core_pos */ func plat_reset_handler jump_if_cpu_midr CORTEX_A75_MIDR, A75 - jump_if_cpu_midr CORTEX_ARES_MIDR, ARES + jump_if_cpu_midr NEOVERSE_N1_MIDR, N1 ret /* ----------------------------------------------------- @@ -73,10 +73,10 @@ A75: isb ret -ARES: - mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 - bic x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK - msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 +N1: + mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 + bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK + msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 isb ret endfunc plat_reset_handler diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h index e9b96dd46..c75f2132b 100644 --- a/plat/arm/css/sgi/include/sgi_variant.h +++ b/plat/arm/css/sgi/include/sgi_variant.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,9 +10,9 @@ /* SSC_VERSION values for SGI575 */ #define SGI575_SSC_VER_PART_NUM 0x0783 -/* SID Version values for SGI-Clark */ -#define SGI_CLARK_SID_VER_PART_NUM 0x0786 -#define SGI_CLARK_HELIOS_CONFIG_ID 0x2 +/* SID Version values for RD-N1E1-Edge */ +#define RD_N1E1_EDGE_SID_VER_PART_NUM 0x0786 +#define RD_E1_EDGE_CONFIG_ID 0x2 /* Structure containing SGI platform variant information */ typedef struct sgi_platform_info { diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c index bfcb521a3..8fa5b01b2 100644 --- a/plat/arm/css/sgi/sgi_bl31_setup.c +++ b/plat/arm/css/sgi/sgi_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ static scmi_channel_plat_info_t sgi575_scmi_plat_info = { .ring_doorbell = &mhu_ring_doorbell, }; -static scmi_channel_plat_info_t sgi_clark_scmi_plat_info = { +static scmi_channel_plat_info_t rd_n1e1_edge_scmi_plat_info = { .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), .db_preserve_mask = 0xfffffffe, @@ -37,8 +37,8 @@ static scmi_channel_plat_info_t sgi_clark_scmi_plat_info = { scmi_channel_plat_info_t *plat_css_get_scmi_info() { - if (sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM) - return &sgi_clark_scmi_plat_info; + if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) + return &rd_n1e1_edge_scmi_plat_info; else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM) return &sgi575_scmi_plat_info; else @@ -65,9 +65,9 @@ void bl31_platform_setup(void) const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) { - /* For SGI-Clark.Helios platform only CPU ON/OFF is supported */ - if ((sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM) && - (sgi_plat_info.config_id == SGI_CLARK_HELIOS_CONFIG_ID)) { + /* For RD-E1-Edge platform only CPU ON/OFF is supported */ + if ((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) && + (sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)) { ops->cpu_standby = NULL; ops->system_off = NULL; ops->system_reset = NULL; diff --git a/plat/arm/css/sgi/sgi_topology.c b/plat/arm/css/sgi/sgi_topology.c index dafaf40bf..f9dbdefe9 100644 --- a/plat/arm/css/sgi/sgi_topology.c +++ b/plat/arm/css/sgi/sgi_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,8 +21,8 @@ const unsigned char sgi_pd_tree_desc[] = { CSS_SGI_MAX_CPUS_PER_CLUSTER }; -/* SGI-Clark.Helios platform consists of 16 physical CPUS and 32 threads */ -const unsigned char sgi_clark_helios_pd_tree_desc[] = { +/* RD-E1-Edge platform consists of 16 physical CPUS and 32 threads */ +const unsigned char rd_e1_edge_pd_tree_desc[] = { PLAT_ARM_CLUSTER_COUNT, CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, @@ -49,9 +49,9 @@ const unsigned char sgi_clark_helios_pd_tree_desc[] = { ******************************************************************************/ const unsigned char *plat_get_power_domain_tree_desc(void) { - if (sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM && - sgi_plat_info.config_id == SGI_CLARK_HELIOS_CONFIG_ID) - return sgi_clark_helios_pd_tree_desc; + if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM && + sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID) + return rd_e1_edge_pd_tree_desc; else return sgi_pd_tree_desc; } diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S index 972a118a4..f9780e80c 100644 --- a/plat/common/aarch64/platform_mp_stack.S +++ b/plat/common/aarch64/platform_mp_stack.S @@ -14,13 +14,13 @@ .weak plat_set_my_stack /* --------------------------------------------------------------------- - * When the compatility layer is disabled, the new platform APIs - * viz plat_get_my_stack() and plat_set_my_stack() are - * supported by the platform and the previous APIs platform_get_stack() - * and platform_set_stack() are defined in terms of new APIs making use - * of the fact that they are only ever invoked for the current CPU. - * This is to enable components of Trusted Firmware like SPDs using the - * old platform APIs to continue to work. + * When the compatility layer is disabled, the platform APIs + * plat_get_my_stack() and plat_set_my_stack() are supported by the + * platform and the previous APIs platform_get_stack() and + * platform_set_stack() are defined in terms of new APIs making use of + * the fact that they are only ever invoked for the current CPU. This + * is to enable components of Trusted Firmware like SPDs using the old + * platform APIs to continue to work. * -------------------------------------------------------------------- */ diff --git a/plat/common/plat_bl_common.c b/plat/common/plat_bl_common.c index 2357edfa9..b46656c7a 100644 --- a/plat/common/plat_bl_common.c +++ b/plat/common/plat_bl_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,9 +10,6 @@ #include <arch_helpers.h> #include <common/bl_common.h> #include <common/debug.h> -#if TRUSTED_BOARD_BOOT -#include <drivers/auth/mbedtls/mbedtls_config.h> -#endif #include <lib/xlat_tables/xlat_tables_compat.h> #include <plat/common/platform.h> @@ -26,7 +23,6 @@ #pragma weak bl2_plat_handle_pre_image_load #pragma weak bl2_plat_handle_post_image_load #pragma weak plat_try_next_boot_source -#pragma weak plat_get_mbedtls_heap void bl2_el3_plat_prepare_exit(void) { @@ -57,24 +53,6 @@ int plat_try_next_boot_source(void) return 0; } -#if TRUSTED_BOARD_BOOT -/* - * The following default implementation of the function simply returns the - * by-default allocated heap. - */ -int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) -{ - static unsigned char heap[TF_MBEDTLS_HEAP_SIZE]; - - assert(heap_addr != NULL); - assert(heap_size != NULL); - - *heap_addr = heap; - *heap_size = sizeof(heap); - return 0; -} -#endif /* TRUSTED_BOARD_BOOT */ - /* * Set up the page tables for the generic and platform-specific memory regions. * The size of the Trusted SRAM seen by the BL image must be specified as well diff --git a/plat/imx/common/plat_imx8_gic.c b/plat/imx/common/plat_imx8_gic.c index 27c525b72..3a7dcfec6 100644 --- a/plat/imx/common/plat_imx8_gic.c +++ b/plat/imx/common/plat_imx8_gic.c @@ -9,6 +9,8 @@ #include <common/bl_common.h> #include <common/interrupt_props.h> #include <drivers/arm/gicv3.h> +#include <drivers/arm/arm_gicv3_common.h> +#include <lib/mmio.h> #include <lib/utils.h> #include <plat/common/platform.h> @@ -52,8 +54,27 @@ void plat_gic_driver_init(void) #endif } +static __inline void plat_gicr_exit_sleep(void) +{ + unsigned int val = mmio_read_32(PLAT_GICR_BASE + GICR_WAKER); + + /* + * ProcessorSleep bit can ONLY be set to zero when + * Quiescent bit and Sleep bit are both zero, so + * need to make sure Quiescent bit and Sleep bit + * are zero before clearing ProcessorSleep bit. + */ + if (val & WAKER_QSC_BIT) { + mmio_write_32(PLAT_GICR_BASE + GICR_WAKER, val & ~WAKER_SL_BIT); + /* Wait till the WAKER_QSC_BIT changes to 0 */ + while ((mmio_read_32(PLAT_GICR_BASE + GICR_WAKER) & WAKER_QSC_BIT) != 0U) + ; + } +} + void plat_gic_init(void) { + plat_gicr_exit_sleep(); gicv3_distif_init(); gicv3_rdistif_init(plat_my_core_pos()); gicv3_cpuif_enable(plat_my_core_pos()); diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c index b18edd96d..99fa9807a 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c @@ -84,6 +84,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); } + /* config CAAM JRaMID set MID to Cortex A */ + mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); + mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); + mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); + #if DEBUG_CONSOLE static console_uart_t console; diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h index 4957582ad..5c5b0a5f9 100644 --- a/plat/imx/imx8m/imx8mq/include/platform_def.h +++ b/plat/imx/imx8m/imx8mq/include/platform_def.h @@ -119,3 +119,8 @@ #define DEBUG_CONSOLE 0 #define IMX_WDOG_B_RESET #define PLAT_IMX8M 1 + +#define CAAM_JR0MID U(0x30900010) +#define CAAM_JR1MID U(0x30900018) +#define CAAM_JR2MID U(0x30900020) +#define CAAM_NS_MID U(0x1) diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk index d9eec4d37..2a2f2782d 100644 --- a/plat/nvidia/tegra/common/tegra_common.mk +++ b/plat/nvidia/tegra/common/tegra_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -22,6 +22,7 @@ TEGRA_GICv2_SOURCES := drivers/arm/gic/common/gic_common.c \ BL31_SOURCES += drivers/console/aarch64/console.S \ drivers/delay_timer/delay_timer.c \ + drivers/io/io_storage.c \ ${TEGRA_GICv2_SOURCES} \ ${COMMON_DIR}/aarch64/tegra_helpers.S \ ${COMMON_DIR}/drivers/pmc/pmc.c \ @@ -29,6 +30,7 @@ BL31_SOURCES += drivers/console/aarch64/console.S \ ${COMMON_DIR}/tegra_bl31_setup.c \ ${COMMON_DIR}/tegra_delay_timer.c \ ${COMMON_DIR}/tegra_fiq_glue.c \ + ${COMMON_DIR}/tegra_io_storage.c \ ${COMMON_DIR}/tegra_platform.c \ ${COMMON_DIR}/tegra_pm.c \ ${COMMON_DIR}/tegra_sip_calls.c \ diff --git a/plat/nvidia/tegra/common/tegra_io_storage.c b/plat/nvidia/tegra/common/tegra_io_storage.c new file mode 100644 index 000000000..21641aad8 --- /dev/null +++ b/plat/nvidia/tegra/common/tegra_io_storage.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2019, NVIDIA Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <errno.h> +#include <plat/common/platform.h> + +/* + * Return an IO device handle and specification which can be used to access + * an image. Use this to enforce platform load policy. + * + * This function is not supported at this time + */ +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + return -ENOTSUP; +} diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index f68b8989b..eb55def4a 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -66,4 +66,10 @@ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */ +/******************************************************************************* + * Dummy macros to compile io_storage support + ******************************************************************************/ +#define MAX_IO_DEVICES U(0) +#define MAX_IO_HANDLES U(0) + #endif /* PLATFORM_DEF_H */ diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk index 6ef1900c6..0917d8701 100644 --- a/plat/nvidia/tegra/platform.mk +++ b/plat/nvidia/tegra/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -59,3 +59,17 @@ override LIBC_SRCS := $(addprefix lib/libc/, \ INCLUDES += -Iinclude/lib/libc \ -Iinclude/lib/libc/$(ARCH) \ + +ifneq ($(findstring armlink,$(notdir $(LD))),) +# o suppress warnings for section mismatches, undefined symbols +# o use only those libraries that are specified in the input file +# list to resolve references +# o create a static callgraph of functions +# o resolve undefined symbols to el3_panic +# o include only required sections +TF_LDFLAGS += --diag_suppress=L6314,L6332 --no_scanlib --callgraph +TF_LDFLAGS += --keep="*(__pubsub*)" --keep="*(rt_svc_descs*)" --keep="*(*cpu_ops)" +ifeq (${ENABLE_PMF},1) +TF_LDFLAGS += --keep="*(*pmf_svc_descs*)" +endif +endif diff --git a/plat/nvidia/tegra/scat/bl31.scat b/plat/nvidia/tegra/scat/bl31.scat new file mode 100644 index 000000000..2f5fd9ecb --- /dev/null +++ b/plat/nvidia/tegra/scat/bl31.scat @@ -0,0 +1,284 @@ +#! armclang -E -x c + +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <platform_def.h> + +#define PAGE_SIZE (1024 * 4) + +LR_START BL31_BASE +{ + __BL31_START__ +0 FIXED EMPTY 0 + { + /* placeholder */ + } + + /* BL31_BASE address must be aligned on a page boundary. */ + ScatterAssert((ImageBase(__BL31_START__) AND 0xFFF) == 0) +} + +LR_TEXT BL31_BASE +{ + __TEXT__ +0 FIXED + { + *(:gdef:bl31_entrypoint, +FIRST) + *(.text*) + *(.vectors) + .ANY1(+RO-CODE) + } + + __TEXT_EPILOGUE__ AlignExpr(+0, PAGE_SIZE) FIXED EMPTY 0 + { + /* section delimiter */ + } +} + +LR_RO_DATA +0 +{ + __RODATA__ AlignExpr(ImageLimit(LR_TEXT), 0) FIXED + { + *(.rodata*) + .ANY2(+RO-DATA) + } + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + __RT_SVC_DESCS__ AlignExpr(ImageLimit(__RODATA__), 8) FIXED + { + *(rt_svc_descs) + } + +#if ENABLE_PMF + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + __PMF_SVC_DESCS__ AlignExpr(ImageLimit(__RT_SVC_DESCS__), 8) FIXED + { + *(pmf_svc_descs) + } +#endif /* ENABLE_PMF */ + + /* + * Ensure 8-byte alignment for cpu_ops so that its fields are also + * aligned. + */ + __CPU_OPS__ AlignExpr(+0, 8) FIXED + { + *(cpu_ops) + } + + /* + * Keep the .got section in the RO section as it is patched + * prior to enabling the MMU and having the .got in RO is better for + * security. GOT is a table of addresses so ensure 8-byte alignment. + */ + __GOT__ AlignExpr(ImageLimit(__CPU_OPS__), 8) FIXED + { + *(.got) + } + + /* Place pubsub sections for events */ + __PUBSUB_EVENTS__ AlignExpr(+0, 8) EMPTY 0 + { + /* placeholder */ + } + +#include <lib/el3_runtime/pubsub_events.h> + + __RODATA_EPILOGUE__ AlignExpr(+0, PAGE_SIZE) FIXED EMPTY 0 + { + /* section delimiter */ + } +} + + /* cpu_ops must always be defined */ + ScatterAssert(ImageLength(__CPU_OPS__) > 0) + +#if ENABLE_SPM +LR_SPM +0 +{ + /* + * Exception vectors of the SPM shim layer. They must be aligned to a 2K + * address, but we need to place them in a separate page so that we can set + * individual permissions to them, so the actual alignment needed is 4K. + * + * There's no need to include this into the RO section of BL31 because it + * doesn't need to be accessed by BL31. + */ + __SPM_SHIM_EXCEPTIONS__ AlignExpr(ImageLimit(LR_RO_DATA), PAGE_SIZE) FIXED + { + *(.spm_shim_exceptions) + } + + __SPM_SHIM_EXCEPTIONS_EPILOGUE__ AlignExpr(ImageLimit(__SPM_SHIM_EXCEPTIONS__), PAGE_SIZE) FIXED + { + /* placeholder */ + } +} +#endif + +LR_RW_DATA +0 +{ + __DATA__ AlignExpr(+0, 16) FIXED + { + *(.data*) + *(.constdata) + *(locale$$data) + } +} + +LR_RELA +0 +{ + /* + * .rela.dyn needs to come after .data for the read-elf utility to parse + * this section correctly. Ensure 8-byte alignment so that the fields of + * RELA data structure are aligned. + */ + __RELA__ AlignExpr(ImageLimit(LR_RW_DATA), 8) FIXED + { + *(.rela.dyn) + } +} + +#ifdef BL31_PROGBITS_LIMIT + /* BL31 progbits has exceeded its limit. */ + ScatterAssert(ImageLimit(LR_RELA) <= BL31_PROGBITS_LIMIT) +#endif + +LR_STACKS +0 +{ + __STACKS__ AlignExpr(+0, 64) FIXED + { + *(tzfw_normal_stacks) + } +} + +#define __BAKERY_LOCK_SIZE__ (ImageLimit(__BAKERY_LOCKS_EPILOGUE__) - \ + ImageBase(__BAKERY_LOCKS__)) +#define BAKERY_LOCK_SIZE (__BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)) +#define __PMF_TIMESTAMP_SIZE__ (ImageLimit(__PMF_TIMESTAMP__) - \ + ImageBase(__PMF_TIMESTAMP__)) +#define PER_CPU_TIMESTAMP_SIZE (__PMF_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)) + +LR_BSS +0 +{ + __BSS__ AlignExpr(ImageLimit(LR_STACKS), 256) FIXED + { + *(.bss*) + *(COMDAT) + } + +#if !USE_COHERENT_MEM + /* + * Bakery locks are stored in normal .bss memory + * + * Each lock's data is spread across multiple cache lines, one per CPU, + * but multiple locks can share the same cache line. + * The compiler will allocate enough memory for one CPU's bakery locks, + * the remaining cache lines are allocated by the linker script + */ + __BAKERY_LOCKS__ AlignExpr(ImageLimit(__BSS__), CACHE_WRITEBACK_GRANULE) FIXED + { + *(bakery_lock) + } + + __BAKERY_LOCKS_EPILOGUE__ AlignExpr(ImageLimit(__BAKERY_LOCKS__), CACHE_WRITEBACK_GRANULE) FIXED EMPTY 0 + { + /* section delimiter */ + } + + __PER_CPU_BAKERY_LOCKS__ ImageLimit(__BAKERY_LOCKS_EPILOGUE__) FIXED FILL 0 BAKERY_LOCK_SIZE + { + /* padded memory section to store per cpu bakery locks */ + } + +#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE + /* PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements */ + ScatterAssert(__PER_CPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE) +#endif +#endif + +#if ENABLE_PMF + /* + * Time-stamps are stored in normal .bss memory + * + * The compiler will allocate enough memory for one CPU's time-stamps, + * the remaining memory for other CPU's is allocated by the + * linker script + */ + __PMF_TIMESTAMP__ AlignExpr(+0, CACHE_WRITEBACK_GRANULE) FIXED EMPTY CACHE_WRITEBACK_GRANULE + { + /* store timestamps in this carved out memory */ + } + + __PMF_TIMESTAMP_EPILOGUE__ AlignExpr(ImageLimit(__PMF_TIMESTAMP__), CACHE_WRITEBACK_GRANULE) FIXED EMPTY 0 + { + /* + * placeholder to make __PMF_TIMESTAMP_START__ end on a + * CACHE_WRITEBACK_GRANULE boundary + */ + } + + __PER_CPU_TIMESTAMPS__ +0 FIXED FILL 0 PER_CPU_TIMESTAMP_SIZE + { + /* padded memory section to store per cpu timestamps */ + } +#endif /* ENABLE_PMF */ +} + +LR_XLAT_TABLE +0 +{ + xlat_table +0 FIXED + { + *(xlat_table) + } +} + +#if USE_COHERENT_MEM +LR_COHERENT_RAM +0 +{ + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + __COHERENT_RAM__ AlignExpr(+0, PAGE_SIZE) FIXED + { + /* + * Bakery locks are stored in coherent memory + * + * Each lock's data is contiguous and fully allocated by the compiler + */ + *(bakery_lock) + *(tzfw_coherent_mem) + } + + __COHERENT_RAM_EPILOGUE_UNALIGNED__ +0 FIXED EMPTY 0 + { + /* section delimiter */ + } + + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + __COHERENT_RAM_EPILOGUE__ AlignExpr(ImageLimit(__COHERENT_RAM_START__), PAGE_SIZE) FIXED EMPTY 0 + { + /* section delimiter */ + } +} +#endif + +LR_END +0 +{ + __BL31_END__ +0 FIXED EMPTY 0 + { + /* placeholder */ + } + + /* BL31 image has exceeded its limit. */ + ScatterAssert(ImageLimit(__BL31_END__) <= BL31_LIMIT) +} diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 2debbf94e..350df127a 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -236,7 +236,7 @@ void bl2_plat_flush_bl31_params(void) product = reg & RCAR_PRODUCT_MASK; cut = reg & RCAR_CUT_MASK; - if (product == RCAR_PRODUCT_M3) + if (product == RCAR_PRODUCT_M3 && RCAR_CUT_VER30 > cut) goto tlb; if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) @@ -693,8 +693,17 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, break; } - if (RCAR_PRODUCT_M3_CUT11 == product_cut) { - NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str); + if ((RCAR_PRODUCT_M3 == product) && + (RCAR_CUT_VER20 == (reg & RCAR_MAJOR_MASK))) { + if (RCAR_M3_CUT_VER11 == (reg & RCAR_CUT_MASK)) { + /* M3 Ver.1.1 or Ver.1.2 */ + NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", + str); + } else { + NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", + str, + (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); + } } else { major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; major = major + RCAR_MAJOR_OFFSET; diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h index 3bb03f2e5..6bbd6fa7b 100644 --- a/plat/renesas/rcar/include/rcar_def.h +++ b/plat/renesas/rcar/include/rcar_def.h @@ -154,7 +154,7 @@ #define RCAR_PRODUCT_M3N U(0x00005500) #define RCAR_PRODUCT_E3 U(0x00005700) #define RCAR_CUT_VER10 U(0x00000000) -#define RCAR_CUT_VER11 U(0x00000001) /* H3/M3N Ver.1.1 */ +#define RCAR_CUT_VER11 U(0x00000001) /* H3/M3N/E3 Ver.1.1 */ #define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */ #define RCAR_CUT_VER20 U(0x00000010) #define RCAR_CUT_VER30 U(0x00000020) @@ -164,6 +164,7 @@ #define RCAR_MAJOR_SHIFT U(4) #define RCAR_MINOR_SHIFT U(0) #define RCAR_MAJOR_OFFSET U(1) +#define RCAR_M3_MINOR_OFFSET U(2) #define RCAR_PRODUCT_H3_CUT10 (RCAR_PRODUCT_H3 | U(0x00)) /* 1.0 */ #define RCAR_PRODUCT_H3_CUT11 (RCAR_PRODUCT_H3 | U(0x01)) /* 1.1 */ #define RCAR_PRODUCT_H3_CUT20 (RCAR_PRODUCT_H3 | U(0x10)) /* 2.0 */ diff --git a/plat/renesas/rcar/include/rcar_version.h b/plat/renesas/rcar/include/rcar_version.h index 5c8805c2e..e43632407 100644 --- a/plat/renesas/rcar/include/rcar_version.h +++ b/plat/renesas/rcar/include/rcar_version.h @@ -9,7 +9,7 @@ #include <arch_helpers.h> -#define VERSION_OF_RENESAS "2.0.0" +#define VERSION_OF_RENESAS "2.0.1" #define VERSION_OF_RENESAS_MAXLEN (128) extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]; diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk index a54a60a37..715b8ae17 100644 --- a/plat/renesas/rcar/platform.mk +++ b/plat/renesas/rcar/platform.mk @@ -13,6 +13,9 @@ GENERATE_COT := 1 BL2_AT_EL3 := 1 ENABLE_SVE_FOR_NS := 0 +CRASH_REPORTING := 1 +HANDLE_EA_EL3_FIRST := 1 + $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) ifeq (${SPD},none) @@ -35,10 +38,12 @@ $(eval $(call add_define,RCAR_H3N)) $(eval $(call add_define,RCAR_AUTO)) RCAR_CUT_10:=0 RCAR_CUT_11:=1 +RCAR_CUT_13:=3 RCAR_CUT_20:=10 RCAR_CUT_30:=20 $(eval $(call add_define,RCAR_CUT_10)) $(eval $(call add_define,RCAR_CUT_11)) +$(eval $(call add_define,RCAR_CUT_13)) $(eval $(call add_define,RCAR_CUT_20)) $(eval $(call add_define,RCAR_CUT_30)) @@ -95,6 +100,10 @@ else RCAR_LSI_CUT:=0 else ifeq (${LSI_CUT},11) RCAR_LSI_CUT:=1 + else ifeq (${LSI_CUT},13) + RCAR_LSI_CUT:=3 + else ifeq (${LSI_CUT},30) + RCAR_LSI_CUT:=20 else $(error "Error: ${LSI_CUT} is not supported.") endif @@ -127,6 +136,8 @@ else # disable compatible function. ifeq (${LSI_CUT},10) RCAR_LSI_CUT:=0 + else ifeq (${LSI_CUT},11) + RCAR_LSI_CUT:=1 else $(error "Error: ${LSI_CUT} is not supported.") endif @@ -322,8 +333,8 @@ PLAT_INCLUDES := -Idrivers/staging/renesas/rcar/ddr \ -Iplat/renesas/rcar/include \ -Iplat/renesas/rcar -PLAT_BL_COMMON_SOURCES := drivers/renesas/rcar/iic_dvfs/iic_dvfs.c - +PLAT_BL_COMMON_SOURCES := drivers/renesas/rcar/iic_dvfs/iic_dvfs.c \ + plat/renesas/rcar/rcar_common.c RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ diff --git a/plat/renesas/rcar/rcar_common.c b/plat/renesas/rcar/rcar_common.c new file mode 100644 index 000000000..b83df8b26 --- /dev/null +++ b/plat/renesas/rcar/rcar_common.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <arch_helpers.h> +#include <drivers/console.h> +#include <lib/xlat_tables/xlat_mmu_helpers.h> +#include <plat/common/platform.h> + +#include <lib/mmio.h> + +#define CPG_BASE 0xE6150000 +#define CPG_MSTPSR3 0x0048 +#define MSTP318 (1 << 18) +#define MSTP319 (1 << 19) +#define PMSR 0x5c +#define PMSR_L1FAEG (1 << 31) +#define PMSR_PMEL1RX (1 << 23) +#define PMCTLR 0x60 +#define PMSR_L1IATN (1 << 31) + +static int rcar_pcie_fixup(unsigned int controller) +{ + uint32_t rcar_pcie_base[] = { 0xfe011000, 0xee811000 }; + uint32_t addr = rcar_pcie_base[controller]; + uint32_t cpg, pmsr; + int ret = 0; + + /* Test if PCIECx is enabled */ + cpg = mmio_read_32(CPG_BASE + CPG_MSTPSR3); + if (cpg & (MSTP318 << !controller)) + return ret; + + pmsr = mmio_read_32(addr + PMSR); + + if ((pmsr & PMSR_PMEL1RX) && ((pmsr & 0x70000) != 0x30000)) { + /* Fix applicable */ + mmio_write_32(addr + PMCTLR, PMSR_L1IATN); + while (!(mmio_read_32(addr + PMSR) & PMSR_L1FAEG)) + ; + mmio_write_32(addr + PMSR, PMSR_L1FAEG | PMSR_PMEL1RX); + ret = 1; + } + + return ret; +} + +/* RAS functions common to AArch64 ARM platforms */ +void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, + void *handle, uint64_t flags) +{ + unsigned int fixed = 0; + + fixed |= rcar_pcie_fixup(0); + fixed |= rcar_pcie_fixup(1); + + if (fixed) + return; + + ERROR("Unhandled External Abort received on 0x%lx at EL3!\n", + read_mpidr_el1()); + ERROR(" exception reason=%u syndrome=0x%llx\n", ea_reason, syndrome); + + panic(); +} diff --git a/plat/rpi3/rpi3_bl2_setup.c b/plat/rpi3/rpi3_bl2_setup.c index 3d1f8f918..b5e58352a 100644 --- a/plat/rpi3/rpi3_bl2_setup.c +++ b/plat/rpi3/rpi3_bl2_setup.c @@ -44,8 +44,8 @@ static void rpi3_sdhost_setup(void) memset(¶ms, 0, sizeof(struct rpi3_sdhost_params)); params.reg_base = RPI3_SDHOST_BASE; - params.bus_width = MMC_BUS_WIDTH_4; - params.clk_rate = 392464; + params.bus_width = MMC_BUS_WIDTH_1; + params.clk_rate = 50000000; mmc_info.mmc_dev_type = MMC_IS_SD_HC; rpi3_sdhost_init(¶ms, &mmc_info); } diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c index c8bb559f4..f1721602d 100644 --- a/plat/st/common/bl2_io_storage.c +++ b/plat/st/common/bl2_io_storage.c @@ -194,7 +194,8 @@ void stm32mp_io_setup(void) case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: dmbsy(); - memset(¶ms, 0, sizeof(struct stm32_sdmmc2_params)); + zeromem(&device_info, sizeof(struct mmc_device_info)); + zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); if (boot_context->boot_interface_selected == BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC) { diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index c7bc39f4e..2477954b0 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -202,6 +202,9 @@ void bl2_el3_plat_arch_setup(void) mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); } + /* Disable MCKPROT */ + mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); + generic_delay_timer_init(); if (stm32mp1_clk_probe() < 0) { diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index f0dc575e2..1c897bdf4 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -183,6 +183,7 @@ enum ddr_type { #define STM32MP1_TZC_BASE U(0x5C006000) #define STM32MP1_TZC_A7_ID U(0) +#define STM32MP1_TZC_M4_ID U(1) #define STM32MP1_TZC_LCD_ID U(3) #define STM32MP1_TZC_GPU_ID U(4) #define STM32MP1_TZC_MDMA_ID U(5) diff --git a/plat/st/stm32mp1/stm32mp1_security.c b/plat/st/stm32mp1/stm32mp1_security.c index ebf1587a6..0ad43e435 100644 --- a/plat/st/stm32mp1/stm32mp1_security.c +++ b/plat/st/stm32mp1/stm32mp1_security.c @@ -41,6 +41,7 @@ static void init_tzc400(void) TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | |