diff options
Diffstat (limited to 'plat')
23 files changed, 425 insertions, 63 deletions
diff --git a/plat/arm/board/fvp/fvp_bl2_el3_setup.c b/plat/arm/board/fvp/fvp_bl2_el3_setup.c new file mode 100644 index 000000000..69f2f7adf --- /dev/null +++ b/plat/arm/board/fvp/fvp_bl2_el3_setup.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <plat_arm.h> +#include "fvp_private.h" + +void bl2_el3_early_platform_setup(u_register_t arg0 __unused, + u_register_t arg1 __unused, + u_register_t arg2 __unused, + u_register_t arg3 __unused) +{ + arm_bl2_el3_early_platform_setup(); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); + + /* + * Initialize Interconnect for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + fvp_interconnect_init(); + /* + * Enable coherency in Interconnect for the primary CPU's cluster. + */ + fvp_interconnect_enable(); +} diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 9d3c5f6b7..a257784cf 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -126,6 +126,13 @@ BL2_SOURCES += drivers/io/io_semihosting.c \ plat/arm/board/fvp/fvp_trusted_boot.c \ ${FVP_SECURITY_SOURCES} +ifeq (${BL2_AT_EL3},1) +BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ + plat/arm/board/fvp/fvp_bl2_el3_setup.c \ + ${FVP_CPU_LIBS} \ + ${FVP_INTERCONNECT_SOURCES} +endif + ifeq (${FVP_USE_SP804_TIMER},1) BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c endif @@ -165,5 +172,9 @@ endif # Add support for platform supplied linker script for BL31 build $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) +ifneq (${BL2_AT_EL3}, 0) + override BL1_SOURCES = +endif + include plat/arm/board/common/board_common.mk include plat/arm/common/arm_common.mk diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c new file mode 100644 index 000000000..e70d115ee --- /dev/null +++ b/plat/arm/common/arm_bl2_el3_setup.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <console.h> +#include <generic_delay_timer.h> +#include <plat_arm.h> +#include <platform.h> + +#pragma weak bl2_el3_early_platform_setup +#pragma weak bl2_el3_plat_arch_setup +#pragma weak bl2_el3_plat_prepare_exit + +static meminfo_t bl2_el3_tzram_layout; + +/* + * Perform arm specific early platform setup. At this moment we only initialize + * the console and the memory layout. + */ +void arm_bl2_el3_early_platform_setup(void) +{ + /* Initialize the console to provide early debug support */ + console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); + + /* + * Allow BL2 to see the whole Trusted RAM. This is determined + * statically since we cannot rely on BL1 passing this information + * in the BL2_AT_EL3 case. + */ + bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE; + bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE; + + /* Initialise the IO layer and register platform IO devices */ + plat_arm_io_setup(); +} + +void bl2_el3_early_platform_setup(u_register_t arg0 __unused, + u_register_t arg1 __unused, + u_register_t arg2 __unused, + u_register_t arg3 __unused) +{ + arm_bl2_el3_early_platform_setup(); + + /* + * Initialize Interconnect for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + plat_arm_interconnect_init(); + /* + * Enable Interconnect coherency for the primary CPU's cluster. + */ + plat_arm_interconnect_enter_coherency(); + + generic_delay_timer_init(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only initializes the mmu in a quick and dirty way. + ******************************************************************************/ +void arm_bl2_el3_plat_arch_setup(void) +{ + arm_setup_page_tables(bl2_el3_tzram_layout.total_base, + bl2_el3_tzram_layout.total_size, + BL_CODE_BASE, + BL_CODE_END, + BL_RO_DATA_BASE, + BL_RO_DATA_END +#if USE_COHERENT_MEM + , BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END +#endif + ); + +#ifdef AARCH32 + enable_mmu_secure(0); +#else + enable_mmu_el3(0); +#endif +} + +void bl2_el3_plat_arch_setup(void) +{ + arm_bl2_el3_plat_arch_setup(); +} + +void bl2_el3_plat_prepare_exit(void) +{ +} diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index fab57f147..e6ce18a72 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -150,6 +150,11 @@ BL2_SOURCES += drivers/delay_timer/delay_timer.c \ drivers/io/io_storage.c \ plat/arm/common/arm_bl2_setup.c \ plat/arm/common/arm_io_storage.c + +ifeq (${BL2_AT_EL3},1) +BL2_SOURCES += plat/arm/common/arm_bl2_el3_setup.c +endif + ifeq (${LOAD_IMAGE_V2},1) # Because BL1/BL2 execute in AArch64 mode but BL32 in AArch32 we need to use # the AArch32 descriptors. diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c index a87e7c673..cfc0c4f41 100644 --- a/plat/common/aarch64/plat_common.c +++ b/plat/common/aarch64/plat_common.c @@ -39,11 +39,11 @@ void bl32_plat_enable_mmu(uint32_t flags) void bl31_plat_runtime_setup(void) { - /* - * Finish the use of console driver in BL31 so that any runtime logs - * from BL31 will be suppressed. - */ +#if MULTI_CONSOLE_API + console_switch_state(CONSOLE_FLAG_RUNTIME); +#else console_uninit(); +#endif } #if !ENABLE_PLAT_COMPAT diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S index 797a93639..852675277 100644 --- a/plat/common/aarch64/platform_helpers.S +++ b/plat/common/aarch64/platform_helpers.S @@ -6,6 +6,7 @@ #include <arch.h> #include <asm_macros.S> +#include <console.h> #include <platform_def.h> .weak plat_report_exception @@ -56,33 +57,78 @@ func plat_report_exception ret endfunc plat_report_exception +#if MULTI_CONSOLE_API /* ----------------------------------------------------- - * Placeholder function which should be redefined by - * each platform. + * int plat_crash_console_init(void) + * Use normal console by default. Switch it to crash + * mode so serial consoles become active again. + * NOTE: This default implementation will only work for + * crashes that occur after a normal console (marked + * valid for the crash state) has been registered with + * the console framework. To debug crashes that occur + * earlier, the platform has to override these functions + * with an implementation that initializes a console + * driver with hardcoded parameters. See + * docs/porting-guide.rst for more information. * ----------------------------------------------------- */ func plat_crash_console_init +#if defined(IMAGE_BL1) + /* + * BL1 code can possibly crash so early that the data segment is not yet + * accessible. Don't risk undefined behavior by trying to run the normal + * console framework. Platforms that want to debug BL1 will need to + * override this with custom functions that can run from registers only. + */ mov x0, #0 ret +#else /* IMAGE_BL1 */ + mov x3, x30 + mov x0, #CONSOLE_FLAG_CRASH + bl console_switch_state + mov x0, #1 + ret x3 +#endif endfunc plat_crash_console_init /* ----------------------------------------------------- - * Placeholder function which should be redefined by - * each platform. + * void plat_crash_console_putc(int character) + * Output through the normal console by default. * ----------------------------------------------------- */ func plat_crash_console_putc - ret + b console_putc endfunc plat_crash_console_putc /* ----------------------------------------------------- - * Placeholder function which should be redefined by - * each platform. + * void plat_crash_console_flush(void) + * Flush normal console by default. + * ----------------------------------------------------- + */ +func plat_crash_console_flush + b console_flush +endfunc plat_crash_console_flush + +#else /* MULTI_CONSOLE_API */ + + /* ----------------------------------------------------- + * In the old API these are all no-op stubs that need to + * be overridden by the platform to be useful. * ----------------------------------------------------- */ +func plat_crash_console_init + mov x0, #0 + ret +endfunc plat_crash_console_init + +func plat_crash_console_putc + ret +endfunc plat_crash_console_putc + func plat_crash_console_flush ret endfunc plat_crash_console_flush +#endif /* ----------------------------------------------------- * Placeholder function which should be redefined by diff --git a/plat/common/plat_bl2_el3_common.c b/plat/common/plat_bl2_el3_common.c new file mode 100644 index 000000000..358a02d5e --- /dev/null +++ b/plat/common/plat_bl2_el3_common.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <assert.h> +#include <bl_common.h> +#include <debug.h> +#include <errno.h> +#include <platform_def.h> + +/* + * The following platform functions are weakly defined. They + * are default implementations that allow BL2 to compile in + * absence of real definitions. The Platforms may override + * with more complex definitions. + */ +#pragma weak bl2_el3_plat_prepare_exit + +void bl2_el3_plat_prepare_exit(void) +{ +} diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c index c65e29e97..7d6f10c2c 100644 --- a/plat/hisilicon/poplar/bl1_plat_setup.c +++ b/plat/hisilicon/poplar/bl1_plat_setup.c @@ -9,6 +9,8 @@ #include <bl_common.h> #include <console.h> #include <debug.h> +#include <dw_mmc.h> +#include <emmc.h> #include <errno.h> #include <generic_delay_timer.h> #include <mmio.h> @@ -71,6 +73,9 @@ void bl1_plat_arch_setup(void) void bl1_platform_setup(void) { int i; +#if !POPLAR_RECOVERY + dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); +#endif generic_delay_timer_init(); @@ -78,6 +83,12 @@ void bl1_platform_setup(void) for (i = 0; i < GPIO_MAX; i++) pl061_gpio_register(GPIO_BASE(i), i); +#if !POPLAR_RECOVERY + /* SoC-specific emmc register are initialized/configured by bootrom */ + INFO("BL1: initializing emmc\n"); + dw_mmc_init(¶ms); +#endif + plat_io_setup(); } diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c index db507c327..7edfab7ff 100644 --- a/plat/hisilicon/poplar/bl2_plat_setup.c +++ b/plat/hisilicon/poplar/bl2_plat_setup.c @@ -9,6 +9,8 @@ #include <bl_common.h> #include <console.h> #include <debug.h> +#include <dw_mmc.h> +#include <emmc.h> #include <errno.h> #include <generic_delay_timer.h> #include <mmio.h> @@ -181,12 +183,24 @@ void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) void bl2_early_platform_setup(meminfo_t *mem_layout) { +#if !POPLAR_RECOVERY + dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); +#endif + console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); /* Enable arch timer */ generic_delay_timer_init(); bl2_tzram_layout = *mem_layout; + +#if !POPLAR_RECOVERY + /* SoC-specific emmc register are initialized/configured by bootrom */ + INFO("BL2: initializing emmc\n"); + dw_mmc_init(¶ms); +#endif + + plat_io_setup(); } void bl2_plat_arch_setup(void) @@ -201,7 +215,6 @@ void bl2_plat_arch_setup(void) void bl2_platform_setup(void) { - plat_io_setup(); } unsigned long plat_get_ns_image_entrypoint(void) diff --git a/plat/hisilicon/poplar/include/hi3798cv200.h b/plat/hisilicon/poplar/include/hi3798cv200.h index 540d0aa18..125b04841 100644 --- a/plat/hisilicon/poplar/include/hi3798cv200.h +++ b/plat/hisilicon/poplar/include/hi3798cv200.h @@ -7,6 +7,8 @@ #ifndef __HI3798cv200_H__ #define __HI3798cv200_H__ +#include <utils_def.h> + /* PL011 */ #define PL011_UART0_BASE (0xF8B00000) #define PL011_BAUDRATE (115200) @@ -63,11 +65,11 @@ #define EMMC_CLK_50M (1 << 8) #define EMMC_CLK_25M (2 << 8) -#define EMMC_DESC_SIZE (0xF0000) +#define EMMC_DESC_SIZE U(0x00100000) /* 1MB */ #define EMMC_INIT_PARAMS(base) \ { .bus_width = EMMC_BUS_WIDTH_8, \ .clk_rate = 25 * 1000 * 1000, \ - .desc_base = (base) - EMMC_DESC_SIZE, \ + .desc_base = (base), \ .desc_size = EMMC_DESC_SIZE, \ .flags = EMMC_FLAG_CMD23, \ .reg_base = REG_BASE_MCI, \ diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h index 3d1ad9b99..c0f83711c 100644 --- a/plat/hisilicon/poplar/include/platform_def.h +++ b/plat/hisilicon/poplar/include/platform_def.h @@ -12,6 +12,7 @@ #include <gic_common.h> #include <interrupt_props.h> #include <tbbr/tbbr_img_def.h> +#include <utils_def.h> #include "hi3798cv200.h" #include "poplar_layout.h" /* BL memory region sizes, etc */ @@ -53,13 +54,12 @@ #define POPLAR_DRAM_ID 1 /* - * DDR for OP-TEE (28MB from 0x02200000 -0x04000000) is divided in several + * DDR for OP-TEE (26MB from 0x02400000 -0x04000000) is divided in several * regions: * - Secure DDR (default is the top 16MB) used by OP-TEE * - Non-secure DDR (4MB) reserved for OP-TEE's future use * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) - * - Non-secure DDR (2MB) reserved for OP-TEE's future use */ #define DDR_SEC_SIZE 0x01000000 #define DDR_SEC_BASE 0x03000000 @@ -96,6 +96,11 @@ #endif /* SPD_none */ #endif +#define POPLAR_EMMC_DATA_BASE U(0x02200000) +#define POPLAR_EMMC_DATA_SIZE EMMC_DESC_SIZE +#define POPLAR_EMMC_DESC_BASE (POPLAR_EMMC_DATA_BASE + POPLAR_EMMC_DATA_SIZE) +#define POPLAR_EMMC_DESC_SIZE EMMC_DESC_SIZE + #define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000 /* Page table and MMU setup constants */ diff --git a/plat/hisilicon/poplar/include/poplar_layout.h b/plat/hisilicon/poplar/include/poplar_layout.h index e0b5618ef..9ce043423 100644 --- a/plat/hisilicon/poplar/include/poplar_layout.h +++ b/plat/hisilicon/poplar/include/poplar_layout.h @@ -12,8 +12,8 @@ */ /* - * When Poplar is powered on, boot ROM loads the initial content of - * boot media into low memory, verifies it, and begins executing it + * When Poplar is powered on, boot ROM verifies the initial content of + * boot media, loads it into low memory, and begins executing it * in 32-bit mode. The image loaded is "l-loader.bin", which contains * a small amount code along with an embedded ARM Trusted Firmware * BL1 image. The main purpose of "l-loader" is to prepare the @@ -78,12 +78,36 @@ #define BL1_OFFSET 0x0000D000 /* page multiple */ #define FIP_BASE 0x02040000 +/* + * FIP_BASE_EMMC = 0x40000 - 0x1000 + * = fip.bin offset - l-loader text offset + * in l-loader.bin + */ +#define FIP_BASE_EMMC 0x0003f000 + #define BL1_RO_SIZE 0x00008000 /* page multiple */ #define BL1_RW_SIZE 0x00008000 /* page multiple */ #define BL1_SIZE (BL1_RO_SIZE + BL1_RW_SIZE) #define BL2_SIZE 0x0000c000 /* page multiple */ #define BL31_SIZE 0x00014000 +#if !POPLAR_RECOVERY +/* + * emmc partition1 4096KB + * - l-loader.bin 1984KB + * |- l-loader + bl1.bin 256KB + * |- fip.bin 1728KB (0x001b0000) + * - u-boot persistent data 64KB + * - uefi persistent data 2048KB + */ +#define FIP_SIZE 0x001b0000 /* absolute max */ +#else +/* + * same as above, but bootrom can only load an image (l-loader.bin) of + * 1024KB max, so after deducting the size of l-loader + bl1.bin (256KB), + * that leaves 768KB (0x000c0000) for fip.bin + */ #define FIP_SIZE 0x000c0000 /* absolute max */ +#endif /* BL1_OFFSET */ /* (Defined above) */ #define BL1_BASE (LLOADER_TEXT_BASE + BL1_OFFSET) diff --git a/plat/hisilicon/poplar/plat_storage.c b/plat/hisilicon/poplar/plat_storage.c index ab94cba33..468e22926 100644 --- a/plat/hisilicon/poplar/plat_storage.c +++ b/plat/hisilicon/poplar/plat_storage.c @@ -7,6 +7,7 @@ #include <arch_helpers.h> #include <assert.h> #include <debug.h> +#include <emmc.h> #include <firmware_image_package.h> #include <io_block.h> #include <io_driver.h> @@ -21,19 +22,41 @@ #include <utils.h> #include "platform_def.h" -static const io_dev_connector_t *mmap_dev_con; -static const io_dev_connector_t *fip_dev_con; +#if !POPLAR_RECOVERY +static const io_dev_connector_t *emmc_dev_con; +static uintptr_t emmc_dev_handle; +static int open_emmc(const uintptr_t spec); -static uintptr_t mmap_dev_handle; -static uintptr_t fip_dev_handle; +static const io_block_spec_t emmc_fip_spec = { + .offset = FIP_BASE_EMMC, + .length = FIP_SIZE +}; +static const io_block_dev_spec_t emmc_dev_spec = { + .buffer = { + .offset = POPLAR_EMMC_DATA_BASE, + .length = POPLAR_EMMC_DATA_SIZE, + }, + .ops = { + .read = emmc_read_blocks, + .write = emmc_write_blocks, + }, + .block_size = EMMC_BLOCK_SIZE, +}; +#else +static const io_dev_connector_t *mmap_dev_con; +static uintptr_t mmap_dev_handle; static int open_mmap(const uintptr_t spec); -static int open_fip(const uintptr_t spec); static const io_block_spec_t loader_fip_spec = { .offset = FIP_BASE, .length = FIP_SIZE }; +#endif + +static const io_dev_connector_t *fip_dev_con; +static uintptr_t fip_dev_handle; +static int open_fip(const uintptr_t spec); static const io_uuid_spec_t bl2_uuid_spec = { .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, @@ -58,11 +81,19 @@ struct plat_io_policy { }; static const struct plat_io_policy policies[] = { +#if !POPLAR_RECOVERY + [FIP_IMAGE_ID] = { + &emmc_dev_handle, + (uintptr_t)&emmc_fip_spec, + open_emmc + }, +#else [FIP_IMAGE_ID] = { &mmap_dev_handle, (uintptr_t)&loader_fip_spec, open_mmap }, +#endif [BL2_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl2_uuid_spec, @@ -85,6 +116,28 @@ static const struct plat_io_policy policies[] = { }, }; +#if !POPLAR_RECOVERY +static int open_emmc(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(emmc_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(emmc_dev_handle, spec, &local_image_handle); + if (result == 0) { + INFO("Using eMMC\n"); + io_close(local_image_handle); + } else { + ERROR("error opening emmc\n"); + } + } else { + ERROR("error initializing emmc\n"); + } + + return result; +} +#else static int open_mmap(const uintptr_t spec) { int result; @@ -94,11 +147,18 @@ static int open_mmap(const uintptr_t spec) if (result == 0) { result = io_open(mmap_dev_handle, spec, &local_image_handle); if (result == 0) { + INFO("Using mmap\n"); io_close(local_image_handle); + } else { + ERROR("error opening mmap\n"); } + } else { + ERROR("error initializing mmap\n"); } + return result; } +#endif static int open_fip(const uintptr_t spec) { @@ -109,12 +169,13 @@ static int open_fip(const uintptr_t spec) if (result == 0) { result = io_open(fip_dev_handle, spec, &local_image_handle); if (result == 0) { + INFO("Using FIP\n"); io_close(local_image_handle); } else { - VERBOSE("error opening fip\n"); + ERROR("error opening fip\n"); } } else { - VERBOSE("error initializing fip\n"); + ERROR("error initializing fip\n"); } return result; @@ -142,17 +203,31 @@ void plat_io_setup(void) { int result; +#if !POPLAR_RECOVERY + result = register_io_dev_block(&emmc_dev_con); +#else result = register_io_dev_memmap(&mmap_dev_con); +#endif assert(result == 0); result = register_io_dev_fip(&fip_dev_con); assert(result == 0); +#if !POPLAR_RECOVERY + result = io_dev_open(fip_dev_con, (uintptr_t)NULL, + &fip_dev_handle); +#else result = io_dev_open(fip_dev_con, (uintptr_t)&loader_fip_spec, &fip_dev_handle); +#endif assert(result == 0); +#if !POPLAR_RECOVERY + result = io_dev_open(emmc_dev_con, (uintptr_t)&emmc_dev_spec, + &emmc_dev_handle); +#else result = io_dev_open(mmap_dev_con, (uintptr_t)NULL, &mmap_dev_handle); +#endif assert(result == 0); (void) result; diff --git a/plat/hisilicon/poplar/platform.mk b/plat/hisilicon/poplar/platform.mk index 818e3115f..2dbbac6e7 100644 --- a/plat/hisilicon/poplar/platform.mk +++ b/plat/hisilicon/poplar/platform.mk @@ -15,6 +15,9 @@ else endif $(eval $(call add_define,POPLAR_TSP_RAM_LOCATION_ID)) +POPLAR_RECOVERY := 0 +$(eval $(call add_define,POPLAR_RECOVERY)) + NEED_BL33 := yes COLD_BOOT_SINGLE_CPU := 1 @@ -36,6 +39,7 @@ PLAT_INCLUDES := -Iplat/hisilicon/poplar/include \ -Iinclude/plat/arm/common/ \ -Iplat/hisilicon/poplar \ -Iinclude/common/tbbr \ + -Iinclude/drivers/synopsys \ -Iinclude/drivers/io PLAT_BL_COMMON_SOURCES := \ @@ -54,6 +58,8 @@ PLAT_BL_COMMON_SOURCES := \ BL1_SOURCES += \ lib/cpus/aarch64/cortex_a53.S \ drivers/arm/pl061/pl061_gpio.c \ + drivers/emmc/emmc.c \ + drivers/synopsys/emmc/dw_mmc.c \ drivers/io/io_storage.c \ drivers/io/io_block.c \ drivers/gpio/gpio.c \ @@ -65,6 +71,8 @@ BL1_SOURCES += \ BL2_SOURCES += \ drivers/arm/pl061/pl061_gpio.c \ + drivers/emmc/emmc.c \ + drivers/synopsys/emmc/dw_mmc.c \ drivers/io/io_storage.c \ drivers/io/io_block.c \ drivers/io/io_fip.c \ diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S index abfb5a795..f415f8772 100644 --- a/plat/rockchip/common/aarch64/plat_helpers.S +++ b/plat/rockchip/common/aarch64/plat_helpers.S @@ -19,10 +19,9 @@ .globl plat_secondary_cold_boot_setup .globl plat_report_exception .globl platform_is_primary_cpu - .globl plat_crash_console_init - .globl plat_crash_console_putc .globl plat_my_core_pos .globl plat_reset_handler + .globl plat_panic_handler /* * void plat_reset_handler(void); @@ -82,30 +81,17 @@ func platform_is_primary_cpu endfunc platform_is_primary_cpu /* -------------------------------------------------------------------- - * int plat_crash_console_init(void) - * Function to initialize the crash console - * without a C Runtime to print crash report. - * Clobber list : x0, x1, x2 + * void plat_panic_handler(void) + * Call system reset function on panic. Set up an emergency stack so we + * can run C functions (it only needs to last for a few calls until we + * reboot anyway). * -------------------------------------------------------------------- */ -func plat_crash_console_init - mov_imm x0, PLAT_RK_UART_BASE - mov_imm x1, PLAT_RK_UART_CLOCK - mov_imm x2, PLAT_RK_UART_BAUDRATE - b console_core_init -endfunc plat_crash_console_init - - /* -------------------------------------------------------------------- - * int plat_crash_console_putc(void) - * Function to print a character on the crash - * console without a C Runtime. - * Clobber list : x1, x2 - * -------------------------------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, PLAT_RK_UART_BASE - b console_core_putc -endfunc plat_crash_console_putc +func plat_panic_handler + msr spsel, #0 + bl plat_set_my_stack + b rockchip_soc_soft_reset +endfunc plat_panic_handler /* -------------------------------------------------------------------- * void platform_cpu_warmboot (void); diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index 292f0dd7d..6199edae2 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -8,12 +8,14 @@ #include <assert.h> #include <bl_common.h> #include <console.h> +#include <coreboot.h> #include <debug.h> #include <generic_delay_timer.h> #include <mmio.h> #include <plat_private.h> #include <platform.h> #include <platform_def.h> +#include <uart_16550.h> /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout @@ -69,8 +71,20 @@ void params_early_setup(void *plat_param_from_bl2) void bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) { - console_init(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, - PLAT_RK_UART_BAUDRATE); + static console_16550_t console; + + params_early_setup(plat_params_from_bl2); + +#if COREBOOT + if (coreboot_serial.type) + console_16550_register(coreboot_serial.baseaddr, + coreboot_serial.input_hertz, + coreboot_serial.baud, + &console); +#else + console_16550_register(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, + PLAT_RK_UART_BAUDRATE, &console); +#endif VERBOSE("bl31_setup\n"); @@ -82,9 +96,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, bl32_ep_info = *from_bl2->bl32_ep_info; bl33_ep_info = *from_bl2->bl33_ep_info; - - /* there may have some board sepcific message need to initialize */ - params_early_setup(plat_params_from_bl2); } /******************************************************************************* diff --git a/plat/rockchip/common/include/plat_macros.S b/plat/rockchip/common/include/plat_macros.S index be1a9fa5d..6b3cb6a72 100644 --- a/plat/rockchip/common/include/plat_macros.S +++ b/plat/rockchip/common/include/plat_macros.S @@ -38,14 +38,14 @@ cci_iface_regs: * The below utility macro prints out relevant GIC * and CCI registers whenever an unhandled * exception is taken in BL31. - * Expects: GICD base in x16, GICC base in x17 + * Expects: GICD base in x26, GICC base in x27 * Clobbers: x0 - x10, sp * --------------------------------------------- */ .macro plat_crash_print_regs - mov_imm x16, PLAT_RK_GICD_BASE - mov_imm x17, PLAT_RK_GICC_BASE + mov_imm x26, PLAT_RK_GICD_BASE + mov_imm x27, PLAT_RK_GICC_BASE /* Check for GICv3 system register access */ mrs x7, id_aa64pfr0_el1 @@ -72,19 +72,19 @@ print_gicv2: /* Load the gicc reg list to x6 */ adr x6, gicc_regs /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ - ldr w8, [x17, #GICC_HPPIR] - ldr w9, [x17, #GICC_AHPPIR] - ldr w10, [x17, #GICC_CTLR] + ldr w8, [x27, #GICC_HPPIR] + ldr w9, [x27, #GICC_AHPPIR] + ldr w10, [x27, #GICC_CTLR] /* Store to the crash buf and print to console */ bl str_in_crash_buf_print print_gic_common: /* Print the GICD_ISPENDR regs */ - add x7, x16, #GICD_ISPENDR + add x7, x26, #GICD_ISPENDR adr x4, gicd_pend_reg bl asm_print_str gicd_ispendr_loop: - sub x4, x7, x16 + sub x4, x7, x26 cmp x4, #0x280 b.eq exit_print_gic_regs bl asm_print_hex diff --git a/plat/rockchip/common/include/plat_params.h b/plat/rockchip/common/include/plat_params.h index aa13f878c..710990760 100644 --- a/plat/rockchip/common/include/plat_params.h +++ b/plat/rockchip/common/include/plat_params.h @@ -56,6 +56,7 @@ enum { PARAM_POWEROFF, PARAM_SUSPEND_GPIO, PARAM_SUSPEND_APIO, + PARAM_COREBOOT_TABLE, }; struct apio_info { @@ -89,4 +90,9 @@ struct bl31_apio_param { struct apio_info apio; }; +struct bl31_u64_param { + struct bl31_plat_param h; + uint64_t value; +}; + #endif /* __PLAT_PARAMS_H__ */ diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c index b37acb76b..65afe8769 100644 --- a/plat/rockchip/common/params_setup.c +++ b/plat/rockchip/common/params_setup.c @@ -8,6 +8,7 @@ #include <assert.h> #include <bl_common.h> #include <console.h> +#include <coreboot.h> #include <debug.h> #include <gpio.h> #include <mmio.h> @@ -84,6 +85,12 @@ void params_early_setup(void *plat_param_from_bl2) sizeof(struct bl31_apio_param)); suspend_apio = ¶m_apio.apio; break; +#if COREBOOT + case PARAM_COREBOOT_TABLE: + coreboot_table_setup((void *) + ((struct bl31_u64_param *)bl2_param)->value); + break; +#endif default: ERROR("not expected type found %ld\n", bl2_param->type); diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk index 5de4680e0..6e4d5b4dc 100644 --- a/plat/rockchip/rk3328/platform.mk +++ b/plat/rockchip/rk3328/platform.mk @@ -49,6 +49,9 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_SOC}/drivers/soc/soc.c ENABLE_PLAT_COMPAT := 0 +MULTI_CONSOLE_API := 1 + +include lib/coreboot/coreboot.mk $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) $(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER)) diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk index d3c6eeffb..ad204e9eb 100644 --- a/plat/rockchip/rk3368/platform.mk +++ b/plat/rockchip/rk3368/platform.mk @@ -49,6 +49,9 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_SOC}/drivers/ddr/ddr_rk3368.c \ ENABLE_PLAT_COMPAT := 0 +MULTI_CONSOLE_API := 1 + +include lib/coreboot/coreboot.mk $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk index 33b9723d7..9e369e482 100644 --- a/plat/rockchip/rk3399/platform.mk +++ b/plat/rockchip/rk3399/platform.mk @@ -64,6 +64,9 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_SOC}/drivers/dram/suspend.c ENABLE_PLAT_COMPAT := 0 +MULTI_CONSOLE_API := 1 + +include lib/coreboot/coreboot.mk $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk index f99bbf58a..e0ddfa821 100644 --- a/plat/socionext/uniphier/platform.mk +++ b/plat/socionext/uniphier/platform.mk @@ -6,7 +6,6 @@ override COLD_BOOT_SINGLE_CPU := 1 override ENABLE_PLAT_COMPAT := 0 -override ERROR_DEPRECATED := 1 override LOAD_IMAGE_V2 := 1 override USE_COHERENT_MEM := 1 override USE_TBBR_DEFS := 1 |