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-rw-r--r--plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c10
-rw-r--r--plat/imx/imx8m/imx8mm/platform.mk1
-rw-r--r--plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c11
-rw-r--r--plat/imx/imx8m/imx8mq/platform.mk1
-rw-r--r--plat/imx/imx8m/imx_aipstz.c24
-rw-r--r--plat/imx/imx8m/include/imx_aipstz.h27
-rw-r--r--plat/meson/gxl/gxl_bl31_setup.c6
-rw-r--r--plat/ti/k3/common/k3_helpers.S22
-rw-r--r--plat/ti/k3/common/plat_common.mk4
9 files changed, 100 insertions, 6 deletions
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index a541ed377..8bfb5452a 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -22,6 +22,7 @@
#include <plat/common/platform.h>
#include <gpc.h>
+#include <imx_aipstz.h>
#include <imx_uart.h>
#include <plat_imx8.h>
@@ -31,6 +32,14 @@ static const mmap_region_t imx_mmap[] = {
{0},
};
+static const struct aipstz_cfg aipstz[] = {
+ {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {0},
+};
+
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -82,6 +91,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
}
+ imx_aipstz_init(aipstz);
console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE, &console);
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 9f9ba922c..bd1c05839 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -19,6 +19,7 @@ IMX_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
BL31_SOURCES += plat/imx/common/imx8_helpers.S \
plat/imx/imx8m/gpc_common.c \
+ plat/imx/imx8m/imx_aipstz.c \
plat/imx/imx8m/imx8m_psci_common.c \
plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c \
plat/imx/imx8m/imx8mm/imx8mm_psci.c \
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
index ea60466f7..ce55d7f31 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
@@ -22,6 +22,7 @@
#include <plat/common/platform.h>
#include <gpc.h>
+#include <imx_aipstz.h>
#include <imx_uart.h>
#include <plat_imx8.h>
@@ -33,6 +34,14 @@ static const mmap_region_t imx_mmap[] = {
{0},
};
+static const struct aipstz_cfg aipstz[] = {
+ {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {0},
+};
+
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -118,6 +127,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff);
}
+ imx_aipstz_init(aipstz);
+
/* config CAAM JRaMID set MID to Cortex A */
mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk
index 3152c7215..c6bec6f3c 100644
--- a/plat/imx/imx8m/imx8mq/platform.mk
+++ b/plat/imx/imx8m/imx8mq/platform.mk
@@ -21,6 +21,7 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \
plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c \
plat/imx/imx8m/imx8mq/imx8mq_psci.c \
plat/imx/imx8m/gpc_common.c \
+ plat/imx/imx8m/imx_aipstz.c \
plat/imx/imx8m/imx8m_psci_common.c \
plat/imx/imx8m/imx8mq/gpc.c \
plat/imx/common/imx8_topology.c \
diff --git a/plat/imx/imx8m/imx_aipstz.c b/plat/imx/imx8m/imx_aipstz.c
new file mode 100644
index 000000000..a36e2961a
--- /dev/null
+++ b/plat/imx/imx8m/imx_aipstz.c
@@ -0,0 +1,24 @@
+/*
+ * copyright (c) 2019, arm limited and contributors. all rights reserved.
+ *
+ * spdx-license-identifier: bsd-3-clause
+ */
+
+#include <lib/mmio.h>
+
+#include <imx_aipstz.h>
+
+void imx_aipstz_init(const struct aipstz_cfg *aipstz_cfg)
+{
+ const struct aipstz_cfg *aipstz = aipstz_cfg;
+
+ while (aipstz->base != 0U) {
+ mmio_write_32(aipstz->base + AIPSTZ_MPR0, aipstz->mpr0);
+ mmio_write_32(aipstz->base + AIPSTZ_MPR1, aipstz->mpr1);
+
+ for (int i = 0; i < AIPSTZ_OPACR_NUM; i++)
+ mmio_write_32(aipstz->base + OPACR_OFFSET(i), aipstz->opacr[i]);
+
+ aipstz++;
+ }
+}
diff --git a/plat/imx/imx8m/include/imx_aipstz.h b/plat/imx/imx8m/include/imx_aipstz.h
new file mode 100644
index 000000000..761686298
--- /dev/null
+++ b/plat/imx/imx8m/include/imx_aipstz.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX_AIPSTZ_H
+#define IMX_AIPSTZ_H
+
+#include <lib/utils_def.h>
+
+#define AIPSTZ_MPR0 U(0x0)
+#define AIPSTZ_MPR1 U(0x4)
+
+#define AIPSTZ_OPACR_NUM U(0x5)
+#define OPACR_OFFSET(i) U((i) * 4 + 0x40)
+
+struct aipstz_cfg {
+ uintptr_t base;
+ uint32_t mpr0;
+ uint32_t mpr1;
+ uint32_t opacr[AIPSTZ_OPACR_NUM];
+};
+
+void imx_aipstz_init(const struct aipstz_cfg *aipstz_cfg);
+
+#endif /* IMX_AIPSTZ_H */
diff --git a/plat/meson/gxl/gxl_bl31_setup.c b/plat/meson/gxl/gxl_bl31_setup.c
index 7fe05292d..f8ce6605b 100644
--- a/plat/meson/gxl/gxl_bl31_setup.c
+++ b/plat/meson/gxl/gxl_bl31_setup.c
@@ -70,12 +70,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
/* Initialize the console to provide early debug support */
gxbb_console_init();
- /*
- * In debug builds, we pass a special value in 'arg1' to verify platform
- * parameters from BL2 to BL31. In release builds it's not used.
- */
- assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL);
-
/* Check that params passed from BL2 are not NULL. */
from_bl2 = (struct gxl_bl31_param *) arg0;
diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S
index 1ab1af54c..3afca591e 100644
--- a/plat/ti/k3/common/k3_helpers.S
+++ b/plat/ti/k3/common/k3_helpers.S
@@ -6,6 +6,8 @@
#include <arch.h>
#include <asm_macros.S>
+#include <cortex_a72.h>
+#include <cpu_macros.S>
#include <platform_def.h>
#define K3_BOOT_REASON_COLD_RESET 0x1
@@ -89,6 +91,26 @@ out:
ret
endfunc plat_my_core_pos
+ /* --------------------------------------------------------------------
+ * This handler does the following:
+ * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
+ * --------------------------------------------------------------------
+ */
+ .globl plat_reset_handler
+func plat_reset_handler
+ /* Only on Cortex-A72 */
+ jump_if_cpu_midr CORTEX_A72_MIDR, a72
+ ret
+
+ /* Cortex-A72 specific settings */
+a72:
+ mrs x0, CORTEX_A72_L2CTLR_EL1
+ orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+ msr CORTEX_A72_L2CTLR_EL1, x0
+ isb
+ ret
+endfunc plat_reset_handler
+
/* ---------------------------------------------
* int plat_crash_console_init(void)
* Function to initialize the crash console
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 29fcafdb9..2e5f58453 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -22,6 +22,9 @@ ERRATA_A53_836870 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+# A72 Erratum for SoC
+ERRATA_A72_859971 := 1
+
# Split out RO data into a non-executable section
SEPARATE_CODE_AND_RODATA := 1
@@ -68,6 +71,7 @@ K3_TI_SCI_SOURCES += \
PLAT_BL_COMMON_SOURCES += \
lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a72.S \
${XLAT_TABLES_LIB_SRCS} \
${K3_CONSOLE_SOURCES} \
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 16:54:27 +0000