diff options
Diffstat (limited to 'plat')
40 files changed, 354 insertions, 642 deletions
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts index 9a4a05799..61bd69c17 100644 --- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts +++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts @@ -39,7 +39,7 @@ tos_fw-config { load-address = <0x0 0x04001200>; - max-size = <0x200>; + max-size = <0x1000>; id = <TOS_FW_CONFIG_ID>; }; @@ -102,12 +102,12 @@ secure-partitions { compatible = "arm,sp"; - cactus { + cactus-primary { uuid = <0x1e67b5b4 0xe14f904a 0x13fb1fb8 0xcbdae1da>; load-address = <0x7000000>; }; - ivy { + cactus-secondary { uuid = <0x092358d1 0xb94723f0 0x64447c82 0xc88f57f5>; load-address = <0x7100000>; }; diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts index db3fb5510..79c4c07f6 100644 --- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts +++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts @@ -6,7 +6,7 @@ /dts-v1/; / { - compatible = "spci-core-manifest-1.0"; + compatible = "arm,spci-core-manifest-1.0"; attribute { spmc_id = <0x8000>; @@ -16,4 +16,52 @@ load_address = <0x0 0x6000000>; entrypoint = <0x0 0x6000000>; }; + + chosen { + linux,initrd-start = <0>; + linux,initrd-end = <0>; + }; + + hypervisor { + compatible = "hafnium,hafnium"; + vm1 { + is_spci_partition; + debug_name = "cactus-primary"; + load-addr = <0x7000000>; + }; + vm2 { + is_spci_partition; + debug_name = "cactus-secondary"; + load-addr = <0x7100000>; + vcpu_count = <2>; + mem_size = <1048576>; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <0x2>; + }; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <0xc>; + phandle = <0x2>; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x6000000 0x2000000>; /* Trusted DRAM */ + }; }; diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index 9a482d0c0..305fcf66b 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -141,7 +141,7 @@ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ ARM_SHARED_RAM_BASE, \ ARM_SHARED_RAM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE \ + MT_NON_CACHEABLE | MT_RW | MT_SECURE \ ) #define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \ diff --git a/plat/imx/common/include/imx8_iomux.h b/plat/imx/common/include/imx8_iomux.h index 0e93d9800..264c295bb 100644 --- a/plat/imx/common/include/imx8_iomux.h +++ b/plat/imx/common/include/imx8_iomux.h @@ -7,19 +7,19 @@ #ifndef IMX8_IOMUX_H #define IMX8_IOMUX_H -#define PADRING_IFMUX_EN_SHIFT 31 -#define PADRING_IFMUX_EN_MASK (1 << PADRING_IFMUX_EN_SHIFT) -#define PADRING_GP_EN_SHIFT 30 -#define PADRING_GP_EN_MASK (1 << PADRING_GP_EN_SHIFT) -#define PADRING_IFMUX_SHIFT 27 -#define PADRING_IFMUX_MASK (0x7 << PADRING_IFMUX_SHIFT) -#define PADRING_CONFIG_SHIFT 25 -#define PADRING_CONFIG_MASK (0x3 << PADRING_CONFIG_SHIFT) -#define PADRING_LPCONFIG_SHIFT 23 -#define PADRING_LPCONFIG_MASK (0x3 << PADRING_LPCONFIG_SHIFT) -#define PADRING_PULL_SHIFT 5 -#define PADRING_PULL_MASK (0x3 << PADRING_PULL_SHIFT) -#define PADRING_DSE_SHIFT 0 -#define PADRING_DSE_MASK (0x7 << PADRING_DSE_SHIFT) +#define PADRING_IFMUX_EN_SHIFT U(31) +#define PADRING_IFMUX_EN_MASK (U(0x1) << PADRING_IFMUX_EN_SHIFT) +#define PADRING_GP_EN_SHIFT U(30) +#define PADRING_GP_EN_MASK (U(0x1) << PADRING_GP_EN_SHIFT) +#define PADRING_IFMUX_SHIFT U(27) +#define PADRING_IFMUX_MASK (U(0x7) << PADRING_IFMUX_SHIFT) +#define PADRING_CONFIG_SHIFT U(25) +#define PADRING_CONFIG_MASK (U(0x3) << PADRING_CONFIG_SHIFT) +#define PADRING_LPCONFIG_SHIFT U(23) +#define PADRING_LPCONFIG_MASK (U(0x3) << PADRING_LPCONFIG_SHIFT) +#define PADRING_PULL_SHIFT U(5) +#define PADRING_PULL_MASK (U(0x3) << PADRING_PULL_SHIFT) +#define PADRING_DSE_SHIFT U(0) +#define PADRING_DSE_MASK (U(0x7) << PADRING_DSE_SHIFT) #endif /* IMX8_IOMUX_H */ diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c index cffb140fb..4ca6a5db4 100644 --- a/plat/imx/imx8qm/imx8qm_bl31_setup.c +++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c @@ -44,6 +44,22 @@ static entry_point_info_t bl33_image_ep_info; (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT)) +#if defined(IMX_USE_UART0) +#define IMX_RES_UART SC_R_UART_0 +#define IMX_PAD_UART_RX SC_P_UART0_RX +#define IMX_PAD_UART_TX SC_P_UART0_TX +#define IMX_PAD_UART_RTS_B SC_P_UART0_RTS_B +#define IMX_PAD_UART_CTS_B SC_P_UART0_CTS_B +#elif defined(IMX_USE_UART1) +#define IMX_RES_UART SC_R_UART_1 +#define IMX_PAD_UART_RX SC_P_UART1_RX +#define IMX_PAD_UART_TX SC_P_UART1_TX +#define IMX_PAD_UART_RTS_B SC_P_UART1_RTS_B +#define IMX_PAD_UART_CTS_B SC_P_UART1_CTS_B +#else +#error "Provide proper UART number in IMX_DEBUG_UART" +#endif + const static int imx8qm_cci_map[] = { CLUSTER0_CCI_SLVAE_IFACE, CLUSTER1_CCI_SLVAE_IFACE @@ -79,7 +95,7 @@ static void lpuart32_serial_setbrg(unsigned int base, int baudrate) if (baudrate == 0) panic(); - sc_pm_get_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); + sc_pm_get_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate); baud_diff = baudrate; osr = 0; @@ -301,16 +317,17 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, panic(); #if DEBUG_CONSOLE_A53 - sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(ipc_handle, IMX_RES_UART, + SC_PM_PW_MODE_ON); sc_pm_clock_rate_t rate = 80000000; - sc_pm_set_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); - sc_pm_clock_enable(ipc_handle, SC_R_UART_0, 2, true, false); + sc_pm_set_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate); + sc_pm_clock_enable(ipc_handle, IMX_RES_UART, 2, true, false); /* configure UART pads */ - sc_pad_set(ipc_handle, SC_P_UART0_RX, UART_PAD_CTRL); - sc_pad_set(ipc_handle, SC_P_UART0_TX, UART_PAD_CTRL); - sc_pad_set(ipc_handle, SC_P_UART0_RTS_B, UART_PAD_CTRL); - sc_pad_set(ipc_handle, SC_P_UART0_CTS_B, UART_PAD_CTRL); + sc_pad_set(ipc_handle, IMX_PAD_UART_RX, UART_PAD_CTRL); + sc_pad_set(ipc_handle, IMX_PAD_UART_TX, UART_PAD_CTRL); + sc_pad_set(ipc_handle, IMX_PAD_UART_RTS_B, UART_PAD_CTRL); + sc_pad_set(ipc_handle, IMX_PAD_UART_CTS_B, UART_PAD_CTRL); lpuart32_serial_init(IMX_BOOT_UART_BASE); #endif diff --git a/plat/imx/imx8qm/include/platform_def.h b/plat/imx/imx8qm/include/platform_def.h index b54943da0..671c77f76 100644 --- a/plat/imx/imx8qm/include/platform_def.h +++ b/plat/imx/imx8qm/include/platform_def.h @@ -40,12 +40,22 @@ #define PLAT_CCI_BASE 0x52090000 #define CLUSTER0_CCI_SLVAE_IFACE 3 #define CLUSTER1_CCI_SLVAE_IFACE 4 + +/* UART */ +#if defined(IMX_USE_UART0) #define IMX_BOOT_UART_BASE 0x5a060000 +#elif defined(IMX_USE_UART1) +#define IMX_BOOT_UART_BASE 0x5a070000 +#else +#error "Provide proper UART number in IMX_DEBUG_UART" +#endif + #define IMX_BOOT_UART_BAUDRATE 115200 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE #define PLAT__CRASH_UART_CLK_IN_HZ 24000000 #define IMX_CONSOLE_BAUDRATE 115200 + #define SC_IPC_BASE 0x5d1b0000 #define IMX_GPT_LPCG_BASE 0x5d540000 #define IMX_GPT_BASE 0x5d140000 @@ -64,7 +74,6 @@ #define MAX_XLAT_TABLES 8 #define MAX_MMAP_REGIONS 12 -#define DEBUG_CONSOLE 0 -#define DEBUG_CONSOLE_A53 0 +#define DEBUG_CONSOLE_A53 DEBUG_CONSOLE #endif /* PLATFORM_DEF_H */ diff --git a/plat/imx/imx8qm/platform.mk b/plat/imx/imx8qm/platform.mk index 5ba9c3f7b..20ee05be9 100644 --- a/plat/imx/imx8qm/platform.mk +++ b/plat/imx/imx8qm/platform.mk @@ -43,3 +43,9 @@ ERRATA_A72_859971 := 1 ERRATA_A53_835769 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 + +IMX_DEBUG_UART ?= 0 +$(eval $(call add_define,IMX_USE_UART${IMX_DEBUG_UART})) + +DEBUG_CONSOLE ?= 0 +$(eval $(call add_define,DEBUG_CONSOLE)) diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index 7cba3a449..5f01416d8 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -39,6 +39,7 @@ .globl plat_crash_console_init .globl plat_crash_console_putc .globl plat_crash_console_flush + .weak plat_core_pos_by_mpidr .globl tegra_secure_entrypoint .globl plat_reset_handler @@ -140,17 +141,14 @@ endfunc plat_is_my_cpu_primary * unsigned int plat_my_core_pos(void); * * result: CorePos = CoreId + (ClusterId * cpus per cluster) + * Registers clobbered: x0, x8 * ---------------------------------------------------------- */ func plat_my_core_pos + mov x8, x30 mrs x0, mpidr_el1 - and x1, x0, #MPIDR_CPU_MASK - and x0, x0, #MPIDR_CLUSTER_MASK - lsr x0, x0, #MPIDR_AFFINITY_BITS - mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER - mul x0, x0, x2 - add x0, x1, x0 - ret + bl plat_core_pos_by_mpidr + ret x8 endfunc plat_my_core_pos /* ----------------------------------------------------- @@ -273,6 +271,42 @@ _end: mov x0, x20 ret endfunc plat_reset_handler + /* ------------------------------------------------------ + * int32_t plat_core_pos_by_mpidr(u_register_t mpidr) + * + * This function implements a part of the critical + * interface between the psci generic layer and the + * platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error + * code (-1) is returned in case the MPIDR is invalid. + * + * Clobbers: x0-x3 + * ------------------------------------------------------ + */ +func plat_core_pos_by_mpidr + lsr x1, x0, #MPIDR_AFF0_SHIFT + and x1, x1, #MPIDR_AFFLVL_MASK /* core id */ + lsr x2, x0, #MPIDR_AFF1_SHIFT + and x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */ + + /* core_id >= PLATFORM_MAX_CPUS_PER_CLUSTER */ + mov x0, #-1 + cmp x1, #(PLATFORM_MAX_CPUS_PER_CLUSTER - 1) + b.gt 1f + + /* cluster_id >= PLATFORM_CLUSTER_COUNT */ + cmp x2, #(PLATFORM_CLUSTER_COUNT - 1) + b.gt 1f + + /* CorePos = CoreId + (ClusterId * cpus per cluster) */ + mov x3, #PLATFORM_MAX_CPUS_PER_CLUSTER + mul x3, x3, x2 + add x0, x1, x3 + +1: + ret +endfunc plat_core_pos_by_mpidr + /* ---------------------------------------- * Secure entrypoint function for CPU boot * ---------------------------------------- diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c index 57daf6aeb..d964fc001 100644 --- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c +++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c @@ -8,6 +8,7 @@ #include <assert.h> #include <common/debug.h> #include <errno.h> +#include <stdbool.h> #include <stddef.h> #include <string.h> diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c index 92fa273b5..c3f95db4d 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -117,7 +117,8 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start, ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */ non_overlap_area_start, /* VA */ non_overlap_area_size, /* size */ - MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ + MT_NS | MT_RW | MT_EXECUTE_NEVER | + MT_NON_CACHEABLE); /* attrs */ assert(ret == 0); zeromem((void *)non_overlap_area_start, non_overlap_area_size); diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index a53f66078..5555f5df3 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -159,69 +159,7 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) */ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) { - uint32_t index; - uint32_t total_128kb_blocks = size_in_bytes >> 17; - uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12; - uint32_t val; - - INFO("Configuring TrustZone SRAM Memory Carveout\n"); - - /* - * Reset the access configuration registers to restrict access - * to the TZRAM aperture - */ - for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0; - index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); - index += 4U) { - tegra_mc_write_32(index, 0); - } - - /* - * Enable CPU access configuration registers to access the TZRAM aperture - */ - if (!tegra_chipid_is_t186()) { - val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0); - val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW; - tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val); - } - - /* - * Set the TZRAM base. TZRAM base must be 4k aligned, at least. - */ - assert((phys_base & (uint64_t)0xFFF) == 0U); - tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base); - tegra_mc_write_32(MC_TZRAM_BASE_HI, - (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK); - - /* - * Set the TZRAM size - * - * total size = (number of 128KB blocks) + (number of remaining 4KB - * blocks) - * - */ - val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) | - total_128kb_blocks; - tegra_mc_write_32(MC_TZRAM_SIZE, val); - - /* - * Lock the configuration settings by disabling TZ-only lock - * and locking the configuration against any future changes - * at all. - */ - val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG); - val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT; - val |= MC_GSC_LOCK_CFG_SETTINGS_BIT; - if (!tegra_chipid_is_t186()) { - val |= MC_GSC_ENABLE_CPU_SECURE_BIT; - } - tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val); - - /* - * MCE propagates the security configuration values across the - * CCPLEX. - */ - mce_update_gsc_tzram(); + ; /* do nothing */ } /* @@ -348,7 +286,8 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start, ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */ non_overlap_area_start, /* VA */ non_overlap_area_size, /* size */ - MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ + MT_NS | MT_RW | MT_EXECUTE_NEVER | + MT_NON_CACHEABLE); /* attrs */ assert(ret == 0); zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size); diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 46686c368..269afb196 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -39,15 +39,8 @@ * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ - IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); -static const uint64_t BL31_RW_END = BL_END; -static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE; -static const uint64_t BL31_RODATA_END = BL_RO_DATA_END; -static const uint64_t TEXT_START = BL_CODE_BASE; -static const uint64_t TEXT_END = BL_CODE_END; - extern uint64_t tegra_bl31_phys_base; static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; @@ -314,15 +307,12 @@ void bl31_plat_runtime_setup(void) void bl31_plat_arch_setup(void) { uint64_t rw_start = BL31_RW_START; - uint64_t rw_size = BL31_RW_END - BL31_RW_START; - uint64_t rodata_start = BL31_RODATA_BASE; - uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; - uint64_t code_base = TEXT_START; - uint64_t code_size = TEXT_END - TEXT_START; + uint64_t rw_size = BL_END - BL31_RW_START; + uint64_t rodata_start = BL_RO_DATA_BASE; + uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE; + uint64_t code_base = BL_CODE_BASE; + uint64_t code_size = BL_CODE_END - BL_CODE_BASE; const mmap_region_t *plat_mmio_map = NULL; -#if USE_COHERENT_MEM - uint32_t coh_start, coh_size; -#endif const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); /* @@ -349,15 +339,6 @@ void bl31_plat_arch_setup(void) code_size, MT_CODE | MT_SECURE); -#if USE_COHERENT_MEM - coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); - coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; - - mmap_add_region(coh_start, coh_start, - coh_size, - (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE); -#endif - /* map TZDRAM used by BL31 as coherent memory */ if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { mmap_add_region(params_from_bl2->tzdram_base, diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk index 50c9592f1..c946a7597 100644 --- a/plat/nvidia/tegra/common/tegra_common.mk +++ b/plat/nvidia/tegra/common/tegra_common.mk @@ -6,8 +6,7 @@ PLAT_INCLUDES := -Iplat/nvidia/tegra/include/drivers \ -Iplat/nvidia/tegra/include/lib \ - -Iplat/nvidia/tegra/include \ - -Iplat/nvidia/tegra/include/${TARGET_SOC} + -Iplat/nvidia/tegra/include include lib/xlat_tables_v2/xlat_tables.mk PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} @@ -32,5 +31,4 @@ BL31_SOURCES += drivers/delay_timer/delay_timer.c \ ${COMMON_DIR}/tegra_io_storage.c \ ${COMMON_DIR}/tegra_platform.c \ ${COMMON_DIR}/tegra_pm.c \ - ${COMMON_DIR}/tegra_sip_calls.c \ - ${COMMON_DIR}/tegra_topology.c + ${COMMON_DIR}/tegra_sip_calls.c diff --git a/plat/nvidia/tegra/common/tegra_gicv2.c b/plat/nvidia/tegra/common/tegra_gicv2.c index 293df8d4f..012107e3b 100644 --- a/plat/nvidia/tegra/common/tegra_gicv2.c +++ b/plat/nvidia/tegra/common/tegra_gicv2.c @@ -1,20 +1,23 @@ /* * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> - #include <platform_def.h> #include <common/bl_common.h> #include <drivers/arm/gicv2.h> #include <lib/utils.h> +#include <plat/common/platform.h> #include <tegra_private.h> #include <tegra_def.h> +static unsigned int tegra_target_masks[PLATFORM_CORE_COUNT]; + /****************************************************************************** * Tegra common helper to setup the GICv2 driver data. *****************************************************************************/ @@ -33,6 +36,8 @@ void tegra_gic_setup(const interrupt_prop_t *interrupt_props, tegra_gic_data.gicc_base = TEGRA_GICC_BASE; tegra_gic_data.interrupt_props = interrupt_props; tegra_gic_data.interrupt_props_num = interrupt_props_num; + tegra_gic_data.target_masks = tegra_target_masks; + tegra_gic_data.target_masks_num = ARRAY_SIZE(tegra_target_masks); gicv2_driver_init(&tegra_gic_data); } @@ -43,6 +48,7 @@ void tegra_gic_init(void) { gicv2_distif_init(); gicv2_pcpu_distif_init(); + gicv2_set_pe_target_mask(plat_my_core_pos()); gicv2_cpuif_enable(); } @@ -61,5 +67,6 @@ void tegra_gic_cpuif_deactivate(void) void tegra_gic_pcpu_init(void) { gicv2_pcpu_distif_init(); + gicv2_set_pe_target_mask(plat_my_core_pos()); gicv2_cpuif_enable(); } diff --git a/plat/nvidia/tegra/common/tegra_topology.c b/plat/nvidia/tegra/common/tegra_topology.c deleted file mode 100644 index 205b05165..000000000 --- a/plat/nvidia/tegra/common/tegra_topology.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <platform_def.h> - -#include <arch.h> -#include <lib/psci/psci.h> -#include <plat/common/platform.h> - -#pragma weak plat_core_pos_by_mpidr - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int32_t plat_core_pos_by_mpidr(u_register_t mpidr) -{ - u_register_t cluster_id, cpu_id; - int32_t result; - - cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & - (u_register_t)MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & - (u_register_t)MPIDR_AFFLVL_MASK; - - /* CorePos = CoreId + (ClusterId * cpus per cluster) */ - result = (int32_t)cpu_id + ((int32_t)cluster_id * - PLATFORM_MAX_CPUS_PER_CLUSTER); - - if (cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) { - result = PSCI_E_NOT_PRESENT; - } - - /* - * Validate cpu_id by checking whether it represents a CPU in - * one of the two clusters present on the platform. - */ - if (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER) { - result = PSCI_E_NOT_PRESENT; - } - - return result; -} diff --git a/plat/nvidia/tegra/include/drivers/flowctrl.h b/plat/nvidia/tegra/include/drivers/flowctrl.h index 54336b044..e5ab600b4 100644 --- a/plat/nvidia/tegra/include/drivers/flowctrl.h +++ b/plat/nvidia/tegra/include/drivers/flowctrl.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +10,8 @@ #include <lib/mmio.h> +#include <stdbool.h> + #include <tegra_def.h> #define FLOWCTRL_HALT_CPU0_EVENTS (0x0U) diff --git a/plat/nvidia/tegra/include/drivers/mce.h b/plat/nvidia/tegra/include/drivers/mce.h index 4470b6b8b..5f1bb4f28 100644 --- a/plat/nvidia/tegra/include/drivers/mce.h +++ b/plat/nvidia/tegra/include/drivers/mce.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,7 +69,6 @@ int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, int mce_update_reset_vector(void); int mce_update_gsc_videomem(void); int mce_update_gsc_tzdram(void); -int mce_update_gsc_tzram(void); __dead2 void mce_enter_ccplex_state(uint32_t state_idx); void mce_update_cstate_info(const mce_cstate_info_t *cstate); void mce_verify_firmware_version(void); diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index eb55def4a..91a24ca7e 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +13,19 @@ #include <tegra_def.h> +/******************************************************************************* + * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1 + ******************************************************************************/ +#if !SEPARATE_CODE_AND_RODATA +#error "SEPARATE_CODE_AND_RODATA should be set to 1" +#endif + +/* + * Platform binary types for linking + */ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + /* * Platform binary types for linking */ @@ -33,7 +47,7 @@ #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_MAX_CPUS_PER_CLUSTER) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ - PLATFORM_CLUSTER_COUNT + 1) + PLATFORM_CLUSTER_COUNT + U(1)) /******************************************************************************* * Platform console related constants @@ -72,4 +86,5 @@ #define MAX_IO_DEVICES U(0) #define MAX_IO_HANDLES U(0) + #endif /* PLATFORM_DEF_H */ diff --git a/plat/nvidia/tegra/include/t186/tegra186_private.h b/plat/nvidia/tegra/include/t186/tegra186_private.h index 60174ab54..4514e1477 100644 --- a/plat/nvidia/tegra/include/t186/tegra186_private.h +++ b/plat/nvidia/tegra/include/t186/tegra186_private.h @@ -7,10 +7,6 @@ #ifndef TEGRA186_PRIVATE_H #define TEGRA186_PRIVATE_H -void tegra186_cpu_reset_handler(void); -uint64_t tegra186_get_cpu_reset_handler_base(void); -uint64_t tegra186_get_cpu_reset_handler_size(void); -uint64_t tegra186_get_mc_ctx_offset(void); -void tegra186_set_system_suspend_entry(void); +uint64_t tegra186_get_mc_ctx_size(void); #endif /* TEGRA186_PRIVATE_H */ diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index dc0644514..e39f9cad6 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -10,6 +10,12 @@ #include <lib/utils_def.h> /******************************************************************************* + * Chip specific cluster and cpu numbers + ******************************************************************************/ +#define PLATFORM_CLUSTER_COUNT U(4) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) + +/******************************************************************************* * Chip specific page table and MMU setup constants ******************************************************************************/ #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40) diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index ad3cee4b4..f72c9cf3c 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -47,6 +47,8 @@ typedef struct plat_params_from_bl2 { uint64_t sc7entry_fw_size; /* System Suspend Entry Firmware base address */ uint64_t sc7entry_fw_base; + /* Enable dual execution */ + uint8_t enable_ccplex_lock_step; } plat_params_from_bl2_t; /******************************************************************************* diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk index d0ed5d57a..87588202c 100644 --- a/plat/nvidia/tegra/platform.mk +++ b/plat/nvidia/tegra/platform.mk @@ -13,7 +13,7 @@ $(eval $(call add_define,CRASH_REPORTING)) # enable assert() for release/debug builds ENABLE_ASSERTIONS := 1 -PLAT_LOG_LEVEL_ASSERT := 40 +PLAT_LOG_LEVEL_ASSERT := 50 $(eval $(call add_define,PLAT_LOG_LEVEL_ASSERT)) # enable dynamic memory mapping @@ -40,7 +40,7 @@ OVERRIDE_LIBC := 1 # Flag to enable WDT FIQ interrupt handling for Tegra SoCs # prior to Tegra186 -ENABLE_WDT_LEGACY_FIQ_HANDLING ?= 0 +ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING ?= 0 # Flag to allow relocation of BL32 image to TZDRAM during boot RELOCATE_BL32_IMAGE ?= 0 @@ -48,7 +48,7 @@ RELOCATE_BL32_IMAGE ?= 0 include plat/nvidia/tegra/common/tegra_common.mk include ${SOC_DIR}/platform_${TARGET_SOC}.mk -$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING)) +$(eval $(call add_define,ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING)) $(eval $(call add_define,RELOCATE_BL32_IMAGE)) # modify BUILD_PLAT to point to SoC specific build directory diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk index 183e1889c..16bd0ead2 100644 --- a/plat/nvidia/tegra/soc/t132/platform_t132.mk +++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk @@ -20,6 +20,9 @@ $(eval $(call add_define,MAX_XLAT_TABLES)) MAX_MMAP_REGIONS := 8 $(eval $(call add_define,MAX_MMAP_REGIONS)) +# platform files +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t132 + BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c index 9e42b2bcb..54d3b2ccd 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -386,14 +387,6 @@ int32_t mce_update_gsc_tzdram(void) } /******************************************************************************* - * Handler to update carveout values for TZ SysRAM aperture - ******************************************************************************/ -int32_t mce_update_gsc_tzram(void) -{ - return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZRAM); -} - -/******************************************************************************* * Handler to shutdown/reset the entire system ******************************************************************************/ __dead2 void mce_enter_ccplex_state(uint32_t state_idx) diff --git a/plat/nvidia/tegra/soc/t186/drivers/se/se.c b/plat/nvidia/tegra/soc/t186/drivers/se/se.c index dfb9de882..25f8cd028 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/se/se.c +++ b/plat/nvidia/tegra/soc/t186/drivers/se/se.c @@ -12,7 +12,6 @@ #include <bpmp_ipc.h> #include <pmc.h> #include <security_engine.h> -#include <tegra186_private.h> #include <tegra_private.h> #include "se_private.h" diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c index 09377bb09..4eb68e44a 100644 --- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c @@ -10,8 +10,8 @@ #include <mce.h> #include <memctrl_v2.h> -#include <tegra_mc_def.h> #include <tegra186_private.h> +#include <tegra_mc_def.h> #include <tegra_platform.h> #include <tegra_private.h> @@ -21,29 +21,6 @@ extern uint64_t tegra_bl31_phys_base; * Array to hold stream_id override config register offsets ******************************************************************************/ const static uint32_t tegra186_streamid_override_regs[] = { - MC_STREAMID_OVERRIDE_CFG_PTCR, - MC_STREAMID_OVERRIDE_CFG_AFIR, - MC_STREAMID_OVERRIDE_CFG_HDAR, - MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, - MC_STREAMID_OVERRIDE_CFG_NVENCSRD, - MC_STREAMID_OVERRIDE_CFG_SATAR, - MC_STREAMID_OVERRIDE_CFG_MPCORER, - MC_STREAMID_OVERRIDE_CFG_NVENCSWR, - MC_STREAMID_OVERRIDE_CFG_AFIW, - MC_STREAMID_OVERRIDE_CFG_HDAW, - MC_STREAMID_OVERRIDE_CFG_MPCOREW, - MC_STREAMID_OVERRIDE_CFG_SATAW, - MC_STREAMID_OVERRIDE_CFG_ISPRA, - MC_STREAMID_OVERRIDE_CFG_ISPWA, - MC_STREAMID_OVERRIDE_CFG_ISPWB, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, - MC_STREAMID_OVERRIDE_CFG_TSECSRD, - MC_STREAMID_OVERRIDE_CFG_TSECSWR, - MC_STREAMID_OVERRIDE_CFG_GPUSRD, - MC_STREAMID_OVERRIDE_CFG_GPUSWR, MC_STREAMID_OVERRIDE_CFG_SDMMCRA, MC_STREAMID_OVERRIDE_CFG_SDMMCRAA, MC_STREAMID_OVERRIDE_CFG_SDMMCR, @@ -52,47 +29,6 @@ const static uint32_t tegra186_streamid_override_regs[] = { MC_STREAMID_OVERRIDE_CFG_SDMMCWAA, MC_STREAMID_OVERRIDE_CFG_SDMMCW, MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, - MC_STREAMID_OVERRIDE_CFG_VICSRD, - MC_STREAMID_OVERRIDE_CFG_VICSWR, - MC_STREAMID_OVERRIDE_CFG_VIW, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD, - MC_STREAMID_OVERRIDE_CFG_NVDECSWR, - MC_STREAMID_OVERRIDE_CFG_APER, - MC_STREAMID_OVERRIDE_CFG_APEW, - MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, - MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, - MC_STREAMID_OVERRIDE_CFG_SESRD, - MC_STREAMID_OVERRIDE_CFG_SESWR, - MC_STREAMID_OVERRIDE_CFG_ETRR, - MC_STREAMID_OVERRIDE_CFG_ETRW, - MC_STREAMID_OVERRIDE_CFG_TSECSRDB, - MC_STREAMID_OVERRIDE_CFG_TSECSWRB, - MC_STREAMID_OVERRIDE_CFG_GPUSRD2, - MC_STREAMID_OVERRIDE_CFG_GPUSWR2, - MC_STREAMID_OVERRIDE_CFG_AXISR, - MC_STREAMID_OVERRIDE_CFG_AXISW, - MC_STREAMID_OVERRIDE_CFG_EQOSR, - MC_STREAMID_OVERRIDE_CFG_EQOSW, - MC_STREAMID_OVERRIDE_CFG_UFSHCR, - MC_STREAMID_OVERRIDE_CFG_UFSHCW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, - MC_STREAMID_OVERRIDE_CFG_BPMPR, - MC_STREAMID_OVERRIDE_CFG_BPMPW, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, - MC_STREAMID_OVERRIDE_CFG_AONR, - MC_STREAMID_OVERRIDE_CFG_AONW, - MC_STREAMID_OVERRIDE_CFG_AONDMAR, - MC_STREAMID_OVERRIDE_CFG_AONDMAW, - MC_STREAMID_OVERRIDE_CFG_SCER, - MC_STREAMID_OVERRIDE_CFG_SCEW, - MC_STREAMID_OVERRIDE_CFG_SCEDMAR, - MC_STREAMID_OVERRIDE_CFG_SCEDMAW, - MC_STREAMID_OVERRIDE_CFG_APEDMAR, - MC_STREAMID_OVERRIDE_CFG_APEDMAW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, - MC_STREAMID_OVERRIDE_CFG_VICSRD1, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 }; /******************************************************************************* @@ -711,13 +647,6 @@ tegra_mc_settings_t *tegra_get_mc_settings(void) void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) { uint32_t val; - uint64_t src_base_tzdram; - const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); - uint64_t src_len_in_bytes = BL31_END - BL31_START; - - /* base address of BL3-1 source in TZDRAM */ - src_base_tzdram = params_from_bl2->tzdram_base + - tegra186_get_cpu_reset_handler_size(); /* * Setup the Memory controller to allow only secure accesses to @@ -747,15 +676,6 @@ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val); /* - * save tzdram_addr_lo and ATF-size, this would be used in SC7-RF to - * generate SHA256. - */ - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO, - (uint32_t)src_base_tzdram); - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI, - (uint32_t)src_len_in_bytes); - - /* * MCE propagates the security configuration values across the * CCPLEX. */ diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index 179dd9654..6f58427b3 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -134,8 +134,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); /* save MC context to TZDRAM */ - mc_ctx_base = params_from_bl2->tzdram_base + - tegra186_get_mc_ctx_offset(); + mc_ctx_base = params_from_bl2->tzdram_base; tegra_mc_save_context((uintptr_t)mc_ctx_base); /* Prepare for system suspend */ @@ -158,9 +157,6 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U); - /* set system suspend state for house-keeping */ - tegra186_set_system_suspend_entry(); - } else { ; /* do nothing */ } @@ -289,7 +285,7 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { val = params_from_bl2->tzdram_base + - tegra186_get_cpu_reset_handler_size(); + tegra186_get_mc_ctx_size(); /* Initialise communication channel with BPMP */ assert(tegra_bpmp_ipc_init() == 0); @@ -316,10 +312,19 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta * BL3-1 over to TZDRAM. */ val = params_from_bl2->tzdram_base + - tegra186_get_cpu_reset_handler_size(); + tegra186_get_mc_ctx_size(); memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, (uintptr_t)BL31_END - (uintptr_t)BL31_BASE); + /* + * Save code base and size; this would be used by SC7-RF to + * verify binary + */ + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO, + (uint32_t)val); + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI, + (uint32_t)src_len_in_bytes); + ret = tegra_bpmp_ipc_disable_clock(TEGRA186_CLK_SE); if (ret != 0) { ERROR("Failed to disable clock\n"); diff --git a/plat/nvidia/tegra/soc/t186/plat_secondary.c b/plat/nvidia/tegra/soc/t186/plat_secondary.c index 16508093e..fbb550af9 100644 --- a/plat/nvidia/tegra/soc/t186/plat_secondary.c +++ b/plat/nvidia/tegra/soc/t186/plat_secondary.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,56 +12,30 @@ #include <lib/mmio.h> #include <mce.h> -#include <tegra186_private.h> #include <tegra_def.h> #include <tegra_private.h> -#define MISCREG_AA64_RST_LOW 0x2004U -#define MISCREG_AA64_RST_HIGH 0x2008U - #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU #define CPU_RESET_MODE_AA64 1U -extern void memcpy16(void *dest, const void *src, unsigned int length); - /******************************************************************************* * Setup secondary CPU vectors ******************************************************************************/ void plat_secondary_setup(void) { uint32_t addr_low, addr_high; - const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); - uint64_t cpu_reset_handler_base, cpu_reset_handler_size; INFO("Setting up secondary CPU boot\n"); - /* - * The BL31 code resides in the TZSRAM which loses state - * when we enter System Suspend. Copy the wakeup trampoline - * code to TZDRAM to help us exit from System Suspend. - */ - cpu_reset_handler_base = tegra186_get_cpu_reset_handler_base(); - cpu_reset_handler_size = tegra186_get_cpu_reset_handler_size(); - (void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base, - (const void *)(uintptr_t)cpu_reset_handler_base, - cpu_reset_handler_size); - /* TZDRAM base will be used as the "resume" address */ - addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; - addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); - - /* write lower 32 bits first, then the upper 11 bits */ - mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); - mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); + addr_low = (uintptr_t)&tegra_secure_entrypoint | CPU_RESET_MODE_AA64; + addr_high = (uintptr_t)(((uintptr_t)&tegra_secure_entrypoint >> 32U) & 0x7ffU); /* save reset vector to be used during SYSTEM_SUSPEND exit */ mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, addr_low); mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, addr_high); - - /* update reset vector address to the CCPLEX */ - (void)mce_update_reset_vector(); } diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S index 818c24b49..2fc2046d0 100644 --- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S @@ -12,135 +12,30 @@ #include <plat/common/common_def.h> #include <tegra_def.h> -#define TEGRA186_STATE_SYSTEM_SUSPEND 0x5C7 -#define TEGRA186_STATE_SYSTEM_RESUME 0x600D #define TEGRA186_MC_CTX_SIZE 0x93 - .globl tegra186_cpu_reset_handler - -/* CPU reset handler routine */ -func tegra186_cpu_reset_handler _align=4 - /* check if we are exiting system suspend state */ - adr x0, __tegra186_system_suspend_state - ldr x1, [x0] - mov x2, #TEGRA186_STATE_SYSTEM_SUSPEND - lsl x2, x2, #16 - add x2, x2, #TEGRA186_STATE_SYSTEM_SUSPEND - cmp x1, x2 - bne boot_cpu - - /* set system resume state */ - mov x1, #TEGRA186_STATE_SYSTEM_RESUME - lsl x1, x1, #16 - mov x2, #TEGRA186_STATE_SYSTEM_RESUME - add x1, x1, x2 - str x1, [x0] - dsb sy - - /* prepare to relocate to TZSRAM */ - mov x0, #BL31_BASE - adr x1, __tegra186_cpu_reset_handler_end - adr x2, __tegra186_cpu_reset_handler_data - ldr x2, [x2, #8] - - /* memcpy16 */ -m_loop16: - cmp x2, #16 - b.lt m_loop1 - ldp x3, x4, [x1], #16 - stp x3, x4, [x0], #16 - sub x2, x2, #16 - b m_loop16 - /* copy byte per byte */ -m_loop1: - cbz x2, boot_cpu - ldrb w3, [x1], #1 - strb w3, [x0], #1 - subs x2, x2, #1 - b.ne m_loop1 - -boot_cpu: - adr x0, __tegra186_cpu_reset_handler_data - ldr x0, [x0] - br x0 -endfunc tegra186_cpu_reset_handler + .globl tegra186_get_mc_ctx_size /* - * Tegra186 reset data (offset 0x0 - 0x430) + * Tegra186 reset data (offset 0x0 - 0x420) * - * 0x000: secure world's entrypoint - * 0x008: BL31 size (RO + RW) - * 0x00C: MC context start - * 0x42C: MC context end + * 0x000: MC context start + * 0x420: MC context end */ .align 4 - .type __tegra186_cpu_reset_handler_data, %object - .globl __tegra186_cpu_reset_handler_data -__tegra186_cpu_reset_handler_data: - .quad tegra_secure_entrypoint - .quad __BL31_END__ - BL31_BASE - - .globl __tegra186_system_suspend_state -__tegra186_system_suspend_state: - .quad 0 - - .align 4 - .globl __tegra186_mc_context __tegra186_mc_context: .rept TEGRA186_MC_CTX_SIZE .quad 0 .endr - .size __tegra186_cpu_reset_handler_data, \ - . - __tegra186_cpu_reset_handler_data .align 4 - .globl __tegra186_cpu_reset_handler_end -__tegra186_cpu_reset_handler_end: - - .globl tegra186_get_cpu_reset_handler_size - .globl tegra186_get_cpu_reset_handler_base - .globl tegra186_get_mc_ctx_offset - .globl tegra186_set_system_suspend_entry - -/* return size of the CPU reset handler */ -func tegra186_get_cpu_reset_handler_size - adr x0, __tegra186_cpu_reset_handler_end - adr x1, tegra186_cpu_reset_handler - sub x0, x0, x1 - ret -endfunc tegra186_get_cpu_reset_handler_size - -/* return the start address of the CPU reset handler */ -func tegra186_get_cpu_reset_handler_base - adr x0, tegra186_cpu_reset_handler - ret -endfunc tegra186_get_cpu_reset_handler_base +__tegra186_mc_context_end: /* return the size of the MC context */ -func tegra186_get_mc_ctx_offset - adr x0, __tegra186_mc_context - adr x1, tegra186_cpu_reset_handler +func tegra186_get_mc_ctx_size + adr x0, __tegra186_mc_context_end + adr x1, __tegra186_mc_context sub x0, x0, x1 ret -endfunc tegra186_get_mc_ctx_offset - -/* set system suspend state before SC7 entry */ -func tegra186_set_system_suspend_entry - mov x0, #TEGRA_MC_BASE - mov x3, #MC_SECURITY_CFG3_0 - ldr w1, [x0, x3] - lsl x1, x1, #32 - mov x3, #MC_SECURITY_CFG0_0 - ldr w2, [x0, x3] - orr x3, x1, x2 /* TZDRAM base */ - adr x0, __tegra186_system_suspend_state - adr x1, tegra186_cpu_reset_handler - sub x2, x0, x1 /* offset in TZDRAM */ - mov x0, #TEGRA186_STATE_SYSTEM_SUSPEND - lsl x0, x0, #16 - add x0, x0, #TEGRA186_STATE_SYSTEM_SUSPEND - str x0, [x3, x2] /* set value in TZDRAM */ - dsb sy - ret -endfunc tegra186_set_system_suspend_entry +endfunc tegra186_get_mc_ctx_size diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk index d79155f31..a5341236d 100644 --- a/plat/nvidia/tegra/soc/t186/platform_t186.mk +++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk @@ -14,7 +14,7 @@ $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) RESET_TO_BL31 := 1 -PROGRAMMABLE_RESET_ADDRESS := 1 +PROGRAMMABLE_RESET_ADDRESS := 0 COLD_BOOT_SINGLE_CPU := 1 @@ -37,7 +37,8 @@ MAX_MMAP_REGIONS := 27 $(eval $(call add_define,MAX_MMAP_REGIONS)) # platform files -PLAT_INCLUDES += -I${SOC_DIR}/drivers/include +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t186 \ + -I${SOC_DIR}/drivers/include BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h index 9ccb82382..7a68a4303 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h @@ -7,6 +7,8 @@ #ifndef T194_NVG_H #define T194_NVG_H +#include <lib/utils_def.h> + /** * t194_nvg.h - Header for the NVIDIA Generic interface (NVG). * Official documentation for this interface is included as part @@ -20,7 +22,7 @@ */ enum { TEGRA_NVG_VERSION_MAJOR = U(6), - TEGRA_NVG_VERSION_MINOR = U(6) + TEGRA_NVG_VERSION_MINOR = U(7) }; typedef enum { @@ -71,6 +73,9 @@ typedef enum { TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = U(77), TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = U(78), TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = U(79), + TEGRA_NVG_CHANNEL_RT_SAFE_MASK = U(80), + TEGRA_NVG_CHANNEL_RT_WINDOW_US = U(81), + TEGRA_NVG_CHANNEL_RT_FWD_PROGRESS_US = U(82), TEGRA_NVG_CHANNEL_LAST_INDEX } tegra_nvg_channel_id_t; @@ -153,7 +158,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_power_perf_channel_t { + struct { uint32_t perf_per_watt : U(1); uint32_t reserved_31_1 : U(31); uint32_t reserved_63_32 : U(32); @@ -162,7 +167,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_power_modes_channel_t { + struct { uint32_t low_battery : U(1); uint32_t reserved_1_1 : U(1); uint32_t battery_save : U(1); @@ -182,7 +187,7 @@ typedef union nvg_channel_1_data_u { typedef union { uint64_t flat; - struct nvg_ccplex_cache_control_channel_t { + struct { uint32_t gpu_ways : U(5); uint32_t reserved_7_5 : U(3); uint32_t gpu_only_ways : U(5); @@ -203,7 +208,7 @@ typedef union nvg_channel_2_data_u { typedef union { uint64_t flat; - struct nvg_wake_time_channel_t { + struct { uint32_t wake_time : U(32); uint32_t reserved_63_32 : U(32); } bits; @@ -211,7 +216,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_cstate_info_channel_t { + struct { uint32_t cluster_state : U(3); uint32_t reserved_6_3 : U(4); uint32_t update_cluster : U(1); @@ -242,7 +247,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_lower_bound_channel_t { + struct { uint32_t crossover_value : U(32); uint32_t reserved_63_32 : U(32); } bits; @@ -250,7 +255,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_cstate_stat_query_channel_t { + struct { uint32_t unit_id : U(4); uint32_t reserved_15_4 : U(12); uint32_t stat_id : U(16); @@ -260,7 +265,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_num_cores_channel_t { + struct { uint32_t num_cores : U(4); uint32_t reserved_31_4 : U(28); uint32_t reserved_63_32 : U(32); @@ -269,7 +274,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_unique_logical_id_channel_t { + struct { uint32_t unique_core_id : U(3); uint32_t reserved_31_3 : U(29); uint32_t reserved_63_32 : U(32); @@ -278,7 +283,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_logical_to_physical_mappings_channel_t { + struct { uint32_t lcore0_pcore_id : U(4); uint32_t lcore1_pcore_id : U(4); uint32_t lcore2_pcore_id : U(4); @@ -306,7 +311,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_is_sc7_allowed_channel_t { + struct { uint32_t is_sc7_allowed : U(1); uint32_t reserved_31_1 : U(31); uint32_t reserved_63_32 : U(32); @@ -315,7 +320,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_core_online_channel_t { + struct { uint32_t core_id : U(4); uint32_t reserved_31_4 : U(28); uint32_t reserved_63_32 : U(32); @@ -324,7 +329,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_cc3_control_channel_t { + struct { uint32_t freq_req : U(9); uint32_t reserved_30_9 : U(22); uint32_t enable : U(1); @@ -374,7 +379,7 @@ typedef enum { typedef union { uint64_t flat; - struct nvg_update_ccplex_gsc_channel_t { + struct { uint32_t gsc_enum : U(16); uint32_t reserved_31_16 : U(16); uint32_t reserved_63_32 : U(32); @@ -411,7 +416,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_hsm_error_ctrl_channel_t { + struct { uint32_t uncorr : U(1); uint32_t corr : U(1); uint32_t reserved_31_2 : U(30); diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index 00c671bcc..7edd7a09e 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -116,25 +116,6 @@ int32_t mce_update_gsc_tzdram(void) } /******************************************************************************* - * Handler to update carveout values for TZ SysRAM aperture - ******************************************************************************/ -int32_t mce_update_gsc_tzram(void) -{ - int32_t ret; - - /* - * MCE firmware is not running on simulation platforms. - */ - if (mce_firmware_not_supported()) { - ret = -EINVAL; - } else { - ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM); - } - - return ret; -} - -/******************************************************************************* * Handler to issue the UPDATE_CSTATE_INFO request ******************************************************************************/ void mce_update_cstate_info(const mce_cstate_info_t *cstate) diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 2d5f8e3c6..9a4d22e68 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -12,150 +12,6 @@ #include <tegra_platform.h> /******************************************************************************* - * Array to hold stream_id override config register offsets - ******************************************************************************/ -const static uint32_t tegra194_streamid_override_regs[] = { - MC_STREAMID_OVERRIDE_CFG_PTCR, - MC_STREAMID_OVERRIDE_CFG_HDAR, - MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, - MC_STREAMID_OVERRIDE_CFG_NVENCSRD, - MC_STREAMID_OVERRIDE_CFG_SATAR, - MC_STREAMID_OVERRIDE_CFG_MPCORER, - MC_STREAMID_OVERRIDE_CFG_NVENCSWR, - MC_STREAMID_OVERRIDE_CFG_HDAW, - MC_STREAMID_OVERRIDE_CFG_MPCOREW, - MC_STREAMID_OVERRIDE_CFG_SATAW, - MC_STREAMID_OVERRIDE_CFG_ISPRA, - MC_STREAMID_OVERRIDE_CFG_ISPFALR, - MC_STREAMID_OVERRIDE_CFG_ISPWA, - MC_STREAMID_OVERRIDE_CFG_ISPWB, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, - MC_STREAMID_OVERRIDE_CFG_TSECSRD, - MC_STREAMID_OVERRIDE_CFG_TSECSWR, - MC_STREAMID_OVERRIDE_CFG_SDMMCRA, - MC_STREAMID_OVERRIDE_CFG_SDMMCR, - MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, - MC_STREAMID_OVERRIDE_CFG_SDMMCWA, - MC_STREAMID_OVERRIDE_CFG_SDMMCW, - MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, - MC_STREAMID_OVERRIDE_CFG_VICSRD, - MC_STREAMID_OVERRIDE_CFG_VICSWR, - MC_STREAMID_OVERRIDE_CFG_VIW, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD, - MC_STREAMID_OVERRIDE_CFG_NVDECSWR, - MC_STREAMID_OVERRIDE_CFG_APER, - MC_STREAMID_OVERRIDE_CFG_APEW, - MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, - MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, - MC_STREAMID_OVERRIDE_CFG_SESRD, - MC_STREAMID_OVERRIDE_CFG_SESWR, - MC_STREAMID_OVERRIDE_CFG_AXIAPR, - MC_STREAMID_OVERRIDE_CFG_AXIAPW, - MC_STREAMID_OVERRIDE_CFG_ETRR, - MC_STREAMID_OVERRIDE_CFG_ETRW, - MC_STREAMID_OVERRIDE_CFG_TSECSRDB, - MC_STREAMID_OVERRIDE_CFG_TSECSWRB, - MC_STREAMID_OVERRIDE_CFG_AXISR, - MC_STREAMID_OVERRIDE_CFG_AXISW, - MC_STREAMID_OVERRIDE_CFG_EQOSR, - MC_STREAMID_OVERRIDE_CFG_EQOSW, - MC_STREAMID_OVERRIDE_CFG_UFSHCR, - MC_STREAMID_OVERRIDE_CFG_UFSHCW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, - MC_STREAMID_OVERRIDE_CFG_BPMPR, - MC_STREAMID_OVERRIDE_CFG_BPMPW, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, - MC_STREAMID_OVERRIDE_CFG_AONR, - MC_STREAMID_OVERRIDE_CFG_AONW, - MC_STREAMID_OVERRIDE_CFG_AONDMAR, - MC_STREAMID_OVERRIDE_CFG_AONDMAW, - MC_STREAMID_OVERRIDE_CFG_SCER, - MC_STREAMID_OVERRIDE_CFG_SCEW, - MC_STREAMID_OVERRIDE_CFG_SCEDMAR, - MC_STREAMID_OVERRIDE_CFG_SCEDMAW, - MC_STREAMID_OVERRIDE_CFG_APEDMAR, - MC_STREAMID_OVERRIDE_CFG_APEDMAW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, - MC_STREAMID_OVERRIDE_CFG_VICSRD1, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, - MC_STREAMID_OVERRIDE_CFG_VIFALR, - MC_STREAMID_OVERRIDE_CFG_VIFALW, - MC_STREAMID_OVERRIDE_CFG_DLA0RDA, - MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, - MC_STREAMID_OVERRIDE_CFG_DLA0WRA, - MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, - MC_STREAMID_OVERRIDE_CFG_DLA1RDA, - MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, - MC_STREAMID_OVERRIDE_CFG_DLA1WRA, - MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, - MC_STREAMID_OVERRIDE_CFG_PVA0RDA, - MC_STREAMID_OVERRIDE_CFG_PVA0RDB, - MC_STREAMID_OVERRIDE_CFG_PVA0RDC, - MC_STREAMID_OVERRIDE_CFG_PVA0WRA, - MC_STREAMID_OVERRIDE_CFG_PVA0WRB, - MC_STREAMID_OVERRIDE_CFG_PVA0WRC, - MC_STREAMID_OVERRIDE_CFG_PVA1RDA, - MC_STREAMID_OVERRIDE_CFG_PVA1RDB, - MC_STREAMID_OVERRIDE_CFG_PVA1RDC, - MC_STREAMID_OVERRIDE_CFG_PVA1WRA, - MC_STREAMID_OVERRIDE_CFG_PVA1WRB, - MC_STREAMID_OVERRIDE_CFG_PVA1WRC, - MC_STREAMID_OVERRIDE_CFG_RCER, - MC_STREAMID_OVERRIDE_CFG_RCEW, - MC_STREAMID_OVERRIDE_CFG_RCEDMAR, - MC_STREAMID_OVERRIDE_CFG_RCEDMAW, - MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, - MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, - MC_STREAMID_OVERRIDE_CFG_PCIE0R, - MC_STREAMID_OVERRIDE_CFG_PCIE0W, - MC_STREAMID_OVERRIDE_CFG_PCIE1R, - MC_STREAMID_OVERRIDE_CFG_PCIE1W, - MC_STREAMID_OVERRIDE_CFG_PCIE2AR, - MC_STREAMID_OVERRIDE_CFG_PCIE2AW, - MC_STREAMID_OVERRIDE_CFG_PCIE3R, - MC_STREAMID_OVERRIDE_CFG_PCIE3W, - MC_STREAMID_OVERRIDE_CFG_PCIE4R, - MC_STREAMID_OVERRIDE_CFG_PCIE4W, - MC_STREAMID_OVERRIDE_CFG_PCIE5R, - MC_STREAMID_OVERRIDE_CFG_PCIE5W, - MC_STREAMID_OVERRIDE_CFG_ISPFALW, - MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, - MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, - MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, - MC_STREAMID_OVERRIDE_CFG_PCIE5R1, - MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, - MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, - MC_STREAMID_OVERRIDE_CFG_ISPRA1, - MC_STREAMID_OVERRIDE_CFG_PCIE0R1, - MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD, - MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1, - MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR, - MC_STREAMID_OVERRIDE_CFG_MIU0R, - MC_STREAMID_OVERRIDE_CFG_MIU0W, - MC_STREAMID_OVERRIDE_CFG_MIU1R, - MC_STREAMID_OVERRIDE_CFG_MIU1W, - MC_STREAMID_OVERRIDE_CFG_MIU2R, - MC_STREAMID_OVERRIDE_CFG_MIU2W, - MC_STREAMID_OVERRIDE_CFG_MIU3R, - MC_STREAMID_OVERRIDE_CFG_MIU3W, - MC_STREAMID_OVERRIDE_CFG_MIU4R, - MC_STREAMID_OVERRIDE_CFG_MIU4W, - MC_STREAMID_OVERRIDE_CFG_MIU5R, - MC_STREAMID_OVERRIDE_CFG_MIU5W, - MC_STREAMID_OVERRIDE_CFG_MIU6R, - MC_STREAMID_OVERRIDE_CFG_MIU6W, - MC_STREAMID_OVERRIDE_CFG_MIU7R, - MC_STREAMID_OVERRIDE_CFG_MIU7W -}; - -/******************************************************************************* * Array to hold the security configs for stream IDs ******************************************************************************/ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { @@ -571,8 +427,6 @@ static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void) * Struct to hold the memory controller settings ******************************************************************************/ static tegra_mc_settings_t tegra194_mc_settings = { - .streamid_override_cfg = tegra194_streamid_override_regs, - .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), .streamid_security_cfg = tegra194_streamid_sec_cfgs, .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), .get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index d92025b8b..ce5815b46 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -368,7 +368,11 @@ int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) { + const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); + uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step; uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; + cpu_context_t *ctx = cm_get_context(NON_SECURE); + uint64_t actlr_elx; /* * Reset power state info for CPUs when onlining, we set @@ -377,6 +381,10 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) * will re-init this info from non-secure software when the * core come online. */ + actlr_elx = read_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1)); + actlr_elx &= ~DENVER_CPU_PMSTATE_MASK; + actlr_elx |= DENVER_CPU_PMSTATE_C1; + write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); /* * Check if we are exiting from deep sleep and restore SE @@ -446,13 +454,23 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) mmio_write_32(TEGRA_XUSB_PADCTL_BASE + XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); } + } - /* - * Reset power state info for the last core doing SC7 - * entry and exit, we set deepest power state as CC7 - * and SC7 for SC7 entry which may not be requested by - * non-secure SW which controls idle states. - */ + /* + * Enable dual execution optimized translations for all ELx. + */ + if (enable_ccplex_lock_step != 0U) { + actlr_elx = read_actlr_el3(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3; + write_actlr_el3(actlr_elx); + + actlr_elx = read_actlr_el2(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2; + write_actlr_el2(actlr_elx); + + actlr_elx = read_actlr_el1(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1; + write_actlr_el1(actlr_elx); } return PSCI_E_SUCCESS; diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 235fba43c..82555403e 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -201,6 +201,10 @@ void plat_enable_console(int32_t id) ******************************************************************************/ void plat_early_platform_setup(void) { + const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); + uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step; + uint64_t actlr_elx; + /* sanity check MCE firmware compatibility */ mce_verify_firmware_version(); @@ -250,6 +254,23 @@ void plat_early_platform_setup(void) mmio_write_32(TEGRA_XUSB_PADCTL_BASE + XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); } + + /* + * Enable dual execution optimized translations for all ELx. + */ + if (enable_ccplex_lock_step != 0U) { + actlr_elx = read_actlr_el3(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3; + write_actlr_el3(actlr_elx); + + actlr_elx = read_actlr_el2(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2; + write_actlr_el2(actlr_elx); + + actlr_elx = read_actlr_el1(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1; + write_actlr_el1(actlr_elx); + } } /* Secure IRQs for Tegra194 */ diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index 33694a16d..884762de7 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -16,11 +16,13 @@ #include <common/runtime_svc.h> #include <tegra_private.h> #include <tegra_platform.h> +#include <smmu.h> #include <stdbool.h> /******************************************************************************* * Tegra194 SiP SMCs ******************************************************************************/ +#define TEGRA_SIP_GET_SMMU_PER 0xC200FF00U /******************************************************************************* * This function is responsible for handling all T194 SiP calls @@ -34,13 +36,43 @@ int32_t plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags) { - int32_t ret = -ENOTSUP; + int32_t ret = 0; + uint32_t i, smmu_per[6] = {0}; + uint32_t num_smmu_devices = plat_get_num_smmu_devices(); + uint64_t per[3] = {0ULL}; - (void)smc_fid; (void)x1; (void)x4; (void)cookie; (void)flags; + switch (smc_fid) { + case TEGRA_SIP_GET_SMMU_PER: + + /* make sure we dont go past the array length */ + assert(num_smmu_devices <= ARRAY_SIZE(smmu_per)); + + /* read all supported SMMU_PER records */ + for (i = 0U; i < num_smmu_devices; i++) { + smmu_per[i] = tegra_smmu_read_32(i, SMMU_GSR0_PER); + } + + /* pack results into 3 64bit variables. */ + per[0] = smmu_per[0] | ((uint64_t)smmu_per[1] << 32U); + per[1] = smmu_per[2] | ((uint64_t)smmu_per[3] << 32U); + per[2] = smmu_per[4] | ((uint64_t)smmu_per[5] << 32U); + + /* provide the results via X1-X3 CPU registers */ + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]); + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]); + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]); + + break; + + default: + ret = -ENOTSUP; + break; + } + return ret; } diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 78766fcbe..c02128ccc 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -24,12 +24,6 @@ COLD_BOOT_SINGLE_CPU := 1 TZDRAM_BASE := 0x40000000 $(eval $(call add_define,TZDRAM_BASE)) -PLATFORM_CLUSTER_COUNT := 4 -$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) - -PLATFORM_MAX_CPUS_PER_CLUSTER := 2 -$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) - MAX_XLAT_TABLES := 25 $(eval $(call add_define,MAX_XLAT_TABLES)) @@ -37,7 +31,8 @@ MAX_MMAP_REGIONS := 30 $(eval $(call add_define,MAX_MMAP_REGIONS)) # platform files -PLAT_INCLUDES += -I${SOC_DIR}/drivers/include +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \ + -I${SOC_DIR}/drivers/include BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ diff --git a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c index 635018dbc..48608583d 100644 --- a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c +++ b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c @@ -927,17 +927,12 @@ static void tegra_se_enable_clocks(void) val &= ~ENTROPY_RESET_BIT; mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEVICES_W, val); - if (!tegra_chipid_is_t210_b01()) { - - /* - * T210 SE clock source is turned off in kernel, to simplify - * SE clock source setting, we switch SE clock source to - * CLK_M, SE_CLK_DIVISOR = 0. T210 B01 SE clock source is - * always on, so don't need this setting. - */ - mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_RST_CTL_CLK_SRC_SE, - SE_CLK_SRC_CLK_M); - } + /* + * Switch SE clock source to CLK_M, to make sure SE clock + * is on when saving SE context + */ + mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_RST_CTL_CLK_SRC_SE, + SE_CLK_SRC_CLK_M); /* Enable SE clock */ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_V); diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c index f29e624ea..7f73ea506 100644 --- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c @@ -534,6 +534,13 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) } /* + * Mark this CPU as ON in the cpu_powergate_mask[], + * so that we use Flow Controller for all subsequent + * power ups. + */ + cpu_powergate_mask[plat_my_core_pos()] = 1; + + /* * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's * used for power management and boot purposes. Inform the BPMP that * we have completed the cluster power up. @@ -561,7 +568,6 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr) /* Turn on CPU using flow controller or PMC */ if (cpu_powergate_mask[cpu] == 0) { tegra_pmc_cpu_on(cpu); - cpu_powergate_mask[cpu] = 1; } else { tegra_fc_cpu_on(cpu); } diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk index ba827a073..14e3324a8 100644 --- a/plat/nvidia/tegra/soc/t210/platform_t210.mk +++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk @@ -23,10 +23,10 @@ $(eval $(call add_define,MAX_XLAT_TABLES)) MAX_MMAP_REGIONS := 16 $(eval $(call add_define,MAX_MMAP_REGIONS)) -ENABLE_WDT_LEGACY_FIQ_HANDLING := 1 -$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING)) +ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING := 1 -PLAT_INCLUDES += -I${SOC_DIR}/drivers/se +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t210 \ + -I${SOC_DIR}/drivers/se BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/cortex_a53.S \ |