diff options
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/arm/common/arm_common.c | 20 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/aarch64/zynqmp_common.c | 15 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/include/platform_def.h | 2 |
3 files changed, 33 insertions, 4 deletions
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 11bdeac66..32fd9ee68 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -160,6 +160,9 @@ void arm_configure_sys_timer(void) { unsigned int reg_val; + /* Read the frequency of the system counter */ + unsigned int freq_val = plat_get_syscnt_freq2(); + #if ARM_CONFIG_CNTACR reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); @@ -169,6 +172,23 @@ void arm_configure_sys_timer(void) reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); + + /* + * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ + * system register initialized during psci_arch_setup() is different + * from this and has to be updated independently. + */ + mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); + +#ifdef PLAT_juno + /* + * Initialize CNTFRQ register in Non-secure CNTBase frame. + * This is only required for Juno, because it doesn't follow ARM ARM + * in that the value updated in CNTFRQ is not reflected in CNTBASE_CNTFRQ. + * Hence update the value manually. + */ + mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASE_CNTFRQ, freq_val); +#endif } #endif /* ARM_SYS_TIMCTL_BASE */ diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c index b144c84bd..c3612706a 100644 --- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c +++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -205,12 +205,21 @@ static char *zynqmp_get_silicon_idcode_name(void) { uint32_t id, ver, chipid[2]; size_t i, j, len; - enum pm_ret_status ret; const char *name = "EG/EV"; - ret = pm_get_chipid(chipid); - if (ret) +#ifdef IMAGE_BL32 + /* + * For BL32, get the chip id info directly by reading corresponding + * registers instead of making pm call. This has limitation + * that these registers should be configured to have access + * from APU which is default case. + */ + chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET); + chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET); +#else + if (pm_get_chipid(chipid) != PM_RET_SUCCESS) return "UNKN"; +#endif id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | ZYNQMP_CSU_IDCODE_SVD_MASK); diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index ebbc8c2cd..49766cc92 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -34,7 +34,7 @@ * little space for growth. */ #ifndef ZYNQMP_ATF_MEM_BASE -#if !DEBUG +#if !DEBUG && defined(SPD_none) # define BL31_BASE 0xfffea000 # define BL31_LIMIT 0xffffffff #else |