diff options
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/arm/board/fvp/include/platform_def.h | 9 | ||||
| -rw-r--r-- | plat/arm/board/juno/include/platform_def.h | 38 | ||||
| -rw-r--r-- | plat/arm/common/arm_gicv2.c | 17 | ||||
| -rw-r--r-- | plat/arm/common/arm_gicv3.c | 18 | ||||
| -rw-r--r-- | plat/common/plat_gicv2.c | 161 | ||||
| -rw-r--r-- | plat/common/plat_gicv3.c | 118 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/include/platform_def.h | 46 | ||||
| -rw-r--r-- | plat/mediatek/mt8173/include/platform_def.h | 33 | ||||
| -rw-r--r-- | plat/socionext/uniphier/uniphier_gicv3.c | 63 | ||||
| -rw-r--r-- | plat/socionext/uniphier/uniphier_rotpk.S | 1 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/include/platform_def.h | 36 |
11 files changed, 439 insertions, 101 deletions
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index e4f942596..e95358035 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -136,4 +136,13 @@ #define PLAT_ARM_G0_IRQS ARM_G0_IRQS +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 3c44a1e9a..395d1fb6d 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -193,23 +193,27 @@ */ #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000 -/* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ - ARM_G1S_IRQS, \ - JUNO_IRQ_DMA_SMMU, \ - JUNO_IRQ_HDLCD0_SMMU, \ - JUNO_IRQ_HDLCD1_SMMU, \ - JUNO_IRQ_USB_SMMU, \ - JUNO_IRQ_THIN_LINKS_SMMU, \ - JUNO_IRQ_SEC_I2C, \ - JUNO_IRQ_GPU_SMMU_1, \ - JUNO_IRQ_ETR_SMMU - -#define PLAT_ARM_G0_IRQS ARM_G0_IRQS +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + CSS_G1S_IRQ_PROPS(grp), \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) /* * Required ARM CSS SoC based platform porting definitions diff --git a/plat/arm/common/arm_gicv2.c b/plat/arm/common/arm_gicv2.c index 521fa8cd6..aac0248c6 100644 --- a/plat/arm/common/arm_gicv2.c +++ b/plat/arm/common/arm_gicv2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,16 +23,20 @@ * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 * interrupts. *****************************************************************************/ -static const unsigned int g0_interrupt_array[] = { - PLAT_ARM_G1S_IRQS, - PLAT_ARM_G0_IRQS +static const interrupt_prop_t arm_interrupt_props[] = { + PLAT_ARM_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), + PLAT_ARM_G0_IRQ_PROPS(GICV2_INTR_GROUP0) }; +static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; + static const gicv2_driver_data_t arm_gic_data = { .gicd_base = PLAT_ARM_GICD_BASE, .gicc_base = PLAT_ARM_GICC_BASE, - .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), - .g0_interrupt_array = g0_interrupt_array, + .interrupt_props = arm_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), + .target_masks = target_mask_array, + .target_masks_num = ARRAY_SIZE(target_mask_array), }; /****************************************************************************** @@ -72,6 +76,7 @@ void plat_arm_gic_cpuif_disable(void) void plat_arm_gic_pcpu_init(void) { gicv2_pcpu_distif_init(); + gicv2_set_pe_target_mask(plat_my_core_pos()); } /****************************************************************************** diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index c9bba0950..cec6a9df7 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -6,6 +6,7 @@ #include <arm_def.h> #include <gicv3.h> +#include <interrupt_props.h> #include <plat_arm.h> #include <platform.h> #include <platform_def.h> @@ -25,14 +26,9 @@ /* The GICv3 driver only needs to be initialized in EL3 */ static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; -/* Array of Group1 secure interrupts to be configured by the gic driver */ -static const unsigned int g1s_interrupt_array[] = { - PLAT_ARM_G1S_IRQS -}; - -/* Array of Group0 interrupts to be configured by the gic driver */ -static const unsigned int g0_interrupt_array[] = { - PLAT_ARM_G0_IRQS +static const interrupt_prop_t arm_interrupt_props[] = { + PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), + PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0) }; /* @@ -58,10 +54,8 @@ static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr) const gicv3_driver_data_t arm_gic_data = { .gicd_base = PLAT_ARM_GICD_BASE, .gicr_base = PLAT_ARM_GICR_BASE, - .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), - .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), - .g0_interrupt_array = g0_interrupt_array, - .g1s_interrupt_array = g1s_interrupt_array, + .interrupt_props = arm_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), .rdistif_num = PLATFORM_CORE_COUNT, .rdistif_base_addrs = rdistif_base_addrs, .mpidr_to_core_pos = arm_gicv3_mpidr_hash diff --git a/plat/common/plat_gicv2.c b/plat/common/plat_gicv2.c index 50a81818c..05fabcab1 100644 --- a/plat/common/plat_gicv2.c +++ b/plat/common/plat_gicv2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #include <gic_common.h> #include <gicv2.h> #include <interrupt_mgmt.h> +#include <platform.h> /* * The following platform GIC functions are weakly defined. They @@ -20,6 +21,18 @@ #pragma weak plat_ic_end_of_interrupt #pragma weak plat_interrupt_type_to_line +#pragma weak plat_ic_get_running_priority +#pragma weak plat_ic_is_spi +#pragma weak plat_ic_is_ppi +#pragma weak plat_ic_is_sgi +#pragma weak plat_ic_get_interrupt_active +#pragma weak plat_ic_enable_interrupt +#pragma weak plat_ic_disable_interrupt +#pragma weak plat_ic_set_interrupt_priority +#pragma weak plat_ic_set_interrupt_type +#pragma weak plat_ic_raise_el3_sgi +#pragma weak plat_ic_set_spi_routing + /* * This function returns the highest priority pending interrupt at * the Interrupt controller @@ -53,8 +66,13 @@ uint32_t plat_ic_get_pending_interrupt_type(void) id = gicv2_get_pending_interrupt_type(); /* Assume that all secure interrupts are S-EL1 interrupts */ - if (id < PENDING_G1_INTID) + if (id < PENDING_G1_INTID) { +#if GICV2_G0_FOR_EL3 + return INTR_TYPE_EL3; +#else return INTR_TYPE_S_EL1; +#endif + } if (id == GIC_SPURIOUS_INTERRUPT) return INTR_TYPE_INVAL; @@ -83,7 +101,12 @@ uint32_t plat_ic_get_interrupt_type(uint32_t id) type = gicv2_get_interrupt_group(id); /* Assume that all secure interrupts are S-EL1 interrupts */ - return (type) ? INTR_TYPE_NS : INTR_TYPE_S_EL1; + return type == GICV2_INTR_GROUP1 ? INTR_TYPE_NS : +#if GICV2_G0_FOR_EL3 + INTR_TYPE_EL3; +#else + INTR_TYPE_S_EL1; +#endif } /* @@ -122,3 +145,135 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, return ((gicv2_is_fiq_enabled()) ? __builtin_ctz(SCR_FIQ_BIT) : __builtin_ctz(SCR_IRQ_BIT)); } + +unsigned int plat_ic_get_running_priority(void) +{ + return gicv2_get_running_priority(); +} + +int plat_ic_is_spi(unsigned int id) +{ + return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); +} + +int plat_ic_is_ppi(unsigned int id) +{ + return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); +} + +int plat_ic_is_sgi(unsigned int id) +{ + return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); +} + +unsigned int plat_ic_get_interrupt_active(unsigned int id) +{ + return gicv2_get_interrupt_active(id); +} + +void plat_ic_enable_interrupt(unsigned int id) +{ + gicv2_enable_interrupt(id); +} + +void plat_ic_disable_interrupt(unsigned int id) +{ + gicv2_disable_interrupt(id); +} + +void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) +{ + gicv2_set_interrupt_priority(id, priority); +} + +int plat_ic_has_interrupt_type(unsigned int type) +{ + switch (type) { +#if GICV2_G0_FOR_EL3 + case INTR_TYPE_EL3: +#else + case INTR_TYPE_S_EL1: +#endif + case INTR_TYPE_NS: + return 1; + default: + return 0; + } +} + +void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) +{ + int gicv2_type = 0; + + /* Map canonical interrupt type to GICv2 type */ + switch (type) { +#if GICV2_G0_FOR_EL3 + case INTR_TYPE_EL3: +#else + case INTR_TYPE_S_EL1: +#endif + gicv2_type = GICV2_INTR_GROUP0; + break; + case INTR_TYPE_NS: + gicv2_type = GICV2_INTR_GROUP1; + break; + default: + assert(0); + } + + gicv2_set_interrupt_type(id, gicv2_type); +} + +void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) +{ +#if GICV2_G0_FOR_EL3 + int id; + + /* Target must be a valid MPIDR in the system */ + id = plat_core_pos_by_mpidr(target); + assert(id >= 0); + + /* Verify that this is a secure SGI */ + assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); + + gicv2_raise_sgi(sgi_num, id); +#else + assert(0); +#endif +} + +void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, + u_register_t mpidr) +{ + int proc_num = 0; + + switch (routing_mode) { + case INTR_ROUTING_MODE_PE: + proc_num = plat_core_pos_by_mpidr(mpidr); + assert(proc_num >= 0); + break; + case INTR_ROUTING_MODE_ANY: + /* Bit mask selecting all 8 CPUs as candidates */ + proc_num = -1; + break; + default: + assert(0); + } + + gicv2_set_spi_routing(id, proc_num); +} + +void plat_ic_set_interrupt_pending(unsigned int id) +{ + gicv2_set_interrupt_pending(id); +} + +void plat_ic_clear_interrupt_pending(unsigned int id) +{ + gicv2_clear_interrupt_pending(id); +} + +unsigned int plat_ic_set_priority_mask(unsigned int mask) +{ + return gicv2_set_pmr(mask); +} diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c index 030a1d902..52ceb6a7c 100644 --- a/plat/common/plat_gicv3.c +++ b/plat/common/plat_gicv3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,6 +26,20 @@ #pragma weak plat_ic_end_of_interrupt #pragma weak plat_interrupt_type_to_line +#pragma weak plat_ic_get_running_priority +#pragma weak plat_ic_is_spi +#pragma weak plat_ic_is_ppi +#pragma weak plat_ic_is_sgi +#pragma weak plat_ic_get_interrupt_active +#pragma weak plat_ic_enable_interrupt +#pragma weak plat_ic_disable_interrupt +#pragma weak plat_ic_set_interrupt_priority +#pragma weak plat_ic_set_interrupt_type +#pragma weak plat_ic_raise_el3_sgi +#pragma weak plat_ic_set_spi_routing +#pragma weak plat_ic_set_interrupt_pending +#pragma weak plat_ic_clear_interrupt_pending + CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) && (INTR_TYPE_NS == INTR_GROUP1NS) && (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch); @@ -155,6 +169,108 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, return __builtin_ctz(SCR_FIQ_BIT); } } + +unsigned int plat_ic_get_running_priority(void) +{ + return gicv3_get_running_priority(); +} + +int plat_ic_is_spi(unsigned int id) +{ + return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); +} + +int plat_ic_is_ppi(unsigned int id) +{ + return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); +} + +int plat_ic_is_sgi(unsigned int id) +{ + return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); +} + +unsigned int plat_ic_get_interrupt_active(unsigned int id) +{ + return gicv3_get_interrupt_active(id, plat_my_core_pos()); +} + +void plat_ic_enable_interrupt(unsigned int id) +{ + gicv3_enable_interrupt(id, plat_my_core_pos()); +} + +void plat_ic_disable_interrupt(unsigned int id) +{ + gicv3_disable_interrupt(id, plat_my_core_pos()); +} + +void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) +{ + gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority); +} + +int plat_ic_has_interrupt_type(unsigned int type) +{ + assert((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) || + (type == INTR_TYPE_NS)); + return 1; +} + +void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) +{ + gicv3_set_interrupt_type(id, plat_my_core_pos(), type); +} + +void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) +{ + /* Target must be a valid MPIDR in the system */ + assert(plat_core_pos_by_mpidr(target) >= 0); + + /* Verify that this is a secure EL3 SGI */ + assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); + + gicv3_raise_secure_g0_sgi(sgi_num, target); +} + +void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, + u_register_t mpidr) +{ + unsigned int irm = 0; + + switch (routing_mode) { + case INTR_ROUTING_MODE_PE: + assert(plat_core_pos_by_mpidr(mpidr) >= 0); + irm = GICV3_IRM_PE; + break; + case INTR_ROUTING_MODE_ANY: + irm = GICV3_IRM_ANY; + break; + default: + assert(0); + } + + gicv3_set_spi_routing(id, irm, mpidr); +} + +void plat_ic_set_interrupt_pending(unsigned int id) +{ + /* Disallow setting SGIs pending */ + assert(id >= MIN_PPI_ID); + gicv3_set_interrupt_pending(id, plat_my_core_pos()); +} + +void plat_ic_clear_interrupt_pending(unsigned int id) +{ + /* Disallow setting SGIs pending */ + assert(id >= MIN_PPI_ID); + gicv3_clear_interrupt_pending(id, plat_my_core_pos()); +} + +unsigned int plat_ic_set_priority_mask(unsigned int mask) +{ + return gicv3_set_pmr(mask); +} #endif #ifdef IMAGE_BL32 diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h index 1b44dd75d..b7afe8201 100644 --- a/plat/hisilicon/poplar/include/platform_def.h +++ b/plat/hisilicon/poplar/include/platform_def.h @@ -9,6 +9,8 @@ #include <arch.h> #include <common_def.h> +#include <gic_common.h> +#include <interrupt_props.h> #include <tbbr/tbbr_img_def.h> #include "hi3798cv200.h" #include "poplar_layout.h" /* BL memory region sizes, etc */ @@ -69,20 +71,34 @@ #define PLAT_ARM_GICD_BASE GICD_BASE #define PLAT_ARM_GICC_BASE GICC_BASE -#define PLAT_ARM_G1S_IRQS HISI_IRQ_SEC_SGI_0, \ - HISI_IRQ_SEC_SGI_1, \ - HISI_IRQ_SEC_SGI_2, \ - HISI_IRQ_SEC_SGI_3, \ - HISI_IRQ_SEC_SGI_4, \ - HISI_IRQ_SEC_SGI_5, \ - HISI_IRQ_SEC_SGI_6, \ - HISI_IRQ_SEC_SGI_7, \ - HISI_IRQ_SEC_TIMER0, \ - HISI_IRQ_SEC_TIMER1, \ - HISI_IRQ_SEC_TIMER2, \ - HISI_IRQ_SEC_TIMER3, \ - HISI_IRQ_SEC_AXI - -#define PLAT_ARM_G0_IRQS +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_TIMER0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_TIMER1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_TIMER2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_TIMER3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_AXI, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/mediatek/mt8173/include/platform_def.h b/plat/mediatek/mt8173/include/platform_def.h index 2f0b14161..76e694bc5 100644 --- a/plat/mediatek/mt8173/include/platform_def.h +++ b/plat/mediatek/mt8173/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #ifndef __PLATFORM_DEF_H__ #define __PLATFORM_DEF_H__ +#include <gic_common.h> +#include <interrupt_props.h> #include "mt8173_def.h" @@ -115,15 +117,24 @@ #define PLAT_ARM_GICD_BASE BASE_GICD_BASE #define PLAT_ARM_GICC_BASE BASE_GICC_BASE -#define PLAT_ARM_G1S_IRQS MT_IRQ_SEC_SGI_0, \ - MT_IRQ_SEC_SGI_1, \ - MT_IRQ_SEC_SGI_2, \ - MT_IRQ_SEC_SGI_3, \ - MT_IRQ_SEC_SGI_4, \ - MT_IRQ_SEC_SGI_5, \ - MT_IRQ_SEC_SGI_6, \ - MT_IRQ_SEC_SGI_7 - -#define PLAT_ARM_G0_IRQS +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/socionext/uniphier/uniphier_gicv3.c b/plat/socionext/uniphier/uniphier_gicv3.c index 05a4e35f2..93bc73ac2 100644 --- a/plat/socionext/uniphier/uniphier_gicv3.c +++ b/plat/socionext/uniphier/uniphier_gicv3.c @@ -6,6 +6,7 @@ #include <assert.h> #include <gicv3.h> +#include <interrupt_props.h> #include <platform.h> #include <platform_def.h> @@ -13,19 +14,39 @@ static uintptr_t uniphier_rdistif_base_addrs[PLATFORM_CORE_COUNT]; -static const unsigned int g0_interrupt_array[] = { - 8, /* SGI0 */ - 14, /* SGI6 */ -}; +static const interrupt_prop_t uniphier_interrupt_props[] = { + /* G0 interrupts */ + + /* SGI0 */ + INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, + GIC_INTR_CFG_EDGE), + /* SGI6 */ + INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, + GIC_INTR_CFG_EDGE), + + /* G1S interrupts */ -static const unsigned int g1s_interrupt_array[] = { - 29, /* Timer */ - 9, /* SGI1 */ - 10, /* SGI2 */ - 11, /* SGI3 */ - 12, /* SGI4 */ - 13, /* SGI5 */ - 15, /* SGI7 */ + /* Timer */ + INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, + GIC_INTR_CFG_LEVEL), + /* SGI1 */ + INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, + GIC_INTR_CFG_EDGE), + /* SGI2 */ + INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, + GIC_INTR_CFG_EDGE), + /* SGI3 */ + INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, + GIC_INTR_CFG_EDGE), + /* SGI4 */ + INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, + GIC_INTR_CFG_EDGE), + /* SGI5 */ + INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, + GIC_INTR_CFG_EDGE), + /* SGI7 */ + INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, + GIC_INTR_CFG_EDGE) }; static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr) @@ -37,10 +58,8 @@ static const struct gicv3_driver_data uniphier_gic_driver_data[] = { [UNIPHIER_SOC_LD11] = { .gicd_base = 0x5fe00000, .gicr_base = 0x5fe40000, - .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), - .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), - .g0_interrupt_array = g0_interrupt_array, - .g1s_interrupt_array = g1s_interrupt_array, + .interrupt_props = uniphier_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props), .rdistif_num = PLATFORM_CORE_COUNT, .rdistif_base_addrs = uniphier_rdistif_base_addrs, .mpidr_to_core_pos = uniphier_mpidr_to_core_pos, @@ -48,10 +67,8 @@ static const struct gicv3_driver_data uniphier_gic_driver_data[] = { [UNIPHIER_SOC_LD20] = { .gicd_base = 0x5fe00000, .gicr_base = 0x5fe80000, - .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), - .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), - .g0_interrupt_array = g0_interrupt_array, - .g1s_interrupt_array = g1s_interrupt_array, + .interrupt_props = uniphier_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props), .rdistif_num = PLATFORM_CORE_COUNT, .rdistif_base_addrs = uniphier_rdistif_base_addrs, .mpidr_to_core_pos = uniphier_mpidr_to_core_pos, @@ -59,10 +76,8 @@ static const struct gicv3_driver_data uniphier_gic_driver_data[] = { [UNIPHIER_SOC_PXS3] = { .gicd_base = 0x5fe00000, .gicr_base = 0x5fe80000, - .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), - .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), - .g0_interrupt_array = g0_interrupt_array, - .g1s_interrupt_array = g1s_interrupt_array, + .interrupt_props = uniphier_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props), .rdistif_num = PLATFORM_CORE_COUNT, .rdistif_base_addrs = uniphier_rdistif_base_addrs, .mpidr_to_core_pos = uniphier_mpidr_to_core_pos, diff --git a/plat/socionext/uniphier/uniphier_rotpk.S b/plat/socionext/uniphier/uniphier_rotpk.S index 0045a3495..21c44b621 100644 --- a/plat/socionext/uniphier/uniphier_rotpk.S +++ b/plat/socionext/uniphier/uniphier_rotpk.S @@ -6,6 +6,7 @@ .global uniphier_rotpk_hash .global uniphier_rotpk_hash_end + .section .rodata.uniphier_rotpk_hash, "a" uniphier_rotpk_hash: /* DER header */ .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index a09b5c629..5dd8d86ea 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,8 @@ #define __PLATFORM_DEF_H__ #include <arch.h> +#include <gic_common.h> +#include <interrupt_props.h> #include "../zynqmp_def.h" /******************************************************************************* @@ -85,20 +87,30 @@ #define PLAT_ARM_GICD_BASE BASE_GICD_BASE #define PLAT_ARM_GICC_BASE BASE_GICC_BASE /* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 * terminology. On a GICv2 system or mode, the lists will be merged and treated * as Group 0 interrupts. */ -#define PLAT_ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ - ARM_IRQ_SEC_SGI_0, \ - ARM_IRQ_SEC_SGI_1, \ - ARM_IRQ_SEC_SGI_2, \ - ARM_IRQ_SEC_SGI_3, \ - ARM_IRQ_SEC_SGI_4, \ - ARM_IRQ_SEC_SGI_5, \ - ARM_IRQ_SEC_SGI_6, \ - ARM_IRQ_SEC_SGI_7 +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE) -#define PLAT_ARM_G0_IRQS +#define PLAT_ARM_G0_IRQ_PROPS(grp) #endif /* __PLATFORM_DEF_H__ */ |