diff options
Diffstat (limited to 'plat')
78 files changed, 466 insertions, 233 deletions
diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk index 98bcf3e22..e60ebc6f2 100644 --- a/plat/allwinner/common/allwinner-common.mk +++ b/plat/allwinner/common/allwinner-common.mk @@ -20,6 +20,8 @@ PLAT_BL_COMMON_SOURCES := drivers/ti/uart/${ARCH}/16550_console.S \ ${AW_PLAT}/common/sunxi_common.c BL31_SOURCES += drivers/allwinner/axp/common.c \ + drivers/allwinner/sunxi_msgbox.c \ + drivers/arm/css/scpi/css_scpi.c \ drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_helpers.c \ drivers/arm/gic/v2/gicv2_main.c \ diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h index 32a7c0408..975cc48d5 100644 --- a/plat/allwinner/common/include/platform_def.h +++ b/plat/allwinner/common/include/platform_def.h @@ -13,8 +13,13 @@ #include <sunxi_mmap.h> -#define BL31_BASE SUNXI_SRAM_A2_BASE -#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE) +#define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000) +#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \ + SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE) + +/* The SCP firmware is allocated the last 16KiB of SRAM A2. */ +#define SUNXI_SCP_BASE BL31_LIMIT +#define SUNXI_SCP_SIZE 0x4000 /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ #define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) @@ -35,6 +40,9 @@ #define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) #define MAX_XLAT_TABLES 1 +#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \ + (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200) + #define PLAT_MAX_PWR_LVL_STATES U(2) #define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_OFF_STATE U(2) @@ -51,7 +59,7 @@ #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_MAX_CPUS_PER_CLUSTER) #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) -#define PLATFORM_MMAP_REGIONS 4 +#define PLATFORM_MMAP_REGIONS 5 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) #ifndef SPD_none diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c index a24527c5d..e836a345b 100644 --- a/plat/allwinner/common/sunxi_bl31_setup.c +++ b/plat/allwinner/common/sunxi_bl31_setup.c @@ -28,7 +28,7 @@ static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; -static console_16550_t console; +static console_t console; static const gicv2_driver_data_t sunxi_gic_data = { .gicd_base = SUNXI_GICD_BASE, diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c index 3759c285e..0ca18adc3 100644 --- a/plat/allwinner/common/sunxi_common.c +++ b/plat/allwinner/common/sunxi_common.c @@ -21,6 +21,8 @@ static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, MT_RW_DATA | MT_SECURE), + MAP_REGION_FLAT(SUNXI_SCP_BASE, SUNXI_SCP_SIZE, + MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, @@ -175,7 +177,7 @@ DEFINE_BAKERY_LOCK(arisc_lock); */ void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param) { - uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE - 0x4000 + 0x100; + uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE + 0x100; do { bakery_lock_get(&arisc_lock); diff --git a/plat/allwinner/common/sunxi_pm.c b/plat/allwinner/common/sunxi_pm.c index 9b074d2ac..e0fa5b3ec 100644 --- a/plat/allwinner/common/sunxi_pm.c +++ b/plat/allwinner/common/sunxi_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include <arch_helpers.h> #include <common/debug.h> +#include <drivers/arm/css/css_scpi.h> #include <drivers/arm/gicv2.h> #include <drivers/delay_timer.h> #include <lib/mmio.h> @@ -17,6 +18,7 @@ #include <plat/common/platform.h> #include <sunxi_cpucfg.h> +#include <sunxi_def.h> #include <sunxi_mmap.h> #include <sunxi_private.h> @@ -24,25 +26,88 @@ #define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014) #define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018) -#define mpidr_is_valid(mpidr) ( \ - MPIDR_AFFLVL3_VAL(mpidr) == 0 && \ - MPIDR_AFFLVL2_VAL(mpidr) == 0 && \ - MPIDR_AFFLVL1_VAL(mpidr) < PLATFORM_CLUSTER_COUNT && \ - MPIDR_AFFLVL0_VAL(mpidr) < PLATFORM_MAX_CPUS_PER_CLUSTER) +#define CPU_PWR_LVL MPIDR_AFFLVL0 +#define CLUSTER_PWR_LVL MPIDR_AFFLVL1 +#define SYSTEM_PWR_LVL MPIDR_AFFLVL2 + +#define CPU_PWR_STATE(state) \ + ((state)->pwr_domain_state[CPU_PWR_LVL]) +#define CLUSTER_PWR_STATE(state) \ + ((state)->pwr_domain_state[CLUSTER_PWR_LVL]) +#define SYSTEM_PWR_STATE(state) \ + ((state)->pwr_domain_state[SYSTEM_PWR_LVL]) + +#define mpidr_is_valid(mpidr) (plat_core_pos_by_mpidr(mpidr) >= 0) + +/* + * The addresses for the SCP exception vectors are defined in the or1k + * architecture specification. + */ +#define OR1K_VEC_FIRST 0x01 +#define OR1K_VEC_LAST 0x0e +#define OR1K_VEC_ADDR(n) (0x100 * (n)) + +/* + * This magic value is the little-endian representation of the or1k + * instruction "l.mfspr r2, r0, 0x12", which is guaranteed to be the + * first instruction in the SCP firmware. + */ +#define SCP_FIRMWARE_MAGIC 0xb4400012 + +static bool scpi_available; + +static inline scpi_power_state_t scpi_map_state(plat_local_state_t psci_state) +{ + if (is_local_state_run(psci_state)) + return scpi_power_on; + if (is_local_state_retn(psci_state)) + return scpi_power_retention; + return scpi_power_off; +} + +static void sunxi_cpu_standby(plat_local_state_t cpu_state) +{ + u_register_t scr = read_scr_el3(); + + assert(is_local_state_retn(cpu_state)); + + write_scr_el3(scr | SCR_IRQ_BIT); + wfi(); + write_scr_el3(scr); +} static int sunxi_pwr_domain_on(u_register_t mpidr) { if (mpidr_is_valid(mpidr) == 0) return PSCI_E_INTERN_FAIL; - sunxi_cpu_on(mpidr); + if (scpi_available) { + scpi_set_css_power_state(mpidr, + scpi_power_on, + scpi_power_on, + scpi_power_on); + } else { + sunxi_cpu_on(mpidr); + } return PSCI_E_SUCCESS; } static void sunxi_pwr_domain_off(const psci_power_state_t *target_state) { - gicv2_cpuif_disable(); + plat_local_state_t cpu_pwr_state = CPU_PWR_STATE(target_state); + plat_local_state_t cluster_pwr_state = CLUSTER_PWR_STATE(target_state); + plat_local_state_t system_pwr_state = SYSTEM_PWR_STATE(target_state); + + if (is_local_state_off(cpu_pwr_state)) + gicv2_cpuif_disable(); + + if (scpi_available) { + scpi_set_css_power_state(read_mpidr(), + scpi_map_state(cpu_pwr_state), + scpi_map_state(cluster_pwr_state), + scpi_map_state(system_pwr_state)); + } } static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state) @@ -55,12 +120,26 @@ static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state) static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state) { - gicv2_pcpu_distif_init(); - gicv2_cpuif_enable(); + if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) + gicv2_distif_init(); + if (is_local_state_off(CPU_PWR_STATE(target_state))) { + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); + } } static void __dead2 sunxi_system_off(void) { + gicv2_cpuif_disable(); + + if (scpi_available) { + /* Send the power down request to the SCP */ + uint32_t ret = scpi_sys_power_state(scpi_system_shutdown); + + if (ret != SCP_OK) + ERROR("PSCI: SCPI %s failed: %d\n", "shutdown", ret); + } + /* Turn off all secondary CPUs */ sunxi_disable_secondary_cpus(read_mpidr()); @@ -74,6 +153,16 @@ static void __dead2 sunxi_system_off(void) static void __dead2 sunxi_system_reset(void) { + gicv2_cpuif_disable(); + + if (scpi_available) { + /* Send the system reset request to the SCP */ + uint32_t ret = scpi_sys_power_state(scpi_system_reboot); + + if (ret != SCP_OK) + ERROR("PSCI: SCPI %s failed: %d\n", "reboot", ret); + } + /* Reset the whole system when the watchdog times out */ mmio_write_32(SUNXI_WDOG0_CFG_REG, 1); /* Enable the watchdog with the shortest timeout (0.5 seconds) */ @@ -86,6 +175,40 @@ static void __dead2 sunxi_system_reset(void) panic(); } +static int sunxi_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int power_level = psci_get_pstate_pwrlvl(power_state); + unsigned int type = psci_get_pstate_type(power_state); + + assert(req_state != NULL); + + if (power_level > PLAT_MAX_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + if (type == PSTATE_TYPE_STANDBY) { + /* Only one retention power state is supported. */ + if (psci_get_pstate_id(power_state) > 0) + return PSCI_E_INVALID_PARAMS; + /* The SoC cannot be suspended without losing state */ + if (power_level == SYSTEM_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + for (unsigned int i = 0; i <= power_level; ++i) + req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; + } else { + /* Only one off power state is supported. */ + if (psci_get_pstate_id(power_state) > 0) + return PSCI_E_INVALID_PARAMS; + for (unsigned int i = 0; i <= power_level; ++i) + req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; + } + /* Higher power domain levels should all remain running */ + for (unsigned int i = power_level + 1; i <= PLAT_MAX_PWR_LVL; ++i) + req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN; + + return PSCI_E_SUCCESS; +} + static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint) { /* The non-secure entry point must be in DRAM */ @@ -95,13 +218,45 @@ static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint) return PSCI_E_INVALID_ADDRESS; } +static void sunxi_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + assert(req_state); + + for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i) + req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; +} + +static int sunxi_get_node_hw_state(u_register_t mpidr, + unsigned int power_level) +{ + unsigned int cluster_state, cpu_state; + unsigned int cpu = MPIDR_AFFLVL0_VAL(mpidr); + + /* SoC power level (always on if PSCI works). */ + if (power_level == SYSTEM_PWR_LVL) + return HW_ON; + if (scpi_get_css_power_state(mpidr, &cpu_state, &cluster_state)) + return PSCI_E_NOT_SUPPORTED; + /* Cluster power level (full power state available). */ + if (power_level == CLUSTER_PWR_LVL) { + if (cluster_state == scpi_power_on) + return HW_ON; + if (cluster_state == scpi_power_retention) + return HW_STANDBY; + return HW_OFF; + } + /* CPU power level (one bit boolean for on or off). */ + return ((cpu_state & BIT(cpu)) != 0) ? HW_ON : HW_OFF; +} + static plat_psci_ops_t sunxi_psci_ops = { + .cpu_standby = sunxi_cpu_standby, .pwr_domain_on = sunxi_pwr_domain_on, .pwr_domain_off = sunxi_pwr_domain_off, - .pwr_domain_pwr_down_wfi = sunxi_pwr_down_wfi, .pwr_domain_on_finish = sunxi_pwr_domain_on_finish, .system_off = sunxi_system_off, .system_reset = sunxi_system_reset, + .validate_power_state = sunxi_validate_power_state, .validate_ns_entrypoint = sunxi_validate_ns_entrypoint, }; @@ -110,13 +265,44 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, { assert(psci_ops); - for (int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) { + /* Program all CPU entry points. */ + for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; ++cpu) { mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu), sec_entrypoint & 0xffffffff); mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu), sec_entrypoint >> 32); } + /* Check for a valid SCP firmware, and boot the SCP if found. */ + if (mmio_read_32(SUNXI_SCP_BASE) == SCP_FIRMWARE_MAGIC) { + /* Program SCP exception vectors to the firmware entrypoint. */ + for (unsigned int i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) { + uint32_t vector = SUNXI_SRAM_A2_BASE + OR1K_VEC_ADDR(i); + uint32_t offset = SUNXI_SCP_BASE - vector; + + mmio_write_32(vector, offset >> 2); + clean_dcache_range(vector, sizeof(uint32_t)); + } + /* Take the SCP out of reset. */ + mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); + /* Wait for the SCP firmware to boot. */ + if (scpi_wait_ready() == 0) + scpi_available = true; + } + + NOTICE("PSCI: System suspend is %s\n", + scpi_available ? "available via SCPI" : "unavailable"); + if (scpi_available) { + /* Suspend is only available via SCPI. */ + sunxi_psci_ops.pwr_domain_suspend = sunxi_pwr_domain_off; + sunxi_psci_ops.pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish; + sunxi_psci_ops.get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state; + sunxi_psci_ops.get_node_hw_state = sunxi_get_node_hw_state; + } else { + /* This is only needed when SCPI is unavailable. */ + sunxi_psci_ops.pwr_domain_pwr_down_wfi = sunxi_pwr_down_wfi; + } + *psci_ops = &sunxi_psci_ops; return 0; diff --git a/plat/allwinner/sun50i_a64/include/sunxi_mmap.h b/plat/allwinner/sun50i_a64/include/sunxi_mmap.h index db4409118..9d2542fce 100644 --- a/plat/allwinner/sun50i_a64/include/sunxi_mmap.h +++ b/plat/allwinner/sun50i_a64/include/sunxi_mmap.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,8 +14,8 @@ #define SUNXI_SRAM_SIZE 0x00044000 #define SUNXI_SRAM_A1_BASE 0x00010000 #define SUNXI_SRAM_A1_SIZE 0x00008000 -#define SUNXI_SRAM_A2_BASE 0x00044000 -#define SUNXI_SRAM_A2_SIZE 0x00010000 +#define SUNXI_SRAM_A2_BASE 0x00040000 +#define SUNXI_SRAM_A2_SIZE 0x00014000 #define SUNXI_SRAM_C_BASE 0x00018000 #define SUNXI_SRAM_C_SIZE 0x0001c000 #define SUNXI_DEV_BASE 0x01000000 diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h index f36491a8a..0e204d0f0 100644 --- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h +++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,8 +14,8 @@ #define SUNXI_SRAM_SIZE 0x000f8000 #define SUNXI_SRAM_A1_BASE 0x00020000 #define SUNXI_SRAM_A1_SIZE 0x00008000 -#define SUNXI_SRAM_A2_BASE 0x00104000 -#define SUNXI_SRAM_A2_SIZE 0x00014000 +#define SUNXI_SRAM_A2_BASE 0x00100000 +#define SUNXI_SRAM_A2_SIZE 0x00018000 #define SUNXI_SRAM_C_BASE 0x00028000 #define SUNXI_SRAM_C_SIZE 0x0001e000 #define SUNXI_DEV_BASE 0x01000000 diff --git a/plat/amlogic/common/aml_console.c b/plat/amlogic/common/aml_console.c index 352279b6c..e21d707a0 100644 --- a/plat/amlogic/common/aml_console.c +++ b/plat/amlogic/common/aml_console.c @@ -11,7 +11,7 @@ /******************************************************************************* * Function that sets up the console ******************************************************************************/ -static console_meson_t aml_console; +static console_t aml_console; void aml_console_init(void) { @@ -28,6 +28,6 @@ void aml_console_init(void) panic(); } - console_set_scope(&aml_console.console, + console_set_scope(&aml_console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); } diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h index 347ba2e1e..909b68717 100644 --- a/plat/arm/board/fvp/fvp_def.h +++ b/plat/arm/board/fvp/fvp_def.h @@ -52,8 +52,10 @@ #define DEVICE1_BASE UL(0x2e000000) #define DEVICE1_SIZE UL(0x1A00000) #else -#define DEVICE1_BASE UL(0x2f000000) -#define DEVICE1_SIZE UL(0x200000) +/* GICv2 and GICv3 mapping: GICD + CORE_COUNT * 128KB */ +#define DEVICE1_BASE BASE_GICD_BASE +#define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \ + (PLATFORM_CORE_COUNT * 0x20000)) #define NSRAM_BASE UL(0x2e000000) #define NSRAM_SIZE UL(0x10000) #endif @@ -110,7 +112,7 @@ #define FVP_SP810_CTRL_TIM3_OV BIT_32(22) /******************************************************************************* - * GIC-400 & interrupt handling related constants + * GIC & interrupt handling related constants ******************************************************************************/ /* VE compatible GIC memory map */ #define VE_GICD_BASE UL(0x2c001000) @@ -128,7 +130,6 @@ #define FVP_IRQ_TZ_WDOG 56 #define FVP_IRQ_SEC_SYS_TIMER 57 - /******************************************************************************* * TrustZone address space controller related constants ******************************************************************************/ diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 4176968f8..05c11ce52 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -292,7 +292,7 @@ ifeq (${ARCH},aarch32) ifeq (${RESET_TO_SP_MIN},1) BL32_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 endif -else # if AArch64 +else # AArch64 ifeq (${RESET_TO_BL31},1) BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 endif @@ -301,6 +301,17 @@ else # if AArch64 endif endif +ifeq (${ALLOW_RO_XLAT_TABLES}, 1) + ifeq (${ARCH},aarch32) + BL32_CFLAGS += -DPLAT_RO_XLAT_TABLES=1 + else # AArch64 + BL31_CFLAGS += -DPLAT_RO_XLAT_TABLES=1 + ifeq (${SPD},tspd) + BL32_CFLAGS += -DPLAT_RO_XLAT_TABLES=1 + endif + endif +endif + ifeq (${USE_DEBUGFS},1) BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 endif diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index 27650d266..f07c1b163 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk @@ -155,6 +155,14 @@ else endif endif +ifeq (${ALLOW_RO_XLAT_TABLES}, 1) + ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) + BL32_CFLAGS += -DPLAT_RO_XLAT_TABLES=1 + else + BL31_CFLAGS += -DPLAT_RO_XLAT_TABLES=1 + endif +endif + # Add the FDT_SOURCES and options for Dynamic Config FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index c135d7f2d..85535c11a 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -256,9 +256,14 @@ void arm_bl31_plat_runtime_setup(void) /* Initialize the runtime console */ arm_console_runtime_init(); + #if RECLAIM_INIT_CODE arm_free_init_memory(); #endif + +#if PLAT_RO_XLAT_TABLES + arm_xlat_make_tables_readonly(); +#endif } #if RECLAIM_INIT_CODE diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index d1e9620de..d1eee08d1 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -25,6 +25,26 @@ * conflicts with the definition in plat/common. */ #pragma weak plat_get_syscnt_freq2 +/******************************************************************************* + * Changes the memory attributes for the region of mapped memory where the BL + * image's translation tables are located such that the tables will have + * read-only permissions. + ******************************************************************************/ +#if PLAT_RO_XLAT_TABLES +void arm_xlat_make_tables_readonly(void) +{ + int rc = xlat_make_tables_readonly(); + + if (rc != 0) { + ERROR("Failed to make translation tables read-only at EL%u.\n", + get_current_el()); + panic(); + } + + INFO("Translation tables are now read-only at EL%u.\n", + get_current_el()); +} +#endif void arm_setup_romlib(void) { diff --git a/plat/arm/common/arm_console.c b/plat/arm/common/arm_console.c index 123811d71..0cac5d999 100644 --- a/plat/arm/common/arm_console.c +++ b/plat/arm/common/arm_console.c @@ -16,8 +16,8 @@ /******************************************************************************* * Functions that set up the console ******************************************************************************/ -static console_pl011_t arm_boot_console; -static console_pl011_t arm_runtime_console; +static console_t arm_boot_console; +static console_t arm_runtime_console; /* Initialize the console to provide early debug support */ void __init arm_console_boot_init(void) @@ -35,13 +35,13 @@ void __init arm_console_boot_init(void) panic(); } - console_set_scope(&arm_boot_console.console, CONSOLE_FLAG_BOOT); + console_set_scope(&arm_boot_console, CONSOLE_FLAG_BOOT); } void arm_console_boot_end(void) { (void)console_flush(); - (void)console_unregister(&arm_boot_console.console); + (void)console_unregister(&arm_boot_console); } /* Initialize the runtime console */ @@ -54,7 +54,7 @@ void arm_console_runtime_init(void) if (rc == 0) panic(); - console_set_scope(&arm_runtime_console.console, CONSOLE_FLAG_RUNTIME); + console_set_scope(&arm_runtime_console, CONSOLE_FLAG_RUNTIME); } void arm_console_runtime_end(void) diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c index 443d40fe8..df7530733 100644 --- a/plat/arm/common/arm_dyn_cfg.c +++ b/plat/arm/common/arm_dyn_cfg.c @@ -21,7 +21,6 @@ #include <lib/fconf/fconf_tbbr_getter.h> #include <plat/arm/common/arm_dyn_cfg_helpers.h> #include <plat/arm/common/plat_arm.h> -#include <plat/common/platform.h> #if TRUSTED_BOARD_BOOT diff --git a/plat/arm/common/arm_fconf_io_storage.c b/plat/arm/common/arm_fconf_io_storage.c index 341622a0b..6fcfbd6fb 100644 --- a/plat/arm/common/arm_fconf_io_storage.c +++ b/plat/arm/common/arm_fconf_io_storage.c @@ -12,7 +12,6 @@ #include <drivers/io/io_memmap.h> #include <drivers/io/io_storage.h> #include <lib/utils.h> -#include <tools_share/firmware_image_package.h> #include <plat/arm/common/arm_fconf_getter.h> #include <plat/arm/common/arm_fconf_io_storage.h> diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c index 3c0586fd0..cfcddc2b2 100644 --- a/plat/arm/common/fconf/arm_fconf_io.c +++ b/plat/arm/common/fconf/arm_fconf_io.c @@ -59,9 +59,9 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { #ifdef IMAGE_BL2 #if TRUSTED_BOARD_BOOT -#define FCONF_ARM_IO_UUID_NUMBER 19 +#define FCONF_ARM_IO_UUID_NUMBER U(19) #else -#define FCONF_ARM_IO_UUID_NUMBER 10 +#define FCONF_ARM_IO_UUID_NUMBER U(10) #endif static io_uuid_spec_t fconf_arm_uuids[FCONF_ARM_IO_UUID_NUMBER]; diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c index 0cc746b10..cbbdfa21b 100644 --- a/plat/arm/common/sp_min/arm_sp_min_setup.c +++ b/plat/arm/common/sp_min/arm_sp_min_setup.c @@ -167,6 +167,10 @@ void arm_sp_min_plat_runtime_setup(void) { /* Initialize the runtime console */ arm_console_runtime_init(); + +#if PLAT_RO_XLAT_TABLES + arm_xlat_make_tables_readonly(); +#endif } /******************************************************************************* diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c index aefdf89c7..a4da8c35e 100644 --- a/plat/arm/common/tsp/arm_tsp_setup.c +++ b/plat/arm/common/tsp/arm_tsp_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,7 +28,7 @@ /******************************************************************************* * Initialize the UART ******************************************************************************/ -static console_pl011_t arm_tsp_runtime_console; +static console_t arm_tsp_runtime_console; void arm_tsp_early_platform_setup(void) { @@ -43,7 +43,7 @@ void arm_tsp_early_platform_setup(void) if (rc == 0) panic(); - console_set_scope(&arm_tsp_runtime_console.console, + console_set_scope(&arm_tsp_runtime_console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); } @@ -79,4 +79,8 @@ void tsp_plat_arch_setup(void) setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_el1(0); + +#if PLAT_RO_XLAT_TABLES + arm_xlat_make_tables_readonly(); +#endif } diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c index a97d76320..86e4fd637 100644 --- a/plat/hisilicon/hikey/hikey_bl1_setup.c +++ b/plat/hisilicon/hikey/hikey_bl1_setup.c @@ -26,7 +26,7 @@ /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; -static console_pl011_t console; +static console_t console; enum { BOOT_NORMAL = 0, diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c index 96136ec12..feb7f8a46 100644 --- a/plat/hisilicon/hikey/hikey_bl2_setup.c +++ b/plat/hisilicon/hikey/hikey_bl2_setup.c @@ -32,7 +32,7 @@ #define BL2_RW_BASE (BL_CODE_END) static meminfo_t bl2_el3_tzram_layout; -static console_pl011_t console; +static console_t console; enum { BOOT_MODE_RECOVERY = 0, diff --git a/plat/hisilicon/hikey/hikey_bl31_setup.c b/plat/hisilicon/hikey/hikey_bl31_setup.c index 0326e9f3d..7d008e741 100644 --- a/plat/hisilicon/hikey/hikey_bl31_setup.c +++ b/plat/hisilicon/hikey/hikey_bl31_setup.c @@ -27,7 +27,7 @@ static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; -static console_pl011_t console; +static console_t console; /****************************************************************************** * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 diff --git a/plat/hisilicon/hikey960/hikey960_bl1_setup.c b/plat/hisilicon/hikey960/hikey960_bl1_setup.c index 4a7036cfc..0a2d062a5 100644 --- a/plat/hisilicon/hikey960/hikey960_bl1_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl1_setup.c @@ -41,7 +41,7 @@ enum { /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; -static console_pl011_t console; +static console_t console; /****************************************************************************** * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c index 35d76921d..c1c2a8c59 100644 --- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c @@ -32,7 +32,7 @@ #define BL2_RW_BASE (BL_CODE_END) static meminfo_t bl2_el3_tzram_layout; -static console_pl011_t console; +static console_t console; extern int load_lpm3(void); enum { diff --git a/plat/hisilicon/hikey960/hikey960_bl31_setup.c b/plat/hisilicon/hikey960/hikey960_bl31_setup.c index 9383265ec..d3b4e4f68 100644 --- a/plat/hisilicon/hikey960/hikey960_bl31_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl31_setup.c @@ -29,7 +29,7 @@ static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; -static console_pl011_t console; +static console_t console; /****************************************************************************** * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 diff --git a/plat/hisilicon/hikey960/hikey960_pm.c b/plat/hisilicon/hikey960/hikey960_pm.c index ede893ecb..9f96fc398 100644 --- a/plat/hisilicon/hikey960/hikey960_pm.c +++ b/plat/hisilicon/hikey960/hikey960_pm.c @@ -33,7 +33,7 @@ #define AXI_CONF_BASE 0x820 static unsigned int uart_base; -static console_pl011_t console; +static console_t console; static uintptr_t hikey960_sec_entrypoint; static void hikey960_pwr_domain_standby(plat_local_state_t cpu_state) diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c index 08ad67c59..047ba6291 100644 --- a/plat/hisilicon/poplar/bl1_plat_setup.c +++ b/plat/hisilicon/poplar/bl1_plat_setup.c @@ -28,7 +28,7 @@ /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; static meminfo_t bl2_tzram_layout; -static console_pl011_t console; +static console_t console; /* * Cannot use default weak implementation in bl1_main.c because BL1 RW data is diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c index cc9d9754e..482935c4a 100644 --- a/plat/hisilicon/poplar/bl2_plat_setup.c +++ b/plat/hisilicon/poplar/bl2_plat_setup.c @@ -25,7 +25,7 @@ #include "plat_private.h" static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); -static console_pl011_t console; +static console_t console; /******************************************************************************* * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. diff --git a/plat/hisilicon/poplar/bl31_plat_setup.c b/plat/hisilicon/poplar/bl31_plat_setup.c index 981ef376b..a4e17cabc 100644 --- a/plat/hisilicon/poplar/bl31_plat_setup.c +++ b/plat/hisilicon/poplar/bl31_plat_setup.c @@ -29,7 +29,7 @@ static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; -static console_pl011_t console; +static console_t console; static void hisi_tzpc_sec_init(void) { diff --git a/plat/imx/common/include/imx8_lpuart.h b/plat/imx/common/include/imx8_lpuart.h index 0ea284fdf..26470e040 100644 --- a/plat/imx/common/include/imx8_lpuart.h +++ b/plat/imx/common/include/imx8_lpuart.h @@ -54,13 +54,8 @@ #include <stdint.h> -typedef struct { - console_t console; - uintptr_t base; -} console_lpuart_t; - int console_lpuart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_lpuart_t *console); + console_t *console); #endif /*__ASSEMBLER__*/ #endif /* IMX8_LPUART_H */ diff --git a/plat/imx/common/include/imx_uart.h b/plat/imx/common/include/imx_uart.h index cc1b5318e..6c4d62f57 100644 --- a/plat/imx/common/include/imx_uart.h +++ b/plat/imx/common/include/imx_uart.h @@ -11,13 +11,8 @@ #ifndef __ASSEMBLER__ -typedef struct { - console_t console; - uintptr_t base; -} console_uart_t; - int console_imx_uart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_uart_t *console); + console_t *console); #endif /*__ASSEMBLER__*/ #endif /* IMX_UART_H */ diff --git a/plat/imx/imx7/common/imx7_bl2_el3_common.c b/plat/imx/imx7/common/imx7_bl2_el3_common.c index a1e2aafd4..7f156e306 100644 --- a/plat/imx/imx7/common/imx7_bl2_el3_common.c +++ b/plat/imx/imx7/common/imx7_bl2_el3_common.c @@ -150,7 +150,7 @@ static void imx7_setup_wdog_clocks(void) void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, u_register_t arg3, u_register_t arg4) { - static console_imx_uart_t console; + static console_t console; int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME; /* Initialize common components */ @@ -170,7 +170,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, PLAT_IMX7_BOOT_UART_CLK_IN_HZ, PLAT_IMX7_CONSOLE_BAUDRATE, &console); - console_set_scope(&console.console, console_scope); + console_set_scope(&console, console_scope); /* Open handles to persistent storage */ plat_imx7_io_setup(); diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c index 4c5f4f0d1..40110d778 100644 --- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c @@ -97,7 +97,7 @@ void bl31_tzc380_setup(void) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - static console_uart_t console; + static console_t console; int i; /* Enable CSU NS access permission */ @@ -114,7 +114,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE, &console); /* This console is only used for boot stage */ - console_set_scope(&console.console, CONSOLE_FLAG_BOOT); + console_set_scope(&console, CONSOLE_FLAG_BOOT); /* * tell BL3-1 where the non-secure software image is located diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c index a347389a2..05b59705f 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c @@ -133,7 +133,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, imx8m_caam_init(); #if DEBUG_CONSOLE - static console_uart_t console; + static console_t console; console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE, &console); diff --git a/plat/imx/imx8m/include/imx_rdc.h b/plat/imx/imx8m/include/imx_rdc.h index 6be8550da..e25b0e6d4 100644 --- a/plat/imx/imx8m/include/imx_rdc.h +++ b/plat/imx/imx8m/include/imx_rdc.h @@ -13,9 +13,9 @@ #define MDAn(x) (IMX_RDC_BASE + 0x200 + (x) * 4) #define PDAPn(x) (IMX_RDC_BASE + 0x400 + (x) * 4) -#define MRSAn(x) (IMX_RDC_BASE + 0x800 + (x) * 4) -#define MREAn(x) (IMX_RDC_BASE + 0x804 + (x) * 4) -#define MRCn(x) (IMX_RDC_BASE + 0x808 + (x) * 4) +#define MRSAn(x) (IMX_RDC_BASE + 0x800 + (x) * 0x10) +#define MREAn(x) (IMX_RDC_BASE + 0x804 + (x) * 0x10) +#define MRCn(x) (IMX_RDC_BASE + 0x808 + (x) * 0x10) #define LCK BIT(31) #define SREQ BIT(30) diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c index 9232cbc2d..cffb140fb 100644 --- a/plat/imx/imx8qm/imx8qm_bl31_setup.c +++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c @@ -295,7 +295,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { #if DEBUG_CONSOLE - static console_lpuart_t console; + static console_t console; #endif if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE) panic(); diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c index 58c82ce60..97d222787 100644 --- a/plat/imx/imx8qx/imx8qx_bl31_setup.c +++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c @@ -255,7 +255,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { #if DEBUG_CONSOLE - static console_lpuart_t console; + static console_t console; #endif if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE) panic(); diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index f32820777..468b356b5 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -51,7 +51,7 @@ boot_source_type boot_source = BOOT_SOURCE; void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, u_register_t x2, u_register_t x4) { - static console_16550_t console; + static console_t console; handoff reverse_handoff_ptr; generic_delay_timer_init(); diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c index 4b1144095..6f32aff4a 100644 --- a/plat/intel/soc/agilex/bl31_plat_setup.c +++ b/plat/intel/soc/agilex/bl31_plat_setup.c @@ -37,7 +37,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - static console_16550_t console; + static console_t console; console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, &console); diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 7d725b0ad..3c56d15bf 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -126,9 +126,9 @@ int mailbox_init(void); void mailbox_set_qspi_close(void); void mailbox_set_qspi_open(void); void mailbox_set_qspi_direct(void); -int mailbox_send_cmd(int job_id, unsigned int cmd, uint64_t *args, +int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent, uint32_t *response, int resp_len); -int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint64_t *args, +int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent); int mailbox_read_response(int job_id, uint32_t *response, int resp_len); int mailbox_get_qspi_clock(void); @@ -140,7 +140,7 @@ int intel_mailbox_is_fpga_not_ready(void); int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len); int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len); -int mailbox_rsu_update(uint64_t *flash_offset); -int mailbox_hps_stage_notify(uint64_t execution_stage); +int mailbox_rsu_update(uint32_t *flash_offset); +int mailbox_hps_stage_notify(uint32_t execution_stage); #endif /* SOCFPGA_MBOX_H */ diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index 2b1d9837c..19a52f7b9 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -10,9 +10,11 @@ /* SiP status response */ #define INTEL_SIP_SMC_STATUS_OK 0 -#define INTEL_SIP_SMC_STATUS_ERROR 0x4 #define INTEL_SIP_SMC_STATUS_BUSY 0x1 #define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 +#define INTEL_SIP_SMC_RSU_ERROR 0x7 + /* SMC SiP service function identifier */ #define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 8ce40a742..d066f27b5 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -11,7 +11,7 @@ #include "socfpga_mailbox.h" #include "socfpga_sip_svc.h" -static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint64_t *args, +static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, int len) { uint32_t cmd_free_offset; @@ -167,7 +167,7 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response, } } -int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint64_t *args, +int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent) { if (urgent) @@ -184,7 +184,7 @@ int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint64_t *args, return 0; } -int mailbox_send_cmd(int job_id, unsigned int cmd, uint64_t *args, +int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent, uint32_t *response, int resp_len) { int status = 0; @@ -252,7 +252,7 @@ int mailbox_get_qspi_clock(void) void mailbox_qspi_set_cs(int device_select) { - uint64_t cs_setting = device_select; + uint32_t cs_setting = device_select; /* QSPI device select settings at 31:28 */ cs_setting = (cs_setting << 28); @@ -304,13 +304,13 @@ int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len) return ret; } -int mailbox_rsu_update(uint64_t *flash_offset) +int mailbox_rsu_update(uint32_t *flash_offset) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_UPDATE, flash_offset, 2, 0, NULL, 0); } -int mailbox_hps_stage_notify(uint64_t execution_stage) +int mailbox_hps_stage_notify(uint32_t execution_stage) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HPS_STAGE_NOTIFY, &execution_stage, 1, 0, NULL, 0); diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c index d48fb5dd0..4b57b8f31 100644 --- a/plat/intel/soc/common/socfpga_psci.c +++ b/plat/intel/soc/common/socfpga_psci.c @@ -134,8 +134,13 @@ extern uint64_t intel_rsu_update_address; static void __dead2 socfpga_system_reset(void) { + uint32_t addr_buf[2]; + + memcpy(addr_buf, &intel_rsu_update_address, + sizeof(intel_rsu_update_address)); + if (intel_rsu_update_address) - mailbox_rsu_update(&intel_rsu_update_address); + mailbox_rsu_update(addr_buf); else mailbox_reset_cold(); diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 1c3d45bee..a20baab4c 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -61,7 +61,7 @@ struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) { - uint64_t args[3]; + uint32_t args[3]; while (max_blocks > 0 && buffer->size > buffer->size_written) { args[0] = (1<<8); @@ -374,7 +374,7 @@ uint64_t intel_rsu_update_address; static uint32_t intel_rsu_status(uint64_t *respbuf, uint32_t respbuf_sz) { if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) - return INTEL_SIP_SMC_STATUS_ERROR; + return INTEL_SIP_SMC_RSU_ERROR; return INTEL_SIP_SMC_STATUS_OK; } @@ -385,10 +385,10 @@ static uint32_t intel_rsu_update(uint64_t update_address) return INTEL_SIP_SMC_STATUS_OK; } -static uint32_t intel_rsu_notify(uint64_t execution_stage) +static uint32_t intel_rsu_notify(uint32_t execution_stage) { if (mailbox_hps_stage_notify(execution_stage) < 0) - return INTEL_SIP_SMC_STATUS_ERROR; + return INTEL_SIP_SMC_RSU_ERROR; return INTEL_SIP_SMC_STATUS_OK; } @@ -397,14 +397,14 @@ static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, uint32_t *ret_stat) { if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) - return INTEL_SIP_SMC_STATUS_ERROR; + return INTEL_SIP_SMC_RSU_ERROR; *ret_stat = respbuf[8]; return INTEL_SIP_SMC_STATUS_OK; } /* Mailbox services */ -static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint64_t *args, int len, +static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, int len, int urgent, uint32_t *response, int resp_len, int *mbox_status, int *len_in_resp) @@ -542,7 +542,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, case INTEL_SIP_SMC_MBOX_SEND_CMD: x5 = SMC_GET_GP(handle, CTX_GPREG_X5); x6 = SMC_GET_GP(handle, CTX_GPREG_X6); - status = intel_mbox_send_cmd(x1, (uint64_t *)x2, x3, x4, + status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, (uint32_t *)x5, x6, &mbox_status, &len_in_resp); SMC_RET4(handle, status, mbox_status, x5, len_in_resp); diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 78ca253e7..d0c8e4c7b 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -50,7 +50,7 @@ boot_source_type boot_source = BOOT_SOURCE; void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, u_register_t x2, u_register_t x4) { - static console_16550_t console; + static console_t console; handoff reverse_handoff_ptr; generic_delay_timer_init(); diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 4c3123815..5813c8f8c 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -45,7 +45,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - static console_16550_t console; + static console_t console; console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, &console); diff --git a/plat/layerscape/common/aarch64/ls_console.S b/plat/layerscape/common/aarch64/ls_console.S index f8948b4ab..c1bd3f731 100644 --- a/plat/layerscape/common/aarch64/ls_console.S +++ b/plat/layerscape/common/aarch64/ls_console.S @@ -81,7 +81,7 @@ endfunc console_ls_16550_core_init .globl console_ls_16550_register /* ----------------------------------------------- - * int console_ls_16550_register(console_ls_16550_t *console, + * int console_ls_16550_register(console_t *console, * uintptr_t base, uint32_t clk, uint32_t baud) * Function to initialize and register a new 16550 * console. Storage passed in for the console struct @@ -89,7 +89,7 @@ endfunc console_ls_16550_core_init * In: x0 - UART register base address * w1 - UART clock in Hz * w2 - Baud rate - * x3 - pointer to empty console_ls_16550_t struct + * x3 - pointer to empty console_t struct * Out: return 1 on success, 0 on error * Clobber list : x0, x1, x2, x6, x7, x14 * ----------------------------------------------- @@ -98,7 +98,7 @@ func console_ls_16550_register mov x7, x30 mov x6, x3 cbz x6, register_fail - str x0, [x6, #CONSOLE_T_16550_BASE] + str x0, [x6, #CONSOLE_T_BASE] bl console_ls_16550_core_init cbz x0, register_fail @@ -150,7 +150,7 @@ func console_ls_16550_core_putc endfunc console_ls_16550_core_putc /* -------------------------------------------------------- - * int console_16550_putc(int c, console_ls_16550_t *console) + * int console_16550_putc(int c, console_t *console) * Function to output a character over the console. It * returns the character printed on success or -1 on error. * In : w0 - character to be printed @@ -164,7 +164,7 @@ func console_ls_16550_putc cmp x1, #0 ASM_ASSERT(ne) #endif /* ENABLE_ASSERTIONS */ - ldr x1, [x1, #CONSOLE_T_16550_BASE] + ldr x1, [x1, #CONSOLE_T_BASE] b console_ls_16550_core_putc endfunc console_ls_16550_putc @@ -195,7 +195,7 @@ no_char: endfunc console_ls_16550_core_getc /* --------------------------------------------- - * int console_ls_16550_getc(console_ls_16550_t *console) + * int console_ls_16550_getc(console_t *console) * Function to get a character from the console. * It returns the character grabbed on success * or -1 on if no character is available. @@ -209,7 +209,7 @@ func console_ls_16550_getc cmp x1, #0 ASM_ASSERT(ne) #endif /* ENABLE_ASSERTIONS */ - ldr x0, [x0, #CONSOLE_T_16550_BASE] + ldr x0, [x0, #CONSOLE_T_BASE] b console_ls_16550_core_getc endfunc console_ls_16550_getc @@ -239,7 +239,7 @@ func console_ls_16550_core_flush endfunc console_ls_16550_core_flush /* --------------------------------------------- - * int console_ls_16550_flush(console_ls_16550_t *console) + * int console_ls_16550_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - pointer to console_t structure @@ -252,6 +252,6 @@ func console_ls_16550_flush cmp x0, #0 ASM_ASSERT(ne) #endif /* ENABLE_ASSERTIONS */ - ldr x0, [x0, #CONSOLE_T_16550_BASE] + ldr x0, [x0, #CONSOLE_T_BASE] b console_ls_16550_core_flush endfunc console_ls_16550_flush diff --git a/plat/layerscape/common/include/ls_16550.h b/plat/layerscape/common/include/ls_16550.h index cb4514f3f..95a64ad34 100644 --- a/plat/layerscape/common/include/ls_16550.h +++ b/plat/layerscape/common/include/ls_16550.h @@ -61,17 +61,10 @@ #define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */ #define UARTLSR_RDR (1 << 2) /* Rx Data Ready */ -#define CONSOLE_T_16550_BASE CONSOLE_T_DRVDATA - #ifndef __ASSEMBLER__ #include <stdint.h> -typedef struct { - console_t console; - uintptr_t base; -} console_ls_16550_t; - /* * Initialize a new 16550 console instance and register it with the console * framework. The |console| pointer must point to storage that will be valid @@ -79,7 +72,7 @@ typedef struct { * Its contents will be reinitialized from scratch. */ int console_ls_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_ls_16550_t *console); + console_t *console); #endif /*__ASSEMBLER__*/ diff --git a/plat/layerscape/common/ls_bl1_setup.c b/plat/layerscape/common/ls_bl1_setup.c index fff065efd..fa69be2e6 100644 --- a/plat/layerscape/common/ls_bl1_setup.c +++ b/plat/layerscape/common/ls_bl1_setup.c @@ -23,7 +23,7 @@ meminfo_t *bl1_plat_sec_mem_layout(void) ******************************************************************************/ void ls_bl1_early_platform_setup(void) { - static console_ls_16550_t console; + static console_t console; #if !LS1043_DISABLE_TRUSTED_WDOG /* TODO: Enable watchdog */ diff --git a/plat/layerscape/common/ls_bl2_setup.c b/plat/layerscape/common/ls_bl2_setup.c index 35f42e1fb..6ca66bd47 100644 --- a/plat/layerscape/common/ls_bl2_setup.c +++ b/plat/layerscape/common/ls_bl2_setup.c @@ -23,7 +23,7 @@ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); ******************************************************************************/ void ls_bl2_early_platform_setup(meminfo_t *mem_layout) { - static console_ls_16550_t console; + static console_t console; /* Initialize the console to provide early debug support */ console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK, diff --git a/plat/layerscape/common/ls_bl31_setup.c b/plat/layerscape/common/ls_bl31_setup.c index 03e580768..7a91aef81 100644 --- a/plat/layerscape/common/ls_bl31_setup.c +++ b/plat/layerscape/common/ls_bl31_setup.c @@ -67,7 +67,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) void ls_bl31_early_platform_setup(void *from_bl2, void *plat_params_from_bl2) { - static console_ls_16550_t console; + static console_t console; /* Initialize the console to provide early debug support */ console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK, @@ -182,7 +182,7 @@ void ls_bl31_platform_setup(void) ******************************************************************************/ void ls_bl31_plat_runtime_setup(void) { - static console_ls_16550_t console; + static console_t console; /* Initialize the runtime console */ console_ls_16550_register(PLAT_LS1043_UART_BASE, PLAT_LS1043_UART_CLOCK, diff --git a/plat/layerscape/common/tsp/ls_tsp_setup.c b/plat/layerscape/common/tsp/ls_tsp_setup.c index f3b60276c..969d0b83b 100644 --- a/plat/layerscape/common/tsp/ls_tsp_setup.c +++ b/plat/layerscape/common/tsp/ls_tsp_setup.c @@ -30,7 +30,7 @@ gicv2_driver_data_t ls_gic_data = { ******************************************************************************/ void ls_tsp_early_platform_setup(void) { - static console_ls_16550_t console; + static console_t console; /* * Initialize a different console than already in use to display * messages from TSP diff --git a/plat/marvell/common/marvell_console.c b/plat/marvell/common/marvell_console.c index 22c5eb3af..17166618a 100644 --- a/plat/marvell/common/marvell_console.c +++ b/plat/marvell/common/marvell_console.c @@ -14,16 +14,15 @@ #ifdef PLAT_a3700 #include <drivers/marvell/uart/a3700_console.h> - -static console_a3700_t marvell_boot_console; -static console_a3700_t marvell_runtime_console; +#define console_marvell_register console_a3700_register #else #include <drivers/ti/uart/uart_16550.h> - -static console_16550_t marvell_boot_console; -static console_16550_t marvell_runtime_console; +#define console_marvell_register console_16550_register #endif +static console_t marvell_boot_console; +static console_t marvell_runtime_console; + /******************************************************************************* * Functions that set up the console ******************************************************************************/ @@ -32,15 +31,10 @@ static console_16550_t marvell_runtime_console; void marvell_console_boot_init(void) { int rc = -#ifdef PLAT_a3700 - console_a3700_register( -#else - console_16550_register( -#endif - PLAT_MARVELL_BOOT_UART_BASE, - PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, - MARVELL_CONSOLE_BAUDRATE, - &marvell_boot_console); + console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE, + PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, + MARVELL_CONSOLE_BAUDRATE, + &marvell_boot_console); if (rc == 0) { /* * The crash console doesn't use the multi console API, it uses @@ -50,40 +44,33 @@ void marvell_console_boot_init(void) panic(); } - console_set_scope(&marvell_boot_console.console, - CONSOLE_FLAG_BOOT); + console_set_scope(&marvell_boot_console, CONSOLE_FLAG_BOOT); } void marvell_console_boot_end(void) { (void)console_flush(); - (void)console_unregister(&marvell_boot_console.console); + (void)console_unregister(&marvell_boot_console); } /* Initialize the runtime console */ void marvell_console_runtime_init(void) { int rc = -#ifdef PLAT_a3700 - console_a3700_register( -#else - console_16550_register( -#endif - PLAT_MARVELL_BOOT_UART_BASE, - PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, - MARVELL_CONSOLE_BAUDRATE, - &marvell_runtime_console); + console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE, + PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, + MARVELL_CONSOLE_BAUDRATE, + &marvell_runtime_console); if (rc == 0) panic(); - console_set_scope(&marvell_runtime_console.console, - CONSOLE_FLAG_RUNTIME); + console_set_scope(&marvell_runtime_console, CONSOLE_FLAG_RUNTIME); } void marvell_console_runtime_end(void) { (void)console_flush(); - (void)console_unregister(&marvell_runtime_console.console); + (void)console_unregister(&marvell_runtime_console); } diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index 73a479b50..bd7d0b0ee 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -100,7 +100,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - static console_16550_t console; + static console_t console; console_16550_register(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE, &console); diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c index 8204d7717..e96b4ad0c 100644 --- a/plat/mediatek/mt8183/bl31_plat_setup.c +++ b/plat/mediatek/mt8183/bl31_plat_setup.c @@ -112,7 +112,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - static console_16550_t console; + static console_t console; params_early_setup(arg1); diff --git a/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c index 64d854885..56d2ce26c 100644 --- a/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c +++ b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c @@ -138,15 +138,9 @@ void emi_mpu_init(void) (FORBIDDEN << 6)); emi_mpu_set_region_protection(0x52900000UL, 0x5FFFFFFFUL, 2, (FORBIDDEN << 3 | FORBIDDEN << 6)); - emi_mpu_set_region_protection(0x60000000UL, 0x7FFFFFFFUL, 3, + emi_mpu_set_region_protection(0x60000000UL, 0xFFFFFFFFUL, 3, (FORBIDDEN << 3 | FORBIDDEN << 6)); - emi_mpu_set_region_protection(0x80000000UL, 0x9FFFFFFFUL, 4, - (FORBIDDEN << 3 | FORBIDDEN << 6)); - emi_mpu_set_region_protection(0xA0000000UL, 0xBFFFFFFFUL, 5, - (FORBIDDEN << 3 | FORBIDDEN << 6)); - emi_mpu_set_region_protection(0xC0000000UL, 0xDFFFFFFFUL, 6, - (FORBIDDEN << 3 | FORBIDDEN << 6)); - emi_mpu_set_region_protection(0xE0000000UL, 0xFFFFFFFFUL, 7, + emi_mpu_set_region_protection(0x100000000UL, 0x23FFFFFFFUL, 4, (FORBIDDEN << 3 | FORBIDDEN << 6)); dump_emi_mpu_regions(); } diff --git a/plat/nvidia/tegra/common/drivers/spe/shared_console.S b/plat/nvidia/tegra/common/drivers/spe/shared_console.S index 0be34e417..c783373dd 100644 --- a/plat/nvidia/tegra/common/drivers/spe/shared_console.S +++ b/plat/nvidia/tegra/common/drivers/spe/shared_console.S @@ -49,14 +49,14 @@ /* ------------------------------------------------- * int console_spe_register(uintptr_t baseaddr, * uint32_t clock, uint32_t baud, - * console_spe_t *console); + * console_t *console); * Function to initialize and register a new spe * console. Storage passed in for the console struct * *must* be persistent (i.e. not from the stack). * In: x0 - UART register base address * w1 - UART clock in Hz * w2 - Baud rate - * x3 - pointer to empty console_spe_t struct + * x3 - pointer to empty console_t struct * Out: return 1 on success, 0 on error * Clobber list : x0, x1, x2, x6, x7, x14 * ------------------------------------------------- @@ -122,7 +122,7 @@ putc_error: endfunc console_spe_core_putc /* -------------------------------------------------------- - * int console_spe_putc(int c, console_spe_t *console) + * int console_spe_putc(int c, console_t *console) * Function to output a character over the console. It * returns the character printed on success or -1 on error. * In : w0 - character to be printed @@ -137,7 +137,7 @@ func console_spe_putc endfunc console_spe_putc /* --------------------------------------------- - * int console_spe_getc(console_spe_t *console) + * int console_spe_getc(console_t *console) * Function to get a character from the console. * It returns the character grabbed on success * or -1 if no character is available. @@ -174,7 +174,7 @@ flush_error: endfunc console_spe_core_flush /* --------------------------------------------- - * int console_spe_flush(console_spe_t *console) + * int console_spe_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - pointer to console_t structure diff --git a/plat/nvidia/tegra/include/drivers/spe.h b/plat/nvidia/tegra/include/drivers/spe.h index 0d6d69d10..e0f871408 100644 --- a/plat/nvidia/tegra/include/drivers/spe.h +++ b/plat/nvidia/tegra/include/drivers/spe.h @@ -11,11 +11,6 @@ #include <drivers/console.h> -typedef struct { - console_t console; - uintptr_t base; -} console_spe_t; - /* * Initialize a new spe console instance and register it with the console * framework. The |console| pointer must point to storage that will be valid @@ -23,6 +18,6 @@ typedef struct { * Its contents will be reinitialized from scratch. */ int console_spe_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_spe_t *console); + console_t *console); #endif /* SPE_H */ diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c index 4bfc2de0e..43acdd642 100644 --- a/plat/nvidia/tegra/soc/t132/plat_setup.c +++ b/plat/nvidia/tegra/soc/t132/plat_setup.c @@ -92,7 +92,7 @@ static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = { ******************************************************************************/ void plat_enable_console(int32_t id) { - static console_16550_t uart_console; + static console_t uart_console; uint32_t console_clock; if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) { @@ -109,7 +109,7 @@ void plat_enable_console(int32_t id) console_clock, TEGRA_CONSOLE_BAUDRATE, &uart_console); - console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | + console_set_scope(&uart_console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); } } diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c index 06a328427..7028bfc5d 100644 --- a/plat/nvidia/tegra/soc/t186/plat_setup.c +++ b/plat/nvidia/tegra/soc/t186/plat_setup.c @@ -150,7 +150,7 @@ static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { ******************************************************************************/ void plat_enable_console(int32_t id) { - static console_16550_t uart_console; + static console_t uart_console; uint32_t console_clock; if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) { @@ -167,7 +167,7 @@ void plat_enable_console(int32_t id) console_clock, TEGRA_CONSOLE_BAUDRATE, &uart_console); - console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | + console_set_scope(&uart_console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); } } diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 3640ade0a..235fba43c 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -163,18 +163,18 @@ void plat_enable_console(int32_t id) uint32_t console_clock = 0U; #if ENABLE_CONSOLE_SPE - static console_spe_t spe_console; + static console_t spe_console; if (id == TEGRA_CONSOLE_SPE_ID) { (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE, console_clock, TEGRA_CONSOLE_BAUDRATE, &spe_console); - console_set_scope(&spe_console.console, CONSOLE_FLAG_BOOT | + console_set_scope(&spe_console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); } #else - static console_16550_t uart_console; + static console_t uart_console; if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) { /* @@ -190,7 +190,7 @@ void plat_enable_console(int32_t id) console_clock, TEGRA_CONSOLE_BAUDRATE, &uart_console); - console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | + console_set_scope(&uart_console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); } #endif diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c index c32772de8..7afbe0d9a 100644 --- a/plat/nvidia/tegra/soc/t210/plat_setup.c +++ b/plat/nvidia/tegra/soc/t210/plat_setup.c @@ -119,7 +119,7 @@ static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { ******************************************************************************/ void plat_enable_console(int32_t id) { - static console_16550_t uart_console; + static console_t uart_console; uint32_t console_clock; if ((id > 0) && (id < TEGRA210_MAX_UART_PORTS)) { @@ -136,7 +136,7 @@ void plat_enable_console(int32_t id) console_clock, TEGRA_CONSOLE_BAUDRATE, &uart_console); - console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | + console_set_scope(&uart_console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); } } diff --git a/plat/qemu/common/qemu_console.c b/plat/qemu/common/qemu_console.c index fec182892..1f00f8a72 100644 --- a/plat/qemu/common/qemu_console.c +++ b/plat/qemu/common/qemu_console.c @@ -9,7 +9,7 @@ #include <drivers/console.h> #include <drivers/arm/pl011.h> -static console_pl011_t console; +static console_t console; void qemu_console_init(void) { @@ -17,7 +17,7 @@ void qemu_console_init(void) PLAT_QEMU_BOOT_UART_CLK_IN_HZ, PLAT_QEMU_CONSOLE_BAUDRATE, &console); - console_set_scope(&console.console, CONSOLE_FLAG_BOOT | + console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); } diff --git a/plat/renesas/rcar/rcar_common.c b/plat/renesas/rcar/rcar_common.c index 4ea753f2d..dec7229b3 100644 --- a/plat/renesas/rcar/rcar_common.c +++ b/plat/renesas/rcar/rcar_common.c @@ -70,8 +70,8 @@ void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, #include <drivers/renesas/rcar/console/console.h> -static console_rcar_t rcar_boot_console; -static console_rcar_t rcar_runtime_console; +static console_t rcar_boot_console; +static console_t rcar_runtime_console; void rcar_console_boot_init(void) { @@ -81,7 +81,7 @@ void rcar_console_boot_init(void) if (!ret) panic(); - console_set_scope(&rcar_boot_console.console, CONSOLE_FLAG_BOOT); + console_set_scope(&rcar_boot_console, CONSOLE_FLAG_BOOT); } void rcar_console_boot_end(void) @@ -96,7 +96,7 @@ void rcar_console_runtime_init(void) if (!ret) panic(); - console_set_scope(&rcar_boot_console.console, CONSOLE_FLAG_RUNTIME); + console_set_scope(&rcar_boot_console, CONSOLE_FLAG_RUNTIME); } void rcar_console_runtime_end(void) diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index c4a03592e..98ef415c9 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -57,7 +57,7 @@ void params_early_setup(u_register_t plat_param_from_bl2) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - static console_16550_t console; + static console_t console; params_early_setup(arg1); diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c index 6d15075f2..0237b167f 100644 --- a/plat/rockchip/common/sp_min_plat_setup.c +++ b/plat/rockchip/common/sp_min_plat_setup.c @@ -52,7 +52,7 @@ unsigned int plat_is_my_cpu_primary(void); void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - static console_16550_t console; + static console_t console; params_early_setup(arg1); diff --git a/plat/rpi/common/rpi3_common.c b/plat/rpi/common/rpi3_common.c index ff3369427..27281f2ba 100644 --- a/plat/rpi/common/rpi3_common.c +++ b/plat/rpi/common/rpi3_common.c @@ -102,7 +102,7 @@ static const mmap_region_t plat_rpi3_mmap[] = { /******************************************************************************* * Function that sets up the console ******************************************************************************/ -static console_16550_t rpi3_console; +static console_t rpi3_console; void rpi3_console_init(unsigned int base_clk_rate) { @@ -123,7 +123,7 @@ void rpi3_console_init(unsigned int base_clk_rate) panic(); } - console_set_scope(&rpi3_console.console, console_scope); + console_set_scope(&rpi3_console, console_scope); } /******************************************************************************* diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c index b86402179..9723ef9f0 100644 --- a/plat/socionext/synquacer/sq_bl31_setup.c +++ b/plat/socionext/synquacer/sq_bl31_setup.c @@ -16,7 +16,7 @@ #include <lib/mmio.h> #include <sq_common.h> -static console_pl011_t console; +static console_t console; static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; @@ -69,8 +69,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, PLAT_SQ_BOOT_UART_CLK_IN_HZ, SQ_CONSOLE_BAUDRATE, &console); - console_set_scope(&console.console, CONSOLE_FLAG_BOOT | - CONSOLE_FLAG_RUNTIME); + console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); /* There are no parameters from BL2 if BL31 is a reset vector */ assert(arg0 == 0U); diff --git a/plat/socionext/uniphier/uniphier_console.S b/plat/socionext/uniphier/uniphier_console.S index 1113c6e81..f3dde0cc1 100644 --- a/plat/socionext/uniphier/uniphier_console.S +++ b/plat/socionext/uniphier/uniphier_console.S @@ -17,7 +17,7 @@ */ .globl uniphier_console_putc func uniphier_console_putc - ldr x1, [x1, #CONSOLE_T_DRVDATA] + ldr x1, [x1, #CONSOLE_T_BASE] /* Wait until the transmitter FIFO gets empty */ 0: ldr w2, [x1, #UNIPHIER_UART_LSR] @@ -36,7 +36,7 @@ endfunc uniphier_console_putc */ .globl uniphier_console_getc func uniphier_console_getc - ldr x0, [x0, #CONSOLE_T_DRVDATA] + ldr x0, [x0, #CONSOLE_T_BASE] ldr w1, [x0, #UNIPHIER_UART_LSR] tbz w1, #UNIPHIER_UART_LSR_DR_BIT, 0f @@ -55,7 +55,7 @@ endfunc uniphier_console_getc */ .global uniphier_console_flush func uniphier_console_flush - ldr x0, [x0, #CONSOLE_T_DRVDATA] + ldr x0, [x0, #CONSOLE_T_BASE] /* wait until the transmitter gets empty */ 0: ldr w1, [x0, #UNIPHIER_UART_LSR] diff --git a/plat/socionext/uniphier/uniphier_console_setup.c b/plat/socionext/uniphier/uniphier_console_setup.c index 1851e4da5..e2ae8bf28 100644 --- a/plat/socionext/uniphier/uniphier_console_setup.c +++ b/plat/socionext/uniphier/uniphier_console_setup.c @@ -17,28 +17,21 @@ #define UNIPHIER_UART_OFFSET 0x100 #define UNIPHIER_UART_NR_PORTS 4 -struct uniphier_console { - struct console console; - uintptr_t base; -}; - /* These callbacks are implemented in assembly to use crash_console_helpers.S */ int uniphier_console_putc(int character, struct console *console); int uniphier_console_getc(struct console *console); int uniphier_console_flush(struct console *console); -static struct uniphier_console uniphier_console = { - .console = { - .flags = CONSOLE_FLAG_BOOT | +static console_t uniphier_console = { + .flags = CONSOLE_FLAG_BOOT | #if DEBUG - CONSOLE_FLAG_RUNTIME | + CONSOLE_FLAG_RUNTIME | #endif - CONSOLE_FLAG_CRASH | - CONSOLE_FLAG_TRANSLATE_CRLF, - .putc = uniphier_console_putc, - .getc = uniphier_console_getc, - .flush = uniphier_console_flush, - }, + CONSOLE_FLAG_CRASH | + CONSOLE_FLAG_TRANSLATE_CRLF, + .putc = uniphier_console_putc, + .getc = uniphier_console_getc, + .flush = uniphier_console_flush, }; static const uintptr_t uniphier_uart_base[] = { @@ -86,7 +79,7 @@ void uniphier_console_setup(unsigned int soc) plat_error_handler(-EINVAL); uniphier_console.base = base; - console_register(&uniphier_console.console); + console_register(&uniphier_console); /* * The hardware might be still printing characters queued up in the diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c index 96180f159..e89c8358c 100644 --- a/plat/socionext/uniphier/uniphier_io_storage.c +++ b/plat/socionext/uniphier/uniphier_io_storage.c @@ -23,7 +23,6 @@ #define UNIPHIER_ROM_REGION_BASE 0x00000000ULL #define UNIPHIER_ROM_REGION_SIZE 0x10000000ULL -#define UNIPHIER_OCM_REGION_BASE 0x30000000ULL #define UNIPHIER_OCM_REGION_SIZE 0x00040000ULL #define UNIPHIER_BLOCK_BUF_OFFSET 0x04200000UL @@ -278,12 +277,20 @@ static int uniphier_io_nor_setup(unsigned int soc_id, size_t buffer_offset) return uniphier_io_memmap_setup(0x70000); } -static int uniphier_io_usb_setup(unsigned int soc_id, size_t buffer_offset) +static const uintptr_t uniphier_ocm_base[] = { + [UNIPHIER_SOC_LD11] = 0x30000000, + [UNIPHIER_SOC_LD20] = 0x30000000, + [UNIPHIER_SOC_PXS3] = 0x30000000, +}; + +static int uniphier_io_rom_api_setup(unsigned int soc) { - struct io_block_dev_spec *block_dev_spec; + uintptr_t ocm_base; int ret; - /* use ROM API for loading images from USB storage */ + assert(soc < ARRAY_SIZE(uniphier_ocm_base)); + ocm_base = uniphier_ocm_base[soc]; + ret = mmap_add_dynamic_region(UNIPHIER_ROM_REGION_BASE, UNIPHIER_ROM_REGION_BASE, UNIPHIER_ROM_REGION_SIZE, @@ -296,14 +303,26 @@ static int uniphier_io_usb_setup(unsigned int soc_id, size_t buffer_offset) * load functions provided by the ROM use this memory region as a work * area, but do not cater to cache coherency. */ - ret = mmap_add_dynamic_region(UNIPHIER_OCM_REGION_BASE, - UNIPHIER_OCM_REGION_BASE, + ret = mmap_add_dynamic_region(ocm_base, ocm_base, UNIPHIER_OCM_REGION_SIZE, MT_DEVICE | MT_RW | MT_SECURE); if (ret) return ret; - ret = uniphier_usb_init(soc_id, &block_dev_spec); + return 0; +} + +static int uniphier_io_usb_setup(unsigned int soc, size_t buffer_offset) +{ + struct io_block_dev_spec *block_dev_spec; + int ret; + + /* use ROM API for loading images from USB storage */ + ret = uniphier_io_rom_api_setup(soc); + if (ret) + return ret; + + ret = uniphier_usb_init(soc, &block_dev_spec); if (ret) return ret; diff --git a/plat/socionext/uniphier/uniphier_soc_info.c b/plat/socionext/uniphier/uniphier_soc_info.c index 377532deb..0e7a2d11a 100644 --- a/plat/socionext/uniphier/uniphier_soc_info.c +++ b/plat/socionext/uniphier/uniphier_soc_info.c @@ -4,18 +4,25 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <common/bl_common.h> #include <lib/mmio.h> #include "uniphier.h" -#define UNIPHIER_REVISION 0x5f800000 +#define UNIPHIER_REVISION 0x5f800000UL +#define UNIPHIER_REVISION_NEW 0x1f800000UL static unsigned int uniphier_get_revision_field(unsigned int mask, unsigned int shift) { - uint32_t revision = mmio_read_32(UNIPHIER_REVISION); + uintptr_t reg; - return (revision >> shift) & mask; + if (BL_CODE_BASE >= 0x80000000UL) + reg = UNIPHIER_REVISION; + else + reg = UNIPHIER_REVISION_NEW; + + return (mmio_read_32(reg) >> shift) & mask; } unsigned int uniphier_get_soc_type(void) diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index d9e29b4e8..024dbe076 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -31,7 +31,7 @@ #include <stm32mp1_context.h> #include <stm32mp1_dbgmcu.h> -static struct console_stm32 console; +static console_t console; static struct stm32mp_auth_ops stm32mp1_auth_ops; static void print_reset_reason(void) @@ -273,7 +273,7 @@ void bl2_el3_plat_arch_setup(void) panic(); } - console_set_scope(&console.console, CONSOLE_FLAG_BOOT | + console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF); stm32mp_print_cpuinfo(); diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c index e10dfbfc0..4e74c275d 100644 --- a/plat/st/stm32mp1/sp_min/sp_min_setup.c +++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c @@ -35,7 +35,7 @@ ******************************************************************************/ static entry_point_info_t bl33_image_ep_info; -static struct console_stm32 console; +static console_t console; /******************************************************************************* * Interrupt handler for FIQ (secure IRQ) @@ -142,7 +142,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, #ifdef DEBUG console_flags |= CONSOLE_FLAG_RUNTIME; #endif - console_set_scope(&console.console, console_flags); + console_set_scope(&console, console_flags); } } diff --git a/plat/ti/k3/common/k3_console.c b/plat/ti/k3/common/k3_console.c index ba0ddacec..8c44c17e2 100644 --- a/plat/ti/k3/common/k3_console.c +++ b/plat/ti/k3/common/k3_console.c @@ -13,7 +13,7 @@ void bl31_console_setup(void) { - static console_16550_t console; + static console_t console; /* Initialize the console to provide early debug support */ console_16550_register(K3_USART_BASE, K3_USART_CLK_SPEED, diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c index a5cf05e9a..03b7fbbb4 100644 --- a/plat/xilinx/versal/bl31_versal_setup.c +++ b/plat/xilinx/versal/bl31_versal_setup.c @@ -22,7 +22,7 @@ static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; -static console_pl011_t versal_runtime_console; +static console_t versal_runtime_console; /* * Return a pointer to the 'entry_point_info' structure of the next image for @@ -71,7 +71,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, if (rc == 0) panic(); - console_set_scope(&versal_runtime_console.console, CONSOLE_FLAG_BOOT | + console_set_scope(&versal_runtime_console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); /* Initialize the platform config for future decision making */ diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index 6e0e811d4..b6d8770cc 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -62,12 +62,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, { uint64_t atf_handoff_addr; /* Register the console to provide early debug support */ - static console_cdns_t bl31_boot_console; + static console_t bl31_boot_console; (void)console_cdns_register(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(), ZYNQMP_UART_BAUDRATE, &bl31_boot_console); - console_set_scope(&bl31_boot_console.console, + console_set_scope(&bl31_boot_console, CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); /* Initialize the platform config for future decision making */ diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c index 7f0ac74cf..5e770f75c 100644 --- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c +++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c @@ -21,12 +21,12 @@ void tsp_early_platform_setup(void) * Register a different console than already in use to display * messages from TSP */ - static console_cdns_t tsp_boot_console; + static console_t tsp_boot_console; (void)console_cdns_register(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(), ZYNQMP_UART_BAUDRATE, &tsp_boot_console); - console_set_scope(&tsp_boot_console.console, + console_set_scope(&tsp_boot_console, CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); /* Initialize the platform config for future decision making */ |