diff options
Diffstat (limited to 'plat')
53 files changed, 399 insertions, 370 deletions
diff --git a/plat/arm/board/fvp/aarch64/fvp_helpers.S b/plat/arm/board/fvp/aarch64/fvp_helpers.S index 6ea458515..88fcdb1b0 100644 --- a/plat/arm/board/fvp/aarch64/fvp_helpers.S +++ b/plat/arm/board/fvp/aarch64/fvp_helpers.S @@ -178,19 +178,22 @@ func plat_is_my_cpu_primary ret endfunc plat_is_my_cpu_primary - /* ----------------------------------------------------- + /* --------------------------------------------------------------------- * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) * * Function to calculate the core position on FVP. * - * (ClusterId * FVP_MAX_CPUS_PER_CLUSTER) + + * (ClusterId * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) + * (CPUId * FVP_MAX_PE_PER_CPU) + * ThreadId - * ----------------------------------------------------- + * + * which can be simplified as: + * + * ((ClusterId * FVP_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_MAX_PE_PER_CPU) + * + ThreadId + * --------------------------------------------------------------------- */ func plat_arm_calc_core_pos - mov x3, x0 - /* * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it * look as if in a multi-threaded implementation. @@ -205,9 +208,9 @@ func plat_arm_calc_core_pos ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS /* Compute linear position */ - mov x4, #FVP_MAX_PE_PER_CPU - madd x0, x1, x4, x0 - mov x5, #FVP_MAX_CPUS_PER_CLUSTER - madd x0, x2, x5, x0 + mov x4, #FVP_MAX_CPUS_PER_CLUSTER + madd x1, x2, x4, x1 + mov x5, #FVP_MAX_PE_PER_CPU + madd x0, x1, x5, x0 ret endfunc plat_arm_calc_core_pos diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index 2df11d653..af258b060 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -145,6 +145,7 @@ const mmap_region_t plat_arm_secure_partition_mmap[] = { const mmap_region_t plat_arm_mmap[] = { #ifdef AARCH32 ARM_MAP_SHARED_RAM, + ARM_V2M_MAP_MEM_PROTECT, #endif V2M_MAP_IOFPGA, MAP_DEVICE0, diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c index f61cdb3c3..0fa83a5c0 100644 --- a/plat/arm/board/fvp/fvp_pm.c +++ b/plat/arm/board/fvp/fvp_pm.c @@ -324,13 +324,11 @@ static int fvp_node_hw_state(u_register_t target_cpu, if (psysr == PSYSR_INVALID) return PSCI_E_INVALID_PARAMS; - switch (power_level) { - case ARM_PWR_LVL0: + if (power_level == ARM_PWR_LVL0) { ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF; - break; - case ARM_PWR_LVL1: + } else { + /* power_level == ARM_PWR_LVL1 */ ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF; - break; } return ret; diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index 7add61dab..8a6c7680e 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -305,6 +305,9 @@ int arm_bl2_handle_post_image_load(unsigned int image_id) } break; #endif + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/arm/common/execution_state_switch.c b/plat/arm/common/execution_state_switch.c index 8499db074..22d552ad9 100644 --- a/plat/arm/common/execution_state_switch.c +++ b/plat/arm/common/execution_state_switch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,7 @@ #include <context_mgmt.h> #include <plat_arm.h> #include <psci.h> -#include <smcc_helpers.h> +#include <smccc_helpers.h> #include <string.h> #include <utils.h> diff --git a/plat/common/plat_gicv2.c b/plat/common/plat_gicv2.c index ca6c03b01..026ea7132 100644 --- a/plat/common/plat_gicv2.c +++ b/plat/common/plat_gicv2.c @@ -190,6 +190,8 @@ void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) int plat_ic_has_interrupt_type(unsigned int type) { + int has_interrupt_type = 0; + switch (type) { #if GICV2_G0_FOR_EL3 case INTR_TYPE_EL3: @@ -197,10 +199,14 @@ int plat_ic_has_interrupt_type(unsigned int type) case INTR_TYPE_S_EL1: #endif case INTR_TYPE_NS: - return 1; + has_interrupt_type = 1; + break; default: - return 0; + /* Do nothing in default case */ + break; } + + return has_interrupt_type; } void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) @@ -221,6 +227,7 @@ void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) break; default: assert(0); + break; } gicv2_set_interrupt_type(id, gicv2_type); @@ -260,6 +267,7 @@ void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, break; default: assert(0); + break; } gicv2_set_spi_routing(id, proc_num); diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c index 030eea723..26a4973f9 100644 --- a/plat/common/plat_gicv3.c +++ b/plat/common/plat_gicv3.c @@ -158,15 +158,14 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, return __builtin_ctz(SCR_FIQ_BIT); else return __builtin_ctz(SCR_IRQ_BIT); - default: - assert(0); - /* Fall through in the release build */ case INTR_TYPE_EL3: /* * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and * NS-EL0/1/2 contexts */ return __builtin_ctz(SCR_FIQ_BIT); + default: + panic(); } } @@ -248,6 +247,7 @@ void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, break; default: assert(0); + break; } gicv3_set_spi_routing(id, irm, mpidr); diff --git a/plat/hisilicon/hikey/aarch64/hikey_common.c b/plat/hisilicon/hikey/aarch64/hikey_common.c index f95af5870..658760b5a 100644 --- a/plat/hisilicon/hikey/aarch64/hikey_common.c +++ b/plat/hisilicon/hikey/aarch64/hikey_common.c @@ -9,13 +9,12 @@ #include <assert.h> #include <bl_common.h> #include <debug.h> +#include <hikey_def.h> +#include <hikey_layout.h> #include <mmio.h> #include <platform.h> -#include <platform_def.h> #include <xlat_tables.h> -#include "../hikey_def.h" - #define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \ DDR_SIZE - DDR_SEC_SIZE, \ MT_DEVICE | MT_RW | MT_NS) diff --git a/plat/hisilicon/hikey/aarch64/hikey_helpers.S b/plat/hisilicon/hikey/aarch64/hikey_helpers.S index 680c0a1d4..32ff8b40c 100644 --- a/plat/hisilicon/hikey/aarch64/hikey_helpers.S +++ b/plat/hisilicon/hikey/aarch64/hikey_helpers.S @@ -1,12 +1,12 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch.h> #include <asm_macros.S> -#include "../hikey_def.h" +#include <hikey_def.h> .globl plat_my_core_pos .globl platform_mem_init diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c index 69b194a53..28ad9df22 100644 --- a/plat/hisilicon/hikey/hikey_bl1_setup.c +++ b/plat/hisilicon/hikey/hikey_bl1_setup.c @@ -13,33 +13,16 @@ #include <emmc.h> #include <errno.h> #include <hi6220.h> +#include <hikey_def.h> +#include <hikey_layout.h> #include <mmio.h> #include <platform.h> -#include <platform_def.h> #include <string.h> #include <tbbr/tbbr_img_desc.h> #include "../../bl1/bl1_private.h" -#include "hikey_def.h" #include "hikey_private.h" -/* - * Declarations of linker defined symbols which will help us find the layout - * of trusted RAM - */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) - /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -103,8 +86,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } /* diff --git a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c index 7c025c34d..23c16ed99 100644 --- a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c +++ b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c @@ -7,7 +7,7 @@ #include <bl_common.h> #include <desc_image_load.h> #include <platform.h> -#include <platform_def.h> +#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/ /******************************************************************************* diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c index 20bb7527e..a78bb1e91 100644 --- a/plat/hisilicon/hikey/hikey_bl2_setup.c +++ b/plat/hisilicon/hikey/hikey_bl2_setup.c @@ -21,10 +21,9 @@ #include <optee_utils.h> #endif #include <platform.h> -#include <platform_def.h> +#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/ #include <string.h> -#include "hikey_def.h" #include "hikey_private.h" /* @@ -176,6 +175,9 @@ int hikey_bl2_handle_post_image_load(unsigned int image_id) } break; #endif + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/hisilicon/hikey/hikey_bl31_setup.c b/plat/hisilicon/hikey/hikey_bl31_setup.c index e13ecf675..a193b5a7f 100644 --- a/plat/hisilicon/hikey/hikey_bl31_setup.c +++ b/plat/hisilicon/hikey/hikey_bl31_setup.c @@ -14,12 +14,12 @@ #include <errno.h> #include <gicv2.h> #include <hi6220.h> +#include <hikey_def.h> #include <hisi_ipc.h> #include <hisi_pwrc.h> #include <mmio.h> #include <platform_def.h> -#include "hikey_def.h" #include "hikey_private.h" /* diff --git a/plat/hisilicon/hikey/hikey_pm.c b/plat/hisilicon/hikey/hikey_pm.c index d4dd683e0..3128a3d12 100644 --- a/plat/hisilicon/hikey/hikey_pm.c +++ b/plat/hisilicon/hikey/hikey_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include <debug.h> #include <gicv2.h> #include <hi6220.h> +#include <hikey_def.h> #include <hisi_ipc.h> #include <hisi_pwrc.h> #include <hisi_sram_map.h> @@ -17,8 +18,6 @@ #include <psci.h> #include <sp804_delay_timer.h> -#include "hikey_def.h" - #define CORE_PWR_STATE(state) \ ((state)->pwr_domain_state[MPIDR_AFFLVL0]) #define CLUSTER_PWR_STATE(state) \ diff --git a/plat/hisilicon/hikey/hikey_def.h b/plat/hisilicon/hikey/include/hikey_def.h index 668b4592b..deb375da9 100644 --- a/plat/hisilicon/hikey/hikey_def.h +++ b/plat/hisilicon/hikey/include/hikey_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,9 +7,6 @@ #ifndef __HIKEY_DEF_H__ #define __HIKEY_DEF_H__ -#include <common_def.h> -#include <tbbr_img_def.h> - /* Always assume DDR is 1GB size. */ #define DDR_BASE 0x0 #define DDR_SIZE 0x40000000 @@ -17,9 +14,6 @@ #define DEVICE_BASE 0xF4000000 #define DEVICE_SIZE 0x05800000 -#define XG2RAM0_BASE 0xF9800000 -#define XG2RAM0_SIZE 0x00400000 - /* Memory location options for TSP */ #define HIKEY_SRAM_ID 0 #define HIKEY_DRAM_ID 1 @@ -43,13 +37,6 @@ #define SRAM_SIZE 0x00012000 /* - * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). - */ -#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) -#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) -#define BL1_XG2RAM0_OFFSET 0x1000 - -/* * PL011 related constants */ #define PL011_UART0_BASE 0xF8015000 diff --git a/plat/hisilicon/hikey/include/hikey_layout.h b/plat/hisilicon/hikey/include/hikey_layout.h new file mode 100644 index 000000000..637a1c9be --- /dev/null +++ b/plat/hisilicon/hikey/include/hikey_layout.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HIKEY_LAYOUT_H +#define __HIKEY_LAYOUT_H + +/* + * Platform memory map related constants + */ +#define XG2RAM0_BASE 0xF9800000 +#define XG2RAM0_SIZE 0x00400000 + +/* + * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). + */ +#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) +#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) +#define BL1_XG2RAM0_OFFSET 0x1000 + +/* + * BL1 specific defines. + * + * Both loader and BL1_RO region stay in SRAM since they are used to simulate + * ROM. + * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. + * + * ++++++++++ 0xF980_0000 + * + loader + + * ++++++++++ 0xF980_1000 + * + BL1_RO + + * ++++++++++ 0xF981_0000 + * + BL1_RW + + * ++++++++++ 0xF989_8000 + */ +#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) +#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) +#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ +#define BL1_RW_SIZE (0x00088000) +#define BL1_RW_LIMIT (0xF9898000) + +/* + * Non-Secure BL1U specific defines. + */ +#define NS_BL1U_BASE (0xf9818000) +#define NS_BL1U_SIZE (0x00010000) +#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) + +/* + * BL2 specific defines. + * + * Both loader and BL2 region stay in SRAM. + * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. + * + * ++++++++++ 0xF980_0000 + * + loader + + * ++++++++++ 0xF980_1000 + * + BL2 + + * ++++++++++ 0xF981_8000 + */ +#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */ +#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */ + +/* + * SCP_BL2 specific defines. + * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer + * at 0x0100_0000. Then BL2 will parse the sections and loaded them into + * predefined separated buffers. + */ +#define SCP_BL2_BASE (DDR_BASE + 0x01000000) +#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000) +#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE) + +/* + * BL31 specific defines. + */ +#define BL31_BASE (0xF9858000) /* 0xf985_8000 */ +#define BL31_LIMIT (0xF9898000) + +/* + * BL3-2 specific defines. + */ + +/* + * The TSP currently executes from TZC secured area of DRAM or SRAM. + */ +#define BL32_SRAM_BASE BL31_LIMIT +#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */ + +#define BL32_DRAM_BASE DDR_SEC_BASE +#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) + +#ifdef SPD_opteed +/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ +#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ +#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ +#endif + +#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID) +#define TSP_SEC_MEM_BASE BL32_DRAM_BASE +#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) +#define BL32_BASE BL32_DRAM_BASE +#define BL32_LIMIT BL32_DRAM_LIMIT +#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID) +#define TSP_SEC_MEM_BASE BL32_SRAM_BASE +#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE) +#define BL32_BASE BL32_SRAM_BASE +#define BL32_LIMIT BL32_SRAM_LIMIT +#else +#error "Currently unsupported HIKEY_TSP_LOCATION_ID value" +#endif + +/* BL32 is mandatory in AArch32 */ +#ifndef AARCH32 +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ +#endif + +#endif /* !__HIKEY_LAYOUT_H */ diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h index 9b4f4631c..8c560047c 100644 --- a/plat/hisilicon/hikey/include/platform_def.h +++ b/plat/hisilicon/hikey/include/platform_def.h @@ -8,7 +8,10 @@ #define __PLATFORM_DEF_H__ #include <arch.h> -#include "../hikey_def.h" +#include <common_def.h> +#include <hikey_def.h> +#include <hikey_layout.h> /* BL memory region sizes, etc */ +#include <tbbr_img_def.h> /* Special value used to verify platform parameters from BL2 to BL3-1 */ #define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL @@ -27,7 +30,7 @@ #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_CORE_COUNT_PER_CLUSTER) -#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 +#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ PLATFORM_CLUSTER_COUNT + 1) @@ -45,114 +48,6 @@ #define PLAT_ARM_GICH_BASE 0xF6804000 #define PLAT_ARM_GICV_BASE 0xF6806000 - -/* - * Platform memory map related constants - */ - -/* - * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). - */ -#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) -#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) -#define BL1_XG2RAM0_OFFSET 0x1000 - -/* - * BL1 specific defines. - * - * Both loader and BL1_RO region stay in SRAM since they are used to simulate - * ROM. - * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. - * - * ++++++++++ 0xF980_0000 - * + loader + - * ++++++++++ 0xF980_1000 - * + BL1_RO + - * ++++++++++ 0xF981_0000 - * + BL1_RW + - * ++++++++++ 0xF989_8000 - */ -#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) -#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) -#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ -#define BL1_RW_SIZE (0x00088000) -#define BL1_RW_LIMIT (0xF9898000) - -/* - * BL2 specific defines. - * - * Both loader and BL2 region stay in SRAM. - * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. - * - * ++++++++++ 0xF980_0000 - * + loader + - * ++++++++++ 0xF980_1000 - * + BL2 + - * ++++++++++ 0xF981_8000 - */ -#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */ -#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */ - -/* - * SCP_BL2 specific defines. - * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer - * at 0x0100_0000. Then BL2 will parse the sections and loaded them into - * predefined separated buffers. - */ -#define SCP_BL2_BASE (DDR_BASE + 0x01000000) -#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000) -#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE) - -/* - * BL31 specific defines. - */ -#define BL31_BASE (0xF9858000) /* 0xf985_8000 */ -#define BL31_LIMIT (0xF9898000) - -/* - * BL3-2 specific defines. - */ - -/* - * The TSP currently executes from TZC secured area of DRAM or SRAM. - */ -#define BL32_SRAM_BASE BL31_LIMIT -#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */ - -#define BL32_DRAM_BASE DDR_SEC_BASE -#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) - -#ifdef SPD_opteed -/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ -#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ -#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ -#endif - -#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID) -#define TSP_SEC_MEM_BASE BL32_DRAM_BASE -#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) -#define BL32_BASE BL32_DRAM_BASE -#define BL32_LIMIT BL32_DRAM_LIMIT -#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID) -#define TSP_SEC_MEM_BASE BL32_SRAM_BASE -#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE) -#define BL32_BASE BL32_SRAM_BASE -#define BL32_LIMIT BL32_SRAM_LIMIT -#else -#error "Currently unsupported HIKEY_TSP_LOCATION_ID value" -#endif - -/* BL32 is mandatory in AArch32 */ -#ifndef AARCH32 -#ifdef SPD_none -#undef BL32_BASE -#endif /* SPD_none */ -#endif - -#define NS_BL1U_BASE (0xf9818000) -#define NS_BL1U_SIZE (0x00010000) -#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) - /* * Platform specific page table and MMU setup constants */ @@ -172,8 +67,6 @@ #define MAX_MMAP_REGIONS 16 -#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000) - /* * Declarations and constants to access the mailboxes safely. Each mailbox is * aligned on the biggest cache line size in the platform. This is known only diff --git a/plat/hisilicon/hikey960/hikey960_bl1_setup.c b/plat/hisilicon/hikey960/hikey960_bl1_setup.c index 9cadba0bb..6a07f0924 100644 --- a/plat/hisilicon/hikey960/hikey960_bl1_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl1_setup.c @@ -37,18 +37,6 @@ enum { * Declarations of linker defined symbols which will help us find the layout * of trusted RAM */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -131,8 +119,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } static void hikey960_ufs_reset(void) diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c index 11bbf9e15..6e726d2f5 100644 --- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c @@ -267,6 +267,9 @@ int hikey960_bl2_handle_post_image_load(unsigned int image_id) } break; #endif + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/hisilicon/hikey960/hikey960_pm.c b/plat/hisilicon/hikey960/hikey960_pm.c index 22963c4f5..ffe7fcf87 100644 --- a/plat/hisilicon/hikey960/hikey960_pm.c +++ b/plat/hisilicon/hikey960/hikey960_pm.c @@ -9,6 +9,7 @@ #include <cci.h> #include <console.h> #include <debug.h> +#include <delay_timer.h> #include <gicv2.h> #include <hi3660.h> #include <hi3660_crg.h> @@ -114,6 +115,9 @@ void hikey960_pwr_domain_off(const psci_power_state_t *target_state) static void __dead2 hikey960_system_reset(void) { + dsb(); + isb(); + mdelay(2000); mmio_write_32(SCTRL_SCPEREN1_REG, SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS); mmio_write_32(SCTRL_SCSYSSTAT_REG, 0xdeadbeef); diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c index 39551135f..25eed5938 100644 --- a/plat/hisilicon/poplar/bl1_plat_setup.c +++ b/plat/hisilicon/poplar/bl1_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,13 +23,6 @@ #include "hi3798cv200.h" #include "plat_private.h" -/* Symbols from link script for conherent section */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) - /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -92,8 +85,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, /* l-loader and BL1 ROM */ BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } void bl1_platform_setup(void) diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c index 177630b03..2671994a2 100644 --- a/plat/hisilicon/poplar/bl2_plat_setup.c +++ b/plat/hisilicon/poplar/bl2_plat_setup.c @@ -193,6 +193,9 @@ int poplar_bl2_handle_post_image_load(unsigned int image_id) } break; #endif + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/mediatek/common/custom/oem_svc.c b/plat/mediatek/common/custom/oem_svc.c index 08baed874..49e7571de 100644 --- a/plat/mediatek/common/custom/oem_svc.c +++ b/plat/mediatek/common/custom/oem_svc.c @@ -41,15 +41,8 @@ uint64_t oem_smc_handler(uint32_t smc_fid, void *handle, uint64_t flags) { - uint64_t rc; - - switch (smc_fid) { - default: - rc = SMC_UNK; - WARN("Unimplemented OEM Call: 0x%x\n", smc_fid); - } - - SMC_RET1(handle, rc); + WARN("Unimplemented OEM Call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); } /* diff --git a/plat/mediatek/common/mtk_sip_svc.c b/plat/mediatek/common/mtk_sip_svc.c index beb2a6978..869a95904 100644 --- a/plat/mediatek/common/mtk_sip_svc.c +++ b/plat/mediatek/common/mtk_sip_svc.c @@ -71,6 +71,9 @@ uint64_t mediatek_sip_handler(uint32_t smc_fid, boot_to_kernel(x1, x2, x3, x4); SMC_RET0(handle); #endif + default: + /* Do nothing in default case */ + break; } } diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c index 803f1ed85..32f015721 100644 --- a/plat/mediatek/mt6795/bl31_plat_setup.c +++ b/plat/mediatek/mt6795/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,22 +21,21 @@ #include <plat_private.h> #include <platform.h> #include <string.h> +#include <utils_def.h> #include <xlat_tables.h> + /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); +IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); /* * Placeholder variables for copying the arguments that have been passed to diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index 7b2930771..e51bdbb9e 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,24 +17,6 @@ #include <platform.h> #include <spm.h> -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted SRAM - ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - -/* - * The next 3 constants identify the extents of the code, RO data region and the - * limit of the BL31 image. These addresses are used by the MMU setup code and - * therefore they must be page-aligned. It is the responsibility of the linker - * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) -#define BL31_END (unsigned long)(&__BL31_END__) - static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; @@ -156,10 +138,10 @@ void bl31_plat_arch_setup(void) plat_cci_init(); plat_cci_enable(); - plat_configure_mmu_el3(BL31_RO_BASE, - BL_COHERENT_RAM_END - BL31_RO_BASE, - BL31_RO_BASE, - BL31_RO_LIMIT, + plat_configure_mmu_el3(BL_CODE_BASE, + BL_COHERENT_RAM_END - BL_CODE_BASE, + BL_CODE_BASE, + BL_CODE_END, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); } diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index d89ad7b94..2fe4e7dbc 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,6 +23,7 @@ #include <string.h> #include <tegra_def.h> #include <tegra_private.h> +#include <utils_def.h> /* length of Trusty's input parameters (in bytes) */ #define TRUSTY_PARAMS_LEN_BYTES (4096*2) @@ -33,29 +34,17 @@ extern void zeromem16(void *mem, unsigned int length); * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ -extern unsigned long __TEXT_START__; -extern unsigned long __TEXT_END__; -extern unsigned long __RW_START__; -extern unsigned long __RW_END__; -extern unsigned long __RODATA_START__; -extern unsigned long __RODATA_END__; -extern unsigned long __BL31_END__; + +IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); +IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); +IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE); +IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END); +IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START); +IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END); extern uint64_t tegra_bl31_phys_base; extern uint64_t tegra_console_base; -/* - * The next 3 constants identify the extents of the code, RO data region and the - * limit of the BL3-1 image. These addresses are used by the MMU setup code and - * therefore they must be page-aligned. It is the responsibility of the linker - * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_RW_START (unsigned long)(&__RW_START__) -#define BL31_RW_END (unsigned long)(&__RW_END__) -#define BL31_RODATA_BASE (unsigned long)(&__RODATA_START__) -#define BL31_RODATA_END (unsigned long)(&__RODATA_END__) -#define BL31_END (unsigned long)(&__BL31_END__) static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { @@ -311,8 +300,8 @@ void bl31_plat_arch_setup(void) unsigned long rw_size = BL31_RW_END - BL31_RW_START; unsigned long rodata_start = BL31_RODATA_BASE; unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; - unsigned long code_base = (unsigned long)(&__TEXT_START__); - unsigned long code_size = (unsigned long)(&__TEXT_END__) - code_base; + unsigned long code_base = TEXT_START; + unsigned long code_size = TEXT_END - TEXT_START; const mmap_region_t *plat_mmio_map = NULL; #if USE_COHERENT_MEM unsigned long coh_start, coh_size; diff --git a/plat/nvidia/tegra/soc/t186/plat_smmu.c b/plat/nvidia/tegra/soc/t186/plat_smmu.c index 4a8e1bee4..ead4c22b8 100644 --- a/plat/nvidia/tegra/soc/t186/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t186/plat_smmu.c @@ -1,23 +1,7 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: BSD-3-Clause */ #include <bl_common.h> diff --git a/plat/qemu/aarch64/plat_helpers.S b/plat/qemu/aarch64/plat_helpers.S index ed5537950..ca5eec62f 100644 --- a/plat/qemu/aarch64/plat_helpers.S +++ b/plat/qemu/aarch64/plat_helpers.S @@ -14,12 +14,13 @@ .globl platform_mem_init .globl plat_qemu_calc_core_pos .globl plat_crash_console_init +#if MULTI_CONSOLE_API .globl plat_crash_console_putc +#endif /* MULTI_CONSOLE_API */ .globl plat_secondary_cold_boot_setup .globl plat_get_my_entrypoint .globl plat_is_my_cpu_primary - func plat_my_core_pos mrs x0, mpidr_el1 b plat_qemu_calc_core_pos @@ -96,10 +97,7 @@ endfunc platform_mem_init * --------------------------------------------- */ func plat_crash_console_init - mov_imm x0, PLAT_QEMU_CRASH_UART_BASE - mov_imm x1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ - mov_imm x2, PLAT_QEMU_CONSOLE_BAUDRATE - b console_core_init + b qemu_crash_console_init endfunc plat_crash_console_init /* --------------------------------------------- @@ -109,9 +107,10 @@ endfunc plat_crash_console_init * Clobber list : x1, x2 * --------------------------------------------- */ +#if !MULTI_CONSOLE_API func plat_crash_console_putc mov_imm x1, PLAT_QEMU_CRASH_UART_BASE b console_core_putc endfunc plat_crash_console_putc - +#endif /* MULTI_CONSOLE_API */ diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h index f8764fbfe..2f2ca6f1e 100644 --- a/plat/qemu/include/platform_def.h +++ b/plat/qemu/include/platform_def.h @@ -75,7 +75,7 @@ #define NS_DRAM0_SIZE 0x3de00000 #define SEC_SRAM_BASE 0x0e000000 -#define SEC_SRAM_SIZE 0x00040000 +#define SEC_SRAM_SIZE 0x00060000 #define SEC_DRAM_BASE 0x0e100000 #define SEC_DRAM_SIZE 0x00f00000 @@ -123,7 +123,7 @@ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug * size plus a little space for growth. */ -#define BL2_BASE (BL31_BASE - 0x1D000) +#define BL2_BASE (BL31_BASE - 0x25000) #define BL2_LIMIT BL31_BASE /* diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk index 5bfd48afc..379ab3dca 100644 --- a/plat/qemu/platform.mk +++ b/plat/qemu/platform.mk @@ -47,8 +47,9 @@ $(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1)) $(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1)) -PLAT_BL_COMMON_SOURCES := plat/qemu/qemu_common.c \ - drivers/arm/pl011/${ARCH}/pl011_console.S +PLAT_BL_COMMON_SOURCES := plat/qemu/qemu_common.c \ + plat/qemu/qemu_console.c \ + drivers/arm/pl011/${ARCH}/pl011_console.S \ ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1) PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \ @@ -168,6 +169,16 @@ $(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2)) endif SEPARATE_CODE_AND_RODATA := 1 +ENABLE_STACK_PROTECTOR := 0 +ifneq ($(ENABLE_STACK_PROTECTOR), 0) + PLAT_BL_COMMON_SOURCES += plat/qemu/qemu_stack_protector.c +endif + +# Use MULTI_CONSOLE_API by default only on AArch64 +# as it is not yet supported on AArch32 +ifeq ($(ARCH),aarch64) +MULTI_CONSOLE_API := 1 +endif # Disable the PSCI platform compatibility layer ENABLE_PLAT_COMPAT := 0 diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c index 3f617e240..556aae593 100644 --- a/plat/qemu/qemu_bl1_setup.c +++ b/plat/qemu/qemu_bl1_setup.c @@ -8,7 +8,6 @@ #include <arch_helpers.h> #include <assert.h> #include <bl_common.h> -#include <console.h> #include <platform_def.h> #include "qemu_private.h" @@ -27,8 +26,7 @@ meminfo_t *bl1_plat_sec_mem_layout(void) void bl1_early_platform_setup(void) { /* Initialize the console to provide early debug support */ - console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ, - PLAT_QEMU_CONSOLE_BAUDRATE); + qemu_console_init(); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = BL_RAM_BASE; diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c index 987c6028c..997c85d7a 100644 --- a/plat/qemu/qemu_bl2_setup.c +++ b/plat/qemu/qemu_bl2_setup.c @@ -6,7 +6,6 @@ #include <arch_helpers.h> #include <assert.h> #include <bl_common.h> -#include <console.h> #include <debug.h> #include <desc_image_load.h> #include <optee_utils.h> @@ -123,8 +122,7 @@ struct entry_point_info *bl2_plat_get_bl31_ep_info(void) void bl2_early_platform_setup(meminfo_t *mem_layout) { /* Initialize the console to provide early debug support */ - console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ, - PLAT_QEMU_CONSOLE_BAUDRATE); + qemu_console_init(); /* Setup the BL2 memory layout */ bl2_tzram_layout = *mem_layout; @@ -289,6 +287,9 @@ static int qemu_bl2_handle_post_image_load(unsigned int image_id) bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry(); break; + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c index 6ded92959..1e8b2ecb6 100644 --- a/plat/qemu/qemu_bl31_setup.c +++ b/plat/qemu/qemu_bl31_setup.c @@ -6,7 +6,6 @@ #include <assert.h> #include <bl_common.h> -#include <console.h> #include <gic_common.h> #include <gicv2.h> #include <platform_def.h> @@ -45,8 +44,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, #endif { /* Initialize the console to provide early debug support */ - console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ, - PLAT_QEMU_CONSOLE_BAUDRATE); + qemu_console_init(); #if LOAD_IMAGE_V2 /* diff --git a/plat/qemu/qemu_console.c b/plat/qemu/qemu_console.c new file mode 100644 index 000000000..1cf84aa78 --- /dev/null +++ b/plat/qemu/qemu_console.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <console.h> +#include <pl011.h> +#include <platform_def.h> + +#if MULTI_CONSOLE_API +static console_pl011_t console; +static console_pl011_t crash_console; +#endif /* MULTI_CONSOLE_API */ + +void qemu_console_init(void) +{ +#if MULTI_CONSOLE_API + (void)console_pl011_register(PLAT_QEMU_BOOT_UART_BASE, + PLAT_QEMU_BOOT_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE, &console); +#else + console_init(PLAT_QEMU_BOOT_UART_BASE, + PLAT_QEMU_BOOT_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE); +#endif /* MULTI_CONSOLE_API */ +} + +void qemu_crash_console_init(void) +{ +#if MULTI_CONSOLE_API + (void)console_pl011_register(PLAT_QEMU_CRASH_UART_BASE, + PLAT_QEMU_CRASH_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE, &crash_console); +#else + console_core_init(PLAT_QEMU_CRASH_UART_BASE, + PLAT_QEMU_CRASH_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE); +#endif /* MULTI_CONSOLE_API */ +} diff --git a/plat/qemu/qemu_private.h b/plat/qemu/qemu_private.h index 716440fb7..c66d0f9cd 100644 --- a/plat/qemu/qemu_private.h +++ b/plat/qemu/qemu_private.h @@ -34,4 +34,7 @@ unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); int dt_add_psci_node(void *fdt); int dt_add_psci_cpu_enable_methods(void *fdt); +void qemu_console_init(void); +void qemu_crash_console_init(void); + #endif /*__QEMU_PRIVATE_H*/ diff --git a/plat/qemu/qemu_stack_protector.c b/plat/qemu/qemu_stack_protector.c new file mode 100644 index 000000000..5b1982833 --- /dev/null +++ b/plat/qemu/qemu_stack_protector.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <platform.h> +#include <stdint.h> + +#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL) + +u_register_t plat_get_stack_protector_canary(void) +{ + /* + * Ideally, a random number should be returned instead of the + * combination of a timer's value and a compile-time constant. + * As the virt platform does not have any random number generator, + * this is better than nothing but not necessarily really secure. + */ + return RANDOM_CANARY_VALUE ^ read_cntpct_el0(); +} + diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index 6199edae2..e5ee68f14 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,21 +17,14 @@ #include <platform_def.h> #include <uart_16550.h> -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted SRAM - ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); +IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; diff --git a/plat/rockchip/common/rockchip_sip_svc.c b/plat/rockchip/common/rockchip_sip_svc.c index 40cc94b7d..eca4f99ac 100644 --- a/plat/rockchip/common/rockchip_sip_svc.c +++ b/plat/rockchip/common/rockchip_sip_svc.c @@ -59,13 +59,11 @@ uint64_t sip_smc_handler(uint32_t smc_fid, case SIP_SVC_UID: /* Return UID to the caller */ SMC_UUID_RET(handle, rk_sip_svc_uid); - break; case SIP_SVC_VERSION: /* Return the version of current implementation */ SMC_RET2(handle, RK_SIP_SVC_VERSION_MAJOR, RK_SIP_SVC_VERSION_MINOR); - break; default: return rockchip_plat_sip_handler(smc_fid, x1, x2, x3, x4, diff --git a/plat/rockchip/rk3368/plat_sip_calls.c b/plat/rockchip/rk3368/plat_sip_calls.c index 7383d2f20..03fee88cb 100644 --- a/plat/rockchip/rk3368/plat_sip_calls.c +++ b/plat/rockchip/rk3368/plat_sip_calls.c @@ -19,9 +19,6 @@ uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags) { - switch (smc_fid) { - default: - ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); - SMC_RET1(handle, SMC_UNK); - } + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + SMC_RET1(handle, SMC_UNK); } diff --git a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c index d0e598610..f1a5e2b7a 100644 --- a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c +++ b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <cdn_dp.h> -#include <smcc.h> +#include <smccc.h> #include <stdlib.h> #include <string.h> diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c index d629e4bfb..70d9423b3 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.c +++ b/plat/rockchip/rk3399/drivers/dram/dfs.c @@ -207,6 +207,9 @@ static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, ptiming_config->rdbi = 0; ptiming_config->wdbi = 0; break; + default: + /* Do nothing in default case */ + break; } ptiming_config->dramds = drv_config->dram_side_drv; ptiming_config->dramodt = drv_config->dram_side_dq_odt; diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c index 2e196b54c..3527f0e5e 100644 --- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c +++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c @@ -1314,5 +1314,8 @@ void dram_get_parameter(struct timing_related_config *timing_config, case LPDDR4: lpddr4_get_parameter(timing_config, pdram_timing); break; + default: + /* Do nothing in default case */ + break; } } diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index f4893efe8..ed1ea8b63 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -310,6 +310,7 @@ static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) pmu_bus_idle_req(BUS_ID_PERIHP, state); break; default: + /* Do nothing in default case */ break; } @@ -647,12 +648,8 @@ int rockchip_soc_cores_pwr_dm_off(void) int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, plat_local_state_t lvl_state) { - switch (lvl) { - case MPIDR_AFFLVL1: + if (lvl == MPIDR_AFFLVL1) { clst_pwr_domain_suspend(lvl_state); - break; - default: - break; } return PSCI_E_SUCCESS; @@ -675,12 +672,8 @@ int rockchip_soc_cores_pwr_dm_suspend(void) int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state) { - switch (lvl) { - case MPIDR_AFFLVL1: + if (lvl == MPIDR_AFFLVL1) { clst_pwr_domain_suspend(lvl_state); - break; - default: - break; } return PSCI_E_SUCCESS; @@ -698,12 +691,8 @@ int rockchip_soc_cores_pwr_dm_on_finish(void) int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, plat_local_state_t lvl_state) { - switch (lvl) { - case MPIDR_AFFLVL1: + if (lvl == MPIDR_AFFLVL1) { clst_pwr_domain_resume(lvl_state); - break; - default: - break; } return PSCI_E_SUCCESS; @@ -721,11 +710,8 @@ int rockchip_soc_cores_pwr_dm_resume(void) int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state) { - switch (lvl) { - case MPIDR_AFFLVL1: + if (lvl == MPIDR_AFFLVL1) { clst_pwr_domain_resume(lvl_state); - default: - break; } return PSCI_E_SUCCESS; @@ -1319,10 +1305,14 @@ void wdt_register_restore(void) { int i; - for (i = 0; i < 2; i++) { + for (i = 1; i >= 0; i--) { mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]); mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]); } + + /* write 0x76 to cnt_restart to keep watchdog alive */ + mmio_write_32(WDT0_BASE + 0x0c, 0x76); + mmio_write_32(WDT1_BASE + 0x0c, 0x76); } int rockchip_soc_sys_pwr_dm_suspend(void) @@ -1383,6 +1373,7 @@ int rockchip_soc_sys_pwr_dm_suspend(void) } mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN)); + wdt_register_save(); secure_watchdog_disable(); /* @@ -1398,7 +1389,6 @@ int rockchip_soc_sys_pwr_dm_suspend(void) suspend_uart(); grf_register_save(); cru_register_save(); - wdt_register_save(); sram_save(); plat_rockchip_save_gpio(); @@ -1411,7 +1401,6 @@ int rockchip_soc_sys_pwr_dm_resume(void) uint32_t status = 0; plat_rockchip_restore_gpio(); - wdt_register_restore(); cru_register_restore(); grf_register_restore(); resume_uart(); @@ -1426,6 +1415,7 @@ int rockchip_soc_sys_pwr_dm_resume(void) secure_watchdog_enable(); secure_sgrf_init(); secure_sgrf_ddr_rgn_init(); + wdt_register_restore(); /* restore clk_ddrc_bpll_src_en gate */ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), diff --git a/plat/rpi3/aarch64/plat_helpers.S b/plat/rpi3/aarch64/plat_helpers.S index 76a542f5c..65c1bf2d4 100644 --- a/plat/rpi3/aarch64/plat_helpers.S +++ b/plat/rpi3/aarch64/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -137,7 +137,7 @@ func plat_crash_console_init mov_imm x0, PLAT_RPI3_UART_BASE mov_imm x1, PLAT_RPI3_UART_CLK_IN_HZ mov_imm x2, PLAT_RPI3_UART_BAUDRATE - b console_core_init + b console_16550_core_init endfunc plat_crash_console_init /* --------------------------------------------- @@ -149,7 +149,7 @@ endfunc plat_crash_console_init */ func plat_crash_console_putc mov_imm x1, PLAT_RPI3_UART_BASE - b console_core_putc + b console_16550_core_putc endfunc plat_crash_console_putc /* --------------------------------------------- @@ -161,8 +161,8 @@ endfunc plat_crash_console_putc * --------------------------------------------- */ func plat_crash_console_flush - mov_imm x1, PLAT_RPI3_UART_BASE - b console_core_flush + mov_imm x0, PLAT_RPI3_UART_BASE + b console_16550_core_flush endfunc plat_crash_console_flush /* --------------------------------------------- diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk index e201ceed0..2cb7a1520 100644 --- a/plat/rpi3/platform.mk +++ b/plat/rpi3/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -81,6 +81,9 @@ USE_COHERENT_MEM := 1 # Enable new version of image loading LOAD_IMAGE_V2 := 1 +# Use multi console API +MULTI_CONSOLE_API := 1 + # Platform build flags # -------------------- @@ -110,6 +113,10 @@ ifneq (${LOAD_IMAGE_V2}, 1) $(error Error: rpi3 needs LOAD_IMAGE_V2=1) endif +ifneq (${MULTI_CONSOLE_API}, 1) + $(error Error: rpi3 needs MULTI_CONSOLE_API=1) +endif + ifeq (${ARCH},aarch32) $(error Error: AArch32 not supported on rpi3) endif diff --git a/plat/rpi3/rpi3_bl1_setup.c b/plat/rpi3/rpi3_bl1_setup.c index 11c0f4af3..c98715b9a 100644 --- a/plat/rpi3/rpi3_bl1_setup.c +++ b/plat/rpi3/rpi3_bl1_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,6 @@ #include <arch.h> #include <arch_helpers.h> #include <bl_common.h> -#include <console.h> #include <platform_def.h> #include <xlat_mmu_helpers.h> #include <xlat_tables_defs.h> @@ -29,8 +28,7 @@ meminfo_t *bl1_plat_sec_mem_layout(void) void bl1_early_platform_setup(void) { /* Initialize the console to provide early debug support */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); + rpi3_console_init(); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = BL_RAM_BASE; diff --git a/plat/rpi3/rpi3_bl2_setup.c b/plat/rpi3/rpi3_bl2_setup.c index 1fd822e9a..f286caf03 100644 --- a/plat/rpi3/rpi3_bl2_setup.c +++ b/plat/rpi3/rpi3_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,6 @@ #include <arch_helpers.h> #include <assert.h> #include <bl_common.h> -#include <console.h> #include <debug.h> #include <desc_image_load.h> #include <platform_def.h> @@ -27,8 +26,7 @@ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); void bl2_early_platform_setup(meminfo_t *mem_layout) { /* Initialize the console to provide early debug support */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); + rpi3_console_init(); /* Setup the BL2 memory layout */ bl2_tzram_layout = *mem_layout; @@ -40,7 +38,7 @@ void bl2_platform_setup(void) { /* * This is where a TrustZone address space controller and other - * security related peripherals, would be configured. + * security related peripherals would be configured. */ } @@ -83,6 +81,9 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry(); break; + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/rpi3/rpi3_bl31_setup.c b/plat/rpi3/rpi3_bl31_setup.c index 391335643..58344ae99 100644 --- a/plat/rpi3/rpi3_bl31_setup.c +++ b/plat/rpi3/rpi3_bl31_setup.c @@ -1,12 +1,11 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> #include <bl_common.h> -#include <console.h> #include <platform.h> #include <platform_def.h> #include <xlat_mmu_helpers.h> @@ -58,8 +57,7 @@ void bl31_early_platform_setup(void *from_bl2, void *plat_params_from_bl2) { /* Initialize the console to provide early debug support */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); + rpi3_console_init(); #if RESET_TO_BL31 @@ -159,10 +157,3 @@ void bl31_platform_setup(void) return; } - -void bl31_plat_runtime_setup(void) -{ - /* Initialize the runtime console */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); -} diff --git a/plat/rpi3/rpi3_common.c b/plat/rpi3/rpi3_common.c index 97dce0913..03914a6d7 100644 --- a/plat/rpi3/rpi3_common.c +++ b/plat/rpi3/rpi3_common.c @@ -1,14 +1,16 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch_helpers.h> #include <bl_common.h> +#include <console.h> #include <debug.h> #include <interrupt_mgmt.h> #include <platform_def.h> +#include <uart_16550.h> #include <xlat_tables_v2.h> #include "rpi3_hw.h" @@ -69,6 +71,30 @@ static const mmap_region_t plat_rpi3_mmap[] = { #endif /******************************************************************************* + * Function that sets up the console + ******************************************************************************/ +static console_16550_t rpi3_console; + +void rpi3_console_init(void) +{ + int rc = console_16550_register(PLAT_RPI3_UART_BASE, + PLAT_RPI3_UART_CLK_IN_HZ, + PLAT_RPI3_UART_BAUDRATE, + &rpi3_console); + if (rc == 0) { + /* + * The crash console doesn't use the multi console API, it uses + * the core console functions directly. It is safe to call panic + * and let it print debug information. + */ + panic(); + } + + console_set_scope(&rpi3_console.console, + CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); +} + +/******************************************************************************* * Function that sets up the translation tables. ******************************************************************************/ void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, diff --git a/plat/rpi3/rpi3_private.h b/plat/rpi3/rpi3_private.h index 01c4055f5..a9fbfe479 100644 --- a/plat/rpi3/rpi3_private.h +++ b/plat/rpi3/rpi3_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,7 @@ ******************************************************************************/ /* Utility functions */ +void rpi3_console_init(void); void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, uintptr_t code_start, uintptr_t code_limit, uintptr_t rodata_start, uintptr_t rodata_limit diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c index 54b30e5b1..f7ae42646 100644 --- a/plat/socionext/uniphier/uniphier_bl2_setup.c +++ b/plat/socionext/uniphier/uniphier_bl2_setup.c @@ -85,6 +85,7 @@ void bl2_el3_plat_arch_setup(void) break; default: plat_error_handler(-ENOTSUP); + break; } if (!skip_scp) { diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c index d7a7d4e2e..fd054beb9 100644 --- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c +++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -48,6 +48,9 @@ unsigned int zynqmp_get_uart_clk(void) return 25000000; case ZYNQMP_CSU_VERSION_QEMU: return 133000000; + default: + /* Do nothing in default case */ + break; } return 100000000; @@ -187,6 +190,9 @@ static void zynqmp_print_platform_name(void) case ZYNQMP_CSU_VERSION_SILICON: label = "silicon"; break; + default: + /* Do nothing in default case */ + break; } NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x%s\n", @@ -258,6 +264,9 @@ unsigned int plat_get_syscnt_freq2(void) return 4000000; case ZYNQMP_CSU_VERSION_QEMU: return 50000000; + default: + /* Do nothing in default case */ + break; } return mmio_read_32(IOU_SCNTRS_BASEFREQ); |