diff options
Diffstat (limited to 'plat/intel')
5 files changed, 12 insertions, 22 deletions
diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h index 381c2d355..be2953664 100644 --- a/plat/intel/soc/agilex/include/agilex_system_manager.h +++ b/plat/intel/soc/agilex/include/agilex_system_manager.h @@ -73,7 +73,6 @@ #define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 #define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) -void enable_nonsecure_access(void); void enable_ns_bridge_access(void); #endif diff --git a/plat/intel/soc/agilex/soc/agilex_memory_controller.c b/plat/intel/soc/agilex/soc/agilex_memory_controller.c index 5f3cae7be..2aabe87cc 100644 --- a/plat/intel/soc/agilex/soc/agilex_memory_controller.c +++ b/plat/intel/soc/agilex/soc/agilex_memory_controller.c @@ -20,9 +20,8 @@ #define PRE_CALIBRATION_DELAY 1 #define POST_CALIBRATION_DELAY 1 #define TIMEOUT_EMIF_CALIBRATION 1000 -#define CLEAR_EMIF_DELAY 50000 -#define CLEAR_EMIF_TIMEOUT 0x100000 -#define TIMEOUT_INT_RESP 10000 +#define CLEAR_EMIF_DELAY 1000 +#define CLEAR_EMIF_TIMEOUT 1000 #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) #define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t)) @@ -125,7 +124,7 @@ static int mem_calibration(void) data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRCALSTAT); if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1) break; - mdelay(1); + udelay(500); } while (++timeout < TIMEOUT_EMIF_CALIBRATION); if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c index d7cd71bec..cecf56088 100644 --- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c +++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c @@ -688,10 +688,7 @@ int cad_qspi_read(void *buffer, uint32_t offset, uint32_t size) if ((offset >= qspi_device_size) || (offset + size - 1 >= qspi_device_size) || - (size == 0) || - ((long) ((int *)buffer) & 0x3) || - (offset & 0x3) || - (size & 0x3)) { + (size == 0)) { ERROR("Invalid read parameter\n"); return -1; } @@ -766,11 +763,9 @@ int cad_qspi_write(void *buffer, uint32_t offset, uint32_t size) if ((offset >= qspi_device_size) || (offset + size - 1 >= qspi_device_size) || - (size == 0) || - ((long)buffer & 0x3) || - (offset & 0x3) || - (size & 0x3)) + (size == 0)) { return -2; + } if (CAD_QSPI_INDWR_RDSTAT(mmio_read_32(CAD_QSPI_OFFSET + CAD_QSPI_INDWR))) { diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h index a67d689fa..4abfedb56 100644 --- a/plat/intel/soc/stratix10/include/s10_system_manager.h +++ b/plat/intel/soc/stratix10/include/s10_system_manager.h @@ -69,5 +69,3 @@ #define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) -void enable_nonsecure_access(void); - diff --git a/plat/intel/soc/stratix10/soc/s10_memory_controller.c b/plat/intel/soc/stratix10/soc/s10_memory_controller.c index ed06f5498..cb4525149 100644 --- a/plat/intel/soc/stratix10/soc/s10_memory_controller.c +++ b/plat/intel/soc/stratix10/soc/s10_memory_controller.c @@ -22,10 +22,9 @@ #define MAX_MEM_CAL_RETRY 3 #define PRE_CALIBRATION_DELAY 1 #define POST_CALIBRATION_DELAY 1 -#define TIMEOUT_EMIF_CALIBRATION 100 -#define CLEAR_EMIF_DELAY 50000 -#define CLEAR_EMIF_TIMEOUT 0x100000 -#define TIMEOUT_INT_RESP 10000 +#define TIMEOUT_EMIF_CALIBRATION 1000 +#define CLEAR_EMIF_DELAY 1000 +#define CLEAR_EMIF_TIMEOUT 1000 #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) #define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t)) @@ -128,13 +127,13 @@ static int mem_calibration(void) data = mmio_read_32(S10_MPFE_HMC_ADP_DDRCALSTAT); if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1) break; - udelay(1); + udelay(500); } while (++timeout < TIMEOUT_EMIF_CALIBRATION); if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { status = clear_emif(); - if (status) - ERROR("Failed to clear Emif\n"); + if (status) + ERROR("Failed to clear Emif\n"); } else { break; } |