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-rw-r--r--lib/cpus/aarch64/neoverse_n1.S12
-rw-r--r--lib/stack_protector/stack_protector.mk4
2 files changed, 8 insertions, 8 deletions
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index c9bb005e3..faf53a848 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -21,9 +21,7 @@
#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-#if ERRATA_N1_IC_TRAP
.global neoverse_n1_errata_ic_trap_handler
-#endif
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Erratum 1043202.
@@ -356,7 +354,7 @@ func errata_n1_1542419_wa
bl check_errata_1542419
cbz x0, 1f
- /* Apply instruction patching sequence */
+ /* Apply instruction patching sequence */
ldr x0, =0x0
msr CPUPSELR_EL3, x0
ldr x0, =0xEE670D35
@@ -536,10 +534,10 @@ func neoverse_n1_errata_ic_trap_handler
tlbi vae3is, xzr
dsb sy
- # Skip the IC instruction itself
- mrs x3, elr_el3
- add x3, x3, #4
- msr elr_el3, x3
+ # Skip the IC instruction itself
+ mrs x3, elr_el3
+ add x3, x3, #4
+ msr elr_el3, x3
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
diff --git a/lib/stack_protector/stack_protector.mk b/lib/stack_protector/stack_protector.mk
index 94e804be9..b5aba1528 100644
--- a/lib/stack_protector/stack_protector.mk
+++ b/lib/stack_protector/stack_protector.mk
@@ -11,7 +11,9 @@ ifeq (${ENABLE_STACK_PROTECTOR},0)
ENABLE_STACK_PROTECTOR := none
endif
-ifneq (${ENABLE_STACK_PROTECTOR},none)
+ifeq (${ENABLE_STACK_PROTECTOR},none)
+ TF_CFLAGS += -fno-stack-protector
+else
STACK_PROTECTOR_ENABLED := 1
BL_COMMON_SOURCES += lib/stack_protector/stack_protector.c \
lib/stack_protector/${ARCH}/asm_stack_protector.S