diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a55.S | 5 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a75.S | 5 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a76.S | 5 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a76ae.S | 5 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_deimos.S | 7 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_e1.S | 5 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_n1.S | 5 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_zeus.S | 5 |
8 files changed, 41 insertions, 1 deletions
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S index b9a3f3653..0ef373a0a 100644 --- a/lib/cpus/aarch64/cortex_a55.S +++ b/lib/cpus/aarch64/cortex_a55.S @@ -11,6 +11,11 @@ #include <cpu_macros.S> #include <plat_macros.S> +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + /* -------------------------------------------------- * Errata Workaround for Cortex A55 Errata #768277. * This applies only to revision r0p0 of Cortex A55. diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index fda1aecbe..657457ee1 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S @@ -10,6 +10,11 @@ #include <cpuamu.h> #include <cpu_macros.S> +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + /* -------------------------------------------------- * Errata Workaround for Cortex A75 Errata #764081. * This applies only to revision r0p0 of Cortex A75. diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index aed7970ed..b48283cbb 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -13,6 +13,11 @@ #include <plat_macros.S> #include <services/arm_arch_svc.h> +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex-A76 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + #define ESR_EL3_A64_SMC0 0x5e000000 #define ESR_EL3_A32_SMC0 0x4e000000 diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S index 1ba8e9a7d..46e9450f2 100644 --- a/lib/cpus/aarch64/cortex_a76ae.S +++ b/lib/cpus/aarch64/cortex_a76ae.S @@ -8,6 +8,11 @@ #include <cortex_a76ae.h> #include <cpu_macros.S> +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_deimos.S b/lib/cpus/aarch64/cortex_deimos.S index 0e72fba5a..e73e89f73 100644 --- a/lib/cpus/aarch64/cortex_deimos.S +++ b/lib/cpus/aarch64/cortex_deimos.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,11 @@ #include <cpu_macros.S> #include <plat_macros.S> +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Deimos must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S index 8e403062f..71e7b5171 100644 --- a/lib/cpus/aarch64/neoverse_e1.S +++ b/lib/cpus/aarch64/neoverse_e1.S @@ -11,6 +11,11 @@ #include <cpu_macros.S> #include <plat_macros.S> +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + func neoverse_e1_cpu_pwr_dwn mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index ce63899a7..2038f318b 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -10,6 +10,11 @@ #include <cpuamu.h> #include <cpu_macros.S> +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Errata * This applies to revision r0p0 and r1p0 of Neoverse N1. diff --git a/lib/cpus/aarch64/neoverse_zeus.S b/lib/cpus/aarch64/neoverse_zeus.S index 79c8b2fdf..c5241afab 100644 --- a/lib/cpus/aarch64/neoverse_zeus.S +++ b/lib/cpus/aarch64/neoverse_zeus.S @@ -11,6 +11,11 @@ #include <cpu_macros.S> #include <plat_macros.S> +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Neoverse Zeus must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- |