diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/arch/aarch32/asm_macros.S | 29 | ||||
| -rw-r--r-- | include/arch/aarch32/el3_common_macros.S | 2 | ||||
| -rw-r--r-- | include/drivers/st/stm32mp1_clk.h | 1 | ||||
| -rw-r--r-- | include/drivers/st/stm32mp1_rcc.h | 4 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_ares.h | 35 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cpu_macros.S | 22 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_e1.h (renamed from include/lib/cpus/aarch64/cortex_helios.h) | 16 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 35 | ||||
| -rw-r--r-- | include/lib/xlat_tables/xlat_tables_defs.h | 6 | ||||
| -rw-r--r-- | include/plat/arm/board/common/board_css_def.h | 8 |
10 files changed, 104 insertions, 54 deletions
diff --git a/include/arch/aarch32/asm_macros.S b/include/arch/aarch32/asm_macros.S index 8408804fb..8cfa21231 100644 --- a/include/arch/aarch32/asm_macros.S +++ b/include/arch/aarch32/asm_macros.S @@ -78,7 +78,7 @@ * Clobber: r14, r1, r2 */ .macro get_my_mp_stack _name, _size - bl plat_my_core_pos + bl plat_my_core_pos ldr r2, =(\_name + \_size) mov r1, #\_size mla r0, r0, r1, r2 @@ -189,4 +189,31 @@ .endif .endm + /* + * Helper macro for carrying out division in software when + * hardware division is not suported. \top holds the dividend + * in the function call and the remainder after + * the function is executed. \bot holds the divisor. \div holds + * the quotient and \temp is a temporary registed used in calcualtion. + * The division algorithm has been obtained from: + * http://www.keil.com/support/man/docs/armasm/armasm_dom1359731155623.htm + */ + .macro softudiv div:req,top:req,bot:req,temp:req + + mov \temp, \bot + cmp \temp, \top, lsr #1 +div1: + movls \temp, \temp, lsl #1 + cmp \temp, \top, lsr #1 + bls div1 + mov \div, #0 + +div2: + cmp \top, \temp + subcs \top, \top,\temp + ADC \div, \div, \div + mov \temp, \temp, lsr #1 + cmp \temp, \bot + bhs div2 + .endm #endif /* ASM_MACROS_S */ diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index ab9ba6ed5..322aed5cd 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -94,9 +94,11 @@ * from all exception levels. * --------------------------------------------------------------------- */ +#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP) ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT) vmsr FPEXC, r0 isb +#endif #if (ARM_ARCH_MAJOR > 7) /* --------------------------------------------------------------------- diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h index 1e0d949ac..7afa5ad84 100644 --- a/include/drivers/st/stm32mp1_clk.h +++ b/include/drivers/st/stm32mp1_clk.h @@ -13,6 +13,7 @@ int stm32mp1_clk_probe(void); int stm32mp1_clk_init(void); bool stm32mp1_rcc_is_secure(void); +bool stm32mp1_rcc_is_mckprot(void); void __stm32mp1_clk_enable(unsigned long id, bool caller_is_secure); void __stm32mp1_clk_disable(unsigned long id, bool caller_is_secure); diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h index 1922c4815..eaa853da3 100644 --- a/include/drivers/st/stm32mp1_rcc.h +++ b/include/drivers/st/stm32mp1_rcc.h @@ -111,6 +111,7 @@ #define RCC_RCK4SELR U(0x824) #define RCC_TIMG1PRER U(0x828) #define RCC_TIMG2PRER U(0x82C) +#define RCC_MCUDIVR U(0x830) #define RCC_APB1DIVR U(0x834) #define RCC_APB2DIVR U(0x838) #define RCC_APB3DIVR U(0x83C) @@ -237,6 +238,7 @@ /* Values for RCC_TZCR register */ #define RCC_TZCR_TZEN BIT(0) +#define RCC_TZCR_MCKPROT BIT(1) /* Used for most of RCC_<x>SELR registers */ #define RCC_SELR_SRC_MASK GENMASK(2, 0) @@ -273,6 +275,7 @@ #define RCC_APBXDIV_MASK GENMASK(2, 0) #define RCC_MPUDIV_MASK GENMASK(2, 0) #define RCC_AXIDIV_MASK GENMASK(2, 0) +#define RCC_MCUDIV_MASK GENMASK(3, 0) /* Used for TIMER Prescaler */ #define RCC_TIMGXPRER_TIMGXPRE BIT(0) @@ -421,6 +424,7 @@ /* Global Reset Register */ #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) +#define RCC_MP_GRSTCSETR_MCURST BIT(1) #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) #define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) diff --git a/include/lib/cpus/aarch64/cortex_ares.h b/include/lib/cpus/aarch64/cortex_ares.h deleted file mode 100644 index cfc36e473..000000000 --- a/include/lib/cpus/aarch64/cortex_ares.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_ARES_H -#define CORTEX_ARES_H - -#include <lib/utils_def.h> - -/* Cortex-ARES MIDR for revision 0 */ -#define CORTEX_ARES_MIDR U(0x410fd0c0) - -/******************************************************************************* - * CPU Extended Control register specific definitions. - ******************************************************************************/ -#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 - -/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ -#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1) - -#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) - -#define CORTEX_ARES_AMU_NR_COUNTERS U(5) -#define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f) - -/* Instruction patching registers */ -#define CPUPSELR_EL3 S3_6_C15_C8_0 -#define CPUPCR_EL3 S3_6_C15_C8_1 -#define CPUPOR_EL3 S3_6_C15_C8_2 -#define CPUPMR_EL3 S3_6_C15_C8_3 - -#endif /* CORTEX_ARES_H */ diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index b907668b3..044aacaf4 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #define CPU_MACROS_S #include <arch.h> +#include <assert_macros.S> #include <lib/cpus/errata_report.h> #define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ @@ -263,11 +264,22 @@ mrs \_reg, id_aa64pfr0_el1 ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH /* - * If the field equals to 1 then branch targets trained in one - * context cannot affect speculative execution in a different context. + * If the field equals 1, branch targets trained in one context cannot + * affect speculative execution in a different context. + * + * If the field equals 2, it means that the system is also aware of + * SCXTNUM_ELx register contexts. We aren't using them in the TF, so we + * expect users of the registers to do the right thing. + * + * Only apply mitigations if the value of this field is 0. */ - cmp \_reg, #1 - beq \_label +#if ENABLE_ASSERTIONS + cmp \_reg, #3 /* Only values 0 to 2 are expected */ + ASM_ASSERT(lo) +#endif + + cmp \_reg, #0 + bne \_label .endm /* diff --git a/include/lib/cpus/aarch64/cortex_helios.h b/include/lib/cpus/aarch64/neoverse_e1.h index 0c11a9a4c..708460480 100644 --- a/include/lib/cpus/aarch64/cortex_helios.h +++ b/include/lib/cpus/aarch64/neoverse_e1.h @@ -4,28 +4,28 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_HELIOS_H -#define CORTEX_HELIOS_H +#ifndef NEOVERSE_E1_H +#define NEOVERSE_E1_H #include <lib/utils_def.h> -#define CORTEX_HELIOS_MIDR U(0x410FD060) +#define NEOVERSE_E1_MIDR U(0x410FD060) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 +#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0 /******************************************************************************* * CPU Power Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) +#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) -#endif /* CORTEX_HELIOS_H */ +#endif /* NEOVERSE_E1_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h new file mode 100644 index 000000000..908993e45 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_N1_H +#define NEOVERSE_N1_H + +#include <lib/utils_def.h> + +/* Neoverse N1 MIDR for revision 0 */ +#define NEOVERSE_N1_MIDR U(0x410fd0c0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ +#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) + +#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) + +#define NEOVERSE_N1_AMU_NR_COUNTERS U(5) +#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) + +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* NEOVERSE_N1_H */ diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h index 6d0fb7896..f9bbe0f60 100644 --- a/include/lib/xlat_tables/xlat_tables_defs.h +++ b/include/lib/xlat_tables/xlat_tables_defs.h @@ -73,7 +73,11 @@ #define PAGE_SIZE_MASK (PAGE_SIZE - U(1)) #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0)) -#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes (1 << 3) */ +#if (ARM_ARCH_MAJOR == 7) && !ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING +#define XLAT_ENTRY_SIZE_SHIFT U(2) /* Each MMU table entry is 4 bytes */ +#else +#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes */ +#endif #define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT) #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h index a77ea96ef..452afbcc8 100644 --- a/include/plat/arm/board/common/board_css_def.h +++ b/include/plat/arm/board/common/board_css_def.h @@ -61,14 +61,14 @@ #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ -#define PLAT_ARM_BL31_RUN_UART_BASE SOC_CSS_UART1_BASE -#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ +#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE +#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ #define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ -#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE -#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |