diff options
Diffstat (limited to 'include')
32 files changed, 385 insertions, 121 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 3421e042d..44044d403 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -71,7 +71,11 @@ /* Data Cache set/way op type defines */ #define DC_OP_ISW U(0x0) #define DC_OP_CISW U(0x1) +#if ERRATA_A53_827319 +#define DC_OP_CSW DC_OP_CISW +#else #define DC_OP_CSW U(0x2) +#endif /******************************************************************************* * Generic timer memory mapped registers & offsets @@ -153,6 +157,7 @@ #define SDCR_SPD_LEGACY U(0x0) #define SDCR_SPD_DISABLE U(0x2) #define SDCR_SPD_ENABLE U(0x3) +#define SDCR_SCCD_BIT (U(1) << 23) #define SDCR_RESET_VAL U(0x0) /* HSCTLR definitions */ diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h index 64ddc86fe..cbac84b93 100644 --- a/include/arch/aarch32/arch_helpers.h +++ b/include/arch/aarch32/arch_helpers.h @@ -328,7 +328,11 @@ DEFINE_BPIOP_FUNC(allis, BPIALLIS) */ DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC) DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC) +#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 +DEFINE_DCOP_PARAM_FUNC(cvac, DCCIMVAC) +#else DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC) +#endif /* Previously defined accessor functions with incomplete register names */ #define dsb() dsbsy() diff --git a/include/arch/aarch32/asm_macros.S b/include/arch/aarch32/asm_macros.S index 8408804fb..8cfa21231 100644 --- a/include/arch/aarch32/asm_macros.S +++ b/include/arch/aarch32/asm_macros.S @@ -78,7 +78,7 @@ * Clobber: r14, r1, r2 */ .macro get_my_mp_stack _name, _size - bl plat_my_core_pos + bl plat_my_core_pos ldr r2, =(\_name + \_size) mov r1, #\_size mla r0, r0, r1, r2 @@ -189,4 +189,31 @@ .endif .endm + /* + * Helper macro for carrying out division in software when + * hardware division is not suported. \top holds the dividend + * in the function call and the remainder after + * the function is executed. \bot holds the divisor. \div holds + * the quotient and \temp is a temporary registed used in calcualtion. + * The division algorithm has been obtained from: + * http://www.keil.com/support/man/docs/armasm/armasm_dom1359731155623.htm + */ + .macro softudiv div:req,top:req,bot:req,temp:req + + mov \temp, \bot + cmp \temp, \top, lsr #1 +div1: + movls \temp, \temp, lsl #1 + cmp \temp, \top, lsr #1 + bls div1 + mov \div, #0 + +div2: + cmp \top, \temp + subcs \top, \top,\temp + ADC \div, \div, \div + mov \temp, \temp, lsr #1 + cmp \temp, \bot + bhs div2 + .endm #endif /* ASM_MACROS_S */ diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 048f16103..322aed5cd 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -94,19 +94,26 @@ * from all exception levels. * --------------------------------------------------------------------- */ +#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP) ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT) vmsr FPEXC, r0 isb +#endif #if (ARM_ARCH_MAJOR > 7) /* --------------------------------------------------------------------- * Initialise SDCR, setting all the fields rather than relying on hw. * * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from - * Secure EL1 are disabled. + * Secure EL1 are disabled. + * + * SDCR: Set to one so that cycle counting by PMCCNTR is prohibited in + * Secure state. This bit is RES0 in versions of the architecture + * earlier than ARMv8.5, setting it to 1 doesn't have any effect on + * them. * --------------------------------------------------------------------- */ - ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE)) + ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE) | SDCR_SCCD_BIT) stcopr r0, SDCR #endif diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 76c3e277b..debe8722c 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -119,7 +119,11 @@ /* Data cache set/way op type defines */ #define DCISW U(0x0) #define DCCISW U(0x1) +#if ERRATA_A53_827319 +#define DCCSW DCCISW +#else #define DCCSW U(0x2) +#endif /* ID_AA64PFR0_EL1 definitions */ #define ID_AA64PFR0_EL0_SHIFT U(0) @@ -154,26 +158,22 @@ #define ID_AA64PFR0_GIC_SHIFT U(24) #define ID_AA64PFR0_GIC_WIDTH U(4) -#define ID_AA64PFR0_GIC_MASK ((ULL(1) << ID_AA64PFR0_GIC_WIDTH) - ULL(1)) +#define ID_AA64PFR0_GIC_MASK ULL(0xf) /* ID_AA64ISAR1_EL1 definitions */ +#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 #define ID_AA64ISAR1_GPI_SHIFT U(28) #define ID_AA64ISAR1_GPI_WIDTH U(4) +#define ID_AA64ISAR1_GPI_MASK ULL(0xf) #define ID_AA64ISAR1_GPA_SHIFT U(24) #define ID_AA64ISAR1_GPA_WIDTH U(4) +#define ID_AA64ISAR1_GPA_MASK ULL(0xf) #define ID_AA64ISAR1_API_SHIFT U(8) #define ID_AA64ISAR1_API_WIDTH U(4) +#define ID_AA64ISAR1_API_MASK ULL(0xf) #define ID_AA64ISAR1_APA_SHIFT U(4) #define ID_AA64ISAR1_APA_WIDTH U(4) - -#define ID_AA64ISAR1_GPI_MASK \ - (((ULL(1) << ID_AA64ISAR1_GPI_WIDTH) - ULL(1)) << ID_AA64ISAR1_GPI_SHIFT) -#define ID_AA64ISAR1_GPA_MASK \ - (((ULL(1) << ID_AA64ISAR1_GPA_WIDTH) - ULL(1)) << ID_AA64ISAR1_GPA_SHIFT) -#define ID_AA64ISAR1_API_MASK \ - (((ULL(1) << ID_AA64ISAR1_API_WIDTH) - ULL(1)) << ID_AA64ISAR1_API_SHIFT) -#define ID_AA64ISAR1_APA_MASK \ - (((ULL(1) << ID_AA64ISAR1_APA_WIDTH) - ULL(1)) << ID_AA64ISAR1_APA_SHIFT) +#define ID_AA64ISAR1_APA_MASK ULL(0xf) /* ID_AA64MMFR0_EL1 definitions */ #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) @@ -255,12 +255,11 @@ #define SCTLR_NTWE_BIT (ULL(1) << 18) #define SCTLR_WXN_BIT (ULL(1) << 19) #define SCTLR_UWXN_BIT (ULL(1) << 20) +#define SCTLR_IESB_BIT (ULL(1) << 21) #define SCTLR_E0E_BIT (ULL(1) << 24) #define SCTLR_EE_BIT (ULL(1) << 25) #define SCTLR_UCI_BIT (ULL(1) << 26) -#define SCTLR_TRE_BIT (ULL(1) << 28) -#define SCTLR_AFE_BIT (ULL(1) << 29) -#define SCTLR_TE_BIT (ULL(1) << 30) +#define SCTLR_EnIA_BIT (ULL(1) << 31) #define SCTLR_DSSBS_BIT (ULL(1) << 44) #define SCTLR_RESET_VAL SCTLR_EL3_RES1 @@ -291,16 +290,17 @@ /* MDCR_EL3 definitions */ #define MDCR_SPD32(x) ((x) << 14) -#define MDCR_SPD32_LEGACY U(0x0) -#define MDCR_SPD32_DISABLE U(0x2) -#define MDCR_SPD32_ENABLE U(0x3) -#define MDCR_SDD_BIT (U(1) << 16) +#define MDCR_SPD32_LEGACY ULL(0x0) +#define MDCR_SPD32_DISABLE ULL(0x2) +#define MDCR_SPD32_ENABLE ULL(0x3) +#define MDCR_SDD_BIT (ULL(1) << 16) #define MDCR_NSPB(x) ((x) << 12) -#define MDCR_NSPB_EL1 U(0x3) -#define MDCR_TDOSA_BIT (U(1) << 10) -#define MDCR_TDA_BIT (U(1) << 9) -#define MDCR_TPM_BIT (U(1) << 6) -#define MDCR_EL3_RESET_VAL U(0x0) +#define MDCR_NSPB_EL1 ULL(0x3) +#define MDCR_TDOSA_BIT (ULL(1) << 10) +#define MDCR_TDA_BIT (ULL(1) << 9) +#define MDCR_TPM_BIT (ULL(1) << 6) +#define MDCR_SCCD_BIT (ULL(1) << 23) +#define MDCR_EL3_RESET_VAL ULL(0x0) /* MDCR_EL2 definitions */ #define MDCR_EL2_TPMS (U(1) << 14) @@ -787,6 +787,10 @@ /* MPAM register definitions */ #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) +#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) + +#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) +#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) @@ -822,7 +826,16 @@ /******************************************************************************* * Armv8.3 Pointer Authentication Registers ******************************************************************************/ +#define APIAKeyLo_EL1 S3_0_C2_C1_0 +#define APIAKeyHi_EL1 S3_0_C2_C1_1 +#define APIBKeyLo_EL1 S3_0_C2_C1_2 +#define APIBKeyHi_EL1 S3_0_C2_C1_3 +#define APDAKeyLo_EL1 S3_0_C2_C2_0 +#define APDAKeyHi_EL1 S3_0_C2_C2_1 +#define APDBKeyLo_EL1 S3_0_C2_C2_2 +#define APDBKeyHi_EL1 S3_0_C2_C2_3 #define APGAKeyLo_EL1 S3_0_C2_C3_0 +#define APGAKeyHi_EL1 S3_0_C2_C3_1 /******************************************************************************* * Armv8.4 Data Independent Timing Registers diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index da8b6e4f1..6af1d0397 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -23,6 +23,25 @@ static inline bool is_armv8_2_ttcnp_present(void) ID_AA64MMFR2_EL1_CNP_MASK) != 0U; } +static inline bool is_armv8_3_pauth_present(void) +{ + uint64_t mask = (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | + (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | + (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | + (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); + + /* If any of the fields is not zero, PAuth is present */ + return (read_id_aa64isar1_el1() & mask) != 0U; +} + +static inline bool is_armv8_3_pauth_apa_api_present(void) +{ + uint64_t mask = (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | + (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); + + return (read_id_aa64isar1_el1() & mask) != 0U; +} + static inline bool is_armv8_4_ttst_present(void) { return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) & diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 4e459bbb9..2fce6686b 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -113,6 +113,18 @@ static inline void tlbi ## _type(uint64_t v) \ } #endif /* ERRATA_A57_813419 */ +#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 +/* + * Define function for DC instruction with register parameter that enables + * the workaround for errata 819472, 824069 and 827319 of Cortex-A53. + */ +#define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \ +static inline void dc ## _name(uint64_t v) \ +{ \ + __asm__("dc " #_type ", %0" : : "r" (v)); \ +} +#endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */ + DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) @@ -143,11 +155,23 @@ DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) ******************************************************************************/ DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) +#if ERRATA_A53_827319 +DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw) +#else DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) +#endif +#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 +DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac) +#else DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) +#endif DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) +#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 +DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac) +#else DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) +#endif DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) /******************************************************************************* @@ -184,6 +208,7 @@ DEFINE_SYSREG_RW_FUNCS(par_el1) DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1) DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1) DEFINE_SYSREG_READ_FUNC(id_afr0_el1) DEFINE_SYSREG_READ_FUNC(CurrentEl) @@ -454,7 +479,8 @@ DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) /* Armv8.3 Pointer Authentication Registers */ -DEFINE_RENAME_SYSREG_RW_FUNCS(apgakeylo_el1, APGAKeyLo_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) #define IS_IN_EL(x) \ (GET_EL(read_CurrentEl()) == MODE_EL##x) diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 410aeab75..22b32b491 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -76,9 +76,16 @@ * authentication instructions from lower ELs. * --------------------------------------------------------------------- */ - mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT | \ - SCR_API_BIT | SCR_APK_BIT) \ + mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) +#if CTX_INCLUDE_PAUTH_REGS + /* + * If the pointer authentication registers are saved during world + * switches, enable pointer authentication everywhere, as it is safe to + * do so. + */ + orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) +#endif msr scr_el3, x0 /* --------------------------------------------------------------------- @@ -101,10 +108,17 @@ * * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register * accesses to all Performance Monitors registers do not trap to EL3. + * + * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is + * prohibited in Secure state. This bit is RES0 in versions of the + * architecture earlier than ARMv8.5, setting it to 1 doesn't have any + * effect on them. * --------------------------------------------------------------------- */ - mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) \ - & ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT)) + mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ + MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) \ + & ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT)) + msr mdcr_el3, x0 /* --------------------------------------------------------------------- diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h index 7b5d87572..937b8c7e8 100644 --- a/include/bl1/bl1.h +++ b/include/bl1/bl1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -83,6 +83,7 @@ register_t bl1_smc_handler(unsigned int smc_fid, void bl1_print_next_bl_ep_info(const struct entry_point_info *bl_ep_info); +void bl1_setup(void); void bl1_main(void); void bl1_plat_prepare_exit(entry_point_info_t *ep_info); diff --git a/include/bl2/bl2.h b/include/bl2/bl2.h index 8ec080c0a..73f5ac7a1 100644 --- a/include/bl2/bl2.h +++ b/include/bl2/bl2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,12 @@ #ifndef BL2_H #define BL2_H +#include <stdint.h> + +void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, + u_register_t arg3); +void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, + u_register_t arg3); void bl2_main(void); #endif /* BL2_H */ diff --git a/include/bl31/bl31.h b/include/bl31/bl31.h index 08c555d90..3deb0a51d 100644 --- a/include/bl31/bl31.h +++ b/include/bl31/bl31.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,8 @@ /******************************************************************************* * Function prototypes ******************************************************************************/ +void bl31_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, + u_register_t arg3); void bl31_next_el_arch_setup(uint32_t security_state); void bl31_set_next_image_type(uint32_t security_state); uint32_t bl31_get_next_image_type(void); diff --git a/include/bl32/tsp/tsp.h b/include/bl32/tsp/tsp.h index ed4792e58..18d3079e2 100644 --- a/include/bl32/tsp/tsp.h +++ b/include/bl32/tsp/tsp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -104,6 +104,7 @@ typedef struct tsp_vectors { tsp_vector_isn_t abort_yield_smc_entry; } tsp_vectors_t; +void tsp_setup(void); #endif /* __ASSEMBLY__ */ diff --git a/include/common/bl_common.h b/include/common/bl_common.h index fd7656eb5..457dc2a1f 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -57,6 +57,48 @@ #define FIQ_AARCH32 U(0xe) #define SERROR_AARCH32 U(0xf) +/* + * Mapping to connect linker symbols from .ld.S with their counterparts + * from .scat for the BL31 image + */ +#if defined(USE_ARM_LINK) +#define __BL31_END__ Load$$LR$$LR_END$$Base +#define __BSS_START__ Load$$LR$$LR_BSS$$Base +#define __BSS_END__ Load$$LR$$LR_BSS$$Limit +#define __BSS_SIZE__ Load$$LR$$LR_BSS$$Length +#define __COHERENT_RAM_START__ Load$$LR$$LR_COHERENT_RAM$$Base +#define __COHERENT_RAM_END_UNALIGNED__ Load$$__COHERENT_RAM_EPILOGUE_UNALIGNED__$$Base +#define __COHERENT_RAM_END__ Load$$LR$$LR_COHERENT_RAM$$Limit +#define __COHERENT_RAM_UNALIGNED_SIZE__ Load$$__COHERENT_RAM__$$Length +#define __CPU_OPS_START__ Load$$__CPU_OPS__$$Base +#define __CPU_OPS_END__ Load$$__CPU_OPS__$$Limit +#define __DATA_START__ Load$$__DATA__$$Base +#define __DATA_END__ Load$$__DATA__$$Limit +#define __GOT_START__ Load$$__GOT__$$Base +#define __GOT_END__ Load$$__GOT__$$Limit +#define __PERCPU_BAKERY_LOCK_START__ Load$$__BAKERY_LOCKS__$$Base +#define __PERCPU_BAKERY_LOCK_END__ Load$$__BAKERY_LOCKS_EPILOGUE__$$Base +#define __PMF_SVC_DESCS_START__ Load$$__PMF_SVC_DESCS__$$Base +#define __PMF_SVC_DESCS_END__ Load$$__PMF_SVC_DESCS__$$Limit +#define __PMF_TIMESTAMP_START__ Load$$__PMF_TIMESTAMP__$$Base +#define __PMF_TIMESTAMP_END__ Load$$__PER_CPU_TIMESTAMPS__$$Limit +#define __PMF_PERCPU_TIMESTAMP_END__ Load$$__PMF_TIMESTAMP_EPILOGUE__$$Base +#define __RELA_END__ Load$$__RELA__$$Limit +#define __RELA_START__ Load$$__RELA__$$Base +#define __RODATA_START__ Load$$__RODATA__$$Base +#define __RODATA_END__ Load$$__RODATA_EPILOGUE__$$Base +#define __RT_SVC_DESCS_START__ Load$$__RT_SVC_DESCS__$$Base +#define __RT_SVC_DESCS_END__ Load$$__RT_SVC_DESCS__$$Limit +#define __RW_START__ Load$$LR$$LR_RW_DATA$$Base +#define __RW_END__ Load$$LR$$LR_END$$Base +#define __SPM_SHIM_EXCEPTIONS_START__ Load$$__SPM_SHIM_EXCEPTIONS__$$Base +#define __SPM_SHIM_EXCEPTIONS_END__ Load$$__SPM_SHIM_EXCEPTIONS_EPILOGUE__$$Base +#define __STACKS_START__ Load$$__STACKS__$$Base +#define __STACKS_END__ Load$$__STACKS__$$Limit +#define __TEXT_START__ Load$$__TEXT__$$Base +#define __TEXT_END__ Load$$__TEXT_EPILOGUE__$$Base +#endif /* USE_ARM_LINK */ + #ifndef __ASSEMBLY__ #include <stddef.h> @@ -207,6 +249,8 @@ struct mmap_region; void setup_page_tables(const struct mmap_region *bl_regions, const struct mmap_region *plat_regions); +void bl_handle_pauth(void); + #endif /*__ASSEMBLY__*/ #endif /* BL_COMMON_H */ diff --git a/include/drivers/arm/css/css_mhu_doorbell.h b/include/drivers/arm/css/css_mhu_doorbell.h index ecee56361..e6f7a1bd1 100644 --- a/include/drivers/arm/css/css_mhu_doorbell.h +++ b/include/drivers/arm/css/css_mhu_doorbell.h @@ -12,7 +12,7 @@ #include <lib/mmio.h> /* MHUv2 Base Address */ -#define MHUV2_BASE_ADDR PLAT_CSS_MHU_BASE +#define MHUV2_BASE_ADDR PLAT_MHUV2_BASE /* MHUv2 Control Registers Offsets */ #define MHU_V2_MSG_NO_CAP_OFFSET 0xF80 diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h index 2aaa28d68..7611f019a 100644 --- a/include/drivers/mmc.h +++ b/include/drivers/mmc.h @@ -220,6 +220,7 @@ struct mmc_device_info { unsigned long long device_size; /* Size of device in bytes */ unsigned int block_size; /* Block size in bytes */ unsigned int max_bus_freq; /* Max bus freq in Hz */ + unsigned int ocr_voltage; /* OCR voltage */ enum mmc_device_type mmc_dev_type; /* Type of MMC */ }; diff --git a/include/drivers/rpi3/sdhost/rpi3_sdhost.h b/include/drivers/rpi3/sdhost/rpi3_sdhost.h index bc906e394..1653240c8 100644 --- a/include/drivers/rpi3/sdhost/rpi3_sdhost.h +++ b/include/drivers/rpi3/sdhost/rpi3_sdhost.h @@ -21,7 +21,6 @@ struct rpi3_sdhost_params { uint8_t cmdbusy; uint8_t mmc_app_cmd; uint32_t ns_per_fifo_word; - uint32_t crc_err_retries; uint32_t sdcard_rca; uint32_t gpio48_pinselect[6]; diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h index 1e0d949ac..7afa5ad84 100644 --- a/include/drivers/st/stm32mp1_clk.h +++ b/include/drivers/st/stm32mp1_clk.h @@ -13,6 +13,7 @@ int stm32mp1_clk_probe(void); int stm32mp1_clk_init(void); bool stm32mp1_rcc_is_secure(void); +bool stm32mp1_rcc_is_mckprot(void); void __stm32mp1_clk_enable(unsigned long id, bool caller_is_secure); void __stm32mp1_clk_disable(unsigned long id, bool caller_is_secure); diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h index 1922c4815..eaa853da3 100644 --- a/include/drivers/st/stm32mp1_rcc.h +++ b/include/drivers/st/stm32mp1_rcc.h @@ -111,6 +111,7 @@ #define RCC_RCK4SELR U(0x824) #define RCC_TIMG1PRER U(0x828) #define RCC_TIMG2PRER U(0x82C) +#define RCC_MCUDIVR U(0x830) #define RCC_APB1DIVR U(0x834) #define RCC_APB2DIVR U(0x838) #define RCC_APB3DIVR U(0x83C) @@ -237,6 +238,7 @@ /* Values for RCC_TZCR register */ #define RCC_TZCR_TZEN BIT(0) +#define RCC_TZCR_MCKPROT BIT(1) /* Used for most of RCC_<x>SELR registers */ #define RCC_SELR_SRC_MASK GENMASK(2, 0) @@ -273,6 +275,7 @@ #define RCC_APBXDIV_MASK GENMASK(2, 0) #define RCC_MPUDIV_MASK GENMASK(2, 0) #define RCC_AXIDIV_MASK GENMASK(2, 0) +#define RCC_MCUDIV_MASK GENMASK(3, 0) /* Used for TIMER Prescaler */ #define RCC_TIMGXPRER_TIMGXPRE BIT(0) @@ -421,6 +424,7 @@ /* Global Reset Register */ #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) +#define RCC_MP_GRSTCSETR_MCURST BIT(1) #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) #define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index f7005da3e..ffabd61ac 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -45,6 +45,7 @@ #define CORTEX_A57_CPUACTLR p15, 0, c15 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION (ULL(1) << 58) #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55) #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52) diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h index 8b21e16a1..feac1d2f0 100644 --- a/include/lib/cpus/aarch64/cortex_a55.h +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -18,6 +18,24 @@ #define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24) +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31) +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49) + +/******************************************************************************* + * CPU Identification register specific definitions. + ******************************************************************************/ +#define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1 + +#define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6) + /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ #define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 1e68f21a4..102ff60c3 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -45,6 +45,7 @@ #define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58) #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index 3b401805a..1238c0ef4 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -31,4 +31,8 @@ #define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3) +#define CORTEX_A73_DIAGNOSTIC_REGISTER S3_0_C15_C0_1 + +#define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2 + #endif /* CORTEX_A73_H */ diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index 5779d7bab..c2af8cad9 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -18,9 +18,15 @@ #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) + /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ +#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) + #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) diff --git a/include/lib/cpus/aarch64/cortex_ares.h b/include/lib/cpus/aarch64/cortex_ares.h deleted file mode 100644 index cfc36e473..000000000 --- a/include/lib/cpus/aarch64/cortex_ares.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_ARES_H -#define CORTEX_ARES_H - -#include <lib/utils_def.h> - -/* Cortex-ARES MIDR for revision 0 */ -#define CORTEX_ARES_MIDR U(0x410fd0c0) - -/******************************************************************************* - * CPU Extended Control register specific definitions. - ******************************************************************************/ -#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 - -/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ -#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1) - -#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) - -#define CORTEX_ARES_AMU_NR_COUNTERS U(5) -#define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f) - -/* Instruction patching registers */ -#define CPUPSELR_EL3 S3_6_C15_C8_0 -#define CPUPCR_EL3 S3_6_C15_C8_1 -#define CPUPOR_EL3 S3_6_C15_C8_2 -#define CPUPMR_EL3 S3_6_C15_C8_3 - -#endif /* CORTEX_ARES_H */ diff --git a/include/lib/cpus/aarch64/cortex_helios.h b/include/lib/cpus/aarch64/neoverse_e1.h index 0c11a9a4c..708460480 100644 --- a/include/lib/cpus/aarch64/cortex_helios.h +++ b/include/lib/cpus/aarch64/neoverse_e1.h @@ -4,28 +4,28 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_HELIOS_H -#define CORTEX_HELIOS_H +#ifndef NEOVERSE_E1_H +#define NEOVERSE_E1_H #include <lib/utils_def.h> -#define CORTEX_HELIOS_MIDR U(0x410FD060) +#define NEOVERSE_E1_MIDR U(0x410FD060) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 +#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0 /******************************************************************************* * CPU Power Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) +#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) -#endif /* CORTEX_HELIOS_H */ +#endif /* NEOVERSE_E1_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h new file mode 100644 index 000000000..908993e45 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_N1_H +#define NEOVERSE_N1_H + +#include <lib/utils_def.h> + +/* Neoverse N1 MIDR for revision 0 */ +#define NEOVERSE_N1_MIDR U(0x410fd0c0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ +#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) + +#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) + +#define NEOVERSE_N1_AMU_NR_COUNTERS U(5) +#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) + +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* NEOVERSE_N1_H */ diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index 70c50aae2..5bd0de424 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -104,25 +104,30 @@ #define CTX_SPSR_FIQ U(0xd8) #define CTX_DACR32_EL2 U(0xe0) #define CTX_IFSR32_EL2 U(0xe8) -#define CTX_TIMER_SYSREGS_OFF U(0xf0) /* Align to the next 16 byte boundary */ +#define CTX_AARCH32_END U(0xf0) /* Align to the next 16 byte boundary */ #else -#define CTX_TIMER_SYSREGS_OFF U(0xc0) /* Align to the next 16 byte boundary */ -#endif /* __CTX_INCLUDE_AARCH32_REGS__ */ +#define CTX_AARCH32_END U(0xc0) /* Align to the next 16 byte boundary */ +#endif /* CTX_INCLUDE_AARCH32_REGS */ /* * If the timer registers aren't saved and restored, we don't have to reserve * space for them in the context */ #if NS_TIMER_SWITCH -#define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x0)) -#define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x8)) -#define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x10)) -#define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x18)) -#define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + U(0x20)) -#define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + U(0x30)) /* Align to the next 16 byte boundary */ +#define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0)) +#define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8)) +#define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10)) +#define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18)) +#define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20)) +#define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */ #else -#define CTX_SYSREGS_END CTX_TIMER_SYSREGS_OFF -#endif /* __NS_TIMER_SWITCH__ */ +#define CTX_TIMER_SYSREGS_END CTX_AARCH32_END +#endif /* NS_TIMER_SWITCH */ + +/* + * End of system registers. + */ +#define CTX_SYSREGS_END CTX_TIMER_SYSREGS_END /******************************************************************************* * Constants that allow assembler code to access members of and the 'fp_regs' @@ -174,16 +179,38 @@ #define CTX_FPREGS_END U(0) #endif +/******************************************************************************* + * Registers related to CVE-2018-3639 + ******************************************************************************/ #define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END) #define CTX_CVE_2018_3639_DISABLE U(0) #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ +/******************************************************************************* + * Registers related to ARMv8.3-PAuth. + ******************************************************************************/ +#define CTX_PAUTH_REGS_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) +#if CTX_INCLUDE_PAUTH_REGS +#define CTX_PACIAKEY_LO U(0x0) +#define CTX_PACIAKEY_HI U(0x8) +#define CTX_PACIBKEY_LO U(0x10) +#define CTX_PACIBKEY_HI U(0x18) +#define CTX_PACDAKEY_LO U(0x20) +#define CTX_PACDAKEY_HI U(0x28) +#define CTX_PACDBKEY_LO U(0x30) +#define CTX_PACDBKEY_HI U(0x38) +#define CTX_PACGAKEY_LO U(0x40) +#define CTX_PACGAKEY_HI U(0x48) +#define CTX_PACGAKEY_END U(0x50) +#define CTX_PAUTH_REGS_END U(0x60) /* Align to the next 16 byte boundary */ +#else +#define CTX_PAUTH_REGS_END U(0) +#endif /* CTX_INCLUDE_PAUTH_REGS */ + #ifndef __ASSEMBLY__ #include <stdint.h> -#include <platform_def.h> /* for CACHE_WRITEBACK_GRANULE */ - #include <lib/cassert.h> /* @@ -200,10 +227,13 @@ #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) #define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) #if CTX_INCLUDE_FPREGS -#define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) +# define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) #endif #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) +#if CTX_INCLUDE_PAUTH_REGS +# define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) +#endif /* * AArch64 general purpose register context structure. Usually x0-x18, @@ -239,6 +269,11 @@ DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); /* Function pointer used by CVE-2018-3639 dynamic mitigation */ DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); +/* Registers associated to ARMv8.3-PAuth */ +#if CTX_INCLUDE_PAUTH_REGS +DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); +#endif + /* * Macros to access members of any of the above structures using their * offsets @@ -264,16 +299,22 @@ typedef struct cpu_context { fp_regs_t fpregs_ctx; #endif cve_2018_3639_t cve_2018_3639_ctx; +#if CTX_INCLUDE_PAUTH_REGS + pauth_t pauth_ctx; +#endif } cpu_context_t; /* Macros to access members of the 'cpu_context_t' structure */ #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) #if CTX_INCLUDE_FPREGS -#define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) +# define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) #endif #define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) +#if CTX_INCLUDE_PAUTH_REGS +# define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) +#endif /* * Compile time assertions related to the 'cpu_context' structure to @@ -292,6 +333,10 @@ CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), assert_core_context_el3state_offset_mismatch); CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), \ assert_core_context_cve_2018_3639_offset_mismatch); +#if CTX_INCLUDE_PAUTH_REGS +CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \ + assert_core_context_pauth_offset_mismatch); +#endif /* * Helper macro to set the general purpose registers that correspond to @@ -339,14 +384,6 @@ void fpregs_context_save(fp_regs_t *regs); void fpregs_context_restore(fp_regs_t *regs); #endif - -#undef CTX_SYSREG_ALL -#if CTX_INCLUDE_FPREGS -#undef CTX_FPREG_ALL -#endif -#undef CTX_GPREG_ALL -#undef CTX_EL3STATE_ALL - #endif /* __ASSEMBLY__ */ #endif /* CONTEXT_H */ diff --git a/include/lib/el3_runtime/pubsub.h b/include/lib/el3_runtime/pubsub.h index eb9128656..64fe5ccb4 100644 --- a/include/lib/el3_runtime/pubsub.h +++ b/include/lib/el3_runtime/pubsub.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,13 +7,11 @@ #ifndef PUBSUB_H #define PUBSUB_H -#define __pubsub_start_sym(event) __pubsub_##event##_start -#define __pubsub_end_sym(event) __pubsub_##event##_end - #ifdef __LINKER__ /* For the linker ... */ - +#define __pubsub_start_sym(event) __pubsub_##event##_start +#define __pubsub_end_sym(event) __pubsub_##event##_end #define __pubsub_section(event) __pubsub_##event /* @@ -21,10 +19,22 @@ * contexts. In linker context, this collects pubsub sections for each event, * placing guard symbols around each. */ +#if defined(USE_ARM_LINK) +#define REGISTER_PUBSUB_EVENT(event) \ + __pubsub_start_sym(event) +0 FIXED \ + { \ + *(__pubsub_section(event)) \ + } \ + __pubsub_end_sym(event) +0 FIXED EMPTY 0 \ + { \ + /* placeholder */ \ + } +#else #define REGISTER_PUBSUB_EVENT(event) \ __pubsub_start_sym(event) = .; \ KEEP(*(__pubsub_section(event))); \ __pubsub_end_sym(event) = . +#endif #else /* __LINKER__ */ @@ -36,6 +46,14 @@ #include <arch_helpers.h> +#if defined(USE_ARM_LINK) +#define __pubsub_start_sym(event) Load$$__pubsub_##event##_start$$Base +#define __pubsub_end_sym(event) Load$$__pubsub_##event##_end$$Base +#else +#define __pubsub_start_sym(event) __pubsub_##event##_start +#define __pubsub_end_sym(event) __pubsub_##event##_end +#endif + #define __pubsub_section(event) __section("__pubsub_" #event) /* @@ -49,7 +67,7 @@ /* * Have the function func called back when the specified event happens. This * macro places the function address into the pubsub section, which is picked up - * and invoked by the invoke_pubsubs() function via. the PUBLISH_EVENT* macros. + * and invoked by the invoke_pubsubs() function via the PUBLISH_EVENT* macros. * * The extern declaration is there to satisfy MISRA C-2012 rule 8.4. */ diff --git a/include/lib/extensions/ras.h b/include/lib/extensions/ras.h index 9f6b2905f..98daab601 100644 --- a/include/lib/extensions/ras.h +++ b/include/lib/extensions/ras.h @@ -106,7 +106,7 @@ struct err_handler_data { */ uint32_t syndrome; - /* For errors signalled via. interrupt, the raw interrupt ID; otherwise, 0. */ + /* For errors signalled via interrupt, the raw interrupt ID; otherwise, 0. */ unsigned int interrupt; }; @@ -129,7 +129,7 @@ struct err_record_info { union { struct { /* - * For a group accessed via. memory-mapped register, + * For a group accessed via memory-mapped register, * base address of the page hosting error records, and * the size of the record group. */ @@ -141,7 +141,7 @@ struct err_record_info { struct { /* - * For error records accessed via. system register, index of + * For error records accessed via system register, index of * the error record. */ unsigned int idx_start; diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h index 6d0fb7896..f9bbe0f60 100644 --- a/include/lib/xlat_tables/xlat_tables_defs.h +++ b/include/lib/xlat_tables/xlat_tables_defs.h @@ -73,7 +73,11 @@ #define PAGE_SIZE_MASK (PAGE_SIZE - U(1)) #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0)) -#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes (1 << 3) */ +#if (ARM_ARCH_MAJOR == 7) && !ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING +#define XLAT_ENTRY_SIZE_SHIFT U(2) /* Each MMU table entry is 4 bytes */ +#else +#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes */ +#endif #define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT) #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h index a77ea96ef..452afbcc8 100644 --- a/include/plat/arm/board/common/board_css_def.h +++ b/include/plat/arm/board/common/board_css_def.h @@ -61,14 +61,14 @@ #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ -#define PLAT_ARM_BL31_RUN_UART_BASE SOC_CSS_UART1_BASE -#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ +#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE +#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ #define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ -#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE -#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index 13767ff0a..4832e491c 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -104,6 +104,7 @@ const char *plat_log_get_prefix(unsigned int log_level); void bl2_plat_preload_setup(void); int plat_try_next_boot_source(void); int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size); +uint64_t *plat_init_apiakey(void); /******************************************************************************* * Mandatory BL1 functions |