diff options
Diffstat (limited to 'include')
26 files changed, 493 insertions, 81 deletions
diff --git a/include/drivers/allwinner/sunxi_rsb.h b/include/drivers/allwinner/sunxi_rsb.h new file mode 100644 index 000000000..5a69d35f2 --- /dev/null +++ b/include/drivers/allwinner/sunxi_rsb.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2017-2018 ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SUNXI_RSB_H +#define SUNXI_RSB_H + +#include <stdint.h> + +int rsb_init_controller(void); +int rsb_set_bus_speed(uint32_t source_freq, uint32_t bus_freq); +int rsb_set_device_mode(uint32_t device_mode); +int rsb_assign_runtime_address(uint16_t hw_addr, uint8_t rt_addr); + +int rsb_read(uint8_t rt_addr, uint8_t reg_addr); +int rsb_write(uint8_t rt_addr, uint8_t reg_addr, uint8_t value); + +#endif diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h index 493c7d472..f68f98f63 100644 --- a/include/lib/cpus/aarch64/cortex_a75.h +++ b/include/lib/cpus/aarch64/cortex_a75.h @@ -4,11 +4,13 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __CORTEX_A75_H__ -#define __CORTEX_A75_H__ +#ifndef CORTEX_A75_H +#define CORTEX_A75_H + +#include <utils_def.h> /* Cortex-A75 MIDR */ -#define CORTEX_A75_MIDR 0x410fd0a0 +#define CORTEX_A75_MIDR U(0x410fd0a0) /******************************************************************************* * CPU Extended Control register specific definitions. @@ -24,7 +26,7 @@ #define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (1 << 35) /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ -#define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1 +#define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1) #define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4) @@ -50,4 +52,4 @@ void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask); void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask); #endif /* __ASSEMBLY__ */ -#endif /* __CORTEX_A75_H__ */ +#endif /* CORTEX_A75_H */ diff --git a/include/lib/cpus/aarch64/cortex_ares.h b/include/lib/cpus/aarch64/cortex_ares.h index 84955b181..4f3e81296 100644 --- a/include/lib/cpus/aarch64/cortex_ares.h +++ b/include/lib/cpus/aarch64/cortex_ares.h @@ -4,11 +4,13 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __CORTEX_ARES_H__ -#define __CORTEX_ARES_H__ +#ifndef CORTEX_ARES_H +#define CORTEX_ARES_H + +#include <utils_def.h> /* Cortex-ARES MIDR for revision 0 */ -#define CORTEX_ARES_MIDR 0x410fd0c0 +#define CORTEX_ARES_MIDR U(0x410fd0c0) /******************************************************************************* * CPU Extended Control register specific definitions. @@ -17,7 +19,7 @@ #define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 /* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ -#define CORTEX_ARES_CORE_PWRDN_EN_MASK 0x1 +#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1) #define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) @@ -30,4 +32,4 @@ #define CPUPOR_EL3 S3_6_C15_C8_2 #define CPUPMR_EL3 S3_6_C15_C8_3 -#endif /* __CORTEX_ARES_H__ */ +#endif /* CORTEX_ARES_H */ diff --git a/include/lib/cpus/aarch64/cpuamu.h b/include/lib/cpus/aarch64/cpuamu.h index 960a52484..921abdbd4 100644 --- a/include/lib/cpus/aarch64/cpuamu.h +++ b/include/lib/cpus/aarch64/cpuamu.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __CPUAMU_H__ -#define __CPUAMU_H__ +#ifndef CPUAMU_H +#define CPUAMU_H /******************************************************************************* * CPU Activity Monitor Unit register specific definitions. @@ -32,8 +32,8 @@ #ifndef __ASSEMBLY__ #include <stdint.h> -uint64_t cpuamu_cnt_read(int idx); -void cpuamu_cnt_write(int idx, uint64_t val); +uint64_t cpuamu_cnt_read(unsigned int idx); +void cpuamu_cnt_write(unsigned int idx, uint64_t val); unsigned int cpuamu_read_cpuamcntenset_el0(void); unsigned int cpuamu_read_cpuamcntenclr_el0(void); void cpuamu_write_cpuamcntenset_el0(unsigned int mask); @@ -45,4 +45,4 @@ void cpuamu_context_restore(unsigned int nr_counters); #endif /* __ASSEMBLY__ */ -#endif /* __CPUAMU_H__ */ +#endif /* CPUAMU_H */ diff --git a/include/lib/cpus/errata_report.h b/include/lib/cpus/errata_report.h index d2138bf55..c97d4c247 100644 --- a/include/lib/cpus/errata_report.h +++ b/include/lib/cpus/errata_report.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __ERRATA_H__ -#define __ERRATA_H__ +#ifndef ERRATA_REPORT_H +#define ERRATA_REPORT_H #ifndef __ASSEMBLY__ @@ -30,5 +30,4 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported); #define ERRATA_APPLIES 1 #define ERRATA_MISSING 2 -#endif /* __ERRATA_H__ */ - +#endif /* ERRATA_REPORT_H */ diff --git a/include/lib/cpus/wa_cve_2017_5715.h b/include/lib/cpus/wa_cve_2017_5715.h index 0a65a5692..940fc659e 100644 --- a/include/lib/cpus/wa_cve_2017_5715.h +++ b/include/lib/cpus/wa_cve_2017_5715.h @@ -4,9 +4,9 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __WA_CVE_2017_5715_H__ -#define __WA_CVE_2017_5715_H__ +#ifndef WA_CVE_2017_5715_H +#define WA_CVE_2017_5715_H int check_wa_cve_2017_5715(void); -#endif /* __WA_CVE_2017_5715_H__ */ +#endif /* WA_CVE_2017_5715_H */ diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h index 36546f70d..e37db377e 100644 --- a/include/lib/cpus/wa_cve_2018_3639.h +++ b/include/lib/cpus/wa_cve_2018_3639.h @@ -4,9 +4,9 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __WA_CVE_2018_3639_H__ -#define __WA_CVE_2018_3639_H__ +#ifndef WA_CVE_2018_3639_H +#define WA_CVE_2018_3639_H void *wa_cve_2018_3639_get_disable_ptr(void); -#endif /* __WA_CVE_2018_3639_H__ */ +#endif /* WA_CVE_2018_3639_H */ diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h index 15d34ebf8..b6959509c 100644 --- a/include/lib/el3_runtime/cpu_data.h +++ b/include/lib/el3_runtime/cpu_data.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __CPU_DATA_H__ -#define __CPU_DATA_H__ +#ifndef CPU_DATA_H +#define CPU_DATA_H #include <ehf.h> #include <platform_def.h> /* CACHE_WRITEBACK_GRANULE required */ @@ -161,4 +161,4 @@ void init_cpu_ops(void); #endif /* __ASSEMBLY__ */ -#endif /* __CPU_DATA_H__ */ +#endif /* CPU_DATA_H */ diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h index 46d5e1593..1836fe5ae 100644 --- a/include/lib/extensions/amu.h +++ b/include/lib/extensions/amu.h @@ -4,33 +4,35 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __AMU_H__ -#define __AMU_H__ +#ifndef AMU_H +#define AMU_H #include <cassert.h> #include <platform_def.h> +#include <stdbool.h> #include <stdint.h> +#include <utils_def.h> /* All group 0 counters */ -#define AMU_GROUP0_COUNTERS_MASK 0xf +#define AMU_GROUP0_COUNTERS_MASK U(0xf) #ifdef PLAT_AMU_GROUP1_COUNTERS_MASK #define AMU_GROUP1_COUNTERS_MASK PLAT_AMU_GROUP1_COUNTERS_MASK #else -#define AMU_GROUP1_COUNTERS_MASK 0 +#define AMU_GROUP1_COUNTERS_MASK U(0) #endif #ifdef PLAT_AMU_GROUP1_NR_COUNTERS #define AMU_GROUP1_NR_COUNTERS PLAT_AMU_GROUP1_NR_COUNTERS #else -#define AMU_GROUP1_NR_COUNTERS 0 +#define AMU_GROUP1_NR_COUNTERS U(0) #endif CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask); CASSERT(AMU_GROUP1_NR_COUNTERS <= 16, invalid_amu_group1_nr_counters); -int amu_supported(void); -void amu_enable(int el2_unused); +bool amu_supported(void); +void amu_enable(bool el2_unused); /* Group 0 configuration helpers */ uint64_t amu_group0_cnt_read(int idx); @@ -41,4 +43,4 @@ uint64_t amu_group1_cnt_read(int idx); void amu_group1_cnt_write(int idx, uint64_t val); void amu_group1_set_evtype(int idx, unsigned int val); -#endif /* __AMU_H__ */ +#endif /* AMU_H */ diff --git a/include/lib/extensions/amu_private.h b/include/lib/extensions/amu_private.h index 0c660bb83..ab4e6aaba 100644 --- a/include/lib/extensions/amu_private.h +++ b/include/lib/extensions/amu_private.h @@ -1,19 +1,19 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __AMU_PRIVATE_H__ -#define __AMU_PRIVATE_H__ +#ifndef AMU_PRIVATE_H +#define AMU_PRIVATE_H #include <stdint.h> uint64_t amu_group0_cnt_read_internal(int idx); -void amu_group0_cnt_write_internal(int idx, uint64_t); +void amu_group0_cnt_write_internal(int idx, uint64_t val); uint64_t amu_group1_cnt_read_internal(int idx); -void amu_group1_cnt_write_internal(int idx, uint64_t); +void amu_group1_cnt_write_internal(int idx, uint64_t val); void amu_group1_set_evtype_internal(int idx, unsigned int val); -#endif /* __AMU_PRIVATE_H__ */ +#endif /* AMU_PRIVATE_H */ diff --git a/include/lib/extensions/mpam.h b/include/lib/extensions/mpam.h index 571b96b65..ac8c00a43 100644 --- a/include/lib/extensions/mpam.h +++ b/include/lib/extensions/mpam.h @@ -10,6 +10,6 @@ #include <stdbool.h> bool mpam_supported(void); -void mpam_enable(int el2_unused); +void mpam_enable(bool el2_unused); #endif /* MPAM_H */ diff --git a/include/lib/extensions/spe.h b/include/lib/extensions/spe.h index b2b188ef5..d4b925fe4 100644 --- a/include/lib/extensions/spe.h +++ b/include/lib/extensions/spe.h @@ -4,11 +4,13 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __SPE_H__ -#define __SPE_H__ +#ifndef SPE_H +#define SPE_H -int spe_supported(void); -void spe_enable(int el2_unused); +#include <stdbool.h> + +bool spe_supported(void); +void spe_enable(bool el2_unused); void spe_disable(void); -#endif /* __SPE_H__ */ +#endif /* SPE_H */ diff --git a/include/lib/extensions/sve.h b/include/lib/extensions/sve.h index 9c7f37f26..83df1775e 100644 --- a/include/lib/extensions/sve.h +++ b/include/lib/extensions/sve.h @@ -4,10 +4,12 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __SVE_H__ -#define __SVE_H__ +#ifndef SVE_H +#define SVE_H -int sve_supported(void); -void sve_enable(int el2_unused); +#include <stdbool.h> -#endif /* __SVE_H__ */ +bool sve_supported(void); +void sve_enable(bool el2_unused); + +#endif /* SVE_H */ diff --git a/include/lib/mmio.h b/include/lib/mmio.h index 880d2c512..38fdf0f23 100644 --- a/include/lib/mmio.h +++ b/include/lib/mmio.h @@ -29,6 +29,13 @@ static inline uint16_t mmio_read_16(uintptr_t addr) return *(volatile uint16_t*)addr; } +static inline void mmio_clrsetbits_16(uintptr_t addr, + uint16_t clear, + uint16_t set) +{ + mmio_write_16(addr, (mmio_read_16(addr) & ~clear) | set); +} + static inline void mmio_write_32(uintptr_t addr, uint32_t value) { *(volatile uint32_t*)addr = value; diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h index a3812fbf2..18ef0a559 100644 --- a/include/lib/pmf/pmf.h +++ b/include/lib/pmf/pmf.h @@ -9,17 +9,18 @@ #include <cassert.h> #include <pmf_helpers.h> +#include <utils_def.h> /* * Constants used for/by PMF services. */ -#define PMF_ARM_TIF_IMPL_ID 0x41 +#define PMF_ARM_TIF_IMPL_ID U(0x41) #define PMF_TID_SHIFT 0 -#define PMF_TID_MASK (0xFF << PMF_TID_SHIFT) +#define PMF_TID_MASK (U(0xFF) << PMF_TID_SHIFT) #define PMF_SVC_ID_SHIFT 10 -#define PMF_SVC_ID_MASK (0x3F << PMF_SVC_ID_SHIFT) +#define PMF_SVC_ID_MASK (U(0x3F) << PMF_SVC_ID_SHIFT) #define PMF_IMPL_ID_SHIFT 24 -#define PMF_IMPL_ID_MASK (0xFFU << PMF_IMPL_ID_SHIFT) +#define PMF_IMPL_ID_MASK (U(0xFF) << PMF_IMPL_ID_SHIFT) /* * Flags passed to PMF_REGISTER_SERVICE @@ -37,16 +38,16 @@ /* * Defines for PMF SMC function ids. */ -#define PMF_SMC_GET_TIMESTAMP_32 0x82000010u -#define PMF_SMC_GET_TIMESTAMP_64 0xC2000010u +#define PMF_SMC_GET_TIMESTAMP_32 U(0x82000010) +#define PMF_SMC_GET_TIMESTAMP_64 U(0xC2000010) #define PMF_NUM_SMC_CALLS 2 /* * The macros below are used to identify * PMF calls from the SMC function ID. */ -#define PMF_FID_MASK 0xffe0u -#define PMF_FID_VALUE 0u +#define PMF_FID_MASK U(0xffe0) +#define PMF_FID_VALUE U(0) #define is_pmf_fid(_fid) (((_fid) & PMF_FID_MASK) == PMF_FID_VALUE) /* Following are the supported PMF service IDs */ diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h index b9757de07..c535b222d 100644 --- a/include/lib/pmf/pmf_helpers.h +++ b/include/lib/pmf/pmf_helpers.h @@ -11,7 +11,6 @@ #include <assert.h> #include <bl_common.h> #include <platform.h> -#include <pmf.h> #include <stddef.h> #include <stdint.h> diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h index 68375afae..3e25cbc6a 100644 --- a/include/plat/arm/common/arm_sip_svc.h +++ b/include/plat/arm/common/arm_sip_svc.h @@ -1,24 +1,26 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __ARM_SIP_SVC_H__ -#define __ARM_SIP_SVC_H__ +#ifndef ARM_SIP_SVC_H +#define ARM_SIP_SVC_H + +#include <utils_def.h> /* SMC function IDs for SiP Service queries */ -#define ARM_SIP_SVC_CALL_COUNT 0x8200ff00 -#define ARM_SIP_SVC_UID 0x8200ff01 -/* 0x8200ff02 is reserved */ -#define ARM_SIP_SVC_VERSION 0x8200ff03 +#define ARM_SIP_SVC_CALL_COUNT U(0x8200ff00) +#define ARM_SIP_SVC_UID U(0x8200ff01) +/* U(0x8200ff02) is reserved */ +#define ARM_SIP_SVC_VERSION U(0x8200ff03) /* Function ID for requesting state switch of lower EL */ -#define ARM_SIP_SVC_EXE_STATE_SWITCH 0x82000020 +#define ARM_SIP_SVC_EXE_STATE_SWITCH U(0x82000020) /* ARM SiP Service Calls version numbers */ -#define ARM_SIP_SVC_VERSION_MAJOR 0x0 -#define ARM_SIP_SVC_VERSION_MINOR 0x2 +#define ARM_SIP_SVC_VERSION_MAJOR U(0x0) +#define ARM_SIP_SVC_VERSION_MINOR U(0x2) -#endif /* __ARM_SIP_SVC_H__ */ +#endif /* ARM_SIP_SVC_H */ diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index bdcb14415..e7082d080 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLAT_ARM_H__ -#define __PLAT_ARM_H__ +#ifndef PLAT_ARM_H +#define PLAT_ARM_H #include <bakery_lock.h> #include <cassert.h> @@ -292,4 +292,4 @@ extern plat_psci_ops_t plat_arm_psci_pm_ops; extern const mmap_region_t plat_arm_mmap[]; extern const unsigned int arm_pm_idle_states[]; -#endif /* __PLAT_ARM_H__ */ +#endif /* PLAT_ARM_H */ diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index 048c58a31..385331977 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -26,6 +26,11 @@ #define SSC_REG_BASE 0x2a420000 #define SSC_GPRETN (SSC_REG_BASE + 0x030) +/* System ID Registers Unit */ +#define SID_REG_BASE 0x2a4a0000 +#define SID_SYSTEM_ID_OFFSET 0x40 +#define SID_SYSTEM_CFG_OFFSET 0x70 + /* The slave_bootsecure controls access to GPU, DMC and CS. */ #define CSS_NIC400_SLAVE_BOOTSECURE 8 @@ -123,6 +128,8 @@ #define SSC_VERSION_DESIGNER_ID_MASK 0xff #define SSC_VERSION_PART_NUM_MASK 0xfff +#define SID_SYSTEM_ID_PART_NUM_MASK 0xfff + /* SSC debug configuration registers */ #define SSC_DBGCFG_SET 0x14 #define SSC_DBGCFG_CLR 0x18 diff --git a/include/plat/marvell/a3700/common/armada_common.h b/include/plat/marvell/a3700/common/armada_common.h new file mode 100644 index 000000000..9fc463484 --- /dev/null +++ b/include/plat/marvell/a3700/common/armada_common.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef __ARMADA_COMMON_H__ +#define __ARMADA_COMMON_H__ + +#include <io_addr_dec.h> +#include <stdint.h> + +int marvell_get_io_dec_win_conf(struct dec_win_config **win, uint32_t *size); + +#endif /* __ARMADA_COMMON_H__ */ diff --git a/include/plat/marvell/a3700/common/board_marvell_def.h b/include/plat/marvell/a3700/common/board_marvell_def.h new file mode 100644 index 000000000..49a1a5c3e --- /dev/null +++ b/include/plat/marvell/a3700/common/board_marvell_def.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef __BOARD_MARVELL_DEF_H__ +#define __BOARD_MARVELL_DEF_H__ + +/* + * Required platform porting definitions common to all ARM + * development platforms + */ + +/* Size of cacheable stacks */ +#if IMAGE_BL1 +#if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +#else +# define PLATFORM_STACK_SIZE 0x440 +#endif +#elif IMAGE_BL2 +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +# else +# define PLATFORM_STACK_SIZE 0x400 +# endif +#elif IMAGE_BL31 +# define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL32 +# define PLATFORM_STACK_SIZE 0x440 +#endif + +/* + * PLAT_MARVELL_MMAP_ENTRIES depends on the number of entries in the + * plat_arm_mmap array defined for each BL stage. + */ +#if IMAGE_BLE +# define PLAT_MARVELL_MMAP_ENTRIES 3 +#endif +#if IMAGE_BL1 +# if TRUSTED_BOARD_BOOT +# define PLAT_MARVELL_MMAP_ENTRIES 7 +# else +# define PLAT_MARVELL_MMAP_ENTRIES 6 +# endif /* TRUSTED_BOARD_BOOT */ +#endif +#if IMAGE_BL2 +# define PLAT_MARVELL_MMAP_ENTRIES 8 +#endif +#if IMAGE_BL31 +#define PLAT_MARVELL_MMAP_ENTRIES 5 +#endif + +/* + * Platform specific page table and MMU setup constants + */ +#if IMAGE_BL1 +#define MAX_XLAT_TABLES 4 +#elif IMAGE_BLE +# define MAX_XLAT_TABLES 4 +#elif IMAGE_BL2 +# define MAX_XLAT_TABLES 4 +#elif IMAGE_BL31 +# define MAX_XLAT_TABLES 4 +#elif IMAGE_BL32 +# define MAX_XLAT_TABLES 4 +#endif + +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */ + + +#endif /* __BOARD_MARVELL_DEF_H__ */ diff --git a/include/plat/marvell/a3700/common/marvell_def.h b/include/plat/marvell/a3700/common/marvell_def.h new file mode 100644 index 000000000..6c3a52487 --- /dev/null +++ b/include/plat/marvell/a3700/common/marvell_def.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef __MARVELL_DEF_H__ +#define __MARVELL_DEF_H__ + +#include <arch.h> +#include <common_def.h> +#include <platform_def.h> +#include <tbbr_img_def.h> +#include <xlat_tables.h> + + +/**************************************************************************** + * Definitions common to all MARVELL standard platforms + **************************************************************************** + */ +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define PLAT_MARVELL_NORTHB_COUNT 1 + +#define PLAT_MARVELL_CLUSTER_COUNT 1 + +#define MARVELL_CACHE_WRITEBACK_SHIFT 6 + +/* + * Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels. + * The power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +#define MARVELL_PWR_LVL0 MPIDR_AFFLVL0 +#define MARVELL_PWR_LVL1 MPIDR_AFFLVL1 +#define MARVELL_PWR_LVL2 MPIDR_AFFLVL2 + +/* + * Macros for local power states in Marvell platforms encoded by State-ID field + * within the power-state parameter. + */ +/* Local power state for power domains in Run state. */ +#define MARVELL_LOCAL_STATE_RUN 0 +/* Local power state for retention. Valid only for CPU power domains */ +#define MARVELL_LOCAL_STATE_RET 1 +/* Local power state for OFF/power-down. + * Valid for CPU and cluster power domains + */ +#define MARVELL_LOCAL_STATE_OFF 2 + +/* The first 4KB of Trusted SRAM are used as shared memory */ +#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE +#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE +#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ + +/* The remaining Trusted SRAM is used to load the BL images */ +#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \ + MARVELL_SHARED_RAM_SIZE) +#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \ + MARVELL_SHARED_RAM_SIZE) + +#define MARVELL_DRAM_BASE ULL(0x0) +#define MARVELL_DRAM_SIZE ULL(0x20000000) +#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \ + MARVELL_DRAM_SIZE - 1) + +#define MARVELL_IRQ_SEC_PHY_TIMER 29 + +#define MARVELL_IRQ_SEC_SGI_0 8 +#define MARVELL_IRQ_SEC_SGI_1 9 +#define MARVELL_IRQ_SEC_SGI_2 10 +#define MARVELL_IRQ_SEC_SGI_3 11 +#define MARVELL_IRQ_SEC_SGI_4 12 +#define MARVELL_IRQ_SEC_SGI_5 13 +#define MARVELL_IRQ_SEC_SGI_6 14 +#define MARVELL_IRQ_SEC_SGI_7 15 + +#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \ + MARVELL_SHARED_RAM_BASE, \ + MARVELL_SHARED_RAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \ + MARVELL_DRAM_BASE, \ + MARVELL_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + + +/* + * The number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#if USE_COHERENT_MEM +#define MARVELL_BL_REGIONS 3 +#else +#define MARVELL_BL_REGIONS 2 +#endif + +#define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \ + MARVELL_BL_REGIONS) + +#define MARVELL_CONSOLE_BAUDRATE 115200 + +/**************************************************************************** + * Required platform porting definitions common to all MARVELL std. platforms + **************************************************************************** + */ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +/* + * This macro defines the deepest retention state possible. A higher state + * id will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF + + +#define PLATFORM_CORE_COUNT PLAT_MARVELL_CLUSTER_CORE_COUNT + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT) + + +/***************************************************************************** + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ***************************************************************************** + */ +#define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE +#define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \ + + PLAT_MARVELL_TRUSTED_ROM_SIZE) +/* + * Put BL1 RW at the top of the Trusted SRAM. + */ +#define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ + MARVELL_BL_RAM_SIZE - \ + PLAT_MARVELL_MAX_BL1_RW_SIZE) +#define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE) + +/***************************************************************************** + * BL2 specific defines. + ***************************************************************************** + */ +/* + * Put BL2 just below BL31. + */ +#define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE) +#define BL2_LIMIT BL31_BASE + +/***************************************************************************** + * BL31 specific defines. + ***************************************************************************** + */ +/* + * Put BL31 at the top of the Trusted SRAM. + */ +#define BL31_BASE (MARVELL_BL_RAM_BASE + \ + MARVELL_BL_RAM_SIZE - \ + PLAT_MARVEL_MAX_BL31_SIZE) +#define BL31_PROGBITS_LIMIT BL1_RW_BASE +#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \ + MARVELL_BL_RAM_SIZE) + + +#endif /* __MARVELL_DEF_H__ */ diff --git a/include/plat/marvell/a3700/common/plat_marvell.h b/include/plat/marvell/a3700/common/plat_marvell.h new file mode 100644 index 000000000..f733d0473 --- /dev/null +++ b/include/plat/marvell/a3700/common/plat_marvell.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2016 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef __PLAT_MARVELL_H__ +#define __PLAT_MARVELL_H__ + +#include <bl_common.h> +#include <cassert.h> +#include <cpu_data.h> +#include <stdint.h> +#include <xlat_tables.h> + +/* + * Extern declarations common to Marvell standard platforms + */ +extern const mmap_region_t plat_marvell_mmap[]; + +#define MARVELL_CASSERT_MMAP \ + CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS) \ + <= MAX_MMAP_REGIONS, \ + assert_max_mmap_regions) + +/* + * Utility functions common to Marvell standard platforms + */ +void marvell_setup_page_tables(uintptr_t total_base, + size_t total_size, + uintptr_t code_start, + uintptr_t code_limit, + uintptr_t rodata_start, + uintptr_t rodata_limit +#if USE_COHERENT_MEM + , uintptr_t coh_start, + uintptr_t coh_limit +#endif +); + +/* IO storage utility functions */ +void marvell_io_setup(void); + +/* Systimer utility function */ +void marvell_configure_sys_timer(void); + +/* Topology utility function */ +int marvell_check_mpidr(u_register_t mpidr); + +/* BL1 utility functions */ +void marvell_bl1_early_platform_setup(void); +void marvell_bl1_platform_setup(void); +void marvell_bl1_plat_arch_setup(void); + +/* BL2 utility functions */ +void marvell_bl2_early_platform_setup(meminfo_t *mem_layout); +void marvell_bl2_platform_setup(void); +void marvell_bl2_plat_arch_setup(void); +uint32_t marvell_get_spsr_for_bl32_entry(void); +uint32_t marvell_get_spsr_for_bl33_entry(void); + +/* BL31 utility functions */ +void marvell_bl31_early_platform_setup(void *from_bl2, + uintptr_t soc_fw_config, + uintptr_t hw_config, + void *plat_params_from_bl2); +void marvell_bl31_platform_setup(void); +void marvell_bl31_plat_runtime_setup(void); +void marvell_bl31_plat_arch_setup(void); + +/* FIP TOC validity check */ +int marvell_io_is_toc_valid(void); + +/* + * PSCI functionality + */ +void marvell_psci_arch_init(int idx); +void plat_marvell_system_reset(void); + +/* + * Optional functions required in Marvell standard platforms + */ +void plat_marvell_io_setup(void); +int plat_marvell_get_alt_image_source( + unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +unsigned int plat_marvell_calc_core_pos(u_register_t mpidr); + +void plat_marvell_interconnect_init(void); +void plat_marvell_interconnect_enter_coherency(void); + +const mmap_region_t *plat_marvell_get_mmap(void); + +#endif /* __PLAT_MARVELL_H__ */ diff --git a/include/plat/marvell/a8k/common/armada_common.h b/include/plat/marvell/a8k/common/armada_common.h index e72746792..c1e37f58a 100644 --- a/include/plat/marvell/a8k/common/armada_common.h +++ b/include/plat/marvell/a8k/common/armada_common.h @@ -5,8 +5,8 @@ * https://spdx.org/licenses */ -#ifndef __A8K_COMMON_H__ -#define __A8K_COMMON_H__ +#ifndef __ARMADA_COMMON_H__ +#define __ARMADA_COMMON_H__ #include <amb_adec.h> #include <io_win.h> diff --git a/include/plat/marvell/common/aarch64/marvell_macros.S b/include/plat/marvell/common/aarch64/marvell_macros.S index 0102af042..faf10705f 100644 --- a/include/plat/marvell/common/aarch64/marvell_macros.S +++ b/include/plat/marvell/common/aarch64/marvell_macros.S @@ -45,7 +45,7 @@ spacer: * Clobbers: x0 - x10, sp * --------------------------------------------- */ - .macro arm_print_gic_regs + .macro marvell_print_gic_regs /* Check for GICv3 system register access */ mrs x7, id_aa64pfr0_el1 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH diff --git a/include/plat/marvell/common/mvebu.h b/include/plat/marvell/common/mvebu.h index a20e538e3..a7d6c3fc2 100644 --- a/include/plat/marvell/common/mvebu.h +++ b/include/plat/marvell/common/mvebu.h @@ -32,7 +32,8 @@ #define ROUND_UP_TO_POW_OF_2(number) (1 << \ (32 - __builtin_clz((number) - 1))) -#define _1MB_ (1024ULL*1024ULL) -#define _1GB_ (_1MB_*1024ULL) +#define _1MB_ (1024ULL * 1024ULL) +#define _1GB_ (_1MB_ * 1024ULL) +#define _2GB_ (2 * _1GB_) #endif /* MVEBU_H */ |