diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/arm/pl011/aarch32/pl011_console.S | 3 | ||||
| -rw-r--r-- | drivers/arm/pl011/aarch64/pl011_console.S | 3 | ||||
| -rw-r--r-- | drivers/arm/tzc/tzc400.c | 60 | ||||
| -rw-r--r-- | drivers/arm/tzc/tzc_common_private.h | 62 | ||||
| -rw-r--r-- | drivers/arm/tzc/tzc_dmc500.c | 20 | ||||
| -rw-r--r-- | drivers/cadence/uart/aarch64/cdns_console.S | 4 | ||||
| -rw-r--r-- | drivers/console/aarch64/skeleton_console.S | 9 | ||||
| -rw-r--r-- | drivers/coreboot/cbmem_console/aarch64/cbmem_console.S | 3 | ||||
| -rw-r--r-- | drivers/meson/console/aarch64/meson_console.S | 264 | ||||
| -rw-r--r-- | drivers/ti/uart/aarch64/16550_console.S | 3 |
10 files changed, 354 insertions, 77 deletions
diff --git a/drivers/arm/pl011/aarch32/pl011_console.S b/drivers/arm/pl011/aarch32/pl011_console.S index 841ea446c..46ff22587 100644 --- a/drivers/arm/pl011/aarch32/pl011_console.S +++ b/drivers/arm/pl011/aarch32/pl011_console.S @@ -6,6 +6,7 @@ #include <arch.h> #include <asm_macros.S> #include <assert_macros.S> +#define USE_FINISH_CONSOLE_REG_2 #include <console_macros.S> #include <pl011.h> @@ -116,7 +117,7 @@ func console_pl011_register mov r0, r4 pop {r4, lr} - finish_console_register pl011 + finish_console_register pl011 putc=1, getc=1, flush=1 register_fail: pop {r4, pc} diff --git a/drivers/arm/pl011/aarch64/pl011_console.S b/drivers/arm/pl011/aarch64/pl011_console.S index d6a2d6b89..3886f3b77 100644 --- a/drivers/arm/pl011/aarch64/pl011_console.S +++ b/drivers/arm/pl011/aarch64/pl011_console.S @@ -6,6 +6,7 @@ #include <arch.h> #include <asm_macros.S> #include <assert_macros.S> +#define USE_FINISH_CONSOLE_REG_2 #include <console_macros.S> #include <pl011.h> @@ -110,7 +111,7 @@ func console_pl011_register mov x0, x6 mov x30, x7 - finish_console_register pl011 + finish_console_register pl011 putc=1, getc=1, flush=1 register_fail: ret x7 diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c index db4f88a9b..763eba73c 100644 --- a/drivers/arm/tzc/tzc400.c +++ b/drivers/arm/tzc/tzc400.c @@ -14,12 +14,12 @@ /* * Macros which will be used by common core functions. */ -#define TZC_400_REGION_BASE_LOW_0_OFFSET 0x100 -#define TZC_400_REGION_BASE_HIGH_0_OFFSET 0x104 -#define TZC_400_REGION_TOP_LOW_0_OFFSET 0x108 -#define TZC_400_REGION_TOP_HIGH_0_OFFSET 0x10c -#define TZC_400_REGION_ATTR_0_OFFSET 0x110 -#define TZC_400_REGION_ID_ACCESS_0_OFFSET 0x114 +#define TZC_400_REGION_BASE_LOW_0_OFFSET U(0x100) +#define TZC_400_REGION_BASE_HIGH_0_OFFSET U(0x104) +#define TZC_400_REGION_TOP_LOW_0_OFFSET U(0x108) +#define TZC_400_REGION_TOP_HIGH_0_OFFSET U(0x10c) +#define TZC_400_REGION_ATTR_0_OFFSET U(0x110) +#define TZC_400_REGION_ID_ACCESS_0_OFFSET U(0x114) /* * Implementation defined values used to validate inputs later. @@ -88,10 +88,10 @@ static void _tzc400_set_gate_keeper(uintptr_t base, /* Upper half is current state. Lower half is requested state. */ open_status = get_gate_keeper_os(base); - if (val) - open_status |= (1 << filter); + if (val != 0) + open_status |= (1U << filter); else - open_status &= ~(1 << filter); + open_status &= ~(1U << filter); _tzc400_write_gate_keeper(base, (open_status & GATE_KEEPER_OR_MASK) << GATE_KEEPER_OR_SHIFT); @@ -101,9 +101,9 @@ static void _tzc400_set_gate_keeper(uintptr_t base, ; } -void tzc400_set_action(tzc_action_t action) +void tzc400_set_action(unsigned int action) { - assert(tzc400.base); + assert(tzc400.base != 0U); assert(action <= TZC_ACTION_ERR_INT); /* @@ -121,7 +121,7 @@ void tzc400_init(uintptr_t base) #endif unsigned int tzc400_build; - assert(base); + assert(base != 0U); tzc400.base = base; #if DEBUG @@ -134,12 +134,12 @@ void tzc400_init(uintptr_t base) /* Save values we will use later. */ tzc400_build = _tzc400_read_build_config(tzc400.base); - tzc400.num_filters = ((tzc400_build >> BUILD_CONFIG_NF_SHIFT) & - BUILD_CONFIG_NF_MASK) + 1; - tzc400.addr_width = ((tzc400_build >> BUILD_CONFIG_AW_SHIFT) & - BUILD_CONFIG_AW_MASK) + 1; - tzc400.num_regions = ((tzc400_build >> BUILD_CONFIG_NR_SHIFT) & - BUILD_CONFIG_NR_MASK) + 1; + tzc400.num_filters = (uint8_t)((tzc400_build >> BUILD_CONFIG_NF_SHIFT) & + BUILD_CONFIG_NF_MASK) + 1U; + tzc400.addr_width = (uint8_t)((tzc400_build >> BUILD_CONFIG_AW_SHIFT) & + BUILD_CONFIG_AW_MASK) + 1U; + tzc400.num_regions = (uint8_t)((tzc400_build >> BUILD_CONFIG_NR_SHIFT) & + BUILD_CONFIG_NR_MASK) + 1U; } /* @@ -148,10 +148,10 @@ void tzc400_init(uintptr_t base) * to any other region, and is enabled on all filters; this cannot be * changed. This function only changes the access permissions. */ -void tzc400_configure_region0(tzc_region_attributes_t sec_attr, +void tzc400_configure_region0(unsigned int sec_attr, unsigned int ns_device_access) { - assert(tzc400.base); + assert(tzc400.base != 0U); assert(sec_attr <= TZC_REGION_S_RDWR); _tzc400_configure_region0(tzc400.base, sec_attr, ns_device_access); @@ -166,17 +166,17 @@ void tzc400_configure_region0(tzc_region_attributes_t sec_attr, * for this region (see comment for that function). */ void tzc400_configure_region(unsigned int filters, - int region, + unsigned int region, unsigned long long region_base, unsigned long long region_top, - tzc_region_attributes_t sec_attr, + unsigned int sec_attr, unsigned int nsaid_permissions) { - assert(tzc400.base); + assert(tzc400.base != 0U); /* Do range checks on filters and regions. */ - assert(((filters >> tzc400.num_filters) == 0) && - (region >= 0) && (region < tzc400.num_regions)); + assert(((filters >> tzc400.num_filters) == 0U) && + (region < tzc400.num_regions)); /* * Do address range check based on TZC configuration. A 64bit address is @@ -186,7 +186,7 @@ void tzc400_configure_region(unsigned int filters, (region_base < region_top))); /* region_base and (region_top + 1) must be 4KB aligned */ - assert(((region_base | (region_top + 1)) & (4096 - 1)) == 0); + assert(((region_base | (region_top + 1U)) & (4096U - 1U)) == 0U); assert(sec_attr <= TZC_REGION_S_RDWR); @@ -200,11 +200,11 @@ void tzc400_enable_filters(void) unsigned int state; unsigned int filter; - assert(tzc400.base); + assert(tzc400.base != 0U); - for (filter = 0; filter < tzc400.num_filters; filter++) { + for (filter = 0U; filter < tzc400.num_filters; filter++) { state = _tzc400_get_gate_keeper(tzc400.base, filter); - if (state) { + if (state != 0U) { /* * The TZC filter is already configured. Changing the * programmer's view in an active system can cause @@ -227,7 +227,7 @@ void tzc400_disable_filters(void) { unsigned int filter; - assert(tzc400.base); + assert(tzc400.base != 0U); /* * We don't do the same state check as above as the Gatekeepers are diff --git a/drivers/arm/tzc/tzc_common_private.h b/drivers/arm/tzc/tzc_common_private.h index e1b7727aa..5fbea92b6 100644 --- a/drivers/arm/tzc/tzc_common_private.h +++ b/drivers/arm/tzc/tzc_common_private.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __TZC_COMMON_PRIVATE_H__ -#define __TZC_COMMON_PRIVATE_H__ +#ifndef TZC_COMMON_PRIVATE_H +#define TZC_COMMON_PRIVATE_H #include <arch.h> #include <arch_helpers.h> @@ -15,7 +15,7 @@ #define DEFINE_TZC_COMMON_WRITE_ACTION(fn_name, macro_name) \ static inline void _tzc##fn_name##_write_action( \ uintptr_t base, \ - tzc_action_t action) \ + unsigned int action) \ { \ mmio_write_32(base + TZC_##macro_name##_ACTION_OFF, \ action); \ @@ -24,7 +24,7 @@ #define DEFINE_TZC_COMMON_WRITE_REGION_BASE(fn_name, macro_name) \ static inline void _tzc##fn_name##_write_region_base( \ uintptr_t base, \ - int region_no, \ + unsigned int region_no, \ unsigned long long region_base) \ { \ mmio_write_32(base + \ @@ -44,7 +44,7 @@ #define DEFINE_TZC_COMMON_WRITE_REGION_TOP(fn_name, macro_name) \ static inline void _tzc##fn_name##_write_region_top( \ uintptr_t base, \ - int region_no, \ + unsigned int region_no, \ unsigned long long region_top) \ { \ mmio_write_32(base + \ @@ -52,19 +52,19 @@ (TZC_##macro_name##_REGION_SIZE, \ region_no) + \ TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \ - (uint32_t)region_top); \ + (uint32_t)region_top); \ mmio_write_32(base + \ TZC_REGION_OFFSET( \ TZC_##macro_name##_REGION_SIZE, \ region_no) + \ TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \ - (uint32_t)(region_top >> 32)); \ + (uint32_t)(region_top >> 32)); \ } #define DEFINE_TZC_COMMON_WRITE_REGION_ATTRIBUTES(fn_name, macro_name) \ static inline void _tzc##fn_name##_write_region_attributes( \ uintptr_t base, \ - int region_no, \ + unsigned int region_no, \ unsigned int attr) \ { \ mmio_write_32(base + \ @@ -78,7 +78,7 @@ #define DEFINE_TZC_COMMON_WRITE_REGION_ID_ACCESS(fn_name, macro_name) \ static inline void _tzc##fn_name##_write_region_id_access( \ uintptr_t base, \ - int region_no, \ + unsigned int region_no, \ unsigned int val) \ { \ mmio_write_32(base + \ @@ -94,13 +94,13 @@ */ #define DEFINE_TZC_COMMON_CONFIGURE_REGION0(fn_name) \ static void _tzc##fn_name##_configure_region0(uintptr_t base, \ - tzc_region_attributes_t sec_attr, \ + unsigned int sec_attr, \ unsigned int ns_device_access) \ { \ - assert(base); \ + assert(base != 0U); \ VERBOSE("TrustZone : Configuring region 0 " \ - "(TZC Interface Base=%p sec_attr=0x%x," \ - " ns_devs=0x%x)\n", (void *)base, \ + "(TZC Interface Base=0x%lx sec_attr=0x%x," \ + " ns_devs=0x%x)\n", base, \ sec_attr, ns_device_access); \ \ /* Set secure attributes on region 0 */ \ @@ -126,18 +126,18 @@ #define DEFINE_TZC_COMMON_CONFIGURE_REGION(fn_name) \ static void _tzc##fn_name##_configure_region(uintptr_t base, \ unsigned int filters, \ - int region_no, \ + unsigned int region_no, \ unsigned long long region_base, \ unsigned long long region_top, \ - tzc_region_attributes_t sec_attr, \ - unsigned int nsaid_permissions) \ + unsigned int sec_attr, \ + unsigned int nsaid_permissions) \ { \ - assert(base); \ + assert(base != 0U); \ VERBOSE("TrustZone : Configuring region " \ - "(TZC Interface Base: %p, region_no = %d)" \ - "...\n", (void *)base, region_no); \ + "(TZC Interface Base: 0x%lx, region_no = %u)" \ + "...\n", base, region_no); \ VERBOSE("TrustZone : ... base = %llx, top = %llx," \ - "\n", region_base, region_top);\ + "\n", region_base, region_top); \ VERBOSE("TrustZone : ... sec_attr = 0x%x," \ " ns_devs = 0x%x)\n", \ sec_attr, nsaid_permissions); \ @@ -175,42 +175,44 @@ static inline unsigned int _tzc_read_peripheral_id(uintptr_t base) id = mmio_read_32(base + PID0_OFF); /* Masks DESC part in PID1 */ - id |= ((mmio_read_32(base + PID1_OFF) & 0xF) << 8); + id |= ((mmio_read_32(base + PID1_OFF) & 0xFU) << 8U); return id; } #if ENABLE_ASSERTIONS #ifdef AARCH32 -static inline unsigned long long _tzc_get_max_top_addr(int addr_width) +static inline unsigned long long _tzc_get_max_top_addr(unsigned int addr_width) { /* * Assume at least 32 bit wide address and initialize the max. * This function doesn't use 64-bit integer arithmetic to avoid * having to implement additional compiler library functions. */ - unsigned long long addr_mask = 0xFFFFFFFF; + unsigned long long addr_mask = 0xFFFFFFFFU; uint32_t *addr_ptr = (uint32_t *)&addr_mask; - assert(addr_width >= 32); + assert(addr_width >= 32U); /* This logic works only on little - endian platforms */ - assert((read_sctlr() & SCTLR_EE_BIT) == 0); + assert((read_sctlr() & SCTLR_EE_BIT) == 0U); /* * If required address width is greater than 32, populate the higher * 32 bits of the 64 bit field with the max address. */ - if (addr_width > 32) - *(addr_ptr + 1) = ((1 << (addr_width - 32)) - 1); + if (addr_width > 32U) + *(addr_ptr + 1U) = ((1U << (addr_width - 32U)) - 1U); return addr_mask; } #else -#define _tzc_get_max_top_addr(addr_width)\ - (UINT64_MAX >> (64 - (addr_width))) +static inline unsigned long long _tzc_get_max_top_addr(unsigned int addr_width) +{ + return UINT64_MAX >> (64U - addr_width); +} #endif /* AARCH32 */ #endif /* ENABLE_ASSERTIONS */ -#endif /* __TZC_COMMON_PRIVATE_H__ */ +#endif /* TZC_COMMON_PRIVATE_H */ diff --git a/drivers/arm/tzc/tzc_dmc500.c b/drivers/arm/tzc/tzc_dmc500.c index 8b618e6d7..3e6c7838c 100644 --- a/drivers/arm/tzc/tzc_dmc500.c +++ b/drivers/arm/tzc/tzc_dmc500.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -36,7 +36,7 @@ static unsigned int g_sys_if_count; * Structure for configured regions attributes in DMC500. */ typedef struct tzc_dmc500_regions { - tzc_region_attributes_t sec_attr; + unsigned int sec_attr; int is_enabled; } tzc_dmc500_regions_t; @@ -63,7 +63,7 @@ DEFINE_TZC_COMMON_CONFIGURE_REGION(_dmc500) static inline unsigned int _tzc_dmc500_read_region_attr_0( uintptr_t dmc_si_base, - int region_no) + unsigned int region_no) { return mmio_read_32(dmc_si_base + TZC_REGION_OFFSET(TZC_DMC500_REGION_SIZE, region_no) + @@ -144,8 +144,8 @@ int tzc_dmc500_verify_complete(void) * and is always enabled; this cannot be changed. This function only changes * the access permissions. */ -void tzc_dmc500_configure_region0(tzc_region_attributes_t sec_attr, - unsigned int nsaid_permissions) +void tzc_dmc500_configure_region0(unsigned int sec_attr, + unsigned int nsaid_permissions) { int dmc_inst, sys_if; @@ -172,17 +172,17 @@ void tzc_dmc500_configure_region0(tzc_region_attributes_t sec_attr, * Region 0 is special; it is preferable to use tzc_dmc500_configure_region0 * for this region (see comment for that function). */ -void tzc_dmc500_configure_region(int region_no, +void tzc_dmc500_configure_region(unsigned int region_no, unsigned long long region_base, unsigned long long region_top, - tzc_region_attributes_t sec_attr, + unsigned int sec_attr, unsigned int nsaid_permissions) { int dmc_inst, sys_if; assert(g_driver_data); /* Do range checks on regions. */ - assert(region_no >= 0 && region_no <= MAX_REGION_VAL); + assert((region_no >= 0U) && (region_no <= MAX_REGION_VAL)); /* * Do address range check based on DMC-TZ configuration. A 43bit address @@ -192,7 +192,7 @@ void tzc_dmc500_configure_region(int region_no, (region_base < region_top))); /* region_base and (region_top + 1) must be 4KB aligned */ - assert(((region_base | (region_top + 1)) & (4096 - 1)) == 0); + assert(((region_base | (region_top + 1U)) & (4096U - 1U)) == 0U); for (dmc_inst = 0; dmc_inst < g_driver_data->dmc_count; dmc_inst++) { assert(DMC_INST_BASE_ADDR(dmc_inst)); @@ -209,7 +209,7 @@ void tzc_dmc500_configure_region(int region_no, } /* Sets the action value for all the DMC instances */ -void tzc_dmc500_set_action(tzc_action_t action) +void tzc_dmc500_set_action(unsigned int action) { int dmc_inst; diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S index 71359a6d2..8f46a6272 100644 --- a/drivers/cadence/uart/aarch64/cdns_console.S +++ b/drivers/cadence/uart/aarch64/cdns_console.S @@ -7,6 +7,8 @@ #include <asm_macros.S> #include <assert_macros.S> #include <cadence/cdns_uart.h> +#define USE_FINISH_CONSOLE_REG_2 +#include <console_macros.S> /* * "core" functions are low-level implementations that don't require @@ -77,7 +79,7 @@ func console_cdns_register mov x0, x6 mov x30, v7 - finish_console_register cdns + finish_console_register cdns putc=1, getc=1, flush=1 register_fail: ret x7 diff --git a/drivers/console/aarch64/skeleton_console.S b/drivers/console/aarch64/skeleton_console.S index 1b5d7393c..3993eef99 100644 --- a/drivers/console/aarch64/skeleton_console.S +++ b/drivers/console/aarch64/skeleton_console.S @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ #include <asm_macros.S> +#define USE_FINISH_CONSOLE_REG_2 #include <console_macros.S> /* @@ -60,8 +61,12 @@ func console_xxx_register * Keep console_t pointer in x0 for later. */ - /* Macro to finish up registration and return (needs valid x0 + x30). */ - finish_console_register xxx + /* + * Macro to finish up registration and return (needs valid x0 + x30). + * If any of the argument is unspecified, then the corresponding + * entry in console_t is set to 0. + */ + finish_console_register xxx putc=1, getc=1, flush=1 /* Jump here if hardware init fails or parameters are invalid. */ register_fail: diff --git a/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S b/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S index 184853d9d..89be349c0 100644 --- a/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S +++ b/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S @@ -6,6 +6,7 @@ #include <asm_macros.S> #include <cbmem_console.h> +#define USE_FINISH_CONSOLE_REG_2 #include <console_macros.S> /* @@ -39,7 +40,7 @@ func console_cbmc_register ldr w2, [x0] str w2, [x1, #CONSOLE_T_CBMC_SIZE] mov x0, x1 - finish_console_register cbmc + finish_console_register cbmc putc=1, flush=1 endfunc console_cbmc_register /* ----------------------------------------------- diff --git a/drivers/meson/console/aarch64/meson_console.S b/drivers/meson/console/aarch64/meson_console.S new file mode 100644 index 000000000..eaee10ef1 --- /dev/null +++ b/drivers/meson/console/aarch64/meson_console.S @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include <assert_macros.S> +#define USE_FINISH_CONSOLE_REG_2 +#include <console_macros.S> +#include <meson_console.h> + + .globl console_meson_register + .globl console_meson_init + .globl console_meson_putc + .globl console_meson_getc + .globl console_meson_flush + .globl console_meson_core_putc + .globl console_meson_core_getc + .globl console_meson_core_flush + + /* ----------------------------------------------- + * Hardware definitions + * ----------------------------------------------- + */ +#define MESON_WFIFO_OFFSET 0x0 +#define MESON_RFIFO_OFFSET 0x4 +#define MESON_CONTROL_OFFSET 0x8 +#define MESON_STATUS_OFFSET 0xC +#define MESON_MISC_OFFSET 0x10 +#define MESON_REG5_OFFSET 0x14 + +#define MESON_CONTROL_CLR_ERROR_BIT 24 +#define MESON_CONTROL_RX_RESET_BIT 23 +#define MESON_CONTROL_TX_RESET_BIT 22 +#define MESON_CONTROL_RX_ENABLE_BIT 13 +#define MESON_CONTROL_TX_ENABLE_BIT 12 + +#define MESON_STATUS_RX_EMPTY_BIT 20 +#define MESON_STATUS_TX_FULL_BIT 21 +#define MESON_STATUS_TX_EMPTY_BIT 22 + +#define MESON_REG5_USE_XTAL_CLK_BIT 24 +#define MESON_REG5_USE_NEW_RATE_BIT 23 +#define MESON_REG5_NEW_BAUD_RATE_MASK 0x7FFFFF + + /* ----------------------------------------------- + * int console_meson_register(uintptr_t base, + * uint32_t clk, uint32_t baud, + * console_meson_t *console); + * Function to initialize and register a new MESON + * console. Storage passed in for the console struct + * *must* be persistent (i.e. not from the stack). + * In: x0 - UART register base address + * w1 - UART clock in Hz + * w2 - Baud rate + * x3 - pointer to empty console_meson_t struct + * Out: return 1 on success, 0 on error + * Clobber list : x0, x1, x2, x6, x7, x14 + * ----------------------------------------------- + */ +func console_meson_register + mov x7, x30 + mov x6, x3 + cbz x6, register_fail + str x0, [x6, #CONSOLE_T_MESON_BASE] + + bl console_meson_init + cbz x0, register_fail + + mov x0, x6 + mov x30, x7 + finish_console_register meson putc=1, getc=1, flush=1 + +register_fail: + ret x7 +endfunc console_meson_register + + /* ----------------------------------------------- + * int console_meson_init(uintptr_t base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : x0-x3 + * ----------------------------------------------- + */ +func console_meson_init + cmp w0, #0 + beq init_fail + mov_imm w3, 24000000 /* TODO: This only works with a 24 MHz clock. */ + cmp w1, w3 + bne init_fail + cmp w2, #0 + beq init_fail + /* Set baud rate: value = ((clock / 3) / baudrate) - 1 */ + mov w3, #3 + udiv w3, w1, w3 + udiv w3, w3, w2 + sub w3, w3, #1 + orr w3, w3, #((1 << MESON_REG5_USE_XTAL_CLK_BIT) | \ + (1 << MESON_REG5_USE_NEW_RATE_BIT)) + str w3, [x0, #MESON_REG5_OFFSET] + /* Reset UART and clear error flag */ + ldr w3, [x0, #MESON_CONTROL_OFFSET] + orr w3, w3, #((1 << MESON_CONTROL_CLR_ERROR_BIT) | \ + (1 << MESON_CONTROL_RX_RESET_BIT) | \ + (1 << MESON_CONTROL_TX_RESET_BIT)) + str w3, [x0, #MESON_CONTROL_OFFSET] + bic w3, w3, #((1 << MESON_CONTROL_CLR_ERROR_BIT) | \ + (1 << MESON_CONTROL_RX_RESET_BIT) | \ + (1 << MESON_CONTROL_TX_RESET_BIT)) + str w3, [x0, #MESON_CONTROL_OFFSET] + /* Enable transfer and receive FIFO */ + orr w3, w3, #((1 << MESON_CONTROL_RX_ENABLE_BIT) | \ + (1 << MESON_CONTROL_TX_ENABLE_BIT)) + str w3, [x0, #MESON_CONTROL_OFFSET] + /* Success */ + mov w0, #1 + ret +init_fail: + mov w0, wzr + ret +endfunc console_meson_init + + /* -------------------------------------------------------- + * int console_meson_putc(int c, console_meson_t *console) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - pointer to console_t structure + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_meson_putc +#if ENABLE_ASSERTIONS + cmp x1, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x1, [x1, #CONSOLE_T_MESON_BASE] + b console_meson_core_putc +endfunc console_meson_putc + + /* -------------------------------------------------------- + * int console_meson_core_putc(int c, uintptr_t base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_meson_core_putc +#if ENABLE_ASSERTIONS + cmp x1, #0 + ASM_ASSERT(ne) +#endif + /* Prepend '\r' to '\n' */ + cmp w0, #0xA + b.ne 2f + /* Wait until the transmit FIFO isn't full */ +1: ldr w2, [x1, #MESON_STATUS_OFFSET] + tbnz w2, #MESON_STATUS_TX_FULL_BIT, 1b + /* Write '\r' if needed */ + mov w2, #0xD + str w2, [x1, #MESON_WFIFO_OFFSET] + /* Wait until the transmit FIFO isn't full */ +2: ldr w2, [x1, #MESON_STATUS_OFFSET] + tbnz w2, #MESON_STATUS_TX_FULL_BIT, 2b + /* Write input character */ + str w0, [x1, #MESON_WFIFO_OFFSET] + ret +endfunc console_meson_core_putc + + /* --------------------------------------------- + * int console_meson_getc(console_meson_t *console) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 if no character is available. + * In : x0 - pointer to console_t structure + * Out: w0 - character if available, else -1 + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_meson_getc +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x0, [x0, #CONSOLE_T_MESON_BASE] + b console_meson_core_getc +endfunc console_meson_getc + + /* --------------------------------------------- + * int console_meson_core_getc(uintptr_t base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 if no character is available. + * In : x0 - console base address + * Out: w0 - character if available, else -1 + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_meson_core_getc +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif + /* Is the receive FIFO empty? */ + ldr w1, [x0, #MESON_STATUS_OFFSET] + tbnz w1, #MESON_STATUS_RX_EMPTY_BIT, 1f + /* Read one character from the RX FIFO */ + ldr w0, [x0, #MESON_RFIFO_OFFSET] + ret +1: + mov w0, #ERROR_NO_PENDING_CHAR + ret +endfunc console_meson_core_getc + + /* --------------------------------------------- + * int console_meson_flush(console_meson_t *console) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - pointer to console_t structure + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_meson_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x0, [x0, #CONSOLE_T_MESON_BASE] + b console_meson_core_flush +endfunc console_meson_flush + + /* --------------------------------------------- + * int console_meson_core_flush(uintptr_t base_addr) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - console base address + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_meson_core_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif + /* Wait until the transmit FIFO is empty */ +1: ldr w1, [x0, #MESON_STATUS_OFFSET] + tbz w1, #MESON_STATUS_TX_EMPTY_BIT, 1b + mov w0, #0 + ret +endfunc console_meson_core_flush diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S index 0f9a9d576..785b640dd 100644 --- a/drivers/ti/uart/aarch64/16550_console.S +++ b/drivers/ti/uart/aarch64/16550_console.S @@ -7,6 +7,7 @@ #include <arch.h> #include <asm_macros.S> #include <assert_macros.S> +#define USE_FINISH_CONSOLE_REG_2 #include <console_macros.S> #include <uart_16550.h> @@ -112,7 +113,7 @@ func console_16550_register mov x0, x6 mov x30, x7 - finish_console_register 16550 + finish_console_register 16550 putc=1, getc=1, flush=1 register_fail: ret x7 |