diff options
Diffstat (limited to 'drivers')
28 files changed, 87 insertions, 1420 deletions
diff --git a/drivers/allwinner/sunxi_i2c.c b/drivers/allwinner/sunxi_i2c.c deleted file mode 100644 index cc91ca58a..000000000 --- a/drivers/allwinner/sunxi_i2c.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io> - * - * SPDX-License-Identifier: BSD-3-Clause - * https://spdx.org/licenses - */ - -/* This driver provides I2C support for Allwinner sunXi SoCs */ - -#include <mmio.h> - -#define CONFIG_SYS_TCLK 24000000 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0 - -#define I2C_INTERRUPT_CLEAR_INVERTED - -struct mentor_i2c_regs { - uint32_t slave_address; - uint32_t xtnd_slave_addr; - uint32_t data; - uint32_t control; - uint32_t status; - uint32_t baudrate; - uint32_t soft_reset; -}; - -#include "../mentor/i2c/mi2cv.c" diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c index 91245d46c..605971cac 100644 --- a/drivers/arm/cci/cci.c +++ b/drivers/arm/cci/cci.c @@ -107,7 +107,8 @@ static int get_slave_ports(unsigned int part_num) } #endif /* ENABLE_ASSERTIONS */ -void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters) +void __init cci_init(uintptr_t base, const int *map, + unsigned int num_cci_masters) { assert(map != NULL); assert(base != 0U); diff --git a/drivers/arm/cci400/cci400.c b/drivers/arm/cci400/cci400.c deleted file mode 100644 index 402e5e196..000000000 --- a/drivers/arm/cci400/cci400.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <assert.h> -#include <cci400.h> -#include <debug.h> -#include <mmio.h> -#include <stdint.h> - -#define MAX_CLUSTERS 2 - -static uintptr_t cci_base_addr; -static unsigned int cci_cluster_ix_to_iface[MAX_CLUSTERS]; - - -void cci_init(uintptr_t cci_base, - int slave_iface3_cluster_ix, - int slave_iface4_cluster_ix) -{ - /* - * Check the passed arguments are valid. The cluster indices must be - * less than MAX_CLUSTERS, not the same as each other and at least one - * of them must refer to a valid cluster index. - */ - assert(cci_base); - assert(slave_iface3_cluster_ix < MAX_CLUSTERS); - assert(slave_iface4_cluster_ix < MAX_CLUSTERS); - assert(slave_iface3_cluster_ix != slave_iface4_cluster_ix); - assert((slave_iface3_cluster_ix >= 0) || - (slave_iface4_cluster_ix >= 0)); - - WARN("Please migrate to common cci driver, This driver will be" \ - " deprecated in future\n"); - - cci_base_addr = cci_base; - if (slave_iface3_cluster_ix >= 0) - cci_cluster_ix_to_iface[slave_iface3_cluster_ix] = - SLAVE_IFACE3_OFFSET; - if (slave_iface4_cluster_ix >= 0) - cci_cluster_ix_to_iface[slave_iface4_cluster_ix] = - SLAVE_IFACE4_OFFSET; -} - -static inline unsigned long get_slave_iface_base(unsigned long mpidr) -{ - /* - * We assume the TF topology code allocates affinity instances - * consecutively from zero. - * It is a programming error if this is called without initializing - * the slave interface to use for this cluster. - */ - unsigned int cluster_id = - (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - - assert(cluster_id < MAX_CLUSTERS); - assert(cci_cluster_ix_to_iface[cluster_id] != 0); - - return cci_base_addr + cci_cluster_ix_to_iface[cluster_id]; -} - -void cci_enable_cluster_coherency(unsigned long mpidr) -{ - assert(cci_base_addr); - /* Enable Snoops and DVM messages */ - mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, - DVM_EN_BIT | SNOOP_EN_BIT); - - /* Wait for the dust to settle down */ - while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT) - ; -} - -void cci_disable_cluster_coherency(unsigned long mpidr) -{ - assert(cci_base_addr); - /* Disable Snoops and DVM messages */ - mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, - ~(DVM_EN_BIT | SNOOP_EN_BIT)); - - /* Wait for the dust to settle down */ - while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT) - ; -} - diff --git a/drivers/arm/ccn/ccn.c b/drivers/arm/ccn/ccn.c index afb7d9d3b..910cd7cd2 100644 --- a/drivers/arm/ccn/ccn.c +++ b/drivers/arm/ccn/ccn.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -167,7 +167,7 @@ static unsigned int ccn_get_rn_master_info(uintptr_t periphbase, * It compares this with the information provided by the platform to determine * the validity of the latter. ******************************************************************************/ -static void ccn_validate_plat_params(const ccn_desc_t *plat_desc) +static void __init ccn_validate_plat_params(const ccn_desc_t *plat_desc) { unsigned int master_id, num_rn_masters; rn_info_t info = { {0} }; @@ -208,7 +208,7 @@ static void ccn_validate_plat_params(const ccn_desc_t *plat_desc) * simultaneous CCN operations at runtime (only BL31) to add and remove Request * nodes from coherency. ******************************************************************************/ -void ccn_init(const ccn_desc_t *plat_desc) +void __init ccn_init(const ccn_desc_t *plat_desc) { #if ENABLE_ASSERTIONS ccn_validate_plat_params(plat_desc); diff --git a/drivers/arm/gic/arm_gic.c b/drivers/arm/gic/arm_gic.c deleted file mode 100644 index e040e0aca..000000000 --- a/drivers/arm/gic/arm_gic.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <arch_helpers.h> -#include <arm_gic.h> -#include <assert.h> -#include <bl_common.h> -#include <debug.h> -#include <gic_v2.h> -#include <gic_v3.h> -#include <interrupt_mgmt.h> -#include <platform.h> -#include <stdint.h> - -/* Value used to initialize Non-Secure IRQ priorities four at a time */ -#define GICD_IPRIORITYR_DEF_VAL \ - (GIC_HIGHEST_NS_PRIORITY | \ - (GIC_HIGHEST_NS_PRIORITY << 8) | \ - (GIC_HIGHEST_NS_PRIORITY << 16) | \ - (GIC_HIGHEST_NS_PRIORITY << 24)) - -static uintptr_t g_gicc_base; -static uintptr_t g_gicd_base; -static uintptr_t g_gicr_base; -static const unsigned int *g_irq_sec_ptr; -static unsigned int g_num_irqs; - - -/******************************************************************************* - * This function does some minimal GICv3 configuration. The Firmware itself does - * not fully support GICv3 at this time and relies on GICv2 emulation as - * provided by GICv3. This function allows software (like Linux) in later stages - * to use full GICv3 features. - ******************************************************************************/ -static void gicv3_cpuif_setup(void) -{ - unsigned int val; - uintptr_t base; - - /* - * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep - * bit set. In order to allow interrupts to get routed to the CPU we - * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep - * to clear (GICv3 Architecture specification 5.4.23). - * GICR_WAKER is NOT banked per CPU, compute the correct base address - * per CPU. - */ - assert(g_gicr_base); - base = gicv3_get_rdist(g_gicr_base, read_mpidr()); - if (base == (uintptr_t)NULL) { - /* No re-distributor base address. This interface cannot be - * configured. - */ - panic(); - } - - val = gicr_read_waker(base); - - val &= ~WAKER_PS; - gicr_write_waker(base, val); - dsb(); - - /* We need to wait for ChildrenAsleep to clear. */ - val = gicr_read_waker(base); - while (val & WAKER_CA) - val = gicr_read_waker(base); - - val = read_icc_sre_el3(); - write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE); - isb(); -} - -/******************************************************************************* - * This function does some minimal GICv3 configuration when cores go - * down. - ******************************************************************************/ -static void gicv3_cpuif_deactivate(void) -{ - unsigned int val; - uintptr_t base; - - /* - * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and - * wait for GICR_WAKER.ChildrenAsleep to get set. - * (GICv3 Architecture specification 5.4.23). - * GICR_WAKER is NOT banked per CPU, compute the correct base address - * per CPU. - */ - assert(g_gicr_base); - base = gicv3_get_rdist(g_gicr_base, read_mpidr()); - if (base == (uintptr_t)NULL) { - /* No re-distributor base address. This interface cannot be - * configured. - */ - panic(); - } - - val = gicr_read_waker(base); - val |= WAKER_PS; - gicr_write_waker(base, val); - dsb(); - - /* We need to wait for ChildrenAsleep to set. */ - val = gicr_read_waker(base); - while ((val & WAKER_CA) == 0) - val = gicr_read_waker(base); -} - - -/******************************************************************************* - * Enable secure interrupts and use FIQs to route them. Disable legacy bypass - * and set the priority mask register to allow all interrupts to trickle in. - ******************************************************************************/ -void arm_gic_cpuif_setup(void) -{ - unsigned int val; - - assert(g_gicc_base); - val = gicc_read_iidr(g_gicc_base); - - /* - * If GICv3 we need to do a bit of additional setup. We want to - * allow default GICv2 behaviour but allow the next stage to - * enable full gicv3 features. - */ - if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) - gicv3_cpuif_setup(); - - val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0; - val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; - - gicc_write_pmr(g_gicc_base, GIC_PRI_MASK); - gicc_write_ctlr(g_gicc_base, val); -} - -/******************************************************************************* - * Place the cpu interface in a state where it can never make a cpu exit wfi as - * as result of an asserted interrupt. This is critical for powering down a cpu - ******************************************************************************/ -void arm_gic_cpuif_deactivate(void) -{ - unsigned int val; - - /* Disable secure, non-secure interrupts and disable their bypass */ - assert(g_gicc_base); - val = gicc_read_ctlr(g_gicc_base); - val &= ~(ENABLE_GRP0 | ENABLE_GRP1); - val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; - val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; - gicc_write_ctlr(g_gicc_base, val); - - val = gicc_read_iidr(g_gicc_base); - - /* - * If GICv3 we need to do a bit of additional setup. Make sure the - * RDIST is put to sleep. - */ - if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) - gicv3_cpuif_deactivate(); -} - -/******************************************************************************* - * Per cpu gic distributor setup which will be done by all cpus after a cold - * boot/hotplug. This marks out the secure interrupts & enables them. - ******************************************************************************/ -void arm_gic_pcpu_distif_setup(void) -{ - unsigned int index, irq_num, sec_ppi_sgi_mask; - - assert(g_gicd_base); - - /* Setup PPI priorities doing four at a time */ - for (index = 0; index < 32; index += 4) { - gicd_write_ipriorityr(g_gicd_base, index, - GICD_IPRIORITYR_DEF_VAL); - } - - assert(g_irq_sec_ptr); - sec_ppi_sgi_mask = 0; - - /* Ensure all SGIs and PPIs are Group0 to begin with */ - gicd_write_igroupr(g_gicd_base, 0, 0); - - for (index = 0; index < g_num_irqs; index++) { - irq_num = g_irq_sec_ptr[index]; - if (irq_num < MIN_SPI_ID) { - /* We have an SGI or a PPI */ - sec_ppi_sgi_mask |= 1U << irq_num; - gicd_set_ipriorityr(g_gicd_base, irq_num, - GIC_HIGHEST_SEC_PRIORITY); - gicd_set_isenabler(g_gicd_base, irq_num); - } - } - - /* - * Invert the bitmask to create a mask for non-secure PPIs and - * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will - * update the GICR_IGROUPR0 as well in case we are running on a GICv3 - * system. This is critical if GICD_CTLR.ARE_NS=1. - */ - gicd_write_igroupr(g_gicd_base, 0, ~sec_ppi_sgi_mask); -} - -/******************************************************************************* - * Get the current CPU bit mask from GICD_ITARGETSR0 - ******************************************************************************/ -static unsigned int arm_gic_get_cpuif_id(void) -{ - unsigned int val; - - val = gicd_read_itargetsr(g_gicd_base, 0); - return val & GIC_TARGET_CPU_MASK; -} - -/******************************************************************************* - * Global gic distributor setup which will be done by the primary cpu after a - * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It - * then enables the secure GIC distributor interface. - ******************************************************************************/ -static void arm_gic_distif_setup(void) -{ - unsigned int num_ints, ctlr, index, irq_num; - uint8_t target_cpu; - - /* Disable the distributor before going further */ - assert(g_gicd_base); - ctlr = gicd_read_ctlr(g_gicd_base); - ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1); - gicd_write_ctlr(g_gicd_base, ctlr); - - /* - * Mark out non-secure SPI interrupts. The number of interrupts is - * calculated as 32 * (IT_LINES + 1). We do 32 at a time. - */ - num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK; - num_ints = (num_ints + 1) << 5; - for (index = MIN_SPI_ID; index < num_ints; index += 32) - gicd_write_igroupr(g_gicd_base, index, ~0); - - /* Setup SPI priorities doing four at a time */ - for (index = MIN_SPI_ID; index < num_ints; index += 4) { - gicd_write_ipriorityr(g_gicd_base, index, - GICD_IPRIORITYR_DEF_VAL); - } - - /* Read the target CPU mask */ - target_cpu = arm_gic_get_cpuif_id(); - - /* Configure SPI secure interrupts now */ - assert(g_irq_sec_ptr); - for (index = 0; index < g_num_irqs; index++) { - irq_num = g_irq_sec_ptr[index]; - if (irq_num >= MIN_SPI_ID) { - /* We have an SPI */ - gicd_clr_igroupr(g_gicd_base, irq_num); - gicd_set_ipriorityr(g_gicd_base, irq_num, - GIC_HIGHEST_SEC_PRIORITY); - gicd_set_itargetsr(g_gicd_base, irq_num, target_cpu); - gicd_set_isenabler(g_gicd_base, irq_num); - } - } - - /* - * Configure the SGI and PPI. This is done in a separated function - * because each CPU is responsible for initializing its own private - * interrupts. - */ - arm_gic_pcpu_distif_setup(); - - gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0); -} - -/******************************************************************************* - * Initialize the ARM GIC driver with the provided platform inputs -******************************************************************************/ -void arm_gic_init(uintptr_t gicc_base, - uintptr_t gicd_base, - uintptr_t gicr_base, - const unsigned int *irq_sec_ptr, - unsigned int num_irqs) -{ - unsigned int val; - - assert(gicc_base); - assert(gicd_base); - assert(irq_sec_ptr); - - g_gicc_base = gicc_base; - g_gicd_base = gicd_base; - - val = gicc_read_iidr(g_gicc_base); - - if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) { - assert(gicr_base); - g_gicr_base = gicr_base; - } - - g_irq_sec_ptr = irq_sec_ptr; - g_num_irqs = num_irqs; -} - -/******************************************************************************* - * Setup the ARM GIC CPU and distributor interfaces. -******************************************************************************/ -void arm_gic_setup(void) -{ - arm_gic_cpuif_setup(); - arm_gic_distif_setup(); -} - -/******************************************************************************* - * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. - * The interrupt controller knows which pin/line it uses to signal a type of - * interrupt. This function provides a common implementation of - * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use - * across platforms. It lets the interrupt management framework determine - * for a type of interrupt and security state, which line should be used in the - * SCR_EL3 to control its routing to EL3. The interrupt line is represented as - * the bit position of the IRQ or FIQ bit in the SCR_EL3. - ******************************************************************************/ -uint32_t arm_gic_interrupt_type_to_line(uint32_t type, - uint32_t security_state) -{ - assert(type == INTR_TYPE_S_EL1 || - type == INTR_TYPE_EL3 || - type == INTR_TYPE_NS); - - assert(sec_state_is_valid(security_state)); - - /* - * We ignore the security state parameter under the assumption that - * both normal and secure worlds are using ARM GICv2. This parameter - * will be used when the secure world starts using GICv3. - */ -#if ARM_GIC_ARCH == 2 - return gicv2_interrupt_type_to_line(g_gicc_base, type); -#else -#error "Invalid ARM GIC architecture version specified for platform port" -#endif /* ARM_GIC_ARCH */ -} - -#if ARM_GIC_ARCH == 2 -/******************************************************************************* - * This function returns the type of the highest priority pending interrupt at - * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no - * interrupt pending. - ******************************************************************************/ -uint32_t arm_gic_get_pending_interrupt_type(void) -{ - uint32_t id; - - assert(g_gicc_base); - id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK; - - /* Assume that all secure interrupts are S-EL1 interrupts */ - if (id < 1022) - return INTR_TYPE_S_EL1; - - if (id == GIC_SPURIOUS_INTERRUPT) - return INTR_TYPE_INVAL; - - return INTR_TYPE_NS; -} - -/******************************************************************************* - * This function returns the id of the highest priority pending interrupt at - * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no - * interrupt pending. - ******************************************************************************/ -uint32_t arm_gic_get_pending_interrupt_id(void) -{ - uint32_t id; - - assert(g_gicc_base); - id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK; - - if (id < 1022) - return id; - - if (id == 1023) - return INTR_ID_UNAVAILABLE; - - /* - * Find out which non-secure interrupt it is under the assumption that - * the GICC_CTLR.AckCtl bit is 0. - */ - return gicc_read_ahppir(g_gicc_base) & INT_ID_MASK; -} - -/******************************************************************************* - * This functions reads the GIC cpu interface Interrupt Acknowledge register - * to start handling the pending interrupt. It returns the contents of the IAR. - ******************************************************************************/ -uint32_t arm_gic_acknowledge_interrupt(void) -{ - assert(g_gicc_base); - return gicc_read_IAR(g_gicc_base); -} - -/******************************************************************************* - * This functions writes the GIC cpu interface End Of Interrupt register with - * the passed value to finish handling the active interrupt - ******************************************************************************/ -void arm_gic_end_of_interrupt(uint32_t id) -{ - assert(g_gicc_base); - gicc_write_EOIR(g_gicc_base, id); -} - -/******************************************************************************* - * This function returns the type of the interrupt id depending upon the group - * this interrupt has been configured under by the interrupt controller i.e. - * group0 or group1. - ******************************************************************************/ -uint32_t arm_gic_get_interrupt_type(uint32_t id) -{ - uint32_t group; - - assert(g_gicd_base); - group = gicd_get_igroupr(g_gicd_base, id); - - /* Assume that all secure interrupts are S-EL1 interrupts */ - if (group == GRP0) - return INTR_TYPE_S_EL1; - else - return INTR_TYPE_NS; -} - -#else -#error "Invalid ARM GIC architecture version specified for platform port" -#endif /* ARM_GIC_ARCH */ diff --git a/drivers/arm/gic/gic_v2.c b/drivers/arm/gic/gic_v2.c deleted file mode 100644 index 29c79e07b..000000000 --- a/drivers/arm/gic/gic_v2.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <assert.h> -#include <gic_v2.h> -#include <interrupt_mgmt.h> -#include <mmio.h> - -/******************************************************************************* - * GIC Distributor interface accessors for reading entire registers - ******************************************************************************/ - -unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id) -{ - unsigned n = id >> IGROUPR_SHIFT; - return mmio_read_32(base + GICD_IGROUPR + (n << 2)); -} - -unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) -{ - unsigned n = id >> ISENABLER_SHIFT; - return mmio_read_32(base + GICD_ISENABLER + (n << 2)); -} - -unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id) -{ - unsigned n = id >> ICENABLER_SHIFT; - return mmio_read_32(base + GICD_ICENABLER + (n << 2)); -} - -unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id) -{ - unsigned n = id >> ISPENDR_SHIFT; - return mmio_read_32(base + GICD_ISPENDR + (n << 2)); -} - -unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id) -{ - unsigned n = id >> ICPENDR_SHIFT; - return mmio_read_32(base + GICD_ICPENDR + (n << 2)); -} - -unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id) -{ - unsigned n = id >> ISACTIVER_SHIFT; - return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); -} - -unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id) -{ - unsigned n = id >> ICACTIVER_SHIFT; - return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); -} - -unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id) -{ - unsigned n = id >> IPRIORITYR_SHIFT; - return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); -} - -unsigned int gicd_read_itargetsr(uintptr_t base, unsigned int id) -{ - unsigned n = id >> ITARGETSR_SHIFT; - return mmio_read_32(base + GICD_ITARGETSR + (n << 2)); -} - -unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id) -{ - unsigned n = id >> ICFGR_SHIFT; - return mmio_read_32(base + GICD_ICFGR + (n << 2)); -} - -unsigned int gicd_read_cpendsgir(uintptr_t base, unsigned int id) -{ - unsigned n = id >> CPENDSGIR_SHIFT; - return mmio_read_32(base + GICD_CPENDSGIR + (n << 2)); -} - -unsigned int gicd_read_spendsgir(uintptr_t base, unsigned int id) -{ - unsigned n = id >> SPENDSGIR_SHIFT; - return mmio_read_32(base + GICD_SPENDSGIR + (n << 2)); -} - -/******************************************************************************* - * GIC Distributor interface accessors for writing entire registers - ******************************************************************************/ - -void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> IGROUPR_SHIFT; - mmio_write_32(base + GICD_IGROUPR + (n << 2), val); -} - -void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ISENABLER_SHIFT; - mmio_write_32(base + GICD_ISENABLER + (n << 2), val); -} - -void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ICENABLER_SHIFT; - mmio_write_32(base + GICD_ICENABLER + (n << 2), val); -} - -void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ISPENDR_SHIFT; - mmio_write_32(base + GICD_ISPENDR + (n << 2), val); -} - -void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ICPENDR_SHIFT; - mmio_write_32(base + GICD_ICPENDR + (n << 2), val); -} - -void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ISACTIVER_SHIFT; - mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); -} - -void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ICACTIVER_SHIFT; - mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); -} - -void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> IPRIORITYR_SHIFT; - mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); -} - -void gicd_write_itargetsr(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ITARGETSR_SHIFT; - mmio_write_32(base + GICD_ITARGETSR + (n << 2), val); -} - -void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ICFGR_SHIFT; - mmio_write_32(base + GICD_ICFGR + (n << 2), val); -} - -void gicd_write_cpendsgir(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> CPENDSGIR_SHIFT; - mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val); -} - -void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val) -{ - unsigned n = id >> SPENDSGIR_SHIFT; - mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val); -} - -/******************************************************************************* - * GIC Distributor interface accessors for individual interrupt manipulation - ******************************************************************************/ -unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id) -{ - unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); - unsigned int reg_val = gicd_read_igroupr(base, id); - - return (reg_val >> bit_num) & 0x1; -} - -void gicd_set_igroupr(uintptr_t base, unsigned int id) -{ - unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); - unsigned int reg_val = gicd_read_igroupr(base, id); - - gicd_write_igroupr(base, id, reg_val | (1 << bit_num)); -} - -void gicd_clr_igroupr(uintptr_t base, unsigned int id) -{ - unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); - unsigned int reg_val = gicd_read_igroupr(base, id); - - gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num)); -} - -void gicd_set_isenabler(uintptr_t base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); - - gicd_write_isenabler(base, id, (1 << bit_num)); -} - -void gicd_set_icenabler(uintptr_t base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); - - gicd_write_icenabler(base, id, (1 << bit_num)); -} - -void gicd_set_ispendr(uintptr_t base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); - - gicd_write_ispendr(base, id, (1 << bit_num)); -} - -void gicd_set_icpendr(uintptr_t base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); - - gicd_write_icpendr(base, id, (1 << bit_num)); -} - -void gicd_set_isactiver(uintptr_t base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); - - gicd_write_isactiver(base, id, (1 << bit_num)); -} - -void gicd_set_icactiver(uintptr_t base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1); - - gicd_write_icactiver(base, id, (1 << bit_num)); -} - -/* - * Make sure that the interrupt's group is set before expecting - * this function to do its job correctly. - */ -void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) -{ - /* - * Enforce ARM recommendation to manage priority values such - * that group1 interrupts always have a lower priority than - * group0 interrupts. - * Note, lower numerical values are higher priorities so the comparison - * checks below are reversed from what might be expected. - */ - assert(gicd_get_igroupr(base, id) == GRP1 ? - pri >= GIC_HIGHEST_NS_PRIORITY && - pri <= GIC_LOWEST_NS_PRIORITY : - pri >= GIC_HIGHEST_SEC_PRIORITY && - pri <= GIC_LOWEST_SEC_PRIORITY); - - mmio_write_8(base + GICD_IPRIORITYR + id, pri & GIC_PRI_MASK); -} - -void gicd_set_itargetsr(uintptr_t base, unsigned int id, unsigned int target) -{ - mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK); -} - -/******************************************************************************* - * This function allows the interrupt management framework to determine (through - * the platform) which interrupt line (IRQ/FIQ) to use for an interrupt type to - * route it to EL3. The interrupt line is represented as the bit position of the - * IRQ or FIQ bit in the SCR_EL3. - ******************************************************************************/ -uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type) -{ - uint32_t gicc_ctlr; - - /* Non-secure interrupts are signalled on the IRQ line always */ - if (type == INTR_TYPE_NS) - return __builtin_ctz(SCR_IRQ_BIT); - - /* - * Secure interrupts are signalled using the IRQ line if the FIQ_EN - * bit is not set else they are signalled using the FIQ line. - */ - gicc_ctlr = gicc_read_ctlr(cpuif_base); - if (gicc_ctlr & FIQ_EN) - return __builtin_ctz(SCR_FIQ_BIT); - else - return __builtin_ctz(SCR_IRQ_BIT); -} diff --git a/drivers/arm/gic/gic_v3.c b/drivers/arm/gic/gic_v3.c deleted file mode 100644 index 548681791..000000000 --- a/drivers/arm/gic/gic_v3.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <debug.h> -#include <gic_v3.h> - -uintptr_t gicv3_get_rdist(uintptr_t gicr_base, u_register_t mpidr) -{ - uint32_t cpu_aff, gicr_aff; - uint64_t gicr_typer; - uintptr_t addr; - - /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level - * mask is the same. - */ - cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) << - GICV3_AFF0_SHIFT; - cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) << - GICV3_AFF1_SHIFT; - cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) << - GICV3_AFF2_SHIFT; - cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) << - GICV3_AFF3_SHIFT; - - addr = gicr_base; - do { - gicr_typer = gicr_read_typer(addr); - - gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) & - GICR_TYPER_AFF_MASK; - if (cpu_aff == gicr_aff) { - /* Disable this print for now as it appears every time - * when using PSCI CPU_SUSPEND. - * TODO: Print this only the first time for each CPU. - * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at %p\n", - * mpidr, (void *) addr); - */ - return addr; - } - - /* TODO: - * For GICv4 we need to adjust the Base address based on - * GICR_TYPER.VLPIS - */ - addr += (1 << GICR_PCPUBASE_SHIFT); - - } while (!(gicr_typer & GICR_TYPER_LAST)); - - /* If we get here we did not find a match. */ - ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr); - return (uintptr_t)NULL; -} diff --git a/drivers/arm/gic/v2/gicv2_helpers.c b/drivers/arm/gic/v2/gicv2_helpers.c index 221f1b539..bc4c1d165 100644 --- a/drivers/arm/gic/v2/gicv2_helpers.c +++ b/drivers/arm/gic/v2/gicv2_helpers.c @@ -114,43 +114,6 @@ void gicv2_spis_configure_defaults(uintptr_t gicd_base) gicd_write_icfgr(gicd_base, index, 0U); } -#if !ERROR_DEPRECATED -/******************************************************************************* - * Helper function to configure secure G0 SPIs. - ******************************************************************************/ -void gicv2_secure_spis_configure(uintptr_t gicd_base, - unsigned int num_ints, - const unsigned int *sec_intr_list) -{ - unsigned int index, irq_num; - - /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ - if (num_ints != 0U) - assert(sec_intr_list != NULL); - - for (index = 0; index < num_ints; index++) { - irq_num = sec_intr_list[index]; - if (irq_num >= MIN_SPI_ID) { - /* Configure this interrupt as a secure interrupt */ - gicd_clr_igroupr(gicd_base, irq_num); - - /* Set the priority of this interrupt */ - gicd_set_ipriorityr(gicd_base, - irq_num, - GIC_HIGHEST_SEC_PRIORITY); - - /* Target the secure interrupts to primary CPU */ - gicd_set_itargetsr(gicd_base, irq_num, - gicv2_get_cpuif_id(gicd_base)); - - /* Enable this interrupt */ - gicd_set_isenabler(gicd_base, irq_num); - } - } - -} -#endif - /******************************************************************************* * Helper function to configure properties of secure G0 SPIs. ******************************************************************************/ @@ -192,56 +155,6 @@ void gicv2_secure_spis_configure_props(uintptr_t gicd_base, } } -#if !ERROR_DEPRECATED -/******************************************************************************* - * Helper function to configure secure G0 SGIs and PPIs. - ******************************************************************************/ -void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base, - unsigned int num_ints, - const unsigned int *sec_intr_list) -{ - unsigned int index, irq_num, sec_ppi_sgi_mask = 0; - - /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ - assert(num_ints ? (uintptr_t)sec_intr_list : 1); - - /* - * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a - * more scalable approach as it avoids clearing the enable bits in the - * GICD_CTLR. - */ - gicd_write_icenabler(gicd_base, 0, ~0); - - /* Setup the default PPI/SGI priorities doing four at a time */ - for (index = 0; index < MIN_SPI_ID; index += 4) - gicd_write_ipriorityr(gicd_base, - index, - GICD_IPRIORITYR_DEF_VAL); - - for (index = 0; index < num_ints; index++) { - irq_num = sec_intr_list[index]; - if (irq_num < MIN_SPI_ID) { - /* We have an SGI or a PPI. They are Group0 at reset */ - sec_ppi_sgi_mask |= 1U << irq_num; - - /* Set the priority of this interrupt */ - gicd_set_ipriorityr(gicd_base, - irq_num, - GIC_HIGHEST_SEC_PRIORITY); - } - } - - /* - * Invert the bitmask to create a mask for non-secure PPIs and - * SGIs. Program the GICD_IGROUPR0 with this bit mask. - */ - gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask); - - /* Enable the Group 0 SGIs and PPIs */ - gicd_write_isenabler(gicd_base, 0, sec_ppi_sgi_mask); -} -#endif - /******************************************************************************* * Helper function to configure properties of secure G0 SGIs and PPIs. ******************************************************************************/ diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index 55897bf96..b8729056d 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -79,27 +79,9 @@ void gicv2_pcpu_distif_init(void) assert(driver_data != NULL); assert(driver_data->gicd_base != 0U); -#if !ERROR_DEPRECATED - if (driver_data->interrupt_props != NULL) { -#endif - gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, - driver_data->interrupt_props, - driver_data->interrupt_props_num); -#if !ERROR_DEPRECATED - } else { - /* - * Suppress deprecated declaration warnings in compatibility - * function - */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - assert(driver_data->g0_interrupt_array); - gicv2_secure_ppi_sgi_setup(driver_data->gicd_base, - driver_data->g0_interrupt_num, - driver_data->g0_interrupt_array); -#pragma GCC diagnostic pop - } -#endif + gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, + driver_data->interrupt_props, + driver_data->interrupt_props_num); /* Enable G0 interrupts if not already */ ctlr = gicd_read_ctlr(driver_data->gicd_base); @@ -129,30 +111,10 @@ void gicv2_distif_init(void) /* Set the default attribute of all SPIs */ gicv2_spis_configure_defaults(driver_data->gicd_base); -#if !ERROR_DEPRECATED - if (driver_data->interrupt_props != NULL) { -#endif - gicv2_secure_spis_configure_props(driver_data->gicd_base, - driver_data->interrupt_props, - driver_data->interrupt_props_num); -#if !ERROR_DEPRECATED - } else { - /* - * Suppress deprecated declaration warnings in compatibility - * function - */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" + gicv2_secure_spis_configure_props(driver_data->gicd_base, + driver_data->interrupt_props, + driver_data->interrupt_props_num); - assert(driver_data->g0_interrupt_array); - - /* Configure the G0 SPIs */ - gicv2_secure_spis_configure(driver_data->gicd_base, - driver_data->g0_interrupt_num, - driver_data->g0_interrupt_array); -#pragma GCC diagnostic pop - } -#endif /* Re-enable the secure SPIs now that they have been configured */ gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); @@ -169,35 +131,8 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) assert(plat_driver_data->gicd_base != 0U); assert(plat_driver_data->gicc_base != 0U); -#if !ERROR_DEPRECATED - if (plat_driver_data->interrupt_props == NULL) { - /* Interrupt properties array size must be 0 */ - assert(plat_driver_data->interrupt_props_num == 0); - - /* - * Suppress deprecated declaration warnings in compatibility - * function - */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - - /* - * If there are no interrupts of a particular type, then the - * number of interrupts of that type should be 0 and vice-versa. - */ - assert(plat_driver_data->g0_interrupt_array ? - plat_driver_data->g0_interrupt_num : - plat_driver_data->g0_interrupt_num == 0); -#pragma GCC diagnostic pop - - WARN("Using deprecated integer interrupt array in " - "gicv2_driver_data_t\n"); - WARN("Please migrate to using an interrupt_prop_t array\n"); - } -#else assert(plat_driver_data->interrupt_props_num > 0 ? plat_driver_data->interrupt_props != NULL : 1); -#endif /* Ensure that this is a GICv2 system */ gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); diff --git a/drivers/arm/gic/v2/gicv2_private.h b/drivers/arm/gic/v2/gicv2_private.h index fadc96006..1eb6d9d51 100644 --- a/drivers/arm/gic/v2/gicv2_private.h +++ b/drivers/arm/gic/v2/gicv2_private.h @@ -15,14 +15,6 @@ * Private function prototypes ******************************************************************************/ void gicv2_spis_configure_defaults(uintptr_t gicd_base); -#if !ERROR_DEPRECATED -void gicv2_secure_spis_configure(uintptr_t gicd_base, - unsigned int num_ints, - const unsigned int *sec_intr_list); -void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base, - unsigned int num_ints, - const unsigned int *sec_intr_list); -#endif void gicv2_secure_spis_configure_props(uintptr_t gicd_base, const interrupt_prop_t *interrupt_props, unsigned int interrupt_props_num); diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c index 1953a37b1..c12a4b651 100644 --- a/drivers/arm/gic/v3/gicv3_helpers.c +++ b/drivers/arm/gic/v3/gicv3_helpers.c @@ -377,56 +377,6 @@ void gicv3_spis_config_defaults(uintptr_t gicd_base) gicd_write_icfgr(gicd_base, index, 0U); } -#if !ERROR_DEPRECATED -/******************************************************************************* - * Helper function to configure secure G0 and G1S SPIs. - ******************************************************************************/ -void gicv3_secure_spis_config(uintptr_t gicd_base, - unsigned int num_ints, - const unsigned int *sec_intr_list, - unsigned int int_grp) -{ - unsigned int index, irq_num; - unsigned long long gic_affinity_val; - - assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); - /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ - if (num_ints != 0U) - assert(sec_intr_list != NULL); - - for (index = 0U; index < num_ints; index++) { - irq_num = sec_intr_list[index]; - if (irq_num >= MIN_SPI_ID) { - - /* Configure this interrupt as a secure interrupt */ - gicd_clr_igroupr(gicd_base, irq_num); - - /* Configure this interrupt as G0 or a G1S interrupt */ - if (int_grp == INTR_GROUP1S) - gicd_set_igrpmodr(gicd_base, irq_num); - else - gicd_clr_igrpmodr(gicd_base, irq_num); - - /* Set the priority of this interrupt */ - gicd_set_ipriorityr(gicd_base, - irq_num, - GIC_HIGHEST_SEC_PRIORITY); - - /* Target SPIs to the primary CPU */ - gic_affinity_val = - gicd_irouter_val_from_mpidr(read_mpidr(), 0U); - gicd_write_irouter(gicd_base, - irq_num, - gic_affinity_val); - - /* Enable this interrupt */ - gicd_set_isenabler(gicd_base, irq_num); - } - } - -} -#endif - /******************************************************************************* * Helper function to configure properties of secure SPIs ******************************************************************************/ @@ -512,47 +462,6 @@ void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) gicr_write_icfgr1(gicr_base, 0U); } -#if !ERROR_DEPRECATED -/******************************************************************************* - * Helper function to configure secure G0 and G1S SPIs. - ******************************************************************************/ -void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base, - unsigned int num_ints, - const unsigned int *sec_intr_list, - unsigned int int_grp) -{ - unsigned int index, irq_num; - - assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); - /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ - if (num_ints != 0U) - assert(sec_intr_list != NULL); - - for (index = 0; index < num_ints; index++) { - irq_num = sec_intr_list[index]; - if (irq_num < MIN_SPI_ID) { - - /* Configure this interrupt as a secure interrupt */ - gicr_clr_igroupr0(gicr_base, irq_num); - - /* Configure this interrupt as G0 or a G1S interrupt */ - if (int_grp == INTR_GROUP1S) - gicr_set_igrpmodr0(gicr_base, irq_num); - else - gicr_clr_igrpmodr0(gicr_base, irq_num); - - /* Set the priority of this interrupt */ - gicr_set_ipriorityr(gicr_base, - irq_num, - GIC_HIGHEST_SEC_PRIORITY); - - /* Enable this interrupt */ - gicr_set_isenabler0(gicr_base, irq_num); - } - } -} -#endif - /******************************************************************************* * Helper function to configure properties of secure G0 and G1S PPIs and SGIs. ******************************************************************************/ diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 8da4512e5..60f2e108a 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -55,7 +55,7 @@ static spinlock_t gic_lock; * This function initialises the ARM GICv3 driver in EL3 with provided platform * inputs. ******************************************************************************/ -void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) +void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) { unsigned int gic_version; @@ -67,45 +67,8 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) assert(IS_IN_EL3()); -#if !ERROR_DEPRECATED - if (plat_driver_data->interrupt_props == NULL) { - /* Interrupt properties array size must be 0 */ - assert(plat_driver_data->interrupt_props_num == 0); - - /* - * Suppress deprecated declaration warnings in compatibility - * function - */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - - /* - * The platform should provide a list of at least one type of - * interrupt. - */ - assert(plat_driver_data->g0_interrupt_array || - plat_driver_data->g1s_interrupt_array); - - /* - * If there are no interrupts of a particular type, then the - * number of interrupts of that type should be 0 and vice-versa. - */ - assert(plat_driver_data->g0_interrupt_array ? - plat_driver_data->g0_interrupt_num : - plat_driver_data->g0_interrupt_num == 0); - assert(plat_driver_data->g1s_interrupt_array ? - plat_driver_data->g1s_interrupt_num : - plat_driver_data->g1s_interrupt_num == 0); -#pragma GCC diagnostic pop - - WARN("Using deprecated integer interrupt arrays in " - "gicv3_driver_data_t\n"); - WARN("Please migrate to using interrupt_prop_t arrays\n"); - } -#else assert(plat_driver_data->interrupt_props_num > 0 ? plat_driver_data->interrupt_props != NULL : 1); -#endif /* Check for system register support */ #ifdef AARCH32 @@ -166,7 +129,7 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) * This function initialises the GIC distributor interface based upon the data * provided by the platform while initialising the driver. ******************************************************************************/ -void gicv3_distif_init(void) +void __init gicv3_distif_init(void) { unsigned int bitmap = 0; @@ -193,45 +156,10 @@ void gicv3_distif_init(void) /* Set the default attribute of all SPIs */ gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); -#if !ERROR_DEPRECATED - if (gicv3_driver_data->interrupt_props != NULL) { -#endif - bitmap = gicv3_secure_spis_config_props( - gicv3_driver_data->gicd_base, - gicv3_driver_data->interrupt_props, - gicv3_driver_data->interrupt_props_num); -#if !ERROR_DEPRECATED - } else { - /* - * Suppress deprecated declaration warnings in compatibility - * function - */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - - assert(gicv3_driver_data->g1s_interrupt_array || - gicv3_driver_data->g0_interrupt_array); - - /* Configure the G1S SPIs */ - if (gicv3_driver_data->g1s_interrupt_array) { - gicv3_secure_spis_config(gicv3_driver_data->gicd_base, - gicv3_driver_data->g1s_interrupt_num, - gicv3_driver_data->g1s_interrupt_array, - INTR_GROUP1S); - bitmap |= CTLR_ENABLE_G1S_BIT; - } - - /* Configure the G0 SPIs */ - if (gicv3_driver_data->g0_interrupt_array) { - gicv3_secure_spis_config(gicv3_driver_data->gicd_base, - gicv3_driver_data->g0_interrupt_num, - gicv3_driver_data->g0_interrupt_array, - INTR_GROUP0); - bitmap |= CTLR_ENABLE_G0_BIT; - } -#pragma GCC diagnostic pop - } -#endif + bitmap = gicv3_secure_spis_config_props( + gicv3_driver_data->gicd_base, + gicv3_driver_data->interrupt_props, + gicv3_driver_data->interrupt_props_num); /* Enable the secure SPIs now that they have been configured */ gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); @@ -266,44 +194,9 @@ void gicv3_rdistif_init(unsigned int proc_num) /* Set the default attribute of all SGIs and PPIs */ gicv3_ppi_sgi_config_defaults(gicr_base); -#if !ERROR_DEPRECATED - if (gicv3_driver_data->interrupt_props != NULL) { -#endif - bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, - gicv3_driver_data->interrupt_props, - gicv3_driver_data->interrupt_props_num); -#if !ERROR_DEPRECATED - } else { - /* - * Suppress deprecated declaration warnings in compatibility - * function - */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - - assert(gicv3_driver_data->g1s_interrupt_array || - gicv3_driver_data->g0_interrupt_array); - - /* Configure the G1S SGIs/PPIs */ - if (gicv3_driver_data->g1s_interrupt_array) { - gicv3_secure_ppi_sgi_config(gicr_base, - gicv3_driver_data->g1s_interrupt_num, - gicv3_driver_data->g1s_interrupt_array, - INTR_GROUP1S); - bitmap |= CTLR_ENABLE_G1S_BIT; - } - - /* Configure the G0 SGIs/PPIs */ - if (gicv3_driver_data->g0_interrupt_array) { - gicv3_secure_ppi_sgi_config(gicr_base, - gicv3_driver_data->g0_interrupt_num, - gicv3_driver_data->g0_interrupt_array, - INTR_GROUP0); - bitmap |= CTLR_ENABLE_G0_BIT; - } -#pragma GCC diagnostic pop - } -#endif + bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, + gicv3_driver_data->interrupt_props, + gicv3_driver_data->interrupt_props_num); /* Enable interrupt groups as required, if not already */ if ((ctlr & bitmap) != bitmap) diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h index 36d4b3ed5..85231ad9d 100644 --- a/drivers/arm/gic/v3/gicv3_private.h +++ b/drivers/arm/gic/v3/gicv3_private.h @@ -95,16 +95,6 @@ void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg); ******************************************************************************/ void gicv3_spis_config_defaults(uintptr_t gicd_base); void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base); -#if !ERROR_DEPRECATED -void gicv3_secure_spis_config(uintptr_t gicd_base, - unsigned int num_ints, - const unsigned int *sec_intr_list, - unsigned int int_grp); -void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base, - unsigned int num_ints, - const unsigned int *sec_intr_list, - unsigned int int_grp); -#endif unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, const interrupt_prop_t *interrupt_props, unsigned int interrupt_props_num); diff --git a/drivers/arm/pl011/pl011_console.S b/drivers/arm/pl011/pl011_console.S deleted file mode 100644 index 1789f153f..000000000 --- a/drivers/arm/pl011/pl011_console.S +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if !ERROR_DEPRECATED -#include "./aarch64/pl011_console.S" -#endif diff --git a/drivers/arm/smmu/smmu_v3.c b/drivers/arm/smmu/smmu_v3.c index ddb99634e..78a9ffa6d 100644 --- a/drivers/arm/smmu/smmu_v3.c +++ b/drivers/arm/smmu/smmu_v3.c @@ -4,21 +4,22 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <cdefs.h> #include <mmio.h> #include <smmu_v3.h> #include <stdbool.h> -static inline uint32_t smmuv3_read_s_idr1(uintptr_t base) +static inline uint32_t __init smmuv3_read_s_idr1(uintptr_t base) { return mmio_read_32(base + SMMU_S_IDR1); } -static inline uint32_t smmuv3_read_s_init(uintptr_t base) +static inline uint32_t __init smmuv3_read_s_init(uintptr_t base) { return mmio_read_32(base + SMMU_S_INIT); } -static inline void smmuv3_write_s_init(uintptr_t base, uint32_t value) +static inline void __init smmuv3_write_s_init(uintptr_t base, uint32_t value) { mmio_write_32(base + SMMU_S_INIT, value); } @@ -34,7 +35,7 @@ static inline bool smmuv3_inval_pending(uintptr_t base) * * Returns 0 on success, and -1 on failure. */ -int smmuv3_init(uintptr_t smmu_base) +int __init smmuv3_init(uintptr_t smmu_base) { uint32_t idr1_reg; diff --git a/drivers/arm/tzc400/tzc400.c b/drivers/arm/tzc400/tzc400.c deleted file mode 100644 index ff2ebc70e..000000000 --- a/drivers/arm/tzc400/tzc400.c +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if ERROR_DEPRECATED -#error "Using deprecated TZC-400 source file" -#else -#include "../tzc/tzc400.c" -#endif /* ERROR_DEPRECATED */ diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk index 71c496eda..cfbd86ab9 100644 --- a/drivers/auth/mbedtls/mbedtls_common.mk +++ b/drivers/auth/mbedtls/mbedtls_common.mk @@ -60,16 +60,6 @@ ifeq (${TF_MBEDTLS_KEY_ALG},) endif endif -# If MBEDTLS_KEY_ALG build flag is defined use it to set TF_MBEDTLS_KEY_ALG for -# backward compatibility -ifdef MBEDTLS_KEY_ALG - ifeq (${ERROR_DEPRECATED},1) - $(error "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG") - endif - $(warning "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG") - TF_MBEDTLS_KEY_ALG := ${MBEDTLS_KEY_ALG} -endif - ifeq (${HASH_ALG}, sha384) TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA384 else ifeq (${HASH_ALG}, sha512) diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S index fc357f8a4..673263197 100644 --- a/drivers/cadence/uart/aarch64/cdns_console.S +++ b/drivers/cadence/uart/aarch64/cdns_console.S @@ -15,9 +15,11 @@ .globl console_cdns_core_init .globl console_cdns_core_putc .globl console_cdns_core_getc + .globl console_cdns_core_flush .globl console_cdns_putc .globl console_cdns_getc + .globl console_cdns_flush /* ----------------------------------------------- * int console_cdns_core_init(uintptr_t base_addr) @@ -87,6 +89,7 @@ endfunc console_cdns_register .equ console_core_init,console_cdns_core_init .equ console_core_putc,console_cdns_core_putc .equ console_core_getc,console_cdns_core_getc + .equ console_core_flush,console_cdns_core_flush #endif /* -------------------------------------------------------- @@ -188,8 +191,7 @@ func console_cdns_getc endfunc console_cdns_getc /* --------------------------------------------- - * int console_core_flush(uintptr_t base_addr) - * DEPRECATED: Not used with MULTI_CONSOLE_API! + * int console_cdns_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address @@ -197,8 +199,30 @@ endfunc console_cdns_getc * Clobber list : x0, x1 * --------------------------------------------- */ -func console_core_flush +func console_cdns_core_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ /* Placeholder */ mov w0, #0 ret -endfunc console_core_flush +endfunc console_cdns_core_flush + + /* --------------------------------------------- + * int console_cdns_flush(console_pl011_t *console) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - pointer to console_t structure + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_cdns_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x0, [x0, #CONSOLE_T_CDNS_BASE] + b console_cdns_core_flush +endfunc console_cdns_flush diff --git a/drivers/cadence/uart/cdns_console.S b/drivers/cadence/uart/cdns_console.S deleted file mode 100644 index 6da8f91a2..000000000 --- a/drivers/cadence/uart/cdns_console.S +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if !ERROR_DEPRECATED -#include "./aarch64/cdns_console.S" -#endif diff --git a/drivers/console/console.S b/drivers/console/console.S deleted file mode 100644 index c48530c9e..000000000 --- a/drivers/console/console.S +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if !ERROR_DEPRECATED -#include "./aarch64/console.S" -#endif diff --git a/drivers/console/skeleton_console.S b/drivers/console/skeleton_console.S deleted file mode 100644 index 905370ddd..000000000 --- a/drivers/console/skeleton_console.S +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if !ERROR_DEPRECATED -#include "./aarch64/skeleton_console.S" -#endif diff --git a/drivers/delay_timer/delay_timer.c b/drivers/delay_timer/delay_timer.c index 587724eb1..feac3579f 100644 --- a/drivers/delay_timer/delay_timer.c +++ b/drivers/delay_timer/delay_timer.c @@ -20,20 +20,21 @@ static const timer_ops_t *timer_ops; ***********************************************************/ void udelay(uint32_t usec) { - assert(timer_ops != NULL && - (timer_ops->clk_mult != 0) && - (timer_ops->clk_div != 0) && + assert((timer_ops != NULL) && + (timer_ops->clk_mult != 0U) && + (timer_ops->clk_div != 0U) && (timer_ops->get_timer_value != NULL)); uint32_t start, delta, total_delta; - assert(usec < UINT32_MAX / timer_ops->clk_div); + assert(usec < (UINT32_MAX / timer_ops->clk_div)); start = timer_ops->get_timer_value(); /* Add an extra tick to avoid delaying less than requested. */ total_delta = - div_round_up(usec * timer_ops->clk_div, timer_ops->clk_mult) + 1; + div_round_up(usec * timer_ops->clk_div, + timer_ops->clk_mult) + 1U; do { /* @@ -51,7 +52,7 @@ void udelay(uint32_t usec) ***********************************************************/ void mdelay(uint32_t msec) { - udelay(msec*1000); + udelay(msec * 1000U); } /*********************************************************** @@ -60,9 +61,9 @@ void mdelay(uint32_t msec) ***********************************************************/ void timer_init(const timer_ops_t *ops_ptr) { - assert(ops_ptr != NULL && - (ops_ptr->clk_mult != 0) && - (ops_ptr->clk_div != 0) && + assert((ops_ptr != NULL) && + (ops_ptr->clk_mult != 0U) && + (ops_ptr->clk_div != 0U) && (ops_ptr->get_timer_value != NULL)); timer_ops = ops_ptr; diff --git a/drivers/delay_timer/generic_delay_timer.c b/drivers/delay_timer/generic_delay_timer.c index 8a36c8abd..03ca5321a 100644 --- a/drivers/delay_timer/generic_delay_timer.c +++ b/drivers/delay_timer/generic_delay_timer.c @@ -49,9 +49,9 @@ void generic_delay_timer_init(void) unsigned int div = plat_get_syscnt_freq2(); /* Reduce multiplier and divider by dividing them repeatedly by 10 */ - while ((mult % 10 == 0) && (div % 10 == 0)) { - mult /= 10; - div /= 10; + while (((mult % 10U) == 0U) && ((div % 10U) == 0U)) { + mult /= 10U; + div /= 10U; } generic_delay_timer_init_args(mult, div); diff --git a/drivers/marvell/i2c/a8k_i2c.c b/drivers/marvell/i2c/a8k_i2c.c deleted file mode 100644 index 1c0f922cd..000000000 --- a/drivers/marvell/i2c/a8k_i2c.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2018 Marvell International Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - * https://spdx.org/licenses - */ - -/* This driver provides I2C support for Marvell A8K and compatible SoCs */ - -#include <mmio.h> - -#define CONFIG_SYS_TCLK 250000000 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x0 - -#define I2C_CAN_UNSTUCK - -struct mentor_i2c_regs { - uint32_t slave_address; - uint32_t data; - uint32_t control; - union { - uint32_t status; /* when reading */ - uint32_t baudrate; /* when writing */ - }; - uint32_t xtnd_slave_addr; - uint32_t reserved[2]; - uint32_t soft_reset; - uint8_t reserved2[0xa0 - 0x20]; - uint32_t unstuck; -}; - -#include "../../mentor/i2c/mi2cv.c" diff --git a/drivers/mentor/i2c/mi2cv.c b/drivers/mentor/i2c/mi2cv.c index 1b73e6f16..8ebd9662b 100644 --- a/drivers/mentor/i2c/mi2cv.c +++ b/drivers/mentor/i2c/mi2cv.c @@ -15,6 +15,7 @@ #include <delay_timer.h> #include <errno.h> #include <mentor/mi2cv.h> +#include <mentor_i2c_plat.h> #include <mmio.h> #if LOG_LEVEL >= LOG_LEVEL_VERBOSE diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 73287aef8..418ab1127 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -87,7 +87,7 @@ static int mmc_device_state(void) } ret = mmc_send_cmd(MMC_CMD(13), rca << RCA_SHIFT_OFFSET, - MMC_RESPONSE_R(1), &resp_data[0]); + MMC_RESPONSE_R1, &resp_data[0]); if (ret != 0) { return ret; } @@ -138,14 +138,14 @@ static int mmc_sd_switch(unsigned int bus_width) /* CMD55: Application Specific Command */ ret = mmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET, - MMC_RESPONSE_R(1), NULL); + MMC_RESPONSE_R5, NULL); if (ret != 0) { return ret; } /* ACMD51: SEND_SCR */ do { - ret = mmc_send_cmd(MMC_ACMD(51), 0, MMC_RESPONSE_R(1), NULL); + ret = mmc_send_cmd(MMC_ACMD(51), 0, MMC_RESPONSE_R1, NULL); if ((ret != 0) && (retries == 0)) { ERROR("ACMD51 failed after %d retries (ret=%d)\n", MMC_DEFAULT_MAX_RETRIES, ret); @@ -167,13 +167,13 @@ static int mmc_sd_switch(unsigned int bus_width) /* CMD55: Application Specific Command */ ret = mmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET, - MMC_RESPONSE_R(1), NULL); + MMC_RESPONSE_R5, NULL); if (ret != 0) { return ret; } /* ACMD6: SET_BUS_WIDTH */ - ret = mmc_send_cmd(MMC_ACMD(6), bus_width_arg, MMC_RESPONSE_R(1), NULL); + ret = mmc_send_cmd(MMC_ACMD(6), bus_width_arg, MMC_RESPONSE_R1, NULL); if (ret != 0) { return ret; } @@ -235,7 +235,7 @@ static int mmc_fill_device_info(void) } /* MMC CMD8: SEND_EXT_CSD */ - ret = mmc_send_cmd(MMC_CMD(8), 0, MMC_RESPONSE_R(1), NULL); + ret = mmc_send_cmd(MMC_CMD(8), 0, MMC_RESPONSE_R1, NULL); if (ret != 0) { return ret; } @@ -327,7 +327,7 @@ static int sd_send_op_cond(void) int ret; /* CMD55: Application Specific Command */ - ret = mmc_send_cmd(MMC_CMD(55), 0, MMC_RESPONSE_R(1), NULL); + ret = mmc_send_cmd(MMC_CMD(55), 0, MMC_RESPONSE_R1, NULL); if (ret != 0) { return ret; } @@ -416,7 +416,7 @@ static int mmc_enumerate(unsigned int clk, unsigned int bus_width) } else { /* CMD8: Send Interface Condition Command */ ret = mmc_send_cmd(MMC_CMD(8), VHS_2_7_3_6_V | CMD8_CHECK_PATTERN, - MMC_RESPONSE_R(7), &resp_data[0]); + MMC_RESPONSE_R5, &resp_data[0]); if ((ret == 0) && ((resp_data[0] & 0xffU) == CMD8_CHECK_PATTERN)) { ret = sd_send_op_cond(); @@ -427,7 +427,7 @@ static int mmc_enumerate(unsigned int clk, unsigned int bus_width) } /* CMD2: Card Identification */ - ret = mmc_send_cmd(MMC_CMD(2), 0, MMC_RESPONSE_R(2), NULL); + ret = mmc_send_cmd(MMC_CMD(2), 0, MMC_RESPONSE_R2, NULL); if (ret != 0) { return ret; } @@ -436,13 +436,13 @@ static int mmc_enumerate(unsigned int clk, unsigned int bus_width) if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) { rca = MMC_FIX_RCA; ret = mmc_send_cmd(MMC_CMD(3), rca << RCA_SHIFT_OFFSET, - MMC_RESPONSE_R(1), NULL); + MMC_RESPONSE_R1, NULL); if (ret != 0) { return ret; } } else { ret = mmc_send_cmd(MMC_CMD(3), 0, - MMC_RESPONSE_R(6), &resp_data[0]); + MMC_RESPONSE_R6, &resp_data[0]); if (ret != 0) { return ret; } @@ -452,7 +452,7 @@ static int mmc_enumerate(unsigned int clk, unsigned int bus_width) /* CMD9: CSD Register */ ret = mmc_send_cmd(MMC_CMD(9), rca << RCA_SHIFT_OFFSET, - MMC_RESPONSE_R(2), &resp_data[0]); + MMC_RESPONSE_R2, &resp_data[0]); if (ret != 0) { return ret; } @@ -461,7 +461,7 @@ static int mmc_enumerate(unsigned int clk, unsigned int bus_width) /* CMD7: Select Card */ ret = mmc_send_cmd(MMC_CMD(7), rca << RCA_SHIFT_OFFSET, - MMC_RESPONSE_R(1), NULL); + MMC_RESPONSE_R1, NULL); if (ret != 0) { return ret; } @@ -499,7 +499,7 @@ size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size) if (is_cmd23_enabled()) { /* Set block count */ ret = mmc_send_cmd(MMC_CMD(23), size / MMC_BLOCK_SIZE, - MMC_RESPONSE_R(1), NULL); + MMC_RESPONSE_R1, NULL); if (ret != 0) { return 0; } @@ -520,7 +520,7 @@ size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size) cmd_arg = lba; } - ret = mmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R(1), NULL); + ret = mmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R1, NULL); if (ret != 0) { return 0; } @@ -567,7 +567,7 @@ size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size) if (is_cmd23_enabled()) { /* Set block count */ ret = mmc_send_cmd(MMC_CMD(23), size / MMC_BLOCK_SIZE, - MMC_RESPONSE_R(1), NULL); + MMC_RESPONSE_R1, NULL); if (ret != 0) { return 0; } @@ -587,7 +587,7 @@ size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size) cmd_arg = lba; } - ret = mmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R(1), NULL); + ret = mmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R1, NULL); if (ret != 0) { return 0; } @@ -622,18 +622,18 @@ size_t mmc_erase_blocks(int lba, size_t size) assert(ops != NULL); assert((size != 0U) && ((size & MMC_BLOCK_MASK) == 0U)); - ret = mmc_send_cmd(MMC_CMD(35), lba, MMC_RESPONSE_R(1), NULL); + ret = mmc_send_cmd(MMC_CMD(35), lba, MMC_RESPONSE_R1, NULL); if (ret != 0) { return 0; } ret = mmc_send_cmd(MMC_CMD(36), lba + (size / MMC_BLOCK_SIZE) - 1U, - MMC_RESPONSE_R(1), NULL); + MMC_RESPONSE_R1, NULL); if (ret != 0) { return 0; } - ret = mmc_send_cmd(MMC_CMD(38), lba, MMC_RESPONSE_R(0x1B), NULL); + ret = mmc_send_cmd(MMC_CMD(38), lba, MMC_RESPONSE_R1B, NULL); if (ret != 0) { return 0; } diff --git a/drivers/synopsys/emmc/dw_mmc.c b/drivers/synopsys/emmc/dw_mmc.c index c544233fc..eb428198f 100644 --- a/drivers/synopsys/emmc/dw_mmc.c +++ b/drivers/synopsys/emmc/dw_mmc.c @@ -263,10 +263,7 @@ static int dw_send_cmd(struct mmc_cmd *cmd) op |= CMD_RESP_EXPECT | CMD_CHECK_RESP_CRC | CMD_RESP_LEN; break; - case MMC_RESPONSE_R1: - case MMC_RESPONSE_R1B: case MMC_RESPONSE_R3: - case MMC_RESPONSE_R5: op |= CMD_RESP_EXPECT; break; default: diff --git a/drivers/ti/uart/16550_console.S b/drivers/ti/uart/16550_console.S deleted file mode 100644 index 03ca526f8..000000000 --- a/drivers/ti/uart/16550_console.S +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if !ERROR_DEPRECATED -#include "./aarch64/16550_console.S" -#endif |