diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/arm/cci/cci.c | 114 | ||||
| -rw-r--r-- | drivers/arm/smmu/smmu_v3.c | 55 |
2 files changed, 137 insertions, 32 deletions
diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c index 04530b01c..e15683840 100644 --- a/drivers/arm/cci/cci.c +++ b/drivers/arm/cci/cci.c @@ -11,11 +11,26 @@ #include <mmio.h> #include <stdint.h> -static uintptr_t g_cci_base; -static unsigned int g_max_master_id; -static const int *g_cci_slave_if_map; +#define MAKE_CCI_PART_NUMBER(hi, lo) ((hi << 8) | lo) +#define CCI_PART_LO_MASK 0xff +#define CCI_PART_HI_MASK 0xf + +/* CCI part number codes read from Peripheral ID registers 0 and 1 */ +#define CCI400_PART_NUM 0x420 +#define CCI500_PART_NUM 0x422 +#define CCI550_PART_NUM 0x423 + +#define CCI400_SLAVE_PORTS 5 +#define CCI500_SLAVE_PORTS 7 +#define CCI550_SLAVE_PORTS 7 + +static uintptr_t cci_base; +static const int *cci_slave_if_map; #if ENABLE_ASSERTIONS +static unsigned int max_master_id; +static int cci_num_slave_ports; + static int validate_cci_map(const int *map) { unsigned int valid_cci_map = 0; @@ -23,13 +38,13 @@ static int validate_cci_map(const int *map) int i; /* Validate the map */ - for (i = 0; i <= g_max_master_id; i++) { + for (i = 0; i <= max_master_id; i++) { slave_if_id = map[i]; if (slave_if_id < 0) continue; - if (slave_if_id >= CCI_SLAVE_INTERFACE_COUNT) { + if (slave_if_id >= cci_num_slave_ports) { ERROR("Slave interface ID is invalid\n"); return 0; } @@ -48,70 +63,105 @@ static int validate_cci_map(const int *map) return 1; } + +/* + * Read CCI part number from Peripheral ID registers + */ +static unsigned int read_cci_part_number(uintptr_t base) +{ + unsigned int part_lo, part_hi; + + part_lo = mmio_read_32(base + PERIPHERAL_ID0) & CCI_PART_LO_MASK; + part_hi = mmio_read_32(base + PERIPHERAL_ID1) & CCI_PART_HI_MASK; + + return MAKE_CCI_PART_NUMBER(part_hi, part_lo); +} + +/* + * Identify a CCI device, and return the number of slaves. Return -1 for an + * unidentified device. + */ +static int get_slave_ports(unsigned int part_num) +{ + /* Macro to match CCI products */ +#define RET_ON_MATCH(product) \ + case CCI ## product ## _PART_NUM: \ + return CCI ## product ## _SLAVE_PORTS + + switch (part_num) { + + RET_ON_MATCH(400); + RET_ON_MATCH(500); + RET_ON_MATCH(550); + + default: + return -1; + } + +#undef RET_ON_MATCH +} #endif /* ENABLE_ASSERTIONS */ -void cci_init(uintptr_t cci_base, - const int *map, - unsigned int num_cci_masters) +void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters) { assert(map); - assert(cci_base); + assert(base); - g_cci_base = cci_base; + cci_base = base; + cci_slave_if_map = map; +#if ENABLE_ASSERTIONS /* * Master Id's are assigned from zero, So in an array of size n * the max master id is (n - 1). */ - g_max_master_id = num_cci_masters - 1; + max_master_id = num_cci_masters - 1; + cci_num_slave_ports = get_slave_ports(read_cci_part_number(base)); +#endif + assert(cci_num_slave_ports >= 0); assert(validate_cci_map(map)); - g_cci_slave_if_map = map; } void cci_enable_snoop_dvm_reqs(unsigned int master_id) { - int slave_if_id; + int slave_if_id = cci_slave_if_map[master_id]; - assert(g_cci_base); - assert(master_id <= g_max_master_id); - - slave_if_id = g_cci_slave_if_map[master_id]; - assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0)); + assert(master_id <= max_master_id); + assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0)); + assert(cci_base); /* * Enable Snoops and DVM messages, no need for Read/Modify/Write as * rest of bits are write ignore */ - mmio_write_32(g_cci_base + - SLAVE_IFACE_OFFSET(slave_if_id) + - SNOOP_CTRL_REG, DVM_EN_BIT | SNOOP_EN_BIT); + mmio_write_32(cci_base + + SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG, + DVM_EN_BIT | SNOOP_EN_BIT); /* Wait for the dust to settle down */ - while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT) + while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) ; } void cci_disable_snoop_dvm_reqs(unsigned int master_id) { - int slave_if_id; - - assert(g_cci_base); - assert(master_id <= g_max_master_id); + int slave_if_id = cci_slave_if_map[master_id]; - slave_if_id = g_cci_slave_if_map[master_id]; - assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0)); + assert(master_id <= max_master_id); + assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0)); + assert(cci_base); /* * Disable Snoops and DVM messages, no need for Read/Modify/Write as * rest of bits are write ignore. */ - mmio_write_32(g_cci_base + - SLAVE_IFACE_OFFSET(slave_if_id) + - SNOOP_CTRL_REG, ~(DVM_EN_BIT | SNOOP_EN_BIT)); + mmio_write_32(cci_base + + SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG, + ~(DVM_EN_BIT | SNOOP_EN_BIT)); /* Wait for the dust to settle down */ - while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT) + while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) ; } diff --git a/drivers/arm/smmu/smmu_v3.c b/drivers/arm/smmu/smmu_v3.c new file mode 100644 index 000000000..cfe8c2a47 --- /dev/null +++ b/drivers/arm/smmu/smmu_v3.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <mmio.h> +#include <smmu_v3.h> + +/* Test for pending invalidate */ +#define INVAL_PENDING(base) \ + smmuv3_read_s_init(base) & SMMU_S_INIT_INV_ALL_MASK + +static inline uint32_t smmuv3_read_s_idr1(uintptr_t base) +{ + return mmio_read_32(base + SMMU_S_IDR1); +} + +static inline uint32_t smmuv3_read_s_init(uintptr_t base) +{ + return mmio_read_32(base + SMMU_S_INIT); +} + +static inline void smmuv3_write_s_init(uintptr_t base, uint32_t value) +{ + mmio_write_32(base + SMMU_S_INIT, value); +} + +/* + * Initialize the SMMU by invalidating all secure caches and TLBs. + * + * Returns 0 on success, and -1 on failure. + */ +int smmuv3_init(uintptr_t smmu_base) +{ + uint32_t idr1_reg; + + /* + * Invalidation of secure caches and TLBs is required only if the SMMU + * supports secure state. If not, it's implementation defined as to how + * SMMU_S_INIT register is accessed. + */ + idr1_reg = smmuv3_read_s_idr1(smmu_base); + if (!((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) & + SMMU_S_IDR1_SECURE_IMPL_MASK)) { + return -1; + } + + /* Initiate invalidation, and wait for it to finish */ + smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK); + while (INVAL_PENDING(smmu_base)) + ; + + return 0; +} |