diff options
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/cpu-specific-build-macros.rst | 6 | ||||
| -rw-r--r-- | docs/porting-guide.rst | 28 | ||||
| -rw-r--r-- | docs/user-guide.rst | 6 |
3 files changed, 38 insertions, 2 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index 9e11cdff6..65f6adb8d 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -18,7 +18,11 @@ TF-A exports a series of build flags which control which security vulnerability workarounds should be applied at runtime. - ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for - `CVE-2017-5715`_. Defaults to 1. + `CVE-2017-5715`_. This flag can be set to 0 by the platform if none + of the PEs in the system need the workaround. Setting this flag to 0 provides + no performance benefit for non-affected platforms, it just helps to comply + with the recommendation in the spec regarding workaround discovery. + Defaults to 1. CPU Errata Workarounds ---------------------- diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index ff5bb1225..12e135f71 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -217,11 +217,37 @@ platform port to define additional platform porting constants in - **#define : BL2\_BASE** Defines the base address in secure RAM where BL1 loads the BL2 binary image. - Must be aligned on a page-size boundary. + Must be aligned on a page-size boundary. This constant is not applicable + when BL2_IN_XIP_MEM is set to '1'. - **#define : BL2\_LIMIT** Defines the maximum address in secure RAM that the BL2 image can occupy. + This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. + +- **#define : BL2\_RO\_BASE** + + Defines the base address in secure XIP memory where BL2 RO section originally + lives. Must be aligned on a page-size boundary. This constant is only needed + when BL2_IN_XIP_MEM is set to '1'. + +- **#define : BL2\_RO\_LIMIT** + + Defines the maximum address in secure XIP memory that BL2's actual content + (i.e. excluding any data section allocated at runtime) can occupy. This + constant is only needed when BL2_IN_XIP_MEM is set to '1'. + +- **#define : BL2\_RW\_BASE** + + Defines the base address in secure RAM where BL2's read-write data will live + at runtime. Must be aligned on a page-size boundary. This constant is only + needed when BL2_IN_XIP_MEM is set to '1'. + +- **#define : BL2\_RW\_LIMIT** + + Defines the maximum address in secure RAM that BL2's read-write data can + occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set + to '1'. - **#define : BL31\_BASE** diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 579485546..fdf1568e1 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -246,6 +246,12 @@ Common build options - ``BL2_AT_EL3``: This is an optional build option that enables the use of BL2 at EL3 execution level. +- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place + (XIP) memory, like BL1. In these use-cases, it is necessary to initialize + the RW sections in RAM, while leaving the RO sections in place. This option + enable this use-case. For now, this option is only supported when BL2_AT_EL3 + is set to '1'. + - ``BL31``: This is an optional build option which specifies the path to BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not be built. |