diff options
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/cpu-specific-build-macros.rst | 6 | ||||
| -rw-r--r-- | docs/plat/ls1043a.rst | 91 | ||||
| -rw-r--r-- | docs/porting-guide.rst | 28 | ||||
| -rw-r--r-- | docs/user-guide.rst | 6 |
4 files changed, 129 insertions, 2 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index 9e11cdff6..65f6adb8d 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -18,7 +18,11 @@ TF-A exports a series of build flags which control which security vulnerability workarounds should be applied at runtime. - ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for - `CVE-2017-5715`_. Defaults to 1. + `CVE-2017-5715`_. This flag can be set to 0 by the platform if none + of the PEs in the system need the workaround. Setting this flag to 0 provides + no performance benefit for non-affected platforms, it just helps to comply + with the recommendation in the spec regarding workaround discovery. + Defaults to 1. CPU Errata Workarounds ---------------------- diff --git a/docs/plat/ls1043a.rst b/docs/plat/ls1043a.rst new file mode 100644 index 000000000..0d604aaeb --- /dev/null +++ b/docs/plat/ls1043a.rst @@ -0,0 +1,91 @@ +Description +=========== + +The QorIQ® LS1043A processor is NXP's first quad-core, 64-bit Arm®-based +processor for embedded networking. The LS1023A (two core version) and the +LS1043A (four core version) deliver greater than 10 Gbps of performance +in a flexible I/O package supporting fanless designs. This SoC is a +purpose-built solution for small-form-factor networking and industrial +applications with BOM optimizations for economic low layer PCB, lower cost +power supply and single clock design. The new 0.9V versions of the LS1043A +and LS1023A deliver addition power savings for applications such as Wireless +LAN and to Power over Ethernet systems. + +LS1043ARDB Specification: +------------------------- +Memory subsystem: + * 2GByte DDR4 SDRAM (32bit bus) + * 128 Mbyte NOR flash single-chip memory + * 512 Mbyte NAND flash + * 16 Mbyte high-speed SPI flash + * SD connector to interface with the SD memory card + +Ethernet: + * XFI 10G port + * QSGMII with 4x 1G ports + * Two RGMII ports + +PCIe: + * PCIe2 (Lanes C) to mini-PCIe slot + * PCIe3 (Lanes D) to PCIe slot + +USB 3.0: two super speed USB 3.0 type A ports + +UART: supports two UARTs up to 115200 bps for console + +More information are listed in `ls1043`_. + +Boot Sequence +============= + + +Bootrom --> TF-A BL1 --> TF-A BL2 --> TF-A BL1 --> TF-A BL31 +--> BL32(Tee OS) --> TF-A BL31 --> BL33(u-boot) --> Linux kernel + + +How to build +============ + +Build Procedure +--------------- + +- Prepare AARCH64 toolchain. + +- Build u-boot and OPTee firstly, and get binary images: u-boot.bin and tee.bin + +- Build TF-A for Nor boot + + Build bl1: + + .. code:: shell + + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 bl1 + + Build fip: + + .. code:: shell + + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 fip \ + BL33=u-boot.bin NEED_BL32=yes BL32=tee.bin SPD=opteed + +Deploy TF-A Images +----------------- + +- Deploy TF-A images on Nor flash Alt Bank. + + .. code:: shell + + => tftp 82000000 bl1.bin + => pro off all;era 64100000 +$filesize;cp.b 82000000 64100000 $filesize + + => tftp 82000000 fip.bin + => pro off all;era 64120000 +$filesize;cp.b 82000000 64120000 $filesize + + Then change to Alt bank and boot up TF-A: + + .. code:: shell + + => cpld reset altbank + + +.. _ls1043: https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/qoriq-layerscape-arm-processors/qoriq-layerscape-1043a-and-1023a-multicore-communications-processors:LS1043A?lang_cd=en diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index ff5bb1225..12e135f71 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -217,11 +217,37 @@ platform port to define additional platform porting constants in - **#define : BL2\_BASE** Defines the base address in secure RAM where BL1 loads the BL2 binary image. - Must be aligned on a page-size boundary. + Must be aligned on a page-size boundary. This constant is not applicable + when BL2_IN_XIP_MEM is set to '1'. - **#define : BL2\_LIMIT** Defines the maximum address in secure RAM that the BL2 image can occupy. + This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. + +- **#define : BL2\_RO\_BASE** + + Defines the base address in secure XIP memory where BL2 RO section originally + lives. Must be aligned on a page-size boundary. This constant is only needed + when BL2_IN_XIP_MEM is set to '1'. + +- **#define : BL2\_RO\_LIMIT** + + Defines the maximum address in secure XIP memory that BL2's actual content + (i.e. excluding any data section allocated at runtime) can occupy. This + constant is only needed when BL2_IN_XIP_MEM is set to '1'. + +- **#define : BL2\_RW\_BASE** + + Defines the base address in secure RAM where BL2's read-write data will live + at runtime. Must be aligned on a page-size boundary. This constant is only + needed when BL2_IN_XIP_MEM is set to '1'. + +- **#define : BL2\_RW\_LIMIT** + + Defines the maximum address in secure RAM that BL2's read-write data can + occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set + to '1'. - **#define : BL31\_BASE** diff --git a/docs/user-guide.rst b/docs/user-guide.rst index be2cf4009..f8bc4be50 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -246,6 +246,12 @@ Common build options - ``BL2_AT_EL3``: This is an optional build option that enables the use of BL2 at EL3 execution level. +- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place + (XIP) memory, like BL1. In these use-cases, it is necessary to initialize + the RW sections in RAM, while leaving the RO sections in place. This option + enable this use-case. For now, this option is only supported when BL2_AT_EL3 + is set to '1'. + - ``BL31``: This is an optional build option which specifies the path to BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not be built. |