diff options
Diffstat (limited to 'bl31/bl31.ld.S')
| -rw-r--r-- | bl31/bl31.ld.S | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 3327f3165..0639d8170 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -101,10 +101,31 @@ SECTIONS * The .bss section gets initialised to 0 at runtime. * Its base address must be 16-byte aligned. */ - .bss : ALIGN(16) { + .bss (NOLOAD) : ALIGN(16) { __BSS_START__ = .; *(.bss*) *(COMMON) +#if !USE_COHERENT_MEM + /* + * Bakery locks are stored in normal .bss memory + * + * Each lock's data is spread across multiple cache lines, one per CPU, + * but multiple locks can share the same cache line. + * The compiler will allocate enough memory for one CPU's bakery locks, + * the remaining cache lines are allocated by the linker script + */ + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __BAKERY_LOCK_START__ = .; + *(bakery_lock) + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __PERCPU_BAKERY_LOCK_SIZE__ = . - __BAKERY_LOCK_START__; + . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); + __BAKERY_LOCK_END__ = .; +#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE + ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, + "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); +#endif +#endif __BSS_END__ = .; } >RAM @@ -126,6 +147,12 @@ SECTIONS */ coherent_ram (NOLOAD) : ALIGN(4096) { __COHERENT_RAM_START__ = .; + /* + * Bakery locks are stored in coherent memory + * + * Each lock's data is contiguous and fully allocated by the compiler + */ + *(bakery_lock) *(tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; /* |