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-rw-r--r--bl2/aarch64/bl2_entrypoint.S23
1 files changed, 10 insertions, 13 deletions
diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S
index 09eadff2e..6fcd0405b 100644
--- a/bl2/aarch64/bl2_entrypoint.S
+++ b/bl2/aarch64/bl2_entrypoint.S
@@ -65,11 +65,13 @@ func bl2_entrypoint
msr vbar_el1, x0
/* ---------------------------------------------
- * Enable the instruction cache.
+ * Enable the instruction cache, stack pointer
+ * and data access alignment checks
* ---------------------------------------------
*/
+ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el1
- orr x0, x0, #SCTLR_I_BIT
+ orr x0, x0, x1
msr sctlr_el1, x0
isb
@@ -96,12 +98,15 @@ func bl2_entrypoint
bl zeromem16
/* --------------------------------------------
- * Give ourselves a small coherent stack to
- * ease the pain of initializing the MMU
+ * Allocate a stack whose memory will be marked
+ * as Normal-IS-WBWA when the MMU is enabled.
+ * There is no risk of reading stale stack
+ * memory after enabling the MMU as only the
+ * primary cpu is running at the moment.
* --------------------------------------------
*/
mrs x0, mpidr_el1
- bl platform_set_coherent_stack
+ bl platform_set_stack
/* ---------------------------------------------
* Perform early platform setup & platform
@@ -113,14 +118,6 @@ func bl2_entrypoint
bl bl2_plat_arch_setup
/* ---------------------------------------------
- * Give ourselves a stack allocated in Normal
- * -IS-WBWA memory
- * ---------------------------------------------
- */
- mrs x0, mpidr_el1
- bl platform_set_stack
-
- /* ---------------------------------------------
* Jump to main function.
* ---------------------------------------------
*/